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    • OL-DFFRAM

      Public
      Pre-hardened DFFRAM macros using DFFRAM
      Verilog
      6220Updated Sep 29, 2025Sep 29, 2025
    • TL-Verilog
      143700Updated Jul 12, 2025Jul 12, 2025
    • Primitives for GF180MCU provided by GlobalFoundries.
      Jupyter Notebook
      301251Updated Jul 6, 2025Jul 6, 2025
    • HTML
      10231Updated Apr 24, 2025Apr 24, 2025
    • chipignite_discover

      Public
      HTML
      7200Updated Mar 31, 2025Mar 31, 2025
    • nldiff

      Public
      Simple netlist comparison utility
      Python
      3601Updated Mar 6, 2025Mar 6, 2025
    • frigate_user_project

      Public
      Verilog
      6100Updated Feb 28, 2025Feb 28, 2025
    • Python
      6130Updated Feb 28, 2025Feb 28, 2025
    • 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      120510Updated Feb 28, 2025Feb 28, 2025
    • sky130_ef_ip__simple_por

      Public
      Simple PoR based on an RC filter
      Shell
      4100Updated Feb 26, 2025Feb 26, 2025
    • 12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
      Verilog
      6200Updated Feb 26, 2025Feb 26, 2025
    • 8-bit resistor ladder DAC with 3.3V output range
      MATLAB
      6100Updated Feb 26, 2025Feb 26, 2025
    • Repository to store metric results for OpenLane 2.0.0+
      4100Updated Feb 26, 2025Feb 26, 2025
    • caravel

      Public
      Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
      Verilog
      98370965Updated Feb 26, 2025Feb 26, 2025
    • Step-specific Unit Tests for OpenLane 2.0.0+
      Verilog
      6100Updated Feb 26, 2025Feb 26, 2025
    • EF_AES

      Public
      Verilog
      6111Updated Feb 26, 2025Feb 26, 2025
    • Verilog
      61031Updated Feb 26, 2025Feb 26, 2025
    • Verilog
      13600Updated Feb 26, 2025Feb 26, 2025
    • The analog signal processing and timing frontend subsystems for the Frigate harness chip
      Verilog
      4111Updated Feb 26, 2025Feb 26, 2025
    • Verilog
      6610Updated Feb 25, 2025Feb 25, 2025
    • Python
      3544407Updated Feb 25, 2025Feb 25, 2025
    • caravel_user_project

      Public template
      Verilog
      3682258522Updated Feb 25, 2025Feb 25, 2025
    • Analog 3.3V sample and hold circuit, with buffered output
      Tcl
      5000Updated Feb 25, 2025Feb 25, 2025
    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      91570Updated Feb 24, 2025Feb 24, 2025
    • Verilog
      5671Updated Feb 24, 2025Feb 24, 2025
    • sky130_ef_ip__template

      Public template
      A template repository for analog designs to ensure consistency and interoperability between IP blocks.
      4100Updated Feb 24, 2025Feb 24, 2025
    • Verilog
      4580Updated Feb 23, 2025Feb 23, 2025
    • EF_SHA256

      Public
      Verilog
      4121Updated Feb 23, 2025Feb 23, 2025
    • C
      7335Updated Feb 23, 2025Feb 23, 2025
    • Continuous Integration Designs for OpenLane 2.0.0 or higher
      Verilog
      10200Updated Feb 23, 2025Feb 23, 2025