Adding check for I_DELAY data output

Author: behzadmehmood

design_edit/Tests/I_DELAY_to_I_BUF/I_DELAY_to_I_BUF.ys

@@ -0,0 +1,25 @@
+ 
+# Yosys synthesis script for ${TOP_MODULE}
+# Read source files
+read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+verilog_defines 
+read_verilog ./rtl/I_DELAY_to_I_BUF.v
+
+# Technology mapping
+hierarchy -auto-top
+
+
+
+#plugin -i synth-rs
+#
+#synth_rs -tech genesis3 -de -goal mixed   -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528  -fsm_encoding onehot   -de_max_threads -1   
+#write_rtlil design.rtlil
+#write_verilog -noexpr -nodec -v ./tmp/I_DELAY_to_I_BUF.v
+#write_blif -param ./tmp/I_DELAY_to_I_BUF.eblif
+plugin -i design-edit
+design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_DELAY_to_I_BUF.v ./tmp//wrapper_I_DELAY_to_I_BUF.eblif
+
+write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_DELAY_to_I_BUF.v
+write_blif -param ./tmp/fabric_I_DELAY_to_I_BUF.eblif
+
+  

design_edit/Tests/I_DELAY_to_I_BUF/pin_constraints.pin

@@ -0,0 +1,13 @@
+set_pin_loc clkGHz HP_1_CC_18_9P
+
+set_pin_loc reset HP_1_0_0P
+
+set_pin_loc enable_n HP_1_2_1P
+
+set_pin_loc data_i HP_1_4_2P
+
+set_pin_loc bitslip_ctrl_n HP_1_6_3P
+
+set_pin_loc data_o HP_1_8_4P
+
+set_pin_loc ready HP_1_28_14P