From 5a39e1a1baddebd83075ad0136cd34ff8ed4b18a Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 2 Oct 2024 13:47:05 +0500 Subject: [PATCH 1/7] Removing O_FAB primitives and updating respected connections --- design_edit/src/rs_design_edit.cc | 61 +++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 07fb1a9c4..9a49d7d81 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -80,6 +80,7 @@ struct DesignEditRapidSilicon : public ScriptPass { } std::vector remove_prims; + std::vector remove_fab_prims; // TODO : change to unoredred set later std::vector remove_non_prims; std::vector remove_wrapper_cells; std::unordered_set wires_interface; @@ -94,6 +95,7 @@ struct DesignEditRapidSilicon : public ScriptPass { std::map wrapper_conns; std::map> io_prim_conn, intf_prim_conn; std::map inout_conn_map; + std::map ofab_sig_map; pool prim_out_bits; pool unused_prim_outs; pool used_bits; @@ -503,6 +505,63 @@ struct DesignEditRapidSilicon : public ScriptPass { } } + void remove_io_fab_prim(Module *mod) + { + for(auto cell : mod->cells()) + { + if (cell->type == RTLIL::escape_id("O_FAB")) + { + SigBit in_bit, out_bit; + for (auto &conn : cell->connections()) + { + IdString portName = conn.first; + if (cell->input(portName)) + { + in_bit = conn.second; + } else { + out_bit = conn.second; + } + } + if (in_bit.wire != nullptr) + { + remove_fab_prims.push_back(cell); + ofab_sig_map.insert(std::make_pair(in_bit, out_bit)); + } + } + } + + delete_cells(mod, remove_fab_prims); + + for (auto cell : mod->cells()) + { + if (cell->type == RTLIL::escape_id("O_FAB") || + cell->type == RTLIL::escape_id("I_FAB")) continue; + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + bool unset_port = true; + RTLIL::SigSpec sigspec; + for (SigBit bit : conn.second) + { + if (ofab_sig_map.count(bit) > 0) + { + if (unset_port) + { + cell->unsetPort(portName); + unset_port = false; + } + sigspec.append(ofab_sig_map[bit]); + } else { + sigspec.append(bit); + } + } + if (!unset_port) cell->setPort(portName, sigspec); + } + } + + std::cout << "O_FABS REMOVED" << std::endl; + } + void handle_dangling_outs(Module *module) { for(auto cell : module->cells()) @@ -1462,6 +1521,8 @@ struct DesignEditRapidSilicon : public ScriptPass { } } + remove_io_fab_prim(original_mod); + start = high_resolution_clock::now(); log("Gathering Wires Data\n"); if (supported_tech) From fbf5a498ec560130e83a12eca0ea0a5b003cf69f Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 2 Oct 2024 14:11:37 +0500 Subject: [PATCH 2/7] Removing I_FABs --- design_edit/src/rs_design_edit.cc | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 9a49d7d81..4ba62f1fc 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -95,7 +95,7 @@ struct DesignEditRapidSilicon : public ScriptPass { std::map wrapper_conns; std::map> io_prim_conn, intf_prim_conn; std::map inout_conn_map; - std::map ofab_sig_map; + std::map fab_sig_map; pool prim_out_bits; pool unused_prim_outs; pool used_bits; @@ -525,7 +525,27 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - ofab_sig_map.insert(std::make_pair(in_bit, out_bit)); + fab_sig_map.insert(std::make_pair(in_bit, out_bit)); + } + } + + if (cell->type == RTLIL::escape_id("I_FAB")) + { + SigBit in_bit, out_bit; + for (auto &conn : cell->connections()) + { + IdString portName = conn.first; + if (cell->input(portName)) + { + in_bit = conn.second; + } else { + out_bit = conn.second; + } + } + if (in_bit.wire != nullptr) + { + remove_fab_prims.push_back(cell); + fab_sig_map.insert(std::make_pair(out_bit, in_bit)); } } } @@ -543,14 +563,14 @@ struct DesignEditRapidSilicon : public ScriptPass { RTLIL::SigSpec sigspec; for (SigBit bit : conn.second) { - if (ofab_sig_map.count(bit) > 0) + if (fab_sig_map.count(bit) > 0) { if (unset_port) { cell->unsetPort(portName); unset_port = false; } - sigspec.append(ofab_sig_map[bit]); + sigspec.append(fab_sig_map[bit]); } else { sigspec.append(bit); } @@ -558,8 +578,6 @@ struct DesignEditRapidSilicon : public ScriptPass { if (!unset_port) cell->setPort(portName, sigspec); } } - - std::cout << "O_FABS REMOVED" << std::endl; } void handle_dangling_outs(Module *module) From 82506b5d52e43f7c6e9fc4b84e8e9882e148c045 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 2 Oct 2024 14:23:35 +0500 Subject: [PATCH 3/7] Disabling checks dependent on I_FAB/O_FAB primitives --- design_edit/src/rs_design_edit.cc | 108 ++---------------------------- design_edit/src/rs_design_edit.h | 2 - 2 files changed, 5 insertions(+), 105 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 4ba62f1fc..d79022472 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -99,9 +99,9 @@ struct DesignEditRapidSilicon : public ScriptPass { pool prim_out_bits; pool unused_prim_outs; pool used_bits; - pool orig_ins, orig_outs, fab_outs, ofab_outs, ifab_ins; - pool i_buf_ins, i_buf_outs, o_buf_outs, i_buf_ctrls, o_buf_ctrls; - pool clk_buf_ins, dly_in_ctrls, dly_out_ctrls; + pool orig_ins, orig_outs, fab_outs; + pool i_buf_ins, i_buf_outs, o_buf_outs; + pool clk_buf_ins; pool fclk_buf_ins; pool diff; @@ -1134,54 +1134,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - void check_dly_cntrls() - { - netlist_checker << "\nChecking I_DELAY/O_DELAY control signals\n"; - netlist_checker << "================================================================\n"; - for (auto &bit : dly_in_ctrls) - { - if (!ofab_outs.count(bit)) - { - netlist_checker << log_signal(bit) << " is an input control signal and must be connected to O_FAB\n"; - netlist_error = true; - } - } - - for (auto &bit : dly_out_ctrls) - { - if (!ifab_ins.count(bit)) - { - netlist_checker << log_signal(bit) << " is an output control signal and must be connected to I_FAB\n"; - netlist_error = true; - } - } - netlist_checker << "================================================================\n"; - } - - void check_buf_cntrls() - { - netlist_checker << "\nChecking Buffer control signals\n"; - netlist_checker << "================================================================\n"; - for (auto &bit : i_buf_ctrls) - { - if (!ofab_outs.count(bit)) - { - netlist_checker << log_signal(bit) << " is an input control signal and must be connected to O_FAB\n"; - netlist_error = true; - } - } - - for (auto &bit : o_buf_ctrls) - { - if (!ofab_outs.count(bit)) - { - netlist_checker << log_signal(bit) << " is an input control signal and must be connected to O_FAB\n"; - netlist_error = true; - } - } - netlist_checker << "================================================================\n"; - } - void check_fclkbuf_conns() { netlist_checker << "\nChecking FCLK_BUF connections\n"; @@ -1564,8 +1516,8 @@ struct DesignEditRapidSilicon : public ScriptPass { { if (bit.wire != nullptr) { - if (cell->input(portName) ) - (remove_backslashes(portName.str()) != "EN") ? i_buf_ins.insert(bit) : i_buf_ctrls.insert(bit); + if (cell->input(portName) && + (remove_backslashes(portName.str()) != "EN")) i_buf_ins.insert(bit); if (cell->output(portName)) i_buf_outs.insert(bit); } } @@ -1595,7 +1547,6 @@ struct DesignEditRapidSilicon : public ScriptPass { if (bit.wire != nullptr) { if(cell->output(portName)) o_buf_outs.insert(bit); - if (remove_backslashes(portName.str()) == "T") o_buf_ctrls.insert(bit); } } } @@ -1634,25 +1585,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } } - } else if (cell->type == RTLIL::escape_id("I_DELAY") || - cell->type == RTLIL::escape_id("O_DELAY")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - if(dly_controls.find(remove_backslashes(portName.str())) != dly_controls.end()) - { - if(cell->input(portName)) - { - for (SigBit bit : conn.second) - if (bit.wire != nullptr) dly_in_ctrls.insert(bit); - } else if(cell->output(portName)) - { - for (SigBit bit : conn.second) - if (bit.wire != nullptr) dly_out_ctrls.insert(bit); - } - } - } } for (auto conn : cell->connections()) { @@ -1717,34 +1649,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } } else { - if (cell->type == RTLIL::escape_id("I_FAB")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - if(remove_backslashes(portName.str()) == "I") - { - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) ifab_ins.insert(bit); - } - } - } - } - if (cell->type == RTLIL::escape_id("O_FAB")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - if(remove_backslashes(portName.str()) == "O") - { - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) ofab_outs.insert(bit); - } - } - } - } for (auto conn : cell->connections()) { IdString portName = conn.first; RTLIL::SigSpec actual = conn.second; @@ -1768,8 +1672,6 @@ struct DesignEditRapidSilicon : public ScriptPass { check_buf_conns(); check_clkbuf_conns(); - check_buf_cntrls(); - check_dly_cntrls(); end = high_resolution_clock::now(); elapsed_time (start, end); diff --git a/design_edit/src/rs_design_edit.h b/design_edit/src/rs_design_edit.h index 009e85633..56e42e2bf 100644 --- a/design_edit/src/rs_design_edit.h +++ b/design_edit/src/rs_design_edit.h @@ -85,8 +85,6 @@ std::string tech; std::stringstream netlist_checker; bool netlist_error = false; int feedback_clocks = 0; -std::unordered_set dly_controls = - {"DLY_LOAD", "DLY_ADJ", "DLY_INCDEC", "DLY_TAP_VALUE"}; std::vector tokenizeString(const std::string &input); void processSdcFile(std::istream &input); From b32210a4bac661a9d7bd4fbb6295157c0fef2f9b Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Thu, 3 Oct 2024 13:28:56 +0500 Subject: [PATCH 4/7] Handling signals connected to multiple O_FABs --- design_edit/src/rs_design_edit.cc | 120 ++++++++++++++++++++++++++++-- 1 file changed, 115 insertions(+), 5 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index d79022472..93f65badd 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -95,7 +95,8 @@ struct DesignEditRapidSilicon : public ScriptPass { std::map wrapper_conns; std::map> io_prim_conn, intf_prim_conn; std::map inout_conn_map; - std::map fab_sig_map; + std::map ifab_sig_map; + std::map> ofab_sig_map, ofab_conns; pool prim_out_bits; pool unused_prim_outs; pool used_bits; @@ -525,7 +526,15 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - fab_sig_map.insert(std::make_pair(in_bit, out_bit)); + auto it = ofab_sig_map.find(in_bit); + + if (it != ofab_sig_map.end()) { + it->second.push_back(out_bit); + } else { + std::vector out_bits; + out_bits.push_back(out_bit); + ofab_sig_map.insert({in_bit, out_bits}); + } } } @@ -545,7 +554,7 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - fab_sig_map.insert(std::make_pair(out_bit, in_bit)); + ifab_sig_map.insert(std::make_pair(out_bit, in_bit)); } } } @@ -563,14 +572,48 @@ struct DesignEditRapidSilicon : public ScriptPass { RTLIL::SigSpec sigspec; for (SigBit bit : conn.second) { - if (fab_sig_map.count(bit) > 0) + if (ifab_sig_map.count(bit) > 0) { if (unset_port) { cell->unsetPort(portName); unset_port = false; } - sigspec.append(fab_sig_map[bit]); + sigspec.append(ifab_sig_map[bit]); + } else { + sigspec.append(bit); + } + } + if (!unset_port) cell->setPort(portName, sigspec); + } + + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + bool unset_port = true; + RTLIL::SigSpec sigspec; + for (SigBit bit : conn.second) + { + if (ofab_sig_map.count(bit) > 0) + { + const std::vector outbits = ofab_sig_map[bit]; + if(outbits.size() < 1) sigspec.append(bit); + if(outbits.size() == 1) + { + if (unset_port) + { + cell->unsetPort(portName); + unset_port = false; + } + sigspec.append(outbits[0]); + } else if (outbits.size() > 1) + { + sigspec.append(bit); + if (ofab_conns.find(bit) == ofab_conns.end()) + { + ofab_conns.insert({bit, outbits}); + } + } } else { sigspec.append(bit); } @@ -578,6 +621,71 @@ struct DesignEditRapidSilicon : public ScriptPass { if (!unset_port) cell->setPort(portName, sigspec); } } + + for (const auto& ofab_conn : ofab_conns) + { + const std::vector out_bits = ofab_conn.second; + if(out_bits.size() <= 1) continue; + for(const auto& out_bit : out_bits) + { + RTLIL::SigSig new_conn; + new_conn.first = out_bit; + new_conn.second = ofab_conn.first; + mod->connect(new_conn); + } + } + } + + void rem_extra_assigns(Module *module) + { + pool assign_bits; + std::unordered_set del_wires; + for(auto cell : module->cells()) + { + for (auto &conn : cell->connections()) + { + IdString portName = conn.first; + if (cell->input(portName)) + { + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) assign_bits.insert(bit); + } + } + } + } + + for(auto &conn : module->connections()) + { + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) assign_bits.insert(bit); + } + } + + for(auto &conn : module->connections()) + { + std::vector conn_lhs = conn.first.to_sigbit_vector(); + if (conn_lhs.size() != 1) continue; + for (SigBit bit : conn.first) + { + if (bit.wire != nullptr) + { + if(!assign_bits.count(bit) && !bit.wire->port_output) + { + connections_to_remove.insert(conn); + del_wires.insert(bit.wire); + } + } + } + } + + remove_extra_conns(module); + connections_to_remove.clear(); + for (auto wire : del_wires) { + module->remove({wire}); + } + del_wires.clear(); } void handle_dangling_outs(Module *module) @@ -1921,6 +2029,8 @@ struct DesignEditRapidSilicon : public ScriptPass { end = high_resolution_clock::now(); elapsed_time (start, end); + rem_extra_assigns(original_mod); + reportInfoFabricClocks(original_mod); delete_wires(interface_mod, interface_intermediate_wires); From 96cb8bfc2343fa84101d97b7c784a717a9faca80 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Thu, 3 Oct 2024 16:21:48 +0500 Subject: [PATCH 5/7] Handling directly connected I_FAB and O_FAB primitives --- design_edit/src/rs_design_edit.cc | 80 ++++++++++++++++++------------- 1 file changed, 46 insertions(+), 34 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 93f65badd..6bbba5b70 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -510,7 +510,7 @@ struct DesignEditRapidSilicon : public ScriptPass { { for(auto cell : mod->cells()) { - if (cell->type == RTLIL::escape_id("O_FAB")) + if (cell->type == RTLIL::escape_id("I_FAB")) { SigBit in_bit, out_bit; for (auto &conn : cell->connections()) @@ -526,19 +526,14 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - auto it = ofab_sig_map.find(in_bit); - - if (it != ofab_sig_map.end()) { - it->second.push_back(out_bit); - } else { - std::vector out_bits; - out_bits.push_back(out_bit); - ofab_sig_map.insert({in_bit, out_bits}); - } + ifab_sig_map.insert(std::make_pair(out_bit, in_bit)); } } + } - if (cell->type == RTLIL::escape_id("I_FAB")) + for(auto cell : mod->cells()) + { + if (cell->type == RTLIL::escape_id("O_FAB")) { SigBit in_bit, out_bit; for (auto &conn : cell->connections()) @@ -554,7 +549,23 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - ifab_sig_map.insert(std::make_pair(out_bit, in_bit)); + if(ifab_sig_map.count(in_bit)) + { + RTLIL::SigSig new_conn; + new_conn.first = out_bit; + new_conn.second = ifab_sig_map[in_bit]; + mod->connect(new_conn); + } else { + auto it = ofab_sig_map.find(in_bit); + + if (it != ofab_sig_map.end()) { + it->second.push_back(out_bit); + } else { + std::vector out_bits; + out_bits.push_back(out_bit); + ofab_sig_map.insert({in_bit, out_bits}); + } + } } } } @@ -565,27 +576,6 @@ struct DesignEditRapidSilicon : public ScriptPass { { if (cell->type == RTLIL::escape_id("O_FAB") || cell->type == RTLIL::escape_id("I_FAB")) continue; - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - bool unset_port = true; - RTLIL::SigSpec sigspec; - for (SigBit bit : conn.second) - { - if (ifab_sig_map.count(bit) > 0) - { - if (unset_port) - { - cell->unsetPort(portName); - unset_port = false; - } - sigspec.append(ifab_sig_map[bit]); - } else { - sigspec.append(bit); - } - } - if (!unset_port) cell->setPort(portName, sigspec); - } for (auto conn : cell->connections()) { @@ -594,7 +584,7 @@ struct DesignEditRapidSilicon : public ScriptPass { RTLIL::SigSpec sigspec; for (SigBit bit : conn.second) { - if (ofab_sig_map.count(bit) > 0) + if (ofab_sig_map.count(bit)) { const std::vector outbits = ofab_sig_map[bit]; if(outbits.size() < 1) sigspec.append(bit); @@ -620,6 +610,28 @@ struct DesignEditRapidSilicon : public ScriptPass { } if (!unset_port) cell->setPort(portName, sigspec); } + + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + bool unset_port = true; + RTLIL::SigSpec sigspec; + for (SigBit bit : conn.second) + { + if (ifab_sig_map.count(bit)) + { + if (unset_port) + { + cell->unsetPort(portName); + unset_port = false; + } + sigspec.append(ifab_sig_map[bit]); + } else { + sigspec.append(bit); + } + } + if (!unset_port) cell->setPort(portName, sigspec); + } } for (const auto& ofab_conn : ofab_conns) From e7baf7cd18595bdbf901100aac257a9e5182f05f Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Sat, 5 Oct 2024 07:17:30 +0000 Subject: [PATCH 6/7] Incremented patch version --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index df700bb17..87cbdf0e5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -17,7 +17,7 @@ set(VERSION_MINOR 0) -set(VERSION_PATCH 376) +set(VERSION_PATCH 377) From 56a05b555c284439f1ba8c018930680485eb1243 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Sat, 5 Oct 2024 12:17:55 +0500 Subject: [PATCH 7/7] Handling I_FAB/O_FAB connecting two IO primitives --- design_edit/src/rs_design_edit.cc | 46 +++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index fa8a2350a..6b6037319 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -100,7 +100,7 @@ struct DesignEditRapidSilicon : public ScriptPass { pool prim_out_bits; pool unused_prim_outs; pool used_bits; - pool orig_ins, orig_outs, fab_outs; + pool orig_ins, orig_outs, fab_outs, fab_ins; pool i_buf_ins, i_buf_outs, o_buf_outs; pool clk_buf_ins; pool fclk_buf_ins; @@ -526,7 +526,15 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - ifab_sig_map.insert(std::make_pair(out_bit, in_bit)); + if (fab_ins.count(in_bit) && fab_outs.count(out_bit)) + { + RTLIL::SigSig new_conn; + new_conn.first = out_bit; + new_conn.second = in_bit; + mod->connect(new_conn); + } else { + ifab_sig_map.insert(std::make_pair(out_bit, in_bit)); + } } } } @@ -549,7 +557,13 @@ struct DesignEditRapidSilicon : public ScriptPass { if (in_bit.wire != nullptr) { remove_fab_prims.push_back(cell); - if(ifab_sig_map.count(in_bit)) + if (fab_ins.count(in_bit) && fab_outs.count(out_bit)) + { + RTLIL::SigSig new_conn; + new_conn.first = out_bit; + new_conn.second = in_bit; + mod->connect(new_conn); + } else if(ifab_sig_map.count(in_bit)) { RTLIL::SigSig new_conn; new_conn.first = out_bit; @@ -1239,17 +1253,24 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - void get_fabric_outputs(Module* mod) + void get_fabric_ios(Module* mod) { for (auto wire : mod->wires()) { bool is_output = wire->port_output ? true :false; - if (!is_output) continue; + bool is_input = wire->port_input ? true :false; + if (!is_output && !is_input) continue; - RTLIL::SigSpec wire_ = wire; - for (auto bit : wire_) + if (is_input) + { + RTLIL::SigSpec wire_ = wire; + for (auto bit : wire_) fab_ins.insert(bit); + } + + if (is_output) { - if(!orig_outs.count(bit)) fab_outs.insert(bit); + RTLIL::SigSpec wire_ = wire; + for (auto bit : wire_) fab_outs.insert(bit); } } } @@ -1611,8 +1632,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - remove_io_fab_prim(original_mod); - start = high_resolution_clock::now(); log("Gathering Wires Data\n"); if (supported_tech) @@ -1938,8 +1957,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - get_fabric_outputs(original_mod); - check_fclkbuf_conns(); delete_wires(original_mod, wires_interface); delete_wires(original_mod, del_ins); delete_wires(original_mod, del_outs); @@ -1948,6 +1965,11 @@ struct DesignEditRapidSilicon : public ScriptPass { fixup_mod_ports(original_mod); + get_fabric_ios(original_mod); + check_fclkbuf_conns(); + + remove_io_fab_prim(original_mod); + start = high_resolution_clock::now(); log("Deleting non-primitive cells and upgrading wires to ports in interface module\n"); for (auto cell : interface_mod->cells()) {