diff --git a/CMakeLists.txt b/CMakeLists.txt
index b8a716ee9..5ec54cf0d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -17,7 +17,7 @@ set(VERSION_MINOR 0)
 
 
 
-set(VERSION_PATCH 380)
+set(VERSION_PATCH 382)
 
 
 
diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc
index d0cc5b223..cb0509b14 100644
--- a/design_edit/src/rs_design_edit.cc
+++ b/design_edit/src/rs_design_edit.cc
@@ -1000,8 +1000,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
               if (std::find(io_prim_wires.begin(), io_prim_wires.end(), bit.wire->name.str()) !=
                   io_prim_wires.end()) {
                 if (cell->input(portName) &&
-                  portName.str() != "\\CLK_IN" &&
-                  portName.str() != "\\C" &&
+                  portName != RTLIL::escape_id("CLK_IN") &&
+                  portName != RTLIL::escape_id("C") &&
+                  portName != RTLIL::escape_id("PLL_CLK") &&
                   (is_out_prim || is_intf_prim)) {
                   if (unset_port)
                   {
@@ -1574,8 +1575,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
                 process_wire(cell, portName, wire);
                 if (is_out_prim || is_intf_prim) {
                   if (cell->input(portName)) {
-                    if (portName.str() != "\\CLK_IN" &&
-                      portName.str() != "\\C")
+                    if (portName != RTLIL::escape_id("CLK_IN") &&
+                      portName != RTLIL::escape_id("C") &&
+                      portName != RTLIL::escape_id("PLL_CLK"))
                       out_prim_ins.insert(wire->name.str());
                   }
                 }
@@ -1596,8 +1598,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
                   process_wire(cell, portName, wire);
                   if (is_out_prim || is_intf_prim) {
                     if (cell->input(portName)) {
-                      if (portName.str() != "\\CLK_IN" &&
-                        portName.str() != "\\C")
+                      if (portName != RTLIL::escape_id("CLK_IN") &&
+                      portName != RTLIL::escape_id("C") &&
+                      portName != RTLIL::escape_id("PLL_CLK"))
                         out_prim_ins.insert(wire->name.str());
                     }
                   }