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[app/redpitaya/double_iq_pid_vco] bif file is not generated when make design #1

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mer0m opened this issue May 14, 2020 · 2 comments
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@mer0m
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mer0m commented May 14, 2020

During disign make:
bootgen -w -image tmp/double_iq_pid_vco.bif -arch zynq -process_bitstream bin fails due to bif file not created.

@trabucayre
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Hi,
I've just tried to generate this design with a fresh clean repository and I'm unable to reproduce your issue.
Could you provide your vivado version and paste the end of the build?
Thanks

@mer0m
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mer0m commented May 15, 2020

At the end of a make -j4:

bootgen -w -image tmp/double_iq_pid_vco.bif -arch zynq -process_bitstream bin


****** Xilinx Bootgen v2019.2
  **** Build date : Nov  6 2019-22:01:16
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

[ERROR]  : Can't read file - tmp/double_iq_pid_vco.bif
make: *** [/home/bma/git/github/oscimpDigital/fpga_ip/vivado.mk:39: tmp/double_iq_pid_vco.runs/impl_1/double_iq_pid_vco_wrapper.bit.bin] Error 1

But all works after a make.

@mer0m mer0m closed this as completed May 15, 2020
@mer0m mer0m pinned this issue May 15, 2020
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