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i915_dp.c
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i915_dp.c
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#include "i915_controller.h"
#include "i915_debug.h"
#include "i915_gmbus.h"
#include "i915_ddi.h"
#include "i915_dp.h"
#include "i915_hdmi.h"
#include "i915_reg.h"
#include <Uefi.h>
#include <Library/UefiBootServicesTableLib.h>
/* Cedartrail */
#define PP_ON_DELAYS 0x61208 /* Cedartrail */
#define PANEL_PORT_SELECT_MASK (3 << 30)
#define PANEL_PORT_SELECT_LVDS (0 << 30)
#define PANEL_PORT_SELECT_EDP (1 << 30)
#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
#define PANEL_POWER_UP_DELAY_SHIFT 16
#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
#define PANEL_LIGHT_ON_DELAY_SHIFT 0
#define PP_OFF_DELAYS 0x6120c /* Cedartrail */
#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
#define PANEL_POWER_DOWN_DELAY_SHIFT 16
#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
//#define PP_DIVISOR 0x61210 /* Cedartrail */
#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
#define PP_REFERENCE_DIVIDER_SHIFT 8
#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
void memcpy(void *dest, void *src, UINTN n)
{
// Typecast src and dest addresses to (char *)
char *csrc = (char *)src;
char *cdest = (char *)dest;
// Copy contents of src[] to dest[]
for (int i = 0; i < n; i++)
cdest[i] = csrc[i];
}
/*
* ..and if you can't take the strict
* types, you can specify one yourself.
*
* Or not use min/max/clamp at all, of course.
*/
#define min_t(type, x, y) ( \
{ \
type __min1 = (x); \
type __min2 = (y); \
__min1 < __min2 ? __min1 : __min2; \
})
#define max_t(type, x, y) ( \
{ \
type __max1 = (x); \
type __max2 = (y); \
__max1 > __max2 ? __max1 : __max2; \
})
static int max(int in1, int in2)
{
return max_t(int, in1, in2);
}
/**
* clamp_t - return a value clamped to a given range using a given type
* @type: the type of variable to use
* @val: current value
* @lo: minimum allowable value
* @hi: maximum allowable value
*
* This macro does no typechecking and uses temporary variables of type
* 'type' to make all the comparisons.
*/
#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi)
EFI_STATUS ReadEDIDDP(EDID *result, i915_CONTROLLER *controller, UINT8 pin)
{
UINT32 *p = (UINT32 *)result;
edp_panel_vdd_on(controller->intel_dp);
PRINT_DEBUG(EFI_D_ERROR, "trying DP aux %d\n", pin);
// aux message header is 3-4 bytes: ctrl8 addr16 len8
// the data is big endian
// len is receive buffer size-1
// i2c init
UINT32 send_ctl =
(DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR | (3 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32));
/* Must try at least 3 times according to DP spec, WHICH WE DON'T CARE */
controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8),
((AUX_I2C_MOT | AUX_I2C_WRITE) << 28) | (0x50 << 8) |
0);
controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl);
UINT32 aux_status;
UINT32 counter = 0;
for (;;)
{
aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8));
if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY))
{
break;
}
counter += 1;
if (counter >= 1500)
{
PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout");
break;
}
gBS->Stall(10);
}
controller->write32(_DPA_AUX_CH_CTL + (pin << 8),
aux_status | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR);
// i2c send 1 byte
send_ctl =
(DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR | (5 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32));
controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8),
(AUX_I2C_WRITE << 28) | (0x50 << 8) | 0);
controller->write32(_DPA_AUX_CH_DATA2 + (pin << 8), 0);
controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl);
counter = 0;
for (;;)
{
aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8));
if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY))
{
break;
}
counter += 1;
if (counter >= 1500)
{
PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout");
break;
}
gBS->Stall(10);
}
controller->write32(_DPA_AUX_CH_CTL + (pin << 8),
aux_status | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR);
if (aux_status &
(DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR))
{
return EFI_NOT_FOUND;
}
// i2c read 1 byte * 128
PRINT_DEBUG(EFI_D_ERROR, "reading DP aux %d\n", pin);
// aux message header is 3-4 bytes: ctrl8 addr16 len8
// the data is big endian
// len is receive buffer size-1
// i2c init
send_ctl =
(DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR | (3 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32));
/* Must try at least 3 times according to DP spec, WHICH WE DON'T CARE */
controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8),
((AUX_I2C_MOT | AUX_I2C_READ) << 28) | (0x50 << 8) | 0);
controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl);
counter = 0;
for (;;)
{
aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8));
if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY))
{
break;
}
counter += 1;
if (counter >= 1500)
{
PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout");
break;
}
gBS->Stall(10);
}
controller->write32(_DPA_AUX_CH_CTL + (pin << 8),
aux_status | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR);
UINT32 i = 0;
for (i = 0; i < 128; i++)
{
send_ctl = (DP_AUX_CH_CTL_SEND_BUSY | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(4 << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32));
controller->write32(_DPA_AUX_CH_DATA1 + (pin << 8),
(AUX_I2C_READ << 28) | (0x50 << 8) | 0);
controller->write32(_DPA_AUX_CH_CTL + (pin << 8), send_ctl);
counter = 0;
for (;;)
{
aux_status = controller->read32(_DPA_AUX_CH_CTL + (pin << 8));
if (!(aux_status & DP_AUX_CH_CTL_SEND_BUSY))
{
break;
}
counter += 1;
if (counter >= 1500)
{
PRINT_DEBUG(EFI_D_ERROR, "DP AUX channel timeout");
break;
}
gBS->Stall(10);
}
controller->write32(_DPA_AUX_CH_CTL + (pin << 8),
aux_status | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR);
UINT32 word = controller->read32(_DPA_AUX_CH_DATA1 + (pin << 8));
((UINT8 *)p)[i] = (word >> 16) & 0xff;
}
for (UINT32 i = 0; i < 16; i++)
{
for (UINT32 j = 0; j < 8; j++)
{
DebugPrint(EFI_D_ERROR, "%02x ", ((UINT8 *)(p))[i * 8 + j]);
}
DebugPrint(EFI_D_ERROR, "\n");
}
if (i >= 128 && *(UINT64 *)result->magic == 0x00FFFFFFFFFFFF00uLL)
{
controller->OutputPath.AuxCh = pin;
return EFI_SUCCESS;
}
return EFI_NOT_FOUND;
}
static int cnp_rawclk(i915_CONTROLLER *controller)
{
int divider, fraction;
if (controller->read32(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY)
{
/* 24 MHz */
divider = 24000;
fraction = 0;
}
else
{
/* 19.2 MHz */
divider = 19000;
fraction = 200;
}
/* rawclk = CNP_RAWCLK_DIV(divider / 1000);
if (fraction) {
int numerator = 1;
rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
fraction) - 1);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
rawclk |= ICP_RAWCLK_NUM(numerator);
}
controller->write32(PCH_RAWCLK_FREQ, rawclk); */
return divider + fraction;
}
// //WE CAN USE THIS TO GET BETTER DELAY VALUES
// // static void
// // intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
// // {
// // //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
// // //struct edp_power_seq cur, vbt, spec;
// // //*final = &intel_dp->pps_delays;
// // //lockdep_assert_held(&dev_priv->pps_mutex);
// // /* already initialized? */
// // if (final->t11_t12 != 0)
// // return;
// // intel_pps_readout_hw_state(intel_dp, &cur);
// // intel_pps_dump_state("cur", &cur);
// // vbt = dev_priv->vbt.edp.pps;
// // /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
// // * of 500ms appears to be too short. Ocassionally the panel
// // * just fails to power back on. Increasing the delay to 800ms
// // * seems sufficient to avoid this problem.
// // */
// // if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
// // vbt.t11_t12 = max_t(UINT16, vbt.t11_t12, 1300 * 10);
// // drm_dbg_kms(&dev_priv->drm,
// // "Increasing T12 panel delay as per the quirk to %d\n",
// // vbt.t11_t12);
// // }
// // /* T11_T12 delay is special and actually in units of 100ms, but zero
// // * based in the hw (so we need to add 100 ms). But the sw vbt
// // * table multiplies it with 1000 to make it in units of 100usec,
// // * too. */
// // vbt.t11_t12 += 100 * 10;
// // /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
// // * our hw here, which are all in 100usec. */
// // spec.t1_t3 = 210 * 10;
// // spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
// // spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
// // spec.t10 = 500 * 10;
// // /* This one is special and actually in units of 100ms, but zero
// // * based in the hw (so we need to add 100 ms). But the sw vbt
// // * table multiplies it with 1000 to make it in units of 100usec,
// // * too. */
// // spec.t11_t12 = (510 + 100) * 10;
// // intel_pps_dump_state("vbt", &vbt);
// // /* Use the max of the register settings and vbt. If both are
// // * unset, fall back to the spec limits. */
// // #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? spec.field : max(cur.field, vbt.field))
// // assign_final(t1_t3);
// // assign_final(t8);
// // assign_final(t9);
// // assign_final(t10);
// // assign_final(t11_t12);
// // #undef assign_final
// // #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
// // intel_dp->panel_power_up_delay = get_delay(t1_t3);
// // intel_dp->backlight_on_delay = get_delay(t8);
// // intel_dp->backlight_off_delay = get_delay(t9);
// // intel_dp->panel_power_down_delay = get_delay(t10);
// // intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
// // #undef get_delay
// // drm_dbg_kms(&dev_priv->drm,
// // "panel power up delay %d, power down delay %d, power cycle delay %d\n",
// // intel_dp->panel_power_up_delay,
// // intel_dp->panel_power_down_delay,
// // intel_dp->panel_power_cycle_delay);
// // drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
// // intel_dp->backlight_on_delay,
// // intel_dp->backlight_off_delay);
// // /*
// // * We override the HW backlight delays to 1 because we do manual waits
// // * on them. For T8, even BSpec recommends doing it. For T9, if we
// // * don't do this, we'll end up waiting for the backlight off delay
// // * twice: once when we do the manual sleep, and once when we disable
// // * the panel and wait for the PP_STATUS bit to become zero.
// // */
// // final->t8 = 1;
// // final->t9 = 1;
// // /*
// // * HW has only a 100msec granularity for t11_t12 so round it up
// // * accordingly.
// // */
// // final->t11_t12 = roundup(final->t11_t12, 100 * 10);
// // }
// static void
// intel_dp_init_panel_power_sequencer_registers(i915_CONTROLLER *controller)
// {
// //struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
// UINT32 pp_on, pp_off, port_sel = 0;
// //int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
// int div = cnp_rawclk(controller); //Varies by generation
// //struct pps_registers regs;
// //UINT32 port = controller->OutputPath.Port;
// //const struct edp_power_seq *seq = &intel_dp->pps_delays;
// // lockdep_assert_held(&dev_priv->pps_mutex);
// // intel_pps_get_registers(intel_dp, ®s);
// //units are 100us
// pp_on = (2100 << 15) |
// (500);
// pp_off = (5000 << 15) |
// (500);
// /* Haswell doesn't have any port selection bits for the panel
// * power sequencer any more. */
// /*
// if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
// port_sel = PANEL_PORT_SELECT_VLV(port);
// } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
// switch (port) {
// case PORT_A:
// port_sel = PANEL_PORT_SELECT_DPA;
// break;
// case PORT_C:
// port_sel = PANEL_PORT_SELECT_DPC;
// break;
// case PORT_D:
// port_sel = PANEL_PORT_SELECT_DPD;
// break;
// default:
// MISSING_CASE(port);
// break;
// }
// }
// */
// pp_on |= port_sel;
// controller->write32(PP_ON, pp_on);
// controller->write32(PP_OFF, pp_off);
// /*
// * Compute the divisor for the pp clock, simply match the Bspec formula.
// */
// //if (i915_mmio_reg_valid(PP_DIVISOR)) {
// controller->write32(PP_DIVISOR,
// (((100 * div) / 2 - 1) << 7) | 11);
// // controller->write32(PP_DIVISOR,
// // 0xffffffff);
// /* } else { USED FOR Gens where divisor is in cntrl var
// UINT32 pp_ctl;
// pp_ctl = controller->read32( regs.pp_ctrl);
// pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
// pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
// controller->write32(regs.pp_ctrl, pp_ctl);
// } */
// PRINT_DEBUG(EFI_D_ERROR,
// "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
// controller->read32(PP_ON),
// controller->read32(PP_OFF),
// controller->read32(PP_DIVISOR));
// }
struct pps_registers
{
UINT64 pp_ctrl;
UINT64 pp_stat;
UINT64 pp_on;
UINT64 pp_off;
UINT64 pp_div;
};
static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct pps_registers *regs)
{
//struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
// int pps_idx = 0;
gBS->SetMem(regs, sizeof(*regs), 0);
//memset(regs, 0, sizeof(*regs));
// if (IS_GEN9_LP(dev_priv))
// pps_idx = bxt_power_sequencer_idx(intel_dp);
// else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
// pps_idx = vlv_power_sequencer_pipe(intel_dp);
regs->pp_ctrl = PP_CONTROL;
regs->pp_stat = PP_STATUS;
regs->pp_on = PP_ON_DELAYS;
regs->pp_off = PP_OFF_DELAYS;
regs->pp_div = PP_DIVISOR;
}
static u32 ironlake_get_pp_control(i915_CONTROLLER *controller)
{
//struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 control;
// lockdep_assert_held(&dev_priv->pps_mutex);
control = controller->read32(PP_CONTROL);
if ((control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)
{
control &= ~PANEL_UNLOCK_MASK;
control |= PANEL_UNLOCK_REGS;
}
return control;
}
static void
intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
{
// struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
struct pps_registers regs;
intel_pps_get_registers(intel_dp, ®s);
/* Workaround: Need to write PP_CONTROL with the unlock key as
* the very first thing. */
pp_ctl = ironlake_get_pp_control(intel_dp->controller);
pp_on = intel_dp->controller->read32(regs.pp_on);
pp_off = intel_dp->controller->read32(regs.pp_off);
// if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
// !HAS_PCH_ICP(dev_priv))
// {
intel_dp->controller->write32(regs.pp_ctrl, pp_ctl);
pp_div = intel_dp->controller->read32(regs.pp_div);
// }
/* Pull timing values out of registers */
seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
PANEL_POWER_UP_DELAY_SHIFT;
seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
PANEL_LIGHT_ON_DELAY_SHIFT;
seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
PANEL_LIGHT_OFF_DELAY_SHIFT;
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
// if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
// HAS_PCH_ICP(dev_priv))
// {
// seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
// BXT_POWER_CYCLE_DELAY_SHIFT) *
// 1000;
// }
// else
//{
seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
PANEL_POWER_CYCLE_DELAY_SHIFT) *
1000;
//}
}
static void
intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
{
PRINT_DEBUG(EFI_D_ERROR, "%a t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
state_name,
seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
}
static void
intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
//struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct edp_power_seq cur, vbt, spec,
*final = &intel_dp->pps_delays;
// lockdep_assert_held(&dev_priv->pps_mutex);
/* already initialized? */
if (final->t11_t12 != 0) {
PRINT_DEBUG(EFI_D_ERROR, "PPS already set. Exiting. t11_t12: %d\n", final->t11_t12);
return;
}
intel_pps_readout_hw_state(intel_dp, &cur);
intel_pps_dump_state("cur", &cur);
vbt = intel_dp->controller->vbt.edp.pps;
// /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
// * of 500ms appears to be too short. Ocassionally the panel
// * just fails to power back on. Increasing the delay to 800ms
// * seems sufficient to avoid this problem.
// */
// if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY)
// {
// vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
// PRINT_DEBUG(EFI_D_ERROR,"Increasing T12 panel delay as per the quirk to %d\n",
// vbt.t11_t12);
// }
/* T11_T12 delay is special and actually in units of 100ms, but zero
* based in the hw (so we need to add 100 ms). But the sw vbt
* table multiplies it with 1000 to make it in units of 100usec,
* too. */
vbt.t11_t12 += 100 * 10;
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
* our hw here, which are all in 100usec. */
spec.t1_t3 = 210 * 10;
spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
spec.t10 = 500 * 10;
/* This one is special and actually in units of 100ms, but zero
* based in the hw (so we need to add 100 ms). But the sw vbt
* table multiplies it with 1000 to make it in units of 100usec,
* too. */
spec.t11_t12 = (510 + 100) * 10;
intel_pps_dump_state("vbt", &vbt);
/* Use the max of the register settings and vbt. If both are
* unset, fall back to the spec limits. */
#define assign_final(field) do {\
final->field = (max(cur.field, vbt.field) == 0 ? spec.field : max(cur.field, vbt.field)); \
PRINT_DEBUG(EFI_D_ERROR, "Assigning val %d as cur: %d, vbt: %d, spec: %d\n", final->field, cur.field, vbt.field, spec.field);\
} while (0)
assign_final(t1_t3);
assign_final(t8);
assign_final(t9);
assign_final(t10);
assign_final(t11_t12);
#undef assign_final
#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
intel_dp->panel_power_up_delay = get_delay(t1_t3);
intel_dp->backlight_on_delay = get_delay(t8);
intel_dp->backlight_off_delay = get_delay(t9);
intel_dp->panel_power_down_delay = get_delay(t10);
intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay
PRINT_DEBUG(EFI_D_ERROR, "panel power up delay %d, power down delay %d, power cycle delay %d\n",
intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
intel_dp->panel_power_cycle_delay);
PRINT_DEBUG(EFI_D_ERROR, "backlight on delay %d, off delay %d\n",
intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
/*
* We override the HW backlight delays to 1 because we do manual waits
* on them. For T8, even BSpec recommends doing it. For T9, if we
* don't do this, we'll end up waiting for the backlight off delay
* twice: once when we do the manual sleep, and once when we disable
* the panel and wait for the PP_STATUS bit to become zero.
*/
final->t8 = 1;
final->t9 = 1;
/*
* HW has only a 100msec granularity for t11_t12 so round it up
* accordingly.
*/
final->t11_t12 = roundup(final->t11_t12, 100 * 10);
}
static void
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp)
{
//struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 pp_on, pp_off, pp_div = 0;
int div = intel_dp->controller->rawclk_freq / 1000;
struct pps_registers regs;
// enum port port = dp_to_dig_port(intel_dp)->base.port;
const struct edp_power_seq *seq = &intel_dp->pps_delays;
//lockdep_assert_held(&intel_dp->controller->pps_mutex);
intel_pps_get_registers(intel_dp, ®s);
// /* ALways false
// * On some VLV machines the BIOS can leave the VDD
// * enabled even on power sequencers which aren't
// * hooked up to any port. This would mess up the
// * power domain tracking the first time we pick
// * one of these power sequencers for use since
// * edp_panel_vdd_on() would notice that the VDD was
// * already on and therefore wouldn't grab the power
// * domain reference. Disable VDD first to avoid this.
// * This also avoids spuriously turning the VDD on as
// * soon as the new power sequencer gets initialized.
// */
// if (force_disable_vdd)
// {
// u32 pp = ironlake_get_pp_control(intel_dp);
// WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
// if (pp & EDP_FORCE_VDD)
// PRINT_DEBUG(EFI_D_ERROR,"VDD already on, disabling first\n");
// pp &= ~EDP_FORCE_VDD;
// intel_dp->controller->write32(regs.pp_ctrl, pp);
// }
pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
// if (IS_GEN9_LP(intel_dp->controller) || HAS_PCH_CNP(intel_dp->controller) ||
// HAS_PCH_ICP(intel_dp->controller))
// {
// pp_div = intel_dp->controller->read32(regs.pp_ctrl);
// pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
// pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
// << BXT_POWER_CYCLE_DELAY_SHIFT);
// }
// else
{
pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
<< PANEL_POWER_CYCLE_DELAY_SHIFT);
}
// /* Haswell doesn't have any port selection bits for the panel
// * power sequencer any more. */
// if (IS_VALLEYVIEW(intel_dp->controller) || IS_CHERRYVIEW(intel_dp->controller))
// {
// port_sel = PANEL_PORT_SELECT_VLV(port);
// }
// else if (HAS_PCH_IBX(intel_dp->controller) || HAS_PCH_CPT(intel_dp->controller))
// {
// switch (port)
// {
// case PORT_A:
// port_sel = PANEL_PORT_SELECT_DPA;
// break;
// case PORT_C:
// port_sel = PANEL_PORT_SELECT_DPC;
// break;
// case PORT_D:
// port_sel = PANEL_PORT_SELECT_DPD;
// break;
// default:
// MISSING_CASE(port);
// break;
// }
// }
// pp_on |= port_sel;
intel_dp->controller->write32(regs.pp_on, pp_on);
intel_dp->controller->write32(regs.pp_off, pp_off);
// if (IS_GEN9_LP(intel_dp->controller) || HAS_PCH_CNP(intel_dp->controller) ||
// HAS_PCH_ICP(intel_dp->controller))
// intel_dp->controller->write32(regs.pp_ctrl, pp_div);
// else
intel_dp->controller->write32(regs.pp_div, pp_div);
PRINT_DEBUG(EFI_D_ERROR, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
intel_dp->controller->read32(regs.pp_on),
intel_dp->controller->read32(regs.pp_off), intel_dp->controller->read32(regs.pp_div));
}
void intel_dp_pps_init(i915_CONTROLLER *controller)
{
//struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
// if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
// vlv_initial_power_sequencer_setup(intel_dp);
// } else {
intel_dp_init_panel_power_sequencer(controller->intel_dp);
intel_dp_init_panel_power_sequencer_registers(controller->intel_dp);
//}
}
EFI_STATUS SetupClockeDP(i915_CONTROLLER *controller)
{
UINT32 ctrl1;
UINT32 port = controller->OutputPath.Port;
UINT8 id = controller->OutputPath.DPLL;
/*
* See comment in intel_dpll_hw_state to understand why we always use 0
* as the DPLL id in this function. Basically, we put them in the first 6 bits then shift them into place for easier comparison
*/
ctrl1 = DPLL_CTRL1_OVERRIDE(id); //Enable Programming
ctrl1 |= DPLL_CTRL1_SSC(id);
// ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); //Set Mode to HDMI
UINT32 val = controller->read32(DPLL_CTRL2);
//val &= ~(DPLL_CTRL2_DDI_CLK_OFF(PORT_A) |
// DPLL_CTRL2_DDI_CLK_SEL_MASK(PORT_A));
//val |= (DPLL_CTRL2_DDI_CLK_SEL(id, PORT_A) |
// DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_A));
val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port));
val |= (DPLL_CTRL2_DDI_CLK_OFF(port));
controller->write32(DPLL_CTRL2, val);
controller->write32(LCPLL2_CTL, controller->read32(LCPLL2_CTL) & ~(LCPLL_PLL_ENABLE));
controller->write32(LCPLL1_CTL, controller->read32(LCPLL1_CTL) & ~(LCPLL_PLL_ENABLE));
val = controller->read32(DPLL_CTRL1);
for (UINT32 counter = 0;; counter++)
{
if (controller->read32(DPLL_STATUS) & DPLL_LOCK(id))
{
PRINT_DEBUG(EFI_D_ERROR, "DPLL %d locked\n", id);
break;
}
if (counter > 500)
{
PRINT_DEBUG(EFI_D_ERROR, "DPLL %d not locked\n", id);
break;
}
gBS->Stall(10);
}
//it's clock id!
//how's port clock comptued?
UINT64 clock_khz = controller->OutputPath.LinkRate;
PRINT_DEBUG(EFI_D_ERROR, "Link Rate: %u\n", clock_khz);
UINT32 linkrate = DPLL_CTRL1_LINK_RATE_810;
if (clock_khz >> 1 >= 135000)
{
linkrate = DPLL_CTRL1_LINK_RATE_1350;
}
else if (clock_khz >> 1 >= 270000)
{
linkrate = DPLL_CTRL1_LINK_RATE_2700;
}
//hack: anything else hangs
// UINT32 id = DPLL_CTRL1_LINK_RATE_1350;
ctrl1 |= DPLL_CTRL1_LINK_RATE(linkrate, id);
val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
DPLL_CTRL1_SSC(id) |
DPLL_CTRL1_LINK_RATE_MASK(id));
val |= ctrl1;
//DPLL 1
controller->write32(DPLL_CTRL1, val);
controller->read32(DPLL_CTRL1);
//845 80400173 3a5
PRINT_DEBUG(EFI_D_ERROR, "DPLL_CTRL1 = %08x\n", controller->read32(DPLL_CTRL1));
PRINT_DEBUG(EFI_D_ERROR, "_DPLL1_CFGCR1 = %08x\n", controller->read32(_DPLL1_CFGCR1));
PRINT_DEBUG(EFI_D_ERROR, "_DPLL1_CFGCR2 = %08x\n", controller->read32(_DPLL1_CFGCR2));
/* the enable bit is always bit 31 */
controller->write32(LCPLL2_CTL, controller->read32(LCPLL2_CTL) | LCPLL_PLL_ENABLE);
controller->write32(LCPLL1_CTL, controller->read32(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
for (UINT32 counter = 0;; counter++)
{
if (controller->read32(DPLL_STATUS) & DPLL_LOCK(id))
{
PRINT_DEBUG(EFI_D_ERROR, "DPLL %d locked\n", id);
break;
}
if (counter > 500)
{
PRINT_DEBUG(EFI_D_ERROR, "DPLL %d not locked\n", id);
break;
}
gBS->Stall(10);
}
//intel_encoders_pre_enable(crtc, pipe_config, old_state);
//could be intel_ddi_pre_enable_hdmi
//intel_ddi_clk_select(encoder, crtc_state);
PRINT_DEBUG(EFI_D_ERROR, "port is %d\n", port);
{
UINT32 val = controller->read32(DPLL_CTRL2);
//val &= ~(DPLL_CTRL2_DDI_CLK_OFF(PORT_A) |
// DPLL_CTRL2_DDI_CLK_SEL_MASK(PORT_A));
//val |= (DPLL_CTRL2_DDI_CLK_SEL(id, PORT_A) |
// DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_A));
val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
val |= (DPLL_CTRL2_DDI_CLK_SEL(id, port) |
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
controller->write32(DPLL_CTRL2, val);
}
PRINT_DEBUG(EFI_D_ERROR, "DPLL_CTRL2 = %08x\n", controller->read32(DPLL_CTRL2));
return EFI_SUCCESS;
}
struct ddi_buf_trans
{
UINT32 trans1; /* balance leg enable, de-emph level */
UINT32 trans2; /* vref sel, vswing */
UINT8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
};
/* Skylake H and S */
static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
{0x00002016, 0x000000A0, 0x0},
{0x00005012, 0x0000009B, 0x0},
{0x00007011, 0x00000088, 0x0},
{0x80009010, 0x000000C0, 0x1},
{0x00002016, 0x0000009B, 0x0},
{0x00005012, 0x00000088, 0x0},
{0x80007011, 0x000000C0, 0x1},
{0x00002016, 0x000000DF, 0x0},
{0x80005012, 0x000000C0, 0x1},
};
/* Skylake U */
static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
{0x0000201B, 0x000000A2, 0x0},
{0x00005012, 0x00000088, 0x0},
{0x80007011, 0x000000CD, 0x1},
{0x80009010, 0x000000C0, 0x1},
{0x0000201B, 0x0000009D, 0x0},
{0x80005012, 0x000000C0, 0x1},
{0x80007011, 0x000000C0, 0x1},
{0x00002016, 0x00000088, 0x0},
{0x80005012, 0x000000C0, 0x1},
};
/* Skylake Y */
static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
{0x00000018, 0x000000A2, 0x0},
{0x00005012, 0x00000088, 0x0},
{0x80007011, 0x000000CD, 0x3},
{0x80009010, 0x000000C0, 0x3},
{0x00000018, 0x0000009D, 0x0},
{0x80005012, 0x000000C0, 0x3},
{0x80007011, 0x000000C0, 0x3},
{0x00000018, 0x00000088, 0x0},
{0x80005012, 0x000000C0, 0x3},
};
#define IS_SKL_ULX(cont) (0)
#define IS_SKL_ULT(cont) (1)
static const struct ddi_buf_trans *
skl_get_buf_trans_dp(i915_CONTROLLER *controller, int *n_entries)
{
if (IS_SKL_ULX(controller))
{
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
return skl_y_ddi_translations_dp;
}
else if (IS_SKL_ULT(controller))
{
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
return skl_u_ddi_translations_dp;
}
else
{
*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
return skl_ddi_translations_dp;
}
}
/* Display Port */
#define DP_A _MMIO(0x64000) /* eDP */
#define DP_B _MMIO(0x64100)
#define DP_C _MMIO(0x64200)
#define DP_D _MMIO(0x64300)
EFI_STATUS SetupDDIBufferDP(i915_CONTROLLER *controller)
{
const struct ddi_buf_trans *ddi_translations;
int i, n_entries;
ddi_translations = skl_get_buf_trans_dp(controller,
&n_entries);
/* If we're boosting the current, set bit 31 of trans1 */
// if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
// iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
UINT32 port = controller->OutputPath.Port;
for (i = 0; i < n_entries; i++)
{
controller->write32(DDI_BUF_TRANS_LO(port, i),
ddi_translations[i].trans1);
controller->write32(DDI_BUF_TRANS_HI(port, i),
ddi_translations[i].trans2);
}
return EFI_SUCCESS;
}
/**
* struct drm_dp_aux_msg - DisplayPort AUX channel transaction
* @address: address of the (first) register to access
* @request: contains the type of transaction (see DP_AUX_* macros)
* @reply: upon completion, contains the reply type of the transaction
* @buffer: pointer to a transmission or reception buffer
* @size: size of @buffer
*/
struct drm_dp_aux_msg
{
unsigned int address;
UINT8 request;
UINT8 reply;
void *buffer;
UINT32 size;
};
struct cec_adapter;
struct edid;
struct drm_connector;
/**
* struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
* @lock: mutex protecting this struct
* @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
* @connector: the connector this CEC adapter is associated with
* @unregister_work: unregister the CEC adapter
*/
/* struct drm_dp_aux_cec {
struct mutex lock;
struct cec_adapter *adap;
struct drm_connector *connector;
struct delayed_work unregister_work;
}; */
/**
* struct drm_dp_aux - DisplayPort AUX channel
* @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
* @ddc: I2C adapter that can be used for I2C-over-AUX communication
* @dev: pointer to struct device that is the parent for this AUX channel
* @crtc: backpointer to the crtc that is currently using this AUX channel
* @hw_mutex: internal mutex used for locking transfers
* @crc_work: worker that captures CRCs for each frame