[handoff] WS-B Stage B: ctx-adaptive lane admission (lift QWISP_LANE_CTX 16K cap)

[penta2himajin]

Snapshot

• Branch: claude/lane-ctx-adaptive
• Last commit: 0261551 @ 2026-07-25
• Working tree: clean
• Last session: 2026-07-25 (Fable — spec authoring only, no implementation)

Status

in-progress (spec complete and binding; implementation not started — intended for a Sonnet session)

Next action

FIRST: merge PR #138 (WS-A archive — RAWTESTS 92→96; Stage B's locked test is numbered 97 on that precondition, see notes/22 "Preconditions"). Then run the devloop recon step from notes/22 §"Suggested session shape" (verify the four load-bearing facts against HEAD line numbers, which will drift after the #138 merge), then the devloop loop phase: locked tests RED (RAWTESTS 97 lane_admit_restore_cross_arena_bitexact + COMPTEST lanesize_*/lanemem_*) → implement → adversarial review.

Verification

• Spec: notes/22-ws-b-stage-b-ctx-adaptive-spec.md — read it IN FULL before any edit. All ambiguities are pre-resolved as binding ("Resolved ambiguities" section); do not re-open them in-session. Engine-physics questions beyond the spec → /askfable (read-only), not guesswork.
• Gates that must stay green through every commit: RAWTESTS (96/96 post-WS-A archive: sdpa_prefill_mma probe kernel (flag-off) + NO-GO verdict #138, 97/97 after the new test lands), COMPTEST 83/83 + new cases, BENCHBATCHTEST PASS.
• Definition of done for the implementation session: notes/22 §"Locked tests" all green + build green; the bench section (§"Bench verification") is run by the driver AFTER green, results appended to notes/22.

Context pointers

• Spec (canonical, binding): notes/22-ws-b-stage-b-ctx-adaptive-spec.md @ 0261551
• Stage A (pattern to mirror + code this builds on): notes/21, PR WS-B Stage A: token-budget admission scheduler (correctness phase) #140 (merged 33c8fba), issue [handoff] WS-B Stage A: token-budget admission scheduler #139 (closed — session log has the process trail incl. two bench false-starts worth reading).
• Code: swift/Sources/QwispCore/LaneServe.swift (sizing + admitStep + LaneBackend), swift/Sources/QwispCore/ContinuousBatch.swift (scheduler + BatchSlots protocol), swift/Sources/QwispCore/SeedlessLaneBatch.swift (read-only — verify the per-lane maxLen fact, do not edit kernels).
• Serialize-path precedent being mirrored: LLMBackend.swift:152-165 (prefixArenaMaxDefault / cachedGenBudget / QWISP_PREFIX_GEN_MAX — PR fix(server): prefix cache 64K cliff — resident arena cap follows model context #135).

Decisions made (binding, from notes/22)

• Adaptive sizing rides the Stage A scheduler flag (budgeted path only); QWISP_TOKEN_BUDGET_SCHED=0 keeps the legacy fixed-16K path bit-for-bit as the escape hatch.
• QWISP_LANE_CTX becomes an eligibility-cap override, default = model context (the 16384 default IS the bug being fixed).
• Memory gate: FCFS head-of-line wait (vLLM semantics), QWISP_LANE_KV_MB default 8192 (≥48GB RAM) / 4096, clamp-to-fit floor prompt+2, visible failure instead of the silent empty stream.
• REJECTED (terminal, do not implement): live warm-lane reuse (L1-incompatible — GDN recurrence no-rewind + decode-produced KV ≠ canonical prefill), warmth-based admission reordering (breaks locked FCFS test), PrefixPersist tier for lanes (backlog, owner decision pending).

Failed approaches

(none yet — spec phase only. Stage A's bench false-starts are documented in issue #139's session log and notes/21; the 35K filler-prompt generator in tools/lane_budget_probe.mjs already carries the units bugfix.)

[penta2himajin]

Session log — 2026-07-25 (Fable, spec phase): confirmed Stage B scope against the actual code before writing anything. Key verifications that shaped the spec: (1) SeedlessLaneBatch kernels take maxLen from each lane's own cache object and init only requires layers.count equality — heterogeneous arena sizes are safe by construction, so the cap lift is an allocation-parameter change, not a kernel change. (2) persistentStateData/restorePersistentState is arena-size-independent by wire format (used-slice save, destination-stride write, len<=maxLen validation) — cross-size restore needs a locked test but no format work. (3) The serialize path's PR #135 policy (cachedGenBudget + QWISP_PREFIX_GEN_MAX) is a reusable public pure function — Stage B mirrors it rather than inventing policy. (4) Live warm-lane reuse investigated and REJECTED as L1-incompatible (GDN recurrence cannot rewind to the prompt boundary; end-of-decode KV rows are decode-kernel-produced, not the canonical hybrid-prefill stream) — recorded in the spec so no future session re-derives it. Wrote notes/22 (binding spec, Sonnet-executable, all ambiguities pre-resolved), pushed branch claude/lane-ctx-adaptive, opened this issue. Implementation deliberately NOT started — owner will run it as a Sonnet session per the spec's 'Suggested session shape'. Precondition flagged loudly: merge PR #138 first (RAWTESTS numbering).

[penta2himajin]

Stage B round 2 + bench complete; PR #142 open.

• Locked test 97 lane_admit_restore_cross_arena_bitexact (RAWTESTS 96→97 by addition).
• Bench found and fixed a blocking regression: the flag-off path was allocating arenas at the 262144 eligibility cap (335MB → 5.37GB/lane, ungated), measured as a B≥2 collapse to 4.8-7.2 tok/s. Root cause was notes/22's Resolved-ambiguities 1 and 2 contradicting each other; both code and prose now split eligibility cap from allocation size.
• Gates: RAWTESTS 97/97, COMPTEST 93/93, BENCHBATCHTEST PASS.
• E2E: a 30,778-token prompt admits and streams (TTFT 152.7s); the QWISP_LANE_CTX=16384 control refuses it visibly in 816ms.

Open item carried forward: oversized prompts fail visibly on stderr but still return an empty HTTP 200.