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nxp_t1024.c
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nxp_t1024.c
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/* nxp_t1024.c
*
* Copyright (C) 2023 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#include <stdint.h>
#include "target.h"
#include "printf.h"
#include "string.h"
#include "hal.h"
#include "nxp_ppc.h"
#include "fdt.h"
#include "pci.h"
/* Tested on T1024E Rev 1.0, e5500 core 2.1, PVR 8024_1021 and SVR 8548_0010 */
/* IFC: CS0 NOR, CS1 MRAM, CS2 APU CPLD, CS3, MPU CPLD */
/* DDR: DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - SPD on I2C1 at Addr 0x51 */
/* Debugging */
/* #define DEBUG_FLASH */
/* #define DEBUG_ESPI 1 */
/* #define DEBUG_PHY */
#define ENABLE_IFC
#define ENABLE_BUS_CLK_CALC
#ifndef BUILD_LOADER_STAGE1
/* Tests */
#if 0
#define TEST_DDR
#define TEST_TPM
#endif
#define ENABLE_PCIE
#define ENABLE_CPLD
#define ENABLE_QE /* QUICC Engine */
#define ENABLE_FMAN
#define ENABLE_PHY
#define ENABLE_MRAM
#if defined(WOLFBOOT_TPM) || defined(TEST_TPM)
#define ENABLE_ESPI /* SPI for TPM */
#endif
#define ENABLE_MP /* multi-core support */
/* Booting Integrity OS */
#define RTOS_INTEGRITY_OS
#endif
#define USE_ERRATA_DDRA008378
#define USE_ERRATA_DDRA008109
#define USE_ERRATA_DDRA009663
#define USE_ERRATA_DDRA009942
/* Foward declarations */
#if defined(ENABLE_DDR) && defined(TEST_DDR)
static int test_ddr(void);
#endif
#if defined(ENABLE_ESPI) && defined(TEST_TPM)
static int test_tpm(void);
#endif
static void hal_flash_unlock_sector(uint32_t sector);
#ifdef ENABLE_ESPI
#include "spi_drv.h" /* for transfer flags and chip select */
#endif
/* T1024 */
/* System input clock */
#define SYS_CLK (100000000) /* 100MHz */
/* Boot page translation register - T1024RM 4.5.9 */
#define LCC_BSTRH ((volatile uint32_t*)(CCSRBAR + 0x20)) /* Boot space translation register high */
#define LCC_BSTRL ((volatile uint32_t*)(CCSRBAR + 0x24)) /* Boot space translation register low */
#define LCC_BSTAR ((volatile uint32_t*)(CCSRBAR + 0x28)) /* Boot space translation attribute register */
#define LCC_BSTAR_EN 0x80000000
#define LCC_BSTAR_LAWTRGT(n) ((n) << 20)
#define LCC_BSTAR_LAWSZ(n) ((n) & 0x3F)
/* DCFG (Device Configuration/Pin Control) T1024RM 7.3 */
#define DCSRBAR_BASE_HIGH 0xF
#define DCSRBAR_BASE 0xF0000000
#define DCFG_BASE (CCSRBAR + 0xE0000)
#define DCFG_PVR ((volatile uint32_t*)(DCFG_BASE + 0xA0UL))
#define DCFG_SVR ((volatile uint32_t*)(DCFG_BASE + 0xA4UL))
#define DCFG_DEVDISR1 ((volatile uint32_t*)(DCFG_BASE + 0x70UL)) /* Device disable register */
#define DCFG_DEVDISR2 ((volatile uint32_t*)(DCFG_BASE + 0x74UL)) /* Device disable register */
#define DCFG_DEVDISR3 ((volatile uint32_t*)(DCFG_BASE + 0x78UL)) /* Device disable register */
#define DCFG_DEVDISR4 ((volatile uint32_t*)(DCFG_BASE + 0x7CUL)) /* Device disable register */
#define DCFG_DEVDISR5 ((volatile uint32_t*)(DCFG_BASE + 0x80UL)) /* Device disable register */
#define DCFG_COREDISR ((volatile uint32_t*)(DCFG_BASE + 0x94UL)) /* Core Enable/Disable */
#define DCFG_RCWSR(n) ((volatile uint32_t*)(DCFG_BASE + 0x100UL + ((n) * 4))) /* Reset Control Word Status Register (0-15) */
#define DCFG_BRR ((volatile uint32_t*)(DCFG_BASE + 0xE4UL)) /* Boot Release Register (DCFG_CCSR_BRR) */
#define DCFG_DCSR ((volatile uint32_t*)(DCFG_BASE + 0x704UL)) /* Debug configuration and status */
/* RCW */
#define RCWSR4_SRDS1_PRTCL 0xFF800000
#define RCWSR4_SRDS1_PRTCL_SHIFT 23
/* Logical I/O Device Number */
#define DCFG_USB1LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x520))
#define DCFG_USB2LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x524))
#define DCFG_SDMMCLIODNR ((volatile uint32_t*)(DCFG_BASE + 0x530))
#define DCFG_SATALIODNR ((volatile uint32_t*)(DCFG_BASE + 0x550))
#define DCFG_DIULIODNR ((volatile uint32_t*)(DCFG_BASE + 0x570))
#define DCFG_TDMDMALIODNR ((volatile uint32_t*)(DCFG_BASE + 0x574))
#define DCFG_QELIODNR ((volatile uint32_t*)(DCFG_BASE + 0x578)) /* QUICC Engine Logical I/O Device Number register */
#define DCFG_DMA1LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x580))
#define DCFG_DMA2LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x584))
/* PCI Express LIODN base register */
#define PCIE_MAX_CONTROLLERS 3
#define PCIE_BASE(n) (CCSRBAR + 0x240000 + ((n-1) * 0x10000))
#define PCIE_CONFIG_ADDR(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0x00)) /* PEXx_PEX_CONFIG_ADDR - configuration address */
#define PCIE_CONFIG_DATA(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0x04)) /* PEXx_PEX_CONFIG_DATA - configuration data */
#define PCIE_LIODN(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0x40)) /* PEXx_PEX_LBR */
#define PCIE_BLK_REV1(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0xBF8)) /* PEXx_PEX_IP_BLK_REV1 */
#define PCIE_BLK_REV2(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0xBFC)) /* PEXx_PEX_IP_BLK_REV1 */
/* PCIe Output Windows (max 5) */
#define PCIE_OTAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC00 + ((w) * 32))) /* PEXx_PEXOTARn - outbound translation address */
#define PCIE_OTEAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC04 + ((w) * 32))) /* PEXx_PEXOTEARn - outbound translation extended address */
#define PCIE_OWBAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC08 + ((w) * 32))) /* PEXx_PEXOWBARn - outbound window base address */
#define PCIE_OWAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC10 + ((w) * 32))) /* PEXx_PEXOWARn - outbound window attributes */
#define POWAR_EN 0x80000000
#define POWAR_IO_READ 0x00080000
#define POWAR_MEM_READ 0x00040000
#define POWAR_IO_WRITE 0x00008000
#define POWAR_MEM_WRITE 0x00004000
/* PCIe Input Windows (max 4 - seq is 3,2,1,0) */
#define PCIE_ITAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD80 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXITARn - inbound translation address */
#define PCIE_IWBAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD88 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBARn - inbound window base address */
#define PCIE_IWBEAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD8C + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBEARn- inbound window base extended address */
#define PCIE_IWAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD90 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWARn - inbound window attributes */
#define PIWAR_EN 0x80000000
#define PIWAR_DIEN 0x40000000
#define PIWAR_PF 0x20000000
#define PIWAR_TRGT_PCI1 0x00000000
#define PIWAR_TRGT_PCI2 0x00100000
#define PIWAR_TRGT_PCI3 0x00200000
#define PIWAR_TRGT_CCSR 0x00E00000
#define PIWAR_TRGT_LOCAL 0x00F00000
#define PIWAR_READ 0x00040000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE 0x00004000
#define PIWAR_WRITE_SNOOP 0x00005000
/* Buffer Manager */
#define BMAN_LIODNR ((volatile uint32_t*)(BMAN_CCSR_BASE + 0xD08))
#define BCSP_ISDR(n) ((volatile uint32_t*)(BMAN_BASE_PHYS + 0x1000E08 + ((n) * 0x1000)))
/* Frame Queue Descriptor (FQD) */
#define FQD_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC04))
#define FQD_AR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC10))
/* Packed Frame Descriptor Record (PFDR) */
#define PFDR_BARE ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC20))
#define PFDR_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC24))
#define PFDR_AR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC30))
/* QMan */
#define QCSP_BARE ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC80)) /* Base Address (upper) */
#define QCSP_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC84)) /* Base Address */
/* QMan Software Portals */
#define QMAN_LIODNR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xD08))
#define QCSP_LIO_CFG(n) ((volatile uint32_t*)(QMAN_CCSR_BASE + 0x1000 + ((n) * 0x10)))
#define QCSP_IO_CFG(n) ((volatile uint32_t*)(QMAN_CCSR_BASE + 0x1004 + ((n) * 0x10)))
#define QCSP_ISDR(n) ((volatile uint32_t*)(QMAN_BASE_PHYS + 0x1000E08 + ((n) * 0x1000)))
/* SCGG (Supplemental Configuration Unit) T1024RM 6.1 */
#define SCFG_BASE (CCSRBAR + 0xFC000)
#define SCFG_QEIOCLKCR ((volatile uint32_t*)(DCFG_BASE + 0x400UL))
#define SCFG_EMIIOCR ((volatile uint32_t*)(DCFG_BASE + 0x404UL))
#define SCFG_SDHCIOVSEL ((volatile uint32_t*)(DCFG_BASE + 0x408UL))
#define SCFG_QEIOCLKCR_CLK11 0x04000000 /* IO_CLK[11] = GPIO_4[16] */
/* T1024RM: 4.6.5 */
#define CLOCKING_BASE (CCSRBAR + 0xE1000)
#define CLOCKING_CLKCCSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x000UL + ((n) * 0x20))) /* Core cluster n clock control/status register */
#define CLOCKING_CLKCGHWACSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x010UL + ((n) * 0x20))) /* Clock generator n hardware accelerator control/status */
#define CLOCKING_PLLCNGSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x800UL + ((n) * 0x20))) /* PLL cluster n general status register */
#define CLOCKING_CLKPCSR ((volatile uint32_t*)(CLOCKING_BASE + 0xA00UL)) /* Platform clock domain control/status register */
#define CLOCKING_PLLPGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC00UL)) /* Platform PLL general status register */
#define CLOCKING_PLLDGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC20UL)) /* DDR PLL general status register */
#define CLKC0CSR_CLKSEL(n) (((n) >> 27) & 0xF) /* 0000=Cluster PLL1 Output, 0001=Cluster PKK1 divide-by-2 */
#define PLLCGSR_CGF(n) (((n) >> 1) & 0x3F) /* Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL */
#define RCPM_BASE (CCSRBAR + 0xE2000)
#define RCPM_PCTBENR ((volatile uint32_t*)(RCPM_BASE + 0x1A0)) /* Physical Core Time Base Enable Bit 0=Core 0 */
#define RCPM_PCTBCKSELR ((volatile uint32_t*)(RCPM_BASE + 0x1A4)) /* Physical Core Time Base Clock Select 0=Platform Clock/16, 1=RTC */
#define RCPM_TBCLKDIVR ((volatile uint32_t*)(RCPM_BASE + 0x1A8)) /* Time Base Clock Divider 0=1/16, 1=1/8, 2=1/24, 3=1/32 */
/* MPIC - T1024RM 24.3 */
#define PIC_BASE (CCSRBAR + 0x40000)
#define PIC_WHOAMI ((volatile uint32_t*)(PIC_BASE + 0x0090UL)) /* Returns the ID of the processor core reading this register */
#define PIC_GCR ((volatile uint32_t*)(PIC_BASE + 0x1020UL)) /* Global configuration register (controls PIC operating mode) */
#define PIC_GCR_RST 0x80000000
#define PIC_GCR_M 0x20000000
/* QUICC Engine */
#define QE_MAX_RISC 1
#define QE_MURAM_SIZE (24 * 1024)
/* QE microcode/firmware address */
#ifndef QE_FW_ADDR
#define QE_FW_ADDR 0xEFE00000 /* location in NOR flash */
#endif
#define QE_BASE (CCSRBAR + 0x140000)
#define QE_IRAM_IADD ((volatile uint32_t*)(QE_BASE + 0x000UL))
#define QE_IRAM_IDATA ((volatile uint32_t*)(QE_BASE + 0x004UL))
#define QE_IRAM_IREADY ((volatile uint32_t*)(QE_BASE + 0x00CUL))
/* QUICC Engine Interrupt Controller */
#define QEIC_CIMR ((volatile uint32_t*)(QE_BASE + 0x0A0UL))
/* T1024 -> Two UCCs — UCC1, UCC3 supported - CMX UCC1/3 Clock Route Register */
#define QE_CMXUCR1 ((volatile uint32_t*)(QE_BASE + 0xC0000 + 0x410UL))
/* Baud-Rate Generator Configuration Registers */
#define BRG_BRGC(n) ((volatile uint32_t*)(QE_BASE + 0xC0000 + 0x640UL + ((n-1) * 0x4)))
#define QE_CP (QE_BASE + 0x100UL) /* Configuration register */
#define QE_CP_CECR ((volatile uint32_t*)(QE_CP + 0x00)) /* command register */
#define QE_CP_CECDR ((volatile uint32_t*)(QE_CP + 0x08)) /* data register */
#define QE_CP_CERCR ((volatile uint16_t*)(QE_CP + 0x38)) /* RAM control register */
#define QE_SDMA (QE_BASE + 0x4000UL) /* Serial DMA */
#define QE_SDMA_SDSR ((volatile uint32_t*)(QE_SDMA + 0x00))
#define QE_SDMA_SDMR ((volatile uint32_t*)(QE_SDMA + 0x04))
#define QE_SDMA_SDAQR ((volatile uint32_t*)(QE_SDMA + 0x38))
#define QE_SDMA_SDAQMR ((volatile uint32_t*)(QE_SDMA + 0x3C))
#define QE_SDMA_SDEBCR ((volatile uint32_t*)(QE_SDMA + 0x44))
#define QE_RSP (QE_BASE + 0x4100UL) /* Special Registers */
#define QE_RSP_TIBCR(n, i) ((volatile uint32_t*)(QE_RSP + ((n) * 0x100) + (i)))
#define QE_RSP_ECCR(n) ((volatile uint32_t*)(QE_RSP + ((n) * 0x100) + 0xF0))
#define QE_MURAM (QE_BASE + 0x110000UL) /* 24KB */
#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
#define QE_IRAM_READY 0x80000000
#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
#define QE_CR_FLG 0x00010000
#define QE_CR_PROTOCOL_SHIFT 6
#define QE_SDMR_GLB_1_MSK 0x80000000
#define QE_SDMR_CEN_SHIFT 13
#define QE_SDEBCR_BA_MASK 0x01FFFFFF
/* QE Commands */
#define QE_RESET 0x80000000
/* T1024RM 10.5.1: Queue Manager (QMan):
* - QMan block base address: 31_8000h
* - 512 frame queue (FQ) cache
* - 2-Kbyte SFDRs
* - 256 congestion groups
*/
#define QMAN_CCSR_BASE (CCSRBAR + 0x318000)
#define QMAN_BASE_PHYS_HIGH 0xF
#define QMAN_BASE_PHYS 0xF6000000
#define QMAN_NUM_PORTALS 10
/* T1024RM 10.5.2: Buffer Manager (BMan):
* - BMan block base address: 31_A000h
* - 64 buffer pools
*/
#define BMAN_CCSR_BASE (CCSRBAR + 0x31A000)
#define BMAN_BASE_PHYS_HIGH 0xF
#define BMAN_BASE_PHYS 0xF4000000
#define BMAN_NUM_POOLS 64
/* T1024RM 10.5.4: Security and Encryption Engine (SEC)
* - SEC block base address: 30_0000h
* - 2.5 Gbps SEC processing at 400 MHz
* - Cryptographic Hardware Accelerators (CHAs) include:
* - PKHA
* - DESA
* - AESA
* - MDHA
* - RNG4
* - AFHA
*/
/* T1024RM 10.5.3: Frame Manager (FMan):
* - FMan block base address: 40_0000h
* - Four multirate Ethernet MACs, for configuration options refer to SerDes Protocols
* - Block base addresses are as follows:
* - FM1 mEMAC1: 4E_0000h
* - FM1 mEMAC2: 4E_2000h
* - FM1 mEMAC3: 4E_4000h
* - FM1 mEMAC4: 4E_6000h
* - mEMAC PortIDs (RX/TX):
* - mEMAC1: 08h/28h
* - mEMAC2: 09h/29h
* - mEMAC3: 0Ah/2Ah
* - mEMAC4: 0Bh/2Bh
* - Supports 1 host command and 3 offline ports:
* - Host command: 02h
* - Offline port 3: 03h
* - Offline port 4: 04h
* - Offline port 5: 05h
* - FM1 Dedicated MDIO1: 4F_C000h
* - FM1 Dedicated MDIO2: 4F_D000h
* - One FMan Controller complexes
* - 192-Kbyte internal FMan memory
* - 32-Kbyte FMan Controller configuration data
* - Up to 32 Keygen schemes
* - Up to 8 Policer profiles
* - Up to 32 entries in FMan DMA command queue
* - Up to 64 TNUMs
* - Up to 1 FMan debug flows
*/
#define FMAN_COUNT 1
#ifndef FMAN_FW_ADDR
#define FMAN_FW_ADDR 0xEFF00000 /* location in NOR flash */
#endif
#define FMAN_BASE (CCSRBAR + 0x400000)
#define FMAN_MURAM (FMAN_BASE)
#define FMAN_MURAM_SIZE (512 * 1024)
/* Hardware Ports (0-63) 4KB each (256KB total) */
#define FMAN_BMI(n) ((FMAN_BASE + 0x80000) + ((n) * 0x1000))
#define FMAN_BMI_SPLIODN(n, p) ((volatile uint32_t*)(FMAN_BMI(n) + 0x304 + ((((p) - 1) & 0x3F) * 4)))
#define FMAN_QMI(n) ((FMAN_BASE + 0x80000) + ((n) * 0x1000) + 0x400)
#define FMAN_DMA (FMAN_BASE + 0xC2000UL) /* FMan DMA */
#define FMAN_DMA_ENTRIES (32)
#define FMAN_DMA_PORT_LIODN(n) ((volatile uint32_t*)(FMAN_DMA + 0x60 + (((n) & 0x1F) * 4))) /* FMan DMA portID-LIODN #0..31 register */
#define FMAN_FPM (FMAN_BASE + 0xC3000UL) /* Frame processing manager (FPM) */
#define FMAN_IRAM (FMAN_BASE + 0xC4000UL) /* FMan Controller Configuration Data */
#define FMAN_IRAM_IADD ((volatile uint32_t*)(FMAN_IRAM + 0x000UL)) /* Address Register (FMCDADDR) */
#define FMAN_IRAM_IDATA ((volatile uint32_t*)(FMAN_IRAM + 0x004UL)) /* Register (FMCDDATA) */
#define FMAN_IRAM_IREADY ((volatile uint32_t*)(FMAN_IRAM + 0x00CUL)) /* Ready Register (FMCDREADY) */
#define FMAN_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
#define FMAN_IRAM_READY 0x80000000
/* mEMAC (Multirate Ethernet Media Access Controller) 1-4 */
#define FMAN_MEMAC_BASE(n) (FMAN_BASE + 0xE0000UL + (((n-1) & 0x3) * 0x2000))
#define FMAN_MEMAC_CMD_CFG(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x008))
#define FMAN_MEMAC_MAC_ADDR_0(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x00C))
#define FMAN_MEMAC_MAC_ADDR_1(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x010))
#define FMAN_MEMAC_MAXFRMG(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x014))
#define FMAN_MEMAC_HTBLE_CTRL(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x02C))
#define FMAN_MEMAC_IEVENT(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x040))
#define FMAN_MEMAC_IMASK(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x04C))
#define FMAN_MEMAC_IF_MODE(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x300))
#define FMAN_MEMAC_IF_STATUS(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x304))
/* FMAN_MEMAC_CMD_CFG - Command and configuration register */
#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC RX path enable */
#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC TX path enable */
#define MEMAC_CMD_CFG_NO_LEN_CHK 0x00020000 /* Payload length check disable */
/* FMAN_MEMAC_IF_MODE - Interface Mode Register */
#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */
#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */
#define IF_MODE_RG 0x00000004 /* 1- RGMII */
#define IF_MODE_RM 0x00000008 /* 1- RGMII */
/* Dedicated MDIO EM1/EM2 Interface for PHY configurion */
#define FMAC_MDIO_BASE(n) (FMAN_BASE + 0xFC000UL + (((n-1) & 0x1) * 0x1000))
#define FMAN_MDIO_CFG(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x030))
#define FMAN_MDIO_CTRL(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x034))
#define FMAN_MDIO_DATA(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x038))
#define FMAN_MDIO_ADDR(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x03C))
#define MDIO_STAT_CLKDIV(x) ((((x)>>1) & 0xFF) << 8) /* valid range 5-511: ratio = (2 * CLKDIV) + 1 */
#define MDIO_STAT_BSY (1 << 0)
#define MDIO_STAT_RD_ER (1 << 1)
#define MDIO_STAT_PRE (1 << 5)
#define MDIO_STAT_EN_C45 (1 << 6) /* Enable Clause 45 support. */
#define MDIO_STAT_HOLD_15_CLK (7 << 2)
#define MDIO_STAT_NEG (1 << 23) /* MDIO is driven by master on MDC negative edge */
#define MDIO_CTL_DEV_ADDR(x) ( (x) & 0x1F)
#define MDIO_CTL_PORT_ADDR(x) (((x) & 0x1F) << 5)
#define MDIO_CTL_PRE_DIS (1 << 10)
#define MDIO_CTL_SCAN_EN (1 << 11)
#define MDIO_CTL_POST_INC (1 << 14)
#define MDIO_CTL_READ (1 << 15)
#define MDIO_ADDR(x) ((x) & 0xFFFF)
#define MDIO_DATA(x) ((x) & 0xFFFF)
#define MDIO_DATA_BSY (1UL << 31)
/* T1024 PC16552D Dual UART */
#define BAUD_RATE 115200
#define UART_SEL 0 /* select UART 0 or 1 */
#define UART_BASE(n) (CCSRBAR + 0x11C500 + (n * 0x1000))
#define UART_RBR(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */
#define UART_THR(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */
#define UART_IER(n) ((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */
#define UART_IIR(n) ((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */
#define UART_FCR(n) ((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */
#define UART_LCR(n) ((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */
#define UART_MCR(n) ((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */
#define UART_LSR(n) ((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */
/* enabled when UART_LCR_DLAB set */
#define UART_DLB(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */
#define UART_DMB(n) ((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */
#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */
#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */
#define UART_FCR_FEN (0x01) /* FIFO enable */
#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */
#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */
#define UART_LSR_TEMT (0x40) /* Transmitter empty */
#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
/* T1024 IFC (Integrated Flash Controller) - RM 23.1 */
#define IFC_BASE (CCSRBAR + 0x00124000)
#define IFC_MAX_BANKS 8
#define IFC_CSPR_EXT(n) ((volatile uint32_t*)(IFC_BASE + 0x000C + (n * 0xC))) /* Extended Base Address */
#define IFC_CSPR(n) ((volatile uint32_t*)(IFC_BASE + 0x0010 + (n * 0xC))) /* Chip-select Property */
#define IFC_AMASK(n) ((volatile uint32_t*)(IFC_BASE + 0x00A0 + (n * 0xC)))
#define IFC_CSOR(n) ((volatile uint32_t*)(IFC_BASE + 0x0130 + (n * 0xC)))
#define IFC_CSOR_EXT(n) ((volatile uint32_t*)(IFC_BASE + 0x0134 + (n * 0xC)))
#define IFC_FTIM0(n) ((volatile uint32_t*)(IFC_BASE + 0x01C0 + (n * 0x30)))
#define IFC_FTIM1(n) ((volatile uint32_t*)(IFC_BASE + 0x01C4 + (n * 0x30)))
#define IFC_FTIM2(n) ((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30)))
#define IFC_FTIM3(n) ((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30)))
#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFFFF00) /* Physical base address */
#define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */
#define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */
#define IFC_CSPR_WP 0x00000040 /* Write Protect */
#define IFC_CSPR_MSEL_NOR 0x00000000 /* Mode Select - NOR */
#define IFC_CSPR_MSEL_NAND 0x00000002 /* Mode Select - NAND */
#define IFC_CSPR_MSEL_GPCM 0x00000004 /* Mode Select - GPCM (General-purpose chip-select machine) */
#define IFC_CSPR_V 0x00000001 /* Bank Valid */
/* NOR Timings (IFC clocks) */
#define IFC_FTIM0_NOR_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */
#define IFC_FTIM0_NOR_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */
#define IFC_FTIM0_NOR_TAVDS(n) (((n) & 0x3F) << 8) /* Delay between CS assertion */
#define IFC_FTIM0_NOR_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */
#define IFC_FTIM1_NOR_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */
#define IFC_FTIM1_NOR_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */
#define IFC_FTIM1_NOR_TSEQ(n) (((n) & 0x3F) << 0) /* sequential read access delay */
#define IFC_FTIM2_NOR_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */
#define IFC_FTIM2_NOR_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */
#define IFC_FTIM2_NOR_TWPH(n) (((n) & 0x3F) << 10) /* Chip-select hold time */
#define IFC_FTIM2_NOR_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */
/* GPCM Timings (IFC clocks) */
#define IFC_FTIM0_GPCM_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */
#define IFC_FTIM0_GPCM_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */
#define IFC_FTIM0_GPCM_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */
#define IFC_FTIM1_GPCM_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */
#define IFC_FTIM1_GPCM_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */
#define IFC_FTIM2_GPCM_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */
#define IFC_FTIM2_GPCM_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */
#define IFC_FTIM2_GPCM_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */
/* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */
enum ifc_amask_sizes {
IFC_AMASK_64KB = 0xFFFF0000,
IFC_AMASK_128KB = 0xFFFE0000,
IFC_AMASK_256KB = 0xFFFC0000,
IFC_AMASK_512KB = 0xFFF80000,
IFC_AMASK_1MB = 0xFFF00000,
IFC_AMASK_2MB = 0xFFE00000,
IFC_AMASK_4MB = 0xFFC00000,
IFC_AMASK_8MB = 0xFF800000,
IFC_AMASK_16MB = 0xFF000000,
IFC_AMASK_32MB = 0xFE000000,
IFC_AMASK_64MB = 0xFC000000,
IFC_AMASK_128MB = 0xF8000000,
IFC_AMASK_256MB = 0xF0000000,
IFC_AMASK_512MB = 0xE0000000,
IFC_AMASK_1GB = 0xC0000000,
IFC_AMASK_2GB = 0x80000000,
IFC_AMASK_4GB = 0x00000000,
};
/* NOR Flash */
#define FLASH_BANK_SIZE (64*1024*1024)
#define FLASH_PAGE_SIZE (1024) /* program buffer */
#define FLASH_SECTOR_SIZE (128*1024)
#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE)
#define FLASH_CFI_WIDTH 16 /* 8 or 16 */
#define FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
/* Intel CFI */
#define FLASH_CMD_CFI 0x98
#define FLASH_CMD_READ_ID 0x90
#define FLASH_CMD_RESET 0xFF
#define FLASH_CMD_BLOCK_ERASE 0x20
#define FLASH_CMD_ERASE_CONFIRM 0xD0
#define FLASH_CMD_WRITE 0x40
#define FLASH_CMD_PROTECT 0x60
#define FLASH_CMD_SETUP 0x60
#define FLASH_CMD_SET_CR_CONFIRM 0x03
#define FLASH_CMD_PROTECT_SET 0x01
#define FLASH_CMD_PROTECT_CLEAR 0xD0
#define FLASH_CMD_CLEAR_STATUS 0x50
#define FLASH_CMD_READ_STATUS 0x70
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
#define FLASH_STATUS_DONE 0x80
#define FLASH_STATUS_ESS 0x40
#define FLASH_STATUS_ECLBS 0x20
#define FLASH_STATUS_PSLBS 0x10
#define FLASH_STATUS_VPENS 0x08
#define FLASH_STATUS_PSS 0x04
#define FLASH_STATUS_DPS 0x02
#define FLASH_STATUS_R 0x01
#define FLASH_STATUS_PROTECT 0x01
/* AMD CFI */
#define AMD_CMD_RESET 0xF0
#define AMD_CMD_WRITE 0xA0
#define AMD_CMD_ERASE_START 0x80
#define AMD_CMD_ERASE_SECTOR 0x30
#define AMD_CMD_UNLOCK_START 0xAA
#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_CMD_WRITE_TO_BUFFER 0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
#define AMD_CMD_SET_PPB_ENTRY 0xC0
#define AMD_CMD_SET_PPB_EXIT_BC1 0x90
#define AMD_CMD_SET_PPB_EXIT_BC2 0x00
#define AMD_CMD_PPB_UNLOCK_BC1 0x80
#define AMD_CMD_PPB_UNLOCK_BC2 0x30
#define AMD_CMD_PPB_LOCK_BC1 0xA0
#define AMD_CMD_PPB_LOCK_BC2 0x00
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
/* Flash unlock addresses */
#if FLASH_CFI_WIDTH == 16
#define FLASH_UNLOCK_ADDR1 0x555
#define FLASH_UNLOCK_ADDR2 0x2AA
#else
#define FLASH_UNLOCK_ADDR1 0xAAA
#define FLASH_UNLOCK_ADDR2 0x555
#endif
/* Flash IO Helpers */
#if FLASH_CFI_WIDTH == 16
#define FLASH_IO8_WRITE(sec, n, val) *((volatile uint16_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + ((n) * 2))) = (((val) << 8) | (val))
#define FLASH_IO16_WRITE(sec, n, val) *((volatile uint16_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + ((n) * 2))) = (val)
#define FLASH_IO8_READ(sec, n) (uint8_t)(*((volatile uint16_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + ((n) * 2))))
#define FLASH_IO16_READ(sec, n) *((volatile uint16_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + ((n) * 2)))
#else
#define FLASH_IO8_WRITE(sec, n, val) *((volatile uint8_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + (n))) = (val)
#define FLASH_IO8_READ(sec, n) *((volatile uint8_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + (n)))
#endif
/* DDR4 - 2GB */
/* 1600 MT/s (64-bit, CL=12, ECC on) */
/* SA[0-15]: 0000: Starting address for chip select (bank)n
* EA[16-31]: 007F: Ending address for chip select (bank)n
*/
#define DDR_CS0_BNDS_VAL 0x0000007F
#define DDR_CS1_BNDS_VAL 0x008000BF
#define DDR_CS2_BNDS_VAL 0x0100013F
#define DDR_CS3_BNDS_VAL 0x0140017F
/* 15=row bits, 10 column bits, 1 bank group bit, 2 logical bank bits, ODT only during writes */
/* CS_EN [0]: 1 Chip select n enable
* AP_EN [8]: 1 Chip select nauto-precharge enable
* ODT_RD_CFG [9-11]: ODT for reads configuration
* ODT_WR_CFG [13-15]: ODT for writes configuration
* BA_BITS_CS [16-17]: Number of bank bits for SDRAM on chip selectn
* ROW_BITS_CS[21-23]: Number of row bits for SDRAM on chip selectn
* BG_BITS_CS [26-27]: Number of bank group bits for SDRAM on chip selectn
* COL_BITS_CS[29-31]: Number of column bits for SDRAM on chip selectn
*/
#define DDR_CS0_CONFIG_VAL 0x80810312 /* was 0x80010312 */
#define DDR_CS1_CONFIG_VAL 0x00000202
#define DDR_CS2_CONFIG_VAL 0x00000202
#define DDR_CS3_CONFIG_VAL 0x00010202
/* PASR_DEC[0]: Partial array decoding
* PASR_CFG[5-7]: Partial array self refresh config
*/
#define DDR_CS_CONFIG_2_VAL 0x00000000
/* RWT [0-1]: 10: 2 clocks: Read-to-write turnaround (tRTW)
* WRT [2-3]: 00: 0 clocks: Write-to-read turnaround
* RRT [4-5]: 00: 0 clocks: Read-to-read turnaround
* WWT [6-7]: 00: 0 clocks: Write-to-write turnaround
* ACT_PD_EXIT [8-11]: 0101: 5 clocks: Active powerdown exit timing (tXP)
* PRE_PD_EXIT [12-15]: 0100: 4 clocks: Precharge powerdown exit timing (tXP)
* EXT_PRE_PD_EXIT[16-17]: 01: 16 clocks: Extended precharge powerdown exit timing (tXP)
* MRS_CYC [27-31]: 01100: 12 clocks: Mode register set cycle time (tMRD, tMOD)
*/
#define DDR_TIMING_CFG_0_VAL 0x8055000C
/* PRETOACT [0-3]: 0011: 3 clocks: Precharge-to-activate interval (tRP)
* ACTTOPRE [4-7]: 1110: 14 clocks (30 total): Activate to precharge interval (tRAS)
* ACTTORW [8-11]: 0010: 2 clocks (18 total): Activate to read/write interval for SDRAM (tRCD)
* CASLAT [12-14]: 011: 4 clocks: MCAS_B latency from READ command
* REFREC [16-19]: 1100: 12 clocks (240+12+8 total): Refresh recovery time (tRFC)
* WRREC [20-23]: 1110: 14 clocks: Last data to precharge minimum interval (tWR)
* ACTTOACT [24-27]: 0100: 4 clocks: Activate-to-activate interval (tRRD)
* WRTORD [28-31]: 0100: 4 clocks: Last write data pair to read command issue interval (tWTR)
*/
#define DDR_TIMING_CFG_1_VAL 0x3E26CE44 /* was 0x2E268E44 */
/* ADD_LAT [0-3]: 0000: 0 clocks Additive latency
* WR_LAT [9-12]: 1001: 9 clocks Write latency
* EXT_WR_LAT [13]: 0: 0 clocks Extended Write Latency (1=16 clocks)
* RD_TO_PRE [15-18]: 1000: 8 clocks Read to precharge (tRTP).
* WR_DATA_DELAY [19-22]: 1000: 1 clock delay Write command to write data strobe timing adjustment.
* CKE_PLS [23-25]: 100: 4 clocks Minimum CKE pulse width (tCKE).
* FOUR_ACT [26-31]: 011100: 28 Window for four activates (tFAW).
*/
#define DDR_TIMING_CFG_2_VAL 0x0049111C /* tried 0x00491124 */
/* EXT_PRETOACT [3]: 1: 16 clocks: Extended precharge-to-activate interval (0=0, 1=16 clocks)
* EXT_ACTTOPRE [6-7]: 01: 16 clocks: Extended Activate to precharge interval (tRAS)
* EXT_ACTTORW [9]: 1: 16 clocks: Extended activate to read/write interval for SDRAM (tRCD) (ACTTORW[5])
* EXT_REFREC [10-15]: 001111: 240 Extended refresh recovery time (tRFC).
* EXT_CASLAT [18-19]: 01: 8 clocks Extended MCAS_B latency from READ command
* EXT_ADD_LAT [21]: 0: 0 clocks Extended Additive Latency
* EXT_WRREC [23]: 1: 16 clocks Extended last data to precharge minimum interval (tWR)
* CNTL_ADJ [29-31]: 000: MODTn, MCSn_B, and MCKEn will be launched aligned with the other DRAM address and control signals.
*/
#define DDR_TIMING_CFG_3_VAL 0x114F1100 /* was 0x114C1000 */
/* RWT [0-3]: 0000: 0 clocks: Read-to-write turnaround for same chip select.
* WRT [4-7]: 0000: 0 clocks: Write-to-read turnaround for same chip select
* RRT [8-11]: 0010: 2 clocks: Read-to-read turnaround for same chip select
* WWT [12-15]: 0010: 2 clocks: Write-to-write turnaround for same chip select.
* EXT_RWT [16-17]: 00: Extended read-to-write turnaround (tRTW)
* EXT_WRT [19]: 0: Extended write-to-read turnaround
* EXT_RRT [21]: 0: Extended read-to-read turnaround
* EXT_WWT [23]: 0: Extended write-to-write turnaround
* EXT_REFINT [27]: 0: Refresh interval (0=0,1=65,536 clocks)
* DLL_LOCK [30-31]: 10: 1024 clocks: DDR SDRAM DLL Lock Time (0=200, 1=512, 2=1024 clocks)
*/
#define DDR_TIMING_CFG_4_VAL 0x00220002 /* was 0x00220001 */
/* RODT_ON [3-7]: 0101: 4 clocks: Read to ODT on (0=CASLAT-WR_LAT, 1=0, 2=1, 12=11 clocks)
* RODT_OFF [9-11]: 100: 4 clocks: Read to ODT off (0=4, 1=1, 7=7 clocks)
* WODT_ON [15-19]: 00001: 1 clock: Write to ODT off (1=0, 2=1, 6=5 clocks)
* WODT_OFF [21-23]: 100: 4 clocks: Write to ODT off (0=4, 1=1, 7=7 clocks)
*/
#define DDR_TIMING_CFG_5_VAL 0x05401400
#define DDR_TIMING_CFG_6_VAL 0x00000000
/* CKE_RST [2-3]: 00: 200 clocks: CKE reset time (tXPR) (0=200, 1=256, 2=512, 3=1024 clocks)
* CKSRE [4-7]: 0000: 15 clocks: Valid clock after Self Refresh entry (tCKSRE) (0=15, 1=6, )
* CKSRX [8-11]: 0000: 15 clocks: Valid clock after Self Refresh exit (tCKSRX)
* PAR_LAT [12-15]: 0000: 0 clocks
* CS_TO_CMD [24-27]: 0000: 0 clocks: Chip select to command latency
*/
#define DDR_TIMING_CFG_7_VAL 0x00000000 /* tried 0x00050000 */
/* RWT_BG [0-3]: 0000: Read-to-write turnaround for same chip select and same bank group
* WRT_BG [4-7]: 0011: Write-to-read turnaround for same chip select and same bank group
* RRT_BG [8-11]: 0001: Read-to-read turnaround for same chip select and same bank group
* WWT_BG [12-15]: 0001: Write-to-write turnaround for same chip select and same bank group
* ACTTOACT_BG [16-19]: 0101: Activate-to-activate interval for the same bank group(tRRD_L).
* WRTORD_BG [20-23]: 1000: Last write data pair to read command issue interval for the same bank group(tWTR_L)
* PRE_ALL_REC [27-31]: 00000: Precharge all-to-activate interval
*/
#define DDR_TIMING_CFG_8_VAL 0x03115800
/* MR1 | MR0
* MR0 0x0215
* | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* [ WR/RTP ] [ CL3-1 ][BT][CL0][ BL ]
* Burst Length (BL) = 01: 00 (fixed 8), 01 (on the fly), 02 (fixed 4)
* Burst Type (BT) = 0 (nibble sequential), 1 (interleave)
* CAS Latency (CL):
* 00000 (9 clocks)
* 00001 (10 clocks)
* 00010 (11 clocks)
* 00011 (12 clocks) (original)
* 00100 (13 clocks)
* 00101 (14 clocks)
* 00110 (15 clocks)
* 00111 (16 clocks)
* 10111 (32 clocks)
* WRITE recovery (WR)/READ-to-PRECHARGE(RTP):
* 0000 (10/5 clocks)
* 0001 (12/6 clocks) (original)
* 0010 (14/7 clocks)
* 0011 (16/8 clocks)
* 0100 (18/9 clocks)
* 0101 (20/10 clocks)
* 0110 (24/12 clocks)
* 0111 (22/11 clocks)
* 1000 (26/13 clocks)
* 1001 (28/14 clocks)
*
* MR1 0x0101
* | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* [TDQS][ RTT_NOM ][Wlev] [ AL ][ ODI ][DLL]
* DLL=1, RTT_NOM=001 (RZQ/4 60ohm), ODI=00 (RZQ/7 34ohm)
*/
#define DDR_SDRAM_MODE_VAL 0x01010215
/* MR2 | MR3
* MR2
* | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* [ RTT_WR ] [ CWL ]
*
* MR3
* | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* [ WR_CMD_LAT]
*/
#define DDR_SDRAM_MODE_2_VAL 0x00000000
/* Not applicable (reuse other MRs) */
#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
/* MR4 | MR5
* MR4: 0x0100
* MR5: 0x013F: RTT_PARK=000 disabled, CA Parity Latency=010 (5 clocks) */
#define DDR_SDRAM_MODE_9_VAL 0x00000500
/* MR6 | MR7:
* MR7: CCD_L 010=6 clocks, VREF Range 1 */
#define DDR_SDRAM_MODE_10_VAL 0x04000000
#define DDR_SDRAM_MD_CNTL_VAL 0x03001000
#define DDR_SDRAM_CFG_VAL 0xE5200000 /* DDR4 w/ECC */
/* ODT_CFG [9-10]: 10: Assert ODT to internal IOs only
* NUM_PR [16-19]: 00001: 1 refresh
* OBC_CFG [25]: 1: On-the-fly Burst Chop mode will be used
* D_INIT [27]: 1: The memory controller will initialize memory once it is enabled
*/
#define DDR_SDRAM_CFG_2_VAL 0x00401050
/* REF_MODE[22-23]: Refresh Mode */
#define DDR_SDRAM_CFG_3_VAL 0x00000000
/* REFINT [0-15]: 6240: Refresh interval 12480=0x30C0
* BSTOPRE [18-31]: 1560: Precharge interval
*/
#define DDR_SDRAM_INTERVAL_VAL 0x18600000 /* was 0x18600618 */
#define DDR_DATA_INIT_VAL 0xDEADBEEF
/* CLK_ADJUST[5-9]: applied cycle after address/command
* 00000 = aligned
* 00001 = 1/16
* 00100 = 1/4
* 00110 = 3/8
* 01001 = 9/16
* 01000 = 1/2 (configured)
* 01010 = 5/8
* 10000 = 1
*/
#define DDR_SDRAM_CLK_CNTL_VAL 0x02000000 /* was 0x02400000 */
/* ZQ_EN */
#define DDR_ZQ_CNTL_VAL 0x8A090705
/* WRLVL_EN [0]: 1: Write Leveling Enable
* WRLVL_MRD [5-7]: 110 0x6: 64 clocks
* WRLVL_ODTEN[9-11]: 111 0x7: 128 clocks ODT delay after margining mode is programmed (tWL_ODTEN).
* WRLVL_DQSEN[13-15]: 101 0x5: 32 clocks DQS/DQS_B delay after margining mode is programmed (tWL_DQSEN).
* WRLVL_SMPL [16-19]: 1111 0xF: 15 clocks Write leveling sample time
* WRLVL_WLR [21-23]: 110 0x6: 64 clocks Write leveling repetition time.
* WRLVL_START[27-31]: 1000 0x8: 3/4 clocks Write leveling start time for DQS[0].
*/
#define DDR_WRLVL_CNTL_VAL 0x8675F606
/* WRLVL_START_1 [3-7]: 3/4 Write leveling start time for DQS[1]
* WRLVL_START_2[11-15]: 7/8 Write leveling start time for DQS[2]
* WRLVL_START_3[19-23]: 7/8 Write leveling start time for DQS[3]
* WRLVL_START_4[27-31]: 9/8 Write leveling start time for DQS[4]
*/
#define DDR_WRLVL_CNTL_2_VAL 0x06070709
/* WRLVL_START_5 [3-7]: 9/8 Write leveling start time for DQS[5]
* WRLVL_START_6[11-15]: 9/8 Write leveling start time for DQS[6]
* WRLVL_START_7[19-23]: 9/8 Write leveling start time for DQS[7]
* WRLVL_START_8[27-31]: 1 Write leveling start time for DQS[8]
*/
#define DDR_WRLVL_CNTL_3_VAL 0x09090908
#define DDR_SDRAM_RCW_1_VAL 0x00000000
#define DDR_SDRAM_RCW_2_VAL 0x00000000
/* DHC_EN[0]=1, ODT[12-13]=120 Ohms, VREF_OVRD 37% */
#define DDR_DDRCDR_1_VAL 0x80000000 /* was 0x80080000 */
#define DDR_DDRCDR_2_VAL 0x00000000
#define DDR_ERR_INT_EN_VAL 0x0000001D
#define DDR_ERR_SBE_VAL 0x00000000
/* 12.4 DDR Memory Map */
#define DDR_BASE (CCSRBAR + 0x8000)
#define DDR_CS_BNDS(n) ((volatile uint32_t*)(DDR_BASE + 0x000 + (n * 8))) /* Chip select n memory bounds */
#define DDR_CS_CONFIG(n) ((volatile uint32_t*)(DDR_BASE + 0x080 + (n * 4))) /* Chip select n configuration */
#define DDR_CS_CONFIG_2(n) ((volatile uint32_t*)(DDR_BASE + 0x0C0 + (n * 4))) /* Chip select n configuration 2 */
#define DDR_SDRAM_CFG ((volatile uint32_t*)(DDR_BASE + 0x110)) /* DDR SDRAM control configuration */
#define DDR_SDRAM_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x114)) /* DDR SDRAM control configuration 2 */
#define DDR_SDRAM_CFG_3 ((volatile uint32_t*)(DDR_BASE + 0x260)) /* DDR SDRAM control configuration 3 */
#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
#define DDR_INIT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x148)) /* DDR training initialization address */
#define DDR_INIT_EXT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x14C)) /* DDR training initialization extended address */
#define DDR_DATA_INIT ((volatile uint32_t*)(DDR_BASE + 0x128)) /* DDR training initialization value */
#define DDR_TIMING_CFG_0 ((volatile uint32_t*)(DDR_BASE + 0x104)) /* DDR SDRAM timing configuration 0 */
#define DDR_TIMING_CFG_1 ((volatile uint32_t*)(DDR_BASE + 0x108)) /* DDR SDRAM timing configuration 1 */
#define DDR_TIMING_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x10C)) /* DDR SDRAM timing configuration 2 */
#define DDR_TIMING_CFG_3 ((volatile uint32_t*)(DDR_BASE + 0x100)) /* DDR SDRAM timing configuration 3 */
#define DDR_TIMING_CFG_4 ((volatile uint32_t*)(DDR_BASE + 0x160)) /* DDR SDRAM timing configuration 4 */
#define DDR_TIMING_CFG_5 ((volatile uint32_t*)(DDR_BASE + 0x164)) /* DDR SDRAM timing configuration 5 */
#define DDR_TIMING_CFG_6 ((volatile uint32_t*)(DDR_BASE + 0x168)) /* DDR SDRAM timing configuration 6 */
#define DDR_TIMING_CFG_7 ((volatile uint32_t*)(DDR_BASE + 0x16C)) /* DDR SDRAM timing configuration 7 */
#define DDR_TIMING_CFG_8 ((volatile uint32_t*)(DDR_BASE + 0x250)) /* DDR SDRAM timing configuration 8 */
#define DDR_ZQ_CNTL ((volatile uint32_t*)(DDR_BASE + 0x170)) /* DDR ZQ calibration control */
#define DDR_WRLVL_CNTL ((volatile uint32_t*)(DDR_BASE + 0x174)) /* DDR write leveling control */
#define DDR_WRLVL_CNTL_2 ((volatile uint32_t*)(DDR_BASE + 0x190)) /* DDR write leveling control 2 */
#define DDR_WRLVL_CNTL_3 ((volatile uint32_t*)(DDR_BASE + 0x194)) /* DDR write leveling control 3 */
#define DDR_SR_CNTR ((volatile uint32_t*)(DDR_BASE + 0x17C)) /* DDR Self Refresh Counter */
#define DDR_SDRAM_RCW_1 ((volatile uint32_t*)(DDR_BASE + 0x180)) /* DDR Register Control Word 1 */
#define DDR_SDRAM_RCW_2 ((volatile uint32_t*)(DDR_BASE + 0x184)) /* DDR Register Control Word 2 */
#define DDR_SDRAM_RCW_3 ((volatile uint32_t*)(DDR_BASE + 0x1A0)) /* DDR Register Control Word 3 */
#define DDR_SDRAM_RCW_4 ((volatile uint32_t*)(DDR_BASE + 0x1A4)) /* DDR Register Control Word 4 */
#define DDR_SDRAM_RCW_5 ((volatile uint32_t*)(DDR_BASE + 0x1A8)) /* DDR Register Control Word 5 */
#define DDR_SDRAM_RCW_6 ((volatile uint32_t*)(DDR_BASE + 0x1AC)) /* DDR Register Control Word 6 */
#define DDR_DDRCDR_1 ((volatile uint32_t*)(DDR_BASE + 0xB28)) /* DDR Control Driver Register 1 */
#define DDR_DDRCDR_2 ((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */
#define DDR_DDRDSR_1 ((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */
#define DDR_DDRDSR_2 ((volatile uint32_t*)(DDR_BASE + 0xB24)) /* DDR Debug Status Register 2 */
#define DDR_ERR_DISABLE ((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */
#define DDR_ERR_INT_EN ((volatile uint32_t*)(DDR_BASE + 0xE48)) /* Memory error interrupt enable */
#define DDR_ERR_SBE ((volatile uint32_t*)(DDR_BASE + 0xE58)) /* Single-Bit ECC memory error management */
#define DDR_SDRAM_MODE ((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */
#define DDR_SDRAM_MODE_2 ((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */
#define DDR_SDRAM_MODE_3 ((volatile uint32_t*)(DDR_BASE + 0x200)) /* DDR SDRAM mode configuration 3 */
#define DDR_SDRAM_MODE_4 ((volatile uint32_t*)(DDR_BASE + 0x204)) /* DDR SDRAM mode configuration 4 */
#define DDR_SDRAM_MODE_5 ((volatile uint32_t*)(DDR_BASE + 0x208)) /* DDR SDRAM mode configuration 5 */
#define DDR_SDRAM_MODE_6 ((volatile uint32_t*)(DDR_BASE + 0x20C)) /* DDR SDRAM mode configuration 6 */
#define DDR_SDRAM_MODE_7 ((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */
#define DDR_SDRAM_MODE_8 ((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */
#define DDR_SDRAM_MODE_9 ((volatile uint32_t*)(DDR_BASE + 0x220)) /* DDR SDRAM mode configuration 9 */
#define DDR_SDRAM_MODE_10 ((volatile uint32_t*)(DDR_BASE + 0x224)) /* DDR SDRAM mode configuration 10 */
#define DDR_SDRAM_MD_CNTL ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
#define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
#define DDR_DEBUG_9 ((volatile uint32_t*)(DDR_BASE + 0xF20))
#define DDR_DEBUG_10 ((volatile uint32_t*)(DDR_BASE + 0xF24))
#define DDR_DEBUG_11 ((volatile uint32_t*)(DDR_BASE + 0xF28))
#define DDR_DEBUG_12 ((volatile uint32_t*)(DDR_BASE + 0xF2C))
#define DDR_DEBUG_13 ((volatile uint32_t*)(DDR_BASE + 0xF30))
#define DDR_DEBUG_14 ((volatile uint32_t*)(DDR_BASE + 0xF34))
#define DDR_DEBUG_19 ((volatile uint32_t*)(DDR_BASE + 0xF48))
#define DDR_DEBUG_29 ((volatile uint32_t*)(DDR_BASE + 0xF70))
#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */
#define DDR_SDRAM_CFG_ECC_EN 0x20000000
#define DDR_SDRAM_CFG_32_BE 0x00080000
#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
#define DDR_SDRAM_CFG_HSE 0x00000008
#define DDR_SDRAM_CFG_BI 0x00000001 /* Bypass initialization */
#define DDR_SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define DDR_SDRAM_CFG_SDRAM_TYPE(n) (((n) & 0x7) << 24)
#define DDR_SDRAM_TYPE_DDR4 5
#define DDR_SDRAM_INTERVAL_BSTOPRE 0x3FFF
/* CPLD (APU) */
#define CPLD_BASE 0xFFDF0000
#define CPLD_BASE_PHYS_HIGH 0xFULL
/* CPLD (MPU) */
#define CPLD_MPU_BASE 0xFFCF0000
#define CPLD_MPU_BASE_PHYS_HIGH 0xFULL
#define BOARD_ID_L_ADDR 0x0002
#define BOARD_ID_H_ADDR 0x0004
#define PLD_VER_ADDR 0x0006
#define POWER_STATUS_ADDRR 0x0400
#define MPU_INT_STATUS_ADDR 0x0402
#define MPU_INT_ENABLE_ADDR 0x0404
#define MPU_CONTROL_ADDR 0x0430
#define MPU_RESET_ADDR 0x0432
#define PCI_STATUS_ADDR 0x0434
#define HS_CSR_ADDR 0x1040
#define CPCI_GA_ADDRS 0x1042
#define CPCI_INTX_ADDR 0x1044
#define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_OVERRIDE 0x40
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
#define CPLD_PCIE_SGMII_MUX 0x80
#define CPLD_OVERRIDE_BOOT_EN 0x01
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
#define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + (n)))
#define CPLD_READ(reg) get16(CPLD_DATA(reg))
#define CPLD_WRITE(reg, value) set16(CPLD_DATA(reg), value)
/* MRAM */
#define MRAM_BASE 0xFF800000
#define MRAM_BASE_PHYS_HIGH 0xFULL
/* eSDHC */
#define ESDHC_BASE (CCSRBAR + 0x114000)
/* eSPI */
#define ESPI_MAX_CS_NUM 4
#define ESPI_MAX_RX_LEN (1 << 16)
#define ESPI_FIFO_WORD 4
#define ESPI_BASE (CCSRBAR + 0x110000)
#define ESPI_SPMODE ((volatile uint32_t*)(ESPI_BASE + 0x00)) /* controls eSPI general operation mode */
#define ESPI_SPIE ((volatile uint32_t*)(ESPI_BASE + 0x04)) /* controls interrupts and report events */
#define ESPI_SPIM ((volatile uint32_t*)(ESPI_BASE + 0x08)) /* enables/masks interrupts */
#define ESPI_SPCOM ((volatile uint32_t*)(ESPI_BASE + 0x0C)) /* command frame information */
#define ESPI_SPITF ((volatile uint32_t*)(ESPI_BASE + 0x10)) /* transmit FIFO access register (32-bit) */
#define ESPI_SPIRF ((volatile uint32_t*)(ESPI_BASE + 0x14)) /* read-only receive data register (32-bit) */
#define ESPI_SPITF8 ((volatile uint8_t*)( ESPI_BASE + 0x10)) /* transmit FIFO access register (8-bit) */
#define ESPI_SPIRF8 ((volatile uint8_t*)( ESPI_BASE + 0x14)) /* read-only receive data register (8-bit) */
#define ESPI_SPCSMODE(x) ((volatile uint32_t*)(ESPI_BASE + 0x20 + ((cs) * 4))) /* controls master operation with chip select 0-3 */
#define ESPI_SPMODE_EN (0x80000000) /* Enable eSPI */
#define ESPI_SPMODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold (1-32) */
#define ESPI_SPMODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold (0-31) */
#define ESPI_SPCOM_CS(x) ((x) << 30) /* Chip select-chip select for which transaction is destined */
#define ESPI_SPCOM_RXSKIP(x) ((x) << 16) /* Number of characters skipped for reception from frame start */
#define ESPI_SPCOM_TRANLEN(x) (((x) - 1) << 0) /* Transaction length */
#define ESPI_SPIE_TXE (1 << 15) /* transmit empty */
#define ESPI_SPIE_DON (1 << 14) /* Last character was transmitted */
#define ESPI_SPIE_RXT (1 << 13) /* Rx FIFO has more than RXTHR bytes */
#define ESPI_SPIE_RNE (1 << 9) /* receive not empty */
#define ESPI_SPIE_TNF (1 << 8) /* transmit not full */
#define ESPI_SPIE_RXCNT(n) (((n) >> 24) & 0x3F) /* The current number of full Rx FIFO bytes */
#define ESPI_CSMODE_CI 0x80000000 /* Inactive high */