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No sadly this isn't possible with the 28 pin variant. The primary reason is that the image sel pins are not 5V tolerant on this board, because the RP2350A doesn't have enough GPIOs. It might be possible to lay out a version of the 28 pin board with the RP2350B - this gives 14 more 5V tolerant GPIOs and could therefore support this function, but it would be an awfully tight squeeze. (It would be possible to support if you have an externa logic level shifter to convert from 5V CS to 3.3V CS. This would require some firmware mods to support.) |
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An obvious follow on question is whether this is possible with the 32 and 40 pin versions, as they use the RP2350B. The answer is still no, but for a different reason. For this capability to work, the CS line is used internally as another address pin, meaning a larger ROM table is looked up in RAM for each byte served. The 40 pin already maxes out use of the RP2350's SRAM (as it is a 0.5MB ROM), so there is no possibility to use another address line. The 32 pin, even though it may be serving a smaller image (27C010 and 27C020) doesn't have any spare address lines, due to the fact that it also supports the 27C301, which has a different pin layout. Hence I've used its extra address lines for other purposes. |
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Thanks a lot for these very informative answers! I saw your recent video on RAM support which was very cool too. If someone would succeed in squeezing an RP2350B into the 28-package, would it then also in theory be possible to emulate RAM by attaching the WR signal, at the same time as ROM emulation? |
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Now with the updated 28-pin (wow!) it seems the WR pin idea to get RAM and bank switching could be a reality? I just ordered a 28 and 24 variant from you so will hopefully be able try something when I receive it. |
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I haven't thought specifically about the RAM and combined ROM/RAM yet, but the X pin positioning on the GPIOs is hopefully compatible. The X pins are muiltiplexed to two pairs of GPIOs - so they are both contiguous with the CS lines and the address lines. This should give the ultimate in flexibility. They are called CX1 & 2 in the schematic 
Your ROMs shipped this morning, so hopefully will be with you soon! |
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Just received the chips, looks great - thanks! What I'm considering to add now is to connect the /WR line to X1 and then by writing to a specific address in the ROM space, swap out some region of the address space to either ROM banks or RAM. Any pointer to an existing piece of code in the repo that could point me in the right direction to implement it? |
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There's two distinct pieces here: Best place to start on 1 might be the current RAM support - sdrr/src/piodma/pioram.c. |
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Thanks a lot, I will dive into it! |
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"The primary reason is that the image sel pins are not 5V tolerant on this board, because the RP2350A doesn't have enough GPIOs." |
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Hi!
First of all, congratulations on a really cool project! Will order some units very soon :)
I've been trying to read info in the docs and schematics but I'm so far a bit uncertain about the "multi-ROM" and/or "multi-chip-select" capabilities of the 28-pin variant. I have some systems running 27128 and some running 2764 where it could be useful to host several sockets with one One ROM, and let the second slot use another chip select. The docs and schematics indicates X1/X2 is only supported on (what I can see) the 24-pin version. Would it be possible to utilise the SEL_A or SEL_B as a "second CS" on the 28-pin version?
/T
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