diff --git a/README.md b/README.md index 19ebbadacd..df7c9c9161 100644 --- a/README.md +++ b/README.md @@ -1,236 +1,160 @@ -# Template for Capstone -이 레파지토리는 학생들이 캡스톤 프로젝트 결과물을 위한 레파지토리 생성시에 참고할 내용들을 담고 있습니다. -1. 레파지토리 생성 -2. 레파지토리 구성 -3. 레파지토리 제출 -4. README.md 가이드라인 -5. README.md 작성팁 - ---- - -## 1. 레파지토리 생성 -- [https://classroom.github.com/a/nRcUn8vA](https://classroom.github.com/a/nRcUn8vA) -- 위 Github Classroom 링크에 접속해 본인 조의 github 레파지토리를 생성하세요. - -깃헙 클래스룸 레포 생성 - -- 레포지토리 생성 시 팀명은 `TEAM-{조 번호}` 형식으로 생성하세요. -- 예를 들어, 2025년도 3조의 팀명은 `TEAM-03` 입니다. -- 이 경우 `Capstone2025-team-03`이란 이름으로 레파지토리가 생성됩니다. - ---- - -## 2. 레파지토리 구성 -- 레파지토리 내에 README.md 파일 생성하고 아래의 가이드라인과 작성팁을 참고하여 README.md 파일을 작성하세요. (이 레파지토리의 SAMPLE_README.md 참조) -- 레파지토리 내에 docs 디렉토리를 생성하고 docs 디렉토리 내에는 과제 수행 하면서 작성한 각종 보고서, 발표자료를 올려둡니다. (이 레파지토리의 docs 디렉토리 참조) -- 그 밖에 레파지토리의 폴더 구성은 과제 결과물에 따라 자유롭게 구성하되 가급적 코드의 목적이나 기능에 따라 디렉토리를 나누어 구성하세요. - ---- - -## 3. 레파지토리 제출 - -- **`[주의]` 레파지토리 제출**은 해당 레파지토리의 ownership을 **학과 계정**으로 넘기는 것이므로 되돌릴 수 없습니다. -- **레파지토리 제출** 전, 더 이상 수정 사항이 없는지 다시 한번 확인하세요. -- github 레파지토리에서 Settings > General > Danger zone > Transfer 클릭 - 소유주 변경 경로 - -- [ Specify an organization or username ]에 'PNUCSE'를 입력하고 확인 메세지를 입력하세요. - 소유주 변경 - ---- - -## 4. README.md 가이드 라인 -- README 파일 작성시에 아래의 5가지 항목의 내용은 필수적으로 포함해야 합니다. -- 아래의 항목이외에 프로젝트의 이해를 돕기 위한 내용을 추가해도 됩니다. -- SAMPLE_README.md 이 단순한 형태의 예제이니 참고하세요. - -```markdown ### 1. 프로젝트 배경 #### 1.1. 국내외 시장 현황 및 문제점 -> 시장 조사 및 기존 문제점 서술 +SSD(Solid-State Drive)는 빠른 입출력 속도와 낮은 지연 시간 덕분에 주요 저장 장치로 자리 잡았다. 그러나 데이터를 덮어쓸 수 없으며, 읽기와 쓰기는 페이지(page) 단위로 이루어지지만, 삭제는 이보다 훨씬 큰 블록(block) 단위로만 가능하다는 점이 문제점이다. 이로 인해 SSD는 기존의 데이터를 무효화하고 새로운 데이터를 다른 공간에 쓰는 방식으로 쓰기 작업을 수행하는데 이 과정이 반복되면 유효하지 않은 데이터가 누적되고, 결국 가비지 컬렉션(Garbage Collection, GC)이라는 정리 작업을 통해 유효한 데이터를 다른 블록으로 옮기는 추가적인 쓰기가 발생한다. +이러한 가비지 컬렉션 과정에서 발생하는 추가적인 쓰기 작업은 **쓰기 증폭** 현상을 유발하며 이로 인해 SSD의 수명을 단축시키게 되는 문제점을 발생시키는데, 기존의 FTL은 사전에 정의된 정적인 정책을 따르기 때문에 이러한 문제를 해결하기 어렵다. #### 1.2. 필요성과 기대효과 -> 왜 이 프로젝트가 필요한지, 기대되는 효과 등 +딥러닝 기술을 도입하여 입출력 워크로드의 패턴을 분석하고, 딥러닝 모델을 활용해 데이터의 Hotness(갱신 빈도)를 예측한다. 이렇게 예측된 Hotness 레이블을 temperature로 정의해 first-touch 태깅과 온도 풀 분리, 동일 풀 우선 GC 복사를 적용하면 Hot/Cold 혼입이 줄어들고, FTL이 데이터를 블록별로 분리 저장하는 동적 정책을 구현함으로써, 가비지 컬렉션 시 유효 페이지를 옮기는 횟수를 최소화하여 **쓰기 증폭** 문제를 완화시킬 수 있다. + +--- ### 2. 개발 목표 #### 2.1. 목표 및 세부 내용 -> 전체적인 개발 목표, 주요 기능 및 기획 내용 +딥러닝을 활용하여 SSD의 Hotness 기반 FTL 정책을 제안하고 검증하는 것이 목표다. 페이지별 입출력 트레이스를 생성하는 데이터 전처리 과정을 거친 뒤, 이 정보를 통해 페이지 정보 해시 테이블을 구축하여 각 페이지의 접근 패턴에 대한 통계 정보를 누적한다. 통계 정보는 K-means 클러스터링을 통해 Hotness 레이블을 생성하는 데 사용되며, 동시에 Stacked-LSTM 모델의 입력 데이터가 되어 페이지 접근 패턴의 시계열적 특성을 학습한다. 학습이 완료된 모델은 오프라인 레이블링을 통해 전체 트레이스에 Hotness 예측 레이블을 추가하여 시뮬레이션에 사용될 Hotness 이 추가된 트레이스를 생성한다. 최종적으로, SimpleSSD-SA 시뮬레이터를 사용하여 Hotness를 고려하지 않는 기존 FTL 정책과 제안된 Hotness 기반 FTL 정책의 성능을 비교 분석한다. +#### 2.2. 기존 서비스 대비 차별성 +FTL에서 블록을 첫 쓰기 시점에 온도로 태깅하고 가득 찰 때까지 동일 온도만 수용하며, GC 시에도 같은 온도 풀의 오픈 블록으로 우선 복사하여 혼입을 구조적으로 최소화한다. 이는 단순 페이지 매핑 대비 불필요한 유효 페이지 복사를 줄여 내부 WAF·지연을 낮추는 점에서 차별화된다. +#### 2.3. 사회적 가치 도입 계획 +정책의 핵심 목표가 WAF와 지연의 감소이므로, 동일 자원에서의 효율 향상과 수명 연장을 기대할 수 있다. -#### 2.2. 기존 서비스 대비 차별성 -> 유사 서비스 비교 및 차별점 부각 +--- -#### 2.3. 사회적 가치 도입 계획 -> 프로젝트의 공공성, 지속 가능성, 환경 보호 등 ### 3. 시스템 설계 #### 3.1. 시스템 구성도 -> 이미지 혹은 텍스트로 시스템 아키텍쳐 작성 -> +KakaoTalk_Photo_2025-09-23-20-29-50 + + #### 3.2. 사용 기술 -> 프론트엔드, 백엔드, API 등 구체 기술 스택 +- **시뮬레이션**: C++17, CMake, SimpleSSD‑Standalone v2.0 +- **ML**: Python, PyTorch, Scikit-learn, NumPy, Pandas +- **데이터**: SNIA IOTTA YCSB 블록 트레이스 + +--- ### 4. 개발 결과 #### 4.1. 전체 시스템 흐름도 -> 기능 흐름 설명 및 도식화 가능 -> +전처리·페이지화 → 학습 데이터 생성 → 모델 학습·검증 → 오프라인 레이블링 → 시뮬레이션 환경 구성 → 결과 분석 + #### 4.2. 기능 설명 및 주요 기능 명세서 -> 주요 기능에 대한 상세 설명, 각 기능의 입력/출력 및 설명 -> +- 레이블 정규화·풀 선택: 요청 temperature를 정규화해(0~3) 해당 풀에서 블록을 선택하고 태깅한다. +- FTL 배치: 첫 쓰기 순간 블록 태깅, 같은 온도만 채운다. +- 일관 GC: 유효 서브페이지는 같은 온도 풀의 오픈 블록으로 우선 복사하여 혼입을 억제한다. +- 메트릭: Internal WAF = `device_write_bytes / host_write_bytes_at_FTL`, GC 복사 서브페이지, 지연, IOPS 등 + #### 4.3. 디렉토리 구조 -> +``` +. +├─ docs/ # 보고서/포스터/발표자료 +├─ scripts/ # 전처리·학습·레이블·재현 스크립트 +├─ SSD-WAF-Analysis-Capstone-2025-main/ #WAF 산출 코드를 추가한 기존 SimpleSSD-Standalone +└─ hotness/SimpleSSD-Standalone/ #hotness 라벨이 붙은 trace로 시뮬레이션 하기 위해 수정된 SimpleSSD-Standalone +``` + #### 4.4. 산업체 멘토링 의견 및 반영 사항 -> 멘토 피드백과 적용한 사례 정리 +- **WAF 외 성능 지표 제시**:평균 응답 시간(Latency)이 98.2% 단축되었음을 확인함으로써 쓰기 지연 시간 개선또한 명확히 입증했다. +- **GC Victim 블록 선택 방식의 차별성**:GC 횟수의 비교로 Victim 블록 선택 전략이 근본적으로 다르게 동작했음을 증명했다. +- **Wear-Leveling**:본 연구에서는 별도의 동적 Wear-Leveling 알고리즘의 구현을 포함하지 않기 때문에 장기적인 관점에서는 마모 불균형이 심화될 수 있는 한계가 있기에 향후 연구 과제로 현재의 Hot/Cold 분리 정책을 기반으로 블록 간 마모도 편차도 고려하는 알고리즘에 대한 연구가 가능할 것이다. + +--- ### 5. 설치 및 실행 방법 -> #### 5.1. 설치절차 및 실행 방법 -> 설치 명령어 및 준비 사항, 실행 명령어, 포트 정보 등 -#### 5.2. 오류 발생 시 해결 방법 -> 선택 사항, 자주 발생하는 오류 및 해결책 등 -### 6. 소개 자료 및 시연 영상 -#### 6.1. 프로젝트 소개 자료 -> PPT 등 -#### 6.2. 시연 영상 -> 영상 링크 또는 주요 장면 설명 - -### 7. 팀 구성 -#### 7.1. 팀원별 소개 및 역할 분담 -> -#### 7.2. 팀원 별 참여 후기 -> 개별적으로 느낀 점, 협업, 기술적 어려움 극복 사례 등 - -### 8. 참고 문헌 및 출처 +이 프로젝트는 SimpleSSD-SA 시뮬레이터와 딥러닝 모델을 활용한 복합 시스템이므로, 시뮬레이터와 Python/ML 환경을 모두 설정해야 한다. 다음은 전체 워크플로우를 단계별로 안내한다. + +1. **Python 환경 설정** + * Python 3.x가 설치되어 있는지 확인한다. + * `scripts/` 디렉터리에 있는 Python 스크립트 실행에 필요한 라이브러리를 설치한다. + ```bash + pip install torch numpy scikit-learn pandas matplotlib seaborn tqdm + ``` + +2. **데이터 전처리 및 모델 학습** + * `scripts/` 디렉터리의 파이썬 스크립트를 순서대로 실행하여 데이터를 전처리하고 모델을 학습한다. + * 원본 트레이스(`ycsb_to_simplessd.py`)를 SimpleSSD-SA 형식으로 변환하고, 페이지 단위로 분할(`simplessd_page_split.py`)한다. + * 분할된 트레이스로 LSTM 모델 학습 데이터셋(`lstm_data_gen.py`)을 생성한다. + ```bash + # 예시: ycsb_trace.txt를 입력으로 사용 + python scripts/ycsb_to_simplessd.py ycsb_trace.txt data/simplessd_trace.csv + python scripts/simplessd_page_split.py data/simplessd_trace.csv data/simplessd_page_split.csv + python scripts/lstm_data_gen.py --input_file data/simplessd_page_split.csv --output_dir data/npy --log_name lstm_data_gen.log + ``` + +3. **모델 학습 및 오프라인 레이블링** + * `ML_model.py` 스크립트를 실행하여 LSTM 모델을 학습한다. 학습이 완료되면 모델 파일(`.pth`)이 `models/` 디렉터리에 저장된다. + * `offline_labeling.py` 스크립트를 실행하여 학습된 모델과 스케일러를 이용, 최종 시뮬레이션에 사용될 Hotness 레이블이 추가된 트레이스 파일을 생성한다. + ```bash + # lstm_data_gen.py로 생성된 파일 경로를 인자로 사용 + python scripts/ML_model.py --x_path data/npy/X_simplessd_page_split.npy --y_path data/npy/y_simplessd_page_split.npy --model_name hotness_model --log_name hotness_model.log + + # 학습된 모델과 스케일러 파일을 사용 + python scripts/offline_labeling.py data/simplessd_page_split.csv models/hotness_model.pth --scaler_file data/npy/scaler_simplessd_page_split.pkl results/labeled_trace.csv + ``` +--- +설치 +```bash +git clone git@github.com:simplessd/simplessd-standalone +cd simplessd-standalone +git submodule update --init --recursive ``` -## 5. README.md 작성팁 -* 마크다운 언어를 이용해 README.md 파일을 작성할 때 참고할 수 있는 마크다운 언어 문법을 공유합니다. -* 다양한 예제와 보다 자세한 문법은 [이 문서](https://www.markdownguide.org/basic-syntax/)를 참고하세요. - -### 5.1. 헤더 Header +시뮬레이터 빌드 (mac 사용) +```bash +mkdir build && cd build +cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo .. +make -j"$(sysctl -n hw.ncpu)" ``` -# This is a Header 1 -## This is a Header 2 -### This is a Header 3 -#### This is a Header 4 -##### This is a Header 5 -###### This is a Header 6 -####### This is a Header 7 은 지원되지 않습니다. -``` -
-### 5.2. 인용문 BlockQuote -``` -> This is a first blockqute. -> > This is a second blockqute. -> > > This is a third blockqute. -``` -> This is a first blockqute. -> > This is a second blockqute. -> > > This is a third blockqute. -
+실험 파라미터 설정
+시뮬레이션의 config 파일과 simple-ssd의 config 파라미터를 설정해 실험할 수 있다. -### 5.3. 목록 List -* **Ordered List** -``` -1. first -2. second -3. third +실행 (mac 사용) +```bash +mkdir results +./simplessd-standalone \ + ../config/sample.cfg \ + ../simplessd/config/sample.cfg \ + results ``` -1. first -2. second -3. third -
-* **Unordered List** -``` -* 하나 - * 둘 +--- -+ 하나 - + 둘 +### 6. 소개 및 시연 영상 +[![시연 영상](https://img.youtube.com/vi/uA37RvXBMUM/0.jpg)](https://www.youtube.com/watch?v=uA37RvXBMUM) -- 하나 - - 둘 -``` -* 하나 - * 둘 +--- -+ 하나 - + 둘 +### 7. 팀 구성 +#### 7.1. 팀원별 소개 및 역할 분담 +- 201924544 이준형 — 데이터 전처리, 입출력 패턴 코드 분석, 모델 개발 +- 201914502 강인석 — 시뮬레이션 환경 구축 및 설정, 성능 측정(WAF), Hotness 레벨 트레이스용 FTL 정책 개선, 성능 비교 +- 202155537 김지수 — 시뮬레이션 환경 구축 및 설정, FTL 개선 정책 구현, 성능 측정, 기존 FTL VS 딥러닝 기반 FTL 비교 +- 지도교수 안성용 — 전체 연구 지도 -- 하나 - - 둘 -
+#### 7.2. 팀원 별 참여 후기 -### 5.4. 코드 CodeBlock -* 코드 블럭 이용 '``' -``` -여러줄 주석 "```" 이용 -"``` -#include -int main(void){ - printf("Hello world!"); - return 0; -} -```" - -단어 주석 "`" 이용 -"`Hello world`" - -* 큰 따움표(") 없이 사용하세요. -``` -
- -### 5.5. 링크 Link -``` -[Title](link) -[부산대학교 정보컴퓨터공학부](https://cse.pusan.ac.kr/cse/index..do) +- **201924544 이준형** - 프로젝트에서 데이터 전처리, 입출력 패턴 분석, 그리고 모델 개발을 담당했습니다. YCSB 블록 트레이스를 SimpleSSD-SA 시뮬레이터에 맞게 변환하고 페이지 단위로 데이터를 분할하는 작업부터 시작했습니다. 페이지별 접근 패턴을 기반으로 통계적 특성을 추출하고, 이를 활용해 Stacked-LSTM 모델을 설계하는 과정은 기억에 남는 경험입니다. - - -``` -[부산대학교 정보컴퓨터공학부](https://cse.pusan.ac.kr/cse/index..do) + 특히 시뮬레이션 환경 구축을 담당한 팀원들과 긴밀히 소통하며, 모델의 예측 결과가 FTL 정책에 어떻게 적용될지 논의했던 것이 큰 도움이 되었습니다. 단순히 모델의 정확도를 높이는 것을 넘어, 실제 시스템에 적용했을 때의 효과를 고려하는 시각을 가질 수 있었기 때문입니다. 이 기술이 SSD의 쓰기 증폭 문제를 해결하는 데 기여할 수 있다는 것을 확인했을 때 큰 보람을 느꼈습니다. - -
+ 이번 프로젝트는 저에게 기술적인 지식뿐만 아니라, 팀원들과의 유기적인 협업을 통해 시너지를 창출하는 소중한 경험을 안겨주었습니다. -### 5.6. 강조 Highlighting -``` -*single asterisks* -_single underscores_ -**double asterisks** -__double underscores__ -~~cancelline~~ -``` -*single asterisks*
-_single underscores_
-**double asterisks**
-__double underscores__
-~~cancelline~~
-
- -### 5.7. 이미지 Image -``` -Alt text -![Alt text](image URL "Optional title") -``` -- 웹에서 작성한다면 README.md 내용 안으로 이미지를 드래그 앤 드롭하면 이미지가 생성됩니다. -- 웹이 아닌 로컬에서 작성한다면, github issue에 이미지를 드래그 앤 드롭하여 image url 을 얻을 수 있습니다. (URL만 복사하고 issue는 제출 안 함.) - 이슈에 image 올림 - image url 복사 +- **201914502 강인석** - 이번 캡스톤 프로젝트를 통해 단순히 코드를 구현하는 수준을 넘어, 저장장치 아키텍처의 근본적인 문제를 실험적으로 분석하고 해결책을 모색하는 과정을 직접 경험할 수 있었습니다. 특히 FTL 정책 개선과 시뮬레이션 환경 구축을 담당하면서, 논문으로만 접하던 쓰기 증폭(Write Amplification) 문제가 실제 실험 환경에서 어떤 수치와 현상으로 나타나는지 확인할 수 있었던 것이 가장 인상 깊었습니다. 단순히 WAF 지표 하나에 머무르지 않고 지연(Latency), IOPS 등 다양한 메트릭을 종합적으로 살펴보며, 제안한 Hotness 기반 정책이 구조적으로 어떤 차이를 만들어내는지 검증한 과정은 큰 배움이 되었습니다. + 또한 팀 단위 협업 속에서 데이터 전처리, 모델 학습, 시뮬레이션, 분석이 서로 긴밀히 연결되어야 한다는 점을 몸소 느꼈습니다. 혼자였다면 끝내기 어려웠을 프로젝트를 동료들과 역할을 분담하고, 문제를 공유하고, 해결책을 함께 찾으면서 완성할 수 있었다는 점에서 큰 보람을 얻었습니다. -### 5.8. 유튜브 영상 추가 -```markdown -[![영상 이름](유튜브 영상 썸네일 URL)](유튜브 영상 URL) -[![부산대학교 정보컴퓨터공학부 소개](http://img.youtube.com/vi/zh_gQ_lmLqE/0.jpg)](https://www.youtube.com/watch?v=zh_gQ_lmLqE) -``` -[![부산대학교 정보컴퓨터공학부 소개](http://img.youtube.com/vi/zh_gQ_lmLqE/0.jpg)](https://www.youtube.com/watch?v=zh_gQ_lmLqE) + 무엇보다 이번 경험은 단순한 과제 수행이 아니라, 실제 산업 현장의 비효율을 개선할 수 있는 실질적인 도구를 만들 수 있다는 가능성을 보여주었습니다. 앞으로도 이번 프로젝트에서 얻은 통찰을 토대로, 학문적 연구뿐만 아니라 실제 서비스와 기술 발전에 기여할 수 있는 개발자로 성장하고 싶습니다. -- 이때 유튜브 영상 썸네일 URL은 유투브 영상 URL로부터 다음과 같이 얻을 수 있습니다. +- **202155537 김지수** - 이번 프로젝트에서 저는 시뮬레이션 환경 구축 및 설정, FTL 개선 정책 구현을 주로 담당했습니다. 처음에는 시뮬레이터 환경을 세팅하는 과정에서 여러 오류와 세부 설정 문제로 어려움이 있었지만, 이를 해결하면서 전체적인 SSD 시뮬레이션 구조와 동작 원리에 대해 더 깊이 이해할 수 있었습니다. 전체적으로 프로젝트를 하면서 각자 맡은 부분에 대해 자연스럽게 소통하고 정보를 주고받으며 팀으로서 시너지를 내는 경험이 매우 인상적이었습니다. 혼자서는 얻기 어려운 다양한 시각과 조언을 접할 수 있었던 것이 큰 배움이었습니다. +--- -- `Youtube URL`: https://www.youtube.com/watch?v={동영상 ID} -- `Youtube Thumbnail URL`: http://img.youtube.com/vi/{동영상 ID}/0.jpg -- 예를 들어, https://www.youtube.com/watch?v=zh_gQ_lmLqE 라고 하면 썸네일의 주소는 http://img.youtube.com/vi/zh_gQ_lmLqE/0.jpg 이다. + +### 8. 참고 문헌 및 출처 +- [SimpleSSD‑Standalone(시뮬레이터)](https://docs.simplessd.org/en/v2.0.12/) +- [YCSB 트레이스](https://iotta.snia.org) +- [PyTorch](https://pytorch.org) +- [deep learning with LSTM networks](https://developer.ibm.com/learningpaths/iot-anomaly-detection-deep-learning/intro-deep-learning-lstm-networks/) +- AGRAWAL, N., et al. "Design Tradeoffs for SSD Performance," Proc. of the 2008 USENIX Annual Technical Conference, pp. 1-14, Jun. 2008. +- YUNE, S. J.,"A Study on Improving SSD Write Amplification through Machine Learning-based Hot/Cold Page Classification," Master's Thesis, Pusan National University, Busan, 2024. +--- diff --git a/SAMPLE_README.md b/SAMPLE_README.md deleted file mode 100644 index f7f1ea25e0..0000000000 --- a/SAMPLE_README.md +++ /dev/null @@ -1,31 +0,0 @@ -### 1. 프로젝트 소개 - -이 프로젝트는 졸업과제를 수행하는 학생들에게 README 작성의 가이드라인을 제공하기 위해 제작되었습니다. - -### 2. 팀소개 - -Tony Stark, ironman@marvel.com, 개발총괄 - -Peter Benjamin Parker, spiderman@marvel.com, 알고리즘 설계 - -Stephen Vincent Strange, doctorstrange@marvel.com, 백앤드 개발 - -Robert Bruce Banner, hulk@marvel.com, 프론트엔드 개발 - -### 3. 시스템 구성도 - -부산대학교 일반대학원 정보융합공학과는 컴퓨터공학전공, AI전공, 의생명융합전공이 있습니다. - -![정보융합공학과 이미지](https://user-images.githubusercontent.com/100384365/192478661-5dc79a18-b076-48ef-b842-bcf65b0d8d44.jpg) - -### 4. 소개 및 시연 영상 - -[![부산대학교 정보컴퓨터공학부 소개](http://img.youtube.com/vi/zh_gQ_lmLqE/0.jpg)](https://youtu.be/zh_gQ_lmLqE) - -### 5. 설치 및 사용법 - -본 프로젝트는 Ubuntu 20.04 버전에서 개발되었으며 함께 포함된 다음의 스크립트를 수행하여 -관련 패키지들의 설치와 빌드를 수행할 수 있습니다. -``` -$ ./install_and_build.sh -``` diff --git a/SSD-WAF-Analysis-Capstone-2025-main/.clang-format b/SSD-WAF-Analysis-Capstone-2025-main/.clang-format new file mode 100644 index 0000000000..38a9d1af6b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/.clang-format @@ -0,0 +1,27 @@ +# Generated by clang-format v5.0.0 +--- +Language: Cpp +BasedOnStyle: Google +AllowShortFunctionsOnASingleLine: Inline +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakBeforeMultilineStrings: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + BeforeCatch: true + BeforeElse: true + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBraces: Custom +DerivePointerAlignment: false +PointerAlignment: Right +... diff --git a/SSD-WAF-Analysis-Capstone-2025-main/.github/ISSUE_TEMPLATE/bug_report.md b/SSD-WAF-Analysis-Capstone-2025-main/.github/ISSUE_TEMPLATE/bug_report.md new file mode 100644 index 0000000000..90db8e42c4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/.github/ISSUE_TEMPLATE/bug_report.md @@ -0,0 +1,30 @@ +--- +name: Bug report +about: Create a report to help us improve +title: '' +labels: '' +assignees: '' + +--- + +### Describe the bug +A clear and concise description of what the bug is. + +### To Reproduce +Steps to reproduce the behavior: +1. Go to '...' +2. Click on '....' +3. Scroll down to '....' +4. See error + +### Expected behavior +A clear and concise description of what you expected to happen. + +### Screenshots +If applicable, add screenshots to help explain your problem. + +### Running Environment (please complete the following information): + - Host OS and Kernel version: [e.g. Ubuntu 16.04 with Linux 4.14] + - Compiler version used to build SimpleSSD-Standalone: [e.g. GCC 5.3.1] + - SimpleSSD-Standalone version: [e.g. v2.0-rc4 - or commit hash] + - SimpleSSD version: [e.g. v2.0.6 - or commit hash] diff --git a/SSD-WAF-Analysis-Capstone-2025-main/.github/ISSUE_TEMPLATE/question.md b/SSD-WAF-Analysis-Capstone-2025-main/.github/ISSUE_TEMPLATE/question.md new file mode 100644 index 0000000000..0c86926b28 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/.github/ISSUE_TEMPLATE/question.md @@ -0,0 +1,21 @@ +--- +name: Question +about: Use this format for asking question +title: '' +labels: '' +assignees: '' + +--- + +### Running Environment (please complete the following information): + - Host OS and Kernel version: [e.g. Ubuntu 16.04 with Linux 4.14] + - Compiler version used to build SimpleSSD-Standalone: [e.g. GCC 5.3.1] + - SimpleSSD-Standalone version: [e.g. v2.0-rc4 - or commit hash] + - SimpleSSD version: [e.g. v2.0.6 - or commit hash] + +### Execution information +- Standalone configuration file: +[e.g. TimingMode = 1 ...] + +### Explain what you want to ask here: +A clear explanation of your question. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/.gitignore b/SSD-WAF-Analysis-Capstone-2025-main/.gitignore new file mode 100644 index 0000000000..8083283edc --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/.gitignore @@ -0,0 +1,28 @@ +# Exclude traces folder as requested +traces/ + +# Build artifacts +*.o +*.a +simplessd-standalone + +# OS generated files +.DS_Store +.DS_Store? +._* +.Spotlight-V100 +.Trashes +ehthumbs.db +Thumbs.db + +# IDE files +.vscode/ +.idea/ +*.swp +*.swo + +# Log files +*.log + +# Result files (optional - can be uncommented if needed) +# result/ \ No newline at end of file diff --git a/SSD-WAF-Analysis-Capstone-2025-main/.gitmodules b/SSD-WAF-Analysis-Capstone-2025-main/.gitmodules new file mode 100644 index 0000000000..45dba65122 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/.gitmodules @@ -0,0 +1,3 @@ +[submodule "simplessd"] + path = simplessd + url = git@github.com:simplessd/simplessd diff --git a/SSD-WAF-Analysis-Capstone-2025-main/CMakeCache.txt b/SSD-WAF-Analysis-Capstone-2025-main/CMakeCache.txt new file mode 100644 index 0000000000..1e0c93bebd --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/CMakeCache.txt @@ -0,0 +1,397 @@ +# This is the CMakeCache file. +# For build in directory: /Users/gagaga/Documents/newCapstone/simplessd-standalone +# It was generated by CMake: /opt/homebrew/bin/cmake +# You can edit this file to change values found and used by cmake. +# If you do not want to change any of the values, simply exit the editor. +# If you do want to change a value, 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+CMAKE_CXX_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG + +//Flags used by the CXX compiler during RELEASE builds. +CMAKE_CXX_FLAGS_RELEASE:STRING=-O3 -DNDEBUG + +//Flags used by the CXX compiler during RELWITHDEBINFO builds. +CMAKE_CXX_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG + +//C compiler +CMAKE_C_COMPILER:FILEPATH=/usr/bin/cc + +//Flags used by the C compiler during all build types. +CMAKE_C_FLAGS:STRING= + +//Flags used by the C compiler during DEBUG builds. +CMAKE_C_FLAGS_DEBUG:STRING=-g + +//Flags used by the C compiler during MINSIZEREL builds. +CMAKE_C_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG + +//Flags used by the C compiler during RELEASE builds. +CMAKE_C_FLAGS_RELEASE:STRING=-O3 -DNDEBUG + +//Flags used by the C compiler during RELWITHDEBINFO builds. +CMAKE_C_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG + +//Path to a program. +CMAKE_DLLTOOL:FILEPATH=CMAKE_DLLTOOL-NOTFOUND + +//Flags used by the linker during all build types. +CMAKE_EXE_LINKER_FLAGS:STRING= + +//Flags used by the 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define COMPILER_VERSION_INTERNAL DEC(__ti_version__) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__)) +# define COMPILER_ID "LCC" +# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100) +# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100) +# if defined(__LCC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__) +# endif +# if defined(__GNUC__) && defined(__GNUC_MINOR__) +# define SIMULATE_ID "GNU" +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# if 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+#if defined(__VERSIONNUM__) + /* __VERSIONNUM__ = 0xVVRRPPTT */ +# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF) +# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF) +# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF) +# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + +#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC) +# define COMPILER_ID "SDCC" +# if defined(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR) +# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH) +# else + /* SDCC = VRP */ +# define COMPILER_VERSION_MAJOR DEC(SDCC/100) +# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10) +# define COMPILER_VERSION_PATCH DEC(SDCC % 10) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +# elif defined(_ADI_COMPILER) +# define PLATFORM_ID "ADSP" + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__clang__) && defined(__ti__) +# if defined(__ARM_ARCH) +# define ARCHITECTURE_ID "ARM" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +# elif defined(__ADSPSHARC__) +# define ARCHITECTURE_ID "SHARC" + +# elif defined(__ADSPBLACKFIN__) +# define ARCHITECTURE_ID "Blackfin" + +#elif defined(__TASKING__) + +# if defined(__CTC__) || defined(__CPTC__) +# define ARCHITECTURE_ID "TriCore" + +# elif defined(__CMCS__) +# define ARCHITECTURE_ID "MCS" + +# elif defined(__CARM__) || defined(__CPARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__CARC__) +# define ARCHITECTURE_ID "ARC" + +# elif defined(__C51__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__CPCP__) +# define ARCHITECTURE_ID "PCP" + +# else +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#define C_STD_99 199901L +#define C_STD_11 201112L +#define C_STD_17 201710L +#define C_STD_23 202311L + +#ifdef __STDC_VERSION__ +# define C_STD __STDC_VERSION__ +#endif + +#if !defined(__STDC__) && !defined(__clang__) +# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__) +# define C_VERSION "90" +# else +# define C_VERSION +# endif +#elif C_STD > C_STD_17 +# define C_VERSION "23" +#elif C_STD > C_STD_11 +# define C_VERSION "17" +#elif C_STD > C_STD_99 +# define C_VERSION "11" +#elif C_STD >= C_STD_99 +# define C_VERSION "99" +#else +# define C_VERSION "90" +#endif +const char* info_language_standard_default = + "INFO" ":" "standard_default[" C_VERSION "]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +#ifdef ID_VOID_MAIN +void main() {} +#else +# if defined(__CLASSIC_C__) +int main(argc, argv) int argc; char *argv[]; +# else +int main(int argc, char* argv[]) +# endif +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; + require += info_arch[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#if defined(COMPILER_VERSION_INTERNAL) || defined(COMPILER_VERSION_INTERNAL_STR) + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; +} +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdC/a.out b/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdC/a.out new file mode 100755 index 0000000000..23affadac2 Binary files /dev/null and b/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdC/a.out differ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdC/apple-sdk.c b/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdC/apple-sdk.c new file mode 100644 index 0000000000..db846b4f5a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdC/apple-sdk.c @@ -0,0 +1 @@ +#include diff --git a/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdCXX/CMakeCXXCompilerId.cpp b/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdCXX/CMakeCXXCompilerId.cpp new file mode 100644 index 0000000000..94d431033a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/CMakeFiles/4.0.3/CompilerIdCXX/CMakeCXXCompilerId.cpp @@ -0,0 +1,920 @@ +/* This source file must have a .cpp extension so that all C++ compilers + recognize the extension without flags. Borland does not know .cxx for + example. */ +#ifndef __cplusplus +# error "A C compiler has been selected for C++." +#endif + +#if !defined(__has_include) +/* If the compiler does not have __has_include, pretend the answer is + always no. */ +# define __has_include(x) 0 +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# if defined(__GNUC__) +# define SIMULATE_ID "GNU" +# endif + /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later, + except that a few beta releases use the old format with V=2021. */ +# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111 +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE) + /* The third version component from --version is an update index, + but no macro is provided for it. */ +# define COMPILER_VERSION_PATCH DEC(0) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER) +# define COMPILER_ID "IntelLLVM" +#if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +#endif +#if defined(__GNUC__) +# define SIMULATE_ID "GNU" +#endif +/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and + * later. Look for 6 digit vs. 8 digit version number to decide encoding. + * VVVV is no smaller than the current year when a version is released. + */ +#if __INTEL_LLVM_COMPILER < 1000000L +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10) +#else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100) +#endif +#if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +#endif +#if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +#elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +#endif +#if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +#endif +#if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_CC) +# define COMPILER_ID "SunPro" +# if __SUNPRO_CC >= 0x5100 + /* __SUNPRO_CC = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# endif + +#elif defined(__HP_aCC) +# define COMPILER_ID "HP" + /* __HP_aCC = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_aCC % 100) + +#elif defined(__DECCXX) +# define COMPILER_ID "Compaq" + /* __DECCXX_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER % 10000) + +#elif defined(__IBMCPP__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__open_xl__) && defined(__clang__) +# define COMPILER_ID "IBMClang" +# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__) +# define COMPILER_VERSION_MINOR DEC(__open_xl_release__) +# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800 +# define COMPILER_ID "XL" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(__clang__) && defined(__cray__) +# define COMPILER_ID "CrayClang" +# define COMPILER_VERSION_MAJOR DEC(__cray_major__) +# define COMPILER_VERSION_MINOR DEC(__cray_minor__) +# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__TASKING__) +# define COMPILER_ID "Tasking" + # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000) + # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100) +# define COMPILER_VERSION_INTERNAL DEC(__VERSION__) + +#elif defined(__ORANGEC__) +# define COMPILER_ID "OrangeC" +# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__) + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100 % 100) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) && defined(__ti__) +# define COMPILER_ID "TIClang" + # define COMPILER_VERSION_MAJOR DEC(__ti_major__) + # define COMPILER_VERSION_MINOR DEC(__ti_minor__) + # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__) +# define COMPILER_VERSION_INTERNAL DEC(__ti_version__) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__)) +# define COMPILER_ID "LCC" +# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100) +# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100) +# if defined(__LCC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__) +# endif +# if defined(__GNUC__) && defined(__GNUC_MINOR__) +# define SIMULATE_ID "GNU" +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif +# endif + +#elif defined(__GNUC__) || defined(__GNUG__) +# define COMPILER_ID "GNU" +# if defined(__GNUC__) +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# else +# define COMPILER_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(_ADI_COMPILER) +# define COMPILER_ID "ADSP" +#if defined(__VERSIONNUM__) + /* __VERSIONNUM__ = 0xVVRRPPTT */ +# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF) +# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF) +# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF) +# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +# elif defined(_ADI_COMPILER) +# define PLATFORM_ID "ADSP" + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__clang__) && defined(__ti__) +# if defined(__ARM_ARCH) +# define ARCHITECTURE_ID "ARM" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +# elif defined(__ADSPSHARC__) +# define ARCHITECTURE_ID "SHARC" + +# elif defined(__ADSPBLACKFIN__) +# define ARCHITECTURE_ID "Blackfin" + +#elif defined(__TASKING__) + +# if defined(__CTC__) || defined(__CPTC__) +# define ARCHITECTURE_ID "TriCore" + +# elif defined(__CMCS__) +# define ARCHITECTURE_ID "MCS" + +# elif defined(__CARM__) || defined(__CPARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__CARC__) +# define ARCHITECTURE_ID "ARC" + +# elif defined(__C51__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__CPCP__) +# define ARCHITECTURE_ID "PCP" + +# else +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#define CXX_STD_98 199711L +#define CXX_STD_11 201103L +#define CXX_STD_14 201402L +#define CXX_STD_17 201703L +#define CXX_STD_20 202002L +#define CXX_STD_23 202302L + +#if defined(__INTEL_COMPILER) && defined(_MSVC_LANG) +# if _MSVC_LANG > CXX_STD_17 +# define CXX_STD _MSVC_LANG +# elif _MSVC_LANG == CXX_STD_17 && defined(__cpp_aggregate_paren_init) +# define CXX_STD CXX_STD_20 +# elif _MSVC_LANG > CXX_STD_14 && __cplusplus > CXX_STD_17 +# define CXX_STD CXX_STD_20 +# elif _MSVC_LANG > CXX_STD_14 +# define CXX_STD CXX_STD_17 +# elif defined(__INTEL_CXX11_MODE__) && defined(__cpp_aggregate_nsdmi) +# define CXX_STD CXX_STD_14 +# elif defined(__INTEL_CXX11_MODE__) +# define CXX_STD CXX_STD_11 +# else +# define CXX_STD CXX_STD_98 +# endif +#elif defined(_MSC_VER) && defined(_MSVC_LANG) +# if _MSVC_LANG > __cplusplus +# define CXX_STD _MSVC_LANG +# else +# define CXX_STD __cplusplus +# endif +#elif defined(__NVCOMPILER) +# if __cplusplus == CXX_STD_17 && defined(__cpp_aggregate_paren_init) +# define CXX_STD CXX_STD_20 +# else +# define CXX_STD __cplusplus +# endif +#elif defined(__INTEL_COMPILER) || defined(__PGI) +# if __cplusplus == CXX_STD_11 && defined(__cpp_namespace_attributes) +# define CXX_STD CXX_STD_17 +# elif __cplusplus == CXX_STD_11 && defined(__cpp_aggregate_nsdmi) +# define CXX_STD CXX_STD_14 +# else +# define CXX_STD __cplusplus +# endif +#elif (defined(__IBMCPP__) || defined(__ibmxl__)) && defined(__linux__) +# if __cplusplus == CXX_STD_11 && defined(__cpp_aggregate_nsdmi) +# define CXX_STD CXX_STD_14 +# else +# define CXX_STD __cplusplus +# endif +#elif __cplusplus == 1 && defined(__GXX_EXPERIMENTAL_CXX0X__) +# define CXX_STD CXX_STD_11 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/Applications/Xcode-beta.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/c++/v1/__functional/mem_fun_ref.h \ + /Applications/Xcode-beta.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/c++/v1/__functional/not_fn.h \ + /Applications/Xcode-beta.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/c++/v1/__functional/pointer_to_binary_function.h \ + /Applications/Xcode-beta.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/c++/v1/__functional/pointer_to_unary_function.h \ + /Applications/Xcode-beta.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/c++/v1/__functional/unary_negate.h diff --git a/SSD-WAF-Analysis-Capstone-2025-main/CMakeLists.txt b/SSD-WAF-Analysis-Capstone-2025-main/CMakeLists.txt new file mode 100644 index 0000000000..13fae4d6d0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/CMakeLists.txt @@ -0,0 +1,159 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# Set version and project name +cmake_minimum_required(VERSION 3.10) +project(simplessd-standalone) + +# Add options for debug build +option(DEBUG_BUILD "Build SimpleSSD-Standalone in debug mode." OFF) + +# Set DRAMPower path +set(DRAMPOWER_SOURCE_DIR + "${PROJECT_SOURCE_DIR}/lib/drampower/src" + CACHE PATH + "" + FORCE +) + +# Check SimpleSSD is valid +if (NOT EXISTS "${PROJECT_SOURCE_DIR}/simplessd/CMakeLists.txt") + message(FATAL_ERROR "Failed to find SimpleSSD. \ +Check you initialized submodules.") +endif () + +# Add subproject +add_subdirectory(${PROJECT_SOURCE_DIR}/simplessd + ${CMAKE_BINARY_DIR}/simplessd +) + +# Set include directories +include_directories( + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/simplessd + ${DRAMPOWER_SOURCE_DIR} +) + +# Platform specific settings +if (MSVC) + add_definitions(-D_CRT_SECURE_NO_WARNINGS) + add_compile_options(/wd4819) # Surpress unicode warning + add_compile_options(/wd4305) # Surpress truncation warning +else () + if (APPLE) + # macOS doesn't support -rdynamic flag + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS + "-O0 -g -pthread -Wall -Wextra ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS + "-O2 -pthread -Wall -Wextra ${CMAKE_CXX_FLAGS}") + endif () + else () + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS + "-O0 -g -rdynamic -pthread -Wall -Wextra -Werror ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS + "-O2 -rdynamic -pthread -Wall -Wextra -Werror ${CMAKE_CXX_FLAGS}") + endif () + endif () + + if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS "4.9") + message(FATAL_ERROR "GNU g++ < 4.9 does not support .\ +Please update your compiler.") + endif () + endif () +endif () + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Specify source files +set(SRC_BIL + bil/entry.cc + bil/noop_scheduler.cc +) +set(SRC_IGL_REQUEST + igl/request/request_config.cc + igl/request/request_generator.cc +) +set(SRC_IGL_TRACE + igl/trace/trace_config.cc + igl/trace/trace_replayer.cc +) +set(SRC_LIB_DRAMPOWER + lib/drampower/src/CAHelpers.cc + lib/drampower/src/CmdHandlers.cc + lib/drampower/src/CmdScheduler.cc + lib/drampower/src/CommandAnalysis.cc + lib/drampower/src/MemArchitectureSpec.cc + lib/drampower/src/MemBankWiseParams.cc + lib/drampower/src/MemCommand.cc + lib/drampower/src/MemoryPowerModel.cc + lib/drampower/src/MemorySpecification.cc + lib/drampower/src/MemPowerSpec.cc + lib/drampower/src/MemTimingSpec.cc + lib/drampower/src/Parameter.cc + lib/drampower/src/Parametrisable.cc + lib/drampower/src/TraceParser.cc + lib/drampower/src/libdrampower/LibDRAMPower.cc +) +set(SRC_SIL_NONE + sil/none/none.cc +) +set(SRC_SIL_NVME + sil/nvme/nvme.cc + sil/nvme/prp.cc + sil/nvme/queue.cc +) +set(SRC_SIM + sim/cfg_reader.cc + sim/engine.cc + sim/global_config.cc + sim/main.cc + sim/signal.cc +) +set(SRC_UTIL + util/convert.cc + util/print.cc + util/stopwatch.cc +) + +# Source group for MSVC +SOURCE_GROUP("Source Files\\bil" FILES ${SRC_BIL}) +SOURCE_GROUP("Source Files\\igl\\request" FILES ${SRC_IGL_REQUEST}) +SOURCE_GROUP("Source Files\\igl\\trace" FILES ${SRC_IGL_TRACE}) +SOURCE_GROUP("Source Files\\lib\\drampower" FILES ${SRC_LIB_DRAMPOWER}) +SOURCE_GROUP("Source Files\\sil\\none" FILES ${SRC_SIL_NONE}) +SOURCE_GROUP("Source Files\\sil\\nvme" FILES ${SRC_SIL_NVME}) +SOURCE_GROUP("Source Files\\sim" FILES ${SRC_SIM}) +SOURCE_GROUP("Source Files\\util" FILES ${SRC_UTIL}) + +# Define executable +add_executable(simplessd-standalone + ${SRC_BIL} + ${SRC_IGL_REQUEST} + ${SRC_IGL_TRACE} + ${SRC_LIB_DRAMPOWER} + ${SRC_SIL_NONE} + ${SRC_SIL_NVME} + ${SRC_SIM} + ${SRC_UTIL} +) +target_link_libraries(simplessd-standalone simplessd) diff --git a/SSD-WAF-Analysis-Capstone-2025-main/LICENSE b/SSD-WAF-Analysis-Capstone-2025-main/LICENSE new file mode 100644 index 0000000000..782c854d45 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. 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Analysis - Capstone Project 2025 +## SSD 쓰기 증폭 분석 - 졸업과제 2025 + +This repository contains a modified version of SimpleSSD v2.0 for analyzing Write Amplification Factor (WAF) with hotness-based labeling in Flash Translation Layer (FTL) algorithms. + +이 저장소는 플래시 변환 계층(FTL) 알고리즘에서 핫니스 기반 라벨링을 통한 쓰기 증폭 계수(WAF) 분석을 위해 수정된 SimpleSSD v2.0을 포함합니다. + +--- + +## Project Purpose | 프로젝트 목적 + + +This project is developed as a capstone research project to study the impact of hotness labeling on Write Amplification Factor in SSD storage systems. The primary focus is on understanding how data hotness classification affects garbage collection behavior and overall write amplification. + + +본 프로젝트는 SSD 저장 시스템에서 핫니스 라벨링이 쓰기 증폭 계수에 미치는 영향을 연구하기 위한 졸업과제 연구 프로젝트로 개발되었습니다. 데이터 핫니스 분류가 가비지 컬렉션 동작과 전체 쓰기 증폭에 어떤 영향을 미치는지 이해하는 것이 주요 목적입니다. + +--- + +## License | 라이센스 + +This project is based on SimpleSSD v2.0, which is licensed under GNU General Public License v3.0. All modifications and additions maintain the same GPL v3.0 license. + +이 프로젝트는 GNU General Public License v3.0으로 라이센스된 SimpleSSD v2.0을 기반으로 합니다. 모든 수정사항과 추가사항은 동일한 GPL v3.0 라이센스를 유지합니다. + +**Original Project:** [SimpleSSD v2.0](http://simplessd.org) by CAMELab +**License:** GNU General Public License v3.0 (see LICENSE file) + +--- + +## Key Modifications | 주요 수정사항 + +**English:** +1. **Real-time WAF Monitoring**: Added live Write Amplification Factor tracking during simulation +2. **Enhanced Statistics**: Improved WAF calculation with separate tracking for user writes and GC writes + + +**Korean:** +1. **실시간 WAF 모니터링**: 시뮬레이션 중 실시간 쓰기 증폭 계수 추적 기능 추가 +2. **향상된 통계**: 사용자 쓰기와 GC 쓰기를 분리 추적하는 개선된 WAF 계산 + +--- + +## Code Changes | 코드 변경사항 + +### Modified Files | 수정된 파일: + +- **`simplessd/ftl/page_mapping.cc`**: Added real-time WAF monitoring and enhanced statistics tracking +- **Configuration files**: Modified for research-specific parameters and reduced SSD size for testing +- **Trace files**: Added hotness-labeled traces for analysis + +### Key Features | 주요 기능: + +- Live WAF display every 1000 write operations +- Detailed GC event monitoring with WAF updates +- Separate tracking of host writes, device writes, user writes, and GC writes +- Real-time terminal output for demonstration purposes + +--- + +## Usage Notes | 사용 주의사항 + +**English:** +- **Configuration Compatibility**: The configuration files in this repository have been significantly modified from the original SimpleSSD. If you need standard SimpleSSD functionality, please refer to the original project. +- **Research Focus**: This version is specifically optimized for WAF analysis with hotness labeling. For general SSD simulation, use the original SimpleSSD. +- **FTL Reference**: The core FTL (Flash Translation Layer) algorithms remain largely unchanged and can be used as reference for standard page mapping implementations. + +**Korean:** +- **설정 호환성**: 이 저장소의 설정 파일들은 원본 SimpleSSD에서 크게 수정되었습니다. 표준 SimpleSSD 기능이 필요한 경우 원본 프로젝트를 참조하세요. +- **연구 목적**: 이 버전은 핫니스 라벨링을 통한 WAF 분석에 특화되어 최적화되었습니다. 일반적인 SSD 시뮬레이션을 위해서는 원본 SimpleSSD를 사용하세요. +- **FTL 참조**: 핵심 FTL(플래시 변환 계층) 알고리즘은 대부분 변경되지 않았으며 표준 페이지 매핑 구현의 참조로 사용할 수 있습니다. + +--- + + + +## Academic Use | 학술적 사용 + +This project is developed for educational and research purposes. If you use this code for academic research, please cite both the original SimpleSSD project and acknowledge this modification for capstone research. + +이 프로젝트는 교육 및 연구 목적으로 개발되었습니다. 학술 연구에 이 코드를 사용하는 경우, 원본 SimpleSSD 프로젝트를 인용하고 졸업과제 연구를 위한 이 수정사항을 인정해 주시기 바랍니다. + +--- + +## Contact | 연락처 + +For questions related to this capstone project modifications, please refer to the commit history and code comments. + +졸업과제 프로젝트 수정사항에 관한 질문은 커밋 히스토리와 코드 주석을 참조하시기 바랍니다. + +**Original SimpleSSD:** [SimpleSSD Website](http://simplessd.org) | [CAMELab](http://camelab.org) \ No newline at end of file diff --git a/SSD-WAF-Analysis-Capstone-2025-main/bil/entry.cc b/SSD-WAF-Analysis-Capstone-2025-main/bil/entry.cc new file mode 100644 index 0000000000..45816f1282 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/bil/entry.cc @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "bil/entry.hh" + +#include + +#include "bil/interface.hh" +#include "bil/noop_scheduler.hh" +#include "simplessd/sim/trace.hh" + +namespace BIL { + +BlockIOEntry::BlockIOEntry(ConfigReader &c, Engine &e, DriverInterface *i, + std::ostream *o) + : conf(c), + engine(e), + pLatencyFile(o), + pScheduler(nullptr), + pDriver(i), + lastProgress(0), + io_progress(0), + io_count(0), + minLatency(std::numeric_limits::max()), + maxLatency(0), + sumLatency(0), + squareSumLatency(0), + callback([this](uint64_t id) { completion(id); }) { + switch (c.readUint(CONFIG_GLOBAL, GLOBAL_SCHEDULER)) { + case SCHEDULER_NOOP: + pScheduler = new NoopScheduler(e, i); + + break; + default: + SimpleSSD::panic("Invalid I/O scheduler specified"); + + break; + } + + pScheduler->init(); +} + +BlockIOEntry::~BlockIOEntry() { + delete pScheduler; +} + +void BlockIOEntry::submitIO(BIO &bio) { + BIO copy(bio); + + io_count++; + bio.submittedAt = engine.getCurrentTick(); + + ioQueue.push_back(bio); + copy.callback = callback; + + pScheduler->submitIO(copy); +} + +void BlockIOEntry::completion(uint64_t id) { + uint64_t tick = engine.getCurrentTick(); + + for (auto iter = ioQueue.begin(); iter != ioQueue.end(); iter++) { + if (iter->id == id) { + tick = tick - iter->submittedAt; + + { + std::lock_guard guard(m); + + io_progress++; + + progress.latency += tick; + progress.iops++; + progress.bandwidth += iter->length; + } + + if (pLatencyFile) { + *pLatencyFile << std::to_string(iter->id) << ", " + << std::to_string(iter->offset) << ", " + << std::to_string(iter->length) << ", " + << std::to_string(tick) << std::endl; + } + + iter->callback(id); + + ioQueue.erase(iter); + + break; + } + } + + if (minLatency > tick) { + minLatency = tick; + } + if (maxLatency < tick) { + maxLatency = tick; + } + + sumLatency += tick; + squareSumLatency += tick * tick; +} + +void BlockIOEntry::printStats(std::ostream &out) { + double avgLatency = (double)sumLatency / io_count; + double stdevLatency = sqrt((double)squareSumLatency / io_count - avgLatency); + double digit = log10(avgLatency); + + out << "*** Statistics of Block I/O Entry ***" << std::endl; + + if (digit < 6.0) { + out << "Latency (ps): min=" << std::to_string(minLatency) + << ", max=" << std::to_string(maxLatency) + << ", avg=" << std::to_string(avgLatency) + << ", stdev=" << std::to_string(stdevLatency) << std::endl; + } + else if (digit < 9.0) { + out << "Latency (ns): min=" << std::to_string(minLatency / 1000.0) + << ", max=" << std::to_string(maxLatency / 1000.0) + << ", avg=" << std::to_string(avgLatency / 1000.0) + << ", stdev=" << std::to_string(stdevLatency / 31.62277660168) + << std::endl; + } + else if (digit < 12.0) { + out << "Latency (us): min=" << std::to_string(minLatency / 1000000.0) + << ", max=" << std::to_string(maxLatency / 1000000.0) + << ", avg=" << std::to_string(avgLatency / 1000000.0) + << ", stdev=" << std::to_string(stdevLatency / 1000.0) << std::endl; + } + else { + out << "Latency (ms): min=" << std::to_string(minLatency / 1000000000.0) + << ", max=" << std::to_string(maxLatency / 1000000000.0) + << ", avg=" << std::to_string(avgLatency / 1000000000.0) + << ", stdev=" << std::to_string(stdevLatency / 31622.77660168379) + << std::endl; + } + + out << "*** End of statistics ***" << std::endl; +} + +void BlockIOEntry::getProgress(Progress &data) { + uint64_t tick = engine.getCurrentTick(); + uint64_t diff = tick - lastProgress; + + if (diff == 0) { + data.iops = 0; + data.bandwidth = 0; + data.latency = 0; + + return; + } + + double ratio = 1000000000000.0 / diff; + + { + std::lock_guard guard(m); + + data.iops = progress.iops * ratio; + data.bandwidth = progress.bandwidth * ratio; + + if (io_progress == 0) { + data.latency = 0; + } + else { + data.latency = progress.latency / io_progress; + } + + io_progress = 0; + progress.iops = 0; + progress.bandwidth = 0; + progress.latency = 0; + } + + lastProgress = tick; +} + +} // namespace BIL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/bil/entry.hh b/SSD-WAF-Analysis-Capstone-2025-main/bil/entry.hh new file mode 100644 index 0000000000..38b3c4ff67 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/bil/entry.hh @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_ENTRY__ +#define __BIL_ENTRY__ + +#include +#include +#include +#include + +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace BIL { + +class Scheduler; +class DriverInterface; + +enum BIO_TYPE : uint8_t { + BIO_READ, + BIO_WRITE, + BIO_FLUSH, + BIO_TRIM, + BIO_NUM, +}; + +typedef struct _BIO { + uint64_t id; + + // I/O definition + BIO_TYPE type; + uint64_t offset; + uint64_t length; + + // I/O completion + std::function callback; + + // Statistics + uint64_t submittedAt; + + _BIO() : id(0), type(BIO_READ), offset(0), length(0), submittedAt(0) {} +} BIO; + +typedef struct _Progress { + uint64_t iops; + uint64_t bandwidth; + uint64_t latency; +} Progress; + +class BlockIOEntry { + private: + ConfigReader &conf; + Engine &engine; + std::list ioQueue; + + std::ostream *pLatencyFile; + + Scheduler *pScheduler; + DriverInterface *pDriver; + + std::mutex m; + uint64_t lastProgress; + uint64_t io_progress; + Progress progress; + + // Statistics + uint64_t io_count; + uint64_t minLatency; + uint64_t maxLatency; + uint64_t sumLatency; + uint64_t squareSumLatency; + + std::function callback; + void completion(uint64_t); + + public: + BlockIOEntry(ConfigReader &, Engine &, DriverInterface *, std::ostream *); + ~BlockIOEntry(); + + void submitIO(BIO &); + + void printStats(std::ostream &); + void getProgress(Progress &); +}; + +} // namespace BIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/bil/interface.hh b/SSD-WAF-Analysis-Capstone-2025-main/bil/interface.hh new file mode 100644 index 0000000000..0db8d86a98 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/bil/interface.hh @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_DRIVER_INTERFACE__ +#define __BIL_DRIVER_INTERFACE__ + +#include + +#include "bil/entry.hh" +#include "simplessd/sim/statistics.hh" + +namespace BIL { + +class DriverInterface { + protected: + Engine &engine; + + std::function beginFunction; + + public: + DriverInterface(Engine &e) : engine(e) {} + virtual ~DriverInterface() {} + + virtual void init(std::function &) = 0; + virtual void getInfo(uint64_t &, uint32_t &) = 0; + virtual void submitIO(BIO &) = 0; + + virtual void initStats(std::vector &) = 0; + virtual void getStats(std::vector &) = 0; +}; + +} // namespace BIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/bil/noop_scheduler.cc b/SSD-WAF-Analysis-Capstone-2025-main/bil/noop_scheduler.cc new file mode 100644 index 0000000000..1f45bb488f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/bil/noop_scheduler.cc @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "bil/noop_scheduler.hh" + +namespace BIL { + +NoopScheduler::NoopScheduler(Engine &e, DriverInterface *i) : Scheduler(e, i) {} + +NoopScheduler::~NoopScheduler() {} + +void NoopScheduler::init() {} + +void NoopScheduler::submitIO(BIO &bio) { + pInterface->submitIO(bio); +} + +} // namespace BIL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/bil/noop_scheduler.hh b/SSD-WAF-Analysis-Capstone-2025-main/bil/noop_scheduler.hh new file mode 100644 index 0000000000..814e385d8c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/bil/noop_scheduler.hh @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_NOOP_SCHEDULER__ +#define __BIL_NOOP_SCHEDULER__ + +#include "bil/scheduler.hh" + +namespace BIL { + +class NoopScheduler : public Scheduler { + public: + NoopScheduler(Engine &, DriverInterface *); + ~NoopScheduler(); + + void init(); + void submitIO(BIO &); +}; + +} // namespace BIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/bil/scheduler.hh b/SSD-WAF-Analysis-Capstone-2025-main/bil/scheduler.hh new file mode 100644 index 0000000000..292b039a66 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/bil/scheduler.hh @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_SCHEDULER__ +#define __BIL_SCHEDULER__ + +#include "bil/interface.hh" + +namespace BIL { + +class Scheduler { + protected: + Engine &engine; + DriverInterface *pInterface; + + public: + Scheduler(Engine &e, DriverInterface *i) : engine(e), pInterface(i) {} + virtual ~Scheduler() {} + + virtual void init() = 0; + virtual void submitIO(BIO &) = 0; +}; + +} // namespace BIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/cmake_install.cmake b/SSD-WAF-Analysis-Capstone-2025-main/cmake_install.cmake new file mode 100644 index 0000000000..4f76736298 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/cmake_install.cmake @@ -0,0 +1,67 @@ +# Install script for directory: /Users/gagaga/Documents/newCapstone/simplessd-standalone + +# Set the install prefix +if(NOT DEFINED CMAKE_INSTALL_PREFIX) + set(CMAKE_INSTALL_PREFIX "/usr/local") +endif() +string(REGEX REPLACE "/$" "" CMAKE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}") + +# Set the install configuration name. +if(NOT DEFINED CMAKE_INSTALL_CONFIG_NAME) + if(BUILD_TYPE) + string(REGEX REPLACE "^[^A-Za-z0-9_]+" "" + CMAKE_INSTALL_CONFIG_NAME "${BUILD_TYPE}") + else() + set(CMAKE_INSTALL_CONFIG_NAME "") + endif() + message(STATUS "Install configuration: \"${CMAKE_INSTALL_CONFIG_NAME}\"") +endif() + +# Set the component getting installed. +if(NOT CMAKE_INSTALL_COMPONENT) + if(COMPONENT) + message(STATUS "Install component: \"${COMPONENT}\"") + set(CMAKE_INSTALL_COMPONENT "${COMPONENT}") + else() + set(CMAKE_INSTALL_COMPONENT) + endif() +endif() + +# Is this installation the result of a crosscompile? +if(NOT DEFINED CMAKE_CROSSCOMPILING) + set(CMAKE_CROSSCOMPILING "FALSE") +endif() + +# Set path to fallback-tool for dependency-resolution. +if(NOT DEFINED CMAKE_OBJDUMP) + set(CMAKE_OBJDUMP "/usr/bin/objdump") +endif() + +if(NOT CMAKE_INSTALL_LOCAL_ONLY) + # Include the install script for each subdirectory. + include("/Users/gagaga/Documents/newCapstone/simplessd-standalone/simplessd/cmake_install.cmake") + +endif() + +string(REPLACE ";" "\n" CMAKE_INSTALL_MANIFEST_CONTENT + "${CMAKE_INSTALL_MANIFEST_FILES}") +if(CMAKE_INSTALL_LOCAL_ONLY) + file(WRITE "/Users/gagaga/Documents/newCapstone/simplessd-standalone/install_local_manifest.txt" + "${CMAKE_INSTALL_MANIFEST_CONTENT}") +endif() +if(CMAKE_INSTALL_COMPONENT) + if(CMAKE_INSTALL_COMPONENT MATCHES "^[a-zA-Z0-9_.+-]+$") + set(CMAKE_INSTALL_MANIFEST "install_manifest_${CMAKE_INSTALL_COMPONENT}.txt") + else() + string(MD5 CMAKE_INST_COMP_HASH "${CMAKE_INSTALL_COMPONENT}") + set(CMAKE_INSTALL_MANIFEST "install_manifest_${CMAKE_INST_COMP_HASH}.txt") + unset(CMAKE_INST_COMP_HASH) + endif() +else() + set(CMAKE_INSTALL_MANIFEST "install_manifest.txt") +endif() + +if(NOT CMAKE_INSTALL_LOCAL_ONLY) + file(WRITE "/Users/gagaga/Documents/newCapstone/simplessd-standalone/${CMAKE_INSTALL_MANIFEST}" + "${CMAKE_INSTALL_MANIFEST_CONTENT}") +endif() diff --git a/SSD-WAF-Analysis-Capstone-2025-main/config/my_test.cfg b/SSD-WAF-Analysis-Capstone-2025-main/config/my_test.cfg new file mode 100644 index 0000000000..4ecc636d19 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/config/my_test.cfg @@ -0,0 +1,224 @@ +# +# Copyright (C) 2017 CAMELab +# +# 이 파일은 SimpleSSD의 일부입니다. +# +# SimpleSSD는 자유 소프트웨어입니다: 자유 소프트웨어 재단이 공표한 GNU 일반 공중 사용 허가서(버전 3 또는 그 이후 버전)의 조건에 따라 재배포 및/또는 수정할 수 있습니다. +# +# SimpleSSD는 유용하게 사용될 수 있으리라 기대되지만, +# 어떠한 형태의 보증도 제공하지 않습니다. 상품성 또는 특정 목적에의 적합성에 대한 묵시적 보증도 없습니다. +# 자세한 내용은 GNU 일반 공중 사용 허가서를 참고하십시오. +# +# SimpleSSD와 함께 GNU 일반 공중 사용 허가서를 받으셨을 것입니다. +# 못 받으셨다면 를 참고하십시오. +# + +# +# SimpleSSD-Standalone 샘플 설정 파일 +# +# 섹션: +# global: 전역 옵션 +# generator: 요청 생성기 설정 +# trace: 트레이스 재생기 설정 +# + +# 전역 설정 +[global] + +## 모드 선택 +# 가능한 값: +# 0: 요청 생성기 모드 ([trace]의 모든 설정은 무시됨)(IO 자동 생성) +# 1: 트레이스 재생기 모드 ([generator]의 모든 설정은 무시됨)(trace파일을 읽어야함 ) +Mode = 1 + +## 통계 로그 주기 +# 주기적으로 통계 로그를 출력합니다 +# 0이면 로그를 출력하지 않음 +# 단위: ms (밀리초, 시뮬레이션 시간 기준, 실제 시간이 아님) +LogPeriod = 0 + +## 로그 파일 +# 통계 로그와 디버그 로그의 출력 경로를 설정합니다 +# <빈 값>이면 로그를 출력하지 않음 +# 가능한 키워드: +# STDOUT: 표준 출력 +# STDERR: 표준 에러 +LogFile = STDOUT +DebugLogFile = + +## I/O 로그 파일 +# 지연 시간 로그의 출력 경로를 설정합니다 +# <빈 값>이면 로그를 출력하지 않음 +LatencyLogFile = + +## 진행 상황 출력 +# 두 로그 모두 파일로 출력될 경우(화면이 아님) +# 이벤트 엔진 속도와 시뮬레이션 진행 상황이 STDOUT에 표시됩니다 +# 이 옵션은 진행 상황 출력 주기를 설정합니다 +# 0이면 로그를 출력하지 않음 +# 단위: s (초, 호스트 시간 기준, 실제 시간) +ProgressPeriod = 0 + +## 인터페이스 +# 사용할 호스트 인터페이스를 설정합니다 +# 가능한 값: +# 0: 인터페이스 없음 - 요청을 HIL 계층에 직접 전달 +# 1: NVMe - Non-Volatile Memory Express 사용 +# 2: SATA - Serial AT Attachment 사용 +# 3: UFS - Universal Flash Storage 사용 +Interface = 0 + +## 스케줄러 +# Block I/O 계층에서 사용할 스케줄러를 설정합니다 +# 가능한 값: +# 0: Noop - 스케줄링 없음 +Scheduler = 0 + +## 시스템 지연 시간 +# 실제 OS의 I/O 스택을 모방하여 소프트웨어 실행 지연 시간을 추가합니다 +SubmissionLatency = 0us +CompletionLatency = 0us + +# 요청 생성기 설정 +[generator] + +## 이 요청 생성기는 Flexible I/O tester와 유사하게 동작합니다 +# 타입 정의: +# str: 문자열, 영숫자 문자들의 시퀀스 +# int: SI 정수, 숫자 문자들의 시퀀스 +# 가능한 접미사(대소문자 구분): +# 10^3 단위: k, m, g, t +# 2^10 단위: K, M, G, T +# float: 부동 소수점 숫자, 소수점이 하나(또는 없음) 포함된 숫자 시퀀스 +# bool: 불리언, 참 또는 거짓 값 +# 가능한 값(대소문자 구분 없음): +# 참: 0이 아닌 숫자, T, True, Y, Yes +# 거짓: 그 외 +# time: SI 정수, 숫자 문자들의 시퀀스 +# 접미사가 없으면 값은 피코초로 처리됨 +# 가능한 접미사(대소문자 구분): +# s, ms, us, ns, ps + +## 전체 I/O 크기 = int +# time_based = false일 때만 유효 +io_size = 16M # 16 * 2^20 바이트 + +## I/O 타입 = str +# 가능한 값: +# read: 순차 읽기 +# write: 순차 쓰기 +# randread: 랜덤 읽기 +# randwrite: 랜덤 쓰기 +# readwrite: 혼합 순차 I/O +# randrw: 혼합 랜덤 I/O +readwrite = read + +## 혼합 I/O 비율 = float +# readwrite가 readwrite 또는 randrw가 아니면 이 값은 무시됨 +# 0 <= 값 <= 1 +rwmixread = 0.5 # 읽기 I/O의 50% + +## 블록 크기 = int +blocksize = 4K + +## 블록 정렬 = int +# 기본 <빈 값>은 blocksize +blockalign = + +## I/O 모드 = str +# 가능한 값: +# sync: 동기식 I/O +# async: 비동기식 I/O +iomode = async + +## I/O 깊이 = int +# = sync일 때 iodepth = 1 +iodepth = 32 + +## 오프셋 = int +offset = 0 + +## 크기 = int +# 기본 <빈 값>은 [SSD 크기] - +size = + +## Thinktime = time +thinktime = 0 + +## 랜덤 시드 = int +randseed = 13245 + +## 시간 기반 = bool +time_based = 0 + +## 실행 시간 = time +# time_based = true일 때만 유효 +runtime = 10s + +# 트레이스 재생기 설정 +[trace] + +## 트레이스 파일 +File = ./traces/sa00_50M_no_hotness.csv + +## 타이밍 옵션 +# 가능한 값: +# 0: 타이밍 제약 없음(동기식) +# I/O가 BreakSyncIO 대기 시간과 함께 동기식으로 발행됨 +# 1: 타이밍 제약 없음(비동기식) +# I/O가 BreakAsyncIO 대기 시간과 함께 비동기식으로 발행됨 +# 2: 엄격한 타이밍 +# I/O가 트레이스의 정확한 시간에 비동기식으로 발행됨 +TimingMode = 1 + +## 큐 깊이 +# TimingMode = 1일 때 최대 비동기 I/O 깊이 +QueueDepth = 64 + +## I/O 개수 제한 +# 0으로 설정하거나 비워두면 트레이스 파일의 모든 I/O를 발행 +IOLimit = 0 + +## 트레이스 파일 정규표현식 +# C++11 정규표현식 라이브러리 참고 +# 항상 ECMAScript 정규표현식 문법 사용 +# 매칭되지 않은 라인은 무시됨 +# 이 예시는 blkparse 결과용 +Regex = "\d+,\d+ +\d+ +\d+ +(\d+).(\d+) +\d+ +D +(\w+) +(\d+) \+ (\d+)" + +## 트레이스 파일 정규표현식 그룹 ID +# 파싱된 트레이스 파일의 필드와 그룹 ID 매핑 +# = +# 필드는 비워둘 수 있음 +# 모든 시간 필드는 합산됨 +# 그룹 ID 0은 매칭된 문자열(사용하지 말 것) +# 모든 필드(연산 제외)는 정수여야 함(부동 소수점 불가) +# 연산(Operation)의 경우 문자열의 첫 글자만 사용 +# R: 읽기, W: 쓰기, F: 플러시, T/D: 트림 +# 대소문자 구분 없음 +# 예: RA (blkparse의 Read, Read-ahead) +# 읽기 연산(R)으로 처리 +# 예: trim (fio iolog 버전 2의 Trim) +# 트림 연산(T)으로 처리 +# 예: D (blkparse의 Trim - Discard) +# 트림 연산(D)으로 처리 +# 예: FWFS (blkparse의 Flush, Write, FUA, SYNC) +# 플러시 연산(F)으로 처리 +Operation = 3 +ByteOffset = +ByteLength = +LBAOffset = 4 +LBALength = 5 +Second = 1 +Millisecond = +Microsecond = +Nanosecond = 2 +Picosecond = + +## LBA 크기 +# LBA offset/length를 사용할 경우 LBA 크기 설정 +LBASize = 512 + +## 필드(시간 제외)를 16진수로 처리 +# 정규표현식이 16진수 숫자를 캡처하는지 반드시 확인 +UseHexadecimal = 0 diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/io_gen.hh b/SSD-WAF-Analysis-Capstone-2025-main/igl/io_gen.hh new file mode 100644 index 0000000000..c9b6d63f0f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/io_gen.hh @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_IO_GEN__ +#define __IGL_IO_GEN__ + +#include "bil/entry.hh" +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace IGL { + +class IOGenerator { + protected: + Engine &engine; + BIL::BlockIOEntry &bioEntry; + std::function &endCallback; + + public: + IOGenerator(Engine &e, BIL::BlockIOEntry &b, std::function &c) + : engine(e), bioEntry(b), endCallback(c) {} + virtual ~IOGenerator() {} + + virtual void init(uint64_t, uint32_t) = 0; + virtual void begin() = 0; + virtual void printStats(std::ostream &) = 0; + virtual void getProgress(float &) = 0; +}; + +} // namespace IGL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_config.cc b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_config.cc new file mode 100644 index 0000000000..e544c7af73 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_config.cc @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/request/request_config.hh" + +#include "simplessd/sim/trace.hh" +#include "util/convert.hh" + +namespace IGL { + +const char NAME_IO_SIZE[] = "io_size"; +const char NAME_IO_TYPE[] = "readwrite"; +const char NAME_IO_MIX_RATIO[] = "rwmixread"; +const char NAME_BLOCK_SIZE[] = "blocksize"; +const char NAME_BLOCK_ALIGN[] = "blockalign"; +const char NAME_IO_MODE[] = "iomode"; +const char NAME_IO_DEPTH[] = "iodepth"; +const char NAME_OFFSET[] = "offset"; +const char NAME_SIZE[] = "size"; +const char NAME_THINKTIME[] = "thinktime"; +const char NAME_RANDOM_SEED[] = "randseed"; +const char NAME_TIME_BASED[] = "time_based"; +const char NAME_RUN_TIME[] = "runtime"; + +RequestConfig::RequestConfig() { + io_size = 0; + type = IO_READ; + rwmixread = 0; + blocksize = 0; + blockalign = 0; + mode = IO_SYNC; + iodepth = 0; + offset = 0; + size = 0; + thinktime = 0; + randseed = 0; + time_based = false; + runtime = 0; +} + +bool RequestConfig::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_IO_SIZE)) { + io_size = convertInteger(value); + } + else if (MATCH_NAME(NAME_IO_TYPE)) { + if (strcasecmp(value, "read") == 0) { + type = IO_READ; + } + else if (strcasecmp(value, "write") == 0) { + type = IO_WRITE; + } + else if (strcasecmp(value, "randread") == 0) { + type = IO_RANDREAD; + } + else if (strcasecmp(value, "randwrite") == 0) { + type = IO_RANDWRITE; + } + else if (strcasecmp(value, "readwrite") == 0) { + type = IO_READWRITE; + } + else if (strcasecmp(value, "randrw") == 0) { + type = IO_RANDRW; + } + else { + type = IO_TYPE_NUM; + } + } + else if (MATCH_NAME(NAME_IO_MIX_RATIO)) { + rwmixread = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_BLOCK_SIZE)) { + blocksize = convertInteger(value); + } + else if (MATCH_NAME(NAME_BLOCK_ALIGN)) { + blockalign = convertInteger(value); + } + else if (MATCH_NAME(NAME_IO_MODE)) { + if (strcasecmp(value, "sync") == 0) { + mode = IO_SYNC; + } + else if (strcasecmp(value, "async") == 0) { + mode = IO_ASYNC; + } + else { + mode = IO_MODE_NUM; + } + } + else if (MATCH_NAME(NAME_IO_DEPTH)) { + iodepth = convertInteger(value); + } + else if (MATCH_NAME(NAME_OFFSET)) { + offset = convertInteger(value); + } + else if (MATCH_NAME(NAME_SIZE)) { + size = convertInteger(value); + } + else if (MATCH_NAME(NAME_THINKTIME)) { + thinktime = convertInteger(value); + } + else if (MATCH_NAME(NAME_RANDOM_SEED)) { + randseed = convertInteger(value); + } + else if (MATCH_NAME(NAME_TIME_BASED)) { + time_based = convertBoolean(value); + } + else if (MATCH_NAME(NAME_RUN_TIME)) { + runtime = convertTime(value); + } + else { + ret = false; + } + + return ret; +} + +void RequestConfig::update() { + if (type == IO_TYPE_NUM) { + SimpleSSD::panic("Invalid value of readwrite"); + } + if (mode == IO_MODE_NUM) { + SimpleSSD::panic("Invalid value of iomode"); + } + if (rwmixread < 0 || rwmixread > 1) { + SimpleSSD::panic("Invalid value of rwmixread"); + } +} + +uint64_t RequestConfig::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case REQUEST_IO_SIZE: + ret = io_size; + break; + case REQUEST_IO_TYPE: + ret = type; + break; + case REQUEST_BLOCK_SIZE: + ret = blocksize; + break; + case REQUEST_BLOCK_ALIGN: + ret = blockalign; + break; + case REQUEST_IO_MODE: + ret = mode; + break; + case REQUEST_IO_DEPTH: + ret = iodepth; + break; + case REQUEST_OFFSET: + ret = offset; + break; + case REQUEST_SIZE: + ret = size; + break; + case REQUEST_THINKTIME: + ret = thinktime; + break; + case REQUEST_RANDOM_SEED: + ret = randseed; + break; + case REQUEST_RUN_TIME: + ret = runtime; + break; + } + + return ret; +} + +float RequestConfig::readFloat(uint32_t idx) { + float ret = 0.f; + + switch (idx) { + case REQUEST_IO_MIX_RATIO: + ret = rwmixread; + break; + } + + return ret; +} + +bool RequestConfig::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case REQUEST_TIME_BASED: + ret = time_based; + break; + } + + return ret; +} + +} // namespace IGL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_config.hh b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_config.hh new file mode 100644 index 0000000000..bd9571f721 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_config.hh @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_REQUEST_CONFIG__ +#define __IGL_REQUEST_CONFIG__ + +#include "simplessd/sim/base_config.hh" + +namespace IGL { + +typedef enum { + REQUEST_IO_SIZE, + REQUEST_IO_TYPE, + REQUEST_IO_MIX_RATIO, + REQUEST_BLOCK_SIZE, + REQUEST_BLOCK_ALIGN, + REQUEST_IO_MODE, + REQUEST_IO_DEPTH, + REQUEST_OFFSET, + REQUEST_SIZE, + REQUEST_THINKTIME, + REQUEST_RANDOM_SEED, + REQUEST_TIME_BASED, + REQUEST_RUN_TIME, +} REQUEST_CONFIG; + +typedef enum { + IO_READ, + IO_WRITE, + IO_RANDREAD, + IO_RANDWRITE, + IO_READWRITE, + IO_RANDRW, + IO_TYPE_NUM, +} IO_TYPE; + +typedef enum { + IO_SYNC, + IO_ASYNC, + IO_MODE_NUM, +} IO_MODE; + +class RequestConfig : public SimpleSSD::BaseConfig { + private: + uint64_t io_size; + IO_TYPE type; + float rwmixread; + uint64_t blocksize; + uint64_t blockalign; + IO_MODE mode; + uint64_t iodepth; + uint64_t offset; + uint64_t size; + uint64_t thinktime; + uint64_t randseed; + bool time_based; + uint64_t runtime; + + public: + RequestConfig(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; + float readFloat(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace IGL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_generator.cc b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_generator.cc new file mode 100644 index 0000000000..0724cda972 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_generator.cc @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/request/request_generator.hh" + +#include + +#include "simplessd/sim/trace.hh" +#include "simplessd/util/algorithm.hh" + +namespace IGL { + +RequestGenerator::RequestGenerator(Engine &e, BIL::BlockIOEntry &b, + std::function &f, ConfigReader &c) + : IOGenerator(e, b, f), + io_submitted(0), + io_count(0), + read_count(0), + io_depth(0), + reserveTermination(false) { + // Read config + io_size = c.readUint(CONFIG_REQ_GEN, REQUEST_IO_SIZE); + type = (IO_TYPE)c.readUint(CONFIG_REQ_GEN, REQUEST_IO_TYPE); + mode = (IO_MODE)c.readUint(CONFIG_REQ_GEN, REQUEST_IO_MODE); + iodepth = c.readUint(CONFIG_REQ_GEN, REQUEST_IO_DEPTH); + rwmixread = c.readFloat(CONFIG_REQ_GEN, REQUEST_IO_MIX_RATIO); + offset = c.readUint(CONFIG_REQ_GEN, REQUEST_OFFSET); + size = c.readUint(CONFIG_REQ_GEN, REQUEST_SIZE); + thinktime = c.readUint(CONFIG_REQ_GEN, REQUEST_THINKTIME); + blocksize = c.readUint(CONFIG_REQ_GEN, REQUEST_BLOCK_SIZE); + blockalign = c.readUint(CONFIG_REQ_GEN, REQUEST_BLOCK_ALIGN); + randseed = c.readUint(CONFIG_REQ_GEN, REQUEST_RANDOM_SEED); + time_based = c.readBoolean(CONFIG_REQ_GEN, REQUEST_TIME_BASED); + runtime = c.readUint(CONFIG_REQ_GEN, REQUEST_RUN_TIME); + + if (blockalign == 0) { + blockalign = blocksize; + } + + if (mode == IO_SYNC) { + iodepth = 1; + mode = IO_ASYNC; + } + + submissionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_SUBMISSION_LATENCY); + completionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_COMPLETION_LATENCY); + + // Set random engine + randengine.seed(randseed); + + submitIO = [this](uint64_t tick) { _submitIO(tick); }; + iocallback = [this](uint64_t id) { _iocallback(id); }; + + submitEvent = engine.allocateEvent(submitIO); +} + +RequestGenerator::~RequestGenerator() {} + +void RequestGenerator::init(uint64_t bytesize, uint32_t bs) { + if (offset > bytesize) { + SimpleSSD::panic("offset is larger than SSD size"); + } + if (blocksize < bs) { + SimpleSSD::panic("blocksize is smaller than SSD's logical block"); + } + if (blockalign < bs) { + SimpleSSD::panic("blockalign is smaller than SSD's logical block"); + } + if (blocksize % bs != 0) { + SimpleSSD::warn("blocksize is not aligned to SSD's logical block"); + + blocksize /= bs; + blocksize *= bs; + } + if (blockalign % bs != 0) { + SimpleSSD::warn("blockalign is not aligned to SSD's logical block"); + + blockalign /= bs; + blockalign *= bs; + } + if (offset % blockalign != 0) { + SimpleSSD::warn("offset is not aligned to blockalign"); + + offset /= blockalign; + offset *= blockalign; + } + if (size == 0 || offset + size > bytesize) { + size = bytesize - offset; + } + if (size == 0) { + SimpleSSD::panic("Invalid offset and size provided"); + } + + randgen = std::uniform_int_distribution(offset, offset + size); +} + +void RequestGenerator::begin() { + initTime = engine.getCurrentTick(); + + _submitIO(initTime); +} + +void RequestGenerator::printStats(std::ostream &out) { + uint64_t tick = engine.getCurrentTick(); + + out << "*** Statistics of Request Generator ***" << std::endl; + out << "Tick: " << tick << std::endl; + out << "Time (ps): " << initTime << " - " << tick << " (" << tick - initTime + << ")" << std::endl; + out << "I/O (bytes): " << io_submitted << " (" + << std::to_string((double)io_submitted / (tick - initTime) * + 1000000000000.) + << " B/s)" << std::endl; + out << "I/O (counts): " << io_count << " (Read: " << read_count + << ", Write: " << io_count - read_count << ")" << std::endl; + out << "*** End of statistics ***" << std::endl; + + bioEntry.printStats(out); +} + +void RequestGenerator::getProgress(float &val) { + bool zero = false; + + { + std::lock_guard guard(m); + + if (io_submitted == 0) { + zero = true; + } + } + + if (zero) { + val = 0.f; + + return; + } + + if (time_based) { // Read-only variable after init + uint64_t tick = engine.getCurrentTick(); // Thread-safe + + // initTime is read-only after begin() called + val = (float)(tick - initTime) / runtime; + } + else { + std::lock_guard guard(m); + + val = (float)io_submitted / io_size; + } +} + +void RequestGenerator::generateAddress(uint64_t &off, uint64_t &len) { + // This function generates address to access + // based on I/O type, blocksize/align and offset/size + if (type == IO_RANDREAD || type == IO_RANDWRITE || type == IO_RANDRW) { + off = randgen(randengine); // randgen range: [offset, offset + size) + off -= off % blockalign; + len = blocksize; + } + else { + off = io_count * blockalign; + len = blocksize; + + // Limit range of address to [offset, offset + size) + while (off + len > size) { + if (off >= size) { + off -= size; + } + else { + // TODO: is this correct? + off -= len; + } + } + + off += offset; + } +} + +bool RequestGenerator::nextIOIsRead() { + // This function determine next I/O is read or write + // based on rwmixread + // io_count should not zero + if (type == IO_READWRITE || type == IO_RANDRW) { + if (rwmixread > (float)read_count / io_count) { + return true; + } + } + else if (type == IO_READ || type == IO_RANDREAD) { + return true; + } + + return false; +} + +void RequestGenerator::_submitIO(uint64_t) { + BIL::BIO bio; + + // This function uses io_count (=0 at very beginning) + generateAddress(bio.offset, bio.length); + + bio.id = io_count++; + + // This function also uses io_count (=1 at very beginning) + if (nextIOIsRead()) { + bio.type = BIL::BIO_READ; + read_count++; + } + else { + bio.type = BIL::BIO_WRITE; + } + + io_submitted += bio.length; + + bio.callback = iocallback; + + // push to queue + io_depth++; + + // Submit to Block I/O entry + bioEntry.submitIO(bio); + + // Check on-the-fly I/O depth + rescheduleSubmit(submissionLatency); +} + +void RequestGenerator::_iocallback(uint64_t) { + io_depth--; + + if (reserveTermination) { + // No I/O will be generated anymore + // If no pending I/O call endCallback + if (io_depth == 0) { + endCallback(); + } + } + else { + // Check on-the-fly I/O depth + rescheduleSubmit(submissionLatency + completionLatency); + } +} + +void RequestGenerator::rescheduleSubmit(uint64_t breakTime) { + uint64_t tick = engine.getCurrentTick(); + + // We are done + if ((!time_based && io_submitted >= io_size) || + (time_based && runtime <= (tick - initTime))) { + reserveTermination = true; + + // We need to double-check this for following case: + // _iocallback (all I/O completed) -> rescheduleSubmit + if (io_depth == 0) { + endCallback(); + } + + return; + } + + if (io_depth < iodepth) { + uint64_t scheduledTick; + bool doSchedule = true; + + // Check conflict + if (engine.isScheduled(submitEvent, &scheduledTick)) { + if (scheduledTick >= tick + breakTime) { + doSchedule = false; + } + } + + // We can schedule it + if (doSchedule) { + engine.scheduleEvent(submitEvent, tick + breakTime); + } + } +} + +} // namespace IGL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_generator.hh b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_generator.hh new file mode 100644 index 0000000000..bebf3bec6c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/request/request_generator.hh @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_REQUEST_GENERATOR__ +#define __IGL_REQUEST_GENERATOR__ + +#include +#include +#include +#include + +#include "bil/entry.hh" +#include "igl/io_gen.hh" +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace IGL { + +class RequestGenerator : public IOGenerator { + private: + std::mutex m; + + uint64_t io_size; + uint64_t io_submitted; + + IO_TYPE type; + + IO_MODE mode; + uint64_t iodepth; + + uint64_t io_count; + uint64_t read_count; + float rwmixread; + + uint64_t offset; + uint64_t size; + + uint64_t thinktime; + + uint64_t blocksize; + uint64_t blockalign; + + uint64_t randseed; + std::mt19937_64 randengine; + std::uniform_int_distribution randgen; + + bool time_based; + uint64_t runtime; + + uint64_t submissionLatency; + uint64_t completionLatency; + + uint64_t io_depth; + + uint64_t initTime; + bool reserveTermination; + + void generateAddress(uint64_t &, uint64_t &); + bool nextIOIsRead(); + void rescheduleSubmit(uint64_t); + + SimpleSSD::Event submitEvent; + SimpleSSD::EventFunction submitIO; + SimpleSSD::EventFunction iocallback; + + void _submitIO(uint64_t); + void _iocallback(uint64_t); + + public: + RequestGenerator(Engine &, BIL::BlockIOEntry &, std::function &, + ConfigReader &); + ~RequestGenerator(); + + void init(uint64_t, uint32_t) override; + void begin() override; + void printStats(std::ostream &) override; + void getProgress(float &) override; +}; + +} // namespace IGL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_config.cc b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_config.cc new file mode 100644 index 0000000000..ef479d91e3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_config.cc @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/trace/trace_config.hh" + +#include "simplessd/sim/trace.hh" + +namespace IGL { + +const char NAME_FILE[] = "File"; +const char NAME_TIMING_MODE[] = "TimingMode"; +const char NAME_QUEUE_DEPTH[] = "QueueDepth"; +const char NAME_IO_LIMIT[] = "IOLimit"; +const char NAME_LINE_REGEX[] = "Regex"; +const char NAME_GROUP_OPERATION[] = "Operation"; +const char NAME_GROUP_BYTE_OFFSET[] = "ByteOffset"; +const char NAME_GROUP_BYTE_LENGTH[] = "ByteLength"; +const char NAME_GROUP_LBA_OFFSET[] = "LBAOffset"; +const char NAME_GROUP_LBA_LENGTH[] = "LBALength"; +const char NAME_GROUP_SEC[] = "Second"; +const char NAME_GROUP_MILI_SEC[] = "Millisecond"; +const char NAME_GROUP_MICRO_SEC[] = "Microsecond"; +const char NAME_GROUP_NANO_SEC[] = "Nanosecond"; +const char NAME_GROUP_PICO_SEC[] = "Picosecond"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_USE_HEX[] = "UseHexadecimal"; + +TraceConfig::TraceConfig() { + mode = MODE_SYNC; + queueDepth = 1; + iolimit = 0; + groupOperation = 0; + groupByteOffset = 0; + groupByteLength = 0; + groupLBAOffset = 0; + groupLBALength = 0; + groupSecond = 0; + groupMiliSecond = 0; + groupMicroSecond = 0; + groupNanoSecond = 0; + groupPicoSecond = 0; + lbaSize = 512; + useHexadecimal = false; +} + +bool TraceConfig::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_FILE)) { + file = value; + } + else if (MATCH_NAME(NAME_TIMING_MODE)) { + mode = (TIMING_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_QUEUE_DEPTH)) { + queueDepth = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_IO_LIMIT)) { + iolimit = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LINE_REGEX)) { + regex = value; + } + else if (MATCH_NAME(NAME_GROUP_OPERATION)) { + groupOperation = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_BYTE_OFFSET)) { + groupByteOffset = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_BYTE_LENGTH)) { + groupByteLength = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_LBA_OFFSET)) { + groupLBAOffset = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_LBA_LENGTH)) { + groupLBALength = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_SEC)) { + groupSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_MILI_SEC)) { + groupMiliSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_MICRO_SEC)) { + groupMicroSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_NANO_SEC)) { + groupNanoSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_PICO_SEC)) { + groupPicoSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_USE_HEX)) { + useHexadecimal = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void TraceConfig::update() { + uint64_t idx = 0; + + // Remove leading spaces + for (auto c : regex) { + if (c != ' ') { + break; + } + + idx++; + } + + // Check double quotes + if (regex[0] == '"') { + regex = regex.substr(idx + 1); + } + else { + regex = regex.substr(idx); + } + + // Remove trailing spaces + while (regex.back() == ' ') { + regex.pop_back(); + } + + if (regex.back() == '"') { + regex.pop_back(); + } + + if (mode >= MODE_NUM) { + SimpleSSD::panic("Invalid timing mode specified"); + } +} + +uint64_t TraceConfig::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case TRACE_TIMING_MODE: + ret = mode; + break; + case TRACE_QUEUE_DEPTH: + ret = queueDepth; + break; + case TRACE_IO_LIMIT: + ret = iolimit; + break; + case TRACE_GROUP_OPERATION: + ret = groupOperation; + break; + case TRACE_GROUP_BYTE_OFFSET: + ret = groupByteOffset; + break; + case TRACE_GROUP_BYTE_LENGTH: + ret = groupByteLength; + break; + case TRACE_GROUP_LBA_OFFSET: + ret = groupLBAOffset; + break; + case TRACE_GROUP_LBA_LENGTH: + ret = groupLBALength; + break; + case TRACE_GROUP_SEC: + ret = groupSecond; + break; + case TRACE_GROUP_MILI_SEC: + ret = groupMiliSecond; + break; + case TRACE_GROUP_MICRO_SEC: + ret = groupMicroSecond; + break; + case TRACE_GROUP_NANO_SEC: + ret = groupNanoSecond; + break; + case TRACE_GROUP_PICO_SEC: + ret = groupPicoSecond; + break; + case TRACE_LBA_SIZE: + ret = lbaSize; + break; + } + + return ret; +} + +std::string TraceConfig::readString(uint32_t idx) { + std::string ret = ""; + + switch (idx) { + case TRACE_FILE: + ret = file; + break; + case TRACE_LINE_REGEX: + ret = regex; + break; + } + + return ret; +} + +bool TraceConfig::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case TRACE_USE_HEX: + ret = useHexadecimal; + break; + } + + return ret; +} + +} // namespace IGL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_config.hh b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_config.hh new file mode 100644 index 0000000000..2a5703a043 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_config.hh @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_TRACE_CONFIG__ +#define __IGL_TRACE_CONFIG__ + +#include "simplessd/sim/base_config.hh" + +namespace IGL { + +typedef enum { + TRACE_FILE, + TRACE_TIMING_MODE, + TRACE_QUEUE_DEPTH, + TRACE_IO_LIMIT, + TRACE_LINE_REGEX, + TRACE_GROUP_OPERATION, + TRACE_GROUP_BYTE_OFFSET, + TRACE_GROUP_BYTE_LENGTH, + TRACE_GROUP_LBA_OFFSET, + TRACE_GROUP_LBA_LENGTH, + TRACE_GROUP_SEC, + TRACE_GROUP_MILI_SEC, + TRACE_GROUP_MICRO_SEC, + TRACE_GROUP_NANO_SEC, + TRACE_GROUP_PICO_SEC, + TRACE_LBA_SIZE, + TRACE_USE_HEX, +} TRACE_CONFIG; + +typedef enum { + MODE_SYNC, + MODE_ASYNC, + MODE_STRICT, + MODE_NUM, +} TIMING_MODE; + +class TraceConfig : public SimpleSSD::BaseConfig { + private: + std::string file; + TIMING_MODE mode; + uint32_t queueDepth; + uint64_t iolimit; + std::string regex; + uint32_t groupOperation; + uint32_t groupByteOffset; + uint32_t groupByteLength; + uint32_t groupLBAOffset; + uint32_t groupLBALength; + uint32_t groupSecond; + uint32_t groupMiliSecond; + uint32_t groupMicroSecond; + uint32_t groupNanoSecond; + uint32_t groupPicoSecond; + uint32_t lbaSize; + bool useHexadecimal; + + public: + TraceConfig(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace IGL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_replayer.cc b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_replayer.cc new file mode 100644 index 0000000000..93fb318c46 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_replayer.cc @@ -0,0 +1,414 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/trace/trace_replayer.hh" + +#include "simplessd/sim/trace.hh" +#include "simplessd/util/algorithm.hh" + +namespace IGL { + +TraceReplayer::TraceReplayer(Engine &e, BIL::BlockIOEntry &b, + std::function &f, ConfigReader &c) + : IOGenerator(e, b, f), + useLBAOffset(false), + useLBALength(false), + nextIOIsSync(false), + reserveTermination(false), + io_submitted(0), + io_count(0), + read_count(0), + write_count(0), + io_depth(0) { + // Check file + auto filename = c.readString(CONFIG_TRACE, TRACE_FILE); + file.open(filename); + + if (!file.is_open()) { + SimpleSSD::panic("Failed to open trace file %s!", filename.c_str()); + } + + file.seekg(0, std::ios::end); + fileSize = file.tellg(); + file.seekg(0, std::ios::beg); + + // Create regex + try { + regex = std::regex(c.readString(CONFIG_TRACE, TRACE_LINE_REGEX)); + } + catch (std::regex_error &e) { + SimpleSSD::panic("Invalid regular expression!"); + } + + // Fill flags + mode = (TIMING_MODE)c.readUint(CONFIG_TRACE, TRACE_TIMING_MODE); + submissionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_SUBMISSION_LATENCY); + completionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_COMPLETION_LATENCY); + maxQueueDepth = c.readUint(CONFIG_TRACE, TRACE_QUEUE_DEPTH); + max_io = c.readUint(CONFIG_TRACE, TRACE_IO_LIMIT); + groupID[ID_OPERATION] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_OPERATION); + groupID[ID_BYTE_OFFSET] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_BYTE_OFFSET); + groupID[ID_BYTE_LENGTH] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_BYTE_LENGTH); + groupID[ID_LBA_OFFSET] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_LBA_OFFSET); + groupID[ID_LBA_LENGTH] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_LBA_LENGTH); + groupID[ID_TIME_SEC] = (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_SEC); + groupID[ID_TIME_MS] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_MILI_SEC); + groupID[ID_TIME_US] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_MICRO_SEC); + groupID[ID_TIME_NS] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_NANO_SEC); + groupID[ID_TIME_PS] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_PICO_SEC); + useHex = c.readBoolean(CONFIG_TRACE, TRACE_USE_HEX); + + if (groupID[ID_OPERATION] == 0) { + SimpleSSD::panic("Operation group ID cannot be 0"); + } + + if (groupID[ID_LBA_OFFSET] > 0) { + useLBAOffset = true; + } + if (groupID[ID_LBA_LENGTH] > 0) { + useLBALength = true; + } + + if (useLBALength || useLBAOffset) { + lbaSize = (uint32_t)c.readUint(CONFIG_TRACE, TRACE_LBA_SIZE); + + if (SimpleSSD::popcount(lbaSize) != 1) { + SimpleSSD::panic("LBA size should be power of 2"); + } + } + + if (!useLBAOffset && groupID[ID_BYTE_OFFSET] == 0) { + SimpleSSD::panic("Both LBA Offset and Byte Offset group ID cannot be 0"); + } + if (!useLBALength && groupID[ID_BYTE_LENGTH] == 0) { + SimpleSSD::panic("Both LBA Length and Byte Length group ID cannot be 0"); + } + + timeValids[0] = groupID[ID_TIME_SEC] > 0 ? true : false; + timeValids[1] = groupID[ID_TIME_MS] > 0 ? true : false; + timeValids[2] = groupID[ID_TIME_US] > 0 ? true : false; + timeValids[3] = groupID[ID_TIME_NS] > 0 ? true : false; + timeValids[4] = groupID[ID_TIME_PS] > 0 ? true : false; + + if (!(timeValids[0] || timeValids[1] || timeValids[2] || timeValids[3] || + timeValids[4])) { + if (mode == MODE_STRICT) { + SimpleSSD::panic("No valid time field specified"); + } + } + + firstTick = std::numeric_limits::max(); + + completionEvent = [this](uint64_t id) { iocallback(id); }; + + submitEvent = engine.allocateEvent([this](uint64_t) { submitIO(); }); +} + +TraceReplayer::~TraceReplayer() { + file.close(); +} + +void TraceReplayer::init(uint64_t bytesize, uint32_t bs) { + ssdSize = bytesize; + blocksize = bs; + + if ((useLBALength || useLBAOffset) && lbaSize < bs) { + SimpleSSD::warn("LBA size of trace file is smaller than SSD's LBA size"); + } +} + +void TraceReplayer::begin() { + initTime = engine.getCurrentTick(); + + parseLine(); + + if (mode == MODE_STRICT) { + firstTick = linedata.tick; + } + else { + firstTick = initTime; + } + + if (reserveTermination) { + SimpleSSD::warn("No I/O submitted. Check regular expression."); + + endCallback(); + } + else { + submitIO(); + } +} + +void TraceReplayer::printStats(std::ostream &out) { + uint64_t tick = engine.getCurrentTick(); + + out << "*** Statistics of Trace Replayer ***" << std::endl; + out << "Tick: " << tick << std::endl; + out << "Time (ps): " << firstTick - initTime << " - " << tick << " (" + << tick + firstTick - initTime << ")" << std::endl; + out << "I/O (bytes): " << io_submitted << " (" + << std::to_string((double)io_submitted / tick * 1000000000000.) << " B/s)" + << std::endl; + out << "I/O (counts): " << io_count << " (Read: " << read_count + << ", Write: " << write_count << ")" << std::endl; + out << "*** End of statistics ***" << std::endl; + + bioEntry.printStats(out); +} + +void TraceReplayer::getProgress(float &val) { + if (max_io == 0) { + // If I/O count is unlimited, use file pointer for fast progress calculation + uint64_t ptr; + + { + std::lock_guard guard(m); + ptr = file.tellg(); + } + + val = (float)ptr / fileSize; + } + else { + // Use submitted I/O count in progress calculation + // If trace file contains I/O requests smaller than max_io, progress value + // cannot reach 1.0 (100%) + val = (float)io_count / max_io; + } +} + +uint64_t TraceReplayer::mergeTime(std::smatch &match) { + uint64_t tick = 0; + bool valid = true; + + if (timeValids[0] && match.size() > groupID[ID_TIME_SEC]) { + tick += strtoul(match[groupID[ID_TIME_SEC]].str().c_str(), nullptr, 10) * + 1000000000000ULL; + } + else if (timeValids[0]) { + valid = false; + } + + if (timeValids[1] && match.size() > groupID[ID_TIME_MS]) { + tick += strtoul(match[groupID[ID_TIME_MS]].str().c_str(), nullptr, 10) * + 1000000000ULL; + } + else if (timeValids[1]) { + valid = false; + } + + if (timeValids[2] && match.size() > groupID[ID_TIME_US]) { + tick += strtoul(match[groupID[ID_TIME_US]].str().c_str(), nullptr, 10) * + 1000000ULL; + } + else if (timeValids[2]) { + valid = false; + } + + if (timeValids[3] && match.size() > groupID[ID_TIME_NS]) { + tick += strtoul(match[groupID[ID_TIME_NS]].str().c_str(), nullptr, 10) * + 1000ULL; + } + else if (timeValids[3]) { + valid = false; + } + + if (timeValids[4] && match.size() > groupID[ID_TIME_PS]) { + tick += strtoul(match[groupID[ID_TIME_PS]].str().c_str(), nullptr, 10); + } + else if (timeValids[4]) { + valid = false; + } + + if (!valid) { + SimpleSSD::panic("Time parse failed"); + } + + return tick; +} + +BIL::BIO_TYPE TraceReplayer::getType(std::string type) { + io_count++; + + switch (type[0]) { + case 'r': + case 'R': + read_count++; + + return BIL::BIO_READ; + case 'w': + case 'W': + write_count++; + + return BIL::BIO_WRITE; + case 'f': + case 'F': + return BIL::BIO_FLUSH; + case 't': + case 'T': + case 'd': + case 'D': + return BIL::BIO_TRIM; + } + + return BIL::BIO_NUM; +} + +void TraceReplayer::parseLine() { + std::string line; + std::smatch match; + + // Read line + while (true) { + bool eof = false; + + { + std::lock_guard guard(m); + + eof = file.eof(); + std::getline(file, line); + } + + if (eof) { + reserveTermination = true; + + if (io_depth == 0) { + // No on-the-fly I/O + endCallback(); + } + + return; + } + if (std::regex_match(line, match, regex)) { + break; + } + } + + // Get time + linedata.tick = mergeTime(match); + + // Fill BIO + if (useLBAOffset) { + linedata.offset = strtoul(match[groupID[ID_LBA_OFFSET]].str().c_str(), + nullptr, useHex ? 16 : 10) * + lbaSize; + } + else { + linedata.offset = strtoul(match[groupID[ID_BYTE_OFFSET]].str().c_str(), + nullptr, useHex ? 16 : 10); + } + + if (useLBALength) { + linedata.length = strtoul(match[groupID[ID_LBA_LENGTH]].str().c_str(), + nullptr, useHex ? 16 : 10) * + lbaSize; + } + else { + linedata.length = strtoul(match[groupID[ID_BYTE_LENGTH]].str().c_str(), + nullptr, useHex ? 16 : 10); + } + + // This function increases I/O count + linedata.type = getType(match[groupID[ID_OPERATION]].str()); +} + +void TraceReplayer::submitIO() { + BIL::BIO bio; + + if (linedata.type == BIL::BIO_NUM) { + SimpleSSD::panic("Unexpected request type."); + } + + bio.callback = completionEvent; + bio.id = io_count; + bio.type = linedata.type; + bio.offset = linedata.offset; + bio.length = linedata.length; + + bioEntry.submitIO(bio); + + io_depth++; + + if ((max_io != 0 && io_count >= max_io)) { + reserveTermination = true; + + return; + } + + parseLine(); + + if (reserveTermination) { + return; + } + + switch (mode) { + case MODE_STRICT: + engine.scheduleEvent(submitEvent, linedata.tick - firstTick + initTime); + break; + case MODE_ASYNC: + rescheduleSubmit(submissionLatency); + break; + default: + break; + } +} + +void TraceReplayer::iocallback(uint64_t) { + io_depth--; + + if (reserveTermination) { + // Everything is done + if (io_depth == 0) { + endCallback(); + } + } + + if (mode == MODE_SYNC || nextIOIsSync) { + // MODE_ASYNC submission blocked by I/O depth limitation + // Let's submit here + nextIOIsSync = false; + + rescheduleSubmit(submissionLatency + completionLatency); + } +} + +void TraceReplayer::rescheduleSubmit(uint64_t breakTime) { + if (mode == MODE_ASYNC) { + if (io_depth >= maxQueueDepth) { + nextIOIsSync = true; + + return; + } + } + else if (mode == MODE_STRICT) { + return; + } + + engine.scheduleEvent(submitEvent, engine.getCurrentTick() + breakTime); +} + +} // namespace IGL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_replayer.hh b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_replayer.hh new file mode 100644 index 0000000000..10896d8a1a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/igl/trace/trace_replayer.hh @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_TRACE_REPLAYER__ +#define __IGL_TRACE_REPLAYER__ + +#include +#include +#include +#include +#include + +#include "bil/entry.hh" +#include "igl/io_gen.hh" +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace IGL { + +class TraceReplayer : public IOGenerator { + private: + enum { + ID_OPERATION, + ID_BYTE_OFFSET, + ID_BYTE_LENGTH, + ID_LBA_OFFSET, + ID_LBA_LENGTH, + ID_TIME_SEC, + ID_TIME_MS, + ID_TIME_US, + ID_TIME_NS, + ID_TIME_PS, + ID_NUM + }; + + std::mutex m; + + std::ifstream file; + std::regex regex; + + uint64_t fileSize; + + TIMING_MODE mode; + uint64_t submissionLatency; + uint64_t completionLatency; + uint32_t maxQueueDepth; // Only used in MODE_ASYNC + + bool useLBAOffset; + bool useLBALength; + uint32_t lbaSize; + uint32_t groupID[ID_NUM]; + bool timeValids[5]; + bool useHex; + + uint64_t ssdSize; + uint32_t blocksize; + + uint64_t initTime; // Only used in MODE_STRICT + uint64_t firstTick; // Only used in MODE_STRICT + bool nextIOIsSync; // Only used in MODE_ASYNC + + bool reserveTermination; + + uint64_t max_io; + uint64_t io_submitted; // Submitted I/O in bytes + uint64_t io_count; // I/O count created and submitted + uint64_t read_count; + uint64_t write_count; + + uint64_t io_depth; + + uint64_t mergeTime(std::smatch &); + BIL::BIO_TYPE getType(std::string); + void parseLine(); + void rescheduleSubmit(uint64_t); + + struct TraceLine { + uint64_t tick; + uint64_t offset; + uint64_t length; + BIL::BIO_TYPE type; + + TraceLine() : tick(0), offset(0), length(0), type(BIL::BIO_NUM) {} + } linedata; + + SimpleSSD::Event submitEvent; + SimpleSSD::EventFunction completionEvent; + + void submitIO(); + void iocallback(uint64_t); + + public: + TraceReplayer(Engine &, BIL::BlockIOEntry &, std::function &, + ConfigReader &); + ~TraceReplayer(); + + void init(uint64_t, uint32_t) override; + void begin() override; + void printStats(std::ostream &) override; + void getProgress(float &) override; +}; + +} // namespace IGL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/ChangeLog b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/ChangeLog new file mode 100644 index 0000000000..e05228e48c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/ChangeLog @@ -0,0 +1,121 @@ +Change Log: + +DRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a user + to access the tool through an API and log commands and their + corresponding time stamps, removing the need to store large + command traces on disk. In addition, cycle counting variables + have been changed to int64 to support longer simulations. + The library can be compiled without Xerces to remove an optional + dependency and reduce the size of the binary. + * Improved robustness. The latest build is automatically checked + out on a test server, compiled, and tested to verify that the + output matches an expected reference. The code is also compiled + with a large number of warning flags enabled and treats all + warnings as errors. + * Bug fix: Fixed bug in io/termination energy calculation. + * Bug fix: Fixed bug in calculation of auto precharge cycle. + +DRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM Power + Calculator, for all supported DRAM generations. In the case of + Wide IO DRAMs, these measures are already included in the provided + current specifications. This feature enables support for multi-rank + DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies + (equivalent to ranks). To indicate use of multi-rank DRAMs or + multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in + the memory specification XMLs can be employed. Note: The DRAM + command scheduler does not support multi-rank/multi-die DRAMs yet. + Only the power estimation component of DRAMPower has been updated + to support them. The current measures for dual-rank DRAMs only + reflect those for the active rank and not the idle rank. The + default state of the idle rank is assumed to be the same as the + current memory state, for background power estimation. Hence, + rank information in the command trace is not required. + * Added warning messages: New warning messages are provided, to + identify if the memory or bank state is inconsistent in the + user-defined traces. Towards this, a state check is performed on + every memory command issued. + * Improved run-time options: Users can now point directly to the + memory specification XML, instead of just the memory ID. Also, + users can optionally include IO and termination power estimates + (for both single and dual rank DRAMs) using '-r' flag in the + command line options. + * Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was + kept ON in the Self-Refresh mode, when it can be turned OFF. This + bug has now been fixed. (2) Precharge All (PREA) always considered + precharging of all banks. It has now been modified to consider + precharging of the open/active banks alone. + +DRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the already + supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM memories. + * Added DRAM Command Scheduler: To support users of DRAMPower + without access to DRAM controllers, we have added a simple DRAM + command scheduler that dynamically schedules DRAM commands as if + it were a memory controller. The scheduler assumes closed-page + policy, employs ASAP scheduling for DRAM commands (i.e. schedules + commands as soon as timing constraints are met), performs FCFS + scheduling on DRAM transactions and supports all the different + DRAM generations supported by the power model. The generated DRAM + command schedule is also analyzable for real-time applications. + Users can also select speculative usage of power-down or + self-refresh modes (if needed) for idle periods between + transactions. It should be noted that using this command scheduler + is optional and it can be (de-)selected during run-time and users + can switch back to the previously used DRAM command interface as + in the earlier versions. + * Improved run-time options: Users can specify the memory and the + trace file to be used by DRAMPower using command line options. + Additionally, if the DRAM command scheduler is being used, the + users can specify the degree of bank interleaving required, the + request size and power-down or self-refresh options. Also, for + DDR4 memories the bank group interleaving can be specified using + command line options. + * Bug fixes: (1) For command traces ending with a RD/WR/RDA/WRA + command, the tool did not consider completion of operations when + estimating the total trace energy. The missing cycles are now + taken into account. + (2) The IDD5 (REF current) specification for WIDE IO SDR memory + specifications only included 2 banks for refreshes instead of all + four. We would like to thank David Roberts from AMD for spotting + the issue in our DATE'13 article. These measures have been updated. + (3) When estimating precharge cycle for commands with + auto-precharge, (RDA/WRA), the command analysis tool employed the + last activation cycle in the entire DRAM instead of the particular + DRAM bank. This bug has been fixed in this release. + +DRAMPower v2.1 - * Added support for variation-aware power estimation, for a + selection of DDR3 memories manufactured using 50nm process + technology, based on the Monte-Carlo analysis presented in our + DAC'13 article. + +DRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories, besides + the already supported DDR2/DDR3 memories. + * Faster analysis: The trace analysis component in DRAMPower v2.0 + triggers the evaluation only during memory state transitions + (between active, precharged, active and precharged power-down, + refresh, self-refresh and power-up states) and not on every clock + cycle, as was the case till the last version. This optimization + speeds up the power simulations using DRAMPower by several times + over cycle-accurate analysis, resulting in fast power analysis, + without affecting the accuracy of the trace analysis or the + reported power and energy estimates. + * Verification effort: Our power model was verified by the + Microelectronic System Design group at TU Kaiserslautern using + circuit-level SPICE simulations of a DRAM cross-section. As a + result of this verification effort, a couple of power equations + have been modified for Refresh and Self-refresh operations. The + difference between the power and energy estimates reported by our + updated model and the equivalent circuit-level simulations is + < 2% for all memory operations of any granularity for all memories + supported by DRAMPower. + +DRAMPower v1.2 - * Supports different power-down and self-refresh modes in DDR2 and + DDR3 DRAM memories. + * Bug fix: Refresh power consumption equation in DRAMPower v1, + incorrectly subtracted IDD2n (precharge background current) + instead of IDD3n (active background current) from IDD5 (total + refresh current). This error has been rectified in this version. + +DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and estimates + power and energy consumption numbers for the trace. + * It supports the basic memory operations like read, write, refresh, + activate and (auto) precharge in DDR2 and DDR3 memories. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/README.md b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/README.md new file mode 100644 index 0000000000..b5843b0197 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/README.md @@ -0,0 +1,263 @@ +# DRAM Power Model (DRAMPower) +[![Build Status](https://travis-ci.org/ravenrd/DRAMPower.svg?branch=master)](https://travis-ci.org/ravenrd/DRAMPower) +[![Coverage Status](https://coveralls.io/repos/ravenrd/DRAMPower/badge.png?branch=master)](https://coveralls.io/r/ravenrd/DRAMPower?branch=master) +## 0. Releases + +The last official release can be found here: +https://github.com/ravenrd/DRAMPower/releases/tag/4.0 + +The master branch of the repository should be regarded as the bleeding-edge version, which has all the latest features, but also all the latest bugs. Use at your own discretion. + +## 1. Installation + +Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. [drampower.cc](src/cli/drampower.cc) file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: +```bash +make -j4 +``` +This command will download a set of trace files from https://github.com/Sv3n/DRAMPowerTraces which can be used as test input for the tool. + +## 2. Required Packages + +The tool was verified on Ubuntu 14.04 using: + + * xerces-c (libxerces-c-dev) - v3.1 with Xerces development package + * gcc - v4.4.3 + +## 3. Directory Structure + * src/: contains the source code of the DRAMPower tool that covers the power model, the command scheduler and the trace analysis tool. + * memspecs/ : contains the memory specification XMLs, which give the architectural, timing and current/voltage details for different DRAM memories. + * traces/ : contains 4 sample DRAM transaction traces and 1 sample command trace (after the installation / compilation) + * test/ : contains test script and reference output + +## 4. Trace Specification +### Command Traces +If the command-level interface is being used, a command trace can be logged in a file. +An example is given in ```traces/commands.trace``` + +The format it uses is: ```,,```. +For example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is +mentioned in [MemCommand.h](src/MemCommand.h) and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be +specified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder. + +### Transaction Traces +If the transaction-level interface is being used, a transaction trace can be logged. + +The format it uses is: ```,,
```. +For example, "35,READ,0x80028", where READ/WRITE can be the transaction type and the logical address (32-bits long and byte addressable) less than the maximum supported DRAM capacity of 4GB (32Gb). + +The tool uses a flexible and efficient memory map as follows: specified in HEX (0x). Timestamp is in clock cycles (cc) and maximum {row}-{bank}-{column}-{BI}-{BC}-{BGI}-{BL} +Here, BI gives the degree of bank interleaving, BC gives the burst size (count), BGI gives the degree of bank group interleaving (for DDR4) and BL gives the burst length used by the device. +Dual-Rank addressing is not yet supported. The BC and BL address bits are derived from the column address bits, whereas the BI and BGI bits are derived from the bank address bits. + +Four sample MediaBench application transaction traces have been provided. The MediaBench applications include: (1) EPIC Encoder, (2) JPEG Encoder, (3) H263 Encoder and (4) MPEG2 Encoder. These applications were independently executed on the SimpleScalar simulator with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and logged them as transaction traces. These can be used with our command scheduler to generate equivalent command traces for any DRAM memory specified. + +## 5. Usage + +[drampower.cc](src/cli/drampower.cc) is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. + +To use DRAMPower at the command-level (command trace), after make, use the following: +```bash +./drampower -m -c +``` +To use DRAMPower at the transaction-level (command scheduler), after make, use the +following: +```bash +./drampower -m -t +``` +Additional options when using transactions trace [-t] include: + * [-i] `````` + * [-s] `````` + * [-g] `````` + * [-p] ```<0 - No Power-Down, 1 - Power-Down, 2 - Self-Refresh>``` + +Also, when using either the commands trace or the transactions trace, the user can +optionally include IO and Termination power estimates (obtained from Micron's DRAM +Power Calculator). To enable the same, the '-r' flag can be employed in command line. + +If these options are not used, the default values assumed are: +* interleaving = 1 +* request size = burst length * I/O width / 8 (in bytes) (from memory XMLs) +* power saving = No power-down +* bank group interleaving = 1 +* IO and termination = OFF (0) +* Burst size (count) of 1 + +## 6. Memory Specifications + +36 sample memory specifications are given in the XMLs targeting DDR2/DDR3/DDR4, LPDDR/LPDDR2/LPDDR3 and WIDE IO DRAM devices. The memory specifications are based on 1Gb DDR2, 1Gb & 2Gb DDR3, 2Gb LPDDR/LPDDR2 and 4Gb DDR4/LPDDR3 Micron datasheets and the 256Mb Wide IO SDR specifications are based on JEDEC timing specifications and circuit-level IDD measurements by TU Kaiserslautern, inplace of the as yet unavailable vendor datasheets. 4 of the memory specifications target dual-rank DDR3 DIMMs. + +Note: The timing specifications in the XMLs are in clock cycles (cc). The current specifications for Reading and Writing do not include the I/O consumption. They are computed and included seperately based on Micron Power Calculator. The IDD measures associated with different power supply sources of equal measure (VDD2, VDDCA and VDDQ) for LPDDR2, LPDDR3, DDR4 and WIDE IO memories have been added up together for simplicity, since it does not impact power computation accuracy. The current measures for dual-rank DIMMs reflect only the measures for the active rank. The default state of the idle rank is assumed to be the same as the complete memory state, for background power estimation. Accordingly, in all dual-rank memory specifications, IDD2P0 has been subtracted from the active currents and all background currents have been halved. They are also accounted for seperately by the power model. Stacking multiple Wide IO DRAM dies can also be captured by the nbrOfRanks parameter. + +## 7. Variation-aware Power And Energy Estimation + +15 of the included datasheets reflect the impact of process-variations on DRAM currents for a selection of DDR3 memories manufactured at 50nm process technology. These memories include: +(1) MICRON_128MB_DDR3-1066_8bit - revision G +(2) MICRON_128MB_DDR3-1066_16bit - revision G +(3) MICRON_128MB_DDR3-1600_8bit - revision G +(4) MICRON_256MB_DDR3-1066_8bit - revision D +(5) MICRON_256MB_DDR3-1600_16bit - revision D + +The original vendor-provided datasheet current specifications are given in XMLs +without suffixes such as _mu, _2s and _3s. XMLs including suffixes indicate that the +current measures are either: (1) typical (mu), or (2) include +2 sigma variation (2s), +or (3) include +3 sigma variation (3s). These measures are derived based on the +Monte-Carlo analysis performed on our SPICE-based DRAM cross-section. + +To include these XMLs in your simulations, simply use them as the target memory. + +## 8. Example Usage + +An example of using this tool is provided below. To compile the example, +use the Makefile and make sure the gcc and Xerces-c are installed. Then, run: +``` +make -j4 +``` +After this, run with the command trace or the transaction trace, as described before: +``` +./drampower -m memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml -t traces/mediabench-epic.trace -r +``` +The output should be something like this: + +``` +* Parsing memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml +* Analysis start time: Thu Aug 4 15:43:52 2016 +* Analyzing the input trace +* Trace Details: + +#ACT commands: 96984 +#RD + #RDA commands: 67179 +#WR + #WRA commands: 29805 +#PRE (+ PREA) commands: 96984 +#REF commands: 13168 +#Active Cycles: 2519793 + #Active Idle Cycles: 196851 + #Active Power-Up Cycles: 0 + #Auto-Refresh Active cycles during Self-Refresh Power-Up: 0 +#Precharged Cycles: 52261474 + #Precharged Idle Cycles: 51649629 + #Precharged Power-Up Cycles: 0 + #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: 0 + #Self-Refresh Power-Up Cycles: 0 +Total Idle Cycles (Active + Precharged): 51846480 +#Power-Downs: 0 + #Active Fast-exit Power-Downs: 0 + #Active Slow-exit Power-Downs: 0 + #Precharged Fast-exit Power-Downs: 0 + #Precharged Slow-exit Power-Downs: 0 +#Power-Down Cycles: 0 + #Active Fast-exit Power-Down Cycles: 0 + #Active Slow-exit Power-Down Cycles: 0 + #Auto-Refresh Active cycles during Self-Refresh: 0 + #Precharged Fast-exit Power-Down Cycles: 0 + #Precharged Slow-exit Power-Down Cycles: 0 + #Auto-Refresh Precharged cycles during Self-Refresh: 0 +#Auto-Refresh Cycles: 776912 +#Self-Refreshes: 0 +#Self-Refresh Cycles: 0 +---------------------------------------- +Total Trace Length (clock cycles): 54781267 +---------------------------------------- + +* Trace Power and Energy Estimates: + +ACT Cmd Energy: 109175234.52 pJ +PRE Cmd Energy: 47764165.10 pJ +RD Cmd Energy: 49155365.85 pJ +WR Cmd Energy: 23486116.32 pJRD I/O Energy: 20872124.58 pJ +WR Termination Energy: 47419587.24 pJ +ACT Stdby Energy: 283653996.25 pJ + Active Idle Energy: 22159587.24 pJ + Active Power-Up Energy: 0.00 pJ + Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ +PRE Stdby Energy: 5147706163.23 pJ + Precharge Idle Energy: 5087440004.69 pJ + Precharged Power-Up Energy: 0.00 pJ + Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ + Self-Refresh Power-Up Energy: 0.00 pJ +Total Idle Energy (Active + Precharged): 5109599591.93 pJ +Total Power-Down Energy: 0.00 pJ + Fast-Exit Active Power-Down Energy: 0.00 pJ + Slow-Exit Active Power-Down Energy: 0.00 pJ + Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ + Fast-Exit Precharged Power-Down Energy: 0.00 pJ + Slow-Exit Precharged Power-Down Energy: 0.00 pJ + Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ +Auto-Refresh Energy: 262371782.36 pJ +Self-Refresh Energy: 0.00 pJ +---------------------------------------- +Total Trace Energy: 5991604535.46 pJ +Average Power: 58.30 mW +---------------------------------------- +* Power Computation End time: Thu Aug 4 15:43:59 2016 +* Total Simulation time: 7 seconds +* +``` + +As can be noticed, the tool performs DRAM command scheduling and reports the number +of activates, precharges, reads, writes, refreshes, power-downs and self-refreshes +besides the number of clock cycles spent in the active and precharged states, in the +power-down (fast/slow-exit) and self-refresh states and in the idle mode. It also +reports the energy consumption of these components, besides the IO and Termination +components in pJ (pico Joules) and the average power consumption of the trace in mW. +It also reports the simulation start/end times and the total simulation time in seconds. + +## 9. DRAMPower Library + +The DRAMPower tool has an additional feature and can be used as a library. +In order to use the library run "make lib", include [LibDRAMPower.h](src/libdrampower/LibDRAMPower.h) in your project and +link the file src/libdrampower.a with your project. +Examples for the usage of the library are [lib_test.cc](test/libdrampowertest/lib_test.cc) and [window_example.cc](test/libdrampowertest/window_example.cc). + +## 10. Authors & Acknowledgment + +The tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven +and verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations. This tool has been developed by +Karthik Chandrasekar with Yonghui Li under the supervision of Dr. Benny Akesson and Prof. Kees Goossens. The IO and Termination Power measures have been employed +from Micron's DRAM Power Calculator. If you decide to use DRAMPower in your research, please cite one of the following references: + +**To cite the DRAMPower Tool:** +``` +[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool +Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens +URL: http://www.drampower.info +``` + +**To cite the DRAM power model:** +``` +[2] "Improved Power Modeling of DDR SDRAMs" +Karthik Chandrasekar, Benny Akesson, and Kees Goossens +In Proc. 14th Euromicro Conference on Digital System Design (DSD), 2011 +``` + +**To cite the 3D-DRAM power model:** +``` +[3] "System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs" +Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens +In Proc. Design, Automation and Test in Europe (DATE), 2013 +``` + +**To cite variation-aware DRAM power estimation:** +``` +[4] "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach" +Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens +In Proc. Design Automation Conference (DAC), 2013 +``` + +## 11. Contact Information + +Further questions about the tool and the power model can be directed to: + +Benny Akesson (k.b.akesson@tue.nl) + +Feel free to ask for updates to the tool's features and please do report any bugs +and errors you encounter. This will encourage us to continuously improve the tool. + +## Disclaimer + +The tool does not check the timing accuracy of the user's memory command trace +and the use of commands and memory modes. It is expected that the user employs +a valid trace generated using a DRAM memory controller or simulator, which +satisfies all memory timing constraints and other requirements. The user DOES +NOT get ANY WARRANTIES when using this tool. This software is released under the +BSD 3-Clause License. By using this software, the user implicitly agrees to the +licensing terms. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CAHelpers.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CAHelpers.cc new file mode 100644 index 0000000000..e7df883187 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CAHelpers.cc @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +#include // std::count +#include + +#include "CommandAnalysis.h" + +using std::cerr; +using std::endl; +using std::string; + +using namespace Data; + + +// To get the time of completion of the issued command +// Derived based on JEDEC specifications + +int64_t CommandAnalysis::timeToCompletion(MemCommand::cmds type) +{ + int64_t offset = 0; + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + + if (type == MemCommand::RD) { + offset = memTimingSpec.RL + + memTimingSpec.DQSCK + 1 + (memArchSpec.burstLength / + memArchSpec.dataRate); + } else if (type == MemCommand::WR) { + offset = memTimingSpec.WL + + (memArchSpec.burstLength / memArchSpec.dataRate) + + memTimingSpec.WR; + } else if (type == MemCommand::ACT) { + offset = memTimingSpec.RCD; + } else if ((type == MemCommand::PRE) || (type == MemCommand::PREA)) { + offset = memTimingSpec.RP; + } + return offset; +} // CommandAnalysis::timeToCompletion + + +// Returns the number of active banks based on the bank_state vector. +unsigned CommandAnalysis::get_num_active_banks(void) +{ + return (unsigned)std::count(bank_state.begin(), bank_state.end(), BANK_ACTIVE); +} + +// Naming-standard compliant wrapper +unsigned CommandAnalysis::nActiveBanks(void) +{ + return CommandAnalysis::get_num_active_banks(); +} + +bool CommandAnalysis::isPrecharged(unsigned bank) +{ + return bank_state[bank] == BANK_PRECHARGED; +} + +void CommandAnalysis::printWarningIfActive(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + if (get_num_active_banks() != 0) { + printWarning(warning, type, timestamp, bank); + } +} + +void CommandAnalysis::printWarningIfNotActive(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + if (get_num_active_banks() == 0) { + printWarning(warning, type, timestamp, bank); + } +} + +void CommandAnalysis::printWarningIfPoweredDown(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + if (mem_state != 0) { + printWarning(warning, type, timestamp, bank); + } +} + +void CommandAnalysis::printWarning(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + cerr << "WARNING: " << warning << endl; + cerr << "Command: " << type << ", Timestamp: " << timestamp << + ", Bank: " << bank << endl; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdHandlers.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdHandlers.cc new file mode 100644 index 0000000000..ac05d22f44 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdHandlers.cc @@ -0,0 +1,627 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#include "CommandAnalysis.h" + +using std::cerr; +using std::endl; +using std::max; + +using namespace Data; + + +int64_t zero_guard(int64_t cycles_in, const char* warning) +{ + // Calculate max(0, cycles_in) + int64_t zero = 0; + if (warning != nullptr && cycles_in < 0) { + // This line is commented out for now, we will attempt to remove the situations where + // these warnings trigger later. + // cerr << "WARNING: " << warning << endl; + } + return max(zero, cycles_in); +} + +void CommandAnalysis::handleAct(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::ACT, timestamp, bank); + // If command is ACT - update number of acts, bank state of the + // target bank, first and latest activation cycle and the memory + // state. Update the number of precharged/idle-precharged cycles. + // If the bank is already active ignore the command and generate a + // warning. + if (isPrecharged(bank)) { + numberofactsBanks[bank]++; + + if (nActiveBanks() == 0) { + // Here a memory state transition to ACT is happening. Save the + // number of cycles in precharge state (increment the counter). + first_act_cycle = timestamp; + precycles += zero_guard(timestamp - last_pre_cycle, "1 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + } + + bank_state[bank] = BANK_ACTIVE; + latest_act_cycle = timestamp; + } else { + printWarning("Bank is already active!", MemCommand::ACT, timestamp, bank); + } +} + +void CommandAnalysis::handleRd(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::RD, timestamp, bank); + // If command is RD - update number of reads and read cycle. Check + // for active idle cycles (if any). + if (isPrecharged(bank)) { + printWarning("Bank is not active!", MemCommand::RD, timestamp, bank); + } + numberofreadsBanks[bank]++; + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + latest_read_cycle = timestamp; +} + +void CommandAnalysis::handleWr(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::WR, timestamp, bank); + // If command is WR - update number of writes and write cycle. Check + // for active idle cycles (if any). + if (isPrecharged(bank)) { + printWarning("Bank is not active!", MemCommand::WR, timestamp, bank); + } + numberofwritesBanks[bank]++; + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + latest_write_cycle = timestamp; +} + +void CommandAnalysis::handleRef(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::REF, timestamp, bank); + // If command is REF - update number of refreshes, set bank state of + // all banks to ACT, set the last PRE cycles at RFC-RP cycles from + // timestamp, set the number of active cycles to RFC-RP and check + // for active and precharged cycles and idle active and idle + // precharged cycles before refresh. Change memory state to 0. + printWarningIfActive("One or more banks are active! REF requires all banks to be precharged.", MemCommand::REF, timestamp, bank); + numberofrefs++; + idle_pre_update(timestamp, latest_pre_cycle); + first_act_cycle = timestamp; + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); + precycles += zero_guard(timestamp - last_pre_cycle, "2 last_pre_cycle is in the future."); + last_pre_cycle = timestamp + memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + latest_pre_cycle = last_pre_cycle; + actcycles += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + for (auto &e : actcyclesBanks) { + e += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + } + for (auto& bs : bank_state) { + bs = BANK_PRECHARGED; + } +} + +void CommandAnalysis::handleRefB(unsigned bank, int64_t timestamp) +{ + // A REFB command requires a previous PRE command. + if (isPrecharged(bank)) { + // This previous PRE command handler is also responsible for keeping the + // memory state updated. + // Here we consider that the memory state is not changed in order to keep + // things simple, since the transition from PRE to ACT state takes time. + numberofrefbBanks[bank]++; + // Length of the refresh: here we have an approximation, we consider tRP + // also as act cycles because the bank will be precharged (stable) after + // tRP. + actcyclesBanks[bank] += memSpec.memTimingSpec.RAS + memSpec.memTimingSpec.RP; + } else { + printWarning("Bank must be precharged for REFB!", MemCommand::REFB, timestamp, bank); + } +} + +void CommandAnalysis::handlePre(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::PRE, timestamp, bank); + // If command is explicit PRE - update number of precharges, bank + // state of the target bank and last and latest precharge cycle. + // Calculate the number of active cycles if the memory was in the + // active state before, but there is a state transition to PRE now + // (i.e., this is the last active bank). + // If the bank is already precharged ignore the command and generate a + // warning. + + // Precharge only if the target bank is active + if (bank_state[bank] == BANK_ACTIVE) { + numberofpresBanks[bank]++; + actcyclesBanks[bank] += zero_guard(timestamp - first_act_cycle_banks[bank], "first_act_cycle is in the future (bank)."); + // Since we got here, at least one bank is active + assert(nActiveBanks() != 0); + + if (nActiveBanks() == 1) { + // This is the last active bank. Therefore, here a memory state + // transition to PRE is happening. Let's increment the active cycle + // counter. + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + last_pre_cycle = timestamp; + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + } + + bank_state[bank] = BANK_PRECHARGED; + latest_pre_cycle = timestamp; + } else { + printWarning("Bank is already precharged!", MemCommand::PRE, timestamp, bank); + } +} + +void CommandAnalysis::handlePreA(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::PREA, timestamp, bank); + // If command is explicit PREA (precharge all banks) - update + // number of precharges by the number of active banks, update the bank + // state of all banks to PRE and set the precharge cycle (the cycle in + // which the memory state changes from ACT to PRE, aka last_pre_cycle). + // Calculate the number of active cycles if the memory was in the + // active state before, but there is a state transition to PRE now. + + if (nActiveBanks() > 0) { + // Active banks are being precharged + // At least one bank was active, therefore the current memory state is + // ACT. Since all banks are being precharged a memory state transition + // to PRE is happening. Add to the counter the amount of cycles the + // memory remained in the ACT state. + + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + last_pre_cycle = timestamp; + + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + // Active banks are being precharged + numberofpresBanks[b] += 1; + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)."); + } + } + + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + + latest_pre_cycle = timestamp; + // Reset the state for all banks to precharged. + for (auto& bs : bank_state) { + bs = BANK_PRECHARGED; + } + } else { + printWarning("All banks are already precharged!", MemCommand::PREA, timestamp, bank); + } +} + +void CommandAnalysis::handlePdnFAct(unsigned bank, int64_t timestamp) +{ + // If command is fast-exit active power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // fast-exit active power-down. Save states of all the banks from + // the cycle before entering active power-down, to be returned to + // after powering-up. Update active and active idle cycles. + printWarningIfNotActive("All banks are precharged! Incorrect use of Active Power-Down.", MemCommand::PDN_F_ACT, timestamp, bank); + f_act_pdns++; + last_bank_state = bank_state; + pdn_cycle = timestamp; + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)."); + } + } + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + mem_state = CommandAnalysis::MS_PDN_F_ACT; +} + +void CommandAnalysis::handlePdnSAct(unsigned bank, int64_t timestamp) +{ + // If command is slow-exit active power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // slow-exit active power-down. Save states of all the banks from + // the cycle before entering active power-down, to be returned to + // after powering-up. Update active and active idle cycles. + printWarningIfNotActive("All banks are precharged! Incorrect use of Active Power-Down.", MemCommand::PDN_S_ACT, timestamp, bank); + s_act_pdns++; + last_bank_state = bank_state; + pdn_cycle = timestamp; + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)."); + } + } + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + mem_state = CommandAnalysis::MS_PDN_S_ACT; +} + +void CommandAnalysis::handlePdnFPre(unsigned bank, int64_t timestamp) +{ + // If command is fast-exit precharged power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // fast-exit precahrged power-down. Update precharged and precharged + // idle cycles. + printWarningIfActive("One or more banks are active! Incorrect use of Precharged Power-Down.", MemCommand::PDN_F_PRE, timestamp, bank); + f_pre_pdns++; + pdn_cycle = timestamp; + precycles += zero_guard(timestamp - last_pre_cycle, "3 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + mem_state = CommandAnalysis::MS_PDN_F_PRE; +} + +void CommandAnalysis::handlePdnSPre(unsigned bank, int64_t timestamp) +{ + // If command is slow-exit precharged power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // slow-exit precahrged power-down. Update precharged and precharged + // idle cycles. + printWarningIfActive("One or more banks are active! Incorrect use of Precharged Power-Down.", MemCommand::PDN_S_PRE, timestamp, bank); + s_pre_pdns++; + pdn_cycle = timestamp; + precycles += zero_guard(timestamp - last_pre_cycle, "4 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + mem_state = CommandAnalysis::MS_PDN_S_PRE; +} + +void CommandAnalysis::handlePupAct(int64_t timestamp) +{ + // If command is power-up in the active mode - check the power-down + // exit-mode employed (fast or slow), update the number of power-down + // and power-up cycles and the latest and first act cycle. Also, reset + // all the individual bank states to the respective saved states + // before entering power-down. + const MemTimingSpec& t = memSpec.memTimingSpec; + + if (mem_state == CommandAnalysis::MS_PDN_F_ACT) { + f_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + pup_act_cycles += t.XP; + latest_act_cycle = timestamp; + } else if (mem_state == CommandAnalysis::MS_PDN_S_ACT) { + s_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + if (memSpec.memArchSpec.dll == false) { + pup_act_cycles += t.XP; + latest_act_cycle = timestamp; + } else { + pup_act_cycles += t.XPDLL - t.RCD; + latest_act_cycle = timestamp + zero_guard(t.XPDLL - (2 * t.RCD), "t.XPDLL - (2 * t.RCD) < 0"); + } + } else { + cerr << "Incorrect use of Active Power-Up!" << endl; + } + mem_state = MS_NOT_IN_PD; + bank_state = last_bank_state; + first_act_cycle = timestamp; + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); +} + +void CommandAnalysis::handlePupPre(int64_t timestamp) +{ + // If command is power-up in the precharged mode - check the power-down + // exit-mode employed (fast or slow), update the number of power-down + // and power-up cycles and the latest and last pre cycle. + const MemTimingSpec& t = memSpec.memTimingSpec; + if (mem_state == CommandAnalysis::MS_PDN_F_PRE) { + f_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + pup_pre_cycles += t.XP; + latest_pre_cycle = timestamp; + } else if (mem_state == CommandAnalysis::MS_PDN_S_PRE) { + s_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + if (memSpec.memArchSpec.dll == false) { + pup_pre_cycles += t.XP; + latest_pre_cycle = timestamp; + } else { + pup_pre_cycles += t.XPDLL - t.RCD; + latest_pre_cycle = timestamp + zero_guard(t.XPDLL - t.RCD - t.RP, "t.XPDLL - t.RCD - t.RP"); + } + } else { + cerr << "Incorrect use of Precharged Power-Up!" << endl; + } + mem_state = MS_NOT_IN_PD; + last_pre_cycle = timestamp; +} + +void CommandAnalysis::handleSREn(unsigned bank, int64_t timestamp) +{ + // If command is self-refresh - update number of self-refreshes, + // set memory state to SREF, update precharge and idle precharge + // cycles and set the self-refresh cycle. + printWarningIfActive("One or more banks are active! SREF requires all banks to be precharged.", MemCommand::SREN, timestamp, bank); + numberofsrefs++; + sref_cycle = timestamp; + sref_cycle_window = timestamp; + sref_ref_pre_cycles_window = 0; + sref_ref_act_cycles_window = 0; + precycles += zero_guard(timestamp - last_pre_cycle, "5 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + mem_state = CommandAnalysis::MS_SREF; +} + +void CommandAnalysis::handleSREx(unsigned bank, int64_t timestamp) +{ + // If command is self-refresh exit - update the number of self-refresh + // clock cycles, number of active and precharged auto-refresh clock + // cycles during self-refresh and self-refresh exit based on the number + // of cycles in the self-refresh mode and auto-refresh duration (RFC). + // Set the last and latest precharge cycle accordingly and set the + // memory state to 0. + const MemTimingSpec& t = memSpec.memTimingSpec; + if (mem_state != CommandAnalysis::MS_SREF) { + cerr << "Incorrect use of Self-Refresh Power-Up!" << endl; + } + // The total duration of self-refresh is given by the difference between + // the current clock cycle and the clock cycle of entering self-refresh. + int64_t sref_duration = timestamp - sref_cycle; + + // Negative or zero duration should never happen. + if (sref_duration <= 0) { + printWarning("Invalid Self-Refresh duration!", MemCommand::SREX, timestamp, bank); + sref_duration = 0; + } + + // The minimum time that the DRAM must remain in Self-Refresh is CKESR. + if (sref_duration < t.CKESR) { + printWarning("Self-Refresh duration < CKESR!", MemCommand::SREX, timestamp, bank); + } + + if (sref_duration >= t.RFC) { + /* + * Self-refresh Exit Context 1 (tSREF >= tRFC): + * The memory remained in self-refresh for a certain number of clock + * cycles greater than a refresh cycle time (RFC). Consequently, the + * initial auto-refresh accomplished. + * + * + * SREN # SREX + * | # ^ + * | # | + * |<------------------------- tSREF ----------...----->| + * | # | + * | Initial Auto-Refresh # | + * v # | + * ------------------------------------#-------...-----------------> t + * # + * <------------- tRFC --------------># + * <---- (tRFC - tRP) ----><-- tRP --># + * | | + * v v + * sref_ref_act_cycles sref_ref_pre_cycles + * + * + * Summary: + * sref_cycles += tSREF – tRFC + * sref_ref_act_cycles += tRFC - tRP + * sref_ref_pre_cycles += tRP + * spup_ref_act_cycles += 0 + * spup_ref_pre_cycles += 0 + * + */ + + // The initial auto-refresh consumes (IDD5 − IDD3N) over one refresh + // period (RFC) from the start of the self-refresh. + sref_ref_act_cycles += t.RFC - + t.RP - sref_ref_act_cycles_window; + sref_ref_pre_cycles += t.RP - sref_ref_pre_cycles_window; + last_pre_cycle = timestamp; + + // The IDD6 current is consumed for the time period spent in the + // self-refresh mode, which excludes the time spent in finishing the + // initial auto-refresh. + if (sref_cycle_window > sref_cycle + t.RFC) { + sref_cycles += zero_guard(timestamp - sref_cycle_window, "sref_cycle_window is in the future."); + } else { + sref_cycles += zero_guard(timestamp - sref_cycle - t.RFC, "sref_cycle - t.RFC < 0"); + } + + // IDD2N current is consumed when exiting the self-refresh state. + if (memSpec.memArchSpec.dll == false) { + spup_cycles += t.XS; + latest_pre_cycle = timestamp + zero_guard(t.XS - t.RP, "t.XS - t.RP < 0"); + } else { + spup_cycles += t.XSDLL - t.RCD; + latest_pre_cycle = timestamp + zero_guard(t.XSDLL - t.RCD - t.RP, "t.XSDLL - t.RCD - t.RP < 0"); + } + + } else { + // Self-refresh Exit Context 2 (tSREF < tRFC): + // Exit self-refresh before the completion of the initial + // auto-refresh. + + // Number of active cycles needed by an auto-refresh. + int64_t ref_act_cycles = t.RFC - t.RP; + + if (sref_duration >= ref_act_cycles) { + /* + * Self-refresh Exit Context 2A (tSREF < tRFC && tSREF >= tRFC - tRP): + * The duration of self-refresh is equal or greater than the number + * of active cycles needed by the initial auto-refresh. + * + * + * SREN SREX + * | ^ # + * | | # + * |<------------------ tSREF --------------------->| # + * | | # + * | Initial Auto-Refresh # + * v | # + * -----------------------------------------------------------#--> t + * # + * <------------------------ tRFC --------------------------># + * <------------- (tRFC - tRP)--------------><----- tRP ----># + * | <-----><-------> + * v | | + * sref_ref_act_cycles v v + * sref_ref_pre_cycles spup_ref_pre_cycles + * + * + * Summary: + * sref_cycles += 0 + * sref_ref_act_cycles += tRFC - tRP + * sref_ref_pre_cycles += tSREF – (tRFC – tRP) + * spup_ref_act_cycles += 0 + * spup_ref_pre_cycles += tRP – sref_ref_pre_cycles + * + */ + + // Number of precharged cycles (zero <= pre_cycles < RP) + int64_t pre_cycles = sref_duration - ref_act_cycles - sref_ref_pre_cycles_window; + + sref_ref_act_cycles += ref_act_cycles - sref_ref_act_cycles_window; + sref_ref_pre_cycles += pre_cycles; + + // Number of precharged cycles during the self-refresh power-up. It + // is at maximum tRP (if pre_cycles is zero). + int64_t spup_pre = t.RP - pre_cycles; + + spup_ref_pre_cycles += spup_pre; + + last_pre_cycle = timestamp + spup_pre; + + if (memSpec.memArchSpec.dll == false) { + spup_cycles += t.XS - spup_pre; + latest_pre_cycle = timestamp + zero_guard(t.XS - spup_pre - t.RP, "t.XS - spup_pre - t.RP < 0"); + } else { + spup_cycles += t.XSDLL - t.RCD - spup_pre; + latest_pre_cycle = timestamp + zero_guard(t.XSDLL - t.RCD - spup_pre - t.RP, "t.XSDLL - t.RCD - spup_pre - t.RP"); + } + } else { + /* + * Self-refresh Exit Context 2B (tSREF < tRFC - tRP): + * self-refresh duration is shorter than the number of active cycles + * needed by the initial auto-refresh. + * + * + * SREN SREX + * | ^ # + * | | # + * |<-------------- tSREF ----------->| # + * | | # + * | Initial Auto-Refresh # + * v | # + * ------------------------------------------------------------#--> t + * # + * <------------------------ tRFC ---------------------------># + * <-------------- (tRFC - tRP)-------------><------ tRP ----># + * <--------------------------------><------><---------------> + * | | | + * v v v + * sref_ref_act_cycles spup_ref_act_cycles spup_ref_pre_cycles + * + * + * Summary: + * sref_cycles += 0 + * sref_ref_act_cycles += tSREF + * sref_ref_pre_cycles += 0 + * spup_ref_act_cycles += (tRFC – tRP) - tSREF + * spup_ref_pre_cycles += tRP + * + */ + + sref_ref_act_cycles += sref_duration - sref_ref_act_cycles_window; + + int64_t spup_act = (t.RFC - t.RP) - sref_duration; + + spup_ref_act_cycles += spup_act; + spup_ref_pre_cycles += t.RP; + + last_pre_cycle = timestamp + spup_act + t.RP; + if (memSpec.memArchSpec.dll == false) { + spup_cycles += t.XS - spup_act - t.RP; + latest_pre_cycle = timestamp + zero_guard(t.XS - spup_act - (2 * t.RP), "t.XS - spup_act - (2 * t.RP) < 0"); + } else { + spup_cycles += t.XSDLL - t.RCD - spup_act - t.RP; + latest_pre_cycle = timestamp + zero_guard(t.XSDLL - t.RCD - spup_act - (2 * t.RP), "t.XSDLL - t.RCD - spup_act - (2 * t.RP) < 0"); + } + } + } + mem_state = MS_NOT_IN_PD; +} + + +void CommandAnalysis::handleNopEnd(int64_t timestamp) +{ + // May be optionally used at the end of memory trace for better accuracy + // Update all counters based on completion of operations. + const MemTimingSpec& t = memSpec.memTimingSpec; + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)"); + } + } + + if (nActiveBanks() > 0 && mem_state == MS_NOT_IN_PD) { + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future"); + idle_act_update(latest_read_cycle, latest_write_cycle, + latest_act_cycle, timestamp); + } else if (nActiveBanks() == 0 && mem_state == MS_NOT_IN_PD) { + precycles += zero_guard(timestamp - last_pre_cycle, "6 last_pre_cycle is in the future"); + idle_pre_update(timestamp, latest_pre_cycle); + } else if (mem_state == CommandAnalysis::MS_PDN_F_ACT) { + f_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_PDN_S_ACT) { + s_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_PDN_F_PRE) { + f_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_PDN_S_PRE) { + s_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_SREF) { + auto rfc_minus_rp = (t.RFC - t.RP); + + if (timestamp > sref_cycle + t.RFC) { + if (sref_cycle_window <= sref_cycle + rfc_minus_rp) { + sref_ref_act_cycles += rfc_minus_rp - sref_ref_act_cycles_window; + sref_ref_act_cycles_window = rfc_minus_rp; + sref_cycle_window = sref_cycle + rfc_minus_rp; + } + if (sref_cycle_window <= sref_cycle + t.RFC) { + sref_ref_pre_cycles += t.RP - sref_ref_pre_cycles_window; + sref_ref_pre_cycles_window = t.RP; + sref_cycle_window = sref_cycle + t.RFC; + } + sref_cycles += zero_guard(timestamp - sref_cycle_window, "sref_cycle_window is in the future"); + } else if (timestamp > sref_cycle + rfc_minus_rp) { + + if (sref_cycle_window <= sref_cycle + rfc_minus_rp) { + sref_ref_act_cycles += rfc_minus_rp - sref_ref_act_cycles_window; + sref_ref_act_cycles_window = rfc_minus_rp; + sref_cycle_window = sref_cycle + rfc_minus_rp; + } + sref_ref_pre_cycles_window += timestamp - sref_cycle_window; + sref_ref_pre_cycles += timestamp - sref_cycle_window; + } else { + sref_ref_act_cycles_window += timestamp - sref_cycle_window; + sref_ref_act_cycles += timestamp - sref_cycle_window; + } + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdScheduler.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdScheduler.cc new file mode 100644 index 0000000000..a4619b94ec --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdScheduler.cc @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, Yonghui Li, Sven Goossens + * + */ +#include "CmdScheduler.h" + +#include +#include // For log2 + +#include // For max + + +#define MILLION 1000000 + + +using namespace std; +using namespace Data; + +// Read the traces and get the transaction. Each transaction is executed by +// scheduling a number of commands to the memory. Hence, the transactions are +// translated into a sequence of commands which will be used for power analysis. +void cmdScheduler::transTranslation(const MemorySpecification& memSpec, + ifstream& trans_trace, int grouping, int interleaving, int burst, int powerdown) +{ + commands.open("commands.trace", ifstream::out); + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + nBanks = memArchSpec.nbrOfBanks; + nColumns = memArchSpec.nbrOfColumns; + burstLength = memArchSpec.burstLength; + nbrOfBankGroups = memArchSpec.nbrOfBankGroups; + + BGI = grouping; + BI = interleaving; + BC = burst; + power_down = powerdown; + + schedulingInitialization(memSpec); + getTrans(trans_trace, memSpec); + + trans_trace.close(); + commands.close(); + ACT.erase(ACT.begin(), ACT.end()); + PRE.erase(PRE.begin(), PRE.end()); + RDWR.erase(RDWR.begin(), RDWR.end()); + cmdScheduling.erase(cmdScheduling.begin(), cmdScheduling.end()); + cmdList.erase(cmdList.begin(), cmdList.end()); + transTrace.erase(transTrace.begin(), transTrace.end()); +} // cmdScheduler::transTranslation + +// initialize the variables and vectors for starting command scheduling. +void cmdScheduler::schedulingInitialization(const MemorySpecification& memSpec) +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + + const size_t numBanks = static_cast(memSpec.memArchSpec.nbrOfBanks); + ACT.resize(2 * numBanks); + RDWR.resize(2 * numBanks); + PRE.resize(numBanks); + bankaccess = memSpec.memArchSpec.nbrOfBanks; + if (!ACT.empty()) { + ACT.erase(ACT.begin(), ACT.end()); + } + if (!PRE.empty()) { + PRE.erase(PRE.begin(), PRE.end()); + } + if (!RDWR.empty()) { + RDWR.erase(RDWR.begin(), RDWR.end()); + } + + ///////////////initialization////////////// + for (int64_t i = 0; i < memSpec.memArchSpec.nbrOfBanks; i++) { + cmd.Type = PRECHARGE; + cmd.bank = static_cast(i); + cmd.name = "PRE"; + if (memSpec.id == "WIDEIO_SDR") { + cmd.time = 1 - memSpec.memTimingSpec.TAW; + } else { + cmd.time = 1 - memSpec.memTimingSpec.FAW; + } + + PRE.push_back(cmd); + + cmd.Type = ACTIVATE; + cmd.name = "ACT"; + ACT.push_back(cmd); + + cmd.Type = WRITE; + cmd.name = "WRITE"; + cmd.time = -1; + RDWR[static_cast(i)].push_back(cmd); + } + tREF = memTimingSpec.REFI; + transFinish.time = 0; + transFinish.bank = 0; + + PreRDWR.bank = -1; + PreRDWR.Type = READ; + PreRDWR.name = "RD"; + PreRDWR.time = -1; + startTime = 0; +} // cmdScheduler::schedulingInitialization + +// transactions are generated according to the information read from the traces. +// Then the command scheduling function is triggered to generate commands and +// schedule them to the memory according to the timing constraints. +void cmdScheduler::getTrans(std::ifstream& trans_trace, const MemorySpecification& memSpec) +{ + std::string line; + + transTime = 0; + uint64_t newtranstime; + uint64_t transAddr; + int64_t transType = 1; + trans TransItem; + + if (!transTrace.empty()) { + transTrace.erase(transTrace.begin(), transTrace.end()); + } + + while (getline(trans_trace, line)) { + istringstream linestream(line); + string item; + uint64_t itemnum = 0; + while (getline(linestream, item, ',')) { + if (itemnum == 0) { + stringstream timestamp(item); + timestamp >> newtranstime; + transTime = transTime + static_cast(newtranstime); + } else if (itemnum == 1) { + if (item == "write" || item == "WRITE") { + transType = WRITE; + } else { + transType = READ; + } + } else if (itemnum == 2) { + stringstream timestamp(item); + timestamp >> std::hex >> transAddr; + } + itemnum++; + } + // generate a transaction + TransItem.timeStamp = transTime; + TransItem.logicalAddress = transAddr; + TransItem.type = transType; + + transTrace.push_back(TransItem); + + if (transTrace.size() == MILLION) { + // The scheduling is implemented for every MILLION transactions. + // It is used to reduce the used memory during the running of this tool. + analyticalScheduling(memSpec); + transTrace.erase(transTrace.begin(), transTrace.end()); + } + } + + if ((transTrace.size() < MILLION) && (!transTrace.empty())) { + analyticalScheduling(memSpec); + transTrace.erase(transTrace.begin(), transTrace.end()); + } +} // cmdScheduler::getTrans + +// Transactions are executed individually and the command scheduling is +// independent between transactions. The commands for a new transaction cannot +// be scheduled until all the commands for the current one are scheduled. +// After the scheduling, a sequence of commands are obtained and they are written +// into commands.txt which will be used for power analysis. +void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec) +{ + int64_t transType = -1; + int64_t timer = 0; + uint64_t bankGroupPointer = 0; + uint64_t bankGroupAddr = 0; + bool collisionFound; + physicalAddr PhysicalAddress; + bool bankGroupSwitch = false; + std::vector bankPointer(static_cast(nbrOfBankGroups), 0); + std::vector bankAccessNum(static_cast(nBanks), -1); + std::vector ACTSchedule(static_cast(nBanks), false); + uint64_t bankAddr = 0; + int64_t endTime = 0; + int64_t tComing_REF = 0; + + Inselfrefresh = 0; + + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + + for (uint64_t t = 0; t < transTrace.size(); t++) { + cmdScheduling.erase(cmdScheduling.begin(), cmdScheduling.end()); + + for (auto a : ACTSchedule) { + a = false; + } + + for (auto& b : bankAccessNum) { + b = -1; + } + + timingsGet = false; + timer = transTrace[t].timeStamp; + + PhysicalAddress = memoryMap(transTrace[t], memSpec); + + for (auto& b : bankPointer) { + b = PhysicalAddress.bankAddr; // the bank pointer per group. + } + bankGroupPointer = PhysicalAddress.bankGroupAddr; + + endTime = max(transFinish.time, PRE[static_cast(transFinish.bank)].time + + static_cast(memTimingSpec.RP)); + + // Before starting the scheduling for the next transaction, it has to + // check whether it is necessary for implementing power down. + if (power_down == SELF_REFRESH) + pdScheduling(endTime, timer, memSpec); + else if (power_down == POWER_DOWN) + pdScheduling(endTime, min(timer, tREF), memSpec); + + tComing_REF = tREF; + + ///////////////Scheduling Refresh//////////////////////// + if (((transFinish.time >= tREF) || (timer >= tREF))) { + for (int64_t i = 0; i <= ((timer - tComing_REF) > 0 ? (timer - tComing_REF) / + memTimingSpec.REFI : 0); i++) { + cmd.bank = 0; + cmd.name = "REF"; + cmd.time = max(max(max(transFinish.time, PRE[static_cast(transFinish.bank)].time + memTimingSpec.RP), tREF), startTime); + if ((power_down == SELF_REFRESH && !Inselfrefresh) || power_down != SELF_REFRESH) { + cmdScheduling.push_back(cmd); + startTime = cmd.time + memTimingSpec.RFC; + } + tREF = tREF + memTimingSpec.REFI; + // during the refreshing, power down should be taken into account. + if (!Inselfrefresh) + pdScheduling(endTime, min(timer, tREF), memSpec); + } + } + ///////////////Execution Transactions/////////////////// + uint64_t Bs = PhysicalAddress.bankAddr; + transType = transTrace[t].type; + + tRWTP = getRWTP(transType, memSpec); + + for (int i = 0; i < BI; i++) { + for (int k = 0; k < BC; k++) { + if (memSpec.memoryType == MemoryType::DDR4) { + bankGroupPointer = PhysicalAddress.bankGroupAddr; + } + + for (int j = 0; j < BGI; j++) { + bankGroupSwitch = false; + if (memSpec.memoryType == MemoryType::DDR4) { + if (bankGroupPointer != bankGroupAddr) { + bankGroupSwitch = true; + } + // update to the current bank group address. + bankGroupAddr = PhysicalAddress.bankGroupAddr + static_cast(j); + bankAddr = bankGroupAddr * static_cast(nBanks) / nbrOfBankGroups + bankPointer[bankGroupAddr]; + } else { + bankAddr = Bs + i; + } + + if (!timingsGet) { + getTimingConstraints(bankGroupSwitch, memSpec, + PreRDWR.Type, transType); + } + + ////////////////ACT Scheduling/////////////////// + if (!ACTSchedule[bankAddr]) { + cmd.bank = bankAddr; + cmd.PhysicalAddr.bankAddr = cmd.bank; + cmd.PhysicalAddr.rowAddr = PhysicalAddress.rowAddr; + cmd.Type = ACTIVATE; + cmd.name = "ACT"; + Inselfrefresh = 0; + cmd.time = max(max(ACT[bankaccess - 1].time + tRRD_init, + PRE[cmd.bank].time + static_cast(memTimingSpec.RP)), + ACT[bankaccess - 4].time + + static_cast(memTimingSpec.FAW)); + + if (memSpec.memoryType == MemoryType::WIDEIO_SDR) { + cmd.time = max(max(ACT[bankaccess - 1].time + tRRD_init, + PRE[cmd.bank].time + static_cast(memTimingSpec.RP)), + ACT[bankaccess - 2].time + + static_cast(memTimingSpec.TAW)); + } + + if (i == 0 && j == 0) { + cmd.time = max(cmd.time, PreRDWR.time + 1); + cmd.time = max(cmd.time, timer); + cmd.time = max(startTime, cmd.time); + } + + //////////collision detection//////////////////// + for (int n = 1; n <= i * BGI + j; n++) { + collisionFound = false; + for (unsigned m = 0; m < RDWR[bankaccess - n].size(); m++) { + if (RDWR[bankaccess - n][m].time == cmd.time) { + cmd.time += 1; // ACT is shifted + collisionFound = true; + break; + } + } + if (collisionFound) { + break; + } + } + + ACT.push_back(cmd); + cmdScheduling.push_back(cmd); + + ACTSchedule[bankAddr] = true; + bankAccessNum[bankAddr] = bankaccess; + bankaccess++; + } + + /////RDWR Scheduling////// + cmd.bank = bankAddr; + cmd.PhysicalAddr.bankAddr = cmd.bank; + cmd.PhysicalAddr.rowAddr = PhysicalAddress.rowAddr; + cmd.PhysicalAddr.colAddr = PhysicalAddress.colAddr + k * burstLength; + cmd.Type = transType; + switch (transType) { + case READ: + cmd.name = "RD"; + break; + + case WRITE: + cmd.name = "WR"; + break; + } + for (int ACTBank = static_cast(ACT.size() - 1); + ACTBank >= 0; ACTBank--) { + if (ACT[ACTBank].bank == static_cast(bankAddr)) { + cmd.time = max(PreRDWR.time + tSwitch_init, ACT.back().time + + static_cast(memTimingSpec.RCD)); + break; + } + } + + if ((i == BI - 1) && (k == BC - 1) && (j == BGI - 1)) { + transFinish.time = cmd.time + 1; + transFinish.bank = bankAddr; + } + if (k == BC - 1) { + switch (transType) { + case READ: + cmd.name = "RDA"; + break; + + case WRITE: + cmd.name = "WRA"; + break; + } + } + PreRDWR = cmd; + + RDWR[bankAccessNum[bankAddr]].push_back(cmd); + cmdScheduling.push_back(cmd); + + ////////////////PRE Scheduling//////////////////// + if (k == BC - 1) { + PRE[bankAddr].bank = bankAddr; + PRE[bankAddr].Type = PRECHARGE; + PRE[bankAddr].name = "PRE"; + for (int ACTBank = static_cast(ACT.size() - 1); + ACTBank >= 0; ACTBank--) { + if (ACT[ACTBank].bank == static_cast(bankAddr)) { + PRE[bankAddr].time = max(ACT.back().time + + static_cast(memTimingSpec.RAS), + PreRDWR.time + tRWTP); + break; + } + } + bankPointer[bankGroupAddr] = bankPointer[bankGroupAddr] + 1; + } + + bankGroupPointer++; + } + } + } + + // make sure the scheduled commands are stored with an ascending scheduling time + sort(cmdScheduling.begin(), cmdScheduling.end(), + commandItem::commandItemSorter()); + + // write the scheduled commands into commands.txt. + for (unsigned i = 0; i < cmdScheduling.size(); i++) { + cmdList.push_back(cmdScheduling[i]); + } + + /////////////Update Vector Length///////////////// + // the vector length is reduced so that less memory is used for running + // this tool. + if (ACT.size() >= static_cast(memSpec.memArchSpec.nbrOfBanks)) { + for (int m = 0; m < BI * BGI; m++) { + ACT.erase(ACT.begin()); + RDWR[0].erase(RDWR[0].begin(), RDWR[0].end()); + for (int h = 0; h < bankaccess - 1 - m; h++) { + RDWR[h].insert(RDWR[h].begin(), RDWR[h + 1].begin(), RDWR[h + 1].end()); + RDWR[h + 1].resize(0); + } + } + bankaccess = bankaccess - (BI * BGI); + } + } + + for (unsigned j = 0; j < cmdList.size(); j++) { + commands.precision(0); + commands << fixed << cmdList[j].time << "," << cmdList[j].name << "," << + cmdList[j].bank << endl; + } + cmdList.erase(cmdList.begin(), cmdList.end()); +} // cmdScheduler::analyticalScheduling + +// to add the power down/up during the command scheduling for transactions. +// It is called when the command scheduling for a transaction is finished, and it +// is also called if there is a refresh. +void cmdScheduler::pdScheduling(int64_t endTime, int64_t timer, + const MemorySpecification& memSpec) +{ + int64_t ZERO = 0; + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + + endTime = max(endTime, startTime); + int64_t pdTime = max(ZERO, timer - endTime); + + if ((timer > (endTime + memTimingSpec.CKE)) && (power_down == POWER_DOWN)) { + cmd.bank = 0; + cmd.name = "PDN_S_PRE"; + cmd.time = endTime; + cmdScheduling.push_back(cmd); + cmd.name = "PUP_PRE"; + + if (pdTime > memTimingSpec.REFI) + cmd.time = cmd.time + memTimingSpec.REFI; + else + cmd.time = cmd.time + pdTime; + + if (memSpec.memoryType.isLPDDRFamily()) + startTime = cmd.time + memTimingSpec.XP; + else + startTime = cmd.time + memTimingSpec.XPDLL - memTimingSpec.RCD; + + cmdScheduling.push_back(cmd); + } else if ((timer > (endTime + memTimingSpec.CKESR)) && (power_down == SELF_REFRESH)) { + cmd.bank = 0; + cmd.name = "SREN"; + cmd.time = endTime; + cmdScheduling.push_back(cmd); + Inselfrefresh = 1; + cmd.name = "SREX"; + cmd.time = cmd.time + pdTime; + + if (memSpec.memoryType.isLPDDRFamily()) + startTime = cmd.time + memTimingSpec.XS; + else + startTime = cmd.time + memTimingSpec.XSDLL - memTimingSpec.RCD; + + cmdScheduling.push_back(cmd); + } +} // cmdScheduler::pdScheduling + +// get the time when a precharge occurs after a read/write command is scheduled. +// In addition, it copes with different kind of memories. +int64_t cmdScheduler::getRWTP(int64_t transType, const MemorySpecification& memSpec) +{ + int64_t tRWTP_init = 0; + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + + if (transType == READ) { + switch (memSpec.memoryType) { + case MemoryType::LPDDR: + case MemoryType::WIDEIO_SDR: + tRWTP_init = memArchSpec.burstLength / memArchSpec.dataRate; + break; + + case MemoryType::LPDDR2: + case MemoryType::LPDDR3: + tRWTP_init = memArchSpec.burstLength / memArchSpec.dataRate + + max(int64_t(0), memTimingSpec.RTP - 2); + break; + + case MemoryType::DDR2: + tRWTP_init = memTimingSpec.AL + memArchSpec.burstLength / + memArchSpec.dataRate + + max(memTimingSpec.RTP, int64_t(2)) - 2; + break; + + case MemoryType::DDR3: + case MemoryType::DDR4: + tRWTP_init = memTimingSpec.RTP; + break; + default: + assert("Unknown memory type" && false); + } // switch + } else if (transType == WRITE) { + if (memSpec.memoryType == MemoryType::WIDEIO_SDR) { + tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate - 1 + memTimingSpec.WR; + } else { + tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate + memTimingSpec.WR; + } + if ((memSpec.memoryType == MemoryType::LPDDR2) || + (memSpec.memoryType == MemoryType::LPDDR3)) { + tRWTP_init = tRWTP_init + 1; + } + } + + return tRWTP_init; +} // cmdScheduler::getRWTP + +// get the timings for command scheduling according to different memories. +// In particular, tSwitch_init is generally used to provide the timings for +// scheduling a read/write command after a read/write command which have been +// scheduled to any possible banks within any possible bank groups (DDR4). +void cmdScheduler::getTimingConstraints(bool BGSwitch, const MemorySpecification& memSpec, + int64_t PreType, int64_t CurrentType) +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + + if (memSpec.memoryType != MemoryType::DDR4) { + tRRD_init = memTimingSpec.RRD; + if (PreType == CurrentType) { + tSwitch_init = memTimingSpec.CCD; + timingsGet = true; + } + + if ((PreType == WRITE) && (CurrentType == READ)) { + if (memSpec.memoryType == MemoryType::WIDEIO_SDR) { + tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate - 1 + memTimingSpec.WTR; + } else { + tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate + memTimingSpec.WTR; + } + + if ((memSpec.memoryType == MemoryType::LPDDR2) || + (memSpec.memoryType == MemoryType::LPDDR3)) { + tSwitch_init = tSwitch_init + 1; + } + } + } + + if (memSpec.memoryType == MemoryType::DDR4) { + if (BGSwitch) { + tCCD_init = memTimingSpec.CCD_S; + tRRD_init = memTimingSpec.RRD_S; + tWTR_init = memTimingSpec.WTR_S; + } else { + tCCD_init = memTimingSpec.CCD_L; + tRRD_init = memTimingSpec.RRD_L; + tWTR_init = memTimingSpec.WTR_L; + } + + if (PreType == CurrentType) { + tSwitch_init = tCCD_init; + timingsGet = true; + } else if (PreType == WRITE && CurrentType == READ) { + tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate + tWTR_init; + } + } + + if ((PreType == READ) && (CurrentType == WRITE)) { + tSwitch_init = memTimingSpec.RL + memArchSpec.burstLength / + memArchSpec.dataRate + 2 - memTimingSpec.WL; + } +} // cmdScheduler::getTimingConstraints + +// The logical address of each transaction is translated into a physical address +// which consists of bank group (for DDR4), bank, row and column addresses. +cmdScheduler::physicalAddr cmdScheduler::memoryMap(trans Trans, + const MemorySpecification& memSpec) +{ + int64_t DecLogic; + physicalAddr PhysicalAddr; + + DecLogic = Trans.logicalAddress; + + // row-bank-column-BI-BC-BGI-BL + if (BGI > 1 && memSpec.memoryType == MemoryType::DDR4) { + uint64_t colBits = uintLog2(nColumns); + uint64_t bankShift = colBits + ((BI > 1) ? uintLog2(BI) : 0) + ((BGI > 1) ? uintLog2(BGI) : 0); + uint64_t bankMask = (nBanks / (BI * nbrOfBankGroups) - 1) << bankShift; + uint64_t bankAddr = (DecLogic & bankMask) >> (colBits + ((BGI > 1) ? uintLog2(BGI) : 0)); + PhysicalAddr.bankAddr = bankAddr; + + uint64_t bankGroupShift = uintLog2(burstLength); + uint64_t bankGroupMask = (nbrOfBankGroups / BGI - 1) << bankGroupShift; + uint64_t bankGroupAddr = (DecLogic & bankGroupMask) >> bankGroupShift; + PhysicalAddr.bankGroupAddr = bankGroupAddr; + + uint64_t colShift = uintLog2(BC * burstLength) + + ((BI > 1) ? uintLog2(BI) : 0) + ((BGI > 1) ? uintLog2(BGI) : 0); + uint64_t colMask = (nColumns / (BC * burstLength) - 1) << colShift; + uint64_t colAddr = (DecLogic & colMask) >> (colShift - uintLog2(static_cast(BC) * burstLength)); + PhysicalAddr.colAddr = colAddr; + } else { + uint64_t colBits = uintLog2(nColumns); + uint64_t bankShift = colBits + ((BI > 1) ? uintLog2(BI) : 0); + uint64_t bankMask = (nBanks / BI - 1) << bankShift; + uint64_t bankAddr = (DecLogic & bankMask) >> colBits; + PhysicalAddr.bankAddr = bankAddr; + + uint64_t colShift = (uintLog2(BC * burstLength) + ((BI > 1) ? uintLog2(BI) : 0)); + uint64_t colMask = (nColumns / (BC * burstLength) - 1) << colShift; + uint64_t colAddr = (DecLogic & colMask) >> (colShift - uintLog2(BC * burstLength)); + PhysicalAddr.colAddr = colAddr; + + PhysicalAddr.bankGroupAddr = 0; + } + + uint64_t rowShift = uintLog2(nColumns * nBanks); + uint64_t rowMask = (memSpec.memArchSpec.nbrOfRows - 1) << rowShift; + uint64_t rowAddr = (DecLogic & rowMask) >> rowShift; + PhysicalAddr.rowAddr = rowAddr; + + return PhysicalAddr; +} // cmdScheduler::memoryMap + +uint64_t cmdScheduler::uintLog2(uint64_t in) +{ + return static_cast(log2(in)); +} \ No newline at end of file diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdScheduler.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdScheduler.h new file mode 100644 index 0000000000..58efd279b1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CmdScheduler.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#ifndef CMDSCHEDULER_H +#define CMDSCHEDULER_H + +#include +#include +#include // for binary_function<> +#include + +#include "MemorySpecification.h" +#include "Utils.h" + +namespace Data { +class cmdScheduler { + public: + #define READ 0 + #define WRITE 1 + #define ACTIVATE 2 + #define PRECHARGE 3 + #define POWER_DOWN 1 + #define SELF_REFRESH 2 + + // the format of a transaction. + class trans { + public: + int64_t type; + int64_t timeStamp; + uint64_t logicalAddress; + }; + + std::vector transTrace; // to store the transactions. + + // the format of physical address. + class physicalAddr { + public: + uint64_t rowAddr; + uint64_t bankAddr; + uint64_t bankGroupAddr; + uint64_t colAddr; + }; + + // the format of a command. + class commandItem { + public: + int64_t Type; + int64_t bank; + int64_t time; + std::string name; + physicalAddr PhysicalAddr; + // sorting the commands according to their scheduling time. + struct commandItemSorter : public std::binary_function{ + bool operator()(const commandItem& lhs, + const commandItem& rhs) const + { + return lhs.time < rhs.time; + } + }; + }; + + commandItem cmd; + commandItem transFinish; // the last scheduled command for a transaction. + commandItem PreRDWR; // the latest scheduled READ or WRITE command. + // the scheduled ACTIVATE commands are stored in ACT. + std::vector ACT; + // PRE is sued to keep recording the time when a precharge occurs. + std::vector PRE; + // the scheduled READ or WRITE commands are stored in RDWR. + std::vector > RDWR; + // all the scheduled commands for a transaction is stored by cmdScheduling. + std::vector cmdScheduling; + std::vector cmdList; + unsigned elements; + int64_t BI, BC, BGI; + + // the function used to translate a transaction into a sequence of + // commands which are scheduled to the memory. + void transTranslation(const MemorySpecification& memSpec, + std::ifstream& trans_trace, + int grouping, + int interleaving, + int burst, + int powerdown); + // get the transactions by reading the traces. + void getTrans(std::ifstream& pwr_trace, + const MemorySpecification& memSpec); + // the initialization function for scheduling. + void schedulingInitialization(const MemorySpecification& memSpec); + // the function used to schedule commands according to the timing constraints. + void analyticalScheduling(const MemorySpecification& memSpec); + // translate the logical address into physical address. + physicalAddr memoryMap(trans Trans, + const MemorySpecification& memSpec); + // the power down and power up are scheduled by pdScheduling + void pdScheduling(int64_t endTime, + int64_t timer, + const MemorySpecification& memSpec); + // get the timings for scheduling a precharge since a read or write command + // is scheduled. + int64_t getRWTP(int64_t transType, + const MemorySpecification& memSpec); + // get different kind of timing constraints according to the used memory. + void getTimingConstraints(bool BGSwitch, + const MemorySpecification& memSpec, + int64_t PreType, + int64_t CurrentType); + + uint64_t uintLog2(uint64_t in); + + int64_t transTime; + // the flag for power down. + int64_t power_down; + int64_t Inselfrefresh; + int64_t tRRD_init; + int64_t tCCD_init; + int64_t tWTR_init; + int64_t tREF; + int64_t tSwitch_init; + int64_t tRWTP; + int64_t bankaccess; + int64_t nBanks; + int64_t nColumns; + int64_t burstLength; + int64_t nbrOfBankGroups; + bool timingsGet; + int64_t startTime; + + // the scheduling results for all the transactions are written into + // commands which will be used by the power analysis part. + std::ofstream commands; +}; +} + +#endif // ifndef CMDSCHEDULER_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CommandAnalysis.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CommandAnalysis.cc new file mode 100644 index 0000000000..b840ab53c3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CommandAnalysis.cc @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, + * Matthias Jung, + * Omar Naji, + * Sven Goossens, + * Éder F. Zulian + * Subash Kannoth + * Felipe S. Prado + * + */ + +#include +#include +#include + +#include "CommandAnalysis.h" +#include "CmdScheduler.h" + +using namespace Data; +using namespace std; + +bool commandSorter(const MemCommand& i, const MemCommand& j) +{ + if (i.getTimeInt64() == j.getTimeInt64()) { + return i.getType() == MemCommand::PRE && j.getType() != MemCommand::PRE; + } else { + return i.getTimeInt64() < j.getTimeInt64(); + } +} + +CommandAnalysis::CommandAnalysis(const Data::MemorySpecification& memSpec) : + memSpec(memSpec) + +{ + auto &nBanks = memSpec.memArchSpec.nbrOfBanks; + // Initializing all counters and variables + numberofactsBanks.assign(static_cast(nBanks), 0); + numberofpresBanks.assign(static_cast(nBanks), 0); + numberofreadsBanks.assign(static_cast(nBanks), 0); + numberofwritesBanks.assign(static_cast(nBanks), 0); + actcyclesBanks.assign(static_cast(nBanks), 0); + numberofrefbBanks.assign(static_cast(nBanks), 0); + + first_act_cycle_banks.resize(static_cast(nBanks), 0); + + clearStats(0); + zero = 0; + + bank_state.resize(static_cast(nBanks), BANK_PRECHARGED); + last_bank_state.resize(static_cast(nBanks), BANK_PRECHARGED); + mem_state = MS_NOT_IN_PD; + + cmd_list.clear(); + cached_cmd.clear(); + activation_cycle.resize(static_cast(nBanks), 0); + num_banks = nBanks; +} + +// function to clear counters +void CommandAnalysis::clearStats(const int64_t timestamp) +{ + std::fill(numberofactsBanks.begin(), numberofactsBanks.end(), 0); + std::fill(numberofpresBanks.begin(), numberofpresBanks.end(), 0); + std::fill(numberofreadsBanks.begin(), numberofreadsBanks.end(), 0); + std::fill(numberofwritesBanks.begin(), numberofwritesBanks.end(), 0); + std::fill(actcyclesBanks.begin(), actcyclesBanks.end(), 0); + + numberofrefs = 0; + f_act_pdns = 0; + s_act_pdns = 0; + f_pre_pdns = 0; + s_pre_pdns = 0; + numberofsrefs = 0; + + actcycles = 0; + precycles = 0; + f_act_pdcycles = 0; + s_act_pdcycles = 0; + f_pre_pdcycles = 0; + s_pre_pdcycles = 0; + pup_act_cycles = 0; + pup_pre_cycles = 0; + sref_cycles = 0; + spup_cycles = 0; + sref_ref_act_cycles = 0; + sref_ref_pre_cycles = 0; + spup_ref_act_cycles = 0; + spup_ref_pre_cycles = 0; + idlecycles_act = 0; + idlecycles_pre = 0; + + // reset count references to timestamp so that they are moved + // to start of next stats generation + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); + first_act_cycle = timestamp; + + pdn_cycle = timestamp; + sref_cycle_window = timestamp; + + end_act_op = timestamp; + end_read_op = timestamp; + end_write_op = timestamp; + + latest_read_cycle = -1; + latest_write_cycle = -1; + + if (timestamp == 0) { + latest_pre_cycle = -1; + latest_act_cycle = -1; + sref_cycle = 0; + last_pre_cycle = 0; + sref_ref_act_cycles_window = 0; + sref_ref_pre_cycles_window = 0; + } else { + last_pre_cycle = max(timestamp,last_pre_cycle); + + latest_pre_cycle = max(timestamp, latest_pre_cycle); + + if (latest_act_cycle < timestamp) + latest_act_cycle = -1; + } +} + +// function to clear all arrays +void CommandAnalysis::clear() +{ + cached_cmd.clear(); + cmd_list.clear(); + last_bank_state.clear(); + bank_state.clear(); +} + +// Reads through the trace file, identifies the timestamp, command and bank +// If the issued command includes an auto-precharge, adds an explicit +// precharge to a cached command list and computes the precharge offset from the +// issued command timestamp, when the auto-precharge would kick in + +void CommandAnalysis::getCommands(std::vector& list, bool lastupdate, int64_t timestamp) +{ + if (!next_window_cmd_list.empty()) { + list.insert(list.begin(), next_window_cmd_list.begin(), next_window_cmd_list.end()); + next_window_cmd_list.clear(); + } + for (size_t i = 0; i < list.size(); ++i) { + MemCommand& cmd = list[i]; + MemCommand::cmds cmdType = cmd.getType(); + if (cmdType == MemCommand::ACT) { + activation_cycle[cmd.getBank()] = cmd.getTimeInt64(); + } else if (cmdType == MemCommand::RDA || cmdType == MemCommand::WRA) { + // Remove auto-precharge flag from command + cmd.setType(cmd.typeWithoutAutoPrechargeFlag()); + + // Add the auto precharge to the list of cached_cmds + int64_t preTime = max(cmd.getTimeInt64() + cmd.getPrechargeOffset(memSpec, cmdType), + activation_cycle[cmd.getBank()] + memSpec.memTimingSpec.RAS); + list.push_back(MemCommand(MemCommand::PRE, cmd.getBank(), preTime)); + } + + if (!lastupdate && timestamp > 0) { + if(cmd.getTimeInt64() > timestamp) + { + MemCommand nextWindowCmd = list[i]; + next_window_cmd_list.push_back(nextWindowCmd); + list.erase(find(list.begin(), list.end(), cmd)); + } + } + } + sort(list.begin(), list.end(), commandSorter); + + if (lastupdate && list.empty() == false) { + // Add cycles at the end of the list + int64_t t = timeToCompletion(list.back().getType()) + list.back().getTimeInt64() - 1; + list.push_back(MemCommand(MemCommand::NOP, 0, t)); + } + + evaluateCommands(list); +} // CommandAnalysis::getCommands + + +// Used to analyse a given list of commands and identify command timings +// and memory state transitions +void CommandAnalysis::evaluateCommands(vector& cmd_list) +{ + // for each command identify timestamp, type and bank + for (auto cmd : cmd_list) { + // For command type + int type = cmd.getType(); + // For command bank + unsigned bank = cmd.getBank(); + // Command Issue timestamp in clock cycles (cc) + int64_t timestamp = cmd.getTimeInt64(); + + if (type == MemCommand::ACT) { + handleAct(bank, timestamp); + } else if (type == MemCommand::RD) { + handleRd(bank, timestamp); + } else if (type == MemCommand::WR) { + handleWr(bank, timestamp); + } else if (type == MemCommand::REF) { + handleRef(bank, timestamp); + } else if (type == MemCommand::REFB) { + handleRefB(bank, timestamp); + } else if (type == MemCommand::PRE) { + handlePre(bank, timestamp); + } else if (type == MemCommand::PREA) { + handlePreA(bank, timestamp); + } else if (type == MemCommand::PDN_F_ACT) { + handlePdnFAct(bank, timestamp); + } else if (type == MemCommand::PDN_S_ACT) { + handlePdnSAct(bank, timestamp); + } else if (type == MemCommand::PDN_F_PRE) { + handlePdnFPre(bank, timestamp); + } else if (type == MemCommand::PDN_S_PRE) { + handlePdnSPre(bank, timestamp); + } else if (type == MemCommand::PUP_ACT) { + handlePupAct(timestamp); + } else if (type == MemCommand::PUP_PRE) { + handlePupPre(timestamp); + } else if (type == MemCommand::SREN) { + handleSREn(bank, timestamp); + } else if (type == MemCommand::SREX) { + handleSREx(bank, timestamp); + } else if (type == MemCommand::END || type == MemCommand::NOP) { + handleNopEnd(timestamp); + } else { + printWarning("Unknown command given, exiting.", type, timestamp, bank); + exit(-1); + } + } +} // CommandAnalysis::evaluateCommands + +// To update idle period information whenever active cycles may be idle +void CommandAnalysis::idle_act_update(int64_t latest_read_cycle, int64_t latest_write_cycle, + int64_t latest_act_cycle, int64_t timestamp) +{ + if (latest_read_cycle >= 0) { + end_read_op = latest_read_cycle + timeToCompletion(MemCommand::RD) - 1; + } + + if (latest_write_cycle >= 0) { + end_write_op = latest_write_cycle + timeToCompletion(MemCommand::WR) - 1; + } + + if (latest_act_cycle >= 0) { + end_act_op = latest_act_cycle + timeToCompletion(MemCommand::ACT) - 1; + } + + idlecycles_act += max(zero, timestamp - max(max(end_read_op, end_write_op), + end_act_op)); +} // CommandAnalysis::idle_act_update + +// To update idle period information whenever precharged cycles may be idle +void CommandAnalysis::idle_pre_update(int64_t timestamp, int64_t latest_pre_cycle) +{ + if (latest_pre_cycle > 0) { + idlecycles_pre += max(zero, timestamp - latest_pre_cycle - + memSpec.memTimingSpec.RP); + } else if (latest_pre_cycle == 0) { + idlecycles_pre += max(zero, timestamp - latest_pre_cycle); + } +} + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CommandAnalysis.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CommandAnalysis.h new file mode 100644 index 0000000000..6161e687b1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/CommandAnalysis.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#ifndef COMMAND_TIMINGS_H +#define COMMAND_TIMINGS_H + +#include + +#include +#include +#include +#include + +#include "MemCommand.h" +#include "MemorySpecification.h" +#include "Utils.h" + +namespace Data { +class CommandAnalysis { + public: + // Power-Down and Self-refresh related memory states + enum memstate { + MS_NOT_IN_PD = 0, MS_PDN_F_ACT = 10, MS_PDN_S_ACT = 11, MS_PDN_F_PRE = 12, + MS_PDN_S_PRE = 13, MS_SREF = 14 + }; + + // Returns number of reads, writes, acts, pres and refs in the trace + CommandAnalysis(const MemorySpecification& memSpec); + + // Number of activate commands per bank + std::vector numberofactsBanks; + // Number of precharge commands per bank + std::vector numberofpresBanks; + // Number of reads commands per bank + std::vector numberofreadsBanks; + // Number of writes commands per bank + std::vector numberofwritesBanks; + // Number of refresh commands + int64_t numberofrefs; + // Number of bankwise refresh commands + std::vector numberofrefbBanks; + // Number of precharge cycles + int64_t precycles; + // Number of active cycles + int64_t actcycles; + std::vector actcyclesBanks; + // Number of Idle cycles in the active state + int64_t idlecycles_act; + // Number of Idle cycles in the precharge state + int64_t idlecycles_pre; + // Number of fast-exit activate power-downs + int64_t f_act_pdns; + // Number of slow-exit activate power-downs + int64_t s_act_pdns; + // Number of fast-exit precharged power-downs + int64_t f_pre_pdns; + // Number of slow-exit activate power-downs + int64_t s_pre_pdns; + // Number of self-refresh commands + int64_t numberofsrefs; + // Number of clock cycles in fast-exit activate power-down mode + int64_t f_act_pdcycles; + // Number of clock cycles in slow-exit activate power-down mode + int64_t s_act_pdcycles; + // Number of clock cycles in fast-exit precharged power-down mode + int64_t f_pre_pdcycles; + // Number of clock cycles in slow-exit precharged power-down mode + int64_t s_pre_pdcycles; + // Number of clock cycles in self-refresh mode (excludes the initial + // auto-refresh). During this time the current drawn is IDD6. + int64_t sref_cycles; + // Number of clock cycles in activate power-up mode + int64_t pup_act_cycles; + // Number of clock cycles in precharged power-up mode + int64_t pup_pre_cycles; + // Number of clock cycles in self-refresh power-up mode + int64_t spup_cycles; + + // Number of active cycles for the initial auto-refresh when entering + // self-refresh mode. + int64_t sref_ref_act_cycles; + // Number of active auto-refresh cycles in self-refresh mode already used to calculate the energy of the previous windows + int64_t sref_ref_act_cycles_window; + // Number of precharged auto-refresh cycles in self-refresh mode + int64_t sref_ref_pre_cycles; + // Number of precharged auto-refresh cycles in self-refresh mode already used to calculate the energy of the previous window + int64_t sref_ref_pre_cycles_window; + // Number of active auto-refresh cycles during self-refresh exit + int64_t spup_ref_act_cycles; + // Number of precharged auto-refresh cycles during self-refresh exit + int64_t spup_ref_pre_cycles; + + // function for clearing counters + void clearStats(const int64_t timestamp); + + // function for clearing arrays + void clear(); + + // To identify auto-precharges + void getCommands(std::vector& list, + bool lastupdate, + int64_t timestamp = 0); + + private: + MemorySpecification memSpec; + + // Possible bank states are precharged or active + enum BankState { + BANK_PRECHARGED = 0, + BANK_ACTIVE + }; + + int64_t zero; + // Cached last read command from the file + std::vector cached_cmd; + + // Stores the memory commands for analysis + std::vector cmd_list; + + //Stores the memory commands for the next window + std::vector next_window_cmd_list; + + // To save states of the different banks, before entering active + // power-down mode (slow/fast-exit). + std::vector last_bank_state; + // Bank state vector + std::vector bank_state; + + std::vector activation_cycle; + // To keep track of the last ACT cycle + int64_t latest_act_cycle; + // To keep track of the last PRE cycle + int64_t latest_pre_cycle; + // To keep track of the last READ cycle + int64_t latest_read_cycle; + // To keep track of the last WRITE cycle + int64_t latest_write_cycle; + + // To calculate end of READ operation + int64_t end_read_op; + // To calculate end of WRITE operation + int64_t end_write_op; + // To calculate end of ACT operation + int64_t end_act_op; + + // Clock cycle when self-refresh was issued + int64_t sref_cycle; + + // Latest Self-Refresh clock cycle used to calculate the energy of the previous window + int64_t sref_cycle_window; + + // Clock cycle when the latest power-down was issued + int64_t pdn_cycle; + + // Memory State + unsigned mem_state; + + int64_t num_banks; + + // Clock cycle of first activate command when memory state changes to ACT + int64_t first_act_cycle; + std::vector first_act_cycle_banks; + + // Clock cycle of last precharge command when memory state changes to PRE + int64_t last_pre_cycle; + + // To perform timing analysis of a given set of commands and update command counters + void evaluateCommands(std::vector& cmd_list); + + // Handlers for commands that are getting processed + void handleAct( unsigned bank, int64_t timestamp); + void handleRd( unsigned bank, int64_t timestamp); + void handleWr( unsigned bank, int64_t timestamp); + void handleRef( unsigned bank, int64_t timestamp); + void handleRefB(unsigned bank, int64_t timestamp); + void handlePre( unsigned bank, int64_t timestamp); + void handlePreA( unsigned bank, int64_t timestamp); + void handlePdnFAct(unsigned bank, int64_t timestamp); + void handlePdnSAct(unsigned bank, int64_t timestamp); + void handlePdnFPre(unsigned bank, int64_t timestamp); + void handlePdnSPre(unsigned bank, int64_t timestamp); + void handlePupAct( int64_t timestamp); + void handlePupPre( int64_t timestamp); + void handleSREn( unsigned bank, int64_t timestamp); + void handleSREx( unsigned bank, int64_t timestamp); + void handleNopEnd( int64_t timestamp); + + // To calculate time of completion of any issued command + int64_t timeToCompletion(MemCommand::cmds type); + + // To update idle period information whenever active cycles may be idle + void idle_act_update(int64_t latest_read_cycle, + int64_t latest_write_cycle, + int64_t latest_act_cycle, + int64_t timestamp); + + // To update idle period information whenever precharged cycles may be idle + void idle_pre_update(int64_t timestamp, + int64_t latest_pre_cycle); + + // Returns the number of active banks according to the bank_state vector. + unsigned get_num_active_banks(void); + unsigned nActiveBanks(void); + + bool isPrecharged(unsigned bank); + + void printWarningIfActive(const std::string& warning, int type, int64_t timestamp, unsigned bank); + void printWarningIfNotActive(const std::string& warning, int type, int64_t timestamp, unsigned bank); + void printWarningIfPoweredDown(const std::string& warning, int type, int64_t timestamp, unsigned bank); + void printWarning(const std::string& warning, int type, int64_t timestamp, unsigned bank); +}; +} +#endif // ifndef COMMAND_TIMINGS_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemArchitectureSpec.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemArchitectureSpec.cc new file mode 100644 index 0000000000..f3155853d7 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemArchitectureSpec.cc @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemArchitectureSpec.h" + +#include + +using namespace Data; + +MemArchitectureSpec::MemArchitectureSpec() : + burstLength(0), + nbrOfBanks(0), + nbrOfRanks(0), + dataRate(0), + nbrOfColumns(0), + nbrOfRows(0), + width(0), + nbrOfBankGroups(0), + dll(false), + twoVoltageDomains(false), + termination(false) +{ +} + +void MemArchitectureSpec::processParameters() +{ + // Load all parameters in our member variables + nbrOfBanks = getParamValWithDefault("nbrOfBanks", 1); + nbrOfRanks = getParamValWithDefault("nbrOfRanks", 1); + nbrOfBankGroups = getParamValWithDefault("nbrOfBankGroups", 1); + dataRate = getParamValWithDefault("dataRate", 1); + burstLength = getParamValWithDefault("burstLength", 1); + nbrOfColumns = getParamValWithDefault("nbrOfColumns", 1); + nbrOfRows = getParamValWithDefault("nbrOfRows", 1); + width = getParamValWithDefault("width", 1); + assert("memory width should be a multiple of 8" && (width % 8) == 0); + dll = getParamValWithDefault("dll", false); + twoVoltageDomains = getParamValWithDefault("twoVoltageDomains", false); + termination = getParamValWithDefault("termination", false); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemArchitectureSpec.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemArchitectureSpec.h new file mode 100644 index 0000000000..49eddc8ac1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemArchitectureSpec.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, Sven Goossens + * + */ + +#ifndef TOOLS_MEM_ARCHITECTURE_SPEC_H +#define TOOLS_MEM_ARCHITECTURE_SPEC_H + +#include + +#include "Parametrisable.h" + +namespace Data { +class MemArchitectureSpec : public virtual Parametrisable { + public: + MemArchitectureSpec(); + void processParameters(); + + int64_t burstLength; + int64_t nbrOfBanks; + int64_t nbrOfRanks; + int64_t dataRate; + int64_t nbrOfColumns; + int64_t nbrOfRows; + int64_t width; + int64_t nbrOfBankGroups; + bool dll; + bool twoVoltageDomains; + bool termination; +}; +} +#endif // ifndef TOOLS_MEM_ARCHITECTURE_SPEC_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemBankWiseParams.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemBankWiseParams.cc new file mode 100644 index 0000000000..c13281688c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemBankWiseParams.cc @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2016, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Subash Kannoth, Matthias Jung, Éder F. Zulian + * + */ + +#include "MemBankWiseParams.h" + +using namespace Data; +/** + * Sets the default bankwise configurations. + */ +MemBankWiseParams::MemBankWiseParams(): + bwPowerFactRho(100), + bwPowerFactSigma(100), + bwMode(false), + flgPASR(false) +{ +} +/** + * Sets all the bankwise parameters required in bankwise mode + */ +MemBankWiseParams::MemBankWiseParams(int64_t factRho, int64_t factSigma, + bool hasPASR, int64_t pasrMode, + bool opMode, unsigned nbrofBanks) +{ + + bwPowerFactRho = factRho; + bwPowerFactSigma = factSigma; + bwMode = opMode; + flgPASR = hasPASR; + /////////////////////////////////////////////////////////// + // Activate banks for self refresh based on the PASR mode + // ACTIVE - X + // NOT ACTIVE - 0 + /////////////////////////////////////////////////////////// + switch(pasrMode){ + + case(PASR_0):{ + // PASR MODE 0 + // FULL ARRAY + // |X X X X | + // |X X X X | + activeBanks.resize(nbrofBanks); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_1):{ + // PASR MODE 1 + // (1/2) ARRAY + // |X X X X | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 4); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_2):{ + // PASR MODE 2 + // (1/4) ARRAY + // |X X 0 0 | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 6); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_3):{ + // PASR MODE 3 + // (1/8) ARRAY + // |X 0 0 0 | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 7); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_4):{ + // PASR MODE 4 + // (3/4) ARRAY + // |0 0 X X | + // |X X X X | + activeBanks.resize(nbrofBanks - 2); + std::iota(activeBanks.begin(), activeBanks.end(), 2); + break; + } + case(PASR_5):{ + // PASR MODE 5 + // (1/2) ARRAY + // |0 0 0 0 | + // |X X X X | + activeBanks.resize(nbrofBanks - 4); + std::iota(activeBanks.begin(), activeBanks.end(), 4); + break; + } + case(PASR_6):{ + // PASR MODE 6 + // (1/4) ARRAY + // |0 0 0 0 | + // |0 0 X X | + activeBanks.resize(nbrofBanks - 6); + std::iota(activeBanks.begin(), activeBanks.end(), 6); + break; + } + case(PASR_7):{ + // PASR MODE 7 + // (1/8) ARRAY + // |0 0 0 0 | + // |0 0 0 X | + activeBanks.resize(nbrofBanks - 7); + std::iota(activeBanks.begin(), activeBanks.end(), 7); + break; + } + default:{ + // PASR MODE 0 + // FULL ARRAY + // |X X X X | + // |X X X X | + activeBanks.resize(nbrofBanks); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + } +} + +/** + * Returns true if the given bank is active under the current PASR mode. + */ +bool MemBankWiseParams::isBankActiveInPasr(const unsigned bankIdx) const +{ + return (std::find(activeBanks.begin(), activeBanks.end(), bankIdx) + != activeBanks.end()); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemBankWiseParams.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemBankWiseParams.h new file mode 100644 index 0000000000..0cc98fb46f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemBankWiseParams.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2016, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Subash Kannoth, Matthias Jung, Eder Zulian + * + */ +#ifndef MEMBANKWISEPARAMS_H +#define MEMBANKWISEPARAMS_H + +#include +#include +#include +#include + +namespace Data { + class MemBankWiseParams { + public: + // Set of possible PASR modes + enum pasrModes{ + PASR_0, + PASR_1, + PASR_2, + PASR_3, + PASR_4, + PASR_5, + PASR_6, + PASR_7 + }; + // List of active banks under the specified PASR mode + std::vector activeBanks; + // ACT Standby power factor + int64_t bwPowerFactRho; + // Self-Refresh power factor( true : Bankwise mode) + int64_t bwPowerFactSigma; + // Bankwise or Normal mode + bool bwMode; + // Wherther PASR is enabled ( true : enabled ) + bool flgPASR; + //Default constructor + MemBankWiseParams(); + MemBankWiseParams(int64_t factRho, int64_t factSigma, + bool hasPASR, int64_t pasrMode, + bool opMode, unsigned nbrofBanks); + + bool isBankActiveInPasr(const unsigned bankIdx) const; + }; +} + +#endif // MEMBANKWISEPARAMS_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemCommand.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemCommand.cc new file mode 100644 index 0000000000..5e1115e050 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemCommand.cc @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemCommand.h" + +#include // for max + +#include "MemorySpecification.h" + +using namespace Data; +using namespace std; + + +MemCommand::MemCommand(MemCommand::cmds type, + unsigned bank, int64_t timestamp) : + type(type), + bank(bank), + timestamp(timestamp) +{ +} + +void MemCommand::setType(MemCommand::cmds _type) +{ + type = _type; +} + +MemCommand::cmds MemCommand::getType() const +{ + return type; +} + +void MemCommand::setBank(unsigned _bank) +{ + bank = _bank; +} + +unsigned MemCommand::getBank() const +{ + return bank; +} + +// For auto-precharge with read or write - to calculate cycle of precharge +int64_t MemCommand::getPrechargeOffset(const MemorySpecification& memSpec, + MemCommand::cmds type) const +{ + int64_t precharge_offset = 0; + + int64_t BL = memSpec.memArchSpec.burstLength; + int64_t RTP = memSpec.memTimingSpec.RTP; + int64_t dataRate = memSpec.memArchSpec.dataRate; + int64_t AL = memSpec.memTimingSpec.AL; + int64_t WL = memSpec.memTimingSpec.WL; + int64_t WR = memSpec.memTimingSpec.WR; + int64_t B = BL/dataRate; + + const MemoryType::MemoryType_t& memType = memSpec.memoryType; + + // Read with auto-precharge + if (type == MemCommand::RDA) { + if (memType == MemoryType::DDR2) { + precharge_offset = B + AL - 2 + max(RTP, int64_t(2)); + } else if (memType == MemoryType::DDR3) { + precharge_offset = AL + max(RTP, int64_t(4)); + } else if (memType == MemoryType::DDR4) { + precharge_offset = AL + RTP; + } else if (memType == MemoryType::LPDDR) { + precharge_offset = B; + } else if (memType == MemoryType::LPDDR2) { + precharge_offset = B + max(int64_t(0), RTP - 2); + } else if (memType == MemoryType::LPDDR3) { + precharge_offset = B + max(int64_t(0), RTP - 4); + } else if (memType == MemoryType::WIDEIO_SDR) { + precharge_offset = B; + } + } else if (type == MemCommand::WRA) { // Write with auto-precharge + if (memType == MemoryType::DDR2) { + precharge_offset = B + WL + WR; + } else if (memType == MemoryType::DDR3) { + precharge_offset = B + WL + WR; + } else if (memType == MemoryType::DDR4) { + precharge_offset = B + WL + WR; + } else if (memType == MemoryType::LPDDR) { + precharge_offset = B + WR; // + DQSS actually, but we don't have that parameter. + } else if (memType == MemoryType::LPDDR2) { + precharge_offset = B + WL + WR + 1; + } else if (memType == MemoryType::LPDDR3) { + precharge_offset = B + WL + WR + 1; + } else if (memType == MemoryType::WIDEIO_SDR) { + precharge_offset = B + WL + WR - 1; + } + } + + return precharge_offset; +} // MemCommand::getPrechargeOffset + +void MemCommand::setTime(int64_t _timestamp) +{ + timestamp = _timestamp; +} + +int64_t MemCommand::getTimeInt64() const +{ + return timestamp; +} + +MemCommand::cmds MemCommand::typeWithoutAutoPrechargeFlag() const +{ + if (type == MemCommand::RDA) { + return MemCommand::RD; + } else if (type == MemCommand::WRA) { + return MemCommand::WR; + } + return type; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemCommand.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemCommand.h new file mode 100644 index 0000000000..3d7b70b5fe --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemCommand.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#ifndef MEMCOMMAND_H +#define MEMCOMMAND_H + +#include +#include +#include + +#include "MemorySpecification.h" + +namespace Data { +class MemCommand { + public: + /* + * 1. ACT - Activate + * 2. RD - Read + * 3. WR - Write + * 4. PRE - Explicit Precharge per bank + * 5. REF - Refresh all banks + * 6 REFB- Refresh a particular bank + * 7. END - To indicate end of trace + * 8. RDA - Read with auto-precharge + * 9. WRA - Write with auto-precharge + * 10. PREA - Precharge all banks + * 11. PDN_F_PRE - Precharge Power-down Entry command (Fast-Exit) + * 12. PDN_S_PRE - Precharge Power-down Entry command (Slow-Exit) + * 13. PDN_F_ACT - Active Power-down Entry command (Fast-Exit) + * 14. PDN_S_ACT - Active Power-down Entry command (Slow-Exit) + * 15. PUP_PRE - Precharge Power-down Exit + * 16. PUP_ACT - Active Power-down Exit + * 17. SREN - Self-Refresh Entry command + * 18. SREX - Self-refresh Exit + * 19. NOP - To indicate end of trace + */ + + enum cmds { + ACT = 0, + RD = 1, + WR = 2, + PRE = 3, + REF = 4, + REFB = 5, + END = 6, + RDA = 7, + WRA = 8, + PREA = 9, + PDN_F_PRE = 10, + PDN_S_PRE = 11, + PDN_F_ACT = 12, + PDN_S_ACT = 13, + PUP_PRE = 14, + PUP_ACT = 15, + SREN = 16, + SREX = 17, + NOP = 18, + UNINITIALIZED = 19 + }; + +// MemCommand(); + MemCommand( + // Command Type + MemCommand::cmds type = UNINITIALIZED, + // Target Bank + unsigned bank = 0, + // Command Issue Timestamp (in cc) + int64_t timestamp = 0L); + + // Get command type + cmds getType() const; + + // Set command type + void setType(MemCommand::cmds type); + + // Set target Bank + void setBank(unsigned bank); + + // Get target Bank + unsigned getBank() const; + + // Set timestamp + void setTime(int64_t _timestamp); + + // Get timestamp + int64_t getTimeInt64() const; + + cmds typeWithoutAutoPrechargeFlag() const; + + // To calculate precharge offset after read or write with auto-precharge + int64_t getPrechargeOffset(const MemorySpecification& memSpec, + MemCommand::cmds type) const; + + // To check for equivalence + + bool operator==(const MemCommand& other) const + { + if ((getType() == other.getType()) && + (getBank() == other.getBank()) + ) { + return true; + } else { + return false; + } + } + + static const unsigned int nCommands = 20; + + static std::string* getCommandTypeStrings() + { + static std::string type_map[nCommands] = { "ACT", + "RD", + "WR", + "PRE", + "REF", + "REFB", + "END", + "RDA", + "WRA", + "PREA", + "PDN_F_PRE", + "PDN_S_PRE", + "PDN_F_ACT", + "PDN_S_ACT", + "PUP_PRE", + "PUP_ACT", + "SREN", + "SREX", + "NOP", + "UNINITIALIZED" }; + + return type_map; + } + + // To identify command type from name + static cmds getTypeFromName(const std::string& name) + { + std::string* typeStrings = getCommandTypeStrings(); + + for (size_t typeId = 0; typeId < nCommands; typeId++) { + if (typeStrings[typeId] == name) { + cmds commandType = static_cast(typeId); + return commandType; + } + } + assert(false); // Unknown name. + return NOP; // For clang compilation + } + + private: + MemCommand::cmds type; + unsigned bank; + int64_t timestamp; +}; +} +#endif // ifndef MEMCOMMAND_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemPowerSpec.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemPowerSpec.cc new file mode 100644 index 0000000000..2f7011c0e2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemPowerSpec.cc @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemPowerSpec.h" + +using namespace Data; + +MemPowerSpec::MemPowerSpec() : + idd0(0.0), + idd02(0.0), + idd2p0(0.0), + idd2p02(0.0), + idd2p1(0.0), + idd2p12(0.0), + idd2n(0.0), + idd2n2(0.0), + idd3p0(0.0), + idd3p02(0.0), + idd3p1(0.0), + idd3p12(0.0), + idd3n(0.0), + idd3n2(0.0), + idd4r(0.0), + idd4r2(0.0), + idd4w(0.0), + idd4w2(0.0), + idd5(0.0), + idd52(0.0), + idd5B(0.0), + idd6(0.0), + idd62(0.0), + vdd(0.0), + vdd2(0.0), + capacitance(0.0), + ioPower(0.0), + wrOdtPower(0.0), + termRdPower(0.0), + termWrPower(0.0) +{ +} + +void MemPowerSpec::processParameters() +{ + idd0 = getParamValWithDefault("idd0", 0.0); + idd02 = getParamValWithDefault("idd02", 0.0); + idd2p0 = getParamValWithDefault("idd2p0", 0.0); + idd2p02 = getParamValWithDefault("idd2p02", 0.0); + idd2p1 = getParamValWithDefault("idd2p1", 0.0); + idd2p12 = getParamValWithDefault("idd2p12", 0.0); + idd2n = getParamValWithDefault("idd2n", 0.0); + idd2n2 = getParamValWithDefault("idd2n2", 0.0); + idd3p0 = getParamValWithDefault("idd3p0", 0.0); + idd3p02 = getParamValWithDefault("idd3p02", 0.0); + idd3p1 = getParamValWithDefault("idd3p1", 0.0); + idd3p12 = getParamValWithDefault("idd3p12", 0.0); + idd3n = getParamValWithDefault("idd3n", 0.0); + idd3n2 = getParamValWithDefault("idd3n2", 0.0); + idd4r = getParamValWithDefault("idd4r", 0.0); + idd4r2 = getParamValWithDefault("idd4r2", 0.0); + idd4w = getParamValWithDefault("idd4w", 0.0); + idd4w2 = getParamValWithDefault("idd4w2", 0.0); + idd5 = getParamValWithDefault("idd5", 0.0); + idd52 = getParamValWithDefault("idd52", 0.0); + idd5B = getParamValWithDefault("idd5B", 0.0); + idd6 = getParamValWithDefault("idd6", 0.0); + idd62 = getParamValWithDefault("idd62", 0.0); + vdd = getParamValWithDefault("vdd", 0.0); + vdd2 = getParamValWithDefault("vdd2", 0.0); + + capacitance = getParamValWithDefault("capacitance", 0.0); + ioPower = getParamValWithDefault("ioPower", 0.0); + wrOdtPower = getParamValWithDefault("wrOdtPower", 0.0); + termRdPower = getParamValWithDefault("termRdPower", 0.0); + termWrPower = getParamValWithDefault("termWrPower", 0.0); +} // MemPowerSpec::processParameters diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemPowerSpec.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemPowerSpec.h new file mode 100644 index 0000000000..c5243dcdf5 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemPowerSpec.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "Parametrisable.h" + +namespace Data { +class MemPowerSpec : public virtual Parametrisable { + public: + MemPowerSpec(); + void processParameters(); + + double idd0; + double idd02; + double idd2p0; + double idd2p02; + double idd2p1; + double idd2p12; + double idd2n; + double idd2n2; + double idd3p0; + double idd3p02; + double idd3p1; + double idd3p12; + double idd3n; + double idd3n2; + double idd4r; + double idd4r2; + double idd4w; + double idd4w2; + double idd5; + double idd52; + double idd5B; + double idd6; + double idd62; + double vdd; + double vdd2; + + double capacitance; + double ioPower; + double wrOdtPower; + double termRdPower; + double termWrPower; +}; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemTimingSpec.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemTimingSpec.cc new file mode 100644 index 0000000000..54b07e3bc3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemTimingSpec.cc @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemTimingSpec.h" + +using namespace Data; + +MemTimingSpec::MemTimingSpec() : + clkMhz(0.0), + RC(0), + RCD(0), + CCD(0), + CCD_S(0), + CCD_L(0), + RRD(0), + RRD_S(0), + RRD_L(0), + FAW(0), + TAW(0), + WTR(0), + WTR_S(0), + WTR_L(0), + REFI(0), + RL(0), + RP(0), + RFC(0), + REFB(0), + RAS(0), + WL(0), + AL(0), + DQSCK(0), + RTP(0), + WR(0), + XP(0), + XPDLL(0), + XS(0), + XSDLL(0), + CKE(0), + CKESR(0), + clkPeriod(0.0) +{ +} + +void MemTimingSpec::processParameters() +{ + clkMhz = getParamValWithDefault("clkMhz", 0.0); + RC = getParamValWithDefault("RC", 0); + RCD = getParamValWithDefault("RCD", 0); + CCD = getParamValWithDefault("CCD", 0); + RRD = getParamValWithDefault("RRD", 0); + WTR = getParamValWithDefault("WTR", 0); + CCD_S = getParamValWithDefault("CCD_S", 0); + CCD_L = getParamValWithDefault("CCD_L", 0); + RRD_S = getParamValWithDefault("RRD_S", 0); + RRD_L = getParamValWithDefault("RRD_L", 0); + WTR_S = getParamValWithDefault("WTR_S", 0); + WTR_L = getParamValWithDefault("WTR_L", 0); + TAW = getParamValWithDefault("TAW", 0); + FAW = getParamValWithDefault("FAW", 0); + REFI = getParamValWithDefault("REFI", 0); + RL = getParamValWithDefault("RL", 0); + RP = getParamValWithDefault("RP", 0); + RFC = getParamValWithDefault("RFC", 0); + REFB = getParamValWithDefault("REFB", 0); + RAS = getParamValWithDefault("RAS", 0); + WL = getParamValWithDefault("WL", 0); + AL = getParamValWithDefault("AL", 0); + DQSCK = getParamValWithDefault("DQSCK", 0); + RTP = getParamValWithDefault("RTP", 0); + WR = getParamValWithDefault("WR", 0); + XP = getParamValWithDefault("XP", 0); + XPDLL = getParamValWithDefault("XPDLL", 0); + XS = getParamValWithDefault("XS", 0); + XSDLL = getParamValWithDefault("XSDLL", 0); + CKE = getParamValWithDefault("CKE", 0); + CKESR = getParamValWithDefault("CKESR", 0); + clkPeriod = 1000.0 / clkMhz; +} // MemTimingSpec::processParameters diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemTimingSpec.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemTimingSpec.h new file mode 100644 index 0000000000..2413177b0f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemTimingSpec.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, Sven Goossens + * + */ + +#include + +#include "Parametrisable.h" + +namespace Data { +class MemTimingSpec : public virtual Parametrisable { + public: + MemTimingSpec(); + void processParameters(); + + double clkMhz; + int64_t RC; + int64_t RCD; + int64_t CCD; + int64_t CCD_S; + int64_t CCD_L; + int64_t RRD; + int64_t RRD_S; + int64_t RRD_L; + int64_t FAW; + int64_t TAW; + int64_t WTR; + int64_t WTR_S; + int64_t WTR_L; + int64_t REFI; + int64_t RL; + int64_t RP; + int64_t RFC; + int64_t REFB; + int64_t RAS; + int64_t WL; + int64_t AL; + int64_t DQSCK; + int64_t RTP; + int64_t WR; + int64_t XP; + int64_t XPDLL; + int64_t XS; + int64_t XSDLL; + int64_t CKE; + int64_t CKESR; + double clkPeriod; +}; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemoryPowerModel.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemoryPowerModel.cc new file mode 100644 index 0000000000..5c3549c00a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemoryPowerModel.cc @@ -0,0 +1,610 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#include "MemoryPowerModel.h" + +#include + +#include // For pow +#include // fmtflags +#include + +using namespace std; +using namespace Data; + +MemoryPowerModel::MemoryPowerModel() +{ + total_cycles = 0; + energy.total_energy = 0; +} + +// Calculate energy and average power consumption for the given command trace + +void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, + const CommandAnalysis& c, + int term, + const MemBankWiseParams& bwPowerParams) +{ + const MemTimingSpec& t = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + const MemPowerSpec& mps = memSpec.memPowerSpec; + const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks; + + energy.act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.read_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.write_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.refb_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.act_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pre_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.idle_energy_act_banks.assign(static_cast(nbrofBanks), 0.0); + energy.idle_energy_pre_banks.assign(static_cast(nbrofBanks), 0.0); + energy.f_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.f_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.s_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.s_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pup_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pup_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.total_energy_banks.assign(static_cast(nbrofBanks), 0.0); + + energy.act_energy = 0.0; + energy.pre_energy = 0.0; + energy.read_energy = 0.0; + energy.write_energy = 0.0; + energy.ref_energy = 0.0; + energy.act_stdby_energy = 0.0; + energy.pre_stdby_energy = 0.0; + energy.idle_energy_act = 0.0; + energy.idle_energy_pre = 0.0; + energy.window_energy = 0.0; + energy.f_act_pd_energy = 0.0; + energy.f_pre_pd_energy = 0.0; + energy.s_act_pd_energy = 0.0; + energy.s_pre_pd_energy = 0.0; + energy.sref_energy = 0.0; + energy.sref_ref_energy = 0.0; + energy.sref_ref_act_energy = 0.0; + energy.sref_ref_pre_energy = 0.0; + energy.spup_energy = 0.0; + energy.spup_ref_energy = 0.0; + energy.spup_ref_act_energy = 0.0; + energy.spup_ref_pre_energy = 0.0; + energy.pup_act_energy = 0.0; + energy.pup_pre_energy = 0.0; + power.IO_power = 0.0; + power.WR_ODT_power = 0.0; + power.TermRD_power = 0.0; + power.TermWR_power = 0.0; + energy.read_io_energy = 0.0; + energy.write_term_energy = 0.0; + energy.read_oterm_energy = 0.0; + energy.write_oterm_energy = 0.0; + energy.io_term_energy = 0.0; + + // How long a single burst takes, measured in command-clock cycles. + int64_t burstCc = memArchSpec.burstLength / memArchSpec.dataRate; + + // IO and Termination Power measures are included, if required. + if (term) { + io_term_power(memSpec); + + // memArchSpec.width represents the number of data (dq) pins. + // 1 DQS pin is associated with every data byte + int64_t dqPlusDqsBits = memArchSpec.width + memArchSpec.width / 8; + // 1 DQS and 1 DM pin is associated with every data byte + int64_t dqPlusDqsPlusMaskBits = memArchSpec.width + memArchSpec.width / 8 + memArchSpec.width / 8; + // Size of one clock period for the data bus. + double ddrPeriod = t.clkPeriod / static_cast(memArchSpec.dataRate); + + // Read IO power is consumed by each DQ (data) and DQS (data strobe) pin + energy.read_io_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength, + ddrPeriod, + power.IO_power, + dqPlusDqsBits); + + // Write ODT power is consumed by each DQ (data), DQS (data strobe) and DM + energy.write_term_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength, + ddrPeriod, + power.WR_ODT_power, + dqPlusDqsPlusMaskBits); + + if (memArchSpec.nbrOfRanks > 1) { + // Termination power consumed in the idle rank during reads on the active + // rank by each DQ (data) and DQS (data strobe) pin. + energy.read_oterm_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength, + ddrPeriod, + power.TermRD_power, + dqPlusDqsBits); + + // Termination power consumed in the idle rank during writes on the active + // rank by each DQ (data), DQS (data strobe) and DM (data mask) pin. + energy.write_oterm_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength, + ddrPeriod, + power.TermWR_power, + dqPlusDqsPlusMaskBits); + } + + // Sum of all IO and termination energy + energy.io_term_energy = energy.read_io_energy + energy.write_term_energy + + energy.read_oterm_energy + energy.write_oterm_energy; + } + + window_cycles = c.actcycles + c.precycles + + c.f_act_pdcycles + c.f_pre_pdcycles + + c.s_act_pdcycles + c.s_pre_pdcycles + c.sref_cycles + + c.sref_ref_act_cycles + c.sref_ref_pre_cycles + + c.spup_ref_act_cycles + c.spup_ref_pre_cycles; + + EnergyDomain vdd0Domain(mps.vdd, t.clkPeriod); + + energy.act_energy = vdd0Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd0 - mps.idd3n); + energy.pre_energy = vdd0Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd0 - mps.idd2n); + energy.read_energy = vdd0Domain.calcTivEnergy(sum(c.numberofreadsBanks) * burstCc , mps.idd4r - mps.idd3n); + energy.write_energy = vdd0Domain.calcTivEnergy(sum(c.numberofwritesBanks) * burstCc , mps.idd4w - mps.idd3n); + energy.ref_energy = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd5 - mps.idd3n); + energy.pre_stdby_energy = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n); + energy.act_stdby_energy = vdd0Domain.calcTivEnergy(c.actcycles, mps.idd3n); + + // Using the number of cycles that at least one bank is active here + // But the current iddrho is less than idd3n + double iddrho = (static_cast(bwPowerParams.bwPowerFactRho) / 100.0) * (mps.idd3n - mps.idd2n) + mps.idd2n; + double esharedActStdby = vdd0Domain.calcTivEnergy(c.actcycles, iddrho); + // Fixed componenent for PASR + double iddsigma = (static_cast(bwPowerParams.bwPowerFactSigma) / 100.0) * mps.idd6; + double esharedPASR = vdd0Domain.calcTivEnergy(c.sref_cycles, iddsigma); + // ione is Active background current for a single bank. When a single bank is Active + //,all the other remainig (B-1) banks will consume a current of iddrho (based on factor Rho) + // So to derrive ione we add (B-1)*iddrho to the idd3n and distribute it to each banks. + double ione = (mps.idd3n + (iddrho * (static_cast(nbrofBanks - 1)))) / (static_cast(nbrofBanks)); + // If memory specification does not provide bank wise refresh current, + // approximate it to single bank background current removed from + // single bank active current + double idd5Blocal = (mps.idd5B == 0.0) ? (mps.idd0 - ione) :(mps.idd5B); + // if memory specification does not provide the REFB timing approximate it + // to time of ACT + PRE + int64_t tRefBlocal = (t.REFB == 0) ? (t.RAS + t.RP) : (t.REFB); + + //Distribution of energy componets to each banks + for (unsigned i = 0; i < nbrofBanks; i++) { + energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - ione); + energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RP), mps.idd0 - ione); + energy.read_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofreadsBanks[i] * burstCc, mps.idd4r - mps.idd3n); + energy.write_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofwritesBanks[i] * burstCc, mps.idd4w - mps.idd3n); + energy.ref_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC, mps.idd5 - mps.idd3n) / static_cast(nbrofBanks); + energy.refb_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefbBanks[i] * tRefBlocal, idd5Blocal); + energy.pre_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n) / static_cast(nbrofBanks); + energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho) / static_cast(nbrofBanks)) + + esharedActStdby / static_cast(nbrofBanks); + energy.idle_energy_act_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n) / static_cast(nbrofBanks); + energy.idle_energy_pre_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n) / static_cast(nbrofBanks); + energy.f_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p1) / static_cast(nbrofBanks); + energy.f_pre_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p1) / static_cast(nbrofBanks); + energy.s_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p0) / static_cast(nbrofBanks); + energy.s_pre_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p0) / static_cast(nbrofBanks); + + energy.sref_energy_banks[i] = engy_sref_banks(mps.idd6, mps.idd3n, + mps.idd5, mps.vdd, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod,esharedPASR,bwPowerParams,i,nbrofBanks + ); + energy.sref_ref_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p0) / static_cast(nbrofBanks); + energy.sref_ref_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p0) / static_cast(nbrofBanks); + energy.sref_ref_energy_banks[i] = energy.sref_ref_act_energy_banks[i] + energy.sref_ref_pre_energy_banks[i] ;// + + energy.spup_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_cycles, mps.idd2n) / static_cast(nbrofBanks); + energy.spup_ref_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n) / static_cast(nbrofBanks);// + energy.spup_ref_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n) / static_cast(nbrofBanks); + energy.spup_ref_energy_banks[i] = ( energy.spup_ref_act_energy + energy.spup_ref_pre_energy ) / static_cast(nbrofBanks); + energy.pup_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n) / static_cast(nbrofBanks); + energy.pup_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n) / static_cast(nbrofBanks); + } + + // Idle energy in the active standby clock cycles + energy.idle_energy_act = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n); + // Idle energy in the precharge standby clock cycles + energy.idle_energy_pre = vdd0Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n); + // fast-exit active power-down cycles energy + energy.f_act_pd_energy = vdd0Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p1); + // fast-exit precharged power-down cycles energy + energy.f_pre_pd_energy = vdd0Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p1); + // slow-exit active power-down cycles energy + energy.s_act_pd_energy = vdd0Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p0); + // slow-exit precharged power-down cycles energy + energy.s_pre_pd_energy = vdd0Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p0); + + // self-refresh cycles energy including a refresh per self-refresh entry + energy.sref_energy = engy_sref(mps.idd6, mps.idd3n, + mps.idd5, mps.vdd, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod); + + // background energy during active auto-refresh cycles in self-refresh + energy.sref_ref_act_energy = vdd0Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p0); + // background energy during precharged auto-refresh cycles in self-refresh + energy.sref_ref_pre_energy = vdd0Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p0); + // background energy during active auto-refresh cycles in self-refresh exit + energy.spup_ref_act_energy = vdd0Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n); + // background energy during precharged auto-refresh cycles in self-refresh exit + energy.spup_ref_pre_energy = vdd0Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n); + // self-refresh power-up cycles energy -- included + energy.spup_energy = vdd0Domain.calcTivEnergy(c.spup_cycles, mps.idd2n); + // active power-up cycles energy - same as active standby -- included + energy.pup_act_energy = vdd0Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n); + // precharged power-up cycles energy - same as precharged standby -- included + energy.pup_pre_energy = vdd0Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n); + + // similar equations as before to support multiple voltage domains in LPDDR2 + // and WIDEIO memories + if (memArchSpec.twoVoltageDomains) { + EnergyDomain vdd2Domain(mps.vdd2, t.clkPeriod); + + energy.act_energy += vdd2Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd02 - mps.idd3n2); + energy.pre_energy += vdd2Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd02 - mps.idd2n2); + energy.read_energy += vdd2Domain.calcTivEnergy(sum(c.numberofreadsBanks) * burstCc , mps.idd4r2 - mps.idd3n2); + energy.write_energy += vdd2Domain.calcTivEnergy(sum(c.numberofwritesBanks) * burstCc , mps.idd4w2 - mps.idd3n2); + energy.ref_energy += vdd2Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd52 - mps.idd3n2); + energy.pre_stdby_energy += vdd2Domain.calcTivEnergy(c.precycles, mps.idd2n2); + energy.act_stdby_energy += vdd2Domain.calcTivEnergy(c.actcycles, mps.idd3n2); + + // Idle energy in the active standby clock cycles + energy.idle_energy_act += vdd2Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n2); + // Idle energy in the precharge standby clock cycles + energy.idle_energy_pre += vdd2Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n2); + // fast-exit active power-down cycles energy + energy.f_act_pd_energy += vdd2Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p12); + // fast-exit precharged power-down cycles energy + energy.f_pre_pd_energy += vdd2Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p12); + // slow-exit active power-down cycles energy + energy.s_act_pd_energy += vdd2Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p02); + // slow-exit precharged power-down cycles energy + energy.s_pre_pd_energy += vdd2Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p02); + + energy.sref_energy += engy_sref(mps.idd62, mps.idd3n2, + mps.idd52, mps.vdd2, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod); + + // background energy during active auto-refresh cycles in self-refresh + energy.sref_ref_act_energy += vdd2Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p02); + // background energy during precharged auto-refresh cycles in self-refresh + energy.sref_ref_pre_energy += vdd2Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p02); + // background energy during active auto-refresh cycles in self-refresh exit + energy.spup_ref_act_energy += vdd2Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n2); + // background energy during precharged auto-refresh cycles in self-refresh exit + energy.spup_ref_pre_energy += vdd2Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n2); + // self-refresh power-up cycles energy -- included + energy.spup_energy += vdd2Domain.calcTivEnergy(c.spup_cycles, mps.idd2n2); + // active power-up cycles energy - same as active standby -- included + energy.pup_act_energy += vdd2Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n2); + // precharged power-up cycles energy - same as precharged standby -- included + energy.pup_pre_energy += vdd2Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n2); + } + + // auto-refresh energy during self-refresh cycles + energy.sref_ref_energy = energy.sref_ref_act_energy + energy.sref_ref_pre_energy; + + // auto-refresh energy during self-refresh exit cycles + energy.spup_ref_energy = energy.spup_ref_act_energy + energy.spup_ref_pre_energy; + + // adding all energy components for the active rank and all background and idle + // energy components for both ranks (in a dual-rank system) + + if (bwPowerParams.bwMode) { + // Calculate total energy per bank. + for (unsigned i = 0; i < nbrofBanks; i++) { + energy.total_energy_banks[i] = energy.act_energy_banks[i] + energy.pre_energy_banks[i] + energy.read_energy_banks[i] + + energy.ref_energy_banks[i] + energy.write_energy_banks[i] + energy.refb_energy_banks[i] + + static_cast(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i] + + energy.pre_stdby_energy_banks[i] + energy.f_pre_pd_energy_banks[i] + energy.s_act_pd_energy_banks[i] + + energy.s_pre_pd_energy_banks[i]+ energy.sref_ref_energy_banks[i] + energy.spup_ref_energy_banks[i]; + } + // Calculate total energy for all banks. + energy.window_energy = sum(energy.total_energy_banks) + energy.io_term_energy; + + } else { + energy.window_energy = energy.act_energy + energy.pre_energy + energy.read_energy + energy.write_energy + + energy.ref_energy + energy.io_term_energy + sum(energy.refb_energy_banks) + + static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + + energy.pre_stdby_energy + energy.sref_energy + energy.f_act_pd_energy + + energy.f_pre_pd_energy + energy.s_act_pd_energy + energy.s_pre_pd_energy + + energy.sref_ref_energy + energy.spup_ref_energy); + } + + power.window_average_power = energy.window_energy / (static_cast(window_cycles) * t.clkPeriod); + + total_cycles += window_cycles; + + energy.total_energy += energy.window_energy; + + // Calculate the average power consumption + power.average_power = energy.total_energy / (static_cast(total_cycles) * t.clkPeriod); +} // MemoryPowerModel::power_calc + +void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, const CommandAnalysis& c, bool bankwiseMode) const +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + const uint64_t nRanks = static_cast(memArchSpec.nbrOfRanks); + const char eUnit[] = " pJ"; + const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks; + double nRanksDouble = static_cast(nRanks); + + ios_base::fmtflags flags = cout.flags(); + streamsize precision = cout.precision(); + cout.precision(0); + + if (bankwiseMode) { + cout << endl << "* Bankwise Details:"; + for (unsigned i = 0; i < nbrofBanks; i++) { + cout << endl << "## @ Bank " << i << fixed + << endl << " #ACT commands: " << c.numberofactsBanks[i] + << endl << " #RD + #RDA commands: " << c.numberofreadsBanks[i] + << endl << " #WR + #WRA commands: " << c.numberofwritesBanks[i] + << endl << " #PRE (+ PREA) commands: " << c.numberofpresBanks[i]; + } + cout << endl; + } + + cout << endl << "* Trace Details:" << fixed << endl + << endl << "#ACT commands: " << sum(c.numberofactsBanks) + << endl << "#RD + #RDA commands: " << sum(c.numberofreadsBanks) + << endl << "#WR + #WRA commands: " << sum(c.numberofwritesBanks) + /* #PRE commands (precharge all counts a number of #PRE commands equal to the number of active banks) */ + << endl << "#PRE (+ PREA) commands: " << sum(c.numberofpresBanks) + << endl << "#REF commands: " << c.numberofrefs + << endl << "#REFB commands: " << sum(c.numberofrefbBanks) + << endl << "#Active Cycles: " << c.actcycles + << endl << " #Active Idle Cycles: " << c.idlecycles_act + << endl << " #Active Power-Up Cycles: " << c.pup_act_cycles + << endl << " #Auto-Refresh Active cycles during Self-Refresh Power-Up: " << c.spup_ref_act_cycles + << endl << "#Precharged Cycles: " << c.precycles + << endl << " #Precharged Idle Cycles: " << c.idlecycles_pre + << endl << " #Precharged Power-Up Cycles: " << c.pup_pre_cycles + << endl << " #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: " << c.spup_ref_pre_cycles + << endl << " #Self-Refresh Power-Up Cycles: " << c.spup_cycles + << endl << "Total Idle Cycles (Active + Precharged): " << c.idlecycles_act + c.idlecycles_pre + << endl << "#Power-Downs: " << c.f_act_pdns + c.s_act_pdns + c.f_pre_pdns + c.s_pre_pdns + << endl << " #Active Fast-exit Power-Downs: " << c.f_act_pdns + << endl << " #Active Slow-exit Power-Downs: " << c.s_act_pdns + << endl << " #Precharged Fast-exit Power-Downs: " << c.f_pre_pdns + << endl << " #Precharged Slow-exit Power-Downs: " << c.s_pre_pdns + << endl << "#Power-Down Cycles: " << c.f_act_pdcycles + c.s_act_pdcycles + c.f_pre_pdcycles + c.s_pre_pdcycles + << endl << " #Active Fast-exit Power-Down Cycles: " << c.f_act_pdcycles + << endl << " #Active Slow-exit Power-Down Cycles: " << c.s_act_pdcycles + << endl << " #Auto-Refresh Active cycles during Self-Refresh: " << c.sref_ref_act_cycles + << endl << " #Precharged Fast-exit Power-Down Cycles: " << c.f_pre_pdcycles + << endl << " #Precharged Slow-exit Power-Down Cycles: " << c.s_pre_pdcycles + << endl << " #Auto-Refresh Precharged cycles during Self-Refresh: " << c.sref_ref_pre_cycles + << endl << "#Auto-Refresh Cycles: " << c.numberofrefs * memTimingSpec.RFC + << endl << "#Self-Refreshes: " << c.numberofsrefs + << endl << "#Self-Refresh Cycles: " << c.sref_cycles + << endl << "----------------------------------------" + << endl << "Total Trace Length (clock cycles): " << total_cycles + << endl << "----------------------------------------" << endl; + + if (bankwiseMode) { + cout << endl << "* Bankwise Details:"; + for (unsigned i = 0; i < nbrofBanks; i++) { + cout << endl << "## @ Bank " << i << fixed + << endl << " ACT Cmd Energy: " << energy.act_energy_banks[i] << eUnit + << endl << " PRE Cmd Energy: " << energy.pre_energy_banks[i] << eUnit + << endl << " RD Cmd Energy: " << energy.read_energy_banks[i] << eUnit + << endl << " WR Cmd Energy: " << energy.write_energy_banks[i] << eUnit + << endl << " Auto-Refresh Energy: " << energy.ref_energy_banks[i] << eUnit + << endl << " Bankwise-Refresh Energy: " << energy.refb_energy_banks[i] << eUnit + << endl << " ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy_banks[i] << eUnit + << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit + << endl << " Active Idle Energy: "<< nRanksDouble * energy.idle_energy_act_banks[i] << eUnit + << endl << " Precharge Idle Energy: "<< nRanksDouble * energy.idle_energy_pre_banks[i] << eUnit + << endl << " Fast-Exit Active Power-Down Energy: "<< nRanksDouble * energy.f_act_pd_energy_banks[i] << eUnit + << endl << " Fast-Exit Precharged Power-Down Energy: "<< nRanksDouble * energy.f_pre_pd_energy_banks[i] << eUnit + << endl << " Slow-Exit Active Power-Down Energy: "<< nRanksDouble * energy.s_act_pd_energy_banks[i] << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy: "<< nRanksDouble * energy.s_pre_pd_energy_banks[i] << eUnit + << endl << " Self-Refresh Energy: "<< nRanksDouble * energy.sref_energy_banks[i] << eUnit + << endl << " Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: "<< nRanksDouble * energy.sref_ref_act_energy_banks[i] << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy_banks[i] << eUnit + << endl << " Self-Refresh Power-Up Energy: "<< nRanksDouble * energy.spup_energy_banks[i] << eUnit + << endl << " Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_act_energy_banks[i] << eUnit + << endl << " Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_pre_energy_banks[i] << eUnit + << endl << " Active Power-Up Energy: "<< nRanksDouble * energy.pup_act_energy_banks[i] << eUnit + << endl << " Precharged Power-Up Energy: "<< nRanksDouble * energy.pup_pre_energy_banks[i] << eUnit + << endl << " Total Energy: "<< energy.total_energy_banks[i] << eUnit + << endl; + } + cout << endl; + } + + cout.precision(2); + cout << endl << "* Trace Power and Energy Estimates:" << endl + << endl << "ACT Cmd Energy: " << energy.act_energy << eUnit + << endl << "PRE Cmd Energy: " << energy.pre_energy << eUnit + << endl << "RD Cmd Energy: " << energy.read_energy << eUnit + << endl << "WR Cmd Energy: " << energy.write_energy << eUnit; + + if (term) { + cout << endl << "RD I/O Energy: " << energy.read_io_energy << eUnit << endl; + // No Termination for LPDDR/2/3 and DDR memories + if (memSpec.memArchSpec.termination) { + cout << "WR Termination Energy: " << energy.write_term_energy << eUnit << endl; + } + + if (nRanks > 1 && memSpec.memArchSpec.termination) { + cout << "RD Termination Energy (Idle rank): " << energy.read_oterm_energy << eUnit + << endl << "WR Termination Energy (Idle rank): " << energy.write_oterm_energy << eUnit << endl; + } + } + + cout << "ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy << eUnit + << endl << " Active Idle Energy: " << nRanksDouble * energy.idle_energy_act << eUnit + << endl << " Active Power-Up Energy: " << nRanksDouble * energy.pup_act_energy << eUnit + << endl << " Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: " << nRanksDouble * energy.spup_ref_act_energy << eUnit + << endl << "PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy << eUnit + << endl << " Precharge Idle Energy: " << nRanksDouble * energy.idle_energy_pre << eUnit + << endl << " Precharged Power-Up Energy: " << nRanksDouble * energy.pup_pre_energy << eUnit + << endl << " Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: " << nRanksDouble * energy.spup_ref_pre_energy << eUnit + << endl << " Self-Refresh Power-Up Energy: " << nRanksDouble * energy.spup_energy << eUnit + << endl << "Total Idle Energy (Active + Precharged): " << nRanksDouble * (energy.idle_energy_act + energy.idle_energy_pre) << eUnit + << endl << "Total Power-Down Energy: " << nRanksDouble * (energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy + energy.s_pre_pd_energy) << eUnit + << endl << " Fast-Exit Active Power-Down Energy: " << nRanksDouble * energy.f_act_pd_energy << eUnit + << endl << " Slow-Exit Active Power-Down Energy: " << nRanksDouble * energy.s_act_pd_energy << eUnit + << endl << " Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_act_energy << eUnit + << endl << " Fast-Exit Precharged Power-Down Energy: " << nRanksDouble * energy.f_pre_pd_energy << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy: " << nRanksDouble * energy.s_pre_pd_energy << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy << eUnit + << endl << "Auto-Refresh Energy: " << energy.ref_energy << eUnit + << endl << "Bankwise-Refresh Energy: " << sum(energy.refb_energy_banks) << eUnit + << endl << "Self-Refresh Energy: " << nRanksDouble * energy.sref_energy << eUnit + << endl << "----------------------------------------" + << endl << "Total Trace Energy: " << energy.total_energy << eUnit + << endl << "Average Power: " << power.average_power << " mW" + << endl << "----------------------------------------" << endl; + + cout.flags(flags); + cout.precision(precision); +} // MemoryPowerModel::power_print + +// Self-refresh active energy estimation (not including background energy) +double MemoryPowerModel::engy_sref(double idd6, double idd3n, double idd5, + double vdd, double sref_cycles, double sref_ref_act_cycles, + double sref_ref_pre_cycles, double spup_ref_act_cycles, + double spup_ref_pre_cycles, double clk) +{ + double sref_energy; + + sref_energy = ((idd6 * sref_cycles) + ((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles))) + * vdd * clk; + return sref_energy; +} + +// Self-refresh active energy estimation per banks +double MemoryPowerModel::engy_sref_banks(double idd6, double idd3n, double idd5, + double vdd, double sref_cycles, double sref_ref_act_cycles, + double sref_ref_pre_cycles, double spup_ref_act_cycles, + double spup_ref_pre_cycles, double clk, + double esharedPASR, const MemBankWiseParams& bwPowerParams, + unsigned bnkIdx, int64_t nbrofBanks) +{ + // Bankwise Self-refresh energy + double sref_energy_banks; + // Dynamic componenents for PASR energy varying based on PASR mode + double iddsigmaDynBanks; + double pasr_energy_dyn; + // This component is distributed among all banks + double sref_energy_shared; + //Is PASR Active + if (bwPowerParams.flgPASR){ + sref_energy_shared = (((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles)) * vdd * clk) + / static_cast(nbrofBanks); + //if the bank is active under current PASR mode + if (bwPowerParams.isBankActiveInPasr(bnkIdx)){ + // Distribute the sref energy to the active banks + iddsigmaDynBanks = (static_cast(100 - bwPowerParams.bwPowerFactSigma) / (100.0 * static_cast(nbrofBanks))) * idd6; + pasr_energy_dyn = vdd * iddsigmaDynBanks * sref_cycles; + // Add the static components + sref_energy_banks = sref_energy_shared + pasr_energy_dyn + (esharedPASR /static_cast(nbrofBanks)); + + }else{ + sref_energy_banks = (esharedPASR /static_cast(nbrofBanks)); + } + } + //When PASR is not active total all the banks are in Self-Refresh. Thus total Self-Refresh energy is distributed across all banks + else{ + + + sref_energy_banks = (((idd6 * sref_cycles) + ((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles))) + * vdd * clk) + / static_cast(nbrofBanks); + } + return sref_energy_banks; +} + + +// IO and Termination power calculation based on Micron Power Calculators +// Absolute power measures are obtained from Micron Power Calculator (mentioned in mW) +void MemoryPowerModel::io_term_power(const MemorySpecification& memSpec) +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + const MemPowerSpec& memPowerSpec = memSpec.memPowerSpec; + + power.IO_power = memPowerSpec.ioPower; // in mW + power.WR_ODT_power = memPowerSpec.wrOdtPower; // in mW + + if (memArchSpec.nbrOfRanks > 1) { + power.TermRD_power = memPowerSpec.termRdPower; // in mW + power.TermWR_power = memPowerSpec.termWrPower; // in mW + } + + if (memPowerSpec.capacitance != 0.0) { + // If capacity is given, then IO Power depends on DRAM clock frequency. + power.IO_power = memPowerSpec.capacitance * 0.5 * pow(memPowerSpec.vdd2, 2.0) * memTimingSpec.clkMhz * 1000000; + } +} // MemoryPowerModel::io_term_power + + +double MemoryPowerModel::calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const +{ + return static_cast(cycles) * period * power * static_cast(numBits); +} + +// time (t) * current (I) * voltage (V) energy calculation +double EnergyDomain::calcTivEnergy(int64_t cycles, double current) const +{ + return static_cast(cycles) * clkPeriod * current * voltage; +} + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemoryPowerModel.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemoryPowerModel.h new file mode 100644 index 0000000000..916d540a83 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemoryPowerModel.h @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#ifndef MEMORY_POWER_MODEL_H +#define MEMORY_POWER_MODEL_H + +#include +#include "MemorySpecification.h" +#include "MemBankWiseParams.h" +#include "CommandAnalysis.h" + +namespace Data { +class MemoryPowerModel { + public: + + MemoryPowerModel(); + + // Calculate energy and average power consumption for the given memory + // command trace + void power_calc(const MemorySpecification& memSpec, + const CommandAnalysis& c, + int term, + const MemBankWiseParams& bwPowerParams); + + // Used to calculate self-refresh active energy + static double engy_sref(double idd6, + double idd3n, + double idd5, + double vdd, + double sref_cycles_idd6, + double sref_ref_act_cycles, + double sref_ref_pre_cycles, + double spup_ref_act_cycles, + double spup_ref_pre_cycles, + double clk); + static double engy_sref_banks(double idd6, + double idd3n, + double idd5, + double vdd, + double sref_cycles, + double sref_ref_act_cycles, + double sref_ref_pre_cycles, + double spup_ref_act_cycles, + double spup_ref_pre_cycles, + double clk, + double esharedPASR, + const MemBankWiseParams& bwPowerParams, + unsigned bnkIdx, + int64_t nbrofBanks); + + int64_t total_cycles; + + int64_t window_cycles; + + struct Energy { + // Total energy of all activates + double act_energy; + std::vector act_energy_banks; + + // Total energy of all precharges + double pre_energy; + std::vector pre_energy_banks; + + // Total energy of all reads + double read_energy; + std::vector read_energy_banks; + + // Total energy of all writes + double write_energy; + std::vector write_energy_banks; + + // Total energy of all refreshes + double ref_energy; + std::vector ref_energy_banks; + + // Bankwise refresh energy + std::vector refb_energy_banks; + + // Total background energy of all active standby cycles + double act_stdby_energy; + std::vector act_stdby_energy_banks; + + // Total background energy of all precharge standby cycles + double pre_stdby_energy; + std::vector pre_stdby_energy_banks; + + // Total energy of idle cycles in the active mode + double idle_energy_act; + std::vector idle_energy_act_banks; + + // Total energy of idle cycles in the precharge mode + double idle_energy_pre; + std::vector idle_energy_pre_banks; + + // Total trace/pattern energy + double total_energy; + std::vector total_energy_banks; + + // Window energy + double window_energy; + + // Average Power + double average_power; + + // Energy consumed in active/precharged fast/slow-exit modes + double f_act_pd_energy; + std::vector f_act_pd_energy_banks; + + double f_pre_pd_energy; + std::vector f_pre_pd_energy_banks; + + double s_act_pd_energy; + std::vector s_act_pd_energy_banks; + + double s_pre_pd_energy; + std::vector s_pre_pd_energy_banks; + + // Energy consumed in self-refresh mode + double sref_energy; + std::vector sref_energy_banks; + + // Energy consumed in auto-refresh during self-refresh mode + double sref_ref_energy; + std::vector sref_ref_energy_banks; + + double sref_ref_act_energy; + std::vector sref_ref_act_energy_banks; + + double sref_ref_pre_energy; + std::vector sref_ref_pre_energy_banks; + + // Energy consumed in powering-up from self-refresh mode + double spup_energy; + std::vector spup_energy_banks; + + // Energy consumed in auto-refresh during self-refresh power-up + double spup_ref_energy; + std::vector spup_ref_energy_banks; + + double spup_ref_act_energy; + std::vector spup_ref_act_energy_banks; + + double spup_ref_pre_energy; + std::vector spup_ref_pre_energy_banks; + + // Energy consumed in powering-up from active/precharged power-down modes + double pup_act_energy; + std::vector pup_act_energy_banks; + + double pup_pre_energy; + std::vector pup_pre_energy_banks; + + // Energy consumed by IO and Termination + double read_io_energy; // Read IO Energy + double write_term_energy; // Write Termination Energy + double read_oterm_energy; // Read Termination Energy from idle rank + double write_oterm_energy; // Write Termination Energy from idle rank + // Total IO and Termination Energy + double io_term_energy; + }; + + struct Power { + // Power measures corresponding to IO and Termination + double IO_power; // Read IO Power + double WR_ODT_power; // Write ODT Power + double TermRD_power; // Read Termination in idle rank (in dual-rank systems) + double TermWR_power; // Write Termination in idle rank (in dual-rank systems) + + // Average Power + double average_power; + + // Window Average Power + double window_average_power; + }; + + // Print the power and energy + void power_print(const MemorySpecification& memSpec, + int term, + const CommandAnalysis& c, + bool bankwiseMode) const; + + // To derive IO and Termination Power measures using DRAM specification + void io_term_power(const MemorySpecification& memSpec); + + Energy energy; + Power power; + + private: + double calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const; + // Sum quantities (e.g., operations, energy, cycles) that are stored in a per bank basis returning the total amount. + template T sum(const std::vector vec) const { return std::accumulate(vec.begin(), vec.end(), static_cast(0)); } +}; + +class EnergyDomain { + public: + EnergyDomain(double voltage, double clkPeriod) : + voltage(voltage), + clkPeriod(clkPeriod) + {} + + double calcTivEnergy(int64_t cycles, double current) const; + double getVoltage() const{ return voltage; }; + private: + const double voltage; + const double clkPeriod; +}; + +} +#endif // ifndef MEMORY_POWER_MODEL_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemorySpecification.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemorySpecification.cc new file mode 100644 index 0000000000..3f9f188112 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemorySpecification.cc @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemorySpecification.h" + +using namespace std; +using namespace Data; + +// Set variable values from XML +void MemorySpecification::processParameters() +{ + setVarFromParam(&id,"memoryId"); + memoryType = getParamValWithDefault("memoryType", string("DDR3")); + + if (hasParameter("memoryType")) { + memArchSpec.twoVoltageDomains = memoryType.hasTwoVoltageDomains(); + memArchSpec.dll = memoryType.hasDll(); + memArchSpec.termination = memoryType.hasTermination(); + + memPowerSpec.capacitance = memoryType.getCapacitance(); + memPowerSpec.ioPower = memoryType.getIoPower(); + memPowerSpec.wrOdtPower = memoryType.getWrOdtPower(); + memPowerSpec.termRdPower = memoryType.getTermRdPower(); + memPowerSpec.termWrPower = memoryType.getTermWrPower(); + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemorySpecification.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemorySpecification.h new file mode 100644 index 0000000000..16d77ef868 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/MemorySpecification.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#ifndef TOOLS_MEMORY_SPECIFICATION_H +#define TOOLS_MEMORY_SPECIFICATION_H + +#include +#include + +#include "MemArchitectureSpec.h" +#include "MemTimingSpec.h" +#include "MemPowerSpec.h" +#include "Parametrisable.h" + + +namespace Data { +// Supported memory types +class MemoryType { + public: + enum MemoryType_t { + DDR2 = 0, + DDR3, + DDR4, + LPDDR, + LPDDR2, + LPDDR3, + WIDEIO_SDR, + MEMORY_TYPE_INVALID + }; + + MemoryType(MemoryType_t _val) : + val(_val) + { + } + + MemoryType() : + val(MEMORY_TYPE_INVALID) + { + } + + MemoryType(const std::string& _val) : + val(MEMORY_TYPE_INVALID) + { + if (_val == "DDR2") { + val = DDR2; + } else if (_val == "DDR3") { + val = DDR3; + } else if (_val == "DDR4") { + val = DDR4; + } else if (_val == "LPDDR") { + val = LPDDR; + } else if (_val == "LPDDR2") { + val = LPDDR2; + } else if (_val == "LPDDR3") { + val = LPDDR3; + } else if (_val == "WIDEIO_SDR") { + val = WIDEIO_SDR; + } + assert("Unknown memory type." && val != MEMORY_TYPE_INVALID); + } + + bool isLPDDRFamily() const + { + return val == LPDDR || + val == LPDDR2 || + val == LPDDR3 || + val == WIDEIO_SDR; + } + + bool hasTwoVoltageDomains() const + { + return val == LPDDR || + val == LPDDR2 || + val == LPDDR3 || + val == WIDEIO_SDR || + val == DDR4; + } + + bool isDDRFamily() const + { + return val == DDR2 || + val == DDR3 || + val == DDR4; + } + + bool hasDll() const + { + return val == DDR2 || + val == DDR3 || + val == DDR4; + } + + bool hasTermination() const + { + return val == DDR2 || + val == DDR3 || + val == DDR4; + } + + double getCapacitance() const + { + // LPDDR1/2 memories only have IO Power (no ODT) + // LPDDR3 has optional ODT, but it is typically not used (reflections are elimitated by other means (layout)) + // The capacitance values are conservative and based on Micron Mobile LPDDR2 Power Calculator + + // LPDDR/2/3 IO Capacitance in mF + if (val == LPDDR) { + return 0.0000000045; + } else if (val == LPDDR2) { + return 0.0000000025; + } else if (val == LPDDR3) { + return 0.0000000018; + } else { + return 0.0; + } + } + + double getIoPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 1.5; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 4.6; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 3.7; // in mW + } else { + return 0.0; + } + } + + double getWrOdtPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 8.2; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 21.2; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 17.0; // in mW + } else { + return 0.0; + } + } + + double getTermRdPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 13.1; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 15.5; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 12.4; // in mW + } else { + return 0.0; + } + } + + double getTermWrPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 14.6; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 15.4; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 12.3; // in mW + } else { + return 0.0; + } + } + + operator MemoryType_t() const { + return val; + } + + private: + MemoryType_t val; +}; + +class MemorySpecification : public virtual Parametrisable { + public: + std::string id; + MemoryType memoryType; + + MemArchitectureSpec memArchSpec; + MemTimingSpec memTimingSpec; + MemPowerSpec memPowerSpec; + + void processParameters(); + + static MemorySpecification getMemSpecFromXML(const std::string& id); +}; +} // namespace Data +#endif // ifndef TOOLS_MEMORY_SPECIFICATION_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parameter.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parameter.cc new file mode 100644 index 0000000000..9767e1c94c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parameter.cc @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#include "Parameter.h" + +#include +#include "Utils.h" + +using namespace Data; +using namespace std; + +Parameter::Parameter(const string& id, const string& type, + const string& value) : id(id), type(type), value(value) +{ +} + +string Parameter::getId() const +{ + return id; +} + +string Parameter::getType() const +{ + return type; +} + +int Parameter::getIntValue() const +{ + return fromString(value); +} + +unsigned int Parameter::getUIntValue() const +{ + bool isHex = value.size() > 1 && value[0] == '0' && value[1] == 'x'; + + return fromString(value, isHex ? std::hex : std::dec); +} + +#ifdef _LP64 + +size_t Parameter::getSizeTValue() const +{ + bool isHex = value.size() > 1 && value[0] == '0' && value[1] == 'x'; + + return fromString(value, isHex ? std::hex : std::dec); +} + +#endif + +double Parameter::getDoubleValue() const +{ + return fromString(value); +} + +bool Parameter::getBoolValue() const +{ + return fromString(value); +} + +string Parameter::getValue() const +{ + return value; +} + +Parameter Data::HexParameter(const string& id, int value) +{ + std::ostringstream ss; + + ss << "0x" << hex << setw(8) << setfill('0') << value; + + return Parameter(id, "int", ss.str()); +} + +Parameter Data::StringParameter(const string& id, const string& value) +{ + return Parameter(id, "string", value); +} + +ostream& Data::operator<<(ostream& os, const Parameter& parameter) +{ + os << ""; + + return os; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parameter.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parameter.h new file mode 100644 index 0000000000..2c9623eeb1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parameter.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#ifndef DATA_PARAMETER_H +#define DATA_PARAMETER_H + +#include +#include + +namespace Data { +class Parameter { + public: + Parameter(const std::string& id, const std::string& type, + const std::string& value); + + std::string getId() const; + std::string getType() const; + std::string getValue() const; + + int getIntValue() const; + unsigned int getUIntValue() const; + size_t getSizeTValue() const; + double getDoubleValue() const; + bool getBoolValue() const; + + operator int() const { + return getIntValue(); + } + + operator unsigned int() const { + return getUIntValue(); + } + +#ifdef _LP64 + + operator size_t() const { + return getSizeTValue(); + } +#endif + + operator double() const { + return getDoubleValue(); + } + + operator bool() const { + return getBoolValue(); + } + + operator std::string() const { + return getValue(); + } + + private: + std::string id; + std::string type; + std::string value; +}; + +Parameter HexParameter(const std::string& id, + int value); + +Parameter StringParameter(const std::string& id, + const std::string& value); + +std::ostream& operator<<(std::ostream& os, + const Parameter& parameter); +} +#endif // ifndef DATA_PARAMETER_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parametrisable.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parametrisable.cc new file mode 100644 index 0000000000..a348fd86e1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parametrisable.cc @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#include "Parametrisable.h" + +#include +#include + +using namespace Data; +using namespace std; + +void Parametrisable::pushParameter(const Parameter& parameter) +{ + parameters.push_back(parameter); +} + +void Parametrisable::setParameter(const Parameter& parameter, + unsigned int index) +{ + unsigned int count = 0; + + vector::iterator p = parameters.begin(); + + while (p != parameters.end() && !(p->getId() == parameter.getId() && + index == count)) { + if (p->getId() == parameter.getId()) + ++count; + ++p; + } + + if (p == parameters.end()) { + parameters.push_back(parameter); + } else { + p = parameters.erase(p); + parameters.insert(p, parameter); + } +} // Parametrisable::setParameter + +bool Parametrisable::removeParameter(const string& id, unsigned int index) +{ + unsigned int count = 0; + + for (vector::iterator p = parameters.begin(); + p != parameters.end(); ++p) { + if ((p->getId() == id) && (index == count++)) { + parameters.erase(p); + return true; + } + } + + return false; +} + +/** + * Get a parameter with a specific id. Should there be a multiplicity, + * then the index is used to determine which instance is returned, in + * order traversal. + */ +Parameter Parametrisable::getParameter(const string& id, + unsigned int index) const +{ + unsigned int count = 0; + + for (vector::const_iterator p = parameters.begin(); + p != parameters.end(); ++p) { + if ((p->getId() == id) && (index == count++)) { + return *p; + } + } + + cerr << "Could not find parameter '" << id << "' (" << index << ")" << endl; + cerr << "Stored parameters are: " << endl; + for (vector::const_iterator p = parameters.begin(); + p != parameters.end(); ++p) { + cerr << " " << p->getId() << ": " << p->getValue() << endl; + } + exit(1); + + return Parameter("", "", ""); +} // Parametrisable::getParameter + +vector Parametrisable::getParameters() const +{ + return parameters; +} + +bool Parametrisable::hasParameter(const string& id, unsigned int index) const +{ + unsigned int count = 0; + + for (vector::const_iterator p = parameters.begin(); + p != parameters.end(); ++p) { + if ((p->getId() == id) && (index == count++)) { + return true; + } + } + + return false; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parametrisable.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parametrisable.h new file mode 100644 index 0000000000..31a69190fa --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Parametrisable.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#ifndef DATA_PARAMETRISABLE_H +#define DATA_PARAMETRISABLE_H + +#include +#include + +#include "Parameter.h" + +namespace Data { +/** + * Convenience class for the architectural components that are + * parametrisable. The interface is shared and implemented only in + * this class. + */ +class Parametrisable { + public: + Parametrisable() + { + } + + virtual ~Parametrisable() + { + } + + /** + * Push a new parameter into the in-order vector without checking + * for duplicates. + */ + virtual void pushParameter(const Parameter& parameter); + + /** + * Set a parameter with a given index (default 0). This could for + * example be a queue size for a given channel id. + */ + void setParameter(const Parameter& parameter, + unsigned int index = 0); + + /** + * Get a parameter of a given name and of a certain index. Calling + * this method on an object that has no parameter of that name + * will result in application exit. + */ + Parameter getParameter(const std::string& id, + unsigned int index = 0) const; + + /** + * Remove a parameter with a specific name and index. If a parameter + * is removed this method returns true, otherwise false. + */ + bool removeParameter(const std::string& id, + unsigned int index = 0); + + /** + * Simply get all the parameters. + */ + std::vector getParameters() const; + + /** + * Check if a parameter of a certain name exists in the object. + */ + bool hasParameter(const std::string& id, + unsigned int index = 0) const; + + /** + * Convenience function to set a variable to the value stored in a parameter + * with built in error detection/assertion. Returns true if the value was + * successfully set. + * @param m + * @param paramName + * @param assertOnFail + * @return + */ + template + bool setVarFromParam(T* m, const char* paramName) + { + if (hasParameter(paramName)) { + *m = static_cast(getParameter(paramName)); + return true; + } else { + *m = static_cast(0); + return false; + } + } + + template + T getParamValWithDefault(const char* paramName, T defaultVal) const + { + if (hasParameter(paramName)) { + return static_cast(getParameter(paramName)); + } else { + return defaultVal; + } + } + + protected: + std::vector parameters; +}; +} +#endif // ifndef DATA_PARAMETRISABLE_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/TraceParser.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/TraceParser.cc new file mode 100644 index 0000000000..88f31c21fd --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/TraceParser.cc @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Omar Naji + * + */ +#include "TraceParser.h" + +#include "CommandAnalysis.h" +#include "CmdScheduler.h" + +using namespace Data; +using namespace std; + +TraceParser::TraceParser(const MemorySpecification& memSpec) : + counters(memSpec) +{ +} + + +Data::MemCommand TraceParser::parseLine(std::string line) +{ + MemCommand memcmd(MemCommand::UNINITIALIZED, 0, 0); + istringstream linestream(line); + string item; + int64_t item_val; + unsigned itemnum = 0; + + while (getline(linestream, item, ',')) { + if (itemnum == 0) { + stringstream timestamp(item); + timestamp >> item_val; + memcmd.setTime(item_val); + } else if (itemnum == 1) { + item_val = MemCommand::getTypeFromName(item); + memcmd.setType(static_cast(item_val)); + } else if (itemnum == 2) { + stringstream bank(item); + bank >> item_val; + memcmd.setBank(static_cast(item_val)); + } + itemnum++; + } + return memcmd; +} // TraceParser::parseLine + +void TraceParser::parseFile(MemorySpecification memSpec, std::ifstream& trace, + int window, int grouping, int interleaving, int burst, + int powerdown, int trans) +{ + ifstream pwr_trace; + + counters = CommandAnalysis(memSpec); + int nCommands = 0; + bool lastupdate = false; + if (trans) { + cmdScheduler cmdsched; + cmdsched.transTranslation(memSpec, trace, grouping, interleaving, burst, powerdown); + pwr_trace.open("commands.trace", ifstream::in); + std::string line; + while (getline(pwr_trace, line)) { + MemCommand cmdline = parseLine(line); + cmd_list.push_back(cmdline); + nCommands++; + if (nCommands == window) { + counters.getCommands(cmd_list, lastupdate); + nCommands = 0; + cmd_list.clear(); + } + } + lastupdate = true; + counters.getCommands(cmd_list, lastupdate); + cmd_list.clear(); + pwr_trace.close(); + } else { + std::string line; + while (getline(trace, line)) { + MemCommand cmdline = parseLine(line); + cmd_list.push_back(cmdline); + nCommands++; + if (nCommands == window) { + counters.getCommands(cmd_list, lastupdate); + nCommands = 0; + cmd_list.clear(); + } + } + lastupdate = true; + counters.getCommands(cmd_list, lastupdate); + cmd_list.clear(); + } + counters.clear(); + trace.close(); +} // TraceParser::parseFile diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/TraceParser.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/TraceParser.h new file mode 100644 index 0000000000..3f68ea6ef2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/TraceParser.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Omar Naji + * + */ + +#ifndef TRACE_PARSER_H +#define TRACE_PARSER_H + +#include +#include + +#include "MemCommand.h" +#include "MemorySpecification.h" +#include "CommandAnalysis.h" + + +class TraceParser { + public: + TraceParser(const Data::MemorySpecification& memSpec); + // list of parsed commands + std::vector cmd_list; + + // function for parsing one line of the trace + Data::MemCommand parseLine(std::string line); + + Data::CommandAnalysis counters; + // function for parsing the whole file. + // use this function for small traces ( no out-of-memory issue ) + void parseFile(Data::MemorySpecification memSpec, + std::ifstream& trace, + int window, + int grouping, + int interleaving, + int burst, + int powerdown, + int trans); +}; + +#endif // ifndef TRACE_PARSER_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Utils.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Utils.h new file mode 100644 index 0000000000..7c165a3034 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/Utils.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#ifndef UTILS_H +#define UTILS_H + +#include +#include +#include + + +template +T fromString(const std::string& s, + std::ios_base& (*f)(std::ios_base &) = std::dec) +{ + std::istringstream is(s); + T t; + + if (!(is >> f >> t)) { + throw std::runtime_error("Cannot convert string"); + } + + return t; +} + +#endif /* UTILS_H */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/libdrampower/LibDRAMPower.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/libdrampower/LibDRAMPower.cc new file mode 100644 index 0000000000..65eedacb5d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/libdrampower/LibDRAMPower.cc @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#include "LibDRAMPower.h" + +using namespace Data; + +libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination) : + memSpec(memSpec), + counters(memSpec), + includeIoAndTermination(includeIoAndTermination), + mpm(MemoryPowerModel()) +{ + MemBankWiseParams p (100,100,false,0,false,static_cast(memSpec.memArchSpec.nbrOfBanks)); + libDRAMPower DRAMPower = libDRAMPower(memSpec, 0, p); +} + +libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination, const Data::MemBankWiseParams& bwPowerParams) : + memSpec(memSpec), + counters(CommandAnalysis(memSpec)), + includeIoAndTermination(includeIoAndTermination), + bwPowerParams(bwPowerParams) +{ +} + +libDRAMPower::~libDRAMPower() +{ +} + +void libDRAMPower::doCommand(MemCommand::cmds type, int bank, int64_t timestamp) +{ + MemCommand cmd(type, static_cast(bank), timestamp); + cmdList.push_back(cmd); +} + +void libDRAMPower::updateCounters(bool lastUpdate, int64_t timestamp) +{ + counters.getCommands(cmdList, lastUpdate, timestamp); + cmdList.clear(); +} + +void libDRAMPower::calcEnergy() +{ + updateCounters(true); + mpm.power_calc(memSpec, counters, includeIoAndTermination, bwPowerParams); +} + +void libDRAMPower::calcWindowEnergy(int64_t timestamp) +{ + doCommand(MemCommand::NOP, 0, timestamp); + updateCounters(false, timestamp); + mpm.power_calc(memSpec, counters, includeIoAndTermination, bwPowerParams); + clearCounters(timestamp); +} + + +void libDRAMPower::clearState() +{ + counters.clear(); +} + +void libDRAMPower::clearCounters(int64_t timestamp) +{ + counters.clearStats(timestamp); +} + +const Data::MemoryPowerModel::Energy& libDRAMPower::getEnergy() const +{ + return mpm.energy; +} + +const Data::MemoryPowerModel::Power& libDRAMPower::getPower() const +{ + return mpm.power; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/libdrampower/LibDRAMPower.h b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/libdrampower/LibDRAMPower.h new file mode 100644 index 0000000000..46e14bdd39 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/libdrampower/LibDRAMPower.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#ifndef LIB_DRAM_POWER_H +#define LIB_DRAM_POWER_H + +#include +#include + +#include "CommandAnalysis.h" +#include "MemoryPowerModel.h" +#include "MemCommand.h" +#include "MemBankWiseParams.h" + + +class libDRAMPower { + public: + libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination); + libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination,const Data::MemBankWiseParams& bwPowerParams); + ~libDRAMPower(); + + void doCommand(Data::MemCommand::cmds type, + int bank, + int64_t timestamp); + + void calcEnergy(); + + void calcWindowEnergy(int64_t timestamp); + + const Data::MemoryPowerModel::Energy& getEnergy() const; + const Data::MemoryPowerModel::Power& getPower() const; + + // list of all commands + std::vector cmdList; + private: + void updateCounters(bool lastUpdate, int64_t timestamp = 0); + + void clearCounters(int64_t timestamp); + + void clearState(); + + Data::MemorySpecification memSpec; + public: + Data::CommandAnalysis counters; + private: + bool includeIoAndTermination; + bool bankwiseMode; + Data:: MemBankWiseParams bwPowerParams; + // Object of MemoryPowerModel which contains the results + // Energies(pJ) stored in energy, Powers(mW) stored in power. Number of + // each command stored in timings. + Data::MemoryPowerModel mpm; +}; + +#endif // ifndef LIB_DRAM_POWER_H diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/uncrustify.cfg b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/uncrustify.cfg new file mode 100644 index 0000000000..ffe0e5f9c2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/src/uncrustify.cfg @@ -0,0 +1,280 @@ +tok_split_gte=false +utf8_byte=false +utf8_force=false +indent_cmt_with_tabs=false +indent_align_string=true +indent_braces=false +indent_braces_no_func=false +indent_braces_no_class=false +indent_braces_no_struct=false +indent_brace_parent=false +indent_namespace=false +indent_extern=false +indent_class=true +indent_class_colon=true +indent_else_if=false +indent_var_def_cont=false +indent_func_call_param=false +indent_func_def_param=false +indent_func_proto_param=false +indent_func_class_param=false +indent_func_ctor_var_param=false +indent_template_param=false +indent_func_param_double=false +indent_relative_single_line_comments=false +indent_col1_comment=true +indent_access_spec_body=false +indent_paren_nl=false +indent_comma_paren=false +indent_bool_paren=false +indent_first_bool_expr=false +indent_square_nl=false +indent_preserve_sql=false +indent_align_assign=true +sp_balance_nested_parens=false +align_keep_tabs=false +align_with_tabs=false +align_on_tabstop=false +align_number_left=true +align_func_params=true +align_same_func_call_params=true +align_var_def_colon=true +align_var_def_attribute=true +align_var_def_inline=true +align_right_cmt_mix=false +align_on_operator=true +align_mix_var_proto=false +align_single_line_func=true +align_single_line_brace=true +align_nl_cont=true +align_left_shift=true +align_oc_decl_colon=false +nl_collapse_empty_body=false +nl_assign_leave_one_liners=false +nl_class_leave_one_liners=false +nl_enum_leave_one_liners=false +nl_getset_leave_one_liners=false +nl_func_leave_one_liners=false +nl_if_leave_one_liners=false +nl_multi_line_cond=false +nl_multi_line_define=false +nl_before_case=true +nl_after_case=false +nl_after_return=true +nl_after_semicolon=true +nl_after_brace_open=false +nl_after_brace_open_cmt=false +nl_after_vbrace_open=false +nl_after_vbrace_open_empty=false +nl_after_brace_close=false +nl_after_vbrace_close=false +nl_define_macro=true +nl_squeeze_ifdef=false +nl_ds_struct_enum_cmt=true +nl_ds_struct_enum_close_brace=true +nl_create_if_one_liner=false +nl_create_for_one_liner=false +nl_create_while_one_liner=false +ls_for_split_full=false +ls_func_split_full=false +nl_after_multiline_comment=true +eat_blanks_after_open_brace=true +eat_blanks_before_close_brace=true +mod_full_brace_if_chain=true +mod_pawn_semicolon=false +mod_full_paren_if_bool=true +mod_remove_extra_semicolon=true +mod_sort_import=false +mod_sort_using=false +mod_sort_include=false +mod_move_case_break=true +mod_remove_empty_return=true +cmt_indent_multi=true +cmt_c_group=false +cmt_c_nl_start=false +cmt_c_nl_end=false +cmt_cpp_group=false +cmt_cpp_nl_start=false +cmt_cpp_nl_end=false +cmt_cpp_to_c=false +cmt_star_cont=false +cmt_multi_check_last=true +cmt_insert_before_preproc=false +pp_indent_at_level=false +pp_region_indent_code=false +pp_if_indent_code=false +pp_define_at_level=false +output_tab_size=2 +indent_columns=2 +indent_namespace_level=0 +indent_namespace_limit=0 +indent_access_spec=-1 +align_var_def_span=2 +align_var_def_star_style=0 +align_var_def_amp_style=0 +align_var_def_thresh=2 +align_var_def_gap=1 +align_assign_span=3 +align_assign_thresh=12 +align_enum_equ_span=1 +align_var_struct_span=1 +align_struct_init_span=1 +align_typedef_span=1 +align_typedef_star_style=2 +align_typedef_amp_style=2 +align_right_cmt_span=4 +align_right_cmt_at_col=1 +align_func_proto_span=1 +nl_end_of_file_min=1 +nl_func_var_def_blk=1 +nl_max=2 +nl_after_func_proto=0 +nl_after_func_body=2 +nl_after_func_body_class=2 +nl_after_func_body_one_liner=2 +nl_before_access_spec=2 +nl_after_access_spec=1 +nl_comment_func_def=1 +nl_after_try_catch_finally=1 +mod_full_brace_nl=1 +mod_add_long_function_closebrace_comment=16 +mod_add_long_switch_closebrace_comment=16 +mod_add_long_ifdef_endif_comment=16 +mod_add_long_ifdef_else_comment=16 +newlines=auto +indent_with_tabs=0 +sp_arith=add +sp_assign=add +sp_enum_assign=add +sp_pp_concat=add +sp_pp_stringify=add +sp_bool=add +sp_compare=add +sp_inside_paren=remove +sp_paren_paren=remove +sp_paren_brace=add +sp_before_ptr_star=remove +sp_before_unnamed_ptr_star=remove +sp_between_ptr_star=remove +sp_after_ptr_star=force +sp_after_ptr_star_func=force +sp_before_ptr_star_func=remove +sp_before_byref=remove +sp_before_unnamed_byref=remove +sp_after_byref=add +sp_after_byref_func=add +sp_before_byref_func=remove +sp_after_type=add +sp_before_angle=remove +sp_inside_angle=remove +sp_after_angle=remove +sp_angle_paren=remove +sp_angle_word=force +sp_before_sparen=force +sp_inside_sparen=remove +sp_after_sparen=remove +sp_sparen_brace=add +sp_special_semi=remove +sp_before_semi=remove +sp_before_semi_for=remove +sp_before_semi_for_empty=remove +sp_after_semi_for_empty=remove +sp_before_square=remove +sp_before_squares=remove +sp_inside_square=remove +sp_after_comma=add +sp_before_comma=remove +sp_after_class_colon=add +sp_before_class_colon=add +sp_before_case_colon=remove +sp_after_operator=remove +sp_after_operator_sym=remove +sp_after_cast=remove +sp_inside_paren_cast=remove +sp_cpp_cast_paren=remove +sp_sizeof_paren=remove +sp_inside_braces_enum=add +sp_inside_braces_struct=add +sp_inside_braces=add +sp_inside_braces_empty=remove +sp_type_func=add +sp_func_proto_paren=remove +sp_func_def_paren=remove +sp_inside_fparens=remove +sp_inside_fparen=remove +sp_square_fparen=remove +sp_fparen_brace=add +sp_func_call_paren=remove +sp_func_call_user_paren=remove +sp_func_class_paren=remove +sp_return_paren=add +sp_attribute_paren=remove +sp_defined_paren=remove +sp_throw_paren=remove +sp_macro=add +sp_macro_func=remove +sp_else_brace=add +sp_brace_else=add +sp_brace_typedef=add +sp_catch_brace=add +sp_brace_catch=add +sp_finally_brace=add +sp_brace_finally=add +sp_try_brace=add +sp_getset_brace=add +sp_before_dc=remove +sp_after_dc=remove +sp_not=remove +sp_inv=remove +sp_addr=remove +sp_member=remove +sp_deref=remove +sp_sign=remove +sp_incdec=remove +sp_before_nl_cont=remove +sp_after_oc_scope=remove +sp_after_oc_colon=remove +sp_before_oc_colon=remove +sp_after_send_oc_colon=add +sp_before_send_oc_colon=remove +sp_after_oc_type=remove +sp_cond_colon=add +sp_cond_question=add +sp_cmt_cpp_start=add +nl_start_of_file=remove +nl_end_of_file=force +nl_fcall_brace=force +nl_if_brace=remove +nl_brace_else=remove +nl_elseif_brace=remove +nl_else_brace=remove +nl_else_if=remove +nl_for_brace=remove +nl_while_brace=remove +nl_do_brace=remove +nl_switch_brace=remove +nl_namespace_brace=remove +nl_class_brace=remove +nl_class_init_args=add +nl_func_def_paren=remove +nl_func_decl_start=remove +nl_func_decl_args=add +nl_fdef_brace=force +nl_before_if=ignore +nl_after_if=ignore +nl_before_for=ignore +nl_after_for=ignore +nl_before_while=ignore +nl_after_while=ignore +nl_before_switch=ignore +nl_after_switch=ignore +nl_before_do=ignore +nl_after_do=ignore +mod_full_brace_do=force +mod_full_brace_for=force +mod_full_brace_function=force +mod_full_brace_if=force +mod_full_brace_while=force +mod_full_brace_using=remove +mod_paren_on_return=remove +pp_space=force diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/test/libdrampowertest/commands.trace b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/test/libdrampowertest/commands.trace new file mode 100644 index 0000000000..75e34a21d5 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/test/libdrampowertest/commands.trace @@ -0,0 +1,19 @@ +35,ACT,0 +50,RDA,0 +51,ACT,4 +66,RDA,4 +86,ACT,0 +101,RDA,0 +102,ACT,2 +117,RDA,2 +119,ACT,5 +134,RDA,5 +137,ACT,0 +152,RDA,0 +159,ACT,3 +174,RDA,3 +195,ACT,0 +210,RDA,0 +232,ACT,4 +247,WRA,4 +265,PDN_F_PRE,3 diff --git a/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/test/libdrampowertest/lib_test.cc b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/test/libdrampowertest/lib_test.cc new file mode 100644 index 0000000000..a79839eef8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/lib/drampower/test/libdrampowertest/lib_test.cc @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2014, TU Delft, TU Eindhoven and TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung, Omar Naji, Felipe S. Prado + * + */ + +#include +#include +#include "libdrampower/LibDRAMPower.h" + +#if USE_XERCES +#include "xmlparser/MemSpecParser.h" +#endif + +using namespace std; +using namespace Data; + +int main(int argc, char* argv[]) +{ + assert(argc == 2); + //Setup of DRAMPower for your simulation + string filename; + //type path to memspec file + filename = argv[1]; + //Parsing the Memspec specification of found in memspec folder +#if USE_XERCES + MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(filename)); +#else + MemorySpecification memSpec; +#endif + libDRAMPower test = libDRAMPower(memSpec, 0); + + ios_base::fmtflags flags = cout.flags(); + streamsize precision = cout.precision(); + cout.precision(2); + cout << fixed << endl; + + // During the simulation you can report activity + // to DRAMPower with the doCommand(...) function: + test.doCommand(MemCommand::ACT,0,35); + test.doCommand(MemCommand::RDA,0,50); + test.doCommand(MemCommand::ACT,4,51); + test.doCommand(MemCommand::RDA,4,66); + test.doCommand(MemCommand::ACT,0,86); + test.doCommand(MemCommand::RDA,0,101); + test.doCommand(MemCommand::ACT,2,102); + test.doCommand(MemCommand::RDA,2,117); + test.doCommand(MemCommand::ACT,5,119); + test.doCommand(MemCommand::RDA,5,134); + test.doCommand(MemCommand::ACT,0,137); + test.doCommand(MemCommand::RDA,0,152); + test.doCommand(MemCommand::ACT,3,159); + test.doCommand(MemCommand::RDA,3,174); + test.doCommand(MemCommand::ACT,0,195); + test.doCommand(MemCommand::RDA,0,210); + test.doCommand(MemCommand::ACT,4,232); + test.doCommand(MemCommand::WRA,4,247); + // Need at least tWRAPDEN = AL + CWL + BL/2 + WR + 1 cycles between WR and PDN_F_PRE + test.doCommand(MemCommand::PDN_F_PRE,3,265); + // Exit from Precharge Power-down + test.doCommand(MemCommand::PUP_PRE,3,300); + // Activate bank 0 + test.doCommand(MemCommand::ACT,0,350); + // Precharge all banks with bank 0 active + test.doCommand(MemCommand::PREA,0,400); + // Precharge all banks again + // XXX: For testing purpose only! Double precharge all should never + // happen. Warnings are generated. + test.doCommand(MemCommand::PREA,0,450); + // Activate bank 0 twice + // XXX: For testing purpose only! Double activate should never happen. + // Warnings are generated. + test.doCommand(MemCommand::ACT,0,500); + test.doCommand(MemCommand::ACT,0,550); + // Precharge bank 0 twice + // XXX: For testing purpose only! Double precharge for the same bank + // should never happen. Warnings are generated. + test.doCommand(MemCommand::PRE,0,600); + test.doCommand(MemCommand::PRE,0,650); + + // At the end of your simulation call the getEnergy(...) + // function to print the power report + test.calcEnergy(); + + // Accesing the results: + + // Number of issued Commands + std::cout << "Number of ACTs: " << std::accumulate(test.counters.numberofactsBanks.begin(), + test.counters.numberofactsBanks.end() + ,0)<< endl; + std::cout << "Number of RDs: " << std::accumulate(test.counters.numberofreadsBanks.begin(), + test.counters.numberofreadsBanks.end() + ,0)<< endl; + std::cout << "Number of PREs: " << std::accumulate(test.counters.numberofpresBanks.begin(), + test.counters.numberofpresBanks.end() + ,0)<< endl; + // many other timing parameters in test.mpm.timings + + //ENERGIES per Rank + std::cout << "ACT Cmd Energy: " << test.getEnergy().act_energy << " pJ" << endl; + std::cout << "PRE Cmd Energy: " << test.getEnergy().pre_energy << " pJ" << endl; + std::cout << "RD Cmd Energy: " << test.getEnergy().read_energy << " pJ" << endl; + std::cout << "WR Cmd Energy: " << test.getEnergy().write_energy << " pJ" << endl << endl; + //Standby Energy for 1 rank + //In total energy calculated for both ranks= test.memSpec.memArchSpec * + //test.getEnergy().act_stdby_energy + std::cout << "ACT Stdby Energy: " << test.getEnergy().act_stdby_energy << " pJ" << endl; + //total active standby energy for both ranks + std::cout << "ACT Stdby Energy total ranks: " << static_cast(memSpec.memArchSpec.nbrOfRanks) * + test.getEnergy().act_stdby_energy << " pJ" << endl ; + std::cout << "PRE Stdby Energy: " << test.getEnergy().pre_stdby_energy << " pJ" << endl << endl; + std::cout << "Total Trace Energy: " << test.getEnergy().total_energy << " pJ" << endl; + //many other energies in test.mpm.energy + + //Powers per Rank + std::cout << "Average Power: " << test.getPower().average_power << " mW" << endl; + //many other powers in test.getPower() + + cout.flags(flags); + cout.precision(precision); + + return 0; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/page_mapping_ssd_server.cfg b/SSD-WAF-Analysis-Capstone-2025-main/page_mapping_ssd_server.cfg new file mode 100644 index 0000000000..d9c0e2afdd --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/page_mapping_ssd_server.cfg @@ -0,0 +1,493 @@ +# +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . +# + +# +# Sample SimpleSSD Configuration File +# +# Section: +# cpu: SSD Controller CPU configuration +# nvme: Non-Volatile Memory Express configuration +# ufs: Universal Flash Storage configuration +# sata: Serial ATA configuration +# pal: Parallelism Abstraction Layer configuration +# ftl: Flash Translation Layer configuration +# icl: Internal Cache Layer configuration +# dram: DRAM configuration +# + +# SSD Controller CPU configuration +[cpu] +## Set clock speed in Hz +ClockSpeed = 400000000 + +## Set dedicated core count +HILCoreCount = 1 +ICLCoreCount = 1 +FTLCoreCount = 1 + +# NVMe interface Configuration +[nvme] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NVMe Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## Hardware FIFO Transfer unit +# Smaller value introduce smaller latency +FIFOTransferUnit = 2048 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## Set maximum number of I/O queue that controller supports +# You should check BAR0 size to fit all doorbell +# Doorbell stride is always 0 (4bytes align) +MaxIOCQueue = 16 +MaxIOSQueue = 16 + +## Set parameters of Weighted Round robin +# Set how many commands should be inserted to internal FIFO +# before switch to next low priority +WRRHigh = 2 # Medium-priority command will inserted after two high-priority commands inserted +WRRMedium = 2 # Low-priority command will inserted after two medium-priority command inserted + +## Default Namespace +# Specify number of namespaces to create +# Each namespace has same capacity +DefaultNamespace = 1 + +## LBA Size +# Set logical block size of default namespace +# If DefaultNamespace is false, this value will ignored +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk size check +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 + +## List of disk image path for each namespace +# e.g. Setting disk image for namespace 2 -> DiskImageFile2 = +DiskImageFile1 = nvme.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Universal Flash Storage Configuration +[ufs] + +## AMBA System Bus <-> UFS Host Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 1 +AXIClock = 250000000 # 64bit @ 250MHz -> 2GB/s + +## UFS Host Controller <-> UFS Device +# Set MIPI M-PHY mode and lane count +# Possible values: +# 0: HS-G1 +# 1: HS-G2 +# 2: HS-G3 +# 3: HS-G4 +MPHYMode = 2 +MPHYLane = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = ufs.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Serial ATA Configuration +[sata] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NSATA AHCI HBA +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## SATA AHCI HBA <-> SATA Device +# Set SATA generation +# Possible values: +# 0: SATA 1.0 (1.5Gbps) +# 1: SATA 2.0 (3Gbps) +# 2: SATA 3.0 (6Gbps) +SATAMode = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = sata.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Parallelism Abstraction Layer Configuration +[pal] + +## Set SSD structure +# Channel: # of channels in SSD +# Package: # of packages in one channel +Channel = 4 +Package = 4 + +## Set NAND package structure +# Die: # of die in one package +# Plane: # of plane in one die +# Block: # of block in one plane +# Page: # of page in one block +# PageSize: Size of one page in byte +Die = 2 +Plane = 2 +Block = 512 +Page = 512 +PageSize = 16384 + +## Multi-plane operation +# 1 for enable multi-plane operation +EnableMultiPlaneOperation = 1 + +## Set type of NAND flash +# Possible values: +# 0: Single Level Cell +# 1: Multi Level Cell +# 2: Triple Level Cell +# Please check NAND timing has valid values +# SLC: LSB timing should valid +# MLC: LSB and MSB timing should valid +# TLC: LSB, CSB and MSB timing should valid +NANDType = 1 + +## Set NAND timing +LSBRead = 40000000 +LSBWrite = 500000000 +CSBRead = 0 +CSBWrite = 0 +MSBRead = 65000000 +MSBWrite = 1300000000 +Erase = 3500000000 + +## Set speed and width of DMA in channel in MT/s +# Width should be 8 or 16 +# Typical values from ONFi: +# ONFi 1.x 2.x 3.x~4.x 4.x +# Timing Mode SDR NV-DDR NV-DDR2 NV-DDR3 +# 0 10 40 67 67 +# 1 20 67 80 80 +# 2 29 100 133 133 +# 3 33 133 167 167 +# 4 40 167 200 200 +# 5 50 200 267 267 +# 6 - - 333 333 +# 7 - - 400 400 +# 8 - - 533 533 +# 9 - - - 667 +# 10 - - - 800 +DMASpeed = 400 +DMAWidth = 8 + +## Set superblock/page size +# Superblock/page size will multiplied by each values +# Leave empty will disable superblock feature +# Possible values: +# C: # Channel +# W: # Package/Way +# D: # Die +# P: # Plane (If multi-plane mode is enabled, P will always applied) +SuperblockSize = + +## Set page allocation order +# This order will used when disassembling logical address to physical address +# Possible values: +# C: Channel +# W: Package/Way +# D: Die +# P: Plane +PageAllocation = CWDP + +# Flash Translation Layer Configuration +[ftl] + +## Set mapping method +# Possible values: +# 0: Page level mapping +MappingMode = 0 + +## Set FTL over-provisioning ratio +OverProvisioningRatio = 0.30 + +## Set FTL erase threshold to mark as bad block +EraseThreshold = 100000 + +## Filling options +# Filling Mode +# Possible values: +# 0: Sequential filling + Sequential invalidation +# 1: Sequential filling + Random invalidation +# 2: Random filling + Random invalidation +FillingMode = 0 +# FillRatio +# Fill (warm-up) pages before simulation +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +FillRatio = 0.25 +# InvalidPageRatio +# Create invalid pages by overwrite filled pages +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +InvalidPageRatio = 0.0 + +## Set victim selection algorithm +# Possible values: +# 0: Greedy: Choose least utilized block to clean +# 1: Cost-Benefit: Choose a block that lowest (Utilization / ((1 - Utilization) * Age)) +# 2: Random: Choose random block +# 3: D-CHOICE: Choose least utilized block in randomly sampled blocks +EvictPolicy = 0 + +## DChoice parameter +# When sampling blocks, total blocks to erase * DChoiceParam will be selected +DChoiceParam = 3 + +## Set garbage collection threshold (ratio of free blocks left) +GCThreshold = 0.64 + +## Garbage collection mode +# Possible values: +# 0: Reclaim n blocks +# 1: Reclaim blocks until threshold +GCMode = 0 + +## Specify n (Only in GCMode = 0) +# n > 0 +GCReclaimBlocks = 1 + +## Specify threshold (Only in GCMode = 1) +# t > GCThreshold +GCReclaimThreshold = 0.25 + +## Random I/O tweak +# Enable random I/O tweak when using superpage based mapping +EnableRandomIOTweak = 1 + +# Internal Cache Layer Configuration +[icl] + +## Set Cache size +# Cacheline size = physical page size * (multi-plane mode ? plane count : 1) +# Directed-map cache: Set way as 1 +# Fully-associative cache: Set way value as 0 +CacheSize = 536870912 # 512MiB +CacheWaySize = 8 + +## Set read caching (1 for enable) +EnableReadCache = 1 + +## Set read prefetching (1 for enable) +EnableReadPrefetch = 1 + +## Set prefetch granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +ReadPrefetchMode = 1 + +## Set # of I/O to determine sequential access +# Value < 1 is invalid +# 1 means if 2 contiguous I/O is sequential, prefetch will be enabled +ReadPrefetchCount = 3 + +## Set size of sequential I/O to determine as sequential access +# At least (Super page size * ratio) should be accessed as sequential +# 0 < ratio +ReadPrefetchRatio = 0.25 + +## Set write caching (1 for enable) +EnableWriteCache = 1 + +## Set cache evict policy +# Possible values: +# 0: RANDOM: Evict entry in random fashion +# 1: FIFO: Evict most oldest entry in selected set +# 2: LRU: Evict least recently used entry in selected set +EvictPolicy = 2 + +## Set cache evict granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +EvictMode = 1 + +## Set cache metadata latency +# Byte / ps +CacheLatency = 10 + +# DRAM configuration +[dram] + +## Select DRAM model to use +# Possible values: +# 0: Simple DRAM model based on atomic dram controller of gem5 +Model = 0 + +## DRAM structure parameters +Channel = 1 +Rank = 1 +Bank = 8 +Chip = 1 +BusWidth = 32 +BurstLength = 8 +ChipSize = 1073741824 +PageSize = 4096 + +## DRAM timing parameters (Unit: ps) +# tCK = 1250 +# tRCD = 13750 +# tCL = 13750 +# tRP = 13750 +# tRAS = 35000 +# tWR = 15000 +# tRTP = 7500 +# tBURST +# tCCD_L = +# tRFC = 160000 # 160ns ~ 70200ns +# tREFI = 7800000 +# tWTR = 7500 +# tRTW = +# tCS = +# tRRD = 6000 +# tRRD_L = +# tXAW = +# tXP = 6000 +# tXPDLL = 24000 +# tXS = 170000 # tRFC + 10ns +# tXSDLL = 640000 + +## DRAM power parameters (Unit: mA or V) +# IDD0_0 = 40 +# IDD0_1 = 0 +# IDD2P0_0 = 12 +# IDD2P0_1 = 0 +# IDD2P1_0 = 14 +# IDD2P1_1 = 0 +# IDD2N_0 = 21 +# IDD2N_1 = 0 +# IDD3P0_0 = 21 +# IDD3P0_1 = 0 +# IDD3P1_0 = 21 +# IDD3P1_1 = 0 +# IDD3N_0 = 34 +# IDD3N_1 = 0 +# IDD4R_0 = 100 +# IDD4R_1 = 0 +# IDD4W_0 = 105 +# IDD4W_1 = 0 +# IDD5_0 = 182 +# IDD5_1 = 0 +# IDD6_0 = 12 +# IDD6_1 = 0 +# VDD_0 = 1.35 +# VDD_1 = 0 diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/none/none.cc b/SSD-WAF-Analysis-Capstone-2025-main/sil/none/none.cc new file mode 100644 index 0000000000..5396081eea --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/none/none.cc @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/none/none.hh" + +#include "simplessd/util/algorithm.hh" + +namespace SIL { + +namespace None { + +Driver::Driver(Engine &e, SimpleSSD::ConfigReader &conf) + : BIL::DriverInterface(e), totalLogicalPages(0), logicalPageSize(0) { + pHIL = new SimpleSSD::HIL::HIL(conf); +} + +Driver::~Driver() { + delete pHIL; +} + +void Driver::init(std::function &func) { + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + // No initialization process is needed for NoneDriver + beginFunction = func; + + auto eid = engine.allocateEvent([this](uint64_t) { beginFunction(); }); + engine.scheduleEvent(eid, 0); + + SimpleSSD::info("SIL::None::Driver: Total SSD capacity: %" PRIu64 " bytes", + totalLogicalPages * logicalPageSize); + SimpleSSD::info("SIL::None::Driver: Logical Page Size: %" PRIu32 " bytes", + logicalPageSize); +} + +void Driver::getInfo(uint64_t &bytesize, uint32_t &minbs) { + bytesize = totalLogicalPages * logicalPageSize; + minbs = 512; +} + +void Driver::submitIO(BIL::BIO &bio) { + SimpleSSD::HIL::Request req; + auto *pFunc = new std::function(bio.callback); + + // Convert to request + req.reqID = bio.id; + req.range.slpn = bio.offset / logicalPageSize; + req.range.nlp = DIVCEIL(bio.length, logicalPageSize); + req.offset = bio.offset % logicalPageSize; + req.length = bio.length; + req.context = (void *)bio.id; + req.function = [pFunc](uint64_t, void *context) { + pFunc->operator()((uint64_t)context); + delete pFunc; + }; + + // Submit + switch (bio.type) { + case BIL::BIO_READ: + pHIL->read(req); + break; + case BIL::BIO_WRITE: + pHIL->write(req); + break; + case BIL::BIO_FLUSH: + pHIL->flush(req); + break; + case BIL::BIO_TRIM: + pHIL->trim(req); + break; + default: + break; + } +} + +void Driver::initStats(std::vector &list) { + pHIL->getStatList(list, ""); + SimpleSSD::getCPUStatList(list, "cpu"); +} + +void Driver::getStats(std::vector &values) { + pHIL->getStatValues(values); + SimpleSSD::getCPUStatValues(values); +} + +} // namespace None + +} // namespace SIL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/none/none.hh b/SSD-WAF-Analysis-Capstone-2025-main/sil/none/none.hh new file mode 100644 index 0000000000..e02c6621cf --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/none/none.hh @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NONE__ +#define __DRIVERS_NONE__ + +#include "bil/interface.hh" +#include "simplessd/hil/hil.hh" + +namespace SIL { + +namespace None { + +class Driver : public BIL::DriverInterface { + private: + SimpleSSD::HIL::HIL *pHIL; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + + public: + Driver(Engine &, SimpleSSD::ConfigReader &); + ~Driver(); + + void init(std::function &) override; + void getInfo(uint64_t &, uint32_t &) override; + void submitIO(BIL::BIO &) override; + + void initStats(std::vector &) override; + void getStats(std::vector &) override; +}; + +} // namespace None + +} // namespace SIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/nvme.cc b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/nvme.cc new file mode 100644 index 0000000000..3352bb222c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/nvme.cc @@ -0,0 +1,623 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/nvme/nvme.hh" + +#include "simplessd/hil/nvme/controller.hh" +#include "simplessd/hil/nvme/def.hh" +#include "simplessd/util/algorithm.hh" + +namespace SIL { + +namespace NVMe { + +Driver::Driver(Engine &e, SimpleSSD::ConfigReader &conf) + : BIL::DriverInterface(e), + dmaReadPending(false), + dmaWritePending(false), + phase(true), + adminSQ(nullptr), + adminCQ(nullptr), + ioSQ(nullptr), + ioCQ(nullptr) { + pcieGen = (SimpleSSD::PCIExpress::PCIE_GEN)conf.readInt( + SimpleSSD::CONFIG_NVME, SimpleSSD::HIL::NVMe::NVME_PCIE_GEN); + pcieLane = (uint8_t)conf.readUint(SimpleSSD::CONFIG_NVME, + SimpleSSD::HIL::NVMe::NVME_PCIE_LANE); + + pController = new SimpleSSD::HIL::NVMe::Controller(this, conf); + + dmaReadEvent = engine.allocateEvent([this](uint64_t) { dmaReadDone(); }); + dmaWriteEvent = engine.allocateEvent([this](uint64_t) { dmaWriteDone(); }); +} + +Driver::~Driver() { + delete pController; + delete adminSQ; + delete adminCQ; + delete ioSQ; + delete ioCQ; +} + +void Driver::init(std::function &func) { + beginFunction = func; + + // NVMe Initialization process (Register) + // See Section 7.6.1. Initialization of NVMe 1.3c + union { + uint64_t value; + uint8_t buffer[8]; + } temp; + uint64_t tick = 0; + + // Step 1. Read CAP + pController->readRegister(SimpleSSD::HIL::NVMe::REG_CONTROLLER_CAPABILITY, 8, + temp.buffer, tick); + + // MPSMAX/MIN is setted to 4KB + // DSTRD is setted to 0 (4bytes) + // Check MQES + maxQueueEntries = (temp.value & 0xFFFF) + 1; + + // Step 2. Wait for CSTS.RDY = 0 + // Step 3. Configure admin queue + // Step 3-1. Set admin queue entry size + uint16_t entries = QUEUE_ENTRY_ADMIN; + + if (entries > maxQueueEntries) { + entries = maxQueueEntries; + } + + temp.value = entries - 1; + temp.value |= (entries - 1) << 16; + + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_ADMIN_QUEUE_ATTRIBUTE, 4, + temp.buffer, tick); + + adminSQ = new Queue(entries, 64); + adminCQ = new Queue(entries, 16); + + // Step 3-2. Write base addresses + adminSQ->getBaseAddress(temp.value); + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_ADMIN_SQUEUE_BASE_ADDR, + 8, temp.buffer, tick); + adminCQ->getBaseAddress(temp.value); + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_ADMIN_CQUEUE_BASE_ADDR, + 8, temp.buffer, tick); + + // Step 4. Configure controller + // Step 5. Enable controller + temp.value = 1; // Round Robin, 4K page, NVM command set, Enable + temp.value |= 0x00460000; // 64B SQEntry, 16B CQEntry + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_CONTROLLER_CONFIG, 4, + temp.buffer, tick); + + // Step 6. Wait for CSTS.RDY = 1 + // Step 7. Send Identify + // Step 7-1. Submit Identify Controller + uint32_t cmd[16]; + PRP *prp = new PRP(4096); + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init0(status, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_IDENTIFY; // CID, FUSE, OPC + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + cmd[10] = SimpleSSD::HIL::NVMe::CNS_IDENTIFY_CONTROLLER; // CNS + + submitCommand(0, (uint8_t *)cmd, callback, prp); +} + +void Driver::_init0(uint16_t, void *context) { + PRP *prp = (PRP *)context; + + // Step 7-2. Send Identify Active Namespace List + // Reuse PRP here + uint32_t cmd[16]; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init1(status, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_IDENTIFY; // CID, FUSE, OPC + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + cmd[10] = SimpleSSD::HIL::NVMe::CNS_ACTIVE_NAMESPACE_LIST; // CNS + + submitCommand(0, (uint8_t *)cmd, callback, prp); +} + +void Driver::_init1(uint16_t, void *context) { + PRP *prp = (PRP *)context; + + // Step 7-3. Check active Namespace + // We will perform I/O on first Namespace + uint32_t count = 0; + uint32_t nsid = 0; + + for (count = 0; count < 1024; count++) { + prp->readData(count * 4, 4, (uint8_t *)&nsid); + + if (nsid == 0) { + break; + } + + if (count == 0) { + namespaceID = nsid; + } + } + + if (count == 0) { + SimpleSSD::panic("This NVMe SSD does not have any namespaces."); + } + else if (count > 1) { + SimpleSSD::warn("This NVMe SSD has %u namespaces.", count); + SimpleSSD::warn("All I/O will performed on namespace ID %u.", namespaceID); + } + + // Step 7-4. Send Identify Namespace + // Reuse PRP here + uint32_t cmd[16]; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init2(status, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_IDENTIFY; // CID, FUSE, OPC + cmd[1] = namespaceID; // NSID + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + cmd[10] = SimpleSSD::HIL::NVMe::CNS_IDENTIFY_NAMESPACE; // CNS + + submitCommand(0, (uint8_t *)cmd, callback, prp); +} + +void Driver::_init2(uint16_t, void *context) { + union { + uint64_t value; + uint8_t buffer[8]; + } temp; + PRP *prp = (PRP *)context; + uint8_t nFormat, currentFormat; + uint32_t formatData; + + // Step 7-4. Check structures + prp->readData(0, 8, temp.buffer); + capacity = temp.value; + + prp->readData(25, 1, &nFormat); + nFormat++; + + prp->readData(26, 1, ¤tFormat); + prp->readData(128 + currentFormat * 4ull, 4, (uint8_t *)&formatData); + + LBAsize = (uint32_t)powf(2.f, (float)((formatData >> 16) & 0xFF)); + capacity *= LBAsize; + + delete prp; + + SimpleSSD::info("SIL::NVMe::Driver: Total SSD capacity: %" PRIu64 " bytes", + capacity); + SimpleSSD::info("SIL::NVMe::Driver: Logical Block Size: %" PRIu32 " bytes", + LBAsize); + + // Step 8. Determine I/O queue count + // Step 8-1. Send Set Feature + uint32_t cmd[16]; + ResponseHandler callback = [this](uint16_t status, uint32_t dw0, + void *context) { + _init3(status, dw0, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_SET_FEATURES; // CID, FUSE, OPC + cmd[10] = SimpleSSD::HIL::NVMe::FEATURE_NUMBER_OF_QUEUES; // FID + cmd[11] = 0x00000000; // One I/O SQ, One I/O CQ + + submitCommand(0, (uint8_t *)cmd, callback, nullptr); +} + +void Driver::_init3(uint16_t, uint32_t dw0, void *) { + // Step 8-2. Check response + if (dw0 != 0x00000000) { + SimpleSSD::warn("NVMe SSD responsed too many I/O queue"); + } + + // Step 9. Allocate I/O Completion Queue + // Step 9-1. Send Create I/O Completion Queue + uint32_t cmd[16]; + uint16_t entries = QUEUE_ENTRY_IO; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init4(status, context); + }; + + if (entries > maxQueueEntries) { + entries = maxQueueEntries; + } + + ioCQ = new Queue(entries, 16); + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_CREATE_IO_CQUEUE; // CID, FUSE, OPC + ioCQ->getBaseAddress(*(uint64_t *)(cmd + 6)); // DPTR.PRP1 + cmd[10] = ((uint32_t)(entries - 1) << 16) | 0x0001; // QSIZE, QID + cmd[11] = 0x00010003; // IV, IEN, PC + + submitCommand(0, (uint8_t *)cmd, callback, nullptr); +} + +void Driver::_init4(uint16_t status, void *) { + // Step 9-2. Check result + if (status != 0) { + SimpleSSD::panic("Failed to create I/O Completion Queue"); + } + + // Step 10. Allocate I/O Submission Queue + // Step 10-1. Send Create I/O Submission Queue + uint32_t cmd[16]; + uint16_t entries = QUEUE_ENTRY_IO; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init5(status, context); + }; + + if (entries > maxQueueEntries) { + entries = maxQueueEntries; + } + + ioSQ = new Queue(entries, 64); + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_CREATE_IO_SQUEUE; // CID, FUSE, OPC + ioSQ->getBaseAddress(*(uint64_t *)(cmd + 6)); // DPTR.PRP1 + cmd[10] = ((uint32_t)(entries - 1) << 16) | 0x0001; // QSIZE, QID + cmd[11] = 0x00010001; // CQID, QPRIO, PC + + submitCommand(0, (uint8_t *)cmd, callback, nullptr); +} + +void Driver::_init5(uint16_t status, void *) { + // Step 10-2. Check result + if (status != 0) { + SimpleSSD::panic("Failed to create I/O Submission Queue"); + } + + SimpleSSD::info("SIL::NVMe::Driver: Initialization finished"); + + // Now we initialized NVMe SSD + beginFunction(); +} + +void Driver::submitCommand(uint16_t iv, uint8_t *cmd, ResponseHandler &func, + void *context) { + uint16_t cid = 0; + uint16_t opcode = cmd[0]; + uint16_t tail = 0; + uint64_t tick = engine.getCurrentTick(); + Queue *queue = nullptr; + + // Push to queue + if (iv == 0) { + increaseCommandID(adminCommandID); + cid = adminCommandID; + queue = adminSQ; + } + else if (iv == 1 && ioSQ) { + increaseCommandID(ioCommandID); + cid = ioCommandID; + queue = ioSQ; + } + else { + SimpleSSD::panic("I/O Submission Queue is not initialized"); + } + + memcpy(cmd + 2, &cid, 2); + queue->setData(cmd, 64); + tail = queue->getTail(); + + // Push to pending cmd list + pendingCommandList.push_back(CommandEntry(iv, opcode, cid, context, func)); + + // Ring doorbell + pController->ringSQTailDoorbell(iv, tail, tick); + queue->incrHead(); +} + +void Driver::increaseCommandID(uint16_t &id) { + static const uint16_t maxID = 32767; + + id++; + + if (id > maxID) { + id = 1; + } +} + +void Driver::getInfo(uint64_t &bytesize, uint32_t &minbs) { + bytesize = capacity; + minbs = LBAsize; +} + +void Driver::submitIO(BIL::BIO &bio) { + uint32_t cmd[16]; + PRP *prp = nullptr; + static ResponseHandler callback = [this](uint16_t status, uint32_t, + void *context) { + _io(status, context); + }; + + memset(cmd, 0, 64); + + uint64_t slba = bio.offset / LBAsize; + uint32_t nlb = (uint32_t)DIVCEIL(bio.length, LBAsize); + + cmd[1] = namespaceID; // NSID + + if (bio.type == BIL::BIO_READ) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_READ; // CID, FUSE, OPC + cmd[10] = (uint32_t)slba; + cmd[11] = slba >> 32; + cmd[12] = nlb - 1; // LR, FUA, PRINFO, NLB + + prp = new PRP(bio.length); + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + } + else if (bio.type == BIL::BIO_WRITE) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_WRITE; // CID, FUSE, OPC + cmd[10] = (uint32_t)slba; + cmd[11] = slba >> 32; + cmd[12] = nlb - 1; // LR, FUA, PRINFO, DTYPE, NLB + + prp = new PRP(bio.length); + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + } + else if (bio.type == BIL::BIO_FLUSH) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_FLUSH; // CID, FUSE, OPC + } + else if (bio.type == BIL::BIO_TRIM) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_DATASET_MANAGEMEMT; // CID, FUSE, OPC + cmd[10] = 0; // NR + cmd[11] = 0x04; // AD + + prp = new PRP(16); + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + + // Fill range definition + uint8_t data[16]; + + memset(data, 0, 16); + memcpy(data + 4, &nlb, 4); + memcpy(data + 8, &slba, 8); + + prp->writeData(0, 16, data); + } + + submitCommand(1, (uint8_t *)cmd, callback, + new IOWrapper(bio.id, prp, bio.callback)); +} + +void Driver::_io(uint16_t status, void *context) { + IOWrapper *wrapper = (IOWrapper *)context; + PRP *prp = wrapper->prp; + + if (status != 0) { + SimpleSSD::warn("I/O error: %04X", status); + } + + wrapper->bioCallback(wrapper->id); + + delete prp; + delete wrapper; +} + +void Driver::initStats(std::vector &list) { + pController->getStatList(list, ""); + SimpleSSD::getCPUStatList(list, "cpu"); +} + +void Driver::getStats(std::vector &values) { + pController->getStatValues(values); + SimpleSSD::getCPUStatValues(values); +} + +void Driver::dmaRead(uint64_t addr, uint64_t size, uint8_t *buffer, + SimpleSSD::DMAFunction &func, void *context) { + if (size == 0) { + SimpleSSD::warn("nvme_interface: zero-size DMA read request. Ignore."); + + return; + } + + dmaReadQueue.push(DMAEntry(func)); + + auto &iter = dmaReadQueue.back(); + iter.addr = addr; + iter.size = size; + iter.buffer = buffer; + iter.context = context; + + if (!dmaReadPending) { + submitDMARead(); + } +} + +void Driver::dmaReadDone() { + auto &iter = dmaReadQueue.front(); + uint64_t tick = engine.getCurrentTick(); + + if (tick < iter.finishedAt) { + engine.scheduleEvent(dmaReadEvent, iter.finishedAt); + + return; + } + + iter.func(tick, iter.context); + dmaReadQueue.pop(); + dmaReadPending = false; + + if (dmaReadQueue.size() > 0) { + submitDMARead(); + } +} + +void Driver::submitDMARead() { + auto &iter = dmaReadQueue.front(); + + dmaReadPending = true; + + iter.beginAt = engine.getCurrentTick(); + iter.finishedAt = iter.beginAt + SimpleSSD::PCIExpress::calculateDelay( + pcieGen, pcieLane, iter.size); + + if (iter.buffer) { + memcpy(iter.buffer, (uint8_t *)iter.addr, iter.size); + } + + engine.scheduleEvent(dmaReadEvent, iter.finishedAt); +} + +void Driver::dmaWrite(uint64_t addr, uint64_t size, uint8_t *buffer, + SimpleSSD::DMAFunction &func, void *context) { + if (size == 0) { + SimpleSSD::warn("nvme_interface: zero-size DMA write request. Ignore."); + + return; + } + + dmaWriteQueue.push(DMAEntry(func)); + + auto &iter = dmaWriteQueue.back(); + iter.addr = addr; + iter.size = size; + iter.buffer = buffer; + iter.context = context; + + if (!dmaWritePending) { + submitDMAWrite(); + } +} + +void Driver::dmaWriteDone() { + auto &iter = dmaWriteQueue.front(); + uint64_t tick = engine.getCurrentTick(); + + if (tick < iter.finishedAt) { + engine.scheduleEvent(dmaWriteEvent, iter.finishedAt); + + return; + } + + iter.func(tick, iter.context); + dmaWriteQueue.pop(); + dmaWritePending = false; + + if (dmaWriteQueue.size() > 0) { + submitDMAWrite(); + } +} + +void Driver::submitDMAWrite() { + auto &iter = dmaWriteQueue.front(); + + dmaWritePending = true; + + iter.beginAt = engine.getCurrentTick(); + iter.finishedAt = iter.beginAt + SimpleSSD::PCIExpress::calculateDelay( + pcieGen, pcieLane, iter.size); + + if (iter.buffer) { + memcpy((uint8_t *)iter.addr, iter.buffer, iter.size); + } + + engine.scheduleEvent(dmaWriteEvent, iter.finishedAt); +} + +void Driver::updateInterrupt(uint16_t iv, bool post) { + uint32_t cqdata[4]; + + if (post) { + uint64_t tick = engine.getCurrentTick(); + uint16_t count = 0; + Queue *queue = nullptr; + + if (iv == 0) { + queue = adminCQ; + } + else if (iv == 1 && ioCQ) { + queue = ioCQ; + } + else { + SimpleSSD::panic("I/O Completion Queue is not initialized"); + } + + // Peek queue for count how many requests are finished + while (true) { + queue->peekData((uint8_t *)cqdata, 16); + + // Check phase tag + if (((cqdata[3] >> 16) & 0x01) == phase) { + bool found = false; + + queue->incrTail(); + count++; + + // Search pending command list + for (auto iter = pendingCommandList.begin(); + iter != pendingCommandList.end(); iter++) { + if (iter->iv == iv && iter->cid == (cqdata[3] & 0xFFFF)) { + iter->callback((uint16_t)(cqdata[3] >> 17), cqdata[0], + iter->context); + + pendingCommandList.erase(iter); + found = true; + + break; + } + } + + if (found) { + queue->incrHead(); + + if (queue->getHead() == 0) { + // Inverted + phase = !phase; + } + } + else { + SimpleSSD::panic("Invalid interrupt"); + } + } + else { + if (count > 0) { + pController->ringCQHeadDoorbell(iv, queue->getHead(), tick); + } + + break; + } + } + } +} + +void Driver::getVendorID(uint16_t &vid, uint16_t &ssvid) { + // Copied from SimpleSSD-FullSystem + vid = 0x144D; + ssvid = 0x8086; +} + +} // namespace NVMe + +} // namespace SIL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/nvme.hh b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/nvme.hh new file mode 100644 index 0000000000..4b8189156e --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/nvme.hh @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NVME__ +#define __DRIVERS_NVME__ + +#include +#include + +#include "bil/interface.hh" +#include "sil/nvme/prp.hh" +#include "sil/nvme/queue.hh" +#include "simplessd/hil/nvme/interface.hh" +#include "simplessd/util/interface.hh" + +#define QUEUE_ENTRY_ADMIN 256 +#define QUEUE_ENTRY_IO 1024 + +namespace SIL { + +namespace NVMe { + +// Copied from SimpleSSD-FullSystem +typedef struct _DMAEntry { + uint64_t beginAt; + uint64_t finishedAt; + uint64_t addr; + uint64_t size; + uint8_t *buffer; + void *context; + SimpleSSD::DMAFunction func; + + _DMAEntry(SimpleSSD::DMAFunction &f) + : beginAt(0), + finishedAt(0), + addr(0), + size(0), + buffer(nullptr), + context(nullptr), + func(f) {} +} DMAEntry; + +typedef std::function ResponseHandler; + +typedef struct _CommandEntry { + uint16_t iv; // Same as Queue ID + uint16_t opcode; + uint16_t cid; + void *context; + + ResponseHandler callback; + + _CommandEntry(uint16_t i, uint16_t o, uint16_t c, void *p, ResponseHandler &f) + : iv(i), opcode(o), cid(c), context(p), callback(f) {} +} CommandEntry; + +typedef struct _IOWrapper { + uint64_t id; + PRP *prp; + std::function bioCallback; + + _IOWrapper(uint64_t i, PRP *p, std::function &f) + : id(i), prp(p), bioCallback(f) {} +} IOWrapper; + +class Driver : public BIL::DriverInterface, SimpleSSD::HIL::NVMe::Interface { + private: + // PCI Express (for DMA throttling) + SimpleSSD::PCIExpress::PCIE_GEN pcieGen; + uint8_t pcieLane; + + // DMA scheduling + SimpleSSD::Event dmaReadEvent; + SimpleSSD::Event dmaWriteEvent; + std::queue dmaReadQueue; + std::queue dmaWriteQueue; + bool dmaReadPending; + bool dmaWritePending; + + // NVMe Identify + uint64_t capacity; + uint32_t LBAsize; + uint32_t namespaceID; + + // Queue + uint16_t maxQueueEntries; + uint16_t adminCommandID; + uint16_t ioCommandID; + bool phase; + Queue *adminSQ; + Queue *adminCQ; + Queue *ioSQ; + Queue *ioCQ; + std::list pendingCommandList; + + void dmaReadDone(); + void submitDMARead(); + void dmaWriteDone(); + void submitDMAWrite(); + + void increaseCommandID(uint16_t &); + + void _init0(uint16_t, void *); + void _init1(uint16_t, void *); + void _init2(uint16_t, void *); + void _init3(uint16_t, uint32_t, void *); + void _init4(uint16_t, void *); + void _init5(uint16_t, void *); + + void _io(uint16_t, void *); + + void submitCommand(uint16_t, uint8_t *, ResponseHandler &, void *); + + public: + Driver(Engine &, SimpleSSD::ConfigReader &); + ~Driver(); + + // BIL::DriverInterface + void init(std::function &) override; + void getInfo(uint64_t &, uint32_t &) override; + void submitIO(BIL::BIO &) override; + + void initStats(std::vector &) override; + void getStats(std::vector &) override; + + // SimpleSSD::DMAInterface + void dmaRead(uint64_t, uint64_t, uint8_t *, SimpleSSD::DMAFunction &, + void * = nullptr) override; + void dmaWrite(uint64_t, uint64_t, uint8_t *, SimpleSSD::DMAFunction &, + void * = nullptr) override; + + // SimpleSSD::HIL::NVMe::Interface + void updateInterrupt(uint16_t, bool) override; + void getVendorID(uint16_t &, uint16_t &) override; +}; + +} // namespace NVMe + +} // namespace SIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/prp.cc b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/prp.cc new file mode 100644 index 0000000000..317ea8e3b4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/prp.cc @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/nvme/prp.hh" + +#include +#include + +#include "simplessd/sim/trace.hh" +#include "simplessd/util/algorithm.hh" + +namespace SIL { + +namespace NVMe { + +PRP::PRP(uint64_t size) : memory(nullptr), capacity(0), ptr1(0), ptr2(0) { + uint8_t mode = 0; + uint32_t listCount = 1; + uint32_t lastEntryCount = 0; + const uint32_t maxEntryCount = PAGE_SIZE / 8; + + // Calculate size to allocate + if (size <= PAGE_SIZE) { + // PRP1 is PRP pointer, PRP2 is not used + capacity = PAGE_SIZE; + mode = 1; + } + else if (size <= PAGE_SIZE * 2) { + // Both are PRP pointer + capacity = PAGE_SIZE * 2; + mode = 2; + } + else { + // We need to create PRPList + // PRP1 is PRP pointer (always) + mode = 3; + size -= PAGE_SIZE; + capacity = PAGE_SIZE * 2; + + while (true) { + if (size > PAGE_SIZE * maxEntryCount) { + listCount++; + + // Last entry is pointing next PRP list + size -= PAGE_SIZE * (maxEntryCount - 1); + capacity += PAGE_SIZE * maxEntryCount; + } + else { + lastEntryCount = (uint32_t)DIVCEIL(size, PAGE_SIZE); + capacity += PAGE_SIZE * lastEntryCount; + + break; + } + } + } + +#ifdef _MSC_VER + memory = (uint8_t *)_aligned_malloc(capacity, PAGE_SIZE); +#else + memory = (uint8_t *)aligned_alloc(PAGE_SIZE, capacity); +#endif + + if (memory == nullptr) { + SimpleSSD::panic("Failed to allocate memory for PRP region"); + } + + memset(memory, 0, capacity); + + if (mode == 1) { + ptr1 = (uint64_t)memory; + ptrList.push_back(ptr1); + } + else { + ptr1 = (uint64_t)memory; + ptr2 = (uint64_t)(memory + PAGE_SIZE); + ptrList.push_back(ptr1); + ptrList.push_back(ptr2); + + if (mode == 3) { + uint64_t *listPtr = (uint64_t *)ptr2; + uint8_t *page = memory + PAGE_SIZE * 2; + uint32_t entry = 0; + + while (true) { + *(listPtr + entry++) = (uint64_t)page; + ptrList.push_back((uint64_t)page); + page += PAGE_SIZE; + + if (listCount == 1 && entry == lastEntryCount) { + *(listPtr + entry) = 0; + + break; + } + else if (listCount > 1 && entry == maxEntryCount - 1) { + *(listPtr + entry) = (uint64_t)page; + listPtr = (uint64_t *)page; + page += PAGE_SIZE; + listCount--; + entry = 0; + } + } + } + } +} + +PRP::~PRP() { +#ifdef _MSC_VER + _aligned_free(memory); +#else + free(memory); +#endif +} + +void PRP::getPointer(uint64_t &prp1, uint64_t &prp2) { + prp1 = ptr1; + prp2 = ptr2; +} + +void PRP::readData(uint64_t offset, uint64_t size, uint8_t *buffer) { + uint64_t begin = offset / PAGE_SIZE; + uint64_t end = DIVCEIL(offset + size, PAGE_SIZE); + uint64_t copied = 0; + + for (uint64_t i = begin; i < end; i++) { + uint64_t ptr = ptrList[i] + (offset - i * PAGE_SIZE); + uint64_t len = MIN((i + 1) * PAGE_SIZE - offset, size - copied); + + memcpy(buffer, (uint8_t *)ptr, len); + + copied += len; + } +} + +void PRP::writeData(uint64_t offset, uint64_t size, uint8_t *buffer) { + uint64_t begin = offset / PAGE_SIZE; + uint64_t end = DIVCEIL(offset + size, PAGE_SIZE); + uint64_t copied = 0; + + for (uint64_t i = begin; i < end; i++) { + uint64_t ptr = ptrList[i] + (offset - i * PAGE_SIZE); + uint64_t len = MIN((i + 1) * PAGE_SIZE - offset, size - copied); + + memcpy((uint8_t *)ptr, buffer, len); + + copied += len; + } +} + +} // namespace NVMe + +} // namespace SIL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/prp.hh b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/prp.hh new file mode 100644 index 0000000000..ed117e9752 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/prp.hh @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NVME_PRP__ +#define __DRIVERS_NVME_PRP__ + +#include +#include + +#define PAGE_SIZE 4096 + +namespace SIL { + +namespace NVMe { + +class PRP { + private: + uint8_t *memory; + uint64_t capacity; + + uint64_t ptr1; + uint64_t ptr2; + + std::vector ptrList; // For faster access + + public: + PRP(uint64_t); + ~PRP(); + + void getPointer(uint64_t &, uint64_t &); + void readData(uint64_t, uint64_t, uint8_t *); + void writeData(uint64_t, uint64_t, uint8_t *); +}; + +} // namespace NVMe + +} // namespace SIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/queue.cc b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/queue.cc new file mode 100644 index 0000000000..9ac3f6e75c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/queue.cc @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/nvme/queue.hh" + +#include +#include + +#include "sil/nvme/prp.hh" +#include "simplessd/sim/trace.hh" + +namespace SIL { + +namespace NVMe { + +Queue::Queue(uint16_t e, uint16_t s) + : memory(nullptr), stride(s), entries(e), head(0), tail(0) { + capacity = stride * entries; + +#ifdef _MSC_VER + memory = (uint8_t *)_aligned_malloc(capacity, PAGE_SIZE); +#else + memory = (uint8_t *)aligned_alloc(PAGE_SIZE, capacity); +#endif + + if (memory == nullptr) { + SimpleSSD::panic("Failed to allocate memory for PRP region"); + } + + memset(memory, 0, capacity); +} + +Queue::~Queue() { +#ifdef _MSC_VER + _aligned_free(memory); +#else + free(memory); +#endif +} + +void Queue::getBaseAddress(uint64_t &ptr) { + ptr = (uint64_t)memory; +} + +void Queue::peekData(uint8_t *buffer, uint16_t length) { + memcpy(buffer, memory + head * stride, length); +} + +void Queue::getData(uint8_t *buffer, uint16_t length) { + peekData(buffer, length); + + incrHead(); +} + +void Queue::setData(uint8_t *buffer, uint16_t length) { + memcpy(memory + tail * stride, buffer, length); + + incrTail(); +} + +uint16_t Queue::getHead() { + return head; +} + +uint16_t Queue::getTail() { + return tail; +} + +void Queue::incrHead() { + head++; + + if (head == entries) { + head = 0; + } +} + +void Queue::incrTail() { + tail++; + + if (tail == entries) { + tail = 0; + } +} + +} // namespace NVMe + +} // namespace SIL diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/queue.hh b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/queue.hh new file mode 100644 index 0000000000..65019b7ecd --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sil/nvme/queue.hh @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NVME_QUEUE__ +#define __DRIVERS_NVME_QUEUE__ + +#include + +namespace SIL { + +namespace NVMe { + +class Queue { + private: + uint8_t *memory; + uint64_t capacity; + + uint16_t stride; + uint16_t entries; + uint16_t head; + uint16_t tail; + + public: + Queue(uint16_t, uint16_t); + ~Queue(); + + void getBaseAddress(uint64_t &); + void getData(uint8_t *, uint16_t); // Increase head + void setData(uint8_t *, uint16_t); // Increase tail + uint16_t getHead(); + uint16_t getTail(); + void incrHead(); + void incrTail(); + void peekData(uint8_t *, uint16_t); // Get data without increasing head +}; + +} // namespace NVMe + +} // namespace SIL + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/cfg_reader.cc b/SSD-WAF-Analysis-Capstone-2025-main/sim/cfg_reader.cc new file mode 100644 index 0000000000..fb5989edfc --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/cfg_reader.cc @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/cfg_reader.hh" + +#include "simplessd/sim/base_config.hh" +#include "simplessd/sim/trace.hh" + +#ifdef _MSC_VER +#define strcasecmp _stricmp +#else +#include +#endif + +const char SECTION_GLOBAL[] = "global"; +const char SECTION_TRACE[] = "trace"; +const char SECTION_REQ_GEN[] = "generator"; + +bool ConfigReader::init(std::string file) { + if (ini_parse(file.c_str(), parserHandler, this) < 0) { + return false; + } + + // Update all + globalConfig.update(); + traceConfig.update(); + requestConfig.update(); + + return true; +} + +int64_t ConfigReader::readInt(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readInt(idx); + case CONFIG_TRACE: + return traceConfig.readInt(idx); + case CONFIG_REQ_GEN: + return requestConfig.readInt(idx); + default: + return 0; + } +} + +uint64_t ConfigReader::readUint(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readUint(idx); + case CONFIG_TRACE: + return traceConfig.readUint(idx); + case CONFIG_REQ_GEN: + return requestConfig.readUint(idx); + default: + return 0; + } +} + +float ConfigReader::readFloat(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readFloat(idx); + case CONFIG_TRACE: + return traceConfig.readFloat(idx); + case CONFIG_REQ_GEN: + return requestConfig.readFloat(idx); + default: + return 0.f; + } +} + +std::string ConfigReader::readString(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readString(idx); + case CONFIG_TRACE: + return traceConfig.readString(idx); + case CONFIG_REQ_GEN: + return requestConfig.readString(idx); + default: + return std::string(); + } +} + +bool ConfigReader::readBoolean(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readBoolean(idx); + case CONFIG_TRACE: + return traceConfig.readBoolean(idx); + case CONFIG_REQ_GEN: + return requestConfig.readBoolean(idx); + default: + return false; + } +} + +int ConfigReader::parserHandler(void *context, const char *section, + const char *name, const char *value) { + ConfigReader *pThis = (ConfigReader *)context; + bool handled = false; + + if (MATCH_SECTION(SECTION_GLOBAL)) { + handled = pThis->globalConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_TRACE)) { + handled = pThis->traceConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_REQ_GEN)) { + handled = pThis->requestConfig.setConfig(name, value); + } + + if (!handled) { + SimpleSSD::warn("Config [%s] %s = %s not handled", section, name, value); + } + + return 1; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/cfg_reader.hh b/SSD-WAF-Analysis-Capstone-2025-main/sim/cfg_reader.hh new file mode 100644 index 0000000000..800da9d6a1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/cfg_reader.hh @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_CONFIG_READER_2__ +#define __SIM_CONFIG_READER_2__ + +#include +#include + +#include "igl/request/request_config.hh" +#include "igl/trace/trace_config.hh" +#include "sim/global_config.hh" +#include "simplessd/lib/inih/ini.h" + +typedef enum { + CONFIG_GLOBAL, + CONFIG_TRACE, + CONFIG_REQ_GEN, +} CONFIG_SECTION; + +class ConfigReader { + private: + Config globalConfig; + IGL::TraceConfig traceConfig; + IGL::RequestConfig requestConfig; + + static int parserHandler(void *, const char *, const char *, const char *); + + public: + bool init(std::string); + + int64_t readInt(CONFIG_SECTION, uint32_t); + uint64_t readUint(CONFIG_SECTION, uint32_t); + float readFloat(CONFIG_SECTION, uint32_t); + std::string readString(CONFIG_SECTION, uint32_t); + bool readBoolean(CONFIG_SECTION, uint32_t); +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/engine.cc b/SSD-WAF-Analysis-Capstone-2025-main/sim/engine.cc new file mode 100644 index 0000000000..81eeb1b6bb --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/engine.cc @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/engine.hh" + +#include "simplessd/sim/trace.hh" + +Engine::Engine() + : SimpleSSD::Simulator(), + simTick(0), + counter(0), + forceStop(false), + eventHandled(0) { + watch.start(); +} + +Engine::~Engine() {} + +bool Engine::insertEvent(SimpleSSD::Event eid, uint64_t tick, + uint64_t *pOldTick) { + bool found = false; + bool flag = false; + auto old = eventQueue.begin(); + auto insert = eventQueue.end(); + + for (auto iter = eventQueue.begin(); iter != eventQueue.end(); iter++) { + if (iter->first == eid) { + found = true; + old = iter; + + if (pOldTick) { + *pOldTick = iter->second; + } + } + + if (iter->second > tick && !flag) { + insert = iter; + flag = true; + } + } + + if (found && pOldTick) { + if (*pOldTick == tick) { + // Rescheduling to same tick. Ignore. + return false; + } + } + + // Iterator will not invalidated on insert + // Do insert first + eventQueue.insert(insert, {eid, tick}); + + if (found) { + eventQueue.erase(old); + } + + return found; +} + +bool Engine::removeEvent(SimpleSSD::Event eid) { + bool found = false; + + for (auto iter = eventQueue.begin(); iter != eventQueue.end(); iter++) { + if (iter->first == eid) { + eventQueue.erase(iter); + found = true; + + break; + } + } + + return found; +} + +bool Engine::isEventExist(SimpleSSD::Event eid, uint64_t *pTick) { + for (auto &iter : eventQueue) { + if (iter.first == eid) { + if (pTick) { + *pTick = iter.second; + } + + return true; + } + } + + return false; +} + +uint64_t Engine::getCurrentTick() { + std::lock_guard guard(mTick); + + return simTick; +} + +SimpleSSD::Event Engine::allocateEvent(SimpleSSD::EventFunction func) { + auto iter = eventList.insert({++counter, func}); + + if (!iter.second) { + SimpleSSD::panic("Fail to allocate event"); + } + + return counter; +} + +void Engine::scheduleEvent(SimpleSSD::Event eid, uint64_t tick) { + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + uint64_t tickCopy; + + { + std::lock_guard guard(mTick); + tickCopy = simTick; + } + + if (tick < tickCopy) { + SimpleSSD::warn("Tried to schedule %" PRIu64 + " < simTick to event %" PRIu64 ". Set tick as simTick.", + tick, eid); + + tick = tickCopy; + } + + uint64_t oldTick; + + if (insertEvent(eid, tick, &oldTick)) { + SimpleSSD::warn("Event %" PRIu64 " rescheduled from %" PRIu64 + " to %" PRIu64, + eid, oldTick, tick); + } + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } +} + +void Engine::descheduleEvent(SimpleSSD::Event eid) { + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + removeEvent(eid); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } +} + +bool Engine::isScheduled(SimpleSSD::Event eid, uint64_t *pTick) { + bool ret = false; + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + ret = isEventExist(eid, pTick); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } + + return ret; +} + +void Engine::deallocateEvent(SimpleSSD::Event eid) { + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + removeEvent(eid); + eventList.erase(iter); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } +} + +bool Engine::doNextEvent() { + uint64_t tickCopy; + + if (forceStop) { + return false; + } + + if (eventQueue.size() > 0) { + auto &now = eventQueue.front(); + + { + std::lock_guard guard(mTick); + + simTick = now.second; + tickCopy = simTick; + } + + auto iter = eventList.find(now.first); + + eventQueue.pop_front(); + + if (iter != eventList.end()) { + iter->second(tickCopy); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", now.first); + } + + { + std::lock_guard guard(m); + eventHandled++; + } + + return true; + } + + return false; +} + +void Engine::stopEngine() { + forceStop = true; +} + +void Engine::printStats(std::ostream &out) { + watch.stop(); + + double duration = watch.getDuration(); + + out << "*** Statistics of Event Engine ***" << std::endl; + { + std::lock_guard guard(mTick); + + out << "Simulation Tick (ps): " << simTick << std::endl; + } + out << "Host time duration (sec): " << std::to_string(duration) << std::endl; + out << "Event handled: " << eventHandled << " (" + << std::to_string(eventHandled / duration) << " ops)" << std::endl; + out << "*** End of statistics ***" << std::endl; +} + +void Engine::getStat(uint64_t &val) { + std::lock_guard guard(m); + val = eventHandled; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/engine.hh b/SSD-WAF-Analysis-Capstone-2025-main/sim/engine.hh new file mode 100644 index 0000000000..2b292f962d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/engine.hh @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_ENGINE__ +#define __SIM_ENGINE__ + +#include +#include +#include +#include +#include + +#include "simplessd/sim/simulator.hh" +#include "util/stopwatch.hh" + +class Engine : public SimpleSSD::Simulator { + private: + std::mutex mTick; + uint64_t simTick; + SimpleSSD::Event counter; + bool forceStop; + std::unordered_map eventList; + std::list> eventQueue; + + Stopwatch watch; + + std::mutex m; + uint64_t eventHandled; + + bool insertEvent(SimpleSSD::Event, uint64_t, uint64_t * = nullptr); + bool removeEvent(SimpleSSD::Event); + bool isEventExist(SimpleSSD::Event, uint64_t * = nullptr); + + public: + Engine(); + ~Engine(); + + uint64_t getCurrentTick() override; + + SimpleSSD::Event allocateEvent(SimpleSSD::EventFunction) override; + void scheduleEvent(SimpleSSD::Event, uint64_t) override; + void descheduleEvent(SimpleSSD::Event) override; + bool isScheduled(SimpleSSD::Event, uint64_t * = nullptr) override; + void deallocateEvent(SimpleSSD::Event) override; + + bool doNextEvent(); + void stopEngine(); + void printStats(std::ostream &); + void getStat(uint64_t &); +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/global_config.cc b/SSD-WAF-Analysis-Capstone-2025-main/sim/global_config.cc new file mode 100644 index 0000000000..af3ac5143b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/global_config.cc @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/global_config.hh" + +#include "simplessd/sim/trace.hh" +#include "util/convert.hh" + +const char NAME_MODE[] = "Mode"; +const char NAME_LOG_PERIOD[] = "LogPeriod"; +const char NAME_LOG_FILE[] = "LogFile"; +const char NAME_DEBUG_LOG_FILE[] = "DebugLogFile"; +const char NAME_LATENCY_LOG_FILE[] = "LatencyLogFile"; +const char NAME_PROGRESS_PERIOD[] = "ProgressPeriod"; +const char NAME_INTERFACE[] = "Interface"; +const char NAME_SCHEDULER[] = "Scheduler"; +const char NAME_SUBMISSION_LATENCY[] = "SubmissionLatency"; +const char NAME_COMPLETION_LATENCY[] = "CompletionLatency"; + +Config::Config() { + mode = MODE_REQUEST_GENERATOR; + logPeriod = 0; + progressPeriod = 0; + interface = INTERFACE_NVME; + scheduler = SCHEDULER_NOOP; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_MODE)) { + mode = (SIM_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LOG_PERIOD)) { + logPeriod = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LOG_FILE)) { + logFile = value; + } + else if (MATCH_NAME(NAME_DEBUG_LOG_FILE)) { + logDebugFile = value; + } + else if (MATCH_NAME(NAME_LATENCY_LOG_FILE)) { + latencyFile = value; + } + else if (MATCH_NAME(NAME_PROGRESS_PERIOD)) { + progressPeriod = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_INTERFACE)) { + interface = (INTERFACE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SCHEDULER)) { + scheduler = (SCHEDULER)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SUBMISSION_LATENCY)) { + submissionLatency = convertTime(value); + } + else if (MATCH_NAME(NAME_COMPLETION_LATENCY)) { + completionLatency = convertTime(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (mode >= MODE_NUM) { + SimpleSSD::panic("Invalid simulation mode"); + } + if (interface >= INTERFACE_NUM) { + SimpleSSD::panic("Invalid interface"); + } +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case GLOBAL_SIM_MODE: + ret = mode; + break; + case GLOBAL_LOG_PERIOD: + ret = logPeriod; + break; + case GLOBAL_PROGRESS_PERIOD: + ret = progressPeriod; + break; + case GLOBAL_INTERFACE: + ret = interface; + break; + case GLOBAL_SCHEDULER: + ret = scheduler; + break; + case GLOBAL_SUBMISSION_LATENCY: + ret = submissionLatency; + break; + case GLOBAL_COMPLETION_LATENCY: + ret = completionLatency; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret = ""; + + switch (idx) { + case GLOBAL_LOG_FILE: + ret = logFile; + break; + case GLOBAL_DEBUG_LOG_FILE: + ret = logDebugFile; + break; + case GLOBAL_LATENCY_LOG_FILE: + ret = latencyFile; + break; + } + + return ret; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/global_config.hh b/SSD-WAF-Analysis-Capstone-2025-main/sim/global_config.hh new file mode 100644 index 0000000000..8ed433cab6 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/global_config.hh @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_GLOBAL_CONFIG__ +#define __SIM_GLOBAL_CONFIG__ + +#include "simplessd/sim/base_config.hh" + +typedef enum { + GLOBAL_SIM_MODE, + GLOBAL_LOG_PERIOD, + GLOBAL_LOG_FILE, + GLOBAL_DEBUG_LOG_FILE, + GLOBAL_LATENCY_LOG_FILE, + GLOBAL_PROGRESS_PERIOD, + GLOBAL_INTERFACE, + GLOBAL_SCHEDULER, + GLOBAL_SUBMISSION_LATENCY, + GLOBAL_COMPLETION_LATENCY, +} GLOBAL_CONFIG; + +typedef enum { + MODE_REQUEST_GENERATOR, + MODE_TRACE_REPLAYER, + MODE_NUM, +} SIM_MODE; + +typedef enum { + INTERFACE_NONE, + INTERFACE_NVME, + INTERFACE_SATA, + INTERFACE_UFS, + INTERFACE_NUM, +} INTERFACE; + +typedef enum { + SCHEDULER_NOOP, + SCHEDULER_NUM, +} SCHEDULER; + +class Config : public SimpleSSD::BaseConfig { + private: + SIM_MODE mode; + uint64_t logPeriod; + std::string logFile; + std::string logDebugFile; + std::string latencyFile; + uint64_t progressPeriod; + INTERFACE interface; + SCHEDULER scheduler; + uint64_t submissionLatency; + uint64_t completionLatency; + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/main.cc b/SSD-WAF-Analysis-Capstone-2025-main/sim/main.cc new file mode 100644 index 0000000000..77df8e0ea4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/main.cc @@ -0,0 +1,371 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include +#include +#include + +#include "bil/entry.hh" +#include "igl/request/request_generator.hh" +#include "igl/trace/trace_replayer.hh" +#include "sil/none/none.hh" +#include "sil/nvme/nvme.hh" +#include "sim/engine.hh" +#include "sim/signal.hh" +#include "simplessd/util/simplessd.hh" +#include "util/print.hh" + +// Global objects +Engine engine; +ConfigReader simConfig; +BIL::DriverInterface *pInterface = nullptr; +BIL::BlockIOEntry *pBIOEntry = nullptr; +IGL::IOGenerator *pIOGen = nullptr; +std::ostream *pLog = nullptr; +std::ostream *pDebugLog = nullptr; +std::ostream *pLatencyFile = nullptr; +std::thread *pThread = nullptr; +std::mutex killLock; +SimpleSSD::Event statEvent; +std::vector statList; +std::ofstream logOut; +std::ofstream debugLogOut; +std::ofstream latencyFile; + +// Declaration +void cleanup(int); +void statistics(uint64_t); +void threadFunc(int); + +void joinPath(std::string &lhs, std::string &rhs) { + if (rhs.front() == '/') { + // Assume absolute path + lhs = rhs; + } + else if (lhs.back() == '/') { + lhs += rhs; + } + else { + lhs += '/'; + lhs += rhs; + } +} + +int main(int argc, char *argv[]) { + std::cout << "SimpleSSD Standalone v2.0" << std::endl; + + // Check argument + if (argc != 4) { + std::cerr << " Invalid number of argument!" << std::endl; + std::cerr << " Usage: simplessd-standalone " + << std::endl; + + return 1; + } + + // Install signal handler + installSignalHandler(cleanup); + + // Read simulation config file + if (!simConfig.init(argv[1])) { + std::cerr << " Failed to open simulation configuration file!" << std::endl; + + return 2; + } + + // Log setting + bool noLogPrintOnScreen = true; + + std::string logPath = simConfig.readString(CONFIG_GLOBAL, GLOBAL_LOG_FILE); + std::string debugLogPath = + simConfig.readString(CONFIG_GLOBAL, GLOBAL_DEBUG_LOG_FILE); + std::string latencyLogPath = + simConfig.readString(CONFIG_GLOBAL, GLOBAL_LATENCY_LOG_FILE); + + if (logPath.compare("STDOUT") == 0) { + noLogPrintOnScreen = false; + pLog = &std::cout; + } + else if (logPath.compare("STDERR") == 0) { + noLogPrintOnScreen = false; + pLog = &std::cerr; + } + else if (logPath.length() != 0) { + std::string full(argv[3]); + + joinPath(full, logPath); + logOut.open(full); + + if (!logOut.is_open()) { + std::cerr << " Failed to open log file: " << full << std::endl; + + return 3; + } + + pLog = &logOut; + } + + if (debugLogPath.compare("STDOUT") == 0) { + noLogPrintOnScreen = false; + pDebugLog = &std::cout; + } + else if (debugLogPath.compare("STDERR") == 0) { + noLogPrintOnScreen = false; + pDebugLog = &std::cerr; + } + else if (debugLogPath.length() != 0) { + std::string full(argv[3]); + + joinPath(full, debugLogPath); + debugLogOut.open(full); + + if (!debugLogOut.is_open()) { + std::cerr << " Failed to open log file: " << full << std::endl; + + return 3; + } + + pDebugLog = &debugLogOut; + } + + if (latencyLogPath.length() != 0) { + std::string full(argv[3]); + + joinPath(full, latencyLogPath); + latencyFile.open(full); + + if (!latencyFile.is_open()) { + std::cerr << " Failed to open log file: " << full << std::endl; + + return 3; + } + + pLatencyFile = &latencyFile; + } + + // Initialize SimpleSSD + auto ssdConfig = initSimpleSSDEngine(&engine, pDebugLog, pDebugLog, argv[2]); + + // Create Driver + switch (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_INTERFACE)) { + case INTERFACE_NONE: + pInterface = new SIL::None::Driver(engine, ssdConfig); + + break; + case INTERFACE_NVME: + pInterface = new SIL::NVMe::Driver(engine, ssdConfig); + + break; + default: + std::cerr << " Undefined interface specified." << std::endl; + + return 4; + } + + // Create Block I/O Layer + pBIOEntry = + new BIL::BlockIOEntry(simConfig, engine, pInterface, pLatencyFile); + + std::function endCallback = []() { + // If stat printout is scheduled, delete it + if (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) > 0) { + engine.descheduleEvent(statEvent); + } + + // Stop simulation + engine.stopEngine(); + }; + + // Create I/O generator + switch (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_SIM_MODE)) { + case MODE_REQUEST_GENERATOR: + pIOGen = + new IGL::RequestGenerator(engine, *pBIOEntry, endCallback, simConfig); + + break; + case MODE_TRACE_REPLAYER: + pIOGen = + new IGL::TraceReplayer(engine, *pBIOEntry, endCallback, simConfig); + + break; + default: + std::cerr << " Undefined simulation mode specified." << std::endl; + + cleanup(0); + + return 5; + } + + std::function beginCallback = []() { + uint64_t bytesize; + uint32_t bs; + + pInterface->getInfo(bytesize, bs); + pIOGen->init(bytesize, bs); + pIOGen->begin(); + }; + + // Insert stat event + pInterface->initStats(statList); + + if (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) > 0) { + statEvent = engine.allocateEvent([](uint64_t tick) { + statistics(tick); + + engine.scheduleEvent( + statEvent, + tick + simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) * + 1000000000ULL); + }); + engine.scheduleEvent( + statEvent, + simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) * 1000000000ULL); + } + + // Do Simulation + std::cout << "********** Begin of simulation **********" << std::endl; + + pInterface->init(beginCallback); + + if (noLogPrintOnScreen) { + int period = (int)simConfig.readUint(CONFIG_GLOBAL, GLOBAL_PROGRESS_PERIOD); + + if (period > 0) { + pThread = new std::thread(threadFunc, period); + } + } + + while (engine.doNextEvent()) + ; + + cleanup(0); + + return 0; +} + +void cleanup(int) { + uint64_t tick; + + killLock.lock(); + + tick = engine.getCurrentTick(); + + if (tick == 0) { + // Exit program + exit(0); + } + + // Print last statistics + statistics(tick); + + // Erase progress + printf("\33[2K \r"); + + releaseSimpleSSDEngine(); + + pIOGen->printStats(std::cout); + engine.printStats(std::cout); + + // Cleanup all here + delete pInterface; + delete pIOGen; + + if (pThread) { + pThread->join(); + + delete pThread; + } + + delete pBIOEntry; // Used by progress thread + + if (logOut.is_open()) { + logOut.close(); + } + if (debugLogOut.is_open()) { + debugLogOut.close(); + } + + std::cout << "End of simulation @ tick " << tick << std::endl; + + // Exit program + exit(0); +} + +void statistics(uint64_t tick) { + if (pLog == nullptr) { + return; + } + + std::ostream &out = *pLog; + std::vector stat; + uint64_t count = 0; + + pInterface->getStats(stat); + + count = statList.size(); + + if (count != stat.size()) { + std::cerr << " Stat list length mismatch" << std::endl; + + std::terminate(); + } + + out << "Periodic log printout @ tick " << tick << std::endl; + + for (uint64_t i = 0; i < count; i++) { + print(out, statList[i].name, 40); + out << "\t"; + print(out, stat[i], 20); + out << "\t" << statList[i].desc << std::endl; + } + + out << "End of log @ tick " << tick << std::endl; +} + +void threadFunc(int tick) { + uint64_t current; + uint64_t old = 0; + float progress; + auto duration = std::chrono::seconds(tick); + BIL::Progress data; + + while (true) { + std::this_thread::sleep_for(duration); + + if (killLock.try_lock()) { + killLock.unlock(); + } + else { + break; + } + + engine.getStat(current); + pIOGen->getProgress(progress); + pBIOEntry->getProgress(data); + + printf("\33[2K*** Progress: %.2f%% (%lf ops) IOPS: %" PRIu64 " BW: %" PRIu64 + " B/s Avg. Lat: %" PRIu64 " ps\r", + progress * 100.f, (double)(current - old) / tick, data.iops, + data.bandwidth, data.latency); + fflush(stdout); + + old = current; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/signal.cc b/SSD-WAF-Analysis-Capstone-2025-main/sim/signal.cc new file mode 100644 index 0000000000..4c3542e2e8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/signal.cc @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +/* + * This file contains some codes from original gem5 project. + * See src/sim/backtrace_glib.cc and src/sim/init_signals.cc of gem5. + * Followings are copyright from gem5. + */ + +/* + * Copyright (c) 2015 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2000-2005 The Regents of The University of Michigan + * Copyright (c) 2008 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg, Nathan Binkert + */ + +#include "sim/signal.hh" + +#include +#include +#include +#include + +#include + +#ifdef _MSC_VER + +#pragma comment(lib, "dbghelp.lib") + +#include +// Windows.h should be included before DbgHelp.h +#include + +#ifndef _M_X64 +#error "Only x86_64 (AMD64) is supported." +#endif + +void (*closeHandler)(int) = nullptr; + +void print_backtrace(); + +BOOL consoleHandler(DWORD type) { + if (closeHandler) { + closeHandler(0); + } + + return TRUE; +} + +LONG WINAPI exceptionHandler(LPEXCEPTION_POINTERS pExceptionInfo) { + switch (pExceptionInfo->ExceptionRecord->ExceptionCode) { + case EXCEPTION_ACCESS_VIOLATION: + case EXCEPTION_IN_PAGE_ERROR: + std::cerr << "Program has encountered a segmentation fault." << std::endl; + break; + case EXCEPTION_INT_OVERFLOW: + case EXCEPTION_INT_DIVIDE_BY_ZERO: + std::cerr << "Program has encountered a floating point exception." + << std::endl; + break; + default: + std::cerr << "Program aborted." << std::endl; + } + + print_backtrace(); + + return EXCEPTION_EXECUTE_HANDLER; +} + +#else + +#include +#include + +#define FRAMECOUNT 32 + +static uint8_t stack[SIGSTKSZ * 2]; + +void print_backtrace(); + +static bool setupStack() { + stack_t st; + + st.ss_sp = stack; + st.ss_size = sizeof(stack); + st.ss_flags = 0; + + return sigaltstack(&st, nullptr) == 0; +} + +static void raiseSignal(int sig) { + pthread_kill(pthread_self(), sig); + + exit(0); +} + +static void installHandler(int sig, void (*handler)(int), + int flags = SA_RESTART) { + struct sigaction sa; + + memset(&sa, 0, sizeof(sa)); + sigemptyset(&sa.sa_mask); + sa.sa_handler = handler; + sa.sa_flags = flags; + + sigaction(sig, &sa, nullptr); +} + +void abortHandler(int sig) { + std::cerr << "Program aborted." << std::endl; + + print_backtrace(); + raiseSignal(sig); +} + +void segfaultHandler(int sig) { + std::cerr << "Program has encountered a segmentation fault." << std::endl; + + print_backtrace(); + raiseSignal(sig); +} + +void fpeHandler(int sig) { + std::cerr << "Program has encountered a floating point exception." + << std::endl; + + print_backtrace(); + raiseSignal(sig); +} + +#endif + +void print_backtrace() { + std::cerr << "--- BEGIN LIBC BACKTRACE ---" << std::endl; + +#ifdef _MSC_VER + CONTEXT context; + STACKFRAME64 frame; + DWORD type; + HANDLE hProcess = GetCurrentProcess(); + HANDLE hThread = GetCurrentThread(); + char buffer[sizeof(SYMBOL_INFO) + MAX_SYM_NAME * sizeof(char)]; + PSYMBOL_INFO symInfo = (PSYMBOL_INFO)buffer; + IMAGEHLP_MODULE modInfo; + DWORD64 displacement; + + RtlCaptureContext(&context); + + memset(&frame, 0, sizeof(STACKFRAME64)); + type = IMAGE_FILE_MACHINE_AMD64; + frame.AddrPC.Offset = context.Rip; + frame.AddrPC.Mode = AddrModeFlat; + frame.AddrFrame.Offset = context.Rsp; + frame.AddrFrame.Mode = AddrModeFlat; + frame.AddrStack.Offset = context.Rsp; + frame.AddrStack.Mode = AddrModeFlat; + + symInfo->SizeOfStruct = sizeof(SYMBOL_INFO); + symInfo->MaxNameLen = MAX_SYM_NAME; + modInfo.SizeOfStruct = sizeof(IMAGEHLP_MODULE); + + if (!SymInitialize(hProcess, nullptr, true)) { + std::cerr << "Failed to initialize symbol table." << std::endl; + std::cerr << "--- END LIBC BACKTRACE ---" << std::endl; + + return; + } + + while (true) { + if (!StackWalk64(type, hProcess, hThread, &frame, &context, nullptr, + SymFunctionTableAccess64, SymGetModuleBase64, nullptr)) { + break; + } + + if (frame.AddrPC.Offset != 0) { + // Get Module Name + if (SymGetModuleInfo(hProcess, frame.AddrPC.Offset, &modInfo)) { + std::cerr << modInfo.ModuleName; + } + else { + std::cerr << ""; + } + + // Get Symbole Name + if (SymFromAddr(hProcess, frame.AddrPC.Offset, &displacement, symInfo)) { + std::cerr << "(" << symInfo->Name << "+0x" << std::hex << displacement + << ")"; + } + + std::cerr << "[0x" << std::hex << frame.AddrPC.Offset << "]" << std::endl; + } + else { + break; + } + } + + SymCleanup(hProcess); + CloseHandle(hThread); + CloseHandle(hProcess); +#else + void *buffer[FRAMECOUNT]; + int size; + + size = backtrace(buffer, sizeof(buffer) / sizeof(*buffer)); + + backtrace_symbols_fd(buffer, size, STDERR_FILENO); + + if (size == sizeof(buffer)) + std::cerr << "Warning: Backtrace may have been truncated." << std::endl; +#endif + + std::cerr << "--- END LIBC BACKTRACE ---" << std::endl; +} + +void installSignalHandler(void (*handler)(int)) { +#ifdef _MSC_VER + closeHandler = handler; + SetConsoleCtrlHandler((PHANDLER_ROUTINE)consoleHandler, TRUE); + SetUnhandledExceptionFilter(exceptionHandler); +#else + installHandler(SIGINT, handler); + installHandler(SIGABRT, abortHandler, SA_RESETHAND | SA_NODEFER); + + setupStack(); + + installHandler(SIGSEGV, segfaultHandler, + SA_RESETHAND | SA_NODEFER | SA_ONSTACK); + installHandler(SIGFPE, fpeHandler, SA_RESETHAND | SA_NODEFER | SA_ONSTACK); +#endif +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/sim/signal.hh b/SSD-WAF-Analysis-Capstone-2025-main/sim/signal.hh new file mode 100644 index 0000000000..edbbc464f9 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/sim/signal.hh @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_SIGNAL__ +#define __SIM_SIGNAL__ + +void installSignalHandler(void (*)(int)); + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.clang-format b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.clang-format new file mode 100644 index 0000000000..f47274946a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.clang-format @@ -0,0 +1,29 @@ +# Generated by clang-format v6.0.0 +--- +Language: Cpp +BasedOnStyle: Google +AlignEscapedNewlines: Right +AllowShortFunctionsOnASingleLine: Inline +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakBeforeMultilineStrings: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: true + BeforeElse: true + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBraces: Custom +DerivePointerAlignment: false +PointerAlignment: Right +... diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.gitignore b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.gitignore new file mode 100644 index 0000000000..e093375753 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.gitignore @@ -0,0 +1,34 @@ +# Visual Studio Specific +.vs/ +*.sln +*.db +*.opendb +*.vcproj +*.filters +*.vcxproj +Debug/ +Release/ +x64/ +.vscode/ + +# CMake Specific +CMakeCache.txt +CMakeFiles +CMakeScripts +Testing +Makefile +cmake_install.cmake +install_manifest.txt +compile_commands.json +CTestTestfile.cmake + +# Atom editor specific +.clang_complete + +# Python +*.pyc +temp_build/ + +# Library output +libsimplessd.a +libmcpat.a diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.gitmodules b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.gitmodules new file mode 100644 index 0000000000..87d6d583db --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/.gitmodules @@ -0,0 +1,3 @@ +[submodule "lib/mcpat"] + path = lib/mcpat + url = git@github.com:simplessd/mcpat diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/CMakeLists.txt b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/CMakeLists.txt new file mode 100644 index 0000000000..4e1abaefb7 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/CMakeLists.txt @@ -0,0 +1,203 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# Set version and project name +cmake_minimum_required(VERSION 3.10) +project(simplessd) + +# Add options for debug build +option(DEBUG_BUILD "Build SimpleSSD in debug mode." OFF) + +# Set output directory +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) + +# Set cache entry for external library include path +set(DRAMPOWER_SOURCE_DIR "." CACHE PATH "Source directory to DRAMPower library") + +# Check DRAMPOWER_SOURCE_DIR is valid +if (NOT EXISTS "${DRAMPOWER_SOURCE_DIR}/libdrampower/LibDRAMPower.h") + message(FATAL_ERROR "Failed to find DRAMPower library. \ +Check you specified DRAMPower path by -DDRAMPOWER_SOURCE_DIR.") +endif () + +# Check mcpat is valid +if (NOT EXISTS "${PROJECT_SOURCE_DIR}/lib/mcpat/mcpat.h") + message(FATAL_ERROR "Failed to find McPAT library. \ +Check you initialized submodules.") +endif () + +# Add subproject +add_subdirectory(${PROJECT_SOURCE_DIR}/lib/mcpat) + +# Set include directories +include_directories( + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/lib/mcpat + ${PROJECT_SOURCE_DIR}/lib/mcpat/cacti + ${PROJECT_SOURCE_DIR}/lib/inih + ${DRAMPOWER_SOURCE_DIR} +) + +# Platform specific settings +if (MSVC) + add_definitions(-D_CRT_SECURE_NO_WARNINGS) + add_compile_options(/wd4819) # Surpress unicode warning + add_compile_options(/wd4244) # Surpress conversion warning + add_compile_options(/wd4267) # Surpress conversion warning + add_compile_options(/wd4305) # Surpress truncation warning + add_compile_options(/wd4800) # Surpress int -> boolean waring +else () + if (APPLE) + # macOS doesn't support -rdynamic flag + set(CMAKE_CXX_FLAGS "-g -Wall -Wextra ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS "-g -rdynamic -Wall -Wextra -Werror ${CMAKE_CXX_FLAGS}") + endif () + + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS "-O0 ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS "-O2 ${CMAKE_CXX_FLAGS}") + endif () + + if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS "6.0") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-strict-aliasing") + endif () + endif () +endif () + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Specify source files +set(SRC_CPU + cpu/config.cc + cpu/cpu.cc +) +set(SRC_DRAM + dram/abstract_dram.cc + dram/config.cc + dram/simple.cc +) +set(SRC_FTL_COMMON + ftl/common/block.cc +) +set(SRC_FTL + ftl/config.cc + ftl/ftl.cc + ftl/page_mapping.cc +) +set(SRC_HIL_NVME + hil/nvme/abstract_subsystem.cc + hil/nvme/config.cc + hil/nvme/controller.cc + hil/nvme/dma.cc + hil/nvme/namespace.cc + hil/nvme/ocssd.cc + hil/nvme/queue.cc + hil/nvme/subsystem.cc +) +set(SRC_HIL_SATA + hil/sata/config.cc + hil/sata/device.cc + hil/sata/hba.cc +) +set(SRC_HIL_UFS + hil/ufs/config.cc + hil/ufs/def.cc + hil/ufs/device.cc + hil/ufs/host.cc +) +set(SRC_HIL + hil/hil.cc +) +set(SRC_ICL + icl/abstract_cache.cc + icl/config.cc + icl/generic_cache.cc + icl/icl.cc +) +set(SRC_LIB_INIH + lib/inih/ini.c +) +set(SRC_PAL_OLD + pal/old/Latency.cc + pal/old/LatencyMLC.cc + pal/old/LatencySLC.cc + pal/old/LatencyTLC.cc + pal/old/PAL2.cc + pal/old/PAL2_TimeSlot.cc + pal/old/PALStatistics.cc +) +set(SRC_PAL + pal/config.cc + pal/pal.cc + pal/pal_old.cc +) +set(SRC_SIM + sim/config_reader.cc + sim/cpu.cc + sim/log.cc + sim/simulator.cc + sim/state.cc +) +set(SRC_UTIL + util/bitset.cc + util/def.cc + util/disk.cc + util/fifo.cc + util/interface.cc + util/simplessd.cc +) + +# Source group for MSVC +SOURCE_GROUP("Source Files\\cpu" FILES ${SRC_CPU}) +SOURCE_GROUP("Source Files\\dram" FILES ${SRC_DRAM}) +SOURCE_GROUP("Source Files\\ftl" FILES ${SRC_FTL}) +SOURCE_GROUP("Source Files\\ftl\\common" FILES ${SRC_FTL_COMMON}) +SOURCE_GROUP("Source Files\\hil" FILES ${SRC_HIL}) +SOURCE_GROUP("Source Files\\hil\\nvme" FILES ${SRC_HIL_NVME}) +SOURCE_GROUP("Source Files\\hil\\sata" FILES ${SRC_HIL_SATA}) +SOURCE_GROUP("Source Files\\hil\\ufs" FILES ${SRC_HIL_UFS}) +SOURCE_GROUP("Source Files\\icl" FILES ${SRC_ICL}) +SOURCE_GROUP("Source Files\\lib\\inih" FILES ${SRC_LIB_INIH}) +SOURCE_GROUP("Source Files\\pal" FILES ${SRC_PAL}) +SOURCE_GROUP("Source Files\\pal\\old" FILES ${SRC_PAL_OLD}) +SOURCE_GROUP("Source Files\\sim" FILES ${SRC_SIM}) +SOURCE_GROUP("Source Files\\util" FILES ${SRC_UTIL}) + +# Define library +add_library(simplessd STATIC + ${SRC_CPU} + ${SRC_DRAM} + ${SRC_FTL} + ${SRC_FTL_COMMON} + ${SRC_HIL} + ${SRC_HIL_NVME} + ${SRC_HIL_SATA} + ${SRC_HIL_UFS} + ${SRC_ICL} + ${SRC_LIB_INIH} + ${SRC_PAL} + ${SRC_PAL_OLD} + ${SRC_SIM} + ${SRC_UTIL} +) +target_link_libraries(simplessd mcpat) diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/CODINGSTYLE.md b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/CODINGSTYLE.md new file mode 100644 index 0000000000..f1f85d0418 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/CODINGSTYLE.md @@ -0,0 +1,17 @@ +# Coding Style +## File +### File Extension +- C++: Use `*.cc` for source files and `*.hh` for header files. +- C: Use `*.c` for source files and `*.h` for header files. + +### File name +Use `snake_case` for filenames. Use only lower-case characters. + +## Language +### C/C++ +User defined type uses `CamelCase`. Typename should begin with upper-case characters. +Variable/function name uses `camelCase`. Variable/function name should begin with lower-case characters. + +### Formatting using `clang-format` +Use C/C++ code formatter `clang-format` version >= 6.0. +See .clang-format file for style definition. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/LICENSE b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/LICENSE new file mode 100644 index 0000000000..8ca04e5e57 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + SimpleSSD + Copyright (C) 2017 SimpleSSD + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + SimpleSSD Copyright (C) 2017 SimpleSSD + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/README.md b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/README.md new file mode 100644 index 0000000000..e92d0cfd59 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/README.md @@ -0,0 +1,15 @@ +# SimpleSSD version 2.0 +Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations + +This project is managed by [CAMELab](http://camelab.org). +For more information, please visit [SimpleSSD homepage](http://simplessd.org). + +## Licenses +SimpleSSD is released under the GPLv3 license. See `LICENSE` file for details. +SimpleSSD uses open-source libraries. + + - [inih](https://github.com/benhoyt/inih) located at `/lib/inih` +INI parser library released under the New BSD license. + - [McPAT](https://github.com/HewlettPackard/mcpat) located at `/lib/mcpat` +Multicore Power Area and Timing calculator. +We modified source code to separate initialize phase and calculation phase. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/config/page_mapping_ssd.cfg b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/config/page_mapping_ssd.cfg new file mode 100644 index 0000000000..a91037377a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/config/page_mapping_ssd.cfg @@ -0,0 +1,494 @@ +# +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . +# + +# +# Sample SimpleSSD Configuration File +# +# Section: +# cpu: SSD Controller CPU configuration +# nvme: Non-Volatile Memory Express configuration +# ufs: Universal Flash Storage configuration +# sata: Serial ATA configuration +# pal: Parallelism Abstraction Layer configuration +# ftl: Flash Translation Layer configuration +# icl: Internal Cache Layer configuration +# dram: DRAM configuration +# + +# SSD Controller CPU configuration +[cpu] +## Set clock speed in Hz +ClockSpeed = 400000000 + +## Set dedicated core count +HILCoreCount = 1 +ICLCoreCount = 1 +FTLCoreCount = 1 + +# NVMe interface Configuration +[nvme] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NVMe Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## Hardware FIFO Transfer unit +# Smaller value introduce smaller latency +FIFOTransferUnit = 2048 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## Set maximum number of I/O queue that controller supports +# You should check BAR0 size to fit all doorbell +# Doorbell stride is always 0 (4bytes align) +MaxIOCQueue = 16 +MaxIOSQueue = 16 + +## Set parameters of Weighted Round robin +# Set how many commands should be inserted to internal FIFO +# before switch to next low priority +WRRHigh = 2 # Medium-priority command will inserted after two high-priority commands inserted +WRRMedium = 2 # Low-priority command will inserted after two medium-priority command inserted + +## Default Namespace +# Specify number of namespaces to create +# Each namespace has same capacity +DefaultNamespace = 1 + +## LBA Size +# Set logical block size of default namespace +# If DefaultNamespace is false, this value will ignored +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk size check +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 + +## List of disk image path for each namespace +# e.g. Setting disk image for namespace 2 -> DiskImageFile2 = +DiskImageFile1 = nvme.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Universal Flash Storage Configuration +[ufs] + +## AMBA System Bus <-> UFS Host Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 1 +AXIClock = 250000000 # 64bit @ 250MHz -> 2GB/s + +## UFS Host Controller <-> UFS Device +# Set MIPI M-PHY mode and lane count +# Possible values: +# 0: HS-G1 +# 1: HS-G2 +# 2: HS-G3 +# 3: HS-G4 +MPHYMode = 2 +MPHYLane = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = ufs.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Serial ATA Configuration +[sata] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NSATA AHCI HBA +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## SATA AHCI HBA <-> SATA Device +# Set SATA generation +# Possible values: +# 0: SATA 1.0 (1.5Gbps) +# 1: SATA 2.0 (3Gbps) +# 2: SATA 3.0 (6Gbps) +SATAMode = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = sata.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Parallelism Abstraction Layer Configuration +[pal] + +## Set SSD structure +# Channel: # of channels in SSD +# Package: # of packages in one channel +Channel = 4 +Package = 8 + +## Set NAND package structure +# Die: # of die in one package +# Plane: # of plane in one die +# Block: # of block in one plane +# Page: # of page in one block +# PageSize: Size of one page in byte +Die = 2 +Plane = 2 +Block = 512 +Page = 512 +PageSize = 8192 + +## Multi-plane operation +# 1 for enable multi-plane operation +EnableMultiPlaneOperation = 0s + +## Set type of NAND flash +# Possible values: +# 0: Single Level Cell +# 1: Multi Level Cell +# 2: Triple Level Cell +# Please check NAND timing has valid values +# SLC: LSB timing should valid +# MLC: LSB and MSB timing should valid +# TLC: LSB, CSB and MSB timing should valid +NANDType = 1 + +## Set NAND timing +LSBRead = 40000000 +LSBWrite = 500000000 +CSBRead = 0 +CSBWrite = 0 +MSBRead = 65000000 +MSBWrite = 1300000000 +Erase = 3500000000 + +## Set speed and width of DMA in channel in MT/s +# Width should be 8 or 16 +# Typical values from ONFi: +# ONFi 1.x 2.x 3.x~4.x 4.x +# Timing Mode SDR NV-DDR NV-DDR2 NV-DDR3 +# 0 10 40 67 67 +# 1 20 67 80 80 +# 2 29 100 133 133 +# 3 33 133 167 167 +# 4 40 167 200 200 +# 5 50 200 267 267 +# 6 - - 333 333 +# 7 - - 400 400 +# 8 - - 533 533 +# 9 - - - 667 +# 10 - - - 800 +DMASpeed = 400 +DMAWidth = 8 + +## Set superblock/page size +# Superblock/page size will multiplied by each values +# Leave empty will disable superblock feature +# Possible values: +# C: # Channel +# W: # Package/Way +# D: # Die +# P: # Plane (If multi-plane mode is enabled, P will always applied) +SuperblockSize = + +## Set page allocation order +# This order will used when disassembling logical address to physical address +# Possible values: +# C: Channel +# W: Package/Way +# D: Die +# P: Plane +PageAllocation = CWDP + +# Flash Translation Layer Configuration +[ftl] + +## Set mapping method +# Possible values: +# 0: Page level mapping +MappingMode = 0 + +## Set FTL over-provisioning ratio +OverProvisioningRatio = 0.30 + +## Set FTL erase threshold to mark as bad block +EraseThreshold = 100000 + +## Filling options +# Filling Mode +# Possible values: +# 0: Sequential filling + Sequential invalidation +# 1: Sequential filling + Random invalidation +# 2: Random filling + Random invalidation +FillingMode = 0 +# FillRatio +# Fill (warm-up) pages before simulation +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +FillRatio = 0.0 +# InvalidPageRatio +# Create invalid pages by overwrite filled pages +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +InvalidPageRatio = 0.0 + +## Set victim selection algorithm +# Possible values: +# 0: Greedy: Choose least utilized block to clean +# 1: Cost-Benefit: Choose a block that lowest (Utilization / ((1 - Utilization) * Age)) +# 2: Random: Choose random block +# 3: D-CHOICE: Choose least utilized block in randomly sampled blocks +EvictPolicy = 1 + + +## DChoice parameter +# When sampling blocks, total blocks to erase * DChoiceParam will be selected +DChoiceParam = 12 + +## Set garbage collection threshold (ratio of free blocks left) +GCThreshold = 0.05 + +## Garbage collection mode +# Possible values: +# 0: Reclaim n blocks +# 1: Reclaim blocks until threshold +GCMode = 0 + +## Specify n (Only in GCMode = 0) +# n > 0 +GCReclaimBlocks = 16 + +## Specify threshold (Only in GCMode = 1) +# t > GCThreshold +GCReclaimThreshold = 0.15 + +## Random I/O tweak +# Enable random I/O tweak when using superpage based mapping +EnableRandomIOTweak = 0 + +# Internal Cache Layer Configuration +[icl] + +## Set Cache size +# Cacheline size = physical page size * (multi-plane mode ? plane count : 1) +# Directed-map cache: Set way as 1 +# Fully-associative cache: Set way value as 0 +CacheSize = 536870912 # 512MiB +CacheWaySize = 8 + +## Set read caching (1 for enable) +EnableReadCache = 1 + +## Set read prefetching (1 for enable) +EnableReadPrefetch = 0 + +## Set prefetch granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +ReadPrefetchMode = 1 + +## Set # of I/O to determine sequential access +# Value < 1 is invalid +# 1 means if 2 contiguous I/O is sequential, prefetch will be enabled +ReadPrefetchCount = 3 + +## Set size of sequential I/O to determine as sequential access +# At least (Super page size * ratio) should be accessed as sequential +# 0 < ratio +ReadPrefetchRatio = 0.25 + +## Set write caching (1 for enable) +EnableWriteCache = 1 + +## Set cache evict policy +# Possible values: +# 0: RANDOM: Evict entry in random fashion +# 1: FIFO: Evict most oldest entry in selected set +# 2: LRU: Evict least recently used entry in selected set +EvictPolicy = 2 + +## Set cache evict granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +EvictMode = 0 + +## Set cache metadata latency +# Byte / ps +CacheLatency = 10 + +# DRAM configuration +[dram] + +## Select DRAM model to use +# Possible values: +# 0: Simple DRAM model based on atomic dram controller of gem5 +Model = 0 + +## DRAM structure parameters +Channel = 1 +Rank = 1 +Bank = 8 +Chip = 1 +BusWidth = 32 +BurstLength = 8 +ChipSize = 1073741824 +PageSize = 4096 + +## DRAM timing parameters (Unit: ps) +# tCK = 1250 +# tRCD = 13750 +# tCL = 13750 +# tRP = 13750 +# tRAS = 35000 +# tWR = 15000 +# tRTP = 7500 +# tBURST +# tCCD_L = +# tRFC = 160000 # 160ns ~ 70200ns +# tREFI = 7800000 +# tWTR = 7500 +# tRTW = +# tCS = +# tRRD = 6000 +# tRRD_L = +# tXAW = +# tXP = 6000 +# tXPDLL = 24000 +# tXS = 170000 # tRFC + 10ns +# tXSDLL = 640000 + +## DRAM power parameters (Unit: mA or V) +# IDD0_0 = 40 +# IDD0_1 = 0 +# IDD2P0_0 = 12 +# IDD2P0_1 = 0 +# IDD2P1_0 = 14 +# IDD2P1_1 = 0 +# IDD2N_0 = 21 +# IDD2N_1 = 0 +# IDD3P0_0 = 21 +# IDD3P0_1 = 0 +# IDD3P1_0 = 21 +# IDD3P1_1 = 0 +# IDD3N_0 = 34 +# IDD3N_1 = 0 +# IDD4R_0 = 100 +# IDD4R_1 = 0 +# IDD4W_0 = 105 +# IDD4W_1 = 0 +# IDD5_0 = 182 +# IDD5_1 = 0 +# IDD6_0 = 12 +# IDD6_1 = 0 +# VDD_0 = 1.35 +# VDD_1 = 0 diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/config/sample.cfg b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/config/sample.cfg new file mode 100644 index 0000000000..4f52b49adf --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/config/sample.cfg @@ -0,0 +1,493 @@ +# +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . +# + +# +# Sample SimpleSSD Configuration File +# +# Section: +# cpu: SSD Controller CPU configuration +# nvme: Non-Volatile Memory Express configuration +# ufs: Universal Flash Storage configuration +# sata: Serial ATA configuration +# pal: Parallelism Abstraction Layer configuration +# ftl: Flash Translation Layer configuration +# icl: Internal Cache Layer configuration +# dram: DRAM configuration +# + +# SSD Controller CPU configuration +[cpu] +## Set clock speed in Hz +ClockSpeed = 400000000 + +## Set dedicated core count +HILCoreCount = 1 +ICLCoreCount = 1 +FTLCoreCount = 1 + +# NVMe interface Configuration +[nvme] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NVMe Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## Hardware FIFO Transfer unit +# Smaller value introduce smaller latency +FIFOTransferUnit = 2048 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## Set maximum number of I/O queue that controller supports +# You should check BAR0 size to fit all doorbell +# Doorbell stride is always 0 (4bytes align) +MaxIOCQueue = 16 +MaxIOSQueue = 16 + +## Set parameters of Weighted Round robin +# Set how many commands should be inserted to internal FIFO +# before switch to next low priority +WRRHigh = 2 # Medium-priority command will inserted after two high-priority commands inserted +WRRMedium = 2 # Low-priority command will inserted after two medium-priority command inserted + +## Default Namespace +# Specify number of namespaces to create +# Each namespace has same capacity +DefaultNamespace = 1 + +## LBA Size +# Set logical block size of default namespace +# If DefaultNamespace is false, this value will ignored +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk size check +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 + +## List of disk image path for each namespace +# e.g. Setting disk image for namespace 2 -> DiskImageFile2 = +DiskImageFile1 = nvme.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Universal Flash Storage Configuration +[ufs] + +## AMBA System Bus <-> UFS Host Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 1 +AXIClock = 250000000 # 64bit @ 250MHz -> 2GB/s + +## UFS Host Controller <-> UFS Device +# Set MIPI M-PHY mode and lane count +# Possible values: +# 0: HS-G1 +# 1: HS-G2 +# 2: HS-G3 +# 3: HS-G4 +MPHYMode = 2 +MPHYLane = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = ufs.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Serial ATA Configuration +[sata] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NSATA AHCI HBA +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## SATA AHCI HBA <-> SATA Device +# Set SATA generation +# Possible values: +# 0: SATA 1.0 (1.5Gbps) +# 1: SATA 2.0 (3Gbps) +# 2: SATA 3.0 (6Gbps) +SATAMode = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = sata.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Parallelism Abstraction Layer Configuration +[pal] + +## Set SSD structure +# Channel: # of channels in SSD +# Package: # of packages in one channel +Channel = 8 +Package = 4 + +## Set NAND package structure +# Die: # of die in one package +# Plane: # of plane in one die +# Block: # of block in one plane +# Page: # of page in one block +# PageSize: Size of one page in byte +Die = 2 +Plane = 2 +Block = 512 +Page = 512 +PageSize = 8192 + +## Multi-plane operation +# 1 for enable multi-plane operation +EnableMultiPlaneOperation = 1 + +## Set type of NAND flash +# Possible values: +# 0: Single Level Cell +# 1: Multi Level Cell +# 2: Triple Level Cell +# Please check NAND timing has valid values +# SLC: LSB timing should valid +# MLC: LSB and MSB timing should valid +# TLC: LSB, CSB and MSB timing should valid +NANDType = 1 + +## Set NAND timing +LSBRead = 40000000 +LSBWrite = 500000000 +CSBRead = 0 +CSBWrite = 0 +MSBRead = 65000000 +MSBWrite = 1300000000 +Erase = 3500000000 + +## Set speed and width of DMA in channel in MT/s +# Width should be 8 or 16 +# Typical values from ONFi: +# ONFi 1.x 2.x 3.x~4.x 4.x +# Timing Mode SDR NV-DDR NV-DDR2 NV-DDR3 +# 0 10 40 67 67 +# 1 20 67 80 80 +# 2 29 100 133 133 +# 3 33 133 167 167 +# 4 40 167 200 200 +# 5 50 200 267 267 +# 6 - - 333 333 +# 7 - - 400 400 +# 8 - - 533 533 +# 9 - - - 667 +# 10 - - - 800 +DMASpeed = 400 +DMAWidth = 8 + +## Set superblock/page size +# Superblock/page size will multiplied by each values +# Leave empty will disable superblock feature +# Possible values: +# C: # Channel +# W: # Package/Way +# D: # Die +# P: # Plane (If multi-plane mode is enabled, P will always applied) +SuperblockSize = C + +## Set page allocation order +# This order will used when disassembling logical address to physical address +# Possible values: +# C: Channel +# W: Package/Way +# D: Die +# P: Plane +PageAllocation = CWDP + +# Flash Translation Layer Configuration +[ftl] + +## Set mapping method +# Possible values: +# 0: Page level mapping +MappingMode = 0 + +## Set FTL over-provisioning ratio +OverProvisioningRatio = 0.70 + +## Set FTL erase threshold to mark as bad block +EraseThreshold = 100000 + +## Filling options +# Filling Mode +# Possible values: +# 0: Sequential filling + Sequential invalidation +# 1: Sequential filling + Random invalidation +# 2: Random filling + Random invalidation +FillingMode = 0 +# FillRatio +# Fill (warm-up) pages before simulation +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +FillRatio = 0.0 +# InvalidPageRatio +# Create invalid pages by overwrite filled pages +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +InvalidPageRatio = 0.0 + +## Set victim selection algorithm +# Possible values: +# 0: Greedy: Choose least utilized block to clean +# 1: Cost-Benefit: Choose a block that lowest (Utilization / ((1 - Utilization) * Age)) +# 2: Random: Choose random block +# 3: D-CHOICE: Choose least utilized block in randomly sampled blocks +EvictPolicy = 0 + +## DChoice parameter +# When sampling blocks, total blocks to erase * DChoiceParam will be selected +DChoiceParam = 3 + +## Set garbage collection threshold (ratio of free blocks left) +GCThreshold = 0.64 + +## Garbage collection mode +# Possible values: +# 0: Reclaim n blocks +# 1: Reclaim blocks until threshold +GCMode = 0 + +## Specify n (Only in GCMode = 0) +# n > 0 +GCReclaimBlocks = 1 + +## Specify threshold (Only in GCMode = 1) +# t > GCThreshold +GCReclaimThreshold = 0.12 + +## Random I/O tweak +# Enable random I/O tweak when using superpage based mapping +EnableRandomIOTweak = 1 + +# Internal Cache Layer Configuration +[icl] + +## Set Cache size +# Cacheline size = physical page size * (multi-plane mode ? plane count : 1) +# Directed-map cache: Set way as 1 +# Fully-associative cache: Set way value as 0 +CacheSize = 536870912 # 512MiB +CacheWaySize = 8 + +## Set read caching (1 for enable) +EnableReadCache = 1 + +## Set read prefetching (1 for enable) +EnableReadPrefetch = 1 + +## Set prefetch granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +ReadPrefetchMode = 1 + +## Set # of I/O to determine sequential access +# Value < 1 is invalid +# 1 means if 2 contiguous I/O is sequential, prefetch will be enabled +ReadPrefetchCount = 3 + +## Set size of sequential I/O to determine as sequential access +# At least (Super page size * ratio) should be accessed as sequential +# 0 < ratio +ReadPrefetchRatio = 0.25 + +## Set write caching (1 for enable) +EnableWriteCache = 1 + +## Set cache evict policy +# Possible values: +# 0: RANDOM: Evict entry in random fashion +# 1: FIFO: Evict most oldest entry in selected set +# 2: LRU: Evict least recently used entry in selected set +EvictPolicy = 2 + +## Set cache evict granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +EvictMode = 1 + +## Set cache metadata latency +# Byte / ps +CacheLatency = 10 + +# DRAM configuration +[dram] + +## Select DRAM model to use +# Possible values: +# 0: Simple DRAM model based on atomic dram controller of gem5 +Model = 0 + +## DRAM structure parameters +Channel = 1 +Rank = 1 +Bank = 8 +Chip = 1 +BusWidth = 32 +BurstLength = 8 +ChipSize = 1073741824 +PageSize = 4096 + +## DRAM timing parameters (Unit: ps) +# tCK = 1250 +# tRCD = 13750 +# tCL = 13750 +# tRP = 13750 +# tRAS = 35000 +# tWR = 15000 +# tRTP = 7500 +# tBURST +# tCCD_L = +# tRFC = 160000 # 160ns ~ 70200ns +# tREFI = 7800000 +# tWTR = 7500 +# tRTW = +# tCS = +# tRRD = 6000 +# tRRD_L = +# tXAW = +# tXP = 6000 +# tXPDLL = 24000 +# tXS = 170000 # tRFC + 10ns +# tXSDLL = 640000 + +## DRAM power parameters (Unit: mA or V) +# IDD0_0 = 40 +# IDD0_1 = 0 +# IDD2P0_0 = 12 +# IDD2P0_1 = 0 +# IDD2P1_0 = 14 +# IDD2P1_1 = 0 +# IDD2N_0 = 21 +# IDD2N_1 = 0 +# IDD3P0_0 = 21 +# IDD3P0_1 = 0 +# IDD3P1_0 = 21 +# IDD3P1_1 = 0 +# IDD3N_0 = 34 +# IDD3N_1 = 0 +# IDD4R_0 = 100 +# IDD4R_1 = 0 +# IDD4W_0 = 105 +# IDD4W_1 = 0 +# IDD5_0 = 182 +# IDD5_1 = 0 +# IDD6_0 = 12 +# IDD6_1 = 0 +# VDD_0 = 1.35 +# VDD_1 = 0 diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/config.cc new file mode 100644 index 0000000000..f010e48741 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/config.cc @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "cpu/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace CPU { + +const char NAME_CLOCK[] = "ClockSpeed"; +const char NAME_CORE_HIL[] = "HILCoreCount"; +const char NAME_CORE_ICL[] = "ICLCoreCount"; +const char NAME_CORE_FTL[] = "FTLCoreCount"; + +Config::Config() { + clock = 400000000; + hilCore = 1; + iclCore = 1; + ftlCore = 1; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_CLOCK)) { + clock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CORE_HIL)) { + hilCore = (uint32_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CORE_ICL)) { + iclCore = (uint32_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CORE_FTL)) { + ftlCore = (uint32_t)strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (clock == 0) { + panic("Invalid ClockSpeed"); + } +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case CPU_CLOCK: + ret = clock; + break; + case CPU_CORE_HIL: + ret = hilCore; + break; + case CPU_CORE_ICL: + ret = iclCore; + break; + case CPU_CORE_FTL: + ret = ftlCore; + break; + } + + return ret; +} + +} // namespace CPU + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/config.hh new file mode 100644 index 0000000000..24b93cf8a1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/config.hh @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __CPU_CONFIG__ +#define __CPU_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace CPU { + +typedef enum { + CPU_CLOCK, + CPU_CORE_HIL, + CPU_CORE_ICL, + CPU_CORE_FTL, +} CPU_CONFIG; + +class Config : public BaseConfig { + private: + uint64_t clock; //!< Default: 400MHz + uint32_t hilCore; //!< Default: 1 + uint32_t iclCore; //!< Default: 1 + uint32_t ftlCore; //!< Default: 1 + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; +}; + +} // namespace CPU + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/cpu.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/cpu.cc new file mode 100644 index 0000000000..36823c13d8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/cpu.cc @@ -0,0 +1,1005 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "cpu/cpu.hh" + +#include + +#include "sim/trace.hh" + +namespace SimpleSSD { + +namespace CPU { + +InstStat::_InstStat() + : branch(0), + load(0), + store(0), + arithmetic(0), + floatingPoint(0), + otherInsts(0), + latency(0) {} + +InstStat::_InstStat(uint64_t b, uint64_t l, uint64_t s, uint64_t a, uint64_t f, + uint64_t o, uint64_t c) + : branch(b), + load(l), + store(s), + arithmetic(a), + floatingPoint(f), + otherInsts(o) { + latency = sum(); + latency *= c; +} + +InstStat &InstStat::operator+=(const InstStat &rhs) { + this->branch += rhs.branch; + this->load += rhs.load; + this->store += rhs.store; + this->arithmetic += rhs.arithmetic; + this->floatingPoint += rhs.floatingPoint; + this->otherInsts += rhs.otherInsts; + // Do not add up totalcycles + + return *this; +} + +uint64_t InstStat::sum() { + return branch + load + store + arithmetic + floatingPoint + otherInsts; +} + +JobEntry::_JobEntry(DMAFunction &f, void *c, InstStat *i) + : func(f), context(c), inst(i) {} + +CPU::CoreStat::CoreStat() : busy(0) {} + +CPU::Core::Core() : busy(false) { + jobEvent = allocate([this](uint64_t) { jobDone(); }); +} + +CPU::Core::~Core() {} + +bool CPU::CPU::Core::isBusy() { + return busy; +} + +uint64_t CPU::CPU::Core::getJobListSize() { + return jobs.size(); +} + +CPU::CoreStat &CPU::Core::getStat() { + return stat; +} + +void CPU::Core::submitJob(JobEntry job, uint64_t delay) { + job.delay = delay; + job.submitAt = getTick(); + jobs.push(job); + + if (!busy) { + handleJob(); + } +} + +void CPU::Core::handleJob() { + auto &iter = jobs.front(); + uint64_t now = getTick(); + uint64_t diff = now - iter.submitAt; + uint64_t finishedAt; + + if (diff >= iter.delay) { + finishedAt = now + iter.inst->latency; + } + else { + finishedAt = now + iter.inst->latency + iter.delay - diff; + } + + busy = true; + + schedule(jobEvent, finishedAt); +} + +void CPU::Core::jobDone() { + auto &iter = jobs.front(); + + iter.func(getTick(), iter.context); + stat.busy += iter.inst->latency; + stat.instStat += *iter.inst; + + jobs.pop(); + busy = false; + + if (jobs.size() > 0) { + handleJob(); + } +} + +void CPU::Core::addStat(InstStat &inst) { + stat.busy += inst.latency; + stat.instStat += inst; +} + +CPU::CPU(ConfigReader &c) : conf(c), lastResetStat(0) { + clockSpeed = conf.readUint(CONFIG_CPU, CPU_CLOCK); + clockPeriod = 1000000000000. / clockSpeed; // in pico-seconds + + hilCore.resize(conf.readUint(CONFIG_CPU, CPU_CORE_HIL)); + iclCore.resize(conf.readUint(CONFIG_CPU, CPU_CORE_ICL)); + ftlCore.resize(conf.readUint(CONFIG_CPU, CPU_CORE_FTL)); + + // Initialize CPU table + cpi.insert({FTL, std::unordered_map()}); + cpi.insert({FTL__PAGE_MAPPING, std::unordered_map()}); + cpi.insert({ICL, std::unordered_map()}); + cpi.insert({ICL__GENERIC_CACHE, std::unordered_map()}); + cpi.insert({HIL, std::unordered_map()}); + cpi.insert({NVME__CONTROLLER, std::unordered_map()}); + cpi.insert({NVME__PRPLIST, std::unordered_map()}); + cpi.insert({NVME__SGL, std::unordered_map()}); + cpi.insert({NVME__SUBSYSTEM, std::unordered_map()}); + cpi.insert({NVME__NAMESPACE, std::unordered_map()}); + cpi.insert({NVME__OCSSD, std::unordered_map()}); + cpi.insert({UFS__DEVICE, std::unordered_map()}); + cpi.insert({SATA__DEVICE, std::unordered_map()}); + + // Insert item (Use cpu/generator/generate.py to generate this code) + cpi.find(0)->second.insert({0, InstStat(5, 32, 6, 13, 0, 1, clockPeriod)}); + cpi.find(0)->second.insert({1, InstStat(5, 32, 6, 13, 0, 1, clockPeriod)}); + cpi.find(0)->second.insert({3, InstStat(5, 32, 6, 13, 0, 1, clockPeriod)}); + cpi.find(0)->second.insert({4, InstStat(4, 24, 4, 6, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert({0, InstStat(8, 28, 7, 18, 0, 1, clockPeriod)}); + cpi.find(1)->second.insert({1, InstStat(8, 28, 7, 19, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert({3, InstStat(4, 28, 6, 11, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert( + {4, InstStat(63, 180, 21, 147, 0, 2, clockPeriod)}); + cpi.find(1)->second.insert( + {9, InstStat(177, 504, 113, 415, 118, 19, clockPeriod)}); + cpi.find(1)->second.insert( + {10, InstStat(157, 616, 102, 338, 0, 2, clockPeriod)}); + cpi.find(1)->second.insert( + {5, InstStat(45, 180, 15, 155, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert( + {6, InstStat(133, 452, 54, 377, 91, 1, clockPeriod)}); + cpi.find(1)->second.insert( + {8, InstStat(34, 140, 10, 146, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert( + {7, InstStat(120, 236, 86, 260, 0, 1, clockPeriod)}); + cpi.find(2)->second.insert({0, InstStat(8, 88, 17, 27, 0, 1, clockPeriod)}); + cpi.find(2)->second.insert({1, InstStat(8, 88, 17, 27, 0, 1, clockPeriod)}); + cpi.find(2)->second.insert({2, InstStat(5, 40, 6, 12, 0, 0, clockPeriod)}); + cpi.find(2)->second.insert({3, InstStat(5, 40, 6, 12, 0, 0, clockPeriod)}); + cpi.find(2)->second.insert({4, InstStat(5, 40, 6, 12, 0, 0, clockPeriod)}); + cpi.find(3)->second.insert( + {0, InstStat(90, 532, 64, 284, 0, 1, clockPeriod)}); + cpi.find(3)->second.insert( + {1, InstStat(82, 496, 53, 312, 0, 5, clockPeriod)}); + cpi.find(3)->second.insert({2, InstStat(22, 120, 20, 59, 0, 2, clockPeriod)}); + cpi.find(3)->second.insert({3, InstStat(22, 120, 20, 61, 0, 2, clockPeriod)}); + cpi.find(3)->second.insert({4, InstStat(9, 72, 12, 86, 0, 1, clockPeriod)}); + cpi.find(4)->second.insert( + {0, InstStat(61, 312, 102, 120, 0, 2, clockPeriod)}); + cpi.find(4)->second.insert( + {1, InstStat(61, 312, 102, 120, 0, 2, clockPeriod)}); + cpi.find(4)->second.insert({2, InstStat(27, 100, 27, 49, 0, 1, clockPeriod)}); + cpi.find(5)->second.insert( + {14, InstStat(44, 164, 32, 68, 0, 2, clockPeriod)}); + cpi.find(5)->second.insert({13, InstStat(0, 0, 0, 0, 0, 0, clockPeriod)}); + cpi.find(5)->second.insert( + {16, InstStat(136, 360, 65, 230, 0, 3, clockPeriod)}); + cpi.find(5)->second.insert( + {15, InstStat(54, 140, 36, 91, 0, 8, clockPeriod)}); + cpi.find(5)->second.insert({11, InstStat(0, 0, 0, 0, 0, 0, clockPeriod)}); + cpi.find(5)->second.insert({12, InstStat(0, 0, 0, 0, 0, 0, clockPeriod)}); + cpi.find(6)->second.insert( + {17, InstStat(41, 168, 42, 75, 0, 1, clockPeriod)}); + cpi.find(6)->second.insert( + {0, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(6)->second.insert( + {1, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(7)->second.insert( + {18, InstStat(44, 152, 35, 78, 0, 2, clockPeriod)}); + cpi.find(7)->second.insert( + {0, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(7)->second.insert( + {1, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(8)->second.insert( + {19, InstStat(119, 220, 45, 160, 0, 6, clockPeriod)}); + cpi.find(8)->second.insert({20, InstStat(4, 40, 14, 110, 0, 1, clockPeriod)}); + cpi.find(8)->second.insert( + {21, InstStat(70, 200, 42, 161, 0, 1, clockPeriod)}); + cpi.find(9)->second.insert({19, InstStat(27, 44, 5, 37, 0, 0, clockPeriod)}); + cpi.find(9)->second.insert( + {0, InstStat(82, 292, 42, 128, 0, 4, clockPeriod)}); + cpi.find(9)->second.insert( + {1, InstStat(86, 304, 47, 141, 0, 3, clockPeriod)}); + cpi.find(9)->second.insert({2, InstStat(51, 124, 28, 78, 0, 3, clockPeriod)}); + cpi.find(9)->second.insert( + {22, InstStat(131, 364, 71, 200, 0, 7, clockPeriod)}); + cpi.find(10)->second.insert( + {19, InstStat(155, 100, 12, 208, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {0, InstStat(93, 284, 60, 146, 0, 5, clockPeriod)}); + cpi.find(10)->second.insert( + {1, InstStat(95, 276, 60, 150, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {22, InstStat(119, 328, 76, 186, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {5, InstStat(54, 172, 69, 89, 0, 1, clockPeriod)}); + cpi.find(10)->second.insert( + {6, InstStat(72, 236, 77, 141, 0, 3, clockPeriod)}); + cpi.find(10)->second.insert( + {7, InstStat(68, 204, 77, 116, 0, 1, clockPeriod)}); + cpi.find(10)->second.insert( + {20, InstStat(65, 388, 63, 303, 0, 1, clockPeriod)}); + cpi.find(10)->second.insert( + {23, InstStat(128, 368, 76, 204, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {24, InstStat(128, 384, 81, 209, 0, 6, clockPeriod)}); + cpi.find(10)->second.insert( + {25, InstStat(69, 184, 43, 112, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {26, InstStat(206, 692, 157, 315, 0, 5, clockPeriod)}); + cpi.find(10)->second.insert( + {27, InstStat(183, 620, 154, 284, 0, 6, clockPeriod)}); + cpi.find(10)->second.insert( + {28, InstStat(162, 460, 78, 227, 0, 4, clockPeriod)}); + cpi.find(11)->second.insert( + {29, InstStat(51, 132, 40, 97, 0, 0, clockPeriod)}); + cpi.find(11)->second.insert( + {30, InstStat(212, 460, 117, 491, 0, 9, clockPeriod)}); + cpi.find(11)->second.insert( + {31, InstStat(42, 172, 43, 74, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert( + {32, InstStat(42, 172, 43, 74, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert({0, InstStat(29, 76, 17, 51, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert({1, InstStat(29, 76, 17, 51, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert({2, InstStat(25, 64, 18, 44, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {19, InstStat(157, 352, 69, 178, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {31, InstStat(42, 172, 43, 73, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {32, InstStat(42, 172, 43, 73, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {0, InstStat(28, 84, 23, 119, 0, 0, clockPeriod)}); + cpi.find(12)->second.insert( + {1, InstStat(28, 84, 23, 120, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert({2, InstStat(25, 64, 18, 44, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {33, InstStat(57, 212, 36, 128, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {34, InstStat(34, 116, 29, 72, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert({35, InstStat(16, 64, 9, 38, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {36, InstStat(28, 72, 15, 48, 0, 2, clockPeriod)}); + cpi.find(12)->second.insert( + {37, InstStat(57, 212, 36, 127, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {38, InstStat(34, 128, 31, 68, 0, 2, clockPeriod)}); + cpi.find(12)->second.insert( + {39, InstStat(18, 56, 10, 37, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {40, InstStat(33, 100, 17, 61, 0, 3, clockPeriod)}); +} + +CPU::~CPU() {} + +void CPU::calculatePower(Power &power) { + // Print stats before die + ParseXML param; + uint64_t simCycle = (getTick() - lastResetStat) / clockPeriod; + uint32_t totalCore = hilCore.size() + iclCore.size() + ftlCore.size(); + uint32_t coreIdx = 0; + + param.initialize(); + + // system + { + param.sys.number_of_L1Directories = 0; + param.sys.number_of_L2Directories = 0; + param.sys.number_of_L2s = 1; + param.sys.Private_L2 = 0; + param.sys.number_of_L3s = 0; + param.sys.number_of_NoCs = 0; + param.sys.homogeneous_cores = 0; + param.sys.homogeneous_L2s = 1; + param.sys.homogeneous_L1Directories = 1; + param.sys.homogeneous_L2Directories = 1; + param.sys.homogeneous_L3s = 1; + param.sys.homogeneous_ccs = 1; + param.sys.homogeneous_NoCs = 1; + param.sys.core_tech_node = 40; + param.sys.target_core_clockrate = clockSpeed / 1000000; + param.sys.temperature = 340; + param.sys.number_cache_levels = 2; + param.sys.interconnect_projection_type = 1; + param.sys.device_type = 0; + param.sys.longer_channel_device = 1; + param.sys.Embedded = 1; + param.sys.opt_clockrate = 1; + param.sys.machine_bits = 64; + param.sys.virtual_address_width = 48; + param.sys.physical_address_width = 48; + param.sys.virtual_memory_page_size = 4096; + param.sys.total_cycles = simCycle; + param.sys.number_of_cores = totalCore; + } + + // Now, we are using heterogeneous cores + for (coreIdx = 0; coreIdx < totalCore; coreIdx++) { + // system.core + { + param.sys.core[coreIdx].clock_rate = param.sys.target_core_clockrate; + param.sys.core[coreIdx].opt_local = 0; + param.sys.core[coreIdx].instruction_length = 32; + param.sys.core[coreIdx].opcode_width = 7; + param.sys.core[coreIdx].x86 = 0; + param.sys.core[coreIdx].micro_opcode_width = 8; + param.sys.core[coreIdx].machine_type = 0; + param.sys.core[coreIdx].number_hardware_threads = 1; + param.sys.core[coreIdx].fetch_width = 2; + param.sys.core[coreIdx].number_instruction_fetch_ports = 1; + param.sys.core[coreIdx].decode_width = 2; + param.sys.core[coreIdx].issue_width = 4; + param.sys.core[coreIdx].peak_issue_width = 7; + param.sys.core[coreIdx].commit_width = 4; + param.sys.core[coreIdx].fp_issue_width = 1; + param.sys.core[coreIdx].prediction_width = 0; + param.sys.core[coreIdx].pipelines_per_core[0] = 1; + param.sys.core[coreIdx].pipelines_per_core[1] = 1; + param.sys.core[coreIdx].pipeline_depth[0] = 8; + param.sys.core[coreIdx].pipeline_depth[1] = 8; + param.sys.core[coreIdx].ALU_per_core = 3; + param.sys.core[coreIdx].MUL_per_core = 1; + param.sys.core[coreIdx].FPU_per_core = 1; + param.sys.core[coreIdx].instruction_buffer_size = 32; + param.sys.core[coreIdx].decoded_stream_buffer_size = 16; + param.sys.core[coreIdx].instruction_window_scheme = 0; + param.sys.core[coreIdx].instruction_window_size = 20; + param.sys.core[coreIdx].fp_instruction_window_size = 15; + param.sys.core[coreIdx].ROB_size = 0; + param.sys.core[coreIdx].archi_Regs_IRF_size = 32; + param.sys.core[coreIdx].archi_Regs_FRF_size = 32; + param.sys.core[coreIdx].phy_Regs_IRF_size = 64; + param.sys.core[coreIdx].phy_Regs_FRF_size = 64; + param.sys.core[coreIdx].rename_scheme = 0; + param.sys.core[coreIdx].checkpoint_depth = 1; + param.sys.core[coreIdx].register_windows_size = 0; + strcpy(param.sys.core[coreIdx].LSU_order, "inorder"); + param.sys.core[coreIdx].store_buffer_size = 4; + param.sys.core[coreIdx].load_buffer_size = 0; + param.sys.core[coreIdx].memory_ports = 1; + param.sys.core[coreIdx].RAS_size = 0; + param.sys.core[coreIdx].number_of_BPT = 2; + param.sys.core[coreIdx].number_of_BTB = 2; + } + + // system.core.itlb + param.sys.core[coreIdx].itlb.number_entries = 64; + + // system.core.icache + { + param.sys.core[coreIdx].icache.icache_config[0] = 32768; + param.sys.core[coreIdx].icache.icache_config[1] = 8; + param.sys.core[coreIdx].icache.icache_config[2] = 4; + param.sys.core[coreIdx].icache.icache_config[3] = 1; + param.sys.core[coreIdx].icache.icache_config[4] = 10; + param.sys.core[coreIdx].icache.icache_config[5] = 10; + param.sys.core[coreIdx].icache.icache_config[6] = 32; + param.sys.core[coreIdx].icache.icache_config[7] = 0; + param.sys.core[coreIdx].icache.buffer_sizes[0] = 4; + param.sys.core[coreIdx].icache.buffer_sizes[1] = 4; + param.sys.core[coreIdx].icache.buffer_sizes[2] = 4; + param.sys.core[coreIdx].icache.buffer_sizes[3] = 0; + } + + // system.core dtlb + param.sys.core[coreIdx].dtlb.number_entries = 64; + + // system.core.dcache + { + param.sys.core[coreIdx].dcache.dcache_config[0] = 32768; + param.sys.core[coreIdx].dcache.dcache_config[1] = 8; + param.sys.core[coreIdx].dcache.dcache_config[2] = 4; + param.sys.core[coreIdx].dcache.dcache_config[3] = 1; + param.sys.core[coreIdx].dcache.dcache_config[4] = 10; + param.sys.core[coreIdx].dcache.dcache_config[5] = 10; + param.sys.core[coreIdx].dcache.dcache_config[6] = 32; + param.sys.core[coreIdx].dcache.dcache_config[7] = 0; + param.sys.core[coreIdx].dcache.buffer_sizes[0] = 4; + param.sys.core[coreIdx].dcache.buffer_sizes[1] = 4; + param.sys.core[coreIdx].dcache.buffer_sizes[2] = 4; + param.sys.core[coreIdx].dcache.buffer_sizes[3] = 4; + } + + // system.core.BTB + param.sys.core[coreIdx].BTB.BTB_config[0] = 4096; + param.sys.core[coreIdx].BTB.BTB_config[1] = 4; + param.sys.core[coreIdx].BTB.BTB_config[2] = 2; + param.sys.core[coreIdx].BTB.BTB_config[3] = 2; + param.sys.core[coreIdx].BTB.BTB_config[4] = 1; + param.sys.core[coreIdx].BTB.BTB_config[5] = 1; + } + + // system.L2 + { + param.sys.L2[0].L2_config[0] = 1048576; + param.sys.L2[0].L2_config[1] = 32; + param.sys.L2[0].L2_config[2] = 8; + param.sys.L2[0].L2_config[3] = 8; + param.sys.L2[0].L2_config[4] = 8; + param.sys.L2[0].L2_config[5] = 23; + param.sys.L2[0].L2_config[6] = 32; + param.sys.L2[0].L2_config[7] = 1; + param.sys.L2[0].buffer_sizes[0] = 16; + param.sys.L2[0].buffer_sizes[1] = 16; + param.sys.L2[0].buffer_sizes[2] = 16; + param.sys.L2[0].buffer_sizes[3] = 16; + param.sys.L2[0].clockrate = param.sys.target_core_clockrate; + param.sys.L2[0].ports[0] = 1; + param.sys.L2[0].ports[1] = 1; + param.sys.L2[0].ports[2] = 1; + param.sys.L2[0].device_type = 0; + } + + // Etcetera + param.sys.mc.req_window_size_per_channel = 32; + + // Apply stat values + + // Core stat + coreIdx = 0; + + for (auto &core : hilCore) { + CoreStat &stat = core.getStat(); + + param.sys.core[coreIdx].total_instructions = stat.instStat.sum(); + param.sys.core[coreIdx].int_instructions = stat.instStat.arithmetic; + param.sys.core[coreIdx].fp_instructions = stat.instStat.floatingPoint; + param.sys.core[coreIdx].branch_instructions = stat.instStat.branch; + param.sys.core[coreIdx].load_instructions = stat.instStat.load; + param.sys.core[coreIdx].store_instructions = stat.instStat.store; + param.sys.core[coreIdx].busy_cycles = stat.busy / clockPeriod; + + coreIdx++; + } + + for (auto &core : iclCore) { + CoreStat &stat = core.getStat(); + + param.sys.core[coreIdx].total_instructions = stat.instStat.sum(); + param.sys.core[coreIdx].int_instructions = stat.instStat.arithmetic; + param.sys.core[coreIdx].fp_instructions = stat.instStat.floatingPoint; + param.sys.core[coreIdx].branch_instructions = stat.instStat.branch; + param.sys.core[coreIdx].load_instructions = stat.instStat.load; + param.sys.core[coreIdx].store_instructions = stat.instStat.store; + param.sys.core[coreIdx].busy_cycles = stat.busy / clockPeriod; + + coreIdx++; + } + + for (auto &core : ftlCore) { + CoreStat &stat = core.getStat(); + + param.sys.core[coreIdx].total_instructions = stat.instStat.sum(); + param.sys.core[coreIdx].int_instructions = stat.instStat.arithmetic; + param.sys.core[coreIdx].fp_instructions = stat.instStat.floatingPoint; + param.sys.core[coreIdx].branch_instructions = stat.instStat.branch; + param.sys.core[coreIdx].load_instructions = stat.instStat.load; + param.sys.core[coreIdx].store_instructions = stat.instStat.store; + param.sys.core[coreIdx].busy_cycles = stat.busy / clockPeriod; + + coreIdx++; + }; + + for (coreIdx = 0; coreIdx < totalCore; coreIdx++) { + param.sys.core[coreIdx].total_cycles = simCycle; + param.sys.core[coreIdx].idle_cycles = + simCycle - param.sys.core[coreIdx].busy_cycles; + param.sys.core[coreIdx].committed_instructions = + param.sys.core[coreIdx].total_instructions; + param.sys.core[coreIdx].committed_int_instructions = + param.sys.core[coreIdx].int_instructions; + param.sys.core[coreIdx].committed_fp_instructions = + param.sys.core[coreIdx].fp_instructions; + param.sys.core[coreIdx].pipeline_duty_cycle = 1; + param.sys.core[coreIdx].IFU_duty_cycle = 0.9; + param.sys.core[coreIdx].BR_duty_cycle = 0.72; + param.sys.core[coreIdx].LSU_duty_cycle = 0.71; + param.sys.core[coreIdx].MemManU_I_duty_cycle = 0.9; + param.sys.core[coreIdx].MemManU_D_duty_cycle = 0.71; + param.sys.core[coreIdx].ALU_duty_cycle = 0.76; + param.sys.core[coreIdx].MUL_duty_cycle = 0.82; + param.sys.core[coreIdx].FPU_duty_cycle = 0.0; + param.sys.core[coreIdx].ALU_cdb_duty_cycle = 0.76; + param.sys.core[coreIdx].MUL_cdb_duty_cycle = 0.82; + param.sys.core[coreIdx].FPU_cdb_duty_cycle = 0.0; + param.sys.core[coreIdx].ialu_accesses = param.sys.core[0].int_instructions; + param.sys.core[coreIdx].fpu_accesses = param.sys.core[0].fp_instructions; + param.sys.core[coreIdx].mul_accesses = + param.sys.core[0].int_instructions * .5; + param.sys.core[coreIdx].int_regfile_reads = + param.sys.core[0].load_instructions; + param.sys.core[coreIdx].float_regfile_reads = + param.sys.core[coreIdx].fp_instructions * .4; + param.sys.core[coreIdx].int_regfile_writes = + param.sys.core[0].store_instructions; + param.sys.core[coreIdx].float_regfile_writes = + param.sys.core[coreIdx].fp_instructions * .4; + + // L1i and L1d + { + auto &core = param.sys.core[coreIdx]; + + core.icache.total_accesses = core.load_instructions * .3; + core.icache.total_hits = core.icache.total_accesses * .7; + core.icache.total_misses = core.icache.total_accesses * .3; + core.icache.read_accesses = core.icache.total_accesses; + core.icache.read_hits = core.icache.total_hits; + core.icache.read_misses = core.icache.total_misses; + core.itlb.total_accesses = core.load_instructions * .2; + core.itlb.total_hits = core.itlb.total_accesses * .8; + core.itlb.total_misses = core.itlb.total_accesses * .2; + + core.dcache.total_accesses = core.load_instructions * .4; + core.dcache.total_hits = core.dcache.total_accesses * .4; + core.dcache.total_misses = core.dcache.total_accesses * .6; + core.dcache.read_accesses = core.dcache.total_accesses * .6; + core.dcache.read_hits = core.dcache.total_hits * .6; + core.dcache.read_misses = core.dcache.total_misses * .6; + core.dcache.write_accesses = core.dcache.total_accesses * .4; + core.dcache.write_hits = core.dcache.total_hits * .4; + core.dcache.write_misses = core.dcache.total_misses * .4; + core.dcache.write_backs = core.dcache.total_misses * .4; + core.dtlb.total_accesses = core.load_instructions * .2; + core.dtlb.total_hits = core.itlb.total_accesses * .8; + core.dtlb.total_misses = core.itlb.total_accesses * .2; + } + } + + // L2 + param.sys.L2[0].duty_cycle = 1.; + + if (param.sys.number_of_L2s > 0) { + auto &L2 = param.sys.L2[0]; + + L2.total_accesses = param.sys.core[0].dcache.write_backs; + L2.total_hits = L2.total_accesses * .4; + L2.total_misses = L2.total_accesses * .6; + L2.read_accesses = L2.total_accesses * .5; + L2.read_hits = L2.total_hits * .5; + L2.read_misses = L2.total_misses * .5; + L2.write_accesses = L2.total_accesses * .5; + L2.write_hits = L2.total_hits * .5; + L2.write_misses = L2.total_misses * .5; + L2.write_backs = L2.total_misses * .4; + } + else { + param.sys.L2[0].total_accesses = 0; + param.sys.L2[0].total_hits = 0; + param.sys.L2[0].total_misses = 0; + param.sys.L2[0].read_accesses = 0; + param.sys.L2[0].read_hits = 0; + param.sys.L2[0].read_misses = 0; + param.sys.L2[0].write_accesses = 0; + param.sys.L2[0].write_hits = 0; + param.sys.L2[0].write_misses = 0; + param.sys.L2[0].write_backs = 0; + } + + // L3 + param.sys.L3[0].duty_cycle = 1.; + + if (param.sys.number_of_L3s > 0) { + auto &L3 = param.sys.L3[0]; + + L3.total_accesses = param.sys.L2[0].write_backs; + L3.total_hits = L3.total_accesses * .4; + L3.total_misses = L3.total_accesses * .6; + L3.read_accesses = L3.total_accesses * .5; + L3.read_hits = L3.total_hits * .5; + L3.read_misses = L3.total_misses * .5; + L3.write_accesses = L3.total_accesses * .5; + L3.write_hits = L3.total_hits * .5; + L3.write_misses = L3.total_misses * .5; + L3.write_backs = L3.total_misses * .4; + } + else { + param.sys.L3[0].total_accesses = 0; + param.sys.L3[0].total_hits = 0; + param.sys.L3[0].total_misses = 0; + param.sys.L3[0].read_accesses = 0; + param.sys.L3[0].read_hits = 0; + param.sys.L3[0].read_misses = 0; + param.sys.L3[0].write_accesses = 0; + param.sys.L3[0].write_hits = 0; + param.sys.L3[0].write_misses = 0; + param.sys.L3[0].write_backs = 0; + } + + McPAT mcpat(¶m); + + mcpat.getPower(power); +} + +uint32_t CPU::leastBusyCPU(std::vector &list) { + uint32_t idx = list.size(); + uint64_t busymin = std::numeric_limits::max(); + + for (uint32_t i = 0; i < list.size(); i++) { + auto &core = list.at(i); + auto busy = core.getStat().busy; + + if (!core.isBusy() && busy < busymin) { + busymin = busy; + idx = i; + } + } + + if (idx == list.size()) { + uint64_t jobmin = std::numeric_limits::max(); + + for (uint32_t i = 0; i < list.size(); i++) { + auto jobs = list.at(i).getJobListSize(); + + if (jobs <= jobmin) { + jobmin = jobs; + idx = i; + } + } + } + + return idx; +} + +void CPU::execute(NAMESPACE ns, FUNCTION fct, DMAFunction &func, void *context, + uint64_t delay) { + Core *pCore = nullptr; + + // Find dedicated core + switch (ns) { + case FTL: + case FTL__PAGE_MAPPING: + if (ftlCore.size() > 0) { + pCore = &ftlCore.at(leastBusyCPU(ftlCore)); + } + + break; + case ICL: + case ICL__GENERIC_CACHE: + if (iclCore.size() > 0) { + pCore = &iclCore.at(leastBusyCPU(iclCore)); + } + + break; + case HIL: + case NVME__CONTROLLER: + case NVME__PRPLIST: + case NVME__SGL: + case NVME__SUBSYSTEM: + case NVME__NAMESPACE: + case NVME__OCSSD: + case UFS__DEVICE: + case SATA__DEVICE: + if (hilCore.size() > 0) { + pCore = &hilCore.at(leastBusyCPU(hilCore)); + } + + break; + default: + panic("Undefined function namespace %u", ns); + + break; + } + + if (pCore) { + // Get CPI table + auto table = cpi.find(ns); + + if (table == cpi.end()) { + panic("Namespace %u not defined in CPI table", ns); + } + + // Get CPI + auto inst = table->second.find(fct); + + if (inst == table->second.end()) { + panic("Namespace %u does not have function %u", ns, fct); + } + + pCore->submitJob(JobEntry(func, context, &inst->second), delay); + } + else { + func(getTick(), context); + } +} + +uint64_t CPU::applyLatency(NAMESPACE ns, FUNCTION fct) { + Core *pCore = nullptr; + + // Find dedicated core + switch (ns) { + case FTL: + case FTL__PAGE_MAPPING: + if (ftlCore.size() > 0) { + pCore = &ftlCore.at(leastBusyCPU(ftlCore)); + } + + break; + case ICL: + case ICL__GENERIC_CACHE: + if (iclCore.size() > 0) { + pCore = &iclCore.at(leastBusyCPU(iclCore)); + } + + break; + case HIL: + case NVME__CONTROLLER: + case NVME__PRPLIST: + case NVME__SGL: + case NVME__SUBSYSTEM: + case NVME__NAMESPACE: + case NVME__OCSSD: + case UFS__DEVICE: + case SATA__DEVICE: + if (hilCore.size() > 0) { + pCore = &hilCore.at(leastBusyCPU(hilCore)); + } + + break; + default: + panic("Undefined function namespace %u", ns); + + break; + } + + if (pCore) { + // Get CPI table + auto table = cpi.find(ns); + + if (table == cpi.end()) { + panic("Namespace %u not defined in CPI table", ns); + } + + // Get CPI + auto inst = table->second.find(fct); + + if (inst == table->second.end()) { + panic("Namespace %u does not have function %u", ns, fct); + } + + pCore->addStat(inst->second); + + return inst->second.latency; + } + + return 0; +} + +void CPU::getStatList(std::vector &list, std::string prefix) { + Stats temp; + std::string number; + + for (uint32_t i = 0; i < hilCore.size(); i++) { + number = std::to_string(i); + + temp.name = prefix + ".hil" + number + ".busy"; + temp.desc = "CPU for HIL core " + number + " busy ticks"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.branch"; + temp.desc = "CPU for HIL core " + number + " executed branch instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.load"; + temp.desc = "CPU for HIL core " + number + " executed load instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.store"; + temp.desc = "CPU for HIL core " + number + " executed store instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.arithmetic"; + temp.desc = + "CPU for HIL core " + number + " executed arithmetic instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.fp"; + temp.desc = + "CPU for HIL core " + number + " executed floating point instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.others"; + temp.desc = "CPU for HIL core " + number + " executed other instructions"; + list.push_back(temp); + } + + for (uint32_t i = 0; i < iclCore.size(); i++) { + number = std::to_string(i); + + temp.name = prefix + ".icl" + number + ".busy"; + temp.desc = "CPU for ICL core " + number + " busy ticks"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.branch"; + temp.desc = "CPU for ICL core " + number + " executed branch instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.load"; + temp.desc = "CPU for ICL core " + number + " executed load instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.store"; + temp.desc = "CPU for ICL core " + number + " executed store instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.arithmetic"; + temp.desc = + "CPU for ICL core " + number + " executed arithmetic instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.fp"; + temp.desc = + "CPU for ICL core " + number + " executed floating point instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.others"; + temp.desc = "CPU for ICL core " + number + " executed other instructions"; + list.push_back(temp); + } + + for (uint32_t i = 0; i < ftlCore.size(); i++) { + number = std::to_string(i); + + temp.name = prefix + ".ftl" + number + ".busy"; + temp.desc = "CPU for FTL core " + number + " busy ticks"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.branch"; + temp.desc = "CPU for FTL core " + number + " executed branch instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.load"; + temp.desc = "CPU for FTL core " + number + " executed store instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.store"; + temp.desc = "CPU for FTL core " + number + " executed load instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.arithmetic"; + temp.desc = + "CPU for FTL core " + number + " executed arithmetic instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.fp"; + temp.desc = + "CPU for FTL core " + number + " executed floating point instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.others"; + temp.desc = "CPU for FTL core " + number + " executed other instructions"; + list.push_back(temp); + } +} + +void CPU::getStatValues(std::vector &values) { + for (auto &core : hilCore) { + auto &stat = core.getStat(); + + values.push_back(stat.busy); + values.push_back(stat.instStat.branch); + values.push_back(stat.instStat.load); + values.push_back(stat.instStat.store); + values.push_back(stat.instStat.arithmetic); + values.push_back(stat.instStat.floatingPoint); + values.push_back(stat.instStat.otherInsts); + } + + for (auto &core : iclCore) { + auto &stat = core.getStat(); + + values.push_back(stat.busy); + values.push_back(stat.instStat.branch); + values.push_back(stat.instStat.load); + values.push_back(stat.instStat.store); + values.push_back(stat.instStat.arithmetic); + values.push_back(stat.instStat.floatingPoint); + values.push_back(stat.instStat.otherInsts); + } + + for (auto &core : ftlCore) { + auto &stat = core.getStat(); + + values.push_back(stat.busy); + values.push_back(stat.instStat.branch); + values.push_back(stat.instStat.load); + values.push_back(stat.instStat.store); + values.push_back(stat.instStat.arithmetic); + values.push_back(stat.instStat.floatingPoint); + values.push_back(stat.instStat.otherInsts); + } +} + +void CPU::resetStatValues() { + lastResetStat = getTick(); + + for (auto &core : hilCore) { + auto &stat = core.getStat(); + + stat.busy = 0; + stat.instStat = InstStat(); + } + + for (auto &core : iclCore) { + auto &stat = core.getStat(); + + stat.busy = 0; + stat.instStat = InstStat(); + } + + for (auto &core : ftlCore) { + auto &stat = core.getStat(); + + stat.busy = 0; + stat.instStat = InstStat(); + } +} + +void CPU::printLastStat() { + Power power; + + debugprint(LOG_CPU, "Begin CPU power calculation"); + + calculatePower(power); + + debugprint(LOG_CPU, "Core:"); + debugprint(LOG_CPU, " Area: %lf mm^2", power.core.area); + debugprint(LOG_CPU, " Peak Dynamic: %lf W", power.core.peakDynamic); + debugprint(LOG_CPU, " Subthreshold Leakage: %lf W", + power.core.subthresholdLeakage); + debugprint(LOG_CPU, " Gate Leakage: %lf W", power.core.gateLeakage); + debugprint(LOG_CPU, " Runtime Dynamic: %lf W", power.core.runtimeDynamic); + + if (power.level2.area > 0.0) { + debugprint(LOG_CPU, "L2:"); + debugprint(LOG_CPU, " Area: %lf mm^2", power.level2.area); + debugprint(LOG_CPU, " Peak Dynamic: %lf W", power.level2.peakDynamic); + debugprint(LOG_CPU, " Subthreshold Leakage: %lf W", + power.level2.subthresholdLeakage); + debugprint(LOG_CPU, " Gate Leakage: %lf W", power.level2.gateLeakage); + debugprint(LOG_CPU, " Runtime Dynamic: %lf W", + power.level2.runtimeDynamic); + } + + if (power.level3.area > 0.0) { + debugprint(LOG_CPU, "L3:"); + debugprint(LOG_CPU, " Area: %lf mm^2", power.level3.area); + debugprint(LOG_CPU, " Peak Dynamic: %lf W", power.level3.peakDynamic); + debugprint(LOG_CPU, " Subthreshold Leakage: %lf W", + power.level3.subthresholdLeakage); + debugprint(LOG_CPU, " Gate Leakage: %lf W", power.level3.gateLeakage); + debugprint(LOG_CPU, " Runtime Dynamic: %lf W", + power.level3.runtimeDynamic); + } +} + +} // namespace CPU + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/cpu.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/cpu.hh new file mode 100644 index 0000000000..c1f7c2ebf6 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/cpu.hh @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __CPU_CPU__ +#define __CPU_CPU__ + +#include +#include +#include +#include + +#include "cpu/def.hh" +#include "lib/mcpat/mcpat.h" +#include "sim/config_reader.hh" +#include "sim/dma_interface.hh" +#include "sim/simulator.hh" +#include "sim/statistics.hh" + +namespace SimpleSSD { + +namespace CPU { + +typedef struct _InstStat { + // Instruction count + uint64_t branch; + uint64_t load; + uint64_t store; + uint64_t arithmetic; + uint64_t floatingPoint; + uint64_t otherInsts; + + // Total times in ps to execute this insturcion group + uint64_t latency; + + _InstStat(); + _InstStat(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, + uint64_t); + _InstStat &operator+=(const _InstStat &); + uint64_t sum(); +} InstStat; + +typedef struct _JobEntry { + DMAFunction func; + void *context; + InstStat *inst; + uint64_t submitAt; + uint64_t delay; + + _JobEntry(DMAFunction &, void *, InstStat *); +} JobEntry; + +class CPU : public StatObject { + private: + struct CoreStat { + InstStat instStat; + uint64_t busy; + + CoreStat(); + }; + + class Core { + private: + bool busy; + + Event jobEvent; + std::queue jobs; + + CoreStat stat; + + void handleJob(); + void jobDone(); + + public: + Core(); + ~Core(); + + void submitJob(JobEntry, uint64_t = 0); + + void addStat(InstStat &); + + bool isBusy(); + uint64_t getJobListSize(); + CoreStat &getStat(); + }; + + ConfigReader &conf; + uint64_t lastResetStat; + + uint64_t clockSpeed; + uint64_t clockPeriod; + + // Cores + std::vector hilCore; + std::vector iclCore; + std::vector ftlCore; + + // CPIs + std::unordered_map> cpi; + + uint32_t leastBusyCPU(std::vector &); + void calculatePower(Power &); + + public: + CPU(ConfigReader &); + ~CPU(); + + void execute(NAMESPACE, FUNCTION, DMAFunction &, void * = nullptr, + uint64_t = 0); + uint64_t applyLatency(NAMESPACE, FUNCTION); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; + + void printLastStat(); +}; + +} // namespace CPU + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/def.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/def.hh new file mode 100644 index 0000000000..ad552cf16d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/def.hh @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __CPU_DEF__ +#define __CPU_DEF__ + +#include + +namespace SimpleSSD { + +namespace CPU { + +typedef enum : uint16_t { + FTL, + FTL__PAGE_MAPPING, + ICL, + ICL__GENERIC_CACHE, + HIL, + NVME__CONTROLLER, + NVME__PRPLIST, + NVME__SGL, + NVME__SUBSYSTEM, + NVME__NAMESPACE, + NVME__OCSSD, + UFS__DEVICE, + SATA__DEVICE, +} NAMESPACE; + +typedef enum : uint16_t { + // Common + READ, + WRITE, + FLUSH, + TRIM, + FORMAT, + + // FTL__PAGE_MAPPING + READ_INTERNAL, + WRITE_INTERNAL, + ERASE_INTERNAL, + TRIM_INTERNAL, + SELECT_VICTIM_BLOCK, + DO_GARBAGE_COLLECTION, + + // NVME__CONTROLLER / NVME__SUBSYSTEM + CREATE_CQ, + CREATE_SQ, + + // NVME__CONTROLLER + COLLECT_SQ, + HANDLE_REQUEST, + WORK, + COMPLETION, + + // NVME__PRPLIST + GET_PRPLIST_FROM_PRP, + + // NVME__SGL + PARSE_SGL_SEGMENT, + + // NVME__SUBSYSTEM / NVME__NAMESPACE + SUBMIT_COMMAND, + + // NVME__SUBSYSTEM + CONVERT_UNIT, + FORMAT_NVM, + + // NVME__NAMESPACE + DATASET_MANAGEMENT, + + // NVME__OCSSD + VECTOR_CHUNK_READ, + VECTOR_CHUNK_WRITE, + VECTOR_CHUNK_RESET, + PHYSICAL_PAGE_READ, + PHYSICAL_PAGE_WRITE, + PHYSICAL_BLOCK_ERASE, + + // UFS__DEVICE + PROCESS_QUERY_COMMAND, + PROCESS_COMMAND, + PRDT_READ, + PRDT_WRITE, + + // SATA__DEVICE + READ_DMA, + READ_NCQ, + READ_DMA_SETUP, + READ_DMA_DONE, + WRITE_DMA, + WRITE_NCQ, + WRITE_DMA_SETUP, + WRITE_DMA_DONE, +} FUNCTION; + +} // namespace CPU + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/analyse.py b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/analyse.py new file mode 100644 index 0000000000..571d14483f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/analyse.py @@ -0,0 +1,86 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +import re +from insts import aarch64 + +asmregex = re.compile('[0-9a-f ]+:\t[0-9a-f ]+\t([\w\.]+)') +endregex = re.compile('[0-9a-f]{16} <') + + +def decode(line): + match = asmregex.match(line) + + if match: + return match.group(1) + + return '' + + +def categorize(opstring): + for list in aarch64: + regex = re.compile(list[0], re.IGNORECASE) + match = regex.match(opstring) + + if match: + if match.group(0) == opstring: + return [True, list[1], list[2]] + + return [False, 1, 0] + + +def matchFunction(line, funcstr): + match = endregex.match(line) + + if match: + if line.find(funcstr) >= 0: + return 1 + else: + return 2 + else: + return 0 + + +def analyse(asmfile, funcname): + category = [0, 0, 0, 0, 0, 0] + funcstr = str(len(funcname)) + funcname + + with open(asmfile, 'r') as f: + collect = False + + for line in f: + if collect: + match = matchFunction(line, funcstr) + + if match > 0: + if match == 2: + collect = False + else: + op = decode(line) + + if len(op) > 0: + ret = categorize(op) + + if not ret[0]: + print('Unknown assembly ' + op + ' found') + + category[ret[2]] += ret[1] + else: + if matchFunction(line, funcstr) == 1: + collect = True + + return category diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/compile.py b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/compile.py new file mode 100644 index 0000000000..810608d680 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/compile.py @@ -0,0 +1,61 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +import subprocess +import os + + +def compile(cxx, src, dst, rootpath): + command = [cxx, + '-std=c++11', + '-O2', + '-g', + '-I' + rootpath, + '-I' + os.path.join(rootpath, '../../../../ext/drampower/src'), + '-I' + os.path.join(rootpath, '../lib/drampower/src'), + '-c', + src, + '-o', + dst] + + proc = subprocess.Popen( + command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + + output = proc.communicate()[0] + + if proc.returncode: + print output + + return proc.returncode + + +def disassemble(objdump, src, dst): + command = [objdump, + '-S', + '-d', + src] + + proc = subprocess.Popen( + command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + + output = proc.communicate()[0] + + if proc.returncode == 0: + with open(dst, 'w') as f: + f.write(output) + + return proc.returncode diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/functions.py b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/functions.py new file mode 100644 index 0000000000..37fdc788a3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/functions.py @@ -0,0 +1,158 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# [ Filename, Regex of function name, NS code, FCT code ] +# NAMESPACE code +# 0: FTL +# 1: FTL::PageMapping +# 2: ICL +# 3: ICL::GenericCache +# 4: HIL +# 5: HIL::NVMe::Controller +# 6: HIL::NVMe::PRPList +# 7: HIL::NVMe::SGL +# 8: HIL::NVMe::Subsystem +# 9: HIL::NVMe::Namespace +# 10: HIL::NVMe::OpenChannelSSD +# 11: HIL::UFS::Device +# 12: HIL::SATA::Device +# FUNCTION code +# 0: read +# 1: write +# 2: flush +# 3: trim +# 4: format +# 5: readInternal +# 6: writeInternal +# 7: eraseInternal +# 8: trimInternal +# 9: selectVictimBlock +# 10: doGarbageCollection +# 11: createCQ +# 12: createSQ +# 13: collectSQ +# 14: handleRequest +# 15: work +# 16: completion +# 17: getPRPListFromPRP +# 18: parseSGLSegment +# 19: submitCommand +# 20: convertUnit +# 21: formatNVM +# 22: datasetManagement +# 23: vectorChunkRead +# 24: vectorChunkWrite +# 25: vectorChunkReset +# 26: physicalPageRead +# 27: physicalPageWrite +# 28: physicalBlockErase +# 29: processQueryCommand +# 30: processCommand +# 31: prdtRead +# 32: prdtWrite +# 33: readDMA +# 34: readNCQ +# 35: readDMASetup +# 36: readDMADone +# 37: writeDMA +# 38: writeNCQ +# 39: writeDMASetup +# 40: writeDMADone +function = [ + ["ftl/ftl.cc", "read", 0, 0], + ["ftl/ftl.cc", "write", 0, 1], + ["ftl/ftl.cc", "trim", 0, 3], + ["ftl/ftl.cc", "format", 0, 4], + ["ftl/page_mapping.cc", "read", 1, 0], + ["ftl/page_mapping.cc", "write", 1, 1], + ["ftl/page_mapping.cc", "trim", 1, 3], + ["ftl/page_mapping.cc", "format", 1, 4], + ["ftl/page_mapping.cc", "selectVictimBlock", 1, 9], + ["ftl/page_mapping.cc", "doGarbageCollection", 1, 10], + ["ftl/page_mapping.cc", "readInternal", 1, 5], + ["ftl/page_mapping.cc", "writeInternal", 1, 6], + ["ftl/page_mapping.cc", "trimInternal", 1, 8], + ["ftl/page_mapping.cc", "eraseInternal", 1, 7], + ["icl/icl.cc", "read", 2, 0], + ["icl/icl.cc", "write", 2, 1], + ["icl/icl.cc", "flush", 2, 2], + ["icl/icl.cc", "trim", 2, 3], + ["icl/icl.cc", "format", 2, 4], + ["icl/generic_cache.cc", "read", 3, 0], + ["icl/generic_cache.cc", "write", 3, 1], + ["icl/generic_cache.cc", "flush", 3, 2], + ["icl/generic_cache.cc", "trim", 3, 3], + ["icl/generic_cache.cc", "format", 3, 4], + ["hil/hil.cc", "read", 4, 0], + ["hil/hil.cc", "write", 4, 1], + ["hil/hil.cc", "flush", 4, 2], + ["hil/nvme/controller.cc", "handleRequest", 5, 14], + ["hil/nvme/controller.cc", "collectSQ", 5, 13], + ["hil/nvme/controller.cc", "completion", 5, 16], + ["hil/nvme/controller.cc", "work", 5, 15], + ["hil/nvme/controller.cc", "createCQ", 5, 11], + ["hil/nvme/controller.cc", "createSQ", 5, 12], + ["hil/nvme/dma.cc", "getPRPListFromPRP", 6, 17], + ["hil/nvme/dma.cc", "read", 6, 0], + ["hil/nvme/dma.cc", "write", 6, 1], + ["hil/nvme/dma.cc", "parseSGLSegment", 7, 18], + ["hil/nvme/dma.cc", "read", 7, 0], + ["hil/nvme/dma.cc", "write", 7, 1], + ["hil/nvme/subsystem.cc", "submitCommand", 8, 19], + ["hil/nvme/subsystem.cc", "convertUnit", 8, 20], + ["hil/nvme/subsystem.cc", "formatNVM", 8, 21], + ["hil/nvme/namespace.cc", "submitCommand", 9, 19], + ["hil/nvme/namespace.cc", "read", 9, 0], + ["hil/nvme/namespace.cc", "write", 9, 1], + ["hil/nvme/namespace.cc", "flush", 9, 2], + ["hil/nvme/namespace.cc", "datasetManagement", 9, 22], + ["hil/nvme/ocssd.cc", "submitCommand", 10, 19], + ["hil/nvme/ocssd.cc", "read", 10, 0], + ["hil/nvme/ocssd.cc", "write", 10, 1], + ["hil/nvme/ocssd.cc", "datasetManagement", 10, 22], + ["hil/nvme/ocssd.cc", "readInternal", 10, 5], + ["hil/nvme/ocssd.cc", "writeInternal", 10, 6], + ["hil/nvme/ocssd.cc", "eraseInternal", 10, 7], + ["hil/nvme/ocssd.cc", "convertUnit", 10, 20], + ["hil/nvme/ocssd.cc", "vectorChunkRead", 10, 23], + ["hil/nvme/ocssd.cc", "vectorChunkWrite", 10, 24], + ["hil/nvme/ocssd.cc", "vectorChunkReset", 10, 25], + ["hil/nvme/ocssd.cc", "physicalPageRead", 10, 26], + ["hil/nvme/ocssd.cc", "physicalPageWrite", 10, 27], + ["hil/nvme/ocssd.cc", "physicalBlockErase", 10, 28], + ["hil/ufs/device.cc", "processQueryCommand", 11, 29], + ["hil/ufs/device.cc", "processCommand", 11, 30], + ["hil/ufs/device.cc", "prdtRead", 11, 31], + ["hil/ufs/device.cc", "prdtWrite", 11, 32], + ["hil/ufs/device.cc", "read", 11, 0], + ["hil/ufs/device.cc", "write", 11, 1], + ["hil/ufs/device.cc", "flush", 11, 2], + ["hil/sata/device.cc", "submitCommand", 12, 19], + ["hil/sata/device.cc", "prdtRead", 12, 31], + ["hil/sata/device.cc", "prdtWrite", 12, 32], + ["hil/sata/device.cc", "read", 12, 0], + ["hil/sata/device.cc", "write", 12, 1], + ["hil/sata/device.cc", "flush", 12, 2], + ["hil/sata/device.cc", "readDMA", 12, 33], + ["hil/sata/device.cc", "readNCQ", 12, 34], + ["hil/sata/device.cc", "_readDMASetup", 12, 35], + ["hil/sata/device.cc", "_readDMADone", 12, 36], + ["hil/sata/device.cc", "writeDMA", 12, 37], + ["hil/sata/device.cc", "writeNCQ", 12, 38], + ["hil/sata/device.cc", "_writeDMASetup", 12, 39], + ["hil/sata/device.cc", "_writeDMADone", 12, 40], +] diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/generate.py b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/generate.py new file mode 100644 index 0000000000..dd6e776895 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/generate.py @@ -0,0 +1,125 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +import os +import shutil +from functions import function as funcList +from compile import compile, disassemble +from analyse import analyse + +# Begin of main +print('SimpleSSD Instruction Counter\n') + +# Find root directory of SimpleSSD +pwd = os.getcwd() +rootdir = '' + +while True: + if pwd == '/': + print('Failed to find SimpleSSD root directory') + exit(-1) + + if os.path.isdir(os.path.join(pwd, 'cpu')) and os.path.isdir(os.path.join(pwd, 'hil')): + rootdir = os.path.abspath(pwd) + break + + pwd = os.path.join(pwd, '..') + +print('SimpleSSD found on ' + rootdir) + +# Create temp directory +tempdir = os.path.join(rootdir, 'temp_build') + +if os.path.exists(tempdir): + shutil.rmtree(tempdir) + +os.mkdir(tempdir) + +if not os.path.isdir(tempdir): + print('Failed to create temp directory') + exit(-1) + +print('Temporary directory ' + tempdir + ' created') + +# Load files to compile & disassemble +result = [] +files = set() + +for func in funcList: + files.add(func[0]) + +files = list(files) + +# Compile all +print('Begin compile') + +for file in files: + path = os.path.join(rootdir, file) + filename = os.path.splitext(file.replace('/', '_'))[0] + '.o' + outfile = os.path.join(tempdir, filename) + + if os.path.exists(path): + ret = compile('aarch64-linux-gnu-g++', path, outfile, rootdir) + + if ret: + print(' file ' + file + ' failed to compile') + else: + print(' file ' + file + ' not exists') + +# Disassemble all +print('Begin disassemble') + +for file in files: + path = os.path.join(rootdir, file) + filename = os.path.splitext(file.replace('/', '_'))[0] + name = os.path.join(tempdir, filename) + objfile = name + '.o' + asmfile = name + '.asm' + + if os.path.exists(objfile): + ret = disassemble('aarch64-linux-gnu-objdump', objfile, asmfile) + + if ret: + print(' file ' + file + ' failed to disassemble') + +# Analyse all +print('Begin analysis') + +for func in funcList: + path = os.path.join(rootdir, func[0]) + filename = os.path.splitext(func[0].replace('/', '_'))[0] + '.asm' + asmfile = os.path.join(tempdir, filename) + + if os.path.exists(asmfile): + insts = analyse(asmfile, func[1]) + + result.append([func[1], func[2], func[3], insts]) + else: + print('Assembly file for function ' + func[1] + ' not exists') + +# Everything is done +# Print result +template = """cpi.find({1})->second.insert( + {{{2}, InstStat({4}, {5}, {6}, {7}, {8}, {3}, clockPeriod)}});""" + +for data in result: + print(template.format(data[0], data[1], data[2], + data[3][0], data[3][1], data[3][2], + data[3][3], data[3][4], data[3][5])) + +# Remove temp directory +shutil.rmtree(tempdir) diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/insts.py b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/insts.py new file mode 100644 index 0000000000..40db8c98c8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/cpu/generator/insts.py @@ -0,0 +1,160 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# [ Regex of instruction, CPI, TYPE ] +# TYPE: +# 0: Others +# 1: Branch +# 2: Load +# 3: Store +# 4: Arithmetic +# 5: FP +aarch64 = [ + ["NOP", 1, 0], + ["CAS[B|H|P|]", 1, 0], + ["SWP[B|H|]", 1, 0], + # Branch + ["B\.(EQ|NE|CS|HS|CC|LO|MI|PL|VS|VC|HI|LS|GE|LT|GT|LE|AL|NV)", 1, 1], + ["CBN?Z", 1, 1], + ["TBN?Z", 1, 1], + ["B", 1, 1], + ["BL", 1, 1], + ["BLR", 2, 1], + ["BR", 1, 1], + ["RET", 1, 1], + # Load + ["LDR(B|SB|H|SH|SW|)", 4, 2], + ["LDUR(B|SB|H|SH|SW|)", 4, 2], + ["LDP(SW|)", 4, 2], + ["LDNP", 4, 2], + ["LDTR(B|SB|H|SH|SW|)", 4, 2], + ["LDXR(B|H|)", 4, 2], + ["LDXP", 4, 2], + ["LDAPR(B|H|)", 4, 2], + ["LDAR(B|H|)", 4, 2], + ["LDAXR(B|H|)", 4, 2], + ["LDAXP", 4, 2], + ["LDLAR(B|H|)", 4, 2], + # Store + ["STR(B|H|)", 1, 3], + ["STUR(B|H|)", 1, 3], + ["STP", 2, 3], + ["STNP", 2, 3], + ["STTR(B|H|)", 1, 3], + ["STXR(B|H|)", 1, 3], + ["STXP", 1, 3], + ["STLR(B|H|)", 1, 3], + ["STLXR(B|H|)", 1, 3], + ["STLXP", 1, 3], + ["STLLR(B|H|)", 1, 3], + # Arithmetic + ["ADD(S|)", 1, 4], + ["SUB(S|)", 1, 4], + ["CMP", 1, 4], + ["CMN", 1, 4], + ["AND(S|)", 1, 4], + ["EOR", 1, 4], + ["ORR", 1, 4], + ["TST", 1, 4], + ["MOV(Z|N|K|)", 1, 4], + ["ADR(P|)", 1, 4], + ["BFM", 2, 4], + ["SBFM", 2, 4], + ["UBFM", 2, 4], + ["BFC", 2, 4], + ["BFI", 2, 4], + ["BFXIL", 1, 4], + ["SBFIZ", 2, 4], + ["SBFX", 1, 4], + ["UBFIZ", 2, 4], + ["UBFX", 1, 4], + ["EXTR", 1, 4], + ["ASR(V|)", 1, 4], + ["LSL(V|)", 1, 4], + ["LSR(V|)", 1, 4], + ["ROR(V|)", 1, 4], + ["SXT(B|H|W|)", 2, 4], + ["UXT(B|H|)", 2, 4], + ["NEG(S|)", 1, 4], + ["ADC(S|)", 1, 4], + ["SBC(S|)", 1, 4], + ["NGC(S|)", 1, 4], + ["BIC(S|)", 1, 4], + ["EON", 1, 4], + ["MNV", 1, 4], + ["ORN", 1, 4], + # Multiply and Divide + ["MADD", 3, 4], + ["MSUB", 3, 4], + ["MNEG", 3, 4], + ["MUL", 3, 4], + ["SMADDL", 3, 4], + ["SMSUBL", 3, 4], + ["SMNEGL", 3, 4], + ["SMULL", 3, 4], + ["SMULH", 6, 4], + ["UMADDL", 3, 4], + ["UMSUBL", 3, 4], + ["UMNEGL", 3, 4], + ["UMULL", 3, 4], + ["UMULH", 6, 4], + ["SDIV", 20, 4], + ["UDIV", 20, 4], + # Bit operation + ["CLS", 1, 4], + ["CLZ", 1, 4], + ["RBIT", 1, 4], + ["REV(16|32|64|)", 1, 4], + # Conditional select + ["CSEL", 1, 4], + ["CSINC", 1, 4], + ["CSINV", 1, 4], + ["CSNEG", 1, 4], + ["CSET(M|)", 1, 4], + ["CINC", 1, 4], + ["CINV", 1, 4], + ["CNEG", 1, 4], + # Conditional comparison + ["CCMN", 1, 4], + ["CCMP", 1, 4], + # Floating Point + ["FMOV", 5, 5], + ["FCVT(XN|)", 5, 5], + ["FCVT(AS|AU|MS|MU|NS|NU|PS|PU|ZS|ZU)", 10, 5], + ["FJCVTZS", 1, 5], + ["SCVTF", 10, 5], + ["UCVTF", 10, 5], + ["FRINT(A|I|M|N|P|X|Z|)", 5, 5], + ["FMADD", 9, 5], + ["FMSUB", 9, 5], + ["FNMADD", 9, 5], + ["FNMSUB", 9, 5], + ["FABS", 3, 5], + ["FNEG", 3, 5], + ["FSQRT", 20, 5], + ["FADD", 5, 5], + ["FDIV", 20, 5], + ["FMUL", 6, 5], + ["FNMUL", 6, 5], + ["FSUB", 5, 5], + ["FMAX", 5, 5], + ["FMAXNM", 5, 5], + ["FMIN", 5, 5], + ["FMINNM", 5, 5], + ["FCMP(E|P|PE|)", 3, 5], + ["FCSEL", 3, 5], +] diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/abstract_dram.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/abstract_dram.cc new file mode 100644 index 0000000000..1ef6db56e2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/abstract_dram.cc @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "dram/abstract_dram.hh" + +#include + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace DRAM { + +AbstractDRAM::AbstractDRAM(ConfigReader &c) + : conf(c), totalEnergy(0.0), totalPower(0.0) { + pStructure = conf.getDRAMStructure(); + pTiming = conf.getDRAMTiming(); + pPower = conf.getDRAMPower(); + + convertMemspec(); + + dramPower = new libDRAMPower(spec, false); +} + +AbstractDRAM::~AbstractDRAM() { + delete dramPower; +} + +void AbstractDRAM::convertMemspec() { + // Calculate datarate + uint32_t burstCycle = DIVCEIL(pTiming->tBURST, pTiming->tCK); + uint8_t dataRate = pStructure->burstLength / burstCycle; + + if (dataRate != 1 && dataRate != 2 && dataRate != 4) { + panic("Invalid DRAM data rate: %d", dataRate); + } + + // gem5 src/mem/drampower.cc + spec.memArchSpec.burstLength = pStructure->burstLength; + spec.memArchSpec.nbrOfBanks = pStructure->bank; + spec.memArchSpec.nbrOfRanks = pStructure->rank; + spec.memArchSpec.dataRate = dataRate; + spec.memArchSpec.nbrOfColumns = 0; + spec.memArchSpec.nbrOfRows = 0; + spec.memArchSpec.width = pStructure->busWidth; + spec.memArchSpec.nbrOfBankGroups = 0; + spec.memArchSpec.dll = pStructure->useDLL; + spec.memArchSpec.twoVoltageDomains = pPower->pVDD[1] != 0.f; + spec.memArchSpec.termination = false; + + spec.memTimingSpec.RC = DIVCEIL(pTiming->tRAS + pTiming->tRP, pTiming->tCK); + spec.memTimingSpec.RCD = DIVCEIL(pTiming->tRCD, pTiming->tCK); + spec.memTimingSpec.RL = DIVCEIL(pTiming->tCL, pTiming->tCK); + spec.memTimingSpec.RP = DIVCEIL(pTiming->tRP, pTiming->tCK); + spec.memTimingSpec.RFC = DIVCEIL(pTiming->tRFC, pTiming->tCK); + spec.memTimingSpec.RAS = DIVCEIL(pTiming->tRAS, pTiming->tCK); + spec.memTimingSpec.WL = spec.memTimingSpec.RL - 1; + spec.memTimingSpec.DQSCK = 0; + spec.memTimingSpec.RTP = DIVCEIL(pTiming->tRTP, pTiming->tCK); + spec.memTimingSpec.WR = DIVCEIL(pTiming->tWR, pTiming->tCK); + spec.memTimingSpec.XP = DIVCEIL(pTiming->tXP, pTiming->tCK); + spec.memTimingSpec.XPDLL = DIVCEIL(pTiming->tXPDLL, pTiming->tCK); + spec.memTimingSpec.XS = DIVCEIL(pTiming->tXS, pTiming->tCK); + spec.memTimingSpec.XSDLL = DIVCEIL(pTiming->tXSDLL, pTiming->tCK); + spec.memTimingSpec.clkPeriod = pTiming->tCK / 1000.; + + if (spec.memTimingSpec.clkPeriod == 0) { + panic("Invalid DRAM clock period"); + } + + spec.memTimingSpec.clkMhz = (1 / spec.memTimingSpec.clkPeriod) * 1000.; + + spec.memPowerSpec.idd0 = pPower->pIDD0[0]; + spec.memPowerSpec.idd02 = pPower->pIDD0[1]; + spec.memPowerSpec.idd2p0 = pPower->pIDD2P0[0]; + spec.memPowerSpec.idd2p02 = pPower->pIDD2P0[1]; + spec.memPowerSpec.idd2p1 = pPower->pIDD2P1[0]; + spec.memPowerSpec.idd2p12 = pPower->pIDD2P1[1]; + spec.memPowerSpec.idd2n = pPower->pIDD2N[0]; + spec.memPowerSpec.idd2n2 = pPower->pIDD2N[1]; + spec.memPowerSpec.idd3p0 = pPower->pIDD3P0[0]; + spec.memPowerSpec.idd3p02 = pPower->pIDD3P0[1]; + spec.memPowerSpec.idd3p1 = pPower->pIDD3P1[0]; + spec.memPowerSpec.idd3p12 = pPower->pIDD3P1[1]; + spec.memPowerSpec.idd3n = pPower->pIDD3N[0]; + spec.memPowerSpec.idd3n2 = pPower->pIDD3N[1]; + spec.memPowerSpec.idd4r = pPower->pIDD4R[0]; + spec.memPowerSpec.idd4r2 = pPower->pIDD4R[1]; + spec.memPowerSpec.idd4w = pPower->pIDD4W[0]; + spec.memPowerSpec.idd4w2 = pPower->pIDD4W[1]; + spec.memPowerSpec.idd5 = pPower->pIDD5[0]; + spec.memPowerSpec.idd52 = pPower->pIDD5[1]; + spec.memPowerSpec.idd6 = pPower->pIDD6[0]; + spec.memPowerSpec.idd62 = pPower->pIDD6[1]; + spec.memPowerSpec.vdd = pPower->pVDD[0]; + spec.memPowerSpec.vdd2 = pPower->pVDD[1]; +} + +void AbstractDRAM::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "energy"; + temp.desc = "Total energy comsumed by embedded DRAM (pJ)"; + list.push_back(temp); + + temp.name = prefix + "power"; + temp.desc = "Total power comsumed by embedded DRAM (mW)"; + list.push_back(temp); +} + +void AbstractDRAM::getStatValues(std::vector &values) { + values.push_back(totalEnergy); + values.push_back(totalPower); +} + +void AbstractDRAM::resetStatValues() { + // calcWindowEnergy clears old data + dramPower->calcWindowEnergy(getTick() / pTiming->tCK); + + totalEnergy = 0.0; + totalPower = 0.0; +} + +} // namespace DRAM + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/abstract_dram.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/abstract_dram.hh new file mode 100644 index 0000000000..0bec5b5ecb --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/abstract_dram.hh @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __DRAM_ABSTRACT_DRAM__ +#define __DRAM_ABSTRACT_DRAM__ + +#include + +#include "libdrampower/LibDRAMPower.h" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace DRAM { + +typedef enum : uint8_t { + ACTIVE, //!< Row active + IDLE, //!< Precharged + POWER_DOWN_PRECHARGE, //!< Precharge power down + POWER_DOWN_ACTIVE, //!< Active power down + SELF_REFRESH, //!< Self refresh +} DRAMState; + +class AbstractDRAM : public StatObject { + protected: + ConfigReader &conf; + + Config::DRAMStructure *pStructure; + Config::DRAMTiming *pTiming; + Config::DRAMPower *pPower; + + Data::MemorySpecification spec; + libDRAMPower *dramPower; + + void convertMemspec(); + + double totalEnergy; // Unit: pJ + double totalPower; // Unit: mW + + public: + AbstractDRAM(ConfigReader &); + virtual ~AbstractDRAM(); + + virtual void read(void *, uint64_t, uint64_t &) = 0; + virtual void write(void *, uint64_t, uint64_t &) = 0; + + // TEMP: Should be removed on v2.2 + virtual void setScheduling(bool) {} + virtual bool isScheduling() { return true; } + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace DRAM + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/config.cc new file mode 100644 index 0000000000..6e10a0c422 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/config.cc @@ -0,0 +1,345 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "dram/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace DRAM { + +const char NAME_DRAM_MODEL[] = "Model"; +const char NAME_DRAM_STRUCTURE_CHANNEL[] = "Channel"; +const char NAME_DRAM_STRUCTURE_RANK[] = "Rank"; +const char NAME_DRAM_STRUCTURE_BANK[] = "Bank"; +const char NAME_DRAM_STRUCTURE_CHIP[] = "Chip"; +const char NAME_DRAM_STRUCTURE_BUS_WIDTH[] = "BusWidth"; +const char NAME_DRAM_STRUCTURE_BURST_LENGTH[] = "BurstLength"; +const char NAME_DRAM_STRUCTURE_CHIP_SIZE[] = "ChipSize"; +const char NAME_DRAM_STRUCTURE_PAGE_SIZE[] = "PageSize"; +const char NAME_DRAM_TIMING_CK[] = "tCK"; +const char NAME_DRAM_TIMING_RCD[] = "tRCD"; +const char NAME_DRAM_TIMING_CL[] = "tCL"; +const char NAME_DRAM_TIMING_RP[] = "tRP"; +const char NAME_DRAM_TIMING_RAS[] = "tRAS"; +const char NAME_DRAM_TIMING_WR[] = "tWR"; +const char NAME_DRAM_TIMING_RTP[] = "tRTP"; +const char NAME_DRAM_TIMING_BURST[] = "tBURST"; +const char NAME_DRAM_TIMING_CCD_L[] = "tCCD_L"; +const char NAME_DRAM_TIMING_RFC[] = "tRFC"; +const char NAME_DRAM_TIMING_REFI[] = "tREFI"; +const char NAME_DRAM_TIMING_WTR[] = "tWTR"; +const char NAME_DRAM_TIMING_RTW[] = "tRTW"; +const char NAME_DRAM_TIMING_CS[] = "tCS"; +const char NAME_DRAM_TIMING_RRD[] = "tRRD"; +const char NAME_DRAM_TIMING_RRD_L[] = "tRRD_L"; +const char NAME_DRAM_TIMING_XAW[] = "tXAW"; +const char NAME_DRAM_TIMING_XP[] = "tXP"; +const char NAME_DRAM_TIMING_XPDLL[] = "tXPDLL"; +const char NAME_DRAM_TIMING_XS[] = "tXS"; +const char NAME_DRAM_TIMING_XSDLL[] = "tXSDLL"; +const char NAME_DRAM_POWER_IDD0_0[] = "IDD0_0"; +const char NAME_DRAM_POWER_IDD0_1[] = "IDD0_1"; +const char NAME_DRAM_POWER_IDD2P0_0[] = "IDD2P0_0"; +const char NAME_DRAM_POWER_IDD2P0_1[] = "IDD2P0_1"; +const char NAME_DRAM_POWER_IDD2P1_0[] = "IDD2P1_0"; +const char NAME_DRAM_POWER_IDD2P1_1[] = "IDD2P1_1"; +const char NAME_DRAM_POWER_IDD2N_0[] = "IDD2N_0"; +const char NAME_DRAM_POWER_IDD2N_1[] = "IDD2N_1"; +const char NAME_DRAM_POWER_IDD3P0_0[] = "IDD3P0_0"; +const char NAME_DRAM_POWER_IDD3P0_1[] = "IDD3P0_1"; +const char NAME_DRAM_POWER_IDD3P1_0[] = "IDD3P1_0"; +const char NAME_DRAM_POWER_IDD3P1_1[] = "IDD3P1_1"; +const char NAME_DRAM_POWER_IDD3N_0[] = "IDD3N_0"; +const char NAME_DRAM_POWER_IDD3N_1[] = "IDD3N_1"; +const char NAME_DRAM_POWER_IDD4R_0[] = "IDD4R_0"; +const char NAME_DRAM_POWER_IDD4R_1[] = "IDD4R_1"; +const char NAME_DRAM_POWER_IDD4W_0[] = "IDD4W_0"; +const char NAME_DRAM_POWER_IDD4W_1[] = "IDD4W_1"; +const char NAME_DRAM_POWER_IDD5_0[] = "IDD5_0"; +const char NAME_DRAM_POWER_IDD5_1[] = "IDD5_1"; +const char NAME_DRAM_POWER_IDD6_0[] = "IDD6_0"; +const char NAME_DRAM_POWER_IDD6_1[] = "IDD6_1"; +const char NAME_DRAM_POWER_VDD_0[] = "VDD_0"; +const char NAME_DRAM_POWER_VDD_1[] = "VDD_1"; + +Config::Config() { + model = SIMPLE_MODEL; + + /* LPDDR3-1600 4Gbit 1x32 */ + dram.channel = 1; + dram.rank = 1; + dram.bank = 8; + dram.chip = 1; + dram.chipSize = 536870912; + dram.busWidth = 32; + dram.burstLength = 8; + dram.activationLimit = 4; + dram.useDLL = false; + dram.pageSize = 4096; + + dramTiming.tCK = 1250; + dramTiming.tRCD = 18000; + dramTiming.tCL = 15000; + dramTiming.tRP = 18000; + dramTiming.tRAS = 42000; + dramTiming.tWR = 15000; + dramTiming.tRTP = 7500; + dramTiming.tBURST = 5000; + dramTiming.tCCD_L = 0; + dramTiming.tRFC = 130000; + dramTiming.tREFI = 3900; + dramTiming.tWTR = 7500; + dramTiming.tRTW = 2500; + dramTiming.tCS = 2500; + dramTiming.tRRD = 10000; + dramTiming.tRRD_L = 0; + dramTiming.tXAW = 50000; + dramTiming.tXP = 0; + dramTiming.tXPDLL = 0; + dramTiming.tXS = 0; + dramTiming.tXSDLL = 0; + + dramPower.pIDD0[0] = 8.f; + dramPower.pIDD0[1] = 60.f; + dramPower.pIDD2P0[0] = 0.f; + dramPower.pIDD2P0[1] = 0.f; + dramPower.pIDD2P1[0] = 0.8f; + dramPower.pIDD2P1[1] = 1.8f; + dramPower.pIDD2N[0] = 0.8f; + dramPower.pIDD2N[1] = 26.f; + dramPower.pIDD3P0[0] = 0.f; + dramPower.pIDD3P0[1] = 0.f; + dramPower.pIDD3P1[0] = 1.4f; + dramPower.pIDD3P1[1] = 11.f; + dramPower.pIDD3N[0] = 2.f; + dramPower.pIDD3N[1] = 34.f; + dramPower.pIDD4R[0] = 2.f; + dramPower.pIDD4R[1] = 230.f; + dramPower.pIDD4W[0] = 2.f; + dramPower.pIDD4W[1] = 190.f; + dramPower.pIDD5[0] = 28.f; + dramPower.pIDD5[1] = 150.f; + dramPower.pIDD6[0] = 0.5f; + dramPower.pIDD6[1] = 1.8f; + dramPower.pVDD[0] = 1.8f; + dramPower.pVDD[1] = 1.2f; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_DRAM_MODEL)) { + model = (MODEL)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_CHANNEL)) { + dram.channel = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_RANK)) { + dram.rank = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_BANK)) { + dram.bank = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_CHIP)) { + dram.chip = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_BUS_WIDTH)) { + dram.busWidth = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_BURST_LENGTH)) { + dram.burstLength = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_CHIP_SIZE)) { + dram.chipSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_PAGE_SIZE)) { + dram.pageSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CK)) { + dramTiming.tCK = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RCD)) { + dramTiming.tRCD = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CL)) { + dramTiming.tCL = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RP)) { + dramTiming.tRP = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RAS)) { + dramTiming.tRAS = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_WR)) { + dramTiming.tWR = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RTP)) { + dramTiming.tRTP = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_BURST)) { + dramTiming.tBURST = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CCD_L)) { + dramTiming.tCCD_L = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RFC)) { + dramTiming.tRFC = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_REFI)) { + dramTiming.tREFI = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_WTR)) { + dramTiming.tWTR = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RTW)) { + dramTiming.tRTW = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CS)) { + dramTiming.tCS = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RRD)) { + dramTiming.tRRD = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RRD_L)) { + dramTiming.tRRD_L = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XAW)) { + dramTiming.tXAW = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XP)) { + dramTiming.tXP = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XPDLL)) { + dramTiming.tXPDLL = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XS)) { + dramTiming.tXS = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XSDLL)) { + dramTiming.tXSDLL = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD0_0)) { + dramPower.pIDD0[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD0_1)) { + dramPower.pIDD0[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P0_0)) { + dramPower.pIDD2P0[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P0_1)) { + dramPower.pIDD2P0[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P1_0)) { + dramPower.pIDD2P1[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P1_1)) { + dramPower.pIDD2P1[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2N_0)) { + dramPower.pIDD2N[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2N_1)) { + dramPower.pIDD2N[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P0_0)) { + dramPower.pIDD3P0[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P0_1)) { + dramPower.pIDD3P0[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P1_0)) { + dramPower.pIDD3P1[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P1_1)) { + dramPower.pIDD3P1[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3N_0)) { + dramPower.pIDD3N[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3N_1)) { + dramPower.pIDD3N[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4R_0)) { + dramPower.pIDD4R[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4R_1)) { + dramPower.pIDD4R[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4W_0)) { + dramPower.pIDD4W[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4W_1)) { + dramPower.pIDD4W[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD5_0)) { + dramPower.pIDD5[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD5_1)) { + dramPower.pIDD5[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD6_0)) { + dramPower.pIDD6[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD6_1)) { + dramPower.pIDD6[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_VDD_0)) { + dramPower.pVDD[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_VDD_1)) { + dramPower.pVDD[1] = strtof(value, nullptr); + } + else { + ret = false; + } + + return ret; +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case DRAM_MODEL: + ret = model; + break; + } + + return ret; +} + +Config::DRAMStructure *Config::getDRAMStructure() { + return &dram; +} + +Config::DRAMTiming *Config::getDRAMTiming() { + return &dramTiming; +} + +Config::DRAMPower *Config::getDRAMPower() { + return &dramPower; +} + +} // namespace DRAM + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/config.hh new file mode 100644 index 0000000000..9aa655ea8f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/config.hh @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __DRAM_CONFIG__ +#define __DRAM_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace DRAM { + +typedef enum { + DRAM_MODEL, +} DRAM_CONFIG; + +typedef enum { + SIMPLE_MODEL, +} MODEL; + +class Config : public BaseConfig { + public: + typedef struct { + uint32_t channel; //!< # of channel + uint32_t rank; //!< Rank / Channel + uint32_t bank; //!< Bank / Rank + uint32_t chip; //!< Chips / Rank + uint32_t busWidth; //!< Bus / Chip + uint32_t burstLength; + uint32_t activationLimit; + bool useDLL; + uint64_t chipSize; + uint64_t pageSize; + } DRAMStructure; + + typedef struct { // Unit: ps + uint32_t tCK; //!< Clock period + uint32_t tRCD; //!< RAS to CAS delay + uint32_t tCL; //!< CAS latency + uint32_t tRP; //!< Row precharge time + uint32_t tRAS; //!< ACT to PRE delay + uint32_t tWR; //!< Write recovery time + uint32_t tRTP; //!< Read to precharge delay + uint32_t tBURST; //!< Burst duration + uint32_t tCCD_L; //!< Same bank group CAS to CAS delay + uint32_t tRFC; //!< Refresh cycle time + uint32_t tREFI; //!< Refresh command interval + uint32_t tWTR; //!< Write to read, same rank switching time + uint32_t tRTW; //!< Read to write, same rank switching time + uint32_t tCS; //!< Rank to rank switching time + uint32_t tRRD; //!< ACT to ACT delay + uint32_t tRRD_L; //!< Same bank group RRD + uint32_t tXAW; //!< X activation window + uint32_t tXP; //!< Power-up delay + uint32_t tXPDLL; //!< Power-up delay with locked DLL + uint32_t tXS; //!< Self-refresh exit latency + uint32_t tXSDLL; //!< Self-refresh exit latency DLL + } DRAMTiming; + + typedef struct { // Unit: mA + float pIDD0[2]; //!< Active precharge current + float pIDD2P0[2]; //!< Precharge powerdown slow + float pIDD2P1[2]; //!< Precharge powerdown fast + float pIDD2N[2]; //!< Precharge standby current + float pIDD3P0[2]; //!< Active powerdown slow + float pIDD3P1[2]; //!< Active powerdown fast + float pIDD3N[2]; //!< Active standby current + float pIDD4R[2]; //!< READ current + float pIDD4W[2]; //!< WRITE current + float pIDD5[2]; //!< Refresh current + float pIDD6[2]; //!< Self-refresh current + float pVDD[2]; //!< Main voltage (Unit: V) + } DRAMPower; + + private: + MODEL model; + + DRAMStructure dram; + DRAMTiming dramTiming; + DRAMPower dramPower; + + public: + Config(); + + bool setConfig(const char *, const char *) override; + + int64_t readInt(uint32_t) override; + + DRAMStructure *getDRAMStructure(); + DRAMTiming *getDRAMTiming(); + DRAMPower *getDRAMPower(); +}; + +} // namespace DRAM + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/simple.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/simple.cc new file mode 100644 index 0000000000..9db42ba643 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/simple.cc @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "dram/simple.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace DRAM { + +#define REFRESH_PERIOD 64000000000 + +SimpleDRAM::Stat::Stat() : count(0), size(0) {} + +SimpleDRAM::SimpleDRAM(ConfigReader &p) + : AbstractDRAM(p), lastDRAMAccess(0), ignoreScheduling(false) { + pageFetchLatency = pTiming->tRP + pTiming->tRAS; + interfaceBandwidth = 2.0 * pStructure->busWidth * pStructure->chip * + pStructure->channel / 8.0 / pTiming->tCK; + + autoRefresh = allocate([this](uint64_t now) { + dramPower->doCommand(Data::MemCommand::REF, 0, now / pTiming->tCK); + + lastDRAMAccess = MAX(lastDRAMAccess, now + pTiming->tRFC); + + schedule(autoRefresh, now + REFRESH_PERIOD); + }); + + schedule(autoRefresh, getTick() + REFRESH_PERIOD); +} + +SimpleDRAM::~SimpleDRAM() { + // DO NOTHING +} + +uint64_t SimpleDRAM::updateDelay(uint64_t latency, uint64_t &tick) { + uint64_t beginAt = tick; + + if (tick > 0) { + if (ignoreScheduling) { + tick += latency; + } + else { + if (lastDRAMAccess <= tick) { + lastDRAMAccess = tick + latency; + } + else { + beginAt = lastDRAMAccess; + lastDRAMAccess += latency; + } + + tick = lastDRAMAccess; + } + } + + return beginAt; +} + +void SimpleDRAM::updateStats(uint64_t cycle) { + dramPower->calcWindowEnergy(cycle); + + auto &energy = dramPower->getEnergy(); + auto &power = dramPower->getPower(); + + totalEnergy += energy.window_energy; + totalPower = power.average_power; +} + +void SimpleDRAM::setScheduling(bool enable) { + ignoreScheduling = !enable; +} + +bool SimpleDRAM::isScheduling() { + return !ignoreScheduling; +} + +void SimpleDRAM::read(void *, uint64_t size, uint64_t &tick) { + uint64_t pageCount = (size > 0) ? (size - 1) / pStructure->pageSize + 1 : 0; + uint64_t latency = + (uint64_t)(pageCount * (pageFetchLatency + + pStructure->pageSize / interfaceBandwidth)); + + uint64_t beginAt = updateDelay(latency, tick); + + // DRAMPower uses cycle unit + beginAt /= pTiming->tCK; + + dramPower->doCommand(Data::MemCommand::ACT, 0, beginAt); + + for (uint64_t i = 0; i < pageCount; i++) { + dramPower->doCommand(Data::MemCommand::RD, 0, + beginAt + spec.memTimingSpec.RCD); + + beginAt += spec.memTimingSpec.RCD; + } + + beginAt -= spec.memTimingSpec.RCD; + + dramPower->doCommand(Data::MemCommand::PRE, 0, + beginAt + spec.memTimingSpec.RAS); + + // Stat Update + updateStats(beginAt + spec.memTimingSpec.RAS + spec.memTimingSpec.RP); + readStat.count++; + readStat.size += size; +} + +void SimpleDRAM::write(void *, uint64_t size, uint64_t &tick) { + uint64_t pageCount = (size > 0) ? (size - 1) / pStructure->pageSize + 1 : 0; + uint64_t latency = + (uint64_t)(pageCount * (pageFetchLatency + + pStructure->pageSize / interfaceBandwidth)); + + uint64_t beginAt = updateDelay(latency, tick); + + // DRAMPower uses cycle unit + beginAt /= pTiming->tCK; + + dramPower->doCommand(Data::MemCommand::ACT, 0, beginAt); + + for (uint64_t i = 0; i < pageCount; i++) { + dramPower->doCommand(Data::MemCommand::WR, 0, + beginAt + spec.memTimingSpec.RCD); + + beginAt += spec.memTimingSpec.RCD; + } + + beginAt -= spec.memTimingSpec.RCD; + + dramPower->doCommand(Data::MemCommand::PRE, 0, + beginAt + spec.memTimingSpec.RAS); + + // Stat Update + updateStats(beginAt + spec.memTimingSpec.RAS + spec.memTimingSpec.RP); + writeStat.count++; + writeStat.size += size; +} + +void SimpleDRAM::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + AbstractDRAM::getStatList(list, prefix); + + temp.name = prefix + "read.request_count"; + temp.desc = "Read request count"; + list.push_back(temp); + + temp.name = prefix + "read.bytes"; + temp.desc = "Read data size in byte"; + list.push_back(temp); + + temp.name = prefix + "write.request_count"; + temp.desc = "Write request count"; + list.push_back(temp); + + temp.name = prefix + "write.bytes"; + temp.desc = "Write data size in byte"; + list.push_back(temp); + + temp.name = prefix + "request_count"; + temp.desc = "Total request count"; + list.push_back(temp); + + temp.name = prefix + "bytes"; + temp.desc = "Total data size in byte"; + list.push_back(temp); +} + +void SimpleDRAM::getStatValues(std::vector &values) { + AbstractDRAM::getStatValues(values); + + values.push_back(readStat.count); + values.push_back(readStat.size); + values.push_back(writeStat.count); + values.push_back(writeStat.size); + values.push_back(readStat.count + writeStat.count); + values.push_back(readStat.size + writeStat.size); +} + +void SimpleDRAM::resetStatValues() { + AbstractDRAM::resetStatValues(); + + readStat = Stat(); + writeStat = Stat(); +} + +} // namespace DRAM + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/simple.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/simple.hh new file mode 100644 index 0000000000..d1c19f0a06 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/dram/simple.hh @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __DRAM_SIMPLE__ +#define __DRAM_SIMPLE__ + +#include + +#include "dram/abstract_dram.hh" + +namespace SimpleSSD { + +namespace DRAM { + +class SimpleDRAM : public AbstractDRAM { + private: + struct Stat { + uint64_t count; + uint64_t size; + + Stat(); + }; + + uint64_t pageFetchLatency; + double interfaceBandwidth; + + uint64_t lastDRAMAccess; + bool ignoreScheduling; + + Event autoRefresh; + + Stat readStat; + Stat writeStat; + + uint64_t updateDelay(uint64_t, uint64_t &); + void updateStats(uint64_t); + + public: + SimpleDRAM(ConfigReader &p); + ~SimpleDRAM(); + + void read(void *, uint64_t, uint64_t &) override; + void write(void *, uint64_t, uint64_t &) override; + + void setScheduling(bool) override; + bool isScheduling() override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace DRAM + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/abstract_ftl.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/abstract_ftl.hh new file mode 100644 index 0000000000..bee59b8e28 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/abstract_ftl.hh @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_ABSTRACT_FTL__ +#define __FTL_ABSTRACT_FTL__ + +#include + +#include "ftl/ftl.hh" + +namespace SimpleSSD { + +namespace FTL { + +typedef struct _Status { + uint64_t totalLogicalPages; + uint64_t mappedLogicalPages; + uint64_t freePhysicalBlocks; +} Status; + +class AbstractFTL : public StatObject { + protected: + Parameter ¶m; + PAL::PAL *pPAL; + DRAM::AbstractDRAM *pDRAM; + Status status; + + public: + AbstractFTL(Parameter &p, PAL::PAL *l, DRAM::AbstractDRAM *d) + : param(p), pPAL(l), pDRAM(d) {} + virtual ~AbstractFTL() {} + + virtual bool initialize() = 0; + + virtual void read(Request &, uint64_t &) = 0; + virtual void write(Request &, uint64_t &) = 0; + virtual void trim(Request &, uint64_t &) = 0; + + virtual void format(LPNRange &, uint64_t &) = 0; + + virtual Status *getStatus(uint64_t, uint64_t) = 0; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/common/block.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/common/block.cc new file mode 100644 index 0000000000..d7be114032 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/common/block.cc @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/common/block.hh" + +#include +#include + +namespace SimpleSSD { + +namespace FTL { + +Block::Block(uint32_t blockIdx, uint32_t count, uint32_t ioUnit) + : idx(blockIdx), + pageCount(count), + ioUnitInPage(ioUnit), + pValidBits(nullptr), + pErasedBits(nullptr), + pLPNs(nullptr), + ppLPNs(nullptr), + lastAccessed(0), + eraseCount(0) { + if (ioUnitInPage == 1) { + pValidBits = new Bitset(pageCount); + pErasedBits = new Bitset(pageCount); + + pLPNs = (uint64_t *)calloc(pageCount, sizeof(uint64_t)); + } + else if (ioUnitInPage > 1) { + Bitset copy(ioUnitInPage); + + validBits = std::vector(pageCount, copy); + erasedBits = std::vector(pageCount, copy); + + ppLPNs = (uint64_t **)calloc(pageCount, sizeof(uint64_t *)); + + for (uint32_t i = 0; i < pageCount; i++) { + ppLPNs[i] = (uint64_t *)calloc(ioUnitInPage, sizeof(uint64_t)); + } + } + else { + panic("Invalid I/O unit in page"); + } + + // C-style allocation + pNextWritePageIndex = (uint32_t *)calloc(ioUnitInPage, sizeof(uint32_t)); + + erase(); + eraseCount = 0; +} + +Block::Block(const Block &old) + : Block(old.idx, old.pageCount, old.ioUnitInPage) { + if (ioUnitInPage == 1) { + *pValidBits = *old.pValidBits; + *pErasedBits = *old.pErasedBits; + + memcpy(pLPNs, old.pLPNs, pageCount * sizeof(uint64_t)); + } + else { + validBits = old.validBits; + erasedBits = old.erasedBits; + + for (uint32_t i = 0; i < pageCount; i++) { + memcpy(ppLPNs[i], old.ppLPNs[i], ioUnitInPage * sizeof(uint64_t)); + } + } + + memcpy(pNextWritePageIndex, old.pNextWritePageIndex, + ioUnitInPage * sizeof(uint32_t)); + + eraseCount = old.eraseCount; +} + +Block::Block(Block &&old) noexcept + : idx(std::move(old.idx)), + pageCount(std::move(old.pageCount)), + ioUnitInPage(std::move(old.ioUnitInPage)), + pNextWritePageIndex(std::move(old.pNextWritePageIndex)), + pValidBits(std::move(old.pValidBits)), + pErasedBits(std::move(old.pErasedBits)), + pLPNs(std::move(old.pLPNs)), + validBits(std::move(old.validBits)), + erasedBits(std::move(old.erasedBits)), + ppLPNs(std::move(old.ppLPNs)), + lastAccessed(std::move(old.lastAccessed)), + eraseCount(std::move(old.eraseCount)) { + // TODO Use std::exchange to set old value to null (C++14) + old.idx = 0; + old.pageCount = 0; + old.ioUnitInPage = 0; + old.pNextWritePageIndex = nullptr; + old.pValidBits = nullptr; + old.pErasedBits = nullptr; + old.pLPNs = nullptr; + old.ppLPNs = nullptr; + old.lastAccessed = 0; + old.eraseCount = 0; +} + +Block::~Block() { + free(pNextWritePageIndex); + free(pLPNs); + + delete pValidBits; + delete pErasedBits; + + if (ppLPNs) { + for (uint32_t i = 0; i < pageCount; i++) { + free(ppLPNs[i]); + } + + free(ppLPNs); + } + + pNextWritePageIndex = nullptr; + pLPNs = nullptr; + pValidBits = nullptr; + pErasedBits = nullptr; + ppLPNs = nullptr; +} + +Block &Block::operator=(const Block &rhs) { + if (this != &rhs) { + this->~Block(); + *this = Block(rhs); // Call copy constructor + } + + return *this; +} + +Block &Block::operator=(Block &&rhs) { + if (this != &rhs) { + this->~Block(); + + idx = std::move(rhs.idx); + pageCount = std::move(rhs.pageCount); + ioUnitInPage = std::move(rhs.ioUnitInPage); + pNextWritePageIndex = std::move(rhs.pNextWritePageIndex); + pValidBits = std::move(rhs.pValidBits); + pErasedBits = std::move(rhs.pErasedBits); + pLPNs = std::move(rhs.pLPNs); + validBits = std::move(rhs.validBits); + erasedBits = std::move(rhs.erasedBits); + ppLPNs = std::move(rhs.ppLPNs); + lastAccessed = std::move(rhs.lastAccessed); + eraseCount = std::move(rhs.eraseCount); + + rhs.pNextWritePageIndex = nullptr; + rhs.pValidBits = nullptr; + rhs.pErasedBits = nullptr; + rhs.pLPNs = nullptr; + rhs.ppLPNs = nullptr; + rhs.lastAccessed = 0; + rhs.eraseCount = 0; + } + + return *this; +} + +uint32_t Block::getBlockIndex() const { + return idx; +} + +uint64_t Block::getLastAccessedTime() { + return lastAccessed; +} + +uint32_t Block::getEraseCount() { + return eraseCount; +} + +uint32_t Block::getValidPageCount() { + uint32_t ret = 0; + + if (ioUnitInPage == 1) { + ret = pValidBits->count(); + } + else { + for (auto &iter : validBits) { + if (iter.any()) { + ret++; + } + } + } + + return ret; +} + +uint32_t Block::getValidPageCountRaw() { + uint32_t ret = 0; + + if (ioUnitInPage == 1) { + // Same as getValidPageCount() + ret = pValidBits->count(); + } + else { + for (auto &iter : validBits) { + ret += iter.count(); + } + } + + return ret; +} + +uint32_t Block::getDirtyPageCount() { + uint32_t ret = 0; + + if (ioUnitInPage == 1) { + ret = (~(*pValidBits | *pErasedBits)).count(); + } + else { + for (uint32_t i = 0; i < pageCount; i++) { + // Dirty: Valid(false), Erased(false) + if ((~(validBits.at(i) | erasedBits.at(i))).any()) { + ret++; + } + } + } + + return ret; +} + +uint32_t Block::getNextWritePageIndex() { + uint32_t idx = 0; + + for (uint32_t i = 0; i < ioUnitInPage; i++) { + if (idx < pNextWritePageIndex[i]) { + idx = pNextWritePageIndex[i]; + } + } + + return idx; +} + +uint32_t Block::getNextWritePageIndex(uint32_t idx) { + return pNextWritePageIndex[idx]; +} + +bool Block::getPageInfo(uint32_t pageIndex, std::vector &lpn, + Bitset &map) { + if (ioUnitInPage == 1 && map.size() == 1) { + map.set(); + lpn = std::vector(1, pLPNs[pageIndex]); + } + else if (map.size() == ioUnitInPage) { + map = validBits.at(pageIndex); + lpn = std::vector(ppLPNs[pageIndex], + ppLPNs[pageIndex] + ioUnitInPage); + } + else { + panic("I/O map size mismatch"); + } + + return map.any(); +} + +bool Block::read(uint32_t pageIndex, uint32_t idx, uint64_t tick) { + bool read = false; + + if (ioUnitInPage == 1 && idx == 0) { + read = pValidBits->test(pageIndex); + } + else if (idx < ioUnitInPage) { + read = validBits.at(pageIndex).test(idx); + } + else { + panic("I/O map size mismatch"); + } + + if (read) { + lastAccessed = tick; + } + + return read; +} + +bool Block::write(uint32_t pageIndex, uint64_t lpn, uint32_t idx, + uint64_t tick) { + bool write = false; + + if (ioUnitInPage == 1 && idx == 0) { + write = pErasedBits->test(pageIndex); + } + else if (idx < ioUnitInPage) { + write = erasedBits.at(pageIndex).test(idx); + } + else { + panic("I/O map size mismatch"); + } + + if (write) { + if (pageIndex < pNextWritePageIndex[idx]) { + panic("Write to block should sequential"); + } + + lastAccessed = tick; + + if (ioUnitInPage == 1) { + pErasedBits->reset(pageIndex); + pValidBits->set(pageIndex); + + pLPNs[pageIndex] = lpn; + } + else { + erasedBits.at(pageIndex).reset(idx); + validBits.at(pageIndex).set(idx); + + ppLPNs[pageIndex][idx] = lpn; + } + + pNextWritePageIndex[idx] = pageIndex + 1; + } + else { + panic("Write to non erased page"); + } + + return write; +} + +void Block::erase() { + if (ioUnitInPage == 1) { + pValidBits->reset(); + pErasedBits->set(); + } + else { + for (auto &iter : validBits) { + iter.reset(); + } + for (auto &iter : erasedBits) { + iter.set(); + } + } + + memset(pNextWritePageIndex, 0, sizeof(uint32_t) * ioUnitInPage); + + eraseCount++; +} + +void Block::invalidate(uint32_t pageIndex, uint32_t idx) { + if (ioUnitInPage == 1) { + pValidBits->reset(pageIndex); + } + else { + validBits.at(pageIndex).reset(idx); + } +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/common/block.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/common/block.hh new file mode 100644 index 0000000000..edceb4a155 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/common/block.hh @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_COMMON_BLOCK__ +#define __FTL_COMMON_BLOCK__ + +#include +#include + +#include "util/bitset.hh" + +namespace SimpleSSD { + +namespace FTL { + +class Block { + private: + uint32_t idx; + uint32_t pageCount; + uint32_t ioUnitInPage; + uint32_t *pNextWritePageIndex; + + // Following variables are used when ioUnitInPage == 1 + Bitset *pValidBits; + Bitset *pErasedBits; + uint64_t *pLPNs; + + // Following variables are used when ioUnitInPage > 1 + std::vector validBits; + std::vector erasedBits; + uint64_t **ppLPNs; + + uint64_t lastAccessed; + uint32_t eraseCount; + + public: + Block(uint32_t, uint32_t, uint32_t); + Block(const Block &); // Copy constructor + Block(Block &&) noexcept; // Move constructor + ~Block(); + + Block &operator=(const Block &); // Copy assignment + Block &operator=(Block &&); // Move assignment + + uint32_t getBlockIndex() const; + uint64_t getLastAccessedTime(); + uint32_t getEraseCount(); + uint32_t getValidPageCount(); + uint32_t getValidPageCountRaw(); + uint32_t getDirtyPageCount(); + uint32_t getNextWritePageIndex(); + uint32_t getNextWritePageIndex(uint32_t); + bool getPageInfo(uint32_t, std::vector &, Bitset &); + bool read(uint32_t, uint32_t, uint64_t); + bool write(uint32_t, uint64_t, uint32_t, uint64_t); + void erase(); + void invalidate(uint32_t, uint32_t); +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/config.cc new file mode 100644 index 0000000000..3db1048247 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/config.cc @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/config.hh" + +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace FTL { + +const char NAME_MAPPING_MODE[] = "MappingMode"; +const char NAME_OVERPROVISION_RATIO[] = "OverProvisioningRatio"; +const char NAME_GC_THRESHOLD[] = "GCThreshold"; +const char NAME_BAD_BLOCK_THRESHOLD[] = "EraseThreshold"; +const char NAME_FILLING_MODE[] = "FillingMode"; +const char NAME_FILL_RATIO[] = "FillRatio"; +const char NAME_INVALID_PAGE_RATIO[] = "InvalidPageRatio"; +const char NAME_GC_MODE[] = "GCMode"; +const char NAME_GC_RECLAIM_BLOCK[] = "GCReclaimBlocks"; +const char NAME_GC_RECLAIM_THRESHOLD[] = "GCReclaimThreshold"; +const char NAME_GC_EVICT_POLICY[] = "EvictPolicy"; +const char NAME_GC_D_CHOICE_PARAM[] = "DChoiceParam"; +const char NAME_USE_RANDOM_IO_TWEAK[] = "EnableRandomIOTweak"; + +Config::Config() { + mapping = PAGE_MAPPING; + overProvision = 0.25f; + gcThreshold = 0.05f; + badBlockThreshold = 100000; + fillingMode = FILLING_MODE_0; + fillingRatio = 0.f; + invalidRatio = 0.f; + reclaimBlock = 1; + reclaimThreshold = 0.1f; + gcMode = GC_MODE_0; + evictPolicy = POLICY_GREEDY; + dChoiceParam = 3; + randomIOTweak = true; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_MAPPING_MODE)) { + mapping = (MAPPING)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_OVERPROVISION_RATIO)) { + overProvision = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_GC_THRESHOLD)) { + gcThreshold = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_BAD_BLOCK_THRESHOLD)) { + badBlockThreshold = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FILLING_MODE)) { + fillingMode = (FILLING_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FILL_RATIO)) { + fillingRatio = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_INVALID_PAGE_RATIO)) { + invalidRatio = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_GC_MODE)) { + gcMode = (GC_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GC_RECLAIM_BLOCK)) { + reclaimBlock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GC_RECLAIM_THRESHOLD)) { + reclaimThreshold = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_GC_EVICT_POLICY)) { + evictPolicy = (EVICT_POLICY)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GC_D_CHOICE_PARAM)) { + dChoiceParam = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_USE_RANDOM_IO_TWEAK)) { + randomIOTweak = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (gcMode == GC_MODE_0 && reclaimBlock == 0) { + panic("Invalid GCReclaimBlocks"); + } + + if (gcMode == GC_MODE_1 && reclaimThreshold < gcThreshold) { + panic("Invalid GCReclaimThreshold"); + } + + if (fillingRatio < 0.f || fillingRatio > 1.f) { + panic("Invalid FillingRatio"); + } + + if (invalidRatio < 0.f || invalidRatio > 1.f) { + panic("Invalid InvalidPageRatio"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case FTL_MAPPING_MODE: + ret = mapping; + break; + case FTL_GC_MODE: + ret = gcMode; + break; + case FTL_GC_EVICT_POLICY: + ret = evictPolicy; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case FTL_FILLING_MODE: + ret = fillingMode; + break; + case FTL_BAD_BLOCK_THRESHOLD: + ret = badBlockThreshold; + break; + case FTL_GC_RECLAIM_BLOCK: + ret = reclaimBlock; + break; + case FTL_GC_D_CHOICE_PARAM: + ret = dChoiceParam; + break; + } + + return ret; +} + +float Config::readFloat(uint32_t idx) { + float ret = 0.f; + + switch (idx) { + case FTL_OVERPROVISION_RATIO: + ret = overProvision; + break; + case FTL_GC_THRESHOLD_RATIO: + ret = gcThreshold; + break; + case FTL_FILL_RATIO: + ret = fillingRatio; + break; + case FTL_INVALID_PAGE_RATIO: + ret = invalidRatio; + break; + case FTL_GC_RECLAIM_THRESHOLD: + ret = reclaimThreshold; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case FTL_USE_RANDOM_IO_TWEAK: + ret = randomIOTweak; + break; + } + + return ret; +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/config.hh new file mode 100644 index 0000000000..e3e923f646 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/config.hh @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_CONFIG__ +#define __FTL_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace FTL { + +typedef enum { + /* Common FTL configuration */ + FTL_MAPPING_MODE, + FTL_OVERPROVISION_RATIO, + FTL_GC_THRESHOLD_RATIO, + FTL_BAD_BLOCK_THRESHOLD, + FTL_FILLING_MODE, + FTL_FILL_RATIO, + FTL_INVALID_PAGE_RATIO, + FTL_GC_MODE, + FTL_GC_RECLAIM_BLOCK, + FTL_GC_RECLAIM_THRESHOLD, + FTL_GC_EVICT_POLICY, + FTL_GC_D_CHOICE_PARAM, + FTL_USE_RANDOM_IO_TWEAK, + + /* N+K Mapping configuration*/ + FTL_NKMAP_N, + FTL_NKMAP_K, +} FTL_CONFIG; + +typedef enum { + PAGE_MAPPING, +} MAPPING; + +typedef enum { + GC_MODE_0, // Reclaim fixed number of blocks + GC_MODE_1, // Reclaim blocks until threshold +} GC_MODE; + +typedef enum { + FILLING_MODE_0, + FILLING_MODE_1, + FILLING_MODE_2, +} FILLING_MODE; + +typedef enum { + POLICY_GREEDY, // Select the block with the least valid pages + POLICY_COST_BENEFIT, + POLICY_RANDOM, // Select the block randomly + POLICY_DCHOICE, +} EVICT_POLICY; + +class Config : public BaseConfig { + private: + MAPPING mapping; //!< Default: PAGE_MAPPING + float overProvision; //!< Default: 0.25 (25%) + float gcThreshold; //!< Default: 0.05 (5%) + uint64_t badBlockThreshold; //!< Default: 100000 + FILLING_MODE fillingMode; //!< Default: FILLING_MODE_0 + float fillingRatio; //!< Default: 0.0 (0%) + float invalidRatio; //!< Default: 0.0 (0%) + uint64_t reclaimBlock; //!< Default: 1 + float reclaimThreshold; //!< Default: 0.1 (10%) + GC_MODE gcMode; //!< Default: FTL_GC_MODE_0 + EVICT_POLICY evictPolicy; //!< Default: POLICY_GREEDY + uint64_t dChoiceParam; //!< Default: 3 + bool randomIOTweak; //!< Default: true + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + float readFloat(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/ftl.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/ftl.cc new file mode 100644 index 0000000000..083631edac --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/ftl.cc @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/ftl.hh" + +#include "ftl/page_mapping.hh" + +namespace SimpleSSD { + +namespace FTL { + +FTL::FTL(ConfigReader &c, DRAM::AbstractDRAM *d) : conf(c), pDRAM(d) { + PAL::Parameter *palparam; + + pPAL = new PAL::PAL(conf); + palparam = pPAL->getInfo(); + + param.totalPhysicalBlocks = palparam->superBlock; + param.totalLogicalBlocks = + palparam->superBlock * + (1 - conf.readFloat(CONFIG_FTL, FTL_OVERPROVISION_RATIO)); + param.pagesInBlock = palparam->page; + param.pageSize = palparam->superPageSize; + param.ioUnitInPage = palparam->pageInSuperPage; + param.pageCountToMaxPerf = palparam->superBlock / palparam->block; + + switch (conf.readInt(CONFIG_FTL, FTL_MAPPING_MODE)) { + case PAGE_MAPPING: + pFTL = new PageMapping(conf, param, pPAL, pDRAM); + break; + } + + if (param.totalPhysicalBlocks <= + param.totalLogicalBlocks + param.pageCountToMaxPerf) { + panic("FTL Over-Provision Ratio is too small"); + } + + // Print mapping Information + debugprint(LOG_FTL, "Total physical blocks %u", param.totalPhysicalBlocks); + debugprint(LOG_FTL, "Total logical blocks %u", param.totalLogicalBlocks); + debugprint(LOG_FTL, "Logical page size %u", param.pageSize); + + // Initialize pFTL + pFTL->initialize(); +} + +FTL::~FTL() { + delete pPAL; + delete pFTL; +} + +void FTL::read(Request &req, uint64_t &tick) { + debugprint(LOG_FTL, "READ | LPN %" PRIu64, req.lpn); + + pFTL->read(req, tick); + + tick += applyLatency(CPU::FTL, CPU::READ); +} + +void FTL::write(Request &req, uint64_t &tick) { + debugprint(LOG_FTL, "WRITE | LPN %" PRIu64, req.lpn); + + pFTL->write(req, tick); + + tick += applyLatency(CPU::FTL, CPU::WRITE); +} + +void FTL::trim(Request &req, uint64_t &tick) { + debugprint(LOG_FTL, "TRIM | LPN %" PRIu64, req.lpn); + + pFTL->trim(req, tick); + + tick += applyLatency(CPU::FTL, CPU::TRIM); +} + +void FTL::format(LPNRange &range, uint64_t &tick) { + pFTL->format(range, tick); + + tick += applyLatency(CPU::FTL, CPU::FORMAT); +} + +Parameter *FTL::getInfo() { + return ¶m; +} + +uint64_t FTL::getUsedPageCount(uint64_t lpnBegin, uint64_t lpnEnd) { + return pFTL->getStatus(lpnBegin, lpnEnd)->mappedLogicalPages; +} + +void FTL::getStatList(std::vector &list, std::string prefix) { + pFTL->getStatList(list, prefix + "ftl."); + pPAL->getStatList(list, prefix); +} + +void FTL::getStatValues(std::vector &values) { + pFTL->getStatValues(values); + pPAL->getStatValues(values); +} + +void FTL::resetStatValues() { + pFTL->resetStatValues(); + pPAL->resetStatValues(); +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/ftl.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/ftl.hh new file mode 100644 index 0000000000..c328dd5f5b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/ftl.hh @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_FTL__ +#define __FTL_FTL__ + +#include "dram/abstract_dram.hh" +#include "pal/pal.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace FTL { + +class AbstractFTL; + +typedef struct { + uint64_t totalPhysicalBlocks; //!< (PAL::Parameter::superBlock) + uint64_t totalLogicalBlocks; + uint64_t pagesInBlock; //!< (PAL::Parameter::page) + uint32_t pageSize; //!< Mapping unit (PAL::Parameter::superPageSize) + uint32_t ioUnitInPage; //!< # smallest I/O unit in one page + uint32_t pageCountToMaxPerf; //!< # pages to fully utilize internal parallism +} Parameter; + +class FTL : public StatObject { + private: + Parameter param; + PAL::PAL *pPAL; + + ConfigReader &conf; + AbstractFTL *pFTL; + DRAM::AbstractDRAM *pDRAM; + + public: + FTL(ConfigReader &, DRAM::AbstractDRAM *); + ~FTL(); + + void read(Request &, uint64_t &); + void write(Request &, uint64_t &); + void trim(Request &, uint64_t &); + + void format(LPNRange &, uint64_t &); + + Parameter *getInfo(); + uint64_t getUsedPageCount(uint64_t, uint64_t); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/page_mapping.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/page_mapping.cc new file mode 100644 index 0000000000..c7f23df094 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/page_mapping.cc @@ -0,0 +1,1067 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/page_mapping.hh" + +#include +#include +#include + +#include "util/algorithm.hh" +#include "util/bitset.hh" + +namespace SimpleSSD { + +namespace FTL { + +PageMapping::PageMapping(ConfigReader &c, Parameter &p, PAL::PAL *l, + DRAM::AbstractDRAM *d) + : AbstractFTL(p, l, d), + pPAL(l), + conf(c), + lastFreeBlock(param.pageCountToMaxPerf), + lastFreeBlockIOMap(param.ioUnitInPage), + bReclaimMore(false) { + blocks.reserve(param.totalPhysicalBlocks); + table.reserve(param.totalLogicalBlocks * param.pagesInBlock); + + for (uint32_t i = 0; i < param.totalPhysicalBlocks; i++) { + freeBlocks.emplace_back(Block(i, param.pagesInBlock, param.ioUnitInPage)); + } + + nFreeBlocks = param.totalPhysicalBlocks; + + status.totalLogicalPages = param.totalLogicalBlocks * param.pagesInBlock; + + // Allocate free blocks + for (uint32_t i = 0; i < param.pageCountToMaxPerf; i++) { + lastFreeBlock.at(i) = getFreeBlock(i); + } + + lastFreeBlockIndex = 0; + + memset(&stat, 0, sizeof(stat)); + + bRandomTweak = conf.readBoolean(CONFIG_FTL, FTL_USE_RANDOM_IO_TWEAK); + bitsetSize = bRandomTweak ? param.ioUnitInPage : 1; +} + +PageMapping::~PageMapping() {} + +bool PageMapping::initialize() { + uint64_t nPagesToWarmup; + uint64_t nPagesToInvalidate; + uint64_t nTotalLogicalPages; + uint64_t maxPagesBeforeGC; + uint64_t tick; + uint64_t valid; + uint64_t invalid; + FILLING_MODE mode; + + Request req(param.ioUnitInPage); + + debugprint(LOG_FTL_PAGE_MAPPING, "Initialization started"); + + nTotalLogicalPages = param.totalLogicalBlocks * param.pagesInBlock; + nPagesToWarmup = + nTotalLogicalPages * conf.readFloat(CONFIG_FTL, FTL_FILL_RATIO); + nPagesToInvalidate = + nTotalLogicalPages * conf.readFloat(CONFIG_FTL, FTL_INVALID_PAGE_RATIO); + mode = (FILLING_MODE)conf.readUint(CONFIG_FTL, FTL_FILLING_MODE); + maxPagesBeforeGC = + param.pagesInBlock * + (param.totalPhysicalBlocks * + (1 - conf.readFloat(CONFIG_FTL, FTL_GC_THRESHOLD_RATIO)) - + param.pageCountToMaxPerf); // # free blocks to maintain + + if (nPagesToWarmup + nPagesToInvalidate > maxPagesBeforeGC) { + warn("ftl: Too high filling ratio. Adjusting invalidPageRatio."); + nPagesToInvalidate = maxPagesBeforeGC - nPagesToWarmup; + } + + debugprint(LOG_FTL_PAGE_MAPPING, "Total logical pages: %" PRIu64, + nTotalLogicalPages); + debugprint(LOG_FTL_PAGE_MAPPING, + "Total logical pages to fill: %" PRIu64 " (%.2f %%)", + nPagesToWarmup, nPagesToWarmup * 100.f / nTotalLogicalPages); + debugprint(LOG_FTL_PAGE_MAPPING, + "Total invalidated pages to create: %" PRIu64 " (%.2f %%)", + nPagesToInvalidate, + nPagesToInvalidate * 100.f / nTotalLogicalPages); + + req.ioFlag.set(); + + // Step 1. Filling + if (mode == FILLING_MODE_0 || mode == FILLING_MODE_1) { + // Sequential + for (uint64_t i = 0; i < nPagesToWarmup; i++) { + tick = 0; + req.lpn = i; + writeInternal(req, tick, false); + } + } + else { + // Random + std::random_device rd; + std::mt19937_64 gen(rd()); + std::uniform_int_distribution dist(0, nTotalLogicalPages - 1); + + for (uint64_t i = 0; i < nPagesToWarmup; i++) { + tick = 0; + req.lpn = dist(gen); + writeInternal(req, tick, false); + } + } + + // Step 2. Invalidating + if (mode == FILLING_MODE_0) { + // Sequential + for (uint64_t i = 0; i < nPagesToInvalidate; i++) { + tick = 0; + req.lpn = i; + writeInternal(req, tick, false); + } + } + else if (mode == FILLING_MODE_1) { + // Random + // We can successfully restrict range of LPN to create exact number of + // invalid pages because we wrote in sequential mannor in step 1. + std::random_device rd; + std::mt19937_64 gen(rd()); + std::uniform_int_distribution dist(0, nPagesToWarmup - 1); + + for (uint64_t i = 0; i < nPagesToInvalidate; i++) { + tick = 0; + req.lpn = dist(gen); + writeInternal(req, tick, false); + } + } + else { + // Random + std::random_device rd; + std::mt19937_64 gen(rd()); + std::uniform_int_distribution dist(0, nTotalLogicalPages - 1); + + for (uint64_t i = 0; i < nPagesToInvalidate; i++) { + tick = 0; + req.lpn = dist(gen); + writeInternal(req, tick, false); + } + } + + // Report + calculateTotalPages(valid, invalid); + debugprint(LOG_FTL_PAGE_MAPPING, "Filling finished. Page status:"); + debugprint(LOG_FTL_PAGE_MAPPING, + " Total valid physical pages: %" PRIu64 + " (%.2f %%, target: %" PRIu64 ", error: %" PRId64 ")", + valid, valid * 100.f / nTotalLogicalPages, nPagesToWarmup, + (int64_t)(valid - nPagesToWarmup)); + debugprint(LOG_FTL_PAGE_MAPPING, + " Total invalid physical pages: %" PRIu64 + " (%.2f %%, target: %" PRIu64 ", error: %" PRId64 ")", + invalid, invalid * 100.f / nTotalLogicalPages, nPagesToInvalidate, + (int64_t)(invalid - nPagesToInvalidate)); + debugprint(LOG_FTL_PAGE_MAPPING, "Initialization finished"); + + // WAF monitoring initialization message + printf("\n=== WAF Real-time Monitoring Started ===\n"); + printf("Monitor will update every 1000 writes and after each GC event\n"); + printf("WAF = Write Amplification Factor (Device Writes / Host Writes)\n\n"); + fflush(stdout); + + return true; +} + +void PageMapping::read(Request &req, uint64_t &tick) { + uint64_t begin = tick; + + if (req.ioFlag.count() > 0) { + readInternal(req, tick); + + debugprint(LOG_FTL_PAGE_MAPPING, + "READ | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + req.lpn, begin, tick, tick - begin); + } + else { + warn("FTL got empty request"); + } + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::READ); +} + +void PageMapping::write(Request &req, uint64_t &tick) { + uint64_t begin = tick; + + if (req.ioFlag.count() > 0) { + // Update host write bytes counter + stat.host_write_bytes += req.ioFlag.count() * (param.pageSize / param.ioUnitInPage); + + writeInternal(req, tick); + + // Real-time WAF monitoring - print every 1000 writes + static uint64_t write_count = 0; + write_count++; + + if (write_count % 1000 == 0) { + double hostB = std::max(1, stat.host_write_bytes); + double waf_total = double(stat.device_write_bytes) / hostB; + double waf_gc = double(stat.device_gc_write_bytes) / hostB; + + printf("\r\33[2K[WAF Monitor] Total: %.3f | GC: %.3f | GC Count: %" PRIu64 " | Host: %.1fMB | Device: %.1fMB", + waf_total, waf_gc, stat.gcCount, + hostB / (1024.0 * 1024.0), + double(stat.device_write_bytes) / (1024.0 * 1024.0)); + fflush(stdout); + } + + debugprint(LOG_FTL_PAGE_MAPPING, + "WRITE | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + req.lpn, begin, tick, tick - begin); + } + else { + warn("FTL got empty request"); + } + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::WRITE); +} + +void PageMapping::trim(Request &req, uint64_t &tick) { + uint64_t begin = tick; + + trimInternal(req, tick); + + debugprint(LOG_FTL_PAGE_MAPPING, + "TRIM | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + req.lpn, begin, tick, tick - begin); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::TRIM); +} + +void PageMapping::format(LPNRange &range, uint64_t &tick) { + PAL::Request req(param.ioUnitInPage); + std::vector list; + + req.ioFlag.set(); + + for (auto iter = table.begin(); iter != table.end();) { + if (iter->first >= range.slpn && iter->first < range.slpn + range.nlp) { + auto &mappingList = iter->second; + + // Do trim + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + auto &mapping = mappingList.at(idx); + auto block = blocks.find(mapping.first); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + block->second.invalidate(mapping.second, idx); + + // Collect block indices + list.push_back(mapping.first); + } + + iter = table.erase(iter); + } + else { + iter++; + } + } + + // Get blocks to erase + std::sort(list.begin(), list.end()); + auto last = std::unique(list.begin(), list.end()); + list.erase(last, list.end()); + + // Do GC only in specified blocks + doGarbageCollection(list, tick); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::FORMAT); +} + +Status *PageMapping::getStatus(uint64_t lpnBegin, uint64_t lpnEnd) { + status.freePhysicalBlocks = nFreeBlocks; + + if (lpnBegin == 0 && lpnEnd >= status.totalLogicalPages) { + status.mappedLogicalPages = table.size(); + } + else { + status.mappedLogicalPages = 0; + + for (uint64_t lpn = lpnBegin; lpn < lpnEnd; lpn++) { + if (table.count(lpn) > 0) { + status.mappedLogicalPages++; + } + } + } + + return &status; +} + +float PageMapping::freeBlockRatio() { + return (float)nFreeBlocks / param.totalPhysicalBlocks; +} + +uint32_t PageMapping::convertBlockIdx(uint32_t blockIdx) { + return blockIdx % param.pageCountToMaxPerf; +} + +uint32_t PageMapping::getFreeBlock(uint32_t idx) { + uint32_t blockIndex = 0; + + if (idx >= param.pageCountToMaxPerf) { + panic("Index out of range"); + } + + if (nFreeBlocks > 0) { + // Search block which is blockIdx % param.pageCountToMaxPerf == idx + auto iter = freeBlocks.begin(); + + for (; iter != freeBlocks.end(); iter++) { + blockIndex = iter->getBlockIndex(); + + if (blockIndex % param.pageCountToMaxPerf == idx) { + break; + } + } + + // Sanity check + if (iter == freeBlocks.end()) { + // Just use first one + iter = freeBlocks.begin(); + blockIndex = iter->getBlockIndex(); + } + + // Insert found block to block list + if (blocks.find(blockIndex) != blocks.end()) { + panic("Corrupted"); + } + + blocks.emplace(blockIndex, std::move(*iter)); + + // Remove found block from free block list + freeBlocks.erase(iter); + nFreeBlocks--; + } + else { + panic("No free block left"); + } + + return blockIndex; +} + +uint32_t PageMapping::getLastFreeBlock(Bitset &iomap) { + if (!bRandomTweak || (lastFreeBlockIOMap & iomap).any()) { + // Update lastFreeBlockIndex + lastFreeBlockIndex++; + + if (lastFreeBlockIndex == param.pageCountToMaxPerf) { + lastFreeBlockIndex = 0; + } + + lastFreeBlockIOMap = iomap; + } + else { + lastFreeBlockIOMap |= iomap; + } + + auto freeBlock = blocks.find(lastFreeBlock.at(lastFreeBlockIndex)); + + // Sanity check + if (freeBlock == blocks.end()) { + panic("Corrupted"); + } + + // If current free block is full, get next block + if (freeBlock->second.getNextWritePageIndex() == param.pagesInBlock) { + lastFreeBlock.at(lastFreeBlockIndex) = getFreeBlock(lastFreeBlockIndex); + + bReclaimMore = true; + } + + return lastFreeBlock.at(lastFreeBlockIndex); +} + +// calculate weight of each block regarding victim selection policy +void PageMapping::calculateVictimWeight( + std::vector> &weight, const EVICT_POLICY policy, + uint64_t tick) { + float temp; + + weight.reserve(blocks.size()); + + switch (policy) { + case POLICY_GREEDY: + case POLICY_RANDOM: + case POLICY_DCHOICE: + for (auto &iter : blocks) { + if (iter.second.getNextWritePageIndex() != param.pagesInBlock) { + continue; + } + + weight.push_back({iter.first, iter.second.getValidPageCountRaw()}); + } + + break; + case POLICY_COST_BENEFIT: + for (auto &iter : blocks) { + if (iter.second.getNextWritePageIndex() != param.pagesInBlock) { + continue; + } + + temp = (float)(iter.second.getValidPageCountRaw()) / param.pagesInBlock; + + weight.push_back( + {iter.first, + temp / ((1 - temp) * (tick - iter.second.getLastAccessedTime()))}); + } + + break; + default: + panic("Invalid evict policy"); + } +} + +void PageMapping::selectVictimBlock(std::vector &list, + uint64_t &tick) { + static const GC_MODE mode = (GC_MODE)conf.readInt(CONFIG_FTL, FTL_GC_MODE); + static const EVICT_POLICY policy = + (EVICT_POLICY)conf.readInt(CONFIG_FTL, FTL_GC_EVICT_POLICY); + static uint32_t dChoiceParam = + conf.readUint(CONFIG_FTL, FTL_GC_D_CHOICE_PARAM); + uint64_t nBlocks = conf.readUint(CONFIG_FTL, FTL_GC_RECLAIM_BLOCK); + std::vector> weight; + + list.clear(); + + // Calculate number of blocks to reclaim + if (mode == GC_MODE_0) { + // DO NOTHING + } + else if (mode == GC_MODE_1) { + static const float t = conf.readFloat(CONFIG_FTL, FTL_GC_RECLAIM_THRESHOLD); + + nBlocks = param.totalPhysicalBlocks * t - nFreeBlocks; + } + else { + panic("Invalid GC mode"); + } + + // reclaim one more if last free block fully used + if (bReclaimMore) { + nBlocks += param.pageCountToMaxPerf; + + bReclaimMore = false; + } + + // Calculate weights of all blocks + calculateVictimWeight(weight, policy, tick); + + if (policy == POLICY_RANDOM || policy == POLICY_DCHOICE) { + uint64_t randomRange = + policy == POLICY_RANDOM ? nBlocks : dChoiceParam * nBlocks; + std::random_device rd; + std::mt19937 gen(rd()); + std::uniform_int_distribution dist(0, weight.size() - 1); + std::vector> selected; + + while (selected.size() < randomRange) { + uint64_t idx = dist(gen); + + if (weight.at(idx).first < std::numeric_limits::max()) { + selected.push_back(weight.at(idx)); + weight.at(idx).first = std::numeric_limits::max(); + } + } + + weight = std::move(selected); + } + + // Sort weights + std::sort( + weight.begin(), weight.end(), + [](std::pair a, std::pair b) -> bool { + return a.second < b.second; + }); + + // Select victims from the blocks with the lowest weight + nBlocks = MIN(nBlocks, weight.size()); + + for (uint64_t i = 0; i < nBlocks; i++) { + list.push_back(weight.at(i).first); + } + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::SELECT_VICTIM_BLOCK); +} + +void PageMapping::doGarbageCollection(std::vector &blocksToReclaim, + uint64_t &tick) { + PAL::Request req(param.ioUnitInPage); + std::vector readRequests; + std::vector writeRequests; + std::vector eraseRequests; + std::vector lpns; + Bitset bit(param.ioUnitInPage); + uint64_t beginAt = 0; + uint64_t readFinishedAt = tick; + uint64_t writeFinishedAt = tick; + uint64_t eraseFinishedAt = tick; + + if (blocksToReclaim.size() == 0) { + return; + } + + // For all blocks to reclaim, collecting request structure only + for (auto &iter : blocksToReclaim) { + auto block = blocks.find(iter); + + if (block == blocks.end()) { + panic("Invalid block"); + } + + // Copy valid pages to free block + for (uint32_t pageIndex = 0; pageIndex < param.pagesInBlock; pageIndex++) { + // Valid? + if (block->second.getPageInfo(pageIndex, lpns, bit)) { + if (!bRandomTweak) { + bit.set(); + } + + // Retrive free block + auto freeBlock = blocks.find(getLastFreeBlock(bit)); + + // Issue Read + req.blockIndex = block->first; + req.pageIndex = pageIndex; + req.ioFlag = bit; + + readRequests.push_back(req); + + // Update mapping table + uint32_t newBlockIdx = freeBlock->first; + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (bit.test(idx)) { + // Invalidate + block->second.invalidate(pageIndex, idx); + + auto mappingList = table.find(lpns.at(idx)); + + if (mappingList == table.end()) { + panic("Invalid mapping table entry"); + } + + pDRAM->read(&(*mappingList), 8 * param.ioUnitInPage, tick); + + auto &mapping = mappingList->second.at(idx); + + uint32_t newPageIdx = freeBlock->second.getNextWritePageIndex(idx); + + mapping.first = newBlockIdx; + mapping.second = newPageIdx; + + freeBlock->second.write(newPageIdx, lpns.at(idx), idx, beginAt); + + // Issue Write + req.blockIndex = newBlockIdx; + req.pageIndex = newPageIdx; + + if (bRandomTweak) { + req.ioFlag.reset(); + req.ioFlag.set(idx); + } + else { + req.ioFlag.set(); + } + + writeRequests.push_back(req); + + stat.validPageCopies++; + } + } + + stat.validSuperPageCopies++; + } + } + + // Erase block + req.blockIndex = block->first; + req.pageIndex = 0; + req.ioFlag.set(); + + eraseRequests.push_back(req); + } + + // Do actual I/O here + // This handles PAL2 limitation (SIGSEGV, infinite loop, or so-on) + for (auto &iter : readRequests) { + beginAt = tick; + + pPAL->read(iter, beginAt); + + readFinishedAt = MAX(readFinishedAt, beginAt); + } + + for (auto &iter : writeRequests) { + beginAt = readFinishedAt; + + pPAL->write(iter, beginAt); + + // Update GC write bytes counters + uint32_t writeBytes = iter.ioFlag.count() * (param.pageSize / param.ioUnitInPage); + stat.device_write_bytes += writeBytes; + stat.device_gc_write_bytes += writeBytes; + + writeFinishedAt = MAX(writeFinishedAt, beginAt); + } + + for (auto &iter : eraseRequests) { + beginAt = readFinishedAt; + + eraseInternal(iter, beginAt); + + eraseFinishedAt = MAX(eraseFinishedAt, beginAt); + } + + tick = MAX(writeFinishedAt, eraseFinishedAt); + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::DO_GARBAGE_COLLECTION); +} + +void PageMapping::readInternal(Request &req, uint64_t &tick) { + PAL::Request palRequest(req); + uint64_t beginAt; + uint64_t finishedAt = tick; + + auto mappingList = table.find(req.lpn); + + if (mappingList != table.end()) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + } + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + auto &mapping = mappingList->second.at(idx); + + if (mapping.first < param.totalPhysicalBlocks && + mapping.second < param.pagesInBlock) { + palRequest.blockIndex = mapping.first; + palRequest.pageIndex = mapping.second; + + if (bRandomTweak) { + palRequest.ioFlag.reset(); + palRequest.ioFlag.set(idx); + } + else { + palRequest.ioFlag.set(); + } + + auto block = blocks.find(palRequest.blockIndex); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + beginAt = tick; + + block->second.read(palRequest.pageIndex, idx, beginAt); + pPAL->read(palRequest, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + } + } + + tick = finishedAt; + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::READ_INTERNAL); + } +} + +void PageMapping::writeInternal(Request &req, uint64_t &tick, bool sendToPAL) { + PAL::Request palRequest(req); + std::unordered_map::iterator block; + auto mappingList = table.find(req.lpn); + uint64_t beginAt; + uint64_t finishedAt = tick; + bool readBeforeWrite = false; + + if (mappingList != table.end()) { + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + auto &mapping = mappingList->second.at(idx); + + if (mapping.first < param.totalPhysicalBlocks && + mapping.second < param.pagesInBlock) { + block = blocks.find(mapping.first); + + // Invalidate current page + block->second.invalidate(mapping.second, idx); + } + } + } + } + else { + // Create empty mapping + auto ret = table.emplace( + req.lpn, + std::vector>( + bitsetSize, {param.totalPhysicalBlocks, param.pagesInBlock})); + + if (!ret.second) { + panic("Failed to insert new mapping"); + } + + mappingList = ret.first; + } + + // Write data to free block + block = blocks.find(getLastFreeBlock(req.ioFlag)); + + if (block == blocks.end()) { + panic("No such block"); + } + + if (sendToPAL) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + pDRAM->write(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + pDRAM->write(&(*mappingList), 8, tick); + } + } + + if (!bRandomTweak && !req.ioFlag.all()) { + // We have to read old data + readBeforeWrite = true; + } + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + uint32_t pageIndex = block->second.getNextWritePageIndex(idx); + auto &mapping = mappingList->second.at(idx); + + beginAt = tick; + + block->second.write(pageIndex, req.lpn, idx, beginAt); + + // Read old data if needed (Only executed when bRandomTweak = false) + // Maybe some other init procedures want to perform 'partial-write' + // So check sendToPAL variable + if (readBeforeWrite && sendToPAL) { + palRequest.blockIndex = mapping.first; + palRequest.pageIndex = mapping.second; + + // We don't need to read old data + palRequest.ioFlag = req.ioFlag; + palRequest.ioFlag.flip(); + + pPAL->read(palRequest, beginAt); + } + + // update mapping to table + mapping.first = block->first; + mapping.second = pageIndex; + + if (sendToPAL) { + palRequest.blockIndex = block->first; + palRequest.pageIndex = pageIndex; + + if (bRandomTweak) { + palRequest.ioFlag.reset(); + palRequest.ioFlag.set(idx); + } + else { + palRequest.ioFlag.set(); + } + + pPAL->write(palRequest, beginAt); + + // Update device write bytes counters + uint32_t writeBytes = palRequest.ioFlag.count() * (param.pageSize / param.ioUnitInPage); + stat.device_write_bytes += writeBytes; + stat.device_user_write_bytes += writeBytes; + } + + finishedAt = MAX(finishedAt, beginAt); + } + } + + // Exclude CPU operation when initializing + if (sendToPAL) { + tick = finishedAt; + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::WRITE_INTERNAL); + } + + // GC if needed + // I assumed that init procedure never invokes GC + static float gcThreshold = conf.readFloat(CONFIG_FTL, FTL_GC_THRESHOLD_RATIO); + + if (freeBlockRatio() < gcThreshold) { + if (!sendToPAL) { + panic("ftl: GC triggered while in initialization"); + } + + std::vector list; + uint64_t beginAt = tick; + + selectVictimBlock(list, beginAt); + + debugprint(LOG_FTL_PAGE_MAPPING, + "GC | On-demand | %u blocks will be reclaimed", list.size()); + + doGarbageCollection(list, beginAt); + + debugprint(LOG_FTL_PAGE_MAPPING, + "GC | Done | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", tick, + beginAt, beginAt - tick); + + stat.gcCount++; + stat.reclaimedBlocks += list.size(); + + // Real-time WAF monitoring after GC + double hostB = std::max(1, stat.host_write_bytes); + double waf_total = double(stat.device_write_bytes) / hostB; + double waf_gc = double(stat.device_gc_write_bytes) / hostB; + + printf("\r\33[2K[GC Event] WAF Total: %.3f | GC: %.3f | GC Count: %" PRIu64 " | Blocks Reclaimed: %zu\n", + waf_total, waf_gc, stat.gcCount, list.size()); + fflush(stdout); + } +} + +void PageMapping::trimInternal(Request &req, uint64_t &tick) { + auto mappingList = table.find(req.lpn); + + if (mappingList != table.end()) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + } + + // Do trim + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + auto &mapping = mappingList->second.at(idx); + auto block = blocks.find(mapping.first); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + block->second.invalidate(mapping.second, idx); + } + + // Remove mapping + table.erase(mappingList); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::TRIM_INTERNAL); + } +} + +void PageMapping::eraseInternal(PAL::Request &req, uint64_t &tick) { + static uint64_t threshold = + conf.readUint(CONFIG_FTL, FTL_BAD_BLOCK_THRESHOLD); + auto block = blocks.find(req.blockIndex); + + // Sanity checks + if (block == blocks.end()) { + panic("No such block"); + } + + if (block->second.getValidPageCount() != 0) { + panic("There are valid pages in victim block"); + } + + // Erase block + block->second.erase(); + + pPAL->erase(req, tick); + + // Check erase count + uint32_t erasedCount = block->second.getEraseCount(); + + if (erasedCount < threshold) { + // Reverse search + auto iter = freeBlocks.end(); + + while (true) { + iter--; + + if (iter->getEraseCount() <= erasedCount) { + // emplace: insert before pos + iter++; + + break; + } + + if (iter == freeBlocks.begin()) { + break; + } + } + + // Insert block to free block list + freeBlocks.emplace(iter, std::move(block->second)); + nFreeBlocks++; + } + + // Remove block from block list + blocks.erase(block); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::ERASE_INTERNAL); +} + +float PageMapping::calculateWearLeveling() { + uint64_t totalEraseCnt = 0; + uint64_t sumOfSquaredEraseCnt = 0; + uint64_t numOfBlocks = param.totalLogicalBlocks; + uint64_t eraseCnt; + + for (auto &iter : blocks) { + eraseCnt = iter.second.getEraseCount(); + totalEraseCnt += eraseCnt; + sumOfSquaredEraseCnt += eraseCnt * eraseCnt; + } + + // freeBlocks is sorted + // Calculate from backward, stop when eraseCnt is zero + for (auto riter = freeBlocks.rbegin(); riter != freeBlocks.rend(); riter++) { + eraseCnt = riter->getEraseCount(); + + if (eraseCnt == 0) { + break; + } + + totalEraseCnt += eraseCnt; + sumOfSquaredEraseCnt += eraseCnt * eraseCnt; + } + + if (sumOfSquaredEraseCnt == 0) { + return -1; // no meaning of wear-leveling + } + + return (float)totalEraseCnt * totalEraseCnt / + (numOfBlocks * sumOfSquaredEraseCnt); +} + +void PageMapping::calculateTotalPages(uint64_t &valid, uint64_t &invalid) { + valid = 0; + invalid = 0; + + for (auto &iter : blocks) { + valid += iter.second.getValidPageCount(); + invalid += iter.second.getDirtyPageCount(); + } +} + +void PageMapping::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "page_mapping.gc.count"; + temp.desc = "Total GC count"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.gc.reclaimed_blocks"; + temp.desc = "Total reclaimed blocks in GC"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.gc.superpage_copies"; + temp.desc = "Total copied valid superpages during GC"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.gc.page_copies"; + temp.desc = "Total copied valid pages during GC"; + list.push_back(temp); + + // For the exact definition, see following paper: + // Li, Yongkun, Patrick PC Lee, and John Lui. + // "Stochastic modeling of large-scale solid-state storage systems: analysis, + // design tradeoffs and optimization." ACM SIGMETRICS (2013) + temp.name = prefix + "page_mapping.wear_leveling"; + temp.desc = "Wear-leveling factor"; + list.push_back(temp); + + // Byte counters for tracking Write Amplification + temp.name = prefix + "page_mapping.bytes.host_write"; + temp.desc = "Total bytes written by host"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.bytes.device_write"; + temp.desc = "Total bytes written to device"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.bytes.device_user_write"; + temp.desc = "Total user bytes written to device"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.bytes.device_gc_write"; + temp.desc = "Total GC bytes written to device"; + list.push_back(temp); + + // Write Amplification Factor statistics + temp.name = prefix + "page_mapping.wa.total"; + temp.desc = "Internal WAF (bytes) = device/host"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.wa.user"; + temp.desc = "User-only WAF (bytes) = device_user/host"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.wa.gc"; + temp.desc = "GC-only WAF (bytes) = device_gc/host"; + list.push_back(temp); +} + +void PageMapping::getStatValues(std::vector &values) { + values.push_back(stat.gcCount); + values.push_back(stat.reclaimedBlocks); + values.push_back(stat.validSuperPageCopies); + values.push_back(stat.validPageCopies); + values.push_back(calculateWearLeveling()); + + // Push byte counters + values.push_back(stat.host_write_bytes); + values.push_back(stat.device_write_bytes); + values.push_back(stat.device_user_write_bytes); + values.push_back(stat.device_gc_write_bytes); + + // Calculate and push Write Amplification Factors + double hostB = std::max(1, stat.host_write_bytes); + values.push_back(double(stat.device_write_bytes) / hostB); // Total WAF + values.push_back(double(stat.device_user_write_bytes) / hostB); // User WAF + values.push_back(double(stat.device_gc_write_bytes) / hostB); // GC WAF +} + +void PageMapping::resetStatValues() { + memset(&stat, 0, sizeof(stat)); +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/page_mapping.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/page_mapping.hh new file mode 100644 index 0000000000..b870730ef9 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/ftl/page_mapping.hh @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_PAGE_MAPPING__ +#define __FTL_PAGE_MAPPING__ + +#include +#include +#include + +#include "ftl/abstract_ftl.hh" +#include "ftl/common/block.hh" +#include "ftl/ftl.hh" +#include "pal/pal.hh" + +namespace SimpleSSD { + +namespace FTL { + +class PageMapping : public AbstractFTL { + private: + PAL::PAL *pPAL; + + ConfigReader &conf; + + std::unordered_map>> + table; + std::unordered_map blocks; + std::list freeBlocks; + uint32_t nFreeBlocks; // For some libraries which std::list::size() is O(n) + std::vector lastFreeBlock; + Bitset lastFreeBlockIOMap; + uint32_t lastFreeBlockIndex; + + bool bReclaimMore; + bool bRandomTweak; + uint32_t bitsetSize; + + struct { + uint64_t gcCount; + uint64_t reclaimedBlocks; + uint64_t validSuperPageCopies; + uint64_t validPageCopies; + + // Byte counters for Write Amplification calculation + uint64_t host_write_bytes; + uint64_t device_write_bytes; + uint64_t device_user_write_bytes; + uint64_t device_gc_write_bytes; + } stat; + + float freeBlockRatio(); + uint32_t convertBlockIdx(uint32_t); + uint32_t getFreeBlock(uint32_t); + uint32_t getLastFreeBlock(Bitset &); + void calculateVictimWeight(std::vector> &, + const EVICT_POLICY, uint64_t); + void selectVictimBlock(std::vector &, uint64_t &); + void doGarbageCollection(std::vector &, uint64_t &); + + float calculateWearLeveling(); + void calculateTotalPages(uint64_t &, uint64_t &); + + void readInternal(Request &, uint64_t &); + void writeInternal(Request &, uint64_t &, bool = true); + void trimInternal(Request &, uint64_t &); + void eraseInternal(PAL::Request &, uint64_t &); + + public: + PageMapping(ConfigReader &, Parameter &, PAL::PAL *, DRAM::AbstractDRAM *); + ~PageMapping(); + + bool initialize() override; + + void read(Request &, uint64_t &) override; + void write(Request &, uint64_t &) override; + void trim(Request &, uint64_t &) override; + + void format(LPNRange &, uint64_t &) override; + + Status *getStatus(uint64_t, uint64_t) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/hil.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/hil.cc new file mode 100644 index 0000000000..6f0917da2c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/hil.cc @@ -0,0 +1,288 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/hil.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +HIL::HIL(ConfigReader &c) : conf(c), reqCount(0), lastScheduled(0) { + pICL = new ICL::ICL(conf); + + memset(&stat, 0, sizeof(stat)); + + completionEvent = allocate([this](uint64_t) { completion(); }); +} + +HIL::~HIL() { + delete pICL; +} + +void HIL::read(Request &req) { + DMAFunction doRead = [this](uint64_t beginAt, void *context) { + auto pReq = (Request *)context; + uint64_t tick = beginAt; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, + "READ | REQ %7u | LCA %" PRIu64 " + %" PRIu64 " | BYTE %" PRIu64 + " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp, pReq->offset, + pReq->length); + + ICL::Request reqInternal(*pReq); + pICL->read(reqInternal, tick); + + stat.request[0]++; + stat.iosize[0] += pReq->length; + updateBusyTime(0, beginAt, tick); + updateBusyTime(2, beginAt, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::READ, doRead, new Request(req)); +} + +void HIL::write(Request &req) { + DMAFunction doWrite = [this](uint64_t beginAt, void *context) { + auto pReq = (Request *)context; + uint64_t tick = beginAt; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, + "WRITE | REQ %7u | LCA %" PRIu64 " + %" PRIu64 " | BYTE %" PRIu64 + " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp, pReq->offset, + pReq->length); + + ICL::Request reqInternal(*pReq); + pICL->write(reqInternal, tick); + + stat.request[1]++; + stat.iosize[1] += pReq->length; + updateBusyTime(1, beginAt, tick); + updateBusyTime(2, beginAt, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::WRITE, doWrite, new Request(req)); +} + +void HIL::flush(Request &req) { + DMAFunction doFlush = [this](uint64_t tick, void *context) { + auto pReq = (Request *)context; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, "FLUSH | REQ %7u | LCA %" PRIu64 " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp); + + pICL->flush(pReq->range, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::FLUSH, doFlush, new Request(req)); +} + +void HIL::trim(Request &req) { + DMAFunction doFlush = [this](uint64_t tick, void *context) { + auto pReq = (Request *)context; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, "TRIM | REQ %7u | LCA %" PRIu64 " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp); + + pICL->trim(pReq->range, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::FLUSH, doFlush, new Request(req)); +} + +void HIL::format(Request &req, bool erase) { + DMAFunction doFlush = [this, erase](uint64_t tick, void *context) { + auto pReq = (Request *)context; + + debugprint(LOG_HIL, "FORMAT| LCA %" PRIu64 " + %" PRIu64, pReq->reqID, + pReq->range.slpn, pReq->range.nlp); + + if (erase) { + pICL->format(pReq->range, tick); + } + else { + pICL->trim(pReq->range, tick); + } + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::FLUSH, doFlush, new Request(req)); +} + +void HIL::getLPNInfo(uint64_t &totalLogicalPages, uint32_t &logicalPageSize) { + pICL->getLPNInfo(totalLogicalPages, logicalPageSize); +} + +uint64_t HIL::getUsedPageCount(uint64_t lcaBegin, uint64_t lcaEnd) { + return pICL->getUsedPageCount(lcaBegin, lcaEnd); +} + +void HIL::updateBusyTime(int idx, uint64_t begin, uint64_t end) { + if (end <= stat.lastBusyAt[idx]) { + return; + } + + if (begin < stat.lastBusyAt[idx]) { + stat.busy[idx] += end - stat.lastBusyAt[idx]; + } + else { + stat.busy[idx] += end - begin; + } + + stat.lastBusyAt[idx] = end; +} + +void HIL::updateCompletion() { + if (completionQueue.size() > 0) { + if (lastScheduled != completionQueue.top().finishedAt) { + lastScheduled = completionQueue.top().finishedAt; + schedule(completionEvent, lastScheduled); + } + } +} + +void HIL::completion() { + uint64_t tick = getTick(); + + while (completionQueue.size() > 0) { + auto &req = completionQueue.top(); + + if (req.finishedAt <= tick) { + req.function(tick, req.context); + + completionQueue.pop(); + } + else { + break; + } + } + + updateCompletion(); +} + +void HIL::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "read.request_count"; + temp.desc = "Read request count"; + list.push_back(temp); + + temp.name = prefix + "read.bytes"; + temp.desc = "Read data size in byte"; + list.push_back(temp); + + temp.name = prefix + "read.busy"; + temp.desc = "Device busy time when read"; + list.push_back(temp); + + temp.name = prefix + "write.request_count"; + temp.desc = "Write request count"; + list.push_back(temp); + + temp.name = prefix + "write.bytes"; + temp.desc = "Write data size in byte"; + list.push_back(temp); + + temp.name = prefix + "write.busy"; + temp.desc = "Device busy time when write"; + list.push_back(temp); + + temp.name = prefix + "request_count"; + temp.desc = "Total request count"; + list.push_back(temp); + + temp.name = prefix + "bytes"; + temp.desc = "Total data size in byte"; + list.push_back(temp); + + temp.name = prefix + "busy"; + temp.desc = "Total device busy time"; + list.push_back(temp); + + pICL->getStatList(list, prefix); +} + +void HIL::getStatValues(std::vector &values) { + values.push_back(stat.request[0]); + values.push_back(stat.iosize[0]); + values.push_back(stat.busy[0]); + values.push_back(stat.request[1]); + values.push_back(stat.iosize[1]); + values.push_back(stat.busy[1]); + values.push_back(stat.request[0] + stat.request[1]); + values.push_back(stat.iosize[0] + stat.iosize[1]); + values.push_back(stat.busy[2]); + + pICL->getStatValues(values); +} + +void HIL::resetStatValues() { + memset(&stat, 0, sizeof(stat)); + + pICL->resetStatValues(); +} + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/hil.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/hil.hh new file mode 100644 index 0000000000..c5ba045ce0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/hil.hh @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_HIL__ +#define __HIL_HIL__ + +#include + +#include "icl/icl.hh" +#include "sim/dma_interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +class HIL : public StatObject { + private: + ConfigReader &conf; + ICL::ICL *pICL; + + uint64_t reqCount; + + uint64_t lastScheduled; + Event completionEvent; + std::priority_queue, Request> completionQueue; + + struct { + uint64_t request[2]; + uint64_t busy[3]; + uint64_t iosize[2]; + uint64_t lastBusyAt[3]; + } stat; + + void updateBusyTime(int, uint64_t, uint64_t); + void updateCompletion(); + void completion(); + + public: + HIL(ConfigReader &); + ~HIL(); + + void read(Request &); + void write(Request &); + void flush(Request &); + void trim(Request &); + + void format(Request &, bool); + + void getLPNInfo(uint64_t &, uint32_t &); + uint64_t getUsedPageCount(uint64_t, uint64_t); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/abstract_subsystem.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/abstract_subsystem.cc new file mode 100644 index 0000000000..1619ff2614 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/abstract_subsystem.cc @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/abstract_subsystem.hh" + +#include "hil/nvme/controller.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +AbstractSubsystem::AbstractSubsystem(Controller *c, ConfigData &cfg) + : pParent(c), cfgdata(cfg), conf(*cfg.pConfigReader) {} + +AbstractSubsystem::~AbstractSubsystem() {} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/abstract_subsystem.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/abstract_subsystem.hh new file mode 100644 index 0000000000..d2b816f252 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/abstract_subsystem.hh @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_ABSTRACT_SUBSYSTEM__ +#define __HIL_NVME_ABSTRACT_SUBSYSTEM__ + +#include "hil/nvme/namespace.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Controller; + +class AbstractSubsystem : public StatObject { + protected: + Controller *pParent; + + ConfigData &cfgdata; + ConfigReader &conf; + + public: + AbstractSubsystem(Controller *, ConfigData &); + virtual ~AbstractSubsystem(); + + virtual void init() = 0; + virtual void submitCommand(SQEntryWrapper &, RequestFunction) = 0; + virtual void getNVMCapacity(uint64_t &, uint64_t &) = 0; + virtual uint32_t validNamespaceCount() = 0; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/config.cc new file mode 100644 index 0000000000..e9e83b485b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/config.cc @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +const char NAME_PCIE_GEN[] = "PCIEGeneration"; +const char NAME_PCIE_LANE[] = "PCIELane"; +const char NAME_AXI_BUS_WIDTH[] = "AXIBusWidth"; +const char NAME_AXI_CLOCK[] = "AXIClock"; +const char NAME_FIFO_UNIT[] = "FIFOTransferUnit"; +const char NAME_WORK_INTERVAL[] = "WorkInterval"; +const char NAME_MAX_REQUEST_COUNT[] = "MaxRequestCount"; +const char NAME_MAX_IO_CQUEUE[] = "MaxIOCQueue"; +const char NAME_MAX_IO_SQUEUE[] = "MaxIOSQueue"; +const char NAME_WRR_HIGH[] = "WRRHigh"; +const char NAME_WRR_MEDIUM[] = "WRRMedium"; +const char NAME_ENABLE_DEFAULT_NAMESPACE[] = "DefaultNamespace"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_ENABLE_DISK_IMAGE[] = "EnableDiskImage"; +const char NAME_STRICT_DISK_SIZE[] = "StrictSizeCheck"; +const char NAME_DISK_IMAGE_PATH[] = "DiskImageFile"; +const char NAME_USE_COW_DISK[] = "UseCopyOnWriteDisk"; + +Config::Config() { + pcieGen = PCIExpress::PCIE_3_X; + pcieLane = 4; + axiWidth = ARM::AXI::BUS_128BIT; + axiClock = 250000000; + fifoUnit = 4096; + workInterval = 50000; + maxRequestCount = 4; + maxIOCQueue = 16; + maxIOSQueue = 16; + wrrHigh = 2; + wrrMedium = 2; + lbaSize = 512; + defaultNamespace = 1; + enableDiskImage = false; + strictDiskSize = false; + useCopyOnWriteDisk = false; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_PCIE_GEN)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + pcieGen = PCIExpress::PCIE_1_X; + break; + case 1: + pcieGen = PCIExpress::PCIE_2_X; + break; + case 2: + pcieGen = PCIExpress::PCIE_3_X; + break; + default: + panic("Invalid PCI Express Generation"); + break; + } + } + else if (MATCH_NAME(NAME_PCIE_LANE)) { + pcieLane = (uint8_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_AXI_BUS_WIDTH)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + axiWidth = ARM::AXI::BUS_32BIT; + break; + case 1: + axiWidth = ARM::AXI::BUS_64BIT; + break; + case 2: + axiWidth = ARM::AXI::BUS_128BIT; + break; + case 3: + axiWidth = ARM::AXI::BUS_256BIT; + break; + case 4: + axiWidth = ARM::AXI::BUS_512BIT; + break; + case 5: + axiWidth = ARM::AXI::BUS_1024BIT; + break; + default: + panic("Invalid AXI Stream Bus Width"); + break; + } + } + else if (MATCH_NAME(NAME_AXI_CLOCK)) { + axiClock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FIFO_UNIT)) { + fifoUnit = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WORK_INTERVAL)) { + workInterval = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_REQUEST_COUNT)) { + maxRequestCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_IO_CQUEUE)) { + maxIOCQueue = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_IO_SQUEUE)) { + maxIOSQueue = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WRR_HIGH)) { + wrrHigh = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WRR_MEDIUM)) { + wrrMedium = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DEFAULT_NAMESPACE)) { + defaultNamespace = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DISK_IMAGE)) { + enableDiskImage = convertBool(value); + } + else if (MATCH_NAME(NAME_STRICT_DISK_SIZE)) { + strictDiskSize = convertBool(value); + } + else if (strncmp(name, NAME_DISK_IMAGE_PATH, strlen(NAME_DISK_IMAGE_PATH)) == + 0) { + uint16_t index = + (uint16_t)strtoul(name + strlen(NAME_DISK_IMAGE_PATH), nullptr, 10); + + if (index > 0) { + auto find = diskImagePaths.find(index); + + if (find == diskImagePaths.end()) { + diskImagePaths.insert({index, value}); + } + else { + find->second = value; + } + } + } + else if (MATCH_NAME(NAME_USE_COW_DISK)) { + useCopyOnWriteDisk = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (popcount(lbaSize) != 1 || lbaSize < 512) { + panic("Invalid LBA size"); + } + if (maxRequestCount == 0) { + panic("MaxRequestCount should be larger then 0"); + } + if (fifoUnit > 4096) { + panic("FIFOTransferUnit should be less than or equal to 4096"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case NVME_PCIE_GEN: + ret = pcieGen; + break; + case NVME_AXI_BUS_WIDTH: + ret = axiWidth; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case NVME_PCIE_LANE: + ret = pcieLane; + break; + case NVME_AXI_CLOCK: + ret = axiClock; + break; + case NVME_FIFO_UNIT: + ret = fifoUnit; + break; + case NVME_WORK_INTERVAL: + ret = workInterval; + break; + case NVME_MAX_REQUEST_COUNT: + ret = maxRequestCount; + break; + case NVME_MAX_IO_CQUEUE: + ret = maxIOCQueue; + break; + case NVME_MAX_IO_SQUEUE: + ret = maxIOSQueue; + break; + case NVME_WRR_HIGH: + ret = wrrHigh; + break; + case NVME_WRR_MEDIUM: + ret = wrrMedium; + break; + case NVME_ENABLE_DEFAULT_NAMESPACE: + ret = defaultNamespace; + break; + case NVME_LBA_SIZE: + ret = lbaSize; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret(""); + + if (idx >= NVME_DISK_IMAGE_PATH) { + idx -= NVME_DISK_IMAGE_PATH; + + auto find = diskImagePaths.find((uint16_t)idx); + + if (find != diskImagePaths.end()) { + ret = find->second; + } + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case NVME_ENABLE_DISK_IMAGE: + ret = enableDiskImage; + break; + case NVME_STRICT_DISK_SIZE: + ret = strictDiskSize; + break; + case NVME_USE_COW_DISK: + ret = useCopyOnWriteDisk; + break; + } + + return ret; +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/config.hh new file mode 100644 index 0000000000..266ad35102 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/config.hh @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_CONFIG__ +#define __HIL_NVME_CONFIG__ + +#include + +#include "sim/base_config.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +typedef enum { + NVME_PCIE_GEN, + NVME_PCIE_LANE, + NVME_AXI_BUS_WIDTH, + NVME_AXI_CLOCK, + NVME_FIFO_UNIT, + NVME_WORK_INTERVAL, + NVME_MAX_REQUEST_COUNT, + NVME_MAX_IO_CQUEUE, + NVME_MAX_IO_SQUEUE, + NVME_WRR_HIGH, + NVME_WRR_MEDIUM, + NVME_ENABLE_DEFAULT_NAMESPACE, + NVME_LBA_SIZE, + NVME_ENABLE_DISK_IMAGE, + NVME_STRICT_DISK_SIZE, + NVME_DISK_IMAGE_PATH, + NVME_USE_COW_DISK +} NVME_CONFIG; + +class Config : public BaseConfig { + private: + PCIExpress::PCIE_GEN pcieGen; //!< Default: PCIE_3_X + uint8_t pcieLane; //!< Default: 4 + ARM::AXI::BUS_WIDTH axiWidth; //!< Default: BUS_128BIT + uint64_t axiClock; //!< Default: 250000000 (250MHz) + uint64_t fifoUnit; //!< Default: 4096 + uint64_t workInterval; //!< Default: 50000 (50ns) + uint64_t maxRequestCount; //!< Default: 4 + uint16_t maxIOCQueue; //!< Default: 16 + uint16_t maxIOSQueue; //!< Default: 16 + uint16_t wrrHigh; //!< Default: 2 + uint16_t wrrMedium; //!< Default: 2 + uint64_t lbaSize; //!< Default: 512 + uint16_t defaultNamespace; //!< Default: 1 + bool enableDiskImage; //!< Default: False + bool strictDiskSize; //!< Default: False + bool useCopyOnWriteDisk; //!< Default: False + std::unordered_map diskImagePaths; //!< Default: "" + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/controller.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/controller.cc new file mode 100644 index 0000000000..36db1252b2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/controller.cc @@ -0,0 +1,1839 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/controller.hh" + +#include +#include + +#include "hil/nvme/interface.hh" +#include "hil/nvme/ocssd.hh" +#include "hil/nvme/subsystem.hh" +#include "util/algorithm.hh" +#include "util/fifo.hh" +#include "util/interface.hh" + +#define BOOLEAN_STRING(b) ((b) ? "true" : "false") + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +RegisterTable::_RegisterTable() { + memset(data, 0, 64); +} + +Controller::Controller(Interface *intrface, ConfigReader &c) + : pParent(intrface), + adminQueueInited(false), + interruptMask(0), + shutdownReserved(false), + aggregationTime(0), + aggregationThreshold(0), + conf(c) { + ARM::AXI::BUS_WIDTH axiWidth; + uint64_t axiClock; + + // Get AXI setting + axiWidth = (ARM::AXI::BUS_WIDTH)conf.readInt(CONFIG_NVME, NVME_AXI_BUS_WIDTH); + axiClock = conf.readUint(CONFIG_NVME, NVME_AXI_CLOCK); + + // Allocate array for Command Queues + cqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_CQUEUE) + 1; + sqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_SQUEUE) + 1; + + ppCQueue = (CQueue **)calloc(cqsize, sizeof(CQueue *)); + ppSQueue = (SQueue **)calloc(sqsize, sizeof(SQueue *)); + + // [Bits ] Name : Description : Current Setting + // [63:56] Reserved + // [55:52] MPSMZX: Memory Page Size Maximum : 2^14 Bytes + // [51:48] MPSMIN: Memory Page Size Minimum : 2^12 Bytes + // [47:45] Reserved + // [44:37] CSS : Command Sets Supported : NVM command set + // [36:36] NSSRS : NVM Subsystem Reset Supported : No + // [35:32] DSTRD : Doorbell Stride : 0 (4 bytes) + // [31:24] TO : Timeout : 40 * 500ms + // [23:19] Reserved + // [18:17] AMS : Arbitration Mechanism Supported : Weighted Round Robin + // [16:16] CQR : Contiguous Queues Required : Yes + // [15:00] MQES : Maximum Queue Entries Supported : 4096 Entries + registers.capabilities = 0x0020002028010FFF; + registers.version = 0x00010201; // NVMe 1.2.1 + + FIFOParam fifoParam; + + // See Xilinx Gen3 Integrated Block for PCIe + fifoParam.rqSize = 8192; + fifoParam.wqSize = 8192; + fifoParam.transferUnit = conf.readUint(CONFIG_NVME, NVME_FIFO_UNIT); + fifoParam.latency = [](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(250000000, ARM::AXI::BUS_128BIT, + size); + }; + + pcieFIFO = new FIFO(pParent, fifoParam); + + if (axiWidth * axiClock == (uint64_t)250000000 * ARM::AXI::BUS_128BIT) { + // We don't need interconnect FIFO + interconnect = pcieFIFO; + pcieFIFO = nullptr; // Prevent double delete(free) + } + else { + fifoParam.latency = [axiWidth, axiClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(axiClock, axiWidth, size); + }; + + interconnect = new FIFO(pcieFIFO, fifoParam); + } + + cfgdata.pConfigReader = &c; + cfgdata.pInterface = interconnect; + cfgdata.maxQueueEntry = (registers.capabilities & 0xFFFF) + 1; + + workEvent = allocate([this](uint64_t) { work(); }); + requestEvent = allocate([this](uint64_t now) { handleRequest(now); }); + completionEvent = allocate([this](uint64_t) { completion(); }); + requestCounter = 0; + maxRequest = conf.readUint(CONFIG_NVME, NVME_MAX_REQUEST_COUNT); + workInterval = conf.readUint(CONFIG_NVME, NVME_WORK_INTERVAL); + requestInterval = workInterval / maxRequest; + + // Which subsystem should we use + uint16_t vid, ssvid; + + bUseOCSSD = false; + pParent->getVendorID(vid, ssvid); + + if (vid == OCSSD_VENDOR) { + bUseOCSSD = true; + + switch (ssvid) { + case OCSSD_SSVID_1_2: + pSubsystem = new OpenChannelSSD12(this, cfgdata); + + break; + case OCSSD_SSVID_2_0: + pSubsystem = new OpenChannelSSD20(this, cfgdata); + + break; + default: + panic("nvme_ctrl: Invalid SSVID for Open-Channel SSD"); + + break; + } + } + else { + pSubsystem = new Subsystem(this, cfgdata); + } + + // Initialize Subsystem + pSubsystem->init(); +} + +Controller::~Controller() { + delete pSubsystem; + + for (uint16_t i = 0; i < cqsize; i++) { + if (ppCQueue[i]) { + delete ppCQueue[i]; + } + } + + for (uint16_t i = 0; i < sqsize; i++) { + if (ppSQueue[i]) { + delete ppSQueue[i]; + } + } + + free(ppCQueue); + free(ppSQueue); + + delete interconnect; + delete pcieFIFO; +} + +void Controller::readRegister(uint64_t offset, uint64_t size, uint8_t *buffer, + uint64_t &) { + registers.interruptMaskSet = interruptMask; + registers.interruptMaskClear = interruptMask; + + memcpy(buffer, registers.data + offset, size); + + switch (offset) { + case REG_CONTROLLER_CAPABILITY: + case REG_CONTROLLER_CAPABILITY + 4: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Controller Capabilities"); + break; + case REG_VERSION: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Version"); + break; + case REG_INTERRUPT_MASK_SET: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Interrupt Mask Set"); + break; + case REG_INTERRUPT_MASK_CLEAR: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Interrupt Mask Clear"); + break; + case REG_CONTROLLER_CONFIG: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Controller Configuration"); + break; + case REG_CONTROLLER_STATUS: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Controller Status"); + break; + case REG_NVM_SUBSYSTEM_RESET: + debugprint(LOG_HIL_NVME, "BAR0 | READ | NVM Subsystem Reset"); + break; + case REG_ADMIN_QUEUE_ATTRIBUTE: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Admin Queue Attributes"); + break; + case REG_ADMIN_SQUEUE_BASE_ADDR: + case REG_ADMIN_SQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Admin Submission Queue Base Address"); + break; + case REG_ADMIN_CQUEUE_BASE_ADDR: + case REG_ADMIN_CQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Admin Completion Queue Base Address"); + break; + case REG_CMB_LOCATION: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Controller Memory Buffer Location"); + break; + case REG_CMB_SIZE: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Controller Memory Buffer Size"); + break; + } + + if (size == 4) { + debugprint(LOG_HIL_NVME, "DMAPORT | READ | DATA %08" PRIX32, + *(uint32_t *)buffer); + } + else { + debugprint(LOG_HIL_NVME, "DMAPORT | READ | DATA %016" PRIX64, + *(uint64_t *)buffer); + } +} + +void Controller::writeRegister(uint64_t offset, uint64_t size, uint8_t *buffer, + uint64_t &) { + static DMAFunction empty = [](uint64_t, void *) {}; + uint32_t uiTemp32; + uint64_t uiTemp64; + + if (size == 4) { + memcpy(&uiTemp32, buffer, 4); + + switch (offset) { + case REG_INTERRUPT_MASK_SET: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Interrupt Mask Set"); + + interruptMask |= uiTemp32; + + break; + case REG_INTERRUPT_MASK_CLEAR: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Interrupt Mask Clear"); + + interruptMask &= ~uiTemp32; + + break; + case REG_CONTROLLER_CONFIG: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Controller Configuration"); + + registers.configuration &= 0xFF00000E; + registers.configuration |= (uiTemp32 & 0x00FFFFF1); + + // Update entry size + sqstride = (int)powf(2.f, (registers.configuration & 0x000F0000) >> 16); + cqstride = (int)powf(2.f, (registers.configuration & 0x00F00000) >> 20); + + // Update Memory Page Size + cfgdata.memoryPageSizeOrder = + ((registers.configuration & 0x780) >> 7) + 11; // CC.MPS + 12 - 1 + cfgdata.memoryPageSize = + (int)powf(2.f, cfgdata.memoryPageSizeOrder + 1); + + // Update Arbitration Mechanism + arbitration = (registers.configuration & 0x00003800) >> 11; + + // Apply to admin queue + if (ppCQueue[0]) { + ppCQueue[0]->setBase( + new PRPList(cfgdata, empty, nullptr, + registers.adminCQueueBaseAddress, + ppCQueue[0]->getSize() * cqstride, true), + cqstride); + } + if (ppSQueue[0]) { + ppSQueue[0]->setBase( + new PRPList(cfgdata, empty, nullptr, + registers.adminSQueueBaseAddress, + ppSQueue[0]->getSize() * sqstride, true), + sqstride); + } + + // Shotdown notification + if (registers.configuration & 0x0000C000) { + registers.status &= 0xFFFFFFF2; // RDY = 1 + registers.status |= 0x00000005; // Shutdown processing occurring + + shutdownReserved = true; + } + // If EN = 1, Set CSTS.RDY = 1 + else if (registers.configuration & 0x00000001) { + registers.status |= 0x00000001; + + schedule(workEvent, getTick() + workInterval); + } + // If EN = 0, Set CSTS.RDY = 0 + else { + registers.status &= 0xFFFFFFFE; + + deschedule(workEvent); + } + + break; + case REG_CONTROLLER_STATUS: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Controller Status"); + + // Clear NSSRO if set + if (uiTemp32 & 0x00000010) { + registers.status &= 0xFFFFFFEF; + } + + break; + case REG_NVM_SUBSYSTEM_RESET: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | NVM Subsystem Reset"); + + registers.subsystemReset = uiTemp32; + + // FIXME: If NSSR is same as NVMe(0x4E564D65), do NVMe Subsystem reset + // (when CAP.NSSRS is 1) + break; + case REG_ADMIN_QUEUE_ATTRIBUTE: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Admin Queue Attributes"); + + registers.adminQueueAttributes &= 0xF000F000; + registers.adminQueueAttributes |= (uiTemp32 & 0x0FFF0FFF); + + break; + case REG_ADMIN_CQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Completion Queue Base Address | L"); + + memcpy(&(registers.adminCQueueBaseAddress), buffer, 4); + adminQueueInited++; + + break; + case REG_ADMIN_CQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Completion Queue Base Address | H"); + + memcpy(((uint8_t *)&(registers.adminCQueueBaseAddress)) + 4, buffer, 4); + adminQueueInited++; + + break; + case REG_ADMIN_SQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Submission Queue Base Address | L"); + memcpy(&(registers.adminSQueueBaseAddress), buffer, 4); + adminQueueInited++; + + break; + case REG_ADMIN_SQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Submission Queue Base Address | H"); + memcpy(((uint8_t *)&(registers.adminSQueueBaseAddress)) + 4, buffer, 4); + adminQueueInited++; + + break; + default: + panic("nvme_ctrl: Write on read only register"); + break; + } + + debugprint(LOG_HIL_NVME, "DMAPORT | WRITE | DATA %08" PRIX32, uiTemp32); + } + else if (size == 8) { + memcpy(&uiTemp64, buffer, 8); + + switch (offset) { + case REG_ADMIN_CQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Completion Queue Base Address"); + + registers.adminCQueueBaseAddress = uiTemp64; + adminQueueInited += 2; + + break; + case REG_ADMIN_SQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Submission Queue Base Address"); + + registers.adminSQueueBaseAddress = uiTemp64; + adminQueueInited += 2; + + break; + default: + panic("nvme_ctrl: Write on read only register"); + break; + } + + debugprint(LOG_HIL_NVME, "DMAPORT | WRITE | DATA %016" PRIX64, uiTemp64); + } + else { + panic("nvme_ctrl: Invalid read size(%d) on controller register", size); + } + + if (adminQueueInited == 4) { + uint16_t entrySize = 0; + + adminQueueInited = 0; + + entrySize = ((registers.adminQueueAttributes & 0x0FFF0000) >> 16) + 1; + ppCQueue[0] = new CQueue(0, true, 0, entrySize); + + debugprint(LOG_HIL_NVME, "CQ 0 | CREATE | Entry size %d", entrySize); + + entrySize = (registers.adminQueueAttributes & 0x0FFF) + 1; + ppSQueue[0] = new SQueue(0, 0, 0, entrySize); + + debugprint(LOG_HIL_NVME, "SQ 0 | CREATE | Entry size %d", entrySize); + } +} // namespace NVMe + +void Controller::ringCQHeadDoorbell(uint16_t qid, uint16_t head, uint64_t &) { + CQueue *pQueue = ppCQueue[qid]; + + if (pQueue) { + uint16_t oldhead = pQueue->getHead(); + uint32_t oldcount = pQueue->getItemCount(); + + pQueue->setHead(head); + + debugprint(LOG_HIL_NVME, + "CQ %-5d| Completion Queue Head Doorbell | Item count in queue " + "%d -> %d | head %d -> %d | tail %d", + qid, oldcount, pQueue->getItemCount(), oldhead, + pQueue->getHead(), pQueue->getTail()); + + if (pQueue->interruptEnabled()) { + clearInterrupt(pQueue->getInterruptVector()); + } + } +} + +void Controller::ringSQTailDoorbell(uint16_t qid, uint16_t tail, uint64_t &) { + SQueue *pQueue = ppSQueue[qid]; + + if (pQueue) { + uint16_t oldtail = pQueue->getTail(); + uint32_t oldcount = pQueue->getItemCount(); + + pQueue->setTail(tail); + + debugprint(LOG_HIL_NVME, + "SQ %-5d| Submission Queue Tail Doorbell | Item count in queue " + "%d -> %d | head %d | tail %d -> %d", + qid, oldcount, pQueue->getItemCount(), pQueue->getHead(), + oldtail, pQueue->getTail()); + } +} + +void Controller::clearInterrupt(uint16_t interruptVector) { + uint16_t notFinished = 0; + + // Check all queues associated with same interrupt vector are processed + for (uint16_t i = 0; i < cqsize; i++) { + if (ppCQueue[i]) { + if (ppCQueue[i]->getInterruptVector() == interruptVector) { + notFinished += ppCQueue[i]->getItemCount(); + } + } + } + + // Update interrupt + updateInterrupt(interruptVector, notFinished > 0); +} + +void Controller::updateInterrupt(uint16_t interruptVector, bool post) { + pParent->updateInterrupt(interruptVector, post); +} + +int Controller::createCQueue(uint16_t cqid, uint16_t size, uint16_t iv, + bool ien, bool pc, uint64_t prp1, + DMAFunction &func, void *context) { + int ret = 1; // Invalid Queue ID + CPUContext *pContext = + new CPUContext(func, context, CPU::NVME__CONTROLLER, CPU::CREATE_CQ); + + if (ppCQueue[cqid] == NULL) { + ppCQueue[cqid] = new CQueue(iv, ien, cqid, size); + ppCQueue[cqid]->setBase( + new PRPList(cfgdata, cpuHandler, pContext, prp1, size * cqstride, pc), + cqstride); + + ret = 0; + + debugprint(LOG_HIL_NVME, + "CQ %-5d| CREATE | Entry size %d | IV %04X | IEN %s | PC %s", + cqid, size, iv, BOOLEAN_STRING(ien), BOOLEAN_STRING(pc)); + + // Interrupt coalescing config + auto iter = aggregationMap.find(iv); + AggregationInfo info; + + info.valid = false; + info.nextTime = 0; + info.requestCount = 0; + + if (iter == aggregationMap.end()) { + aggregationMap.insert({iv, info}); + } + else { + iter->second = info; + } + } + + return ret; +} + +int Controller::createSQueue(uint16_t sqid, uint16_t cqid, uint16_t size, + uint8_t priority, bool pc, uint64_t prp1, + DMAFunction &func, void *context) { + int ret = 1; // Invalid Queue ID + CPUContext *pContext = + new CPUContext(func, context, CPU::NVME__CONTROLLER, CPU::CREATE_SQ); + + if (ppSQueue[sqid] == NULL) { + if (ppCQueue[cqid] != NULL) { + ppSQueue[sqid] = new SQueue(cqid, priority, sqid, size); + ppSQueue[sqid]->setBase( + new PRPList(cfgdata, cpuHandler, pContext, prp1, size * sqstride, pc), + sqstride); + + ret = 0; + + debugprint(LOG_HIL_NVME, + "SQ %-5d| CREATE | Entry size %d | Priority %d | PC %s", cqid, + size, priority, BOOLEAN_STRING(pc)); + } + else { + ret = 2; // Invalid CQueue + } + } + + return ret; +} + +int Controller::deleteCQueue(uint16_t cqid) { + int ret = 0; // Success + + if (ppCQueue[cqid] != NULL && cqid > 0) { + for (uint16_t i = 1; i < cqsize; i++) { + if (ppSQueue[i]) { + if (ppSQueue[i]->getCQID() == cqid) { + ret = 2; // Invalid Queue Deletion + break; + } + } + } + + if (ret == 0) { + uint16_t iv = ppCQueue[cqid]->getInterruptVector(); + bool sameIV = false; + + delete ppCQueue[cqid]; + ppCQueue[cqid] = NULL; + + debugprint(LOG_HIL_NVME, "CQ %-5d| DELETE", cqid); + + // Interrupt coalescing config + for (uint16_t i = 1; i < cqsize; i++) { + if (ppCQueue[i]) { + if (ppCQueue[i]->getInterruptVector() == iv) { + sameIV = true; + + break; + } + } + } + + if (!sameIV) { + aggregationMap.erase(aggregationMap.find(iv)); + } + } + } + else { + ret = 1; // Invalid Queue ID + } + + return ret; +} + +int Controller::deleteSQueue(uint16_t sqid) { + int ret = 0; // Success + + if (ppSQueue[sqid] != NULL && sqid > 0) { + // Create abort response + uint16_t sqHead = ppSQueue[sqid]->getHead(); + uint16_t status = 0x8000 | (TYPE_GENERIC_COMMAND_STATUS << 9) | + (STATUS_ABORT_DUE_TO_SQ_DELETE << 1); + + // Abort all commands in SQueue + for (auto iter = lSQFIFO.begin(); iter != lSQFIFO.end(); iter++) { + if (iter->sqID == sqid) { + CQEntryWrapper wrapper(*iter); + wrapper.entry.dword2.sqHead = sqHead; + wrapper.entry.dword3.status = status; + submit(wrapper); + + iter = lSQFIFO.erase(iter); + } + } + + // Delete SQueue + delete ppSQueue[sqid]; + ppSQueue[sqid] = NULL; + + debugprint(LOG_HIL_NVME, "SQ %-5d| DELETE", sqid); + } + else { + ret = 1; // Invalid Queue ID + } + + return ret; +} + +int Controller::abort(uint16_t sqid, uint16_t cid) { + int ret = 0; // Not aborted + uint16_t sqHead; + uint16_t status; + + for (auto iter = lSQFIFO.begin(); iter != lSQFIFO.end(); iter++) { + if (iter->sqID == sqid && iter->entry.dword0.commandID == cid) { + CQEntry entry; + + // Create abort response + sqHead = ppSQueue[sqid]->getHead(); + status = 0x8000 | (TYPE_GENERIC_COMMAND_STATUS << 9) | + (STATUS_ABORT_REQUESTED << 1); + + // Submit abort + CQEntryWrapper wrapper(*iter); + wrapper.entry.dword2.sqHead = sqHead; + wrapper.entry.dword3.status = status; + + submit(wrapper); + + // Remove + iter = lSQFIFO.erase(iter); + ret = 1; // Aborted + + break; + } + } + + return ret; +} + +void Controller::identify(uint8_t *data) { + uint16_t vid, ssvid; + uint64_t totalSize; + uint64_t unallocated; + + pParent->getVendorID(vid, ssvid); + pSubsystem->getNVMCapacity(totalSize, unallocated); + + unallocated = totalSize - unallocated; + + /** Controller Capabilities and Features **/ + { + // PCI Vendor ID + memcpy(data + 0x0000, &vid, 2); + + // PCI Subsystem Vendor ID + memcpy(data + 0x0002, &ssvid, 2); + + // Serial Number + memcpy(data + 0x0004, "00000000000000000000", 0x14); + + // Model Number + if (bUseOCSSD) { + memcpy(data + 0x0018, "SimpleSSD OCSSD Controller by CAMELab ", 0x28); + } + else { + memcpy(data + 0x0018, "SimpleSSD NVMe Controller by CAMELab ", 0x28); + } + + // Firmware Revision + memcpy(data + 0x0040, "02.01.03", 0x08); + + // Recommended Arbitration Burst + data[0x0048] = 0x00; + + // IEEE OUI Identifier + { + data[0x0049] = 0x00; + data[0x004A] = 0x00; + data[0x004B] = 0x00; + } + + // Controller Multi-Path I/O and Namespace Sharing Capabilities + // [Bits ] Description + // [07:04] Reserved + // [03:03] 1 for Asymmetric Namespace Access Reporting + // [02:02] 1 for SR-IOV Virtual Function, 0 for PCI (Physical) Function + // [01:01] 1 for more than one host may connected to NVM subsystem + // [00:00] 1 for NVM subsystem may has more than one NVM subsystem port + data[0x004C] = 0x00; + + // Maximum Data Transfer Size + data[0x004D] = 0x00; // No limit + + // Controller ID + { + data[0x004E] = 0x00; + data[0x004F] = 0x00; + } + + // Version + { + data[0x0050] = 0x01; + data[0x0051] = 0x04; + data[0x0052] = 0x00; + data[0x0053] = 0x00; + } // NVM Express 1.4 Compliant Controller + + // RTD3 Resume Latency + { + data[0x0054] = 0x00; + data[0x0055] = 0x00; + data[0x0056] = 0x00; + data[0x0057] = 0x00; + } // Not reported + + // RTD3 Enter Latency + { + data[0x0058] = 0x00; + data[0x0059] = 0x00; + data[0x005A] = 0x00; + data[0x005B] = 0x00; + } // Not repotred + + // Optional Asynchronous Events Supported + { + // [Bits ] Description + // [31:15] Reserved + // [14:14] 1 for Support Endurance Group Event Aggregate Log Page Change + // Notice + // [13:13] 1 for Support LBA Status Information Notice + // [12:12] 1 for Support Predictable Latency Event Aggregate Log Change + // Notice + // [11:11] 1 for Support Asymmetric Namespace Access Change Notice + // [10:10] Reserved + // [09:09] 1 for Support Firmware Activation Notice + // [08:08] 1 for Support Namespace Attributes Notice + // [07:00] Reserved + data[0x005C] = 0x00; + data[0x005D] = 0x00; + data[0x005E] = 0x00; + data[0x005F] = 0x00; + } + + // Controller Attributes + { + // [Bits ] Description + // [31:01] Reserved + // [09:09] 1 for Support UUID List + // [08:08] 1 for Support SQ Associations + // [07:07] 1 for Support Namespace Granularity + // [06:06] 1 for Traffic Based Keep Alive Support + // [05:05] 1 for Support Predictable Latency Mode + // [04:04] 1 for Support Endurance Group + // [03:03] 1 for Support Read Recovery Levels + // [02:02] 1 for Support NVM Sets + // [01:01] 1 for Support Non-Operational Power State Permissive Mode + // [00:00] 1 for Support 128-bit Host Identifier + data[0x0060] = 0x00; + data[0x0061] = 0x00; + data[0x0062] = 0x00; + data[0x0063] = 0x00; + } + + // Read Recovery Levels Supported + { + // [Bits ] Description + // [15:15] 1 for Read Recovery Level 15 - Fast Fail + // ... + // [04:04] 1 for Read Recovery Level 4 - Default + // ... + // [00:00] 1 for Read Recovery Level 0 + data[0x0064] = 0x00; + data[0x0065] = 0x00; + } + + memset(data + 0x0066, 0, 9); // Reserved + + // Controller Type + // [Value] Description + // [ 0h] Reserved (Controller Type not reported) + // [ 1h] I/O Controller + // [ 2h] Discovery Controller + // [ 3h] Administrative Controller + // [4h to FFh] Reserved + data[0x006F] = 0x01; + + // FRU Globally Unique Identifier + memset(data + 0x0070, 0, 16); + + // Command Retry Delay Time 1 + { + data[0x0080] = 0x00; + data[0x0081] = 0x00; + } + + // Command Retry Delay Time 2 + { + data[0x0082] = 0x00; + data[0x0083] = 0x00; + } + + // Command Retry Delay Time 3 + { + data[0x0084] = 0x00; + data[0x0085] = 0x00; + } + + memset(data + 0x0086, 0, 106); // Reserved + memset(data + 0x00F0, 0, 16); // See NVMe-MI Specification + } + + /** Admin Command Set Attributes & Optional Controller Capabilities **/ + { + // Optional Admin Command Support + { + // [Bits ] Description + // [15:10] Reserved + // [09:09] 1 for SupportGet LBA Status capability + // [08:08] 1 for Support Doorbell Buffer Config command + // [07:07] 1 for Support Virtualization Management command + // [06:06] 1 for Support NVMe-MI Send and NVMe-MI Receive commands + // [05:05] 1 for Support Directives + // [04:04] 1 for Support Device Self-Test command + // [03:03] 1 for Support Namespace Management and Namespace Attachment + // commands + // [02:02] 1 for Support Firmware Commit and Firmware Image Download + // commands + // [01:01] 1 for Support Format NVM command + // [00:00] 1 for Support Security Send and Security Receive commands + if (bUseOCSSD) { + data[0x0100] = 0x00; + } + else { + data[0x0100] = 0x0A; + } + data[0x0101] = 0x00; + } + + // Abort Command Limit + data[0x0102] = 0x03; // Recommanded value is 4 (3 + 1) + + // Asynchronous Event Request Limit + data[0x0103] = 0x03; // Recommanded value is 4 (3 + 1)) + + // Firmware Updates + // [Bits ] Description + // [07:05] Reserved + // [04:04] 1 for Support firmware activation without a reset + // [03:01] The number of firmware slot + // [00:00] 1 for First firmware slot is read only, 0 for read/write + data[0x0104] = 0x00; + + // Log Page Attributes + // [Bits ] Description + // [07:05] Reserved + // [04:04] 1 for Support Persisten Event log + // [03:03] 1 for Support Telemetry Host-Initiated and Telemetry Controller- + // Initiated log pages and Telemetry Log Notices + // [02:02] 1 for Support extended data for Get Log Page command + // [01:01] 1 for Support Command Effects log page + // [00:00] 1 for Support S.M.A.R.T. / Health information log page per + // namespace basis + data[0x0105] = 0x01; + + // Error Log Page Entries, 0's based value + data[0x0106] = 0x63; // 64 entries + + // Number of Power States Support, 0's based value + data[0x0107] = 0x00; // 1 states + + // Admin Vendor Specific Command Configuration + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for all vendor specific commands use the format at Figure 12. + // 0 for format is vendor specific + data[0x0108] = 0x00; + + // Autonomous Power State Transition Attributes + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for Support autonomous power state transitions + data[0x0109] = 0x00; + + // Warning Composite Temperature Threshold + { + data[0x010A] = 0x00; + data[0x010B] = 0x00; + } + + // Critical Composite Temperature Threshold + { + data[0x010C] = 0x00; + data[0x010D] = 0x00; + } + + // Maximum Time for Firmware Activation + { + data[0x010E] = 0x00; + data[0x010F] = 0x00; + } + + // Host Memory Buffer Preferred Size + { + data[0x0110] = 0x00; + data[0x0111] = 0x00; + data[0x0112] = 0x00; + data[0x0113] = 0x00; + } + + // Host Memory Buffer Minimum Size + { + data[0x0114] = 0x00; + data[0x0115] = 0x00; + data[0x0116] = 0x00; + data[0x0117] = 0x00; + } + + // Total NVM Capacity + { + memcpy(data + 0x118, &totalSize, 8); + memset(data + 0x120, 0, 8); + } + + // Unallocated NVM Capacity + { + memcpy(data + 0x118, &unallocated, 8); + memset(data + 0x120, 0, 8); + } + + // Replay Protected Memory Block Support + { + // [Bits ] Description + // [31:24] Access Size + // [23:16] Total Size + // [15:06] Reserved + // [05:03] Authentication Method + // [02:00] Number of RPMB Units + data[0x0138] = 0x00; + data[0x0139] = 0x00; + data[0x013A] = 0x00; + data[0x013B] = 0x00; + } + + // Extended Device Self-Test Time + { + data[0x013C] = 0x00; + data[0x013D] = 0x00; + } + + // Device Self-Test Options + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for Support only one device self-test operation in process at + // a time + data[0x013E] = 0x00; + + // Firmware Update Granularity + data[0x013F] = 0x00; + + // Keep Alive Support + { + data[0x0140] = 0x00; + data[0x0141] = 0x00; + } + + // Host Controlled Thermal Management Attributes + { + // [Bits ] Description + // [15:01] Reserved + // [00:00] 1 for Support host controlled thermal management + data[0x0142] = 0x00; + data[0x0143] = 0x00; + } + + // Minimum Thernam Management Temperature + { + data[0x0144] = 0x00; + data[0x0145] = 0x00; + } + + // Maximum Thernam Management Temperature + { + data[0x0146] = 0x00; + data[0x0147] = 0x00; + } + + // Sanitize Capabilities + { + // [Bits ] Description + // [31:30] No-Deallocate Modifies Media After Sanitize + // [29:29] No-Deallocate Inhibited + // [28:03] Reserved + // [02:02] 1 for Support Overwrite + // [01:01] 1 for Support Block Erase + // [00:00] 1 for Support Crypto Erase + data[0x0148] = 0x00; + data[0x0149] = 0x00; + data[0x014A] = 0x00; + data[0x014B] = 0x00; + } + + // Host Memory Buffer Minimum Descriptor Entry Size + { + data[0x014C] = 0x00; + data[0x014D] = 0x00; + data[0x014E] = 0x00; + data[0x014F] = 0x00; + } + + // Host Memory Maximum Descriptors Entries + { + data[0x0150] = 0x00; + data[0x0151] = 0x00; + } + + // NVM Set Identifier Maximum + { + data[0x0152] = 0x00; + data[0x0153] = 0x00; + } + + // Endurance Group Identifier Maximum + { + data[0x0154] = 0x00; + data[0x0155] = 0x00; + } + + // ANA Transition Time + data[0x0156] = 0x00; + + // Asymmetric Namespace Access Capabilities + // [Bits ] Description + // [07:07] 1 for Support non-zero ANAGRPID + // [06:06] 1 for ANAGRPID does not change while namespace is attached + // [05:05] Reserved + // [04:04] 1 for Support ANA Change state + // [03:03] 1 for Support ANA Persistent Loss state + // [02:02] 1 for Support ANA Inaccessible state + // [01:01] 1 for Support ANA Non-Optimized state + // [00:00] 1 for Support ANA Optimized state + data[0x157] = 0x00; + + // ANA Group Identifier Maximum + { + data[0x0158] = 0x00; + data[0x0159] = 0x00; + data[0x015A] = 0x00; + data[0x015B] = 0x00; + } + + // Number of ANA AGroup Identifiers + { + data[0x015C] = 0x00; + data[0x015D] = 0x00; + data[0x015E] = 0x00; + data[0x015F] = 0x00; + } + + // Persistent Event Log Size + { + data[0x0160] = 0x00; + data[0x0161] = 0x00; + data[0x0162] = 0x00; + data[0x0163] = 0x00; + } + + // Reserved + memset(data + 0x0164, 0, 156); + } + + /** NVM Command Set Attributes **/ + { + // Submission Queue Entry Size + // [Bits ] Description + // [07:04] Maximum Submission Queue Entry Size + // [03:00] Minimum Submission Queue Entry Size + data[0x0200] = 0x66; // 64Bytes, 64Bytes + + // Completion Queue Entry Size + // [Bits ] Description + // [07:04] Maximum Completion Queue Entry Size + // [03:00] Minimum Completion Queue Entry Size + data[0x0201] = 0x44; // 16Bytes, 16Bytes + + // Maximum Outstanding Commands + { + data[0x0202] = 0x00; + data[0x0203] = 0x00; + } + + // Number of Namespaces + // SimpleSSD supports infinite number of namespaces (0xFFFFFFFD) + // But kernel's DIV_ROUND_UP has problem when number is too big + // #define _KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + // This wrong macro introduces DIV_ROUND_UP(0xFFFFFFFD, 1024) to zero + // So we use 1024 here, for only one IDENTIFY NSLIST command + *(uint32_t *)(data + 0x0204) = 1024; + + // Optional NVM Command Support + { + // [Bits ] Description + // [15:08] Reserved + // [07:07] 1 for Support Verify command + // [06:06] 1 for Support Timestamp features + // [05:05] 1 for Support reservations + // [04:04] 1 for Support Save field in Set Features command and Select + // field in Get Features command + // [03:03] 1 for Support Write Zeros command + // [02:02] 1 for Support Dataset Management command + // [01:01] 1 for Support Write Uncorrectable command + // [00:00] 1 for Support Compare command + data[0x0208] = 0x05; + data[0x0209] = 0x00; + } + + // Fused Operation Support + { + // [Bits ] Description + // [15:01] Reserved + // [00:00] 1 for Support Compare and Write fused operation + data[0x020A] = 0x00; + data[0x020B] = 0x00; + } + + // Format NVM Attributes + // [Bits ] Description + // [07:03] Reserved + // [02:02] 1 for Support cryptographic erase + // [01:01] 1 for Support cryptographic erase performed on all namespaces, + // 0 for namespace basis + // [00:00] 1 for Format on specific namespace results on format on all + // namespaces, 0 for namespace basis + data[0x020C] = 0x00; + + // Volatile Write Cache + // [Bits ] Description + // [07:03] Reserved + // [02:01] Indicated Flush comand behavior if the NSID is 0xFFFFFFFF + // [00:00] 1 for volatile write cache is present + data[0x020D] = + conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE) ? 0x01 : 0x00; + data[0x020D] |= 0x06; + + // Atomic Write Unit Normal + { + data[0x020E] = 0x00; + data[0x020F] = 0x00; + } + + // Atomic Write Unit Power Fail + { + data[0x0210] = 0x00; + data[0x0211] = 0x00; + } + + // NVM Vendor Specific Command Configuration + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for all vendor specific commands use the format at Figure 12. + // 0 for format is vendor specific + data[0x0212] = 0x00; + + // Namespace Write Protection Capabilities + // [Bits ] Description + // [07:03] Reserved + // [02:02] 1 for Support Permenant Write Protect state + // [01:01] 1 for Support Write Protect Until Power Cycle state + // [00:00] 1 for Support No Write Protect and Write Protect state + data[0x0213] = 0x00; + + // Atomic Compare & Write Unit + { + data[0x0214] = 0x00; + data[0x0215] = 0x00; + } + + // Reserved + memset(data + 0x0216, 0, 2); + + // SGL Support + { + // [Bits ] Description + // [31:22] Reserved + // [21:21] 1 for Support Ransport SGL Data Block + // [20:20] 1 for Support Address field in SGL Data Block + // [19:19] 1 for Support MPTR containing SGL descriptor + // [18:18] 1 for Support MPTR/DPTR containing SGL with larger than amount + // of data to be trasferred + // [17:17] 1 for Support byte aligned contiguous physical buffer of + // metadata is supported + // [16:16] 1 for Support SGL Bit Bucket descriptor + // [15:03] Reserved + // [02:02] 1 for Support Keyed SGL Data Block descriptor + // [01:01] Reserved + // [00:00] 1 for Support SGLs in NVM Command Set + data[0x0218] = 0x01; + data[0x0219] = 0x00; + data[0x021A] = 0x17; + data[0x021B] = 0x00; + } + + // Maximun Number of Allowed Namespaces + *(uint32_t *)(data + 0x021C) = 0; + + // Reserved + memset(data + 0x0220, 0, 224); + + // NVM Subsystem NVMe Qualified Name + { + memset(data + 0x300, 0, 0x100); + strncpy((char *)data + 0x0300, + "nqn.2014-08.org.nvmexpress:uuid:270a1c70-962c-4116-6f1e340b9321", + 0x44); + } + + // Reserved + memset(data + 0x0400, 0, 768); + + // NVMe over Fabric + memset(data + 0x0700, 0, 256); + } + + /** Power State Descriptors **/ + // Power State 0 + /// Descriptor + { + // Maximum Power + { + data[0x0800] = 0xC4; + data[0x0801] = 0x09; + } + + // Reserved + data[0x0802] = 0x00; + + // [Bits ] Description + // [31:26] Reserved + // [25:25] Non-Operational State + // [24:24] Max Power Scale + data[0x0803] = 0x00; + + // Entry Latency + { + data[0x0804] = 0x00; + data[0x0805] = 0x00; + data[0x0806] = 0x00; + data[0x0807] = 0x00; + } + + // Exit Latency + { + data[0x0808] = 0x00; + data[0x0809] = 0x00; + data[0x080A] = 0x00; + data[0x080B] = 0x00; + } + + // [Bits ] Description + // [103:101] Reserved + // [100:096] Relative Read Throughput + data[0x080C] = 0x00; + + // [Bits ] Description + // [111:109] Reserved + // [108:104] Relative Read Latency + data[0x080D] = 0x00; + + // [Bits ] Description + // [119:117] Reserved + // [116:112] Relative Write Throughput + data[0x080E] = 0x00; + + // [Bits ] Description + // [127:125] Reserved + // [124:120] Relative Write Latency + data[0x080E] = 0x00; + + // Idle Power + { + data[0x080F] = 0x00; + data[0x0810] = 0x00; + } + + // [Bits ] Description + // [151:150] Idle Power Scale + // [149:144] Reserved + data[0x0811] = 0x00; + + // Reserved + data[0x0812] = 0x00; + + // Active Power + { + data[0x0813] = 0x00; + data[0x0814] = 0x00; + } + + // [Bits ] Description + // [183:182] Active Power Scale + // [181:179] Reserved + // [178:176] Active Power Workload + data[0x0815] = 0x00; + + // Reserved + memset(data + 0x0816, 0, 9); + } + + // PSD1 ~ PSD31 + memset(data + 0x0820, 0, 992); + + // Vendor specific area + memset(data + 0x0C00, 0, 1024); +} + +void Controller::setCoalescingParameter(uint8_t time, uint8_t thres) { + debugprint(LOG_HIL_NVME, + "INTR | Update coalescing parameters | TIME %u | THRES %u", + time, thres); + + aggregationTime = time * 100000000; + aggregationThreshold = thres; +} + +void Controller::getCoalescingParameter(uint8_t *time, uint8_t *thres) { + if (time) { + *time = aggregationTime / 100000000; + } + if (thres) { + *thres = aggregationThreshold; + } +} + +void Controller::setCoalescing(uint16_t iv, bool enable) { + auto iter = aggregationMap.find(iv); + + if (iter != aggregationMap.end()) { + debugprint(LOG_HIL_NVME, "INTR | %s interrupt coalescing | IV %u", + enable ? "Enable" : "Disable", iv); + + iter->second.valid = enable; + iter->second.nextTime = 0; + iter->second.requestCount = 0; + iter->second.pending = false; + } +} + +bool Controller::getCoalescing(uint16_t iv) { + auto iter = aggregationMap.find(iv); + + if (iter != aggregationMap.end()) { + return iter->second.valid; + } + + return false; +} + +void Controller::collectSQueue(DMAFunction &func, void *context) { + static uint16_t wrrHigh = conf.readUint(CONFIG_NVME, NVME_WRR_HIGH); + static uint16_t wrrMedium = conf.readUint(CONFIG_NVME, NVME_WRR_MEDIUM); + DMAContext *pContext = new DMAContext(func, context); + + static DMAFunction doQueue = [](uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + + delete pContext; + } + }; + + // Check ready + if (!(registers.status & 0x00000001)) { + return; + } + + // Round robin + if (arbitration == ROUND_ROBIN) { + SQueue *pQueue; + + uint16_t updated = 0; + + while (true) { + for (uint16_t i = 0; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + } + } + } + + if (updated == 0) { + break; + } + + updated = 0; + } + } + // Weighted round robin + else if (arbitration == WEIGHTED_ROUND_ROBIN) { + SQueue *pQueue; + + uint16_t updated = 0; + + // Collect all Admin Commands + pQueue = ppSQueue[0]; + + while (true) { + if (!checkQueue(pQueue, doQueue, pContext)) { + break; + } + else { + pContext->counter++; + } + } + + // Round robin all urgent command queues + while (true) { + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_URGENT) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + } + } + } + } + + if (updated == 0) { + break; + } + + updated = 0; + } + + // Weighted Round robin + uint32_t total_updated = 0; + + while (true) { + // Round robin all high-priority command queues + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_HIGH) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + total_updated++; + + if (updated == wrrHigh) { + updated = 0; + break; + } + } + } + } + } + + // Round robin all medium-priority command queues + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_MEDIUM) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + total_updated++; + + if (updated == wrrMedium) { + updated = 0; + break; + } + } + } + } + } + + // Round robin all low-priority command queues + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_MEDIUM) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + total_updated++; + + break; + } + } + } + } + + // Check finished + if (total_updated == 0) { + break; + } + + total_updated = 0; + } + } + else { + panic("nvme_ctrl: Invalid arbitration method"); + } + + if (pContext->counter == 0) { + // No item in submission queues + func(getTick(), context); + + delete pContext; + } +} + +void Controller::work() { + DMAFunction queueFunction = [this](uint64_t now, void *) { + DMAFunction doRequest = [this](uint64_t, void *) { + DMAFunction handle = [this](uint64_t now, void *) { handleRequest(now); }; + + execute(CPU::NVME__CONTROLLER, CPU::HANDLE_REQUEST, handle); + }; + + lastWorkAt = now; + + // Check NVMe shutdown + if (shutdownReserved) { + deschedule(workEvent); + + registers.status &= 0xFFFFFFF2; // RDY = 0 + registers.status |= 0x00000008; // Shutdown processing complete + + shutdownReserved = false; + + lSQFIFO.clear(); + } + + // Call request event + requestCounter = 0; + + execute(CPU::NVME__CONTROLLER, CPU::COLLECT_SQ, doRequest); + }; + + // Check ready + if (!(registers.status & 0x00000001)) { + return; + } + + // Collect requests in SQs + CPUContext *pContext = + new CPUContext(queueFunction, nullptr, CPU::NVME__CONTROLLER, CPU::WORK); + + collectSQueue(cpuHandler, pContext); +} + +void Controller::handleRequest(uint64_t now) { + // Check SQFIFO + if (lSQFIFO.size() > 0) { + SQEntryWrapper *front = new SQEntryWrapper(lSQFIFO.front()); + lSQFIFO.pop_front(); + + // Process command + DMAFunction doSubmit = [this](uint64_t, void *context) { + SQEntryWrapper *req = (SQEntryWrapper *)context; + + pSubsystem->submitCommand( + *req, [this](CQEntryWrapper &response) { submit(response); }); + + delete req; + }; + + if (bUseOCSSD) { + execute(CPU::NVME__OCSSD, CPU::SUBMIT_COMMAND, doSubmit, front); + } + else { + execute(CPU::NVME__SUBSYSTEM, CPU::SUBMIT_COMMAND, doSubmit, front); + } + } + + // Call request event + requestCounter++; + + if (lSQFIFO.size() > 0 && requestCounter < maxRequest) { + schedule(requestEvent, now + requestInterval); + } + else { + schedule(workEvent, MAX(now + requestInterval, lastWorkAt + workInterval)); + } +} + +bool Controller::checkQueue(SQueue *pQueue, DMAFunction &func, void *context) { + struct QueueContext { + SQEntry entry; + SQueue *pQueue; + DMAFunction function; + void *context; + uint16_t oldhead; + + QueueContext(DMAFunction &f) : pQueue(nullptr), function(f) {} + }; + + QueueContext *queueContext = new QueueContext(func); + queueContext->pQueue = pQueue; + queueContext->context = context; + + DMAFunction doRead = [this](uint64_t now, void *context) { + QueueContext *pContext = (QueueContext *)context; + + lSQFIFO.push_back(SQEntryWrapper( + pContext->entry, pContext->pQueue->getID(), pContext->pQueue->getCQID(), + pContext->pQueue->getHead(), pContext->oldhead)); + pContext->function(now, pContext->context); + + delete pContext; + }; + + if (pQueue->getItemCount() > 0) { + queueContext->oldhead = pQueue->getHead(); + pQueue->getData(&queueContext->entry, doRead, queueContext); + + return true; + } + else { + delete queueContext; + } + + return false; +} + +void Controller::submit(CQEntryWrapper &entry) { + CQueue *pQueue = ppCQueue[entry.cqID]; + + if (pQueue == NULL) { + panic("nvme_ctrl: Completion Queue not created! CQID %d", entry.cqID); + } + + // Set submit time + entry.submitAt = getTick(); + + // Enqueue with delay + auto iter = lCQFIFO.begin(); + + for (; iter != lCQFIFO.end(); iter++) { + if (iter->submitAt > entry.submitAt) { + break; + } + } + + lCQFIFO.insert(iter, entry); + + reserveCompletion(); +} + +void Controller::reserveCompletion() { + uint64_t tick = std::numeric_limits::max(); + bool valid = false; + + if (lCQFIFO.size() > 0) { + valid = true; + tick = lCQFIFO.front().submitAt; + } + + for (auto &iter : aggregationMap) { + if (iter.second.valid && iter.second.pending) { + if (!valid) { + valid = true; + tick = iter.second.nextTime; + } + else if (tick > iter.second.nextTime) { + tick = iter.second.nextTime; + } + } + } + + if (valid) { + schedule(completionEvent, tick); + } +} + +void Controller::completion() { + struct CompletionContext { + std::vector entryToPost; + std::vector ivToPost; + }; + + uint64_t tick = getTick(); + CQueue *pQueue = nullptr; + + DMAFunction doSubmit = [this](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + CompletionContext *pData = (CompletionContext *)pContext->context; + + pContext->counter--; + + if (pContext->counter == 0) { + DMAFunction send = [this](uint64_t, void *context) { + CompletionContext *pData = (CompletionContext *)context; + + if (pData->ivToPost.size() > 0) { + std::sort(pData->ivToPost.begin(), pData->ivToPost.end()); + auto end = + std::unique(pData->ivToPost.begin(), pData->ivToPost.end()); + + for (auto iter = pData->ivToPost.begin(); iter != end; iter++) { + // Update interrupt + updateInterrupt(*iter, true); + } + } + + reserveCompletion(); + + delete pData; + }; + + execute(CPU::NVME__CONTROLLER, CPU::COMPLETION, send, pData); + + delete pContext; + } + }; + + DMAContext *submitContext = new DMAContext(doSubmit); + CompletionContext *pData = new CompletionContext(); + + submitContext->context = pData; + + for (auto iter = lCQFIFO.begin(); iter != lCQFIFO.end();) { + if (iter->submitAt <= tick) { + // Copy CQ + pData->entryToPost.push_back(*iter); + + // Delete entry + iter = lCQFIFO.erase(iter); + } + else { + iter++; + } + } + + for (auto &iter : pData->entryToPost) { + pQueue = ppCQueue[iter.cqID]; + + submitContext->counter++; + pQueue->setData(&iter.entry, doSubmit, submitContext); + + // Collect interrupt vector + if (pQueue->interruptEnabled()) { + uint16_t iv = pQueue->getInterruptVector(); + bool post = true; + + if (iter.cqID > 0) { + // Interrupt Coalescing does not applied to admin queues + auto map = aggregationMap.find(iv); + + if (map != aggregationMap.end()) { + if (map->second.valid) { + map->second.requestCount++; + + if (iter.submitAt < map->second.nextTime && + map->second.requestCount <= aggregationThreshold) { + post = false; + map->second.pending = true; + } + + if (post) { + map->second.nextTime = tick + aggregationTime; + map->second.requestCount = 0; + } + } + } + } + + if (post) { + // Prepare for merge + pData->ivToPost.push_back(iv); + } + } + } + + for (auto &iter : aggregationMap) { + if (iter.second.valid && iter.second.nextTime <= tick && + iter.second.pending) { + iter.second.nextTime = tick + aggregationTime; + iter.second.requestCount = 0; + iter.second.pending = false; + + pData->ivToPost.push_back(iter.first); + } + } + + if (submitContext->counter == 0) { + delete pData; + delete submitContext; + } +} + +void Controller::getStatList(std::vector &list, std::string prefix) { + pSubsystem->getStatList(list, prefix); +} + +void Controller::getStatValues(std::vector &values) { + pSubsystem->getStatValues(values); +} + +void Controller::resetStatValues() { + pSubsystem->resetStatValues(); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/controller.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/controller.hh new file mode 100644 index 0000000000..d6f3267aef --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/controller.hh @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_CONTROLLER__ +#define __HIL_NVME_CONTROLLER__ + +#include +#include + +#include "hil/nvme/abstract_subsystem.hh" +#include "hil/nvme/def.hh" +#include "hil/nvme/dma.hh" +#include "hil/nvme/queue.hh" +#include "util/bitset.hh" +#include "util/def.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Interface; + +typedef union _RegisterTable { + uint8_t data[64]; + struct { + uint64_t capabilities; + uint32_t version; + uint32_t interruptMaskSet; + uint32_t interruptMaskClear; + uint32_t configuration; + uint32_t reserved; + uint32_t status; + uint32_t subsystemReset; + uint32_t adminQueueAttributes; + uint64_t adminSQueueBaseAddress; + uint64_t adminCQueueBaseAddress; + uint32_t memoryBufferLocation; + uint32_t memoryBufferSize; + }; + + _RegisterTable(); +} RegisterTable; + +typedef struct { + uint64_t nextTime; + uint32_t requestCount; + bool valid; + bool pending; +} AggregationInfo; + +class Controller : public StatObject { + private: + Interface *pParent; //!< NVMe::Interface passed from constructor + AbstractSubsystem *pSubsystem; //!< NVMe::Subsystem allocate in constructor + + bool bUseOCSSD; + + SimpleSSD::DMAInterface *pcieFIFO; + SimpleSSD::DMAInterface *interconnect; + + RegisterTable registers; //!< Table for NVMe Controller Registers + uint64_t sqstride; //!< Calculated SQ Stride + uint64_t cqstride; //!< Calculated CQ stride + uint8_t adminQueueInited; //!< Flag for initialization of Admin CQ/SQ + uint16_t arbitration; //!< Selected Arbitration Mechanism + uint32_t interruptMask; //!< Variable to store current interrupt mask + + uint32_t cqsize; + uint32_t sqsize; + CQueue **ppCQueue; //!< Completion Queue array + SQueue **ppSQueue; //!< Submission Queue array + + std::list lSQFIFO; //!< Internal FIFO queue for submission + std::list lCQFIFO; //!< Internal FIFO queue for completion + + bool shutdownReserved; + + uint64_t aggregationTime; + uint32_t aggregationThreshold; + std::unordered_map aggregationMap; + + ConfigData cfgdata; + ConfigReader &conf; + + Event workEvent; + Event requestEvent; + Event completionEvent; + uint32_t requestCounter; + uint32_t maxRequest; + uint64_t requestInterval; + uint64_t workInterval; + uint64_t lastWorkAt; + + bool checkQueue(SQueue *, DMAFunction &, void *); + + public: + Controller(Interface *, ConfigReader &); + ~Controller(); + + void readRegister(uint64_t, uint64_t, uint8_t *, uint64_t &); + void writeRegister(uint64_t, uint64_t, uint8_t *, uint64_t &); + void ringCQHeadDoorbell(uint16_t, uint16_t, uint64_t &); + void ringSQTailDoorbell(uint16_t, uint16_t, uint64_t &); + + void clearInterrupt(uint16_t); + void updateInterrupt(uint16_t, bool); + + int createCQueue(uint16_t, uint16_t, uint16_t, bool, bool, uint64_t, + DMAFunction &, void *); + int createSQueue(uint16_t, uint16_t, uint16_t, uint8_t, bool, uint64_t, + DMAFunction &, void *); + int deleteCQueue(uint16_t); + int deleteSQueue(uint16_t); + int abort(uint16_t, uint16_t); + void identify(uint8_t *); + void setCoalescingParameter(uint8_t, uint8_t); + void getCoalescingParameter(uint8_t *, uint8_t *); + void setCoalescing(uint16_t, bool); + bool getCoalescing(uint16_t); + + void collectSQueue(DMAFunction &, void *); + void handleRequest(uint64_t); + void work(); + + void submit(CQEntryWrapper &); + void reserveCompletion(); + void completion(); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/def.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/def.hh new file mode 100644 index 0000000000..8e67542568 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/def.hh @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_DEF__ +#define __HIL_NVME_DEF__ + +#include +#include + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +#define NSID_NONE 0x00000000 +#define NSID_LOWEST 0x00000001 +#define NSID_ALL 0xFFFFFFFF + +#define MAKE_SGL_ID(type, subtype) \ + (uint8_t)(((type << 4) & 0xF0) | (subtype & 0x0F)) +#define SGL_TYPE(id) (uint8_t)(id >> 4) +#define SGL_SUBTYPE(id) (uint8_t)(id & 0x0F) + +#define OCSSD_VENDOR 0x1D1D +#define OCSSD_SSVID_1_2 0x0102 +#define OCSSD_SSVID_2_0 0x0200 + +typedef union _HealthInfo { + uint8_t data[0x200]; + struct { + uint8_t status; + uint16_t temperature; + uint8_t availableSpare; + uint8_t spareThreshold; + uint8_t lifeUsed; + uint8_t reserved[26]; + uint64_t readL; + uint64_t readH; + uint64_t writeL; + uint64_t writeH; + uint64_t readCommandL; + uint64_t readCommandH; + uint64_t writeCommandL; + uint64_t writeCommandH; + }; + + _HealthInfo() { memset(data, 0, 0x200); } +} HealthInfo; + +typedef enum : uint8_t { + TYPE_DATA_BLOCK_DESCRIPTOR = 0x00, + TYPE_BIT_BUCKET_DESCRIPTOR = 0x01, + TYPE_SEGMENT_DESCRIPTOR = 0x02, + TYPE_LAST_SEGMENT_DESCRIPTOR = 0x03, + TYPE_KEYED_DATA_BLOCK_DESCRIPTOR = 0x04 +} SGL_DESCRIPTOR_TYPE; + +typedef enum : uint8_t { + SUBTYPE_ADDRESS = 0x00, + SUBTYPE_OFFSET = 0x01, + SUBTYPE_NVME_TRANSPORT_SPECIFIC = 0x02 +} SGL_DESCRIPTOR_SUBTYPE; + +typedef enum { + PRIORITY_URGENT, + PRIORITY_HIGH, + PRIORITY_MEDIUM, + PRIORITY_LOW +} SQUEUE_PRIORITY; + +typedef enum { + REG_CONTROLLER_CAPABILITY = 0x00, + REG_VERSION = 0x08, + REG_INTERRUPT_MASK_SET = 0x0C, + REG_INTERRUPT_MASK_CLEAR = 0x10, + REG_CONTROLLER_CONFIG = 0x14, + REG_CONTROLLER_STATUS = 0x1C, + REG_NVM_SUBSYSTEM_RESET = 0x20, + REG_ADMIN_QUEUE_ATTRIBUTE = 0x24, + REG_ADMIN_SQUEUE_BASE_ADDR = 0x28, + REG_ADMIN_CQUEUE_BASE_ADDR = 0x30, + REG_CMB_LOCATION = 0x38, + REG_CMB_SIZE = 0x3C, + REG_DOORBELL_BEGIN = 0x1000 +} COMMAND_REGISTER; + +typedef enum { ROUND_ROBIN, WEIGHTED_ROUND_ROBIN } ARBITRATION_METHOD; + +typedef enum { + OPCODE_PROPERTY_SET = 0x00, + OPCODE_CONNECT = 0x01, + OPCODE_PROPERTY_GET = 0x04, + OPCODE_AUTHENTICATION_SEND = 0x05, + OPCODE_AUTHENTICATION_RECEIVE = 0x06 +} FABRIC_OPCODE; + +typedef enum { + OPCODE_DELETE_IO_SQUEUE = 0x00, + OPCODE_CREATE_IO_SQUEUE = 0x01, + OPCODE_GET_LOG_PAGE = 0x02, + OPCODE_DELETE_IO_CQUEUE = 0x04, + OPCODE_CREATE_IO_CQUEUE = 0x05, + OPCODE_IDENTIFY = 0x06, + OPCODE_ABORT = 0x08, + OPCODE_SET_FEATURES = 0x09, + OPCODE_GET_FEATURES = 0x0A, + OPCODE_ASYNC_EVENT_REQ = 0x0C, + OPCODE_NAMESPACE_MANAGEMENT = 0x0D, + OPCODE_FIRMWARE_COMMIT = 0x10, + OPCODE_FIRMWARE_DOWNLOAD = 0x11, + OPCODE_DEVICE_SELF_TEST = 0x14, + OPCODE_NAMESPACE_ATTACHMENT = 0x15, + OPCODE_KEEPALIVE = 0x18, + OPCODE_DIRECTIVE_SEND = 0x19, + OPCODE_DIRECTIVE_RECEIVE = 0x1A, + OPCODE_VIRTUALIZATION_MANAGEMENT = 0x1C, + OPCODE_NVME_MI_SEND = 0x1D, + OPCODE_NVME_MI_RECEIVE = 0x1E, + OPCODE_DOORBELL_BUFFER_CONFIG = 0x7C, + OPCODE_FORMAT_NVM = 0x80, + OPCODE_SECURITY_SEND = 0x81, + OPCODE_SECURITY_RECEIVE = 0x82, + OPCODE_SANITIZE = 0x84, + + // OpenChannel SSD 1.2 + OPCODE_DEVICE_IDENTIFICATION = 0xE2, + OPCODE_SET_BAD_BLOCK_TABLE = 0xF1, + OPCODE_GET_BAD_BLOCK_TABLE = 0xF2, + + // OpenChannel SSD 2.0 + OPCODE_GEOMETRY = 0xE2 +} ADMIN_OPCODE; + +typedef enum { + OPCODE_FLUSH = 0x00, + OPCODE_WRITE = 0x01, + OPCODE_READ = 0x02, + OPCODE_WRITE_UNCORRECTABLE = 0x04, + OPCODE_COMPARE = 0x05, + OPCODE_WRITE_ZEROS = 0x08, + OPCODE_DATASET_MANAGEMEMT = 0x09, + OPCODE_RESERVATION_REGISTER = 0x0D, + OPCODE_RESERVATION_REPORT = 0x0E, + OPCODE_RESERVATION_ACQUIRE = 0x11, + OPCODE_RESERVATION_RELEASE = 0x15, + + // OpenChannel SSD 1.2 + OPCODE_PHYSICAL_BLOCK_ERASE = 0x90, + OPCODE_PHYSICAL_PAGE_WRITE, + OPCODE_PHYSICAL_PAGE_READ, + OPCODE_PHYSICAL_PAGE_RAW_WRITE = 0x95, + OPCODE_PHYSICAL_PAGE_RAW_READ, + + // OpenChannel SSD 2.0 + OPCODE_VECTOR_CHUNK_RESET = 0x90, + OPCODE_VECTOR_CHUNK_WRITE, + OPCODE_VECTOR_CHUNK_READ, + OPCODE_VECTOR_CHUNK_COPY +} NVM_OPCODE; + +typedef enum { + LOG_ERROR_INFORMATION = 0x01, + LOG_SMART_HEALTH_INFORMATION, + LOG_FIRMWARE_SLOT_INFORMATION, + LOG_CHANGED_NAMESPACE_LIST, + LOG_COMMAND_EFFECTS_LOG, + LOG_RESERVATION_NOTIFICATION = 0x80, + + // OpenChannel SSD + LOG_CHUNK_INFORMATION = 0xCA +} LOG_PAGE; + +typedef enum { + CNS_IDENTIFY_NAMESPACE = 0x00, + CNS_IDENTIFY_CONTROLLER = 0x01, + CNS_ACTIVE_NAMESPACE_LIST = 0x02, + CNS_ALLOCATED_NAMESPACE_LIST = 0x10, + CNS_IDENTIFY_ALLOCATED_NAMESPACE = 0x11, + CNS_ATTACHED_CONTROLLER_LIST = 0x12, + CNS_CONTROLLER_LIST = 0x13 +} IDENTIFY_CNS; + +typedef enum { + FEATURE_ARBITRATION = 0x01, + FEATURE_POWER_MANAGEMENT, + FEATURE_LBA_RANGE_TYPE, + FEATURE_TEMPERATURE_THRESHOLD, + FEATURE_ERROR_RECOVERY, + FEATURE_VOLATILE_WRITE_CACHE, + FEATURE_NUMBER_OF_QUEUES, + FEATURE_INTERRUPT_COALESCING, + FEATURE_INTERRUPT_VECTOR_CONFIGURATION, + FEATURE_WRITE_ATOMICITY_NORMAL, + FEATURE_ASYNC_EVENT_CONFIGURATION, + FEATURE_AUTO_POWER_STATE_TRANSITION, + FEATURE_HOST_MEMORY_BUFFER, + FEATURE_TIMESTAMP, + FEATURE_KEEPALIVE_TIMER, + FEATURE_HOST_CONTROLLED_THERMAL_MANAGEMENT, + FEATURE_NON_OPERATIONAL_POWER_STATE_CONFIG, + FEATURE_SOFTWARE_PROGRESS_MARKER = 0x80, + FEATURE_HOST_IDENTIFIER, + FEATURE_RESERVATION_NOTIFICATION_MASK, + FEATURE_RESERVATION_PERSISTANCE, + + // OpenChannel SSD + FEATURE_MEDIA_FEEDBACH = 0xCA +} FEATURE; + +typedef enum { + TYPE_GENERIC_COMMAND_STATUS, // -> NVME_STATUS_CODE + TYPE_COMMAND_SPECIFIC_STATUS, // -> NVME_ERROR_CODE + TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, +} STATUS_CODE_TYPE; + +typedef enum { + /** Generic Command Status **/ + STATUS_SUCCESS, + STATUS_INVALID_OPCODE, + STATUS_INVALID_FIELD, + STATUS_CID_CONFLICT, + STATUS_DATA_TRANSFER_ERROR, + STATUS_ABORT_DUE_TO_POWER_LOSS, + STATUS_INTERNAL_ERROR, + STATUS_ABORT_REQUESTED, + STATUS_ABORT_DUE_TO_SQ_DELETE, + STATUS_ABORT_DUE_TO_FAILED_FUSE, + STATUS_ABORT_DUE_TO_MISSING_FUSE, + STATUS_ABORT_INVALID_NAMESPACE, + STATUS_ABORT_INVALID_FORMAT = STATUS_ABORT_INVALID_NAMESPACE, + STATUS_COMMAND_SEQUENCE_ERROR, + STATUS_INVALID_SGL_SEGMENT_DESCRIPTOR, + STATUS_INVALID_NUMBER_OF_SGL_DESCRIPTOR, + STATUS_INVALID_DATA_SGL_LENGTH, + STATUS_INVALID_METADATA_SGL_LENGTH, + STATUS_INVALID_SGL_DESCRIPTOR_TYPE, + STATUS_INVALID_USE_OF_MEMORY_BUFFER, + STATUS_PRP_OFFSET_INVALID, + STATUS_ATOMIC_WRITE_UNIT_EXCEEDED, + STATUS_INVALID_SGL_OFFSET = 0x16, + STATUS_INVALID_SGL_SUB_TYPE, + STATUS_HOST_ID_INCONSISTENT_FORMAT, + STATUS_KEEPALIVE_TIMEOUT_EXPIRED, + STATUS_INVALID_KEEPALIVE_TIMEOUT, + + /** NVM Command Status **/ + STATUS_LBA_OUT_OF_RANGE = 0x80, + STATUS_CAPACITY_EXCEEDED, + STATUS_NAMESPACE_NOT_READY, + STATUE_RESERVATION_CONFLICT, + STATUS_FORMAT_IN_PROGRESS +} STATUS_CODE; + +typedef enum { + /** Generic Command Errors **/ + STATUS_INVALID_COMPLETION_QUEUE, + STATUS_INVALID_QUEUE_ID, + STATUS_INVALID_QUEUE_SIZE, + STATUS_ABORT_COMMAND_LIMIT_EXCEEDED, + STATUS_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, + STATUS_INVALID_FIRMWARE_SLOT, + STATUS_INVALID_FIRMWARE_IMAGE, + STATUS_INVALID_INTERRUPT_VECTOR, + STATUS_INVALID_LOG_PAGE, + STATUS_INVALID_FORMAT, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_CONVENTIONAL_RESET, + STATUS_INVALID_QUEUE_DELETE, + STATUS_FEATURE_ID_NOT_SAVEABLE, + STATUS_FEATURE_NOT_CHANGABLE, + STATUS_FEATURE_NOT_NAMESPACE_SPECIFIC, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_NVM_SUBSYSTEM_RESET, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_RESET, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_MAXIMUM_TIME_VIOLATION, + STATUS_FIRMWARE_ACTIVATION_PROHIBITED, + STATUS_OVERLAPPING_RANGE, + STATUS_NAMESPACE_INSUFFICIENT_CAPACITY, + STATUS_NAMESPACE_ID_UNAVAILABLE, + STATUS_NAMESPACE_ALREADY_ATTACHED = 0x18, + STATUS_NAMESPACE_IS_PRIVATE, + STATUS_NAMESPACE_NOT_ATTACHED, + STATUS_THIN_PROVISIONING_NOT_SUPPORTED, + STATUS_CONTROLLER_LIST_INVALID, + + /** NVM Command Errors **/ + STATUS_ATTRIBUTE_CONFLICT = 0x80, + STATUS_INVALID_PROTECTION_INFORMATION, + STATUS_WRITE_TO_READ_ONLY_RANGE, +} ERROR_CODE; + +typedef enum { + /** I/O Command Media Errors **/ + STATUS_WRITE_FAULT = 0x80, + STATUS_UNRECOVERED_READ_ERROR, + STATUS_END_TO_END_GUARD_CHECK_ERROR, + STATUS_END_TO_END_APPLICATION_TAG_CHECK_ERROR, + STATUS_END_TO_END_REFERENCE_TAG_CHECK_ERROR, + STATUS_COMPARE_FAILURE, + STATUS_ACCESS_DENIED, + STATUS_DEALLOCATED_OR_UNWRITTEN_LOGICAL_BLOCK +} MEDIA_ERROR_CODE; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/dma.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/dma.cc new file mode 100644 index 0000000000..fba747aaf2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/dma.cc @@ -0,0 +1,543 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/dma.hh" + +#include "hil/nvme/controller.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +DMAInterface::DMAInterface(ConfigData &cfg, DMAFunction &f, void *c) + : pInterface(cfg.pInterface), + initFunction(f), + callCounter(0), + context(c), + dmaHandler(commonDMAHandler) { + immediateEvent = + allocate([this](uint64_t now) { initFunction(now, context); }); +} + +DMAInterface::~DMAInterface() {} + +void DMAInterface::commonDMAHandler(uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + delete pContext; + } +} + +PRP::PRP() : addr(0), size(0) {} + +PRP::PRP(uint64_t address, uint64_t s) : addr(address), size(s) {} + +PRPList::PRPList(ConfigData &cfg, DMAFunction &f, void *c, uint64_t prp1, + uint64_t prp2, uint64_t size) + : DMAInterface(cfg, f, c), totalSize(size), pagesize(cfg.memoryPageSize) { + bool immediate = true; + uint64_t prp1Size = getPRPSize(prp1); + uint64_t prp2Size = getPRPSize(prp2); + + // Determine PRP1 and PRP2 + if (totalSize <= pagesize) { + if (totalSize <= prp1Size) { + // PRP1 is PRP pointer, PRP2 is not used + prpList.push_back(PRP(prp1, totalSize)); + } + else { + // PRP1 is PRP pointer, PRP2 is PRP pointer + prpList.push_back(PRP(prp1, prp1Size)); + prpList.push_back(PRP(prp2, prp2Size)); + + if (prp1Size + prp2Size < totalSize) { + panic("prp_list: Invalid DPTR size"); + } + } + } + else if (totalSize <= pagesize * 2) { + if (prp1Size == pagesize) { + // PRP1 is PRP pointer, PRP2 is PRP pointer + prpList.push_back(PRP(prp1, prp1Size)); + prpList.push_back(PRP(prp2, prp2Size)); + + if (prp1Size + prp2Size < totalSize) { + panic("prp_list: Invalid DPTR size"); + } + } + else { + immediate = false; + + // PRP1 is PRP pointer, PRP2 is PRP list + prpList.push_back(PRP(prp1, prp1Size)); + getPRPListFromPRP(prp2, totalSize - prp1Size); + } + } + else { + immediate = false; + + // PRP1 is PRP pointer, PRP2 is PRP list + prpList.push_back(PRP(prp1, prp1Size)); + getPRPListFromPRP(prp2, totalSize - prp1Size); + } + + if (immediate) { + schedule(immediateEvent, getTick()); + } +} + +PRPList::PRPList(ConfigData &cfg, DMAFunction &f, void *c, uint64_t base, + uint64_t size, bool cont) + : DMAInterface(cfg, f, c), totalSize(size), pagesize(cfg.memoryPageSize) { + if (cont) { + prpList.push_back(PRP(base, size)); + + schedule(immediateEvent, getTick()); + } + else { + getPRPListFromPRP(base, size); + } +} + +PRPList::~PRPList() {} + +void PRPList::getPRPListFromPRP(uint64_t base, uint64_t size) { + static DMAFunction doRead = [](uint64_t now, void *context) { + DMAInitContext *pContext = (DMAInitContext *)context; + PRPList *pThis = (PRPList *)pContext->pThis; + uint64_t listPRP; + uint64_t listPRPSize; + uint64_t currentSize = 0; + + pThis->callCounter--; + + for (size_t i = 0; i < pContext->currentSize; i += 8) { + listPRP = *((uint64_t *)(pContext->buffer + i)); + listPRPSize = pThis->getPRPSize(listPRP); + currentSize += listPRPSize; + + if (listPRP == 0) { + panic("prp_list: Invalid PRP in PRP List"); + } + + pThis->prpList.push_back(PRP(listPRP, listPRPSize)); + + if (currentSize >= pContext->totalSize) { + break; + } + } + + free(pContext->buffer); + + if (currentSize < pContext->totalSize) { + // PRP list ends but size is not full + // Last item of PRP list is pointer of another PRP + // list + listPRP = pThis->prpList.back().addr; + pThis->prpList.pop_back(); + + pThis->getPRPListFromPRP(listPRP, pContext->totalSize - currentSize); + } + + if (pThis->callCounter == 0) { + // Everything is done + pThis->initFunction(now, pThis->context); + } + + delete pContext; + }; + + DMAInitContext *pContext = new DMAInitContext(); + + callCounter++; + + pContext->pThis = this; + pContext->totalSize = size; + + // Get PRP size + pContext->currentSize = getPRPSize(base); + + // Allocate buffer + pContext->buffer = (uint8_t *)malloc(pContext->currentSize); + + if (pContext->buffer) { + // Read PRP + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::NVME__PRPLIST, + CPU::GET_PRPLIST_FROM_PRP); + pInterface->dmaRead(base, pContext->currentSize, pContext->buffer, + cpuHandler, pCPU); + } + else { + delete pContext; + + panic("prp_list: ENOMEM"); + } +} + +uint64_t PRPList::getPRPSize(uint64_t addr) { + return pagesize - (addr & (pagesize - 1)); +} + +void PRPList::read(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doRead = [this, offset, length, buffer](uint64_t, void *context) { + uint64_t totalRead = 0; + uint64_t currentOffset = 0; + uint64_t read; + bool begin = false; + + DMAContext *readContext = (DMAContext *)context; + + for (auto &iter : prpList) { + if (begin) { + read = MIN(iter.size, length - totalRead); + readContext->counter++; + pInterface->dmaRead(iter.addr, read, buffer ? buffer + totalRead : NULL, + dmaHandler, readContext); + totalRead += read; + + if (totalRead == length) { + break; + } + } + + if (!begin && currentOffset + iter.size > offset) { + begin = true; + totalRead = offset - currentOffset; + read = MIN(iter.size - totalRead, length); + readContext->counter++; + pInterface->dmaRead(iter.addr + totalRead, read, buffer, dmaHandler, + readContext); + totalRead = read; + } + + currentOffset += iter.size; + } + + if (readContext->counter == 0) { + readContext->counter = 1; + + dmaHandler(getTick(), readContext); + } + }; + + DMAContext *readContext = new DMAContext(func, context); + + execute(CPU::NVME__PRPLIST, CPU::READ, doRead, readContext); +} + +void PRPList::write(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doWrite = [this, offset, length, buffer](uint64_t, + void *context) { + uint64_t totalWritten = 0; + uint64_t currentOffset = 0; + uint64_t written; + bool begin = false; + + DMAContext *writeContext = (DMAContext *)context; + + for (auto &iter : prpList) { + if (begin) { + written = MIN(iter.size, length - totalWritten); + writeContext->counter++; + pInterface->dmaWrite(iter.addr, written, + buffer ? buffer + totalWritten : NULL, dmaHandler, + writeContext); + totalWritten += written; + + if (totalWritten == length) { + break; + } + } + + if (!begin && currentOffset + iter.size > offset) { + begin = true; + totalWritten = offset - currentOffset; + written = MIN(iter.size - totalWritten, length); + writeContext->counter++; + pInterface->dmaWrite(iter.addr + totalWritten, written, buffer, + dmaHandler, writeContext); + totalWritten = written; + } + + currentOffset += iter.size; + } + + if (writeContext->counter == 0) { + writeContext->counter = 1; + + dmaHandler(getTick(), writeContext); + } + }; + + DMAContext *writeContext = new DMAContext(func, context); + + execute(CPU::NVME__PRPLIST, CPU::WRITE, doWrite, writeContext); +} + +SGLDescriptor::SGLDescriptor() { + memset(data, 0, 16); +} + +Chunk::Chunk() : addr(0), length(0), ignore(true) {} + +Chunk::Chunk(uint64_t a, uint32_t l, bool i) : addr(a), length(l), ignore(i) {} + +SGL::SGL(ConfigData &cfg, DMAFunction &f, void *c, uint64_t prp1, uint64_t prp2) + : DMAInterface(cfg, f, c), totalSize(0) { + SGLDescriptor desc; + + // Create first SGL descriptor from PRP pointers + memcpy(desc.data, &prp1, 8); + memcpy(desc.data + 8, &prp2, 8); + + // Check type + if (SGL_TYPE(desc.id) == TYPE_DATA_BLOCK_DESCRIPTOR || + SGL_TYPE(desc.id) == TYPE_KEYED_DATA_BLOCK_DESCRIPTOR) { + // This is entire buffer + parseSGLDescriptor(desc); + + schedule(immediateEvent, getTick()); + } + else if (SGL_TYPE(desc.id) == TYPE_SEGMENT_DESCRIPTOR || + SGL_TYPE(desc.id) == TYPE_LAST_SEGMENT_DESCRIPTOR) { + // This points segment + parseSGLSegment(desc.address, desc.length); + } +} + +SGL::~SGL() {} + +void SGL::parseSGLDescriptor(SGLDescriptor &desc) { + switch (SGL_TYPE(desc.id)) { + case TYPE_DATA_BLOCK_DESCRIPTOR: + case TYPE_KEYED_DATA_BLOCK_DESCRIPTOR: + chunkList.push_back(Chunk(desc.address, desc.length, false)); + totalSize += desc.length; + + break; + case TYPE_BIT_BUCKET_DESCRIPTOR: + chunkList.push_back(Chunk(desc.address, desc.length, true)); + totalSize += desc.length; + + break; + default: + panic("Invalid SGL descriptor"); + break; + } + + if (SGL_SUBTYPE(desc.id) != SUBTYPE_ADDRESS) { + panic("Unexpected SGL subtype"); + } +} + +void SGL::parseSGLSegment(uint64_t address, uint32_t length) { + static DMAFunction doRead = [](uint64_t now, void *context) { + SGLDescriptor desc; + DMAInitContext *pContext = (DMAInitContext *)context; + SGL *pThis = (SGL *)pContext->pThis; + bool next = false; + + pThis->callCounter--; + + for (uint32_t i = 0; i < pContext->currentSize; i += 16) { + memcpy(desc.data, pContext->buffer + i, 16); + + switch (SGL_TYPE(desc.id)) { + case TYPE_DATA_BLOCK_DESCRIPTOR: + case TYPE_KEYED_DATA_BLOCK_DESCRIPTOR: + case TYPE_BIT_BUCKET_DESCRIPTOR: + pThis->parseSGLDescriptor(desc); + + break; + case TYPE_SEGMENT_DESCRIPTOR: + case TYPE_LAST_SEGMENT_DESCRIPTOR: + if (i != pContext->currentSize - 16) { + panic("Invalid SGL segment"); + } + next = true; + + break; + } + } + + free(pContext->buffer); + + // Go to next + if (next) { + pThis->parseSGLSegment(desc.address, desc.length); + } + + if (pThis->callCounter == 0) { + pThis->initFunction(now, pThis->context); + } + + delete pContext; + }; + + DMAInitContext *pContext = new DMAInitContext(); + + callCounter++; + + // Allocate buffer + pContext->pThis = this; + pContext->currentSize = length; + pContext->buffer = (uint8_t *)calloc(length, 1); + + if (pContext->buffer) { + // Read segment + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::NVME__SGL, + CPU::PARSE_SGL_SEGMENT); + pInterface->dmaRead(address, length, pContext->buffer, cpuHandler, pCPU); + } + else { + delete pContext; + + panic("sgl: ENOMEM"); + } +} + +void SGL::read(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doRead = [this, offset, length, buffer](uint64_t, void *context) { + uint64_t totalRead = 0; + uint64_t currentOffset = 0; + uint64_t read; + bool begin = false; + + DMAContext *readContext = (DMAContext *)context; + + for (auto &iter : chunkList) { + if (begin) { + read = MIN(iter.length, length - totalRead); + + if (!iter.ignore) { + readContext->counter++; + pInterface->dmaRead(iter.addr, read, + buffer ? buffer + totalRead : NULL, dmaHandler, + readContext); + } + + totalRead += read; + + if (totalRead == length) { + break; + } + } + + if (!begin && currentOffset + iter.length > offset) { + begin = true; + totalRead = offset - currentOffset; + read = MIN(iter.length - totalRead, length); + + if (!iter.ignore) { + readContext->counter++; + pInterface->dmaRead(iter.addr + totalRead, read, buffer, dmaHandler, + readContext); + } + + totalRead = read; + } + + currentOffset += iter.length; + } + + if (readContext->counter == 0) { + readContext->counter = 1; + + dmaHandler(getTick(), readContext); + } + }; + + DMAContext *readContext = new DMAContext(func, context); + + execute(CPU::NVME__SGL, CPU::READ, doRead, readContext); +} + +void SGL::write(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doWrite = [this, offset, length, buffer](uint64_t, + void *context) { + uint64_t totalWritten = 0; + uint64_t currentOffset = 0; + uint64_t written; + bool begin = false; + + DMAContext *writeContext = (DMAContext *)context; + + for (auto &iter : chunkList) { + if (begin) { + written = MIN(iter.length, length - totalWritten); + + if (!iter.ignore) { + writeContext->counter++; + pInterface->dmaWrite(iter.addr, written, + buffer ? buffer + totalWritten : NULL, + dmaHandler, writeContext); + } + + totalWritten += written; + + if (totalWritten == length) { + break; + } + } + + if (!begin && currentOffset + iter.length > offset) { + begin = true; + totalWritten = offset - currentOffset; + written = MIN(iter.length - totalWritten, length); + + if (!iter.ignore) { + writeContext->counter++; + pInterface->dmaWrite(iter.addr + totalWritten, written, buffer, + dmaHandler, writeContext); + } + + totalWritten = written; + } + + currentOffset += iter.length; + } + + if (writeContext->counter == 0) { + writeContext->counter = 1; + + dmaHandler(getTick(), writeContext); + } + }; + + DMAContext *writeContext = new DMAContext(func, context); + + execute(CPU::NVME__SGL, CPU::WRITE, doWrite, writeContext); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/dma.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/dma.hh new file mode 100644 index 0000000000..90b8a41e2f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/dma.hh @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_DMA__ +#define __HIL_NVME_DMA__ + +#include + +#include "hil/nvme/config.hh" +#include "hil/nvme/def.hh" +#include "sim/dma_interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Controller; + +typedef struct { + ConfigReader *pConfigReader; + DMAInterface *pInterface; + uint64_t memoryPageSize; + uint8_t memoryPageSizeOrder; + uint16_t maxQueueEntry; +} ConfigData; + +class DMAInterface { + protected: + SimpleSSD::DMAInterface *pInterface; + DMAFunction initFunction; + uint64_t callCounter; + void *context; + + Event immediateEvent; + + DMAFunction dmaHandler; + static void commonDMAHandler(uint64_t, void *); + + public: + DMAInterface(ConfigData &, DMAFunction &, void *); + virtual ~DMAInterface(); + + virtual void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; + virtual void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; +}; + +struct DMAInitContext { + DMAInterface *pThis; + uint64_t totalSize; + uint64_t currentSize; + uint8_t *buffer; +}; + +struct PRP { + uint64_t addr; + uint64_t size; + + PRP(); + PRP(uint64_t, uint64_t); +}; + +class PRPList : public DMAInterface { + private: + std::vector prpList; + uint64_t totalSize; + uint64_t pagesize; + + void getPRPListFromPRP(uint64_t, uint64_t); + uint64_t getPRPSize(uint64_t); + + public: + PRPList(ConfigData &, DMAFunction &, void *, uint64_t, uint64_t, uint64_t); + PRPList(ConfigData &, DMAFunction &, void *, uint64_t, uint64_t, bool); + ~PRPList(); + + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; +}; + +union SGLDescriptor { + uint8_t data[16]; + struct { + uint64_t address; + uint32_t length; + uint8_t reserved[3]; + uint8_t id; + }; + + SGLDescriptor(); +}; + +struct Chunk { + uint64_t addr; + uint32_t length; + + bool ignore; + + Chunk(); + Chunk(uint64_t, uint32_t, bool); +}; + +class SGL : public DMAInterface { + private: + std::vector chunkList; + uint64_t totalSize; + + void parseSGLDescriptor(SGLDescriptor &); + void parseSGLSegment(uint64_t, uint32_t); + + public: + SGL(ConfigData &, DMAFunction &, void *, uint64_t, uint64_t); + ~SGL(); + + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/interface.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/interface.hh new file mode 100644 index 0000000000..5e1dd83ad3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/interface.hh @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_INTERFACE__ +#define __HIL_NVME_INTERFACE__ + +#include + +#include "sim/dma_interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Controller; + +class Interface : public SimpleSSD::DMAInterface { + protected: + Controller *pController; + + public: + virtual void updateInterrupt(uint16_t, bool) = 0; + virtual void getVendorID(uint16_t &, uint16_t &) = 0; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/namespace.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/namespace.cc new file mode 100644 index 0000000000..d80a72941d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/namespace.cc @@ -0,0 +1,689 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/namespace.hh" + +#include "hil/nvme/subsystem.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +Namespace::Namespace(Subsystem *p, ConfigData &c) + : pParent(p), + pDisk(nullptr), + cfgdata(c), + conf(*c.pConfigReader), + nsid(NSID_NONE), + attached(false), + allocated(false), + formatFinishedAt(0) {} + +Namespace::~Namespace() { + if (pDisk) { + delete pDisk; + } +} + +void Namespace::submitCommand(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + bool response = false; + + if (getTick() < formatFinishedAt) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_FORMAT_IN_PROGRESS); + + response = true; + } + else { + // Admin commands + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_GET_LOG_PAGE: + getLogPage(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + + response = true; + + break; + } + } + + // NVM commands + else { + switch (req.entry.dword0.opcode) { + case OPCODE_FLUSH: + flush(req, func); + break; + case OPCODE_WRITE: + write(req, func); + break; + case OPCODE_READ: + read(req, func); + break; + case OPCODE_COMPARE: + compare(req, func); + break; + case OPCODE_DATASET_MANAGEMEMT: + datasetManagement(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + + response = true; + + break; + } + } + } + + if (response) { + func(resp); + } +} + +void Namespace::setData(uint32_t id, Information *data) { + nsid = id; + memcpy(&info, data, sizeof(Information)); + + if (conf.readBoolean(CONFIG_NVME, NVME_ENABLE_DISK_IMAGE)) { + uint64_t diskSize; + + std::string filename = + conf.readString(CONFIG_NVME, NVME_DISK_IMAGE_PATH + nsid); + + if (filename.length() == 0) { + pDisk = new MemDisk(); + } + else if (conf.readBoolean(CONFIG_NVME, NVME_USE_COW_DISK)) { + pDisk = new CoWDisk(); + } + else { + pDisk = new Disk(); + } + + diskSize = pDisk->open(filename, info.size * info.lbaSize, info.lbaSize); + + if (diskSize == 0) { + panic("Failed to open disk image"); + } + else if (diskSize != info.size * info.lbaSize) { + if (conf.readBoolean(CONFIG_NVME, NVME_STRICT_DISK_SIZE)) { + panic("Disk size not match"); + } + } + + if (filename.length() > 0) { + SimpleSSD::info("Using disk image at %s for NSID %u", filename.c_str(), + nsid); + } + } + + allocated = true; +} + +void Namespace::attach(bool attach) { + attached = attach; +} + +uint32_t Namespace::getNSID() { + return nsid; +} + +Namespace::Information *Namespace::getInfo() { + return &info; +} + +bool Namespace::isAttached() { + return attached; +} + +void Namespace::format(uint64_t tick) { + formatFinishedAt = tick; + + health = HealthInfo(); + + if (pDisk) { + delete pDisk; + pDisk = nullptr; + } +} + +void Namespace::getLogPage(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t numdl = (req.entry.dword10 & 0xFFFF0000) >> 16; + uint16_t lid = req.entry.dword10 & 0xFFFF; + uint16_t numdu = req.entry.dword11 & 0xFFFF; + uint32_t lopl = req.entry.dword12; + uint32_t lopu = req.entry.dword13; + bool submit = true; + + uint32_t req_size = (((uint32_t)numdu << 16 | numdl) + 1) * 4; + uint64_t offset = ((uint64_t)lopu << 32) | lopl; + + debugprint(LOG_HIL_NVME, + "ADMIN | Get Log Page | Log %d | Size %d | NSID %d", lid, + req_size, nsid); + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + DMAFunction smartInfo = [offset](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(offset, 512, pContext->buffer, dmaDone, context); + }; + + switch (lid) { + case LOG_SMART_HEALTH_INFORMATION: + if (req.entry.namespaceID == nsid) { + submit = false; + RequestContext *pContext = new RequestContext(func, resp); + + pContext->buffer = health.data; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2, (uint64_t)req_size); + } + } + else { + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + + break; + default: + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_LOG_PAGE); + break; + } + + if (submit) { + func(resp); + } +} + +void Namespace::flush(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + + func(resp); + } + + if (!err) { + DMAFunction begin = [this](uint64_t, void *context) { + DMAFunction doFlush = [this](uint64_t now, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint( + LOG_HIL_NVME, + "NVM | FLUSH | CQ %u | SQ %u:%u | CID %u | NSID %-5d | %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + pParent->flush(this, doFlush, context); + }; + + debugprint(LOG_HIL_NVME, "NVM | FLUSH | SQ %u:%u | CID %u | NSID %-5d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid); + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + + execute(CPU::NVME__NAMESPACE, CPU::FLUSH, begin, pContext); + } +} + +void Namespace::write(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to write 0 blocks"); + } + + debugprint(LOG_HIL_NVME, + "NVM | WRITE | SQ %u:%u | CID %u | NSID %-5d | %" PRIX64 + " + %d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->beginAt++; + + if (pContext->beginAt == 2) { + debugprint( + LOG_HIL_NVME, + "NVM | WRITE | CQ %u | SQ %u:%u | CID %u | NSID %-5d | " + "%" PRIX64 " + %d | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + pContext->function(pContext->resp); + + if (pContext->buffer) { + pDisk->write(pContext->slba, pContext->nlb, pContext->buffer); + + free(pContext->buffer); + } + + delete pContext->dma; + delete pContext; + } + }; + + IOContext *pContext = (IOContext *)context; + + pContext->tick = tick; + pContext->beginAt = 0; + + if (pDisk) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + + pContext->dma->read(0, pContext->nlb * info.lbaSize, pContext->buffer, + dmaDone, context); + } + else { + pContext->dma->read(0, pContext->nlb * info.lbaSize, nullptr, dmaDone, + context); + } + + pParent->write(this, pContext->slba, pContext->nlb, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__NAMESPACE, CPU::WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nlb * info.lbaSize); + } + } + else { + func(resp); + } +} + +void Namespace::read(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + // bool fua = req.entry.dword12 & 0x40000000; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to read 0 blocks"); + } + + debugprint(LOG_HIL_NVME, + "NVM | READ | SQ %u:%u | CID %u | NSID %-5d | %" PRIX64 + " + %d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->beginAt++; + + if (pContext->beginAt == 2) { + debugprint( + LOG_HIL_NVME, + "NVM | READ | CQ %u | SQ %u:%u | CID %u | NSID %-5d | " + "%" PRIX64 " + %d | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + if (pContext->buffer) { + free(pContext->buffer); + } + + delete pContext->dma; + delete pContext; + } + }; + + IOContext *pContext = (IOContext *)context; + + pContext->tick = tick; + pContext->beginAt = 0; + + pParent->read(this, pContext->slba, pContext->nlb, dmaDone, pContext); + + pContext->buffer = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + + if (pDisk) { + pDisk->read(pContext->slba, pContext->nlb, pContext->buffer); + } + + pContext->dma->write(0, pContext->nlb * info.lbaSize, pContext->buffer, + dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__NAMESPACE, CPU::READ); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * info.lbaSize); + } + } + else { + func(resp); + } +} + +void Namespace::compare(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + // bool fua = req.entry.dword12 & 0x40000000; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to read 0 blocks"); + } + + debugprint(LOG_HIL_NVME, + "NVM | COMP | SQ %u:%u | CID %u | NSID %-5d | %" PRIX64 + " + %d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + CompareContext *pContext = (CompareContext *)context; + + pContext->beginAt++; + + if (pContext->beginAt == 2) { + // Compare buffer! + // Always success if no disk + if (pDisk && memcmp(pContext->buffer, pContext->hostContent, + pContext->nlb * info.lbaSize) != 0) { + pContext->resp.makeStatus(false, false, + TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + STATUS_COMPARE_FAILURE); + } + + debugprint( + LOG_HIL_NVME, + "NVM | COMP | CQ %u | SQ %u:%u | CID %u | NSID %-5d | " + "%" PRIX64 " + %d | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + if (pContext->buffer) { + free(pContext->buffer); + } + if (pContext->hostContent) { + free(pContext->hostContent); + } + + delete pContext->dma; + delete pContext; + } + }; + + CompareContext *pContext = (CompareContext *)context; + + pContext->tick = tick; + pContext->beginAt = 0; + + pParent->read(this, pContext->slba, pContext->nlb, dmaDone, pContext); + + pContext->buffer = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + pContext->hostContent = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + + if (pDisk) { + pDisk->read(pContext->slba, pContext->nlb, pContext->buffer); + } + + pContext->dma->read(0, pContext->nlb * info.lbaSize, + pContext->hostContent, dmaDone, context); + }; + + CompareContext *pContext = new CompareContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__NAMESPACE, CPU::READ); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * info.lbaSize); + } + } + else { + func(resp); + } +} + +void Namespace::datasetManagement(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + int nr = (req.entry.dword10 & 0xFF) + 1; + bool ad = req.entry.dword11 & 0x04; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (!ad) { + err = true; + // Just ignore + } + + debugprint( + LOG_HIL_NVME, + "NVM | TRIM | SQ %u:%u | CID %u | NSID %-5d| %d ranges | Attr %1X", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, nr, + req.entry.dword11 & 0x0F); + + if (!err) { + static DMAFunction eachTrimDone = [](uint64_t tick, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(tick, pContext->context); + } + + delete pContext; + }; + DMAFunction doTrim = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t, void *context) { + DMAFunction trimDone = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "NVM | TRIM | CQ %u | SQ %u:%u | CID %u | NSID %-5d| " + "%" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, + pContext->resp.entry.dword3.commandID, nsid, + pContext->beginAt, tick, tick - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + DatasetManagementRange range; + IOContext *pContext = (IOContext *)context; + DMAContext *pDMA = new DMAContext(trimDone); + + pDMA->context = context; + + for (uint64_t i = 0; i < pContext->slba; i++) { + memcpy(range.data, + pContext->buffer + i * sizeof(DatasetManagementRange), + sizeof(DatasetManagementRange)); + + pDMA->counter++; + pParent->trim(this, range.slba, range.nlb, eachTrimDone, pDMA); + } + + if (pDMA->counter == 0) { + pDMA->counter = 1; + + eachTrimDone(getTick(), pDMA); + } + + free(pContext->buffer); + delete pContext->dma; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = + (uint8_t *)calloc(pContext->slba, sizeof(DatasetManagementRange)); + + pContext->dma->read(0, pContext->slba * sizeof(DatasetManagementRange), + pContext->buffer, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = nr; + + CPUContext *pCPU = new CPUContext(doTrim, pContext, CPU::NVME__NAMESPACE, + CPU::DATASET_MANAGEMENT); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nr * 0x10); + } + } + else { + func(resp); + } +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/namespace.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/namespace.hh new file mode 100644 index 0000000000..8475bf6db1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/namespace.hh @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_NAMESPACE__ +#define __HIL_NVME_NAMESPACE__ + +#include + +#include "hil/nvme/def.hh" +#include "hil/nvme/dma.hh" +#include "hil/nvme/queue.hh" +#include "util/def.hh" +#include "util/disk.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Subsystem; + +typedef union _DatasetManagementRange { + uint8_t data[0x10]; + struct { + uint32_t attr; + uint32_t nlb; + uint64_t slba; + }; +} DatasetManagementRange; + +typedef std::function RequestFunction; + +class RequestContext { + public: + DMAInterface *dma; + RequestFunction function; + CQEntryWrapper resp; + + uint8_t *buffer; + + RequestContext(RequestFunction &f, CQEntryWrapper &r) + : dma(nullptr), function(f), resp(r), buffer(nullptr) {} +}; + +class IOContext : public RequestContext { + public: + uint64_t beginAt; + uint64_t slba; + uint64_t nlb; + uint64_t tick; + + IOContext(RequestFunction &f, CQEntryWrapper &r) : RequestContext(f, r) {} +}; + +class CompareContext : public IOContext { + public: + uint8_t *hostContent; + + CompareContext(RequestFunction &f, CQEntryWrapper &r) + : IOContext(f, r), hostContent(nullptr) {} +}; + +class Namespace { + public: + typedef struct _Information { + uint64_t size; //!< NSZE + uint64_t capacity; //!< NCAP + uint64_t utilization; //!< NUSE + uint64_t sizeInByteL; //. + */ + +#include "hil/nvme/ocssd.hh" + +#include "hil/nvme/controller.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +struct OCSSDContext { + Request req; + std::vector<::CPDPBP> list; + uint64_t beginAt; +}; + +BlockData::_BlockData() : index(0), value(0) {} + +BlockData::_BlockData(uint32_t i, uint8_t v) : index(i), value(v) {} + +ChunkUpdateEntry::_ChunkUpdateEntry(ChunkDescriptor *p, uint32_t i) + : pDesc(p), pageIdx(i) {} + +OpenChannelSSD12::OpenChannelSSD12(Controller *c, ConfigData &cfg) + : Subsystem(c, cfg), + lastScheduled(0), + eraseCount(0), + readCount(0), + writeCount(0) { + completionEvent = allocate([this](uint64_t) { completion(); }); +} + +OpenChannelSSD12::~OpenChannelSSD12() { + for (auto &iter : lNamespaces) { + delete iter; + } + + delete pPALOLD; + delete pDisk; +} + +void OpenChannelSSD12::init() { + bool useMP = conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + param.channel = conf.readUint(CONFIG_PAL, PAL::PAL_CHANNEL); + param.package = conf.readUint(CONFIG_PAL, PAL::PAL_PACKAGE); + + param.die = conf.readUint(CONFIG_PAL, PAL::NAND_DIE); + param.plane = conf.readUint(CONFIG_PAL, PAL::NAND_PLANE); + param.block = conf.readUint(CONFIG_PAL, PAL::NAND_BLOCK); + param.page = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE); + param.pageSize = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE_SIZE); + param.superPageSize = param.pageSize; + + // Super block includes plane + if (useMP) { + param.superPageSize *= param.plane; + } + + // Print super block information + debugprint(LOG_PAL, + "Channel | Way | Die | Plane | Block | Page "); + debugprint(LOG_PAL, "%7u | %7u | %7u | %7u | %7u | %7u", param.channel, + param.package, param.die, param.plane, param.block, param.page); + debugprint(LOG_PAL, "Multi-plane mode %s", useMP ? "enabled" : "disabled"); + debugprint(LOG_PAL, "Page size %u -> %u", param.pageSize, + param.superPageSize); + debugprint( + LOG_PAL, "Total block count %u -> %u", + param.channel * param.package * param.die * param.plane * param.block, + param.superBlock); + + pPALOLD = new PAL::PALOLD(param, conf); + + // Set geometry + structure.group = param.channel; + structure.parallelUnit = param.package; + structure.parallelUnit *= param.die; + structure.chunk = param.block; + structure.chunk *= useMP ? 1 : param.plane; + structure.chunkSize = param.page * param.superPageSize / LBA_SIZE; + structure.writeSize = param.superPageSize / LBA_SIZE; + + // Print structure + debugprint(LOG_HIL_NVME, "OpenChannel SSD v1.2"); + debugprint(LOG_HIL_NVME, "OpenChannel SSD Structure: (Blk size is %u)", + LBA_SIZE); + debugprint(LOG_HIL_NVME, " Group | PU (LUN) | Chunk | Chunk Size " + "| Write Size"); + debugprint(LOG_HIL_NVME, " %4u | %6u | %6u | %6u Blk | %6u Blk", + structure.group, structure.parallelUnit, structure.chunk, + structure.chunkSize, structure.writeSize); + debugprint(LOG_HIL_NVME, + " In total: | %6u | %6u | %u Blk / %" PRIu64 " Bytes", + structure.group * structure.parallelUnit, + structure.group * structure.parallelUnit * structure.chunk, + structure.group * structure.parallelUnit * structure.chunk * + structure.chunkSize, + (uint64_t)structure.group * structure.parallelUnit * + structure.chunk * structure.chunkSize * LBA_SIZE); + debugprint(LOG_HIL_NVME, "nvm notation (old): [%u/1/%u/%u/%u/%u]", + structure.writeSize, param.page, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + debugprint(LOG_HIL_NVME, "nvm notation (new): [%u/%u/%u/%u/%u]", + structure.writeSize, structure.writeSize, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + + // Calculate mask + uint32_t lastidx = 0; + uint64_t sum = 0; + + int sectorPerPage = param.superPageSize / LBA_SIZE; + + ppaMask.sectorMask = generateMask(sectorPerPage, lastidx); + ppaMask.pageShift = lastidx; + ppaMask.pageMask = generateMask(param.page, lastidx); + ppaMask.blockShift = lastidx; + ppaMask.blockMask = generateMask(structure.chunk, lastidx); + ppaMask.planeShift = lastidx; + ppaMask.planeMask = 0; // No plane + ppaMask.dieShift = lastidx; + ppaMask.dieMask = 0; // No die + ppaMask.wayShift = lastidx; + ppaMask.wayMask = generateMask(structure.parallelUnit, lastidx); + ppaMask.channelShift = lastidx; + ppaMask.channelMask = generateMask(structure.group, lastidx); + + sum ^= ppaMask.sectorMask; + sum ^= ppaMask.pageMask; + sum ^= ppaMask.blockMask; + sum ^= ppaMask.planeMask; + sum ^= ppaMask.dieMask; + sum ^= ppaMask.wayMask; + sum ^= ppaMask.channelMask; + + ppaMask.padding = ~sum; + + // Create default namespace + Namespace::Information info; + + info.lbaSize = LBA_SIZE; + info.lbaFormatIndex = 3; // See subsystem.cc + info.dataProtectionSettings = 0; + info.namespaceSharingCapabilities = 0; + info.sizeInByteL = structure.group * structure.parallelUnit * structure.chunk; + info.size = info.sizeInByteL * structure.chunkSize; + info.sizeInByteL *= LBA_SIZE * structure.chunkSize; + info.sizeInByteH = 0; + info.capacity = info.size; + info.utilization = info.size; + + Namespace *pNS = new Namespace(this, cfgdata); + + pNS->setData(1, &info); + pNS->attach(true); + + lNamespaces.push_back(pNS); + + // Open Disk image + pDisk = new MemDisk(); + + pDisk->open("", info.sizeInByteL, LBA_SIZE); +} + +void OpenChannelSSD12::submitCommand(SQEntryWrapper &req, + RequestFunction func) { + struct CommandContext { + SQEntryWrapper req; + RequestFunction func; + + CommandContext(SQEntryWrapper &r, RequestFunction &f) : req(r), func(f) {} + }; + + CQEntryWrapper resp(req); + bool processed = false; + + commandCount++; + + // Admin command + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_DELETE_IO_SQUEUE: + processed = deleteSQueue(req, func); + break; + case OPCODE_CREATE_IO_SQUEUE: + processed = createSQueue(req, func); + break; + case OPCODE_GET_LOG_PAGE: + processed = getLogPage(req, func); + break; + case OPCODE_DELETE_IO_CQUEUE: + processed = deleteCQueue(req, func); + break; + case OPCODE_CREATE_IO_CQUEUE: + processed = createCQueue(req, func); + break; + case OPCODE_IDENTIFY: + processed = identify(req, func); + break; + case OPCODE_ABORT: + processed = abort(req, func); + break; + case OPCODE_SET_FEATURES: + processed = setFeatures(req, func); + break; + case OPCODE_GET_FEATURES: + processed = getFeatures(req, func); + break; + case OPCODE_ASYNC_EVENT_REQ: + break; + case OPCODE_DEVICE_IDENTIFICATION: + processed = deviceIdentification(req, func); + break; + case OPCODE_GET_BAD_BLOCK_TABLE: + processed = getBadBlockTable(req, func); + break; + case OPCODE_SET_BAD_BLOCK_TABLE: + processed = setBadBlockTable(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + break; + } + } + + // NVM commands or Namespace specific Admin commands + if (!processed) { + if (req.entry.namespaceID == NSID_ALL || req.entry.namespaceID == 1) { + processed = true; + + switch (req.entry.dword0.opcode) { + case OPCODE_READ: + // This for automatic partition table detection + // Just return SUCCESS, which means null data + debugprint(LOG_HIL_NVME, "OCSSD | READ | Ignored"); + + func(resp); + break; + case OPCODE_PHYSICAL_BLOCK_ERASE: + physicalBlockErase(req, func); + break; + case OPCODE_PHYSICAL_PAGE_READ: + physicalPageRead(req, func); + break; + case OPCODE_PHYSICAL_PAGE_WRITE: + physicalPageWrite(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + processed = false; + break; + } + } + } + + // Invalid namespace + if (!processed) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + + func(resp); + } +} + +void OpenChannelSSD12::getNVMCapacity(uint64_t &total, uint64_t &used) { + total = structure.group * structure.parallelUnit * structure.chunk * + structure.chunkSize; + used = total; +} + +uint32_t OpenChannelSSD12::validNamespaceCount() { + return 1; +} + +bool OpenChannelSSD12::parsePPA(uint64_t ppa, ::CPDPBP &addr) { + if ((ppa & ppaMask.padding) == 0) { + addr.Channel = (ppa & ppaMask.channelMask) >> ppaMask.channelShift; + addr.Package = (ppa & ppaMask.wayMask) >> ppaMask.wayShift; + addr.Die = (ppa & ppaMask.dieMask) >> ppaMask.dieShift; + addr.Plane = (ppa & ppaMask.planeMask) >> ppaMask.planeShift; + addr.Block = (ppa & ppaMask.blockMask) >> ppaMask.blockShift; + addr.Page = (ppa & ppaMask.pageMask) >> ppaMask.pageShift; + + return true; + } + + return false; +} + +void OpenChannelSSD12::convertUnit(::CPDPBP &addr) { + static bool useMP = + conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + addr.Die = addr.Package % param.die; + addr.Package = addr.Package / param.die; + if (useMP) { + addr.Plane = 0; + } + else { + addr.Plane = addr.Block % param.plane; + addr.Block = addr.Block / param.plane; + } +} + +void OpenChannelSSD12::mergeList(std::vector &lbaList, + std::vector<::CPDPBP> &list, bool block) { + ::CPDPBP temp; + + list.clear(); + + for (auto &lba : lbaList) { + if (parsePPA(lba, temp)) { + convertUnit(temp); + + if (list.size() > 0) { + auto &back = list.back(); + + if (back.Channel == temp.Channel && back.Package == temp.Package && + back.Die == temp.Die && back.Plane == temp.Plane && + back.Block == temp.Block && (block || back.Page == temp.Page)) { + continue; + } + } + + list.push_back(temp); + } + } +} + +void OpenChannelSSD12::updateCompletion() { + if (completionQueue.size() > 0) { + if (lastScheduled != completionQueue.top().finishedAt) { + lastScheduled = completionQueue.top().finishedAt; + + if (lastScheduled < getTick()) { + warn("Invalid tick %" PRIu64, lastScheduled); + lastScheduled = getTick(); + } + + schedule(completionEvent, lastScheduled); + } + } +} + +void OpenChannelSSD12::completion() { + uint64_t tick = getTick(); + + while (completionQueue.size() > 0) { + auto &req = completionQueue.top(); + + if (req.finishedAt <= tick) { + req.function(tick, req.context); + + completionQueue.pop(); + } + else { + break; + } + } + + updateCompletion(); +} + +bool OpenChannelSSD12::deviceIdentification(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + PAL::NAND_TYPE type = + (PAL::NAND_TYPE)conf.readInt(CONFIG_PAL, PAL::NAND_FLASH_TYPE); + + RequestContext *pContext = new RequestContext(func, resp); + + uint8_t *data = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + debugprint(LOG_HIL_NVME, "OCSSD | Device Identification"); + + // Version + data[0x00] = 0x01; // OpenChannel SSD v1.x + + // Vendor NVM opcode command set + data[0x01] = 0x00; + + // Configuration groups + data[0x02] = 0x01; + data[0x03] = 0x00; // Reserved + + // Device capabilities and feature support + // [Bits ] Description + // [31:02] Reserved + // [01:01] 1 for support hybrid command + // [00:00] 1 for support bad block table management + data[0x04] = 0x01; + data[0x05] = 0x00; + data[0x06] = 0x00; + data[0x07] = 0x00; + + // Device operating mode + // [Bits ] Description + // [31:02] Reserved + // [01:01] 1 for ECC is provided by host + // [00:00] 1 for operating in hybrid mode + data[0x08] = 0x00; + data[0x09] = 0x00; + data[0x0A] = 0x00; + data[0x0B] = 0x00; + + // PPA Format + { + data[0x0C] = ppaMask.channelShift; + data[0x0D] = popcount(ppaMask.channelMask); + data[0x0E] = __builtin_ffsl(ppaMask.wayMask | ppaMask.dieMask) - 1; + data[0x0F] = popcount(ppaMask.wayMask | ppaMask.dieMask); + data[0x10] = ppaMask.planeShift; + data[0x11] = popcount(ppaMask.planeMask); + data[0x12] = ppaMask.blockShift; + data[0x13] = popcount(ppaMask.blockMask); + data[0x14] = ppaMask.pageShift; + data[0x15] = popcount(ppaMask.pageMask); + data[0x16] = 0; + data[0x17] = popcount(ppaMask.sectorMask); + } + + // Description of 1st group + { + // Media type + data[0x100] = 0x00; // NAND Flash + + // Flash type + switch (type) { + case PAL::NAND_SLC: + data[0x101] = 0; + break; + case PAL::NAND_MLC: + data[0x101] = 1; + break; + default: + panic("Unsupported NAND type in OpenChannel SSD v1.2"); + break; + } + + // Number of channels + data[0x104] = structure.group; + + // Number of LUNs + data[0x105] = structure.parallelUnit; + + // Number of planes + data[0x106] = 1; + + // Number of blocks + *(uint16_t *)(data + 0x108) = structure.chunk; + + // Number of pages + *(uint16_t *)(data + 0x10A) = param.page; + + // Size of page + *(uint16_t *)(data + 0x10C) = param.superPageSize; + + // Size of sector + *(uint16_t *)(data + 0x10E) = LBA_SIZE; + + // Sector meta size + *(uint16_t *)(data + 0x110) = 0; + + // Performance Related Metrics + PAL::Config::NANDTiming *pNANDTiming = conf.getNANDTiming(); + + // Typical page read time + *(uint32_t *)(data + 0x114) = pNANDTiming->msb.read / 1000; + + // Typical page write time + *(uint32_t *)(data + 0x11C) = pNANDTiming->msb.write / 1000; + + if (conf.readInt(CONFIG_PAL, PAL::NAND_FLASH_TYPE) != PAL::NAND_SLC) { + // Max page read time + *(uint32_t *)(data + 0x118) = pNANDTiming->lsb.read / 1000; + + // Max page write time + *(uint32_t *)(data + 0x120) = pNANDTiming->lsb.write / 1000; + } + else { + // Max page read time + *(uint32_t *)(data + 0x118) = pNANDTiming->msb.read / 1000; + + // Max page write time + *(uint32_t *)(data + 0x120) = pNANDTiming->msb.write / 1000; + } + + // Typical block erase time + *(uint32_t *)(data + 0x124) = pNANDTiming->erase / 1000; + + // Max block erase time + *(uint32_t *)(data + 0x128) = pNANDTiming->erase / 1000; + + // Multi-plane operations + // [Bits ] Description + // [31:19] Reserved + // [18:18] 1 for Quad plane erase + // [17:17] 1 for Dual plane erase + // [16:16] 1 for Single plane erase + // [15:11] Reserved + // [10:10] 1 for Quad plane write + // [09:09] 1 for Dual plane write + // [08:08] 1 for Single plane write + // [07:03] Reserved + // [02:02] 1 for Quad plane read + // [01:01] 1 for Dual plane read + // [00:00] 1 for Single plane read + data[0x12C] = 0x00; + data[0x12D] = 0x00; + data[0x12E] = 0x00; + data[0x12F] = 0x00; + + // Media and Controller Capabilities + // [Bits ] Description + // [31:04] Reserved + // [03:03] 1 for support Encryption + // [02:02] 1 for support Scramble On/Off + // [01:01] 1 for support Command suspension + // [00:00] 1 for support SLC mode + data[0x130] = 0x01; + data[0x131] = 0x00; + data[0x132] = 0x00; + data[0x133] = 0x00; + + // Channel parallelism + *(uint16_t *)(data + 0x134) = 1; + + // Media type specific data + memset(data + 0x140, 0, 896); + + if (type == PAL::NAND_MLC) { + *(uint16_t *)(data + 0x148) = 1; + data[0x14A] = 0x11; + } + } + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + static DMAFunction doWrite = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + pContext->buffer = data; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + + return true; +} + +bool OpenChannelSSD12::setBadBlockTable(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + IOContext *pContext = new IOContext(func, resp); + + uint16_t nppa = (req.entry.dword12 & 0xFFFF) + 1; + uint8_t val = (req.entry.dword12 & 0xFF0000) >> 16; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + debugprint(LOG_HIL_NVME, "OCSSD | Set Badblock Table"); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + std::vector ppaList; + CPDPBP addr; + uint8_t val = pContext->tick; + + if (pContext->nlb == 1) { + ppaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + ppaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + for (auto &iter : ppaList) { + if (parsePPA(iter, addr)) { + auto data = badBlocks.find(iter); + + if (data == badBlocks.end()) { + // Push new value + if (val != 0) { + badBlocks.insert({iter, BlockData(addr.Block, val)}); + } + } + else { + if (val == 0) { + badBlocks.erase(data); + } + else { + data->second.index = addr.Block; + data->second.value = val; + } + } + + convertUnit(addr); + + debugprint( + LOG_HIL_NVME, + "OCSSD | C %5u | W %5u | D %5u | P %5u | B %5u | P %5u", + addr.Channel, addr.Package, addr.Die, addr.Plane, addr.Block, + addr.Page); + } + } + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + pContext->dma->read(0, pContext->nlb * 8, pContext->buffer, dmaDone, + context); + }; + + pContext->tick = val; + pContext->dma = new PRPList(cfgdata, doRead, pContext, pContext->slba, + (uint64_t)nppa * 8, true); + } + + if (err) { + func(resp); + } + + return true; +} + +bool OpenChannelSSD12::getBadBlockTable(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + CPDPBP addr; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint64_t prpsize = 64 + structure.chunk; + + RequestContext *pContext = new RequestContext(func, resp); + + debugprint(LOG_HIL_NVME, "OCSSD | Get Badblock Table"); + + uint64_t mask = ppaMask.channelMask | ppaMask.wayMask | ppaMask.dieMask; + uint8_t *data = (uint8_t *)calloc(prpsize, 1); + + if (parsePPA(ppa, addr) && data) { + convertUnit(addr); + + debugprint(LOG_HIL_NVME, + "OCSSD | C %5u | W %5u | D %5u | P %5u | B %5u | P %5u", + addr.Channel, addr.Package, addr.Die, addr.Plane, addr.Block, + addr.Page); + + // Table ID + memcpy(data, "BBLT", 4); + // Version number + *(uint16_t *)(data + 0x04) = 1; + // Total number of blocks in this LUN + *(uint32_t *)(data + 0x0C) = prpsize - 64; + // Number of factory bad blocks + *(uint32_t *)(data + 0x10) = 0; + // Number of grown bad blocks + *(uint32_t *)(data + 0x14) = 0; + // Number of device reserved blocks + *(uint32_t *)(data + 0x18) = 0; + // Number of host reserved blocks + *(uint32_t *)(data + 0x1C) = 0; + memset(data + 0x20, 0, 32); // Reserved + // Block table + memset(data + 0x40, 0, prpsize - 64); + + for (auto iter = badBlocks.begin(); iter != badBlocks.end(); iter++) { + if ((iter->first & mask) == (ppa & mask)) { + data[0x40 + iter->second.index] = iter->second.value; + } + } + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + DMAFunction doWrite = [prpsize](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, prpsize, pContext->buffer, dmaDone, context); + }; + + pContext->buffer = data; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, prpsize); + } + } + else { + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + + func(resp); + } + + return true; +} + +void OpenChannelSSD12::physicalBlockErase(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + IOContext *pContext = new IOContext(func, resp); + + uint8_t nppa = (req.entry.dword12 & 0x3F) + 1; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + eraseCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Physical Block Erase | %d lbas", nppa); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doErase = [this](uint64_t now, void *context) { + DMAFunction dmaDone = [this](uint64_t now, void *context) { + DMAFunction nandDone = [](uint64_t now, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Physical Block Erase | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + std::vector ppaList; + std::vector<::CPDPBP> list; + uint64_t beginAt; + uint64_t finishedAt = now; + + if (pContext->nlb == 1) { + ppaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + ppaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + for (uint64_t i = 0; i < pContext->nlb; i++) { + pDisk->erase(ppaList.at(i), 1); + } + + mergeList(ppaList, list, true); + + for (auto &iter : list) { + beginAt = now; + + pPALOLD->erase(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + Request req = Request(nandDone, context); + req.finishedAt = finishedAt; + + completionQueue.push(req); + updateCompletion(); + + delete pContext->dma; + }; + + IOContext *pContext = (IOContext *)context; + + if (pContext->nlb > 1) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + pContext->dma->read(0, pContext->nlb * 8, pContext->buffer, dmaDone, + context); + } + else { + dmaDone(now, context); + } + }; + + CPUContext *pCPU = new CPUContext(doErase, pContext, CPU::NVME__OCSSD, + CPU::PHYSICAL_BLOCK_ERASE); + + pContext->beginAt = getTick(); + + if (pContext->nlb > 1) { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, pContext->slba, + (uint64_t)nppa * 8, true); + } + else { + pContext->dma = nullptr; + + cpuHandler(getTick(), pCPU); + } + } + + if (err) { + func(resp); + } +} + +void OpenChannelSSD12::physicalPageWrite(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + VectorContext *pContext = new VectorContext(func, resp); + + uint8_t nppa = (req.entry.dword12 & 0x3F) + 1; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + writeCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Physical Page Write | %d lbas", nppa); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doDMA = [this](uint64_t now, void *context) { + DMAFunction doWrite = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t now, void *context) { + DMAFunction nandDone = [](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Physical Page Write | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->resp.entry.dword0 = 0xFFFFFFFF; + pContext->resp.entry.reserved = 0xFFFFFFFF; + + pContext->function(pContext->resp); + + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + uint64_t beginAt; + uint64_t finishedAt = now; + std::vector<::CPDPBP> list; + + for (uint64_t i = 0; i < pContext->nlb; i++) { + pDisk->write(pContext->lbaList.at(i), 1, + pContext->buffer + i * LBA_SIZE); + } + + mergeList(pContext->lbaList, list); + + for (auto &iter : list) { + beginAt = now; + + pPALOLD->write(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + Request req = Request(nandDone, context); + req.finishedAt = finishedAt; + + completionQueue.push(req); + updateCompletion(); + + free(pContext->buffer); + delete pContext->dma; + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb == 1) { + pContext->lbaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back( + *(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + pContext->buffer = (uint8_t *)calloc(pContext->nlb * LBA_SIZE, 1); + pContext->dma->read(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, pContext->nlb * 8, + pContext->buffer, doWrite, context); + } + else { + doWrite(now, context); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::PHYSICAL_PAGE_WRITE); + + pContext->beginAt = getTick(); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nppa * LBA_SIZE); + } + } + + if (err) { + func(resp); + } +} + +void OpenChannelSSD12::physicalPageRead(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + VectorContext *pContext = new VectorContext(func, resp); + + uint8_t nppa = (req.entry.dword12 & 0x3F) + 1; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + readCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Physical Page Read | %d lbas", nppa); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doDMA = [this](uint64_t now, void *context) { + DMAFunction doRead = [this](uint64_t now, void *context) { + DMAFunction nandDone = [](uint64_t, void *context) { + DMAFunction dmaDone = [](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Physical Block Read | %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->resp.entry.dword0 = 0xFFFFFFFF; + pContext->resp.entry.reserved = 0xFFFFFFFF; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + pContext->dma->write(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + + std::vector<::CPDPBP> list; + uint64_t beginAt; + uint64_t finishedAt = now; + + if (pContext->nlb == 1) { + pContext->lbaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back( + *(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + pContext->buffer = (uint8_t *)calloc(pContext->nlb * LBA_SIZE, 1); + + for (uint64_t i = 0; i < pContext->nlb; i++) { + pDisk->read(pContext->lbaList.at(i), 1, + pContext->buffer + i * LBA_SIZE); + } + + mergeList(pContext->lbaList, list); + + for (auto &iter : list) { + beginAt = now; + + pPALOLD->read(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + Request req = Request(nandDone, context); + req.finishedAt = finishedAt; + + completionQueue.push(req); + updateCompletion(); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, pContext->nlb * 8, + pContext->buffer, doRead, context); + } + else { + doRead(now, context); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::PHYSICAL_PAGE_READ); + + pContext->beginAt = getTick(); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nppa * LBA_SIZE); + } + } + + if (err) { + func(resp); + } +} + +void OpenChannelSSD12::getStatList(std::vector &list, + std::string prefix) { + Stats temp; + + temp.name = prefix + "command_count"; + temp.desc = "Total number of OCSSD command handled"; + list.push_back(temp); + + temp.name = prefix + "erase"; + temp.desc = "Total number of Physical Block Erase command"; + list.push_back(temp); + + temp.name = prefix + "read"; + temp.desc = "Total number of Physical Page Read command"; + list.push_back(temp); + + temp.name = prefix + "write"; + temp.desc = "Total number of Physical Page Write command"; + list.push_back(temp); + + pPALOLD->getStatList(list, prefix + "pal."); +} + +void OpenChannelSSD12::getStatValues(std::vector &values) { + values.push_back(commandCount); + values.push_back(eraseCount); + values.push_back(readCount); + values.push_back(writeCount); + + pPALOLD->getStatValues(values); +} + +void OpenChannelSSD12::resetStatValues() { + commandCount = 0; + eraseCount = 0; + readCount = 0; + writeCount = 0; + + pPALOLD->resetStatValues(); +} + +OpenChannelSSD20::OpenChannelSSD20(Controller *c, ConfigData &cfg) + : OpenChannelSSD12(c, cfg), + pDescriptor(nullptr), + vectorEraseCount(0), + vectorReadCount(0), + vectorWriteCount(0) {} + +OpenChannelSSD20::~OpenChannelSSD20() { + free(pDescriptor); +} + +void OpenChannelSSD20::init() { + bool useMP = conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + param.channel = conf.readUint(CONFIG_PAL, PAL::PAL_CHANNEL); + param.package = conf.readUint(CONFIG_PAL, PAL::PAL_PACKAGE); + + param.die = conf.readUint(CONFIG_PAL, PAL::NAND_DIE); + param.plane = conf.readUint(CONFIG_PAL, PAL::NAND_PLANE); + param.block = conf.readUint(CONFIG_PAL, PAL::NAND_BLOCK); + param.page = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE); + param.pageSize = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE_SIZE); + param.superPageSize = param.pageSize; + + // Super block includes plane + if (useMP) { + param.superPageSize *= param.plane; + } + + // Print super block information + debugprint(LOG_PAL, + "Channel | Way | Die | Plane | Block | Page "); + debugprint(LOG_PAL, "%7u | %7u | %7u | %7u | %7u | %7u", param.channel, + param.package, param.die, param.plane, param.block, param.page); + debugprint(LOG_PAL, "Multi-plane mode %s", useMP ? "enabled" : "disabled"); + debugprint(LOG_PAL, "Page size %u -> %u", param.pageSize, + param.superPageSize); + debugprint( + LOG_PAL, "Total block count %u -> %u", + param.channel * param.package * param.die * param.plane * param.block, + param.superBlock); + + pPALOLD = new PAL::PALOLD(param, conf); + + // Set geometry + structure.group = param.channel; + structure.parallelUnit = param.package; + structure.parallelUnit *= param.die; + structure.chunk = param.block; + structure.chunk *= useMP ? 1 : param.plane; + structure.chunkSize = param.page * param.superPageSize / LBA_SIZE; + structure.writeSize = param.superPageSize / LBA_SIZE; + + // Print structure + debugprint(LOG_HIL_NVME, "OpenChannel SSD v2.0"); + debugprint(LOG_HIL_NVME, "OpenChannel SSD Structure: (Blk size is %u)", + LBA_SIZE); + debugprint(LOG_HIL_NVME, " Group | PU (LUN) | Chunk | Chunk Size " + "| Write Size"); + debugprint(LOG_HIL_NVME, " %4u | %6u | %6u | %6u Blk | %6u Blk", + structure.group, structure.parallelUnit, structure.chunk, + structure.chunkSize, structure.writeSize); + debugprint(LOG_HIL_NVME, + " In total: | %6u | %6u | %u Blk / %" PRIu64 " Bytes", + structure.group * structure.parallelUnit, + structure.group * structure.parallelUnit * structure.chunk, + structure.group * structure.parallelUnit * structure.chunk * + structure.chunkSize, + (uint64_t)structure.group * structure.parallelUnit * + structure.chunk * structure.chunkSize * LBA_SIZE); + debugprint(LOG_HIL_NVME, "nvm notation (old): [%u/1/%u/%u/%u/%u]", + structure.writeSize, param.page, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + debugprint(LOG_HIL_NVME, "nvm notation (new): [%u/%u/%u/%u/%u]", + structure.writeSize, structure.writeSize, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + + // Calculate mask + uint32_t lastidx = 0; + + ppaMask.sectorMask = generateMask(structure.chunkSize, lastidx); + ppaMask.blockShift = lastidx; + ppaMask.blockMask = generateMask(structure.chunk, lastidx); + ppaMask.wayShift = lastidx; + ppaMask.wayMask = generateMask(structure.parallelUnit, lastidx); + ppaMask.channelShift = lastidx; + ppaMask.channelMask = generateMask(structure.group, lastidx); + + // Chunk Descriptor + descriptorLength = structure.group * structure.parallelUnit * structure.chunk; + pDescriptor = + (ChunkDescriptor *)calloc(descriptorLength, sizeof(ChunkDescriptor)); + + for (uint32_t g = 0; g < structure.group; g++) { + for (uint32_t p = 0; p < structure.parallelUnit; p++) { + for (uint32_t c = 0; c < structure.chunk; c++) { + auto desc = getChunkDescriptor(g, p, c); + + desc->chunkState = FREE; + desc->chunkType = 0x01; // Force sequential write + desc->slba = makeLBA(g, p, c, 0); + desc->nlb = structure.chunkSize; + } + } + } + + // Create default namespace + Namespace::Information info; + + info.lbaSize = LBA_SIZE; + info.lbaFormatIndex = 3; // See subsystem.cc + info.dataProtectionSettings = 0; + info.namespaceSharingCapabilities = 0; + info.sizeInByteL = structure.group * structure.parallelUnit * structure.chunk; + info.size = info.sizeInByteL * structure.chunkSize; + info.sizeInByteL *= LBA_SIZE * structure.chunkSize; + info.sizeInByteH = 0; + info.capacity = info.size; + info.utilization = info.size; + + Namespace *pNS = new Namespace(this, cfgdata); + + pNS->setData(1, &info); + pNS->attach(true); + + lNamespaces.push_back(pNS); + + // Open Disk image + pDisk = new MemDisk(); + + pDisk->open("", info.sizeInByteL, LBA_SIZE); +} + +void OpenChannelSSD20::submitCommand(SQEntryWrapper &req, + RequestFunction func) { + struct CommandContext { + SQEntryWrapper req; + RequestFunction func; + + CommandContext(SQEntryWrapper &r, RequestFunction &f) : req(r), func(f) {} + }; + + CQEntryWrapper resp(req); + bool processed = false; + + commandCount++; + + // Admin command + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_DELETE_IO_SQUEUE: + processed = deleteSQueue(req, func); + break; + case OPCODE_CREATE_IO_SQUEUE: + processed = createSQueue(req, func); + break; + case OPCODE_GET_LOG_PAGE: + processed = getLogPage(req, func); + break; + case OPCODE_DELETE_IO_CQUEUE: + processed = deleteCQueue(req, func); + break; + case OPCODE_CREATE_IO_CQUEUE: + processed = createCQueue(req, func); + break; + case OPCODE_IDENTIFY: + processed = identify(req, func); + break; + case OPCODE_ABORT: + processed = abort(req, func); + break; + case OPCODE_SET_FEATURES: + processed = setFeatures(req, func); + break; + case OPCODE_GET_FEATURES: + processed = getFeatures(req, func); + break; + case OPCODE_ASYNC_EVENT_REQ: + break; + case OPCODE_GEOMETRY: + processed = geometry(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + break; + } + } + + // NVM commands or Namespace specific Admin commands + if (!processed) { + if (req.entry.namespaceID == NSID_ALL || req.entry.namespaceID == 1) { + processed = true; + + switch (req.entry.dword0.opcode) { + case OPCODE_READ: + read(req, func); + break; + case OPCODE_WRITE: + write(req, func); + break; + case OPCODE_DATASET_MANAGEMEMT: + datasetManagement(req, func); + break; + case OPCODE_VECTOR_CHUNK_RESET: + vectorChunkReset(req, func); + break; + case OPCODE_VECTOR_CHUNK_READ: + vectorChunkRead(req, func); + break; + case OPCODE_VECTOR_CHUNK_WRITE: + vectorChunkWrite(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + processed = false; + break; + } + } + } + + // Invalid namespace + if (!processed) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + + func(resp); + } +} + +ChunkDescriptor *OpenChannelSSD20::getChunkDescriptor(uint32_t g, uint32_t p, + uint32_t c) { + return &pDescriptor[g * structure.parallelUnit * structure.chunk + + p * structure.chunk + c]; +} + +uint64_t OpenChannelSSD20::makeLBA(uint32_t g, uint32_t p, uint32_t c, + uint32_t l) { + uint64_t ret = 0; + + ret = l & ppaMask.sectorMask; + ret |= (c << ppaMask.blockShift) & ppaMask.blockMask; + ret |= (p << ppaMask.wayShift) & ppaMask.wayMask; + ret |= (g << ppaMask.channelShift) & ppaMask.channelMask; + + return ret; +} + +void OpenChannelSSD20::parseLBA(uint64_t lba, uint32_t &g, uint32_t &p, + uint32_t &c, uint32_t &l) { + l = lba & ppaMask.sectorMask; + c = (lba & ppaMask.blockMask) >> ppaMask.blockShift; + p = (lba & ppaMask.wayMask) >> ppaMask.wayShift; + g = (lba & ppaMask.channelMask) >> ppaMask.channelShift; +} + +void OpenChannelSSD20::convertUnit(std::vector &lbaList, + std::vector<::CPDPBP> &list, + std::vector &chunk, + bool block, bool mode) { + static bool useMP = + conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + list.clear(); + chunk.clear(); + + // Optimize this + auto convert = [&](uint64_t lba) { + ::CPDPBP temp; + uint32_t g, p, c, l; + + parseLBA(lba, g, p, c, l); + + // Group -> [Channel] + // Parallel Unit -> [Package][Die] + // Chunk -> [Block][Plane] + temp.Channel = g; + temp.Package = p / param.die; + temp.Die = p % param.die; + + if (useMP) { + temp.Plane = 0; + temp.Block = c; + } + else { + temp.Plane = c % param.plane; + temp.Block = c / param.plane; + } + + temp.Page = l / structure.writeSize; + + if (list.size() > 0) { + auto &back = list.back(); + + if (back.Channel == temp.Channel && back.Package == temp.Package && + back.Die == temp.Die && back.Plane == temp.Plane && + back.Block == temp.Block && (block || back.Page == temp.Page)) { + return; + } + } + + chunk.push_back(ChunkUpdateEntry(getChunkDescriptor(g, p, c), temp.Page)); + list.push_back(temp); + }; + + if (mode) { + for (auto &lba : lbaList) { + convert(lba); + } + } + else { + for (uint64_t lba = lbaList.front(); lba < lbaList.back(); lba++) { + convert(lba); + } + } +} + +void OpenChannelSSD20::readInternal(std::vector &lbaList, + DMAFunction &func, void *context, + bool mode) { + OCSSDContext *pContext = new OCSSDContext(); + std::vector chunks; + bool err = false; + uint64_t idx = 1; + + pContext->req = Request(func, context); + pContext->beginAt = + getTick() + applyLatency(CPU::NVME__OCSSD, CPU::CONVERT_UNIT); + + convertUnit(lbaList, pContext->list, chunks, false, mode); + + // Update ChunkDescriptor + for (auto &iter : chunks) { + // Check block status + if (iter.pDesc->chunkState == OFFLINE) { + warn("Reading dead block"); + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + STATUS_DEALLOCATED_OR_UNWRITTEN_LOGICAL_BLOCK); + } + + if (err) { + if (idx <= 0xFFFFFFFF) { + ((IOContext *)context)->resp.entry.dword0 |= idx; + } + else { + ((IOContext *)context)->resp.entry.reserved |= (idx >> 32); + } + } + + idx <<= 1; + } + + if (!err) { + ((IOContext *)context)->resp.entry.dword0 = 0xFFFFFFFF; + ((IOContext *)context)->resp.entry.reserved = 0xFFFFFFFF; + } + else { + // Remove invalid LBAs + uint64_t mask = ((IOContext *)context)->resp.entry.reserved; + idx = 1; + + mask <<= 32; + mask |= ((IOContext *)context)->resp.entry.dword0; + + for (auto iter = pContext->list.begin(); iter != pContext->list.end();) { + if (mask & idx) { + iter = pContext->list.erase(iter); + } + else { + iter++; + } + + idx <<= 1; + } + } + + DMAFunction doRead = [this](uint64_t tick, void *context) { + auto pContext = (OCSSDContext *)context; + + tick = MAX(tick, pContext->beginAt); + + uint64_t beginAt; + uint64_t finishedAt = tick; + + for (auto &iter : pContext->list) { + beginAt = pContext->beginAt; + + pPALOLD->read(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + pContext->req.finishedAt = finishedAt; + completionQueue.push(pContext->req); + + updateCompletion(); + + delete pContext; + }; + + execute(CPU::NVME__OCSSD, CPU::READ_INTERNAL, doRead, pContext); +} + +void OpenChannelSSD20::writeInternal(std::vector &lbaList, + DMAFunction &func, void *context, + bool mode) { + OCSSDContext *pContext = new OCSSDContext(); + std::vector chunks; + bool err = false; + uint64_t idx = 1; + + pContext->req = Request(func, context); + pContext->beginAt = + getTick() + applyLatency(CPU::NVME__OCSSD, CPU::CONVERT_UNIT); + + convertUnit(lbaList, pContext->list, chunks, false, mode); + + // Update ChunkDescriptor + for (auto &iter : chunks) { + // Check block status + if (iter.pDesc->chunkState == OFFLINE) { + err = true; + warn("Writing to dead chunk"); + } + else if (iter.pDesc->chunkState == CLOSED) { + err = true; + warn("Writing to closed chunk"); + } + // Check write pointer + else if (iter.pDesc->chunkState == OPEN && + iter.pDesc->writePointer / structure.writeSize > iter.pageIdx) { + err = true; + warn("Write pointer violation"); + } + + if (err) { + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + 0xF2); // Out of order write + } + else { + // Update write pointer + iter.pDesc->writePointer = (iter.pageIdx + 1) * structure.writeSize; + iter.pDesc->chunkState = OPEN; + + // Do we need to close this chunk? + if (iter.pageIdx == param.page - 1) { + iter.pDesc->chunkState = CLOSED; + } + } + + if (err) { + if (idx <= 0xFFFFFFFF) { + ((IOContext *)context)->resp.entry.dword0 |= idx; + } + else { + ((IOContext *)context)->resp.entry.reserved |= (idx >> 32); + } + } + + idx <<= 1; + } + + if (!err) { + ((IOContext *)context)->resp.entry.dword0 = 0xFFFFFFFF; + ((IOContext *)context)->resp.entry.reserved = 0xFFFFFFFF; + } + else { + // Remove invalid LBAs + uint64_t mask = ((IOContext *)context)->resp.entry.reserved; + idx = 1; + + mask <<= 32; + mask |= ((IOContext *)context)->resp.entry.dword0; + + for (auto iter = pContext->list.begin(); iter != pContext->list.end();) { + if (mask & idx) { + iter = pContext->list.erase(iter); + } + else { + iter++; + } + + idx <<= 1; + } + } + + DMAFunction doWrite = [this](uint64_t tick, void *context) { + auto pContext = (OCSSDContext *)context; + + tick = MAX(tick, pContext->beginAt); + + uint64_t beginAt; + uint64_t finishedAt = tick; + + for (auto &iter : pContext->list) { + beginAt = pContext->beginAt; + + pPALOLD->write(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + pContext->req.finishedAt = finishedAt; + completionQueue.push(pContext->req); + + updateCompletion(); + + delete pContext; + }; + + execute(CPU::NVME__OCSSD, CPU::WRITE_INTERNAL, doWrite, pContext); +} + +void OpenChannelSSD20::eraseInternal(std::vector &lbaList, + DMAFunction &func, void *context, + bool mode) { + OCSSDContext *pContext = new OCSSDContext(); + std::vector chunks; + bool err = false; + uint64_t idx = 1; + + pContext->req = Request(func, context); + pContext->beginAt = + getTick() + applyLatency(CPU::NVME__OCSSD, CPU::CONVERT_UNIT); + + convertUnit(lbaList, pContext->list, chunks, true, mode); + + ((IOContext *)context)->resp.entry.dword0 = 0; + ((IOContext *)context)->resp.entry.reserved = 0; + + // Update ChunkDescriptor + for (auto &iter : chunks) { + // Check block status + if (iter.pDesc->chunkState == OFFLINE) { + err = true; + warn("Erasing dead chunk"); + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + 0xC0); // Offline chunk + } + else if (iter.pDesc->chunkState == FREE || iter.pDesc->chunkState == OPEN) { + err = true; + warn("Erasing free or open chunk"); + + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + 0xC1); // Invalid reset + } + else { + // Update + iter.pDesc->writePointer = 0; + iter.pDesc->chunkState = FREE; + } + + if (err) { + if (idx <= 0xFFFFFFFF) { + ((IOContext *)context)->resp.entry.dword0 |= idx; + } + else { + ((IOContext *)context)->resp.entry.reserved |= (idx >> 32); + } + } + + idx <<= 1; + } + + if (!err) { + ((IOContext *)context)->resp.entry.dword0 = 0xFFFFFFFF; + ((IOContext *)context)->resp.entry.reserved = 0xFFFFFFFF; + } + else { + // Remove invalid LBAs + uint64_t mask = ((IOContext *)context)->resp.entry.reserved; + idx = 1; + + mask <<= 32; + mask |= ((IOContext *)context)->resp.entry.dword0; + + for (auto iter = pContext->list.begin(); iter != pContext->list.end();) { + if (mask & idx) { + iter = pContext->list.erase(iter); + } + else { + iter++; + } + + idx <<= 1; + } + } + + DMAFunction doErase = [this](uint64_t tick, void *context) { + auto pContext = (OCSSDContext *)context; + + tick = MAX(tick, pContext->beginAt); + + uint64_t beginAt; + uint64_t finishedAt = tick; + + for (auto &iter : pContext->list) { + beginAt = pContext->beginAt; + + pPALOLD->erase(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + pContext->req.finishedAt = finishedAt; + completionQueue.push(pContext->req); + + updateCompletion(); + + delete pContext; + }; + + execute(CPU::NVME__OCSSD, CPU::ERASE_INTERNAL, doErase, pContext); +} + +bool OpenChannelSSD20::getLogPage(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t numdl = (req.entry.dword10 & 0xFFFF0000) >> 16; + uint16_t lid = req.entry.dword10 & 0xFFFF; + uint16_t numdu = req.entry.dword11 & 0xFFFF; + uint32_t lopl = req.entry.dword12; + uint32_t lopu = req.entry.dword13; + bool ret = false; + bool submit = true; + + uint32_t req_size = (((uint32_t)numdu << 16 | numdl) + 1) * 4; + uint64_t offset = ((uint64_t)lopu << 32) | lopl; + + debugprint(LOG_HIL_NVME, + "ADMIN | Get Log Page | Log %d | Size %d | NSID %d", lid, + req_size, req.entry.namespaceID); + + static DMAFunction dmaDone = [](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + DMAFunction smartInfo = [offset](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->dma->write(offset, pContext->nlb, pContext->buffer, dmaDone, + context); + }; + + switch (lid) { + case LOG_ERROR_INFORMATION: + case LOG_SMART_HEALTH_INFORMATION: + case LOG_FIRMWARE_SLOT_INFORMATION: + ret = true; + break; + case LOG_CHUNK_INFORMATION: { + ret = true; + submit = false; + IOContext *pContext = new IOContext(func, resp); + + // Fill data + pContext->buffer = (uint8_t *)pDescriptor; + pContext->nlb = req_size; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2, (uint64_t)req_size); + } + } break; + default: + ret = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_LOG_PAGE); + break; + } + + if (submit) { + func(resp); + } + + return ret; +} + +bool OpenChannelSSD20::geometry(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + + RequestContext *pContext = new RequestContext(func, resp); + + pContext->buffer = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + debugprint(LOG_HIL_NVME, "OCSSD | Geometry"); + + // Fill Geometry Information + pContext->buffer[0x00] = 2; // OpenChannel SSD Spec Rev. 2.0 + pContext->buffer[0x01] = 0; + pContext->buffer[0x08] = popcount(ppaMask.channelMask); + pContext->buffer[0x09] = popcount(ppaMask.wayMask); + pContext->buffer[0x0A] = popcount(ppaMask.blockMask); + pContext->buffer[0x0B] = popcount(ppaMask.sectorMask); + pContext->buffer[0x20] = 0x7F; + + // Geometry Related + *(uint16_t *)(pContext->buffer + 0x40) = structure.group; + *(uint16_t *)(pContext->buffer + 0x42) = structure.parallelUnit; + *(uint32_t *)(pContext->buffer + 0x44) = structure.chunk; + *(uint32_t *)(pContext->buffer + 0x48) = structure.chunkSize; + + // Write Data Requrements + *(uint32_t *)(pContext->buffer + 0x80) = structure.writeSize; + *(uint32_t *)(pContext->buffer + 0x84) = structure.writeSize; + + // Performance Related Metrics + PAL::Config::NANDTiming *pNANDTiming = conf.getNANDTiming(); + + *(uint32_t *)(pContext->buffer + 0xC0) = pNANDTiming->msb.read / 1000; + *(uint32_t *)(pContext->buffer + 0xC8) = pNANDTiming->msb.write / 1000; + + if (conf.readInt(CONFIG_PAL, PAL::NAND_FLASH_TYPE) != PAL::NAND_SLC) { + *(uint32_t *)(pContext->buffer + 0xC4) = pNANDTiming->lsb.read / 1000; + *(uint32_t *)(pContext->buffer + 0xCC) = pNANDTiming->lsb.write / 1000; + } + else { + *(uint32_t *)(pContext->buffer + 0xC4) = pNANDTiming->msb.read / 1000; + *(uint32_t *)(pContext->buffer + 0xCC) = pNANDTiming->msb.write / 1000; + } + + *(uint32_t *)(pContext->buffer + 0xD0) = pNANDTiming->erase / 1000; + *(uint32_t *)(pContext->buffer + 0xD4) = pNANDTiming->erase / 1000; + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + static DMAFunction doWrite = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + + return true; +} + +void OpenChannelSSD20::read(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + // bool fua = req.entry.dword12 & 0x40000000; + + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to read 0 blocks"); + } + + readCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | READ | %" PRIX64 " + %d", slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction doWrite = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | READ | %" PRIX64 " + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + if (pContext->buffer) { + free(pContext->buffer); + } + + delete pContext->dma; + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | READ | %" PRIX64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + pContext->buffer = (uint8_t *)calloc(pContext->nlb, LBA_SIZE); + + pDisk->read(pContext->slba, pContext->nlb, pContext->buffer); + pContext->dma->write(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + IOContext *pContext = (IOContext *)context; + std::vector input = {pContext->slba, pContext->nlb}; + + readInternal(input, doWrite, pContext); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__OCSSD, CPU::READ); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * LBA_SIZE); + } + } + else { + func(resp); + } +} + +void OpenChannelSSD20::write(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to write 0 blocks"); + } + + writeCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | WRITE | %" PRIX64 " + %d", slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | WRITE | %" PRIX64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->tick = tick; + + if (pContext->buffer) { + pDisk->write(pContext->slba, pContext->nlb, pContext->buffer); + + free(pContext->buffer); + } + + debugprint(LOG_HIL_NVME, + "OCSSD | WRITE | %" PRIX64 " + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + delete pContext->dma; + + std::vector input = {pContext->slba, pContext->nlb}; + + writeInternal(input, doWrite, context); + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = (uint8_t *)calloc(pContext->nlb, LBA_SIZE); + pContext->dma->read(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__OCSSD, CPU::WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nlb * LBA_SIZE); + } + } + else { + func(resp); + } +} + +void OpenChannelSSD20::datasetManagement(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + int nr = (req.entry.dword10 & 0xFF) + 1; + bool ad = req.entry.dword11 & 0x04; + + if (!ad) { + err = true; + // Just ignore + } + + eraseCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | TRIM | %d ranges | Attr %1X", nr, + req.entry.dword11 & 0x0F); + + if (!err) { + static DMAFunction eachTrimDone = [](uint64_t tick, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(tick, pContext->context); + } + + delete pContext; + }; + DMAFunction doTrim = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t, void *context) { + DMAFunction trimDone = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "NVM | ERASE | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + pContext->beginAt, tick, tick - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + DatasetManagementRange range; + IOContext *pContext = (IOContext *)context; + DMAContext *pDMA = new DMAContext(trimDone); + + pDMA->context = context; + + for (uint64_t i = 0; i < pContext->slba; i++) { + memcpy(range.data, + pContext->buffer + i * sizeof(DatasetManagementRange), + sizeof(DatasetManagementRange)); + + pDMA->counter++; + + pDisk->erase(range.slba, range.nlb); + + std::vector input = {range.slba, range.nlb}; + + eraseInternal(input, eachTrimDone, pDMA); + } + + free(pContext->buffer); + delete pContext->dma; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = + (uint8_t *)calloc(pContext->slba, sizeof(DatasetManagementRange)); + + pContext->dma->read(0, pContext->slba * sizeof(DatasetManagementRange), + pContext->buffer, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = nr; + + CPUContext *pCPU = new CPUContext(doTrim, pContext, CPU::NVME__OCSSD, + CPU::DATASET_MANAGEMENT); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nr * 0x10); + } + } + else { + func(resp); + } +} + +void OpenChannelSSD20::vectorChunkRead(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + VectorContext *pContext = new VectorContext(func, resp); + + pContext->slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + pContext->nlb = (req.entry.dword12 & 0x0000003F) + 1; + pContext->beginAt = getTick(); + + vectorReadCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Vector Chunk Read | %d lbas", + pContext->nlb); + + DMAFunction doDMA = [this](uint64_t, void *context) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction eachRead = [this](uint64_t, void *context) { + DMAFunction dmaDone = [](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + + // Done + debugprint(LOG_HIL_NVME, + "OCSSD | Vector Chunk Read | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + // Do Read + uint64_t size = (pContext->nlb + 1) * LBA_SIZE; + pContext->buffer = (uint8_t *)calloc(size, 1); + + for (uint64_t i = 0; i < pContext->nlb; i++) { + uint64_t lba = pContext->lbaList.at(i); + + pDisk->read(lba, 1, pContext->buffer + i * LBA_SIZE); + } + + pContext->dma->write(0, size, pContext->buffer, dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + std::vector<::CPDPBP> list; + + // Collect LBA List + if (pContext->nlb > 1) { + for (uint64_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + else { + pContext->lbaList.push_back(pContext->slba); + } + + // Do Read + readInternal(pContext->lbaList, eachRead, context, true); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + uint64_t size = pContext->nlb * 8; + + pContext->buffer = (uint8_t *)calloc(size, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, size, pContext->buffer, + doRead, pContext); + } + else { + doRead(0, pContext); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::VECTOR_CHUNK_WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * LBA_SIZE); + } +} + +void OpenChannelSSD20::vectorChunkWrite(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + VectorContext *pContext = new VectorContext(func, resp); + + pContext->slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + pContext->nlb = (req.entry.dword12 & 0x0000003F) + 1; + pContext->beginAt = getTick(); + + vectorWriteCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Vector Chunk Write | %d lbas", + pContext->nlb); + + DMAFunction doDMA = [this](uint64_t, void *context) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction eachWrite = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + uint64_t mask = pContext->resp.entry.reserved; + + mask <<= 32; + mask |= pContext->resp.entry.dword0; + + if (pContext->resp.entry.dword3.status == 0) { + mask = 0; + } + + // Write to disk + for (uint64_t i = 0; i < pContext->nlb; i++) { + if ((1 << i) & mask) { + continue; + } + + uint64_t lba = pContext->lbaList.at(i); + + pDisk->write(lba, 1, pContext->buffer + i * LBA_SIZE); + } + + // Done + debugprint(LOG_HIL_NVME, + "OCSSD | Vector Chunk Write | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + // Do Read + uint64_t size = pContext->nlb * LBA_SIZE; + pContext->buffer = (uint8_t *)calloc(size, 1); + pContext->dma->read(0, size, pContext->buffer, dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + std::vector<::CPDPBP> list; + + // Collect LBA List + if (pContext->nlb > 1) { + for (uint64_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + else { + pContext->lbaList.push_back(pContext->slba); + } + + // Do Write + writeInternal(pContext->lbaList, eachWrite, context, true); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + uint64_t size = pContext->nlb * 8; + + pContext->buffer = (uint8_t *)calloc(size, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, size, pContext->buffer, + doRead, pContext); + } + else { + doRead(0, pContext); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::VECTOR_CHUNK_WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * LBA_SIZE); + } +} + +void OpenChannelSSD20::vectorChunkReset(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + IOContext *pContext = new IOContext(func, resp); + + pContext->slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + pContext->nlb = (req.entry.dword12 & 0x0000003F) + 1; + pContext->beginAt = getTick(); + + vectorEraseCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Vector Chunk Reset | %d lbas", + pContext->nlb); + + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction eachErase = [](uint64_t now, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Vector Chunk Reset | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + std::vector lbaList; + std::vector<::CPDPBP> list; + + // Collect LBA List + if (pContext->nlb > 1) { + for (uint64_t i = 0; i < pContext->nlb; i++) { + lbaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + else { + lbaList.push_back(pContext->slba); + } + + // Do Reset + eraseInternal(lbaList, eachErase, context, true); + }; + + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::NVME__OCSSD, + CPU::VECTOR_CHUNK_RESET); + + if (pContext->nlb > 1) { + uint64_t size = pContext->nlb * 8; + + pContext->buffer = (uint8_t *)calloc(size, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, size, pContext->buffer, + cpuHandler, pCPU); + } + else { + doRead(0, pContext); + } +} + +void OpenChannelSSD20::getStatList(std::vector &list, + std::string prefix) { + Stats temp; + + temp.name = prefix + "command_count"; + temp.desc = "Total number of OCSSD command handled"; + list.push_back(temp); + + temp.name = prefix + "erase"; + temp.desc = "Total number of TRIM (Erase) command"; + list.push_back(temp); + + temp.name = prefix + "read"; + temp.desc = "Total number of Read command"; + list.push_back(temp); + + temp.name = prefix + "write"; + temp.desc = "Total number of Write command"; + list.push_back(temp); + + temp.name = prefix + "vector.erase"; + temp.desc = "Total number of Vector Chunk Reset command"; + list.push_back(temp); + + temp.name = prefix + "vector.read"; + temp.desc = "Total number of Vector Chunk Read command"; + list.push_back(temp); + + temp.name = prefix + "vector.write"; + temp.desc = "Total number of Vector Chunk Write command"; + list.push_back(temp); + + pPALOLD->getStatList(list, prefix + "pal."); +} + +void OpenChannelSSD20::getStatValues(std::vector &values) { + values.push_back(commandCount); + values.push_back(eraseCount); + values.push_back(readCount); + values.push_back(writeCount); + values.push_back(vectorEraseCount); + values.push_back(vectorReadCount); + values.push_back(vectorWriteCount); + + pPALOLD->getStatValues(values); +} + +void OpenChannelSSD20::resetStatValues() { + commandCount = 0; + eraseCount = 0; + readCount = 0; + writeCount = 0; + vectorEraseCount = 0; + vectorReadCount = 0; + vectorWriteCount = 0; + + pPALOLD->resetStatValues(); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/ocssd.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/ocssd.hh new file mode 100644 index 0000000000..326c413b8d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/ocssd.hh @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_OCSSD__ +#define __HIL_NVME_OCSSD__ + +#include "hil/nvme/subsystem.hh" +#include "pal/pal.hh" +#include "pal/pal_old.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +#define LBA_SIZE 4096 // Always OCSSD's logical block size is 4K + +typedef struct _BlockData { + uint32_t index; + uint8_t value; + + _BlockData(); + _BlockData(uint32_t, uint8_t); +} BlockData; + +typedef union _ChunkDescriptor { + uint8_t data[32]; + struct { + uint8_t chunkState; + uint8_t chunkType; + uint8_t wearLevelIndex; + uint8_t reserved1; + uint32_t reserved2; + uint64_t slba; + uint64_t nlb; + uint64_t writePointer; + }; +} ChunkDescriptor; + +typedef enum { + FREE = 0x01, //!< Erased (WP = 0) + CLOSED = 0x02, //!< Fulled (WP = max) + OPEN = 0x04, //!< Writing (WP < max) + OFFLINE = 0x08, //!< Dead +} CHUNK_STATE; + +typedef struct _ChunkUpdateEntry { + ChunkDescriptor *pDesc; + uint32_t pageIdx; + + _ChunkUpdateEntry(ChunkDescriptor *, uint32_t); +} ChunkUpdateEntry; + +typedef struct { + uint32_t group; // Channel + uint32_t parallelUnit; // Way + uint32_t chunk; // Blocks + uint32_t chunkSize; // Block Size / LBA_SIZE + uint32_t writeSize; // Page Size / LBA_SIZE +} Geometry; + +typedef struct { + uint64_t padding; + uint64_t channelMask; + uint32_t channelShift; + uint64_t wayMask; + uint32_t wayShift; + uint64_t dieMask; + uint32_t dieShift; + uint64_t planeMask; + uint32_t planeShift; + uint64_t blockMask; + uint32_t blockShift; + uint64_t pageMask; + uint32_t pageShift; + uint64_t sectorMask; +} Mask; + +class VectorContext : public IOContext { + public: + std::vector lbaList; + + VectorContext(RequestFunction &f, CQEntryWrapper &r) : IOContext(f, r) {} +}; + +class OpenChannelSSD12 : public Subsystem { + protected: + PAL::Parameter param; + PAL::PALOLD *pPALOLD; + + Disk *pDisk; + + Geometry structure; + Mask ppaMask; + + uint64_t lastScheduled; + Event completionEvent; + std::priority_queue, Request> completionQueue; + + // Stats + uint64_t eraseCount; + uint64_t readCount; + uint64_t writeCount; + + void updateCompletion(); + void completion(); + + private: + std::unordered_map badBlocks; + + bool parsePPA(uint64_t, ::CPDPBP &); + void convertUnit(::CPDPBP &); + void mergeList(std::vector &, std::vector<::CPDPBP> &, + bool = false); + + // Commands + bool deviceIdentification(SQEntryWrapper &, RequestFunction &); + bool setBadBlockTable(SQEntryWrapper &, RequestFunction &); + bool getBadBlockTable(SQEntryWrapper &, RequestFunction &); + void physicalBlockErase(SQEntryWrapper &, RequestFunction &); + void physicalPageWrite(SQEntryWrapper &, RequestFunction &); + void physicalPageRead(SQEntryWrapper &, RequestFunction &); + + public: + OpenChannelSSD12(Controller *, ConfigData &); + ~OpenChannelSSD12(); + + void init() override; + + void submitCommand(SQEntryWrapper &, RequestFunction) override; + void getNVMCapacity(uint64_t &, uint64_t &) override; + uint32_t validNamespaceCount() override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +class OpenChannelSSD20 : public OpenChannelSSD12 { + private: + ChunkDescriptor *pDescriptor; + uint64_t descriptorLength; + + uint64_t vectorEraseCount; + uint64_t vectorReadCount; + uint64_t vectorWriteCount; + + ChunkDescriptor *getChunkDescriptor(uint32_t, uint32_t, uint32_t); + uint64_t makeLBA(uint32_t, uint32_t, uint32_t, uint32_t); + void parseLBA(uint64_t, uint32_t &, uint32_t &, uint32_t &, uint32_t &); + void convertUnit(std::vector &, std::vector<::CPDPBP> &, + std::vector &, bool = false, bool = false); + void readInternal(std::vector &, DMAFunction &, void *, + bool = false); + void writeInternal(std::vector &, DMAFunction &, void *, + bool = false); + void eraseInternal(std::vector &, DMAFunction &, void *, + bool = false); + + // Commands + bool getLogPage(SQEntryWrapper &, RequestFunction &); + bool geometry(SQEntryWrapper &, RequestFunction &); + void read(SQEntryWrapper &, RequestFunction &); + void write(SQEntryWrapper &, RequestFunction &); + void datasetManagement(SQEntryWrapper &, RequestFunction &); + void vectorChunkRead(SQEntryWrapper &, RequestFunction &); + void vectorChunkWrite(SQEntryWrapper &, RequestFunction &); + void vectorChunkReset(SQEntryWrapper &, RequestFunction &); + + public: + OpenChannelSSD20(Controller *, ConfigData &); + ~OpenChannelSSD20(); + + void init() override; + + void submitCommand(SQEntryWrapper &, RequestFunction) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/queue.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/queue.cc new file mode 100644 index 0000000000..a9287575a7 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/queue.cc @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/queue.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +SQEntry::_SQEntry() { + memset(data, 0, 64); +} + +CQEntry::_CQEntry() { + memset(data, 0, 16); +} + +SQEntryWrapper::_SQEntryWrapper(SQEntry &sqdata, uint16_t sqid, uint16_t cqid, + uint16_t sqhead, uint16_t squid) + : entry(sqdata), + sqID(sqid), + cqID(cqid), + sqHead(sqhead), + sqUID(squid), + useSGL(true) { + if ((sqdata.dword0.fuse >> 6) == 0x00) { + useSGL = false; + } +} + +CQEntryWrapper::_CQEntryWrapper(SQEntryWrapper &sqew) { + cqID = sqew.cqID; + sqUID = sqew.sqUID; + entry.dword2.sqHead = sqew.sqHead; + entry.dword2.sqID = sqew.sqID; + entry.dword3.commandID = sqew.entry.dword0.commandID; +} + +void CQEntryWrapper::makeStatus(bool dnr, bool more, STATUS_CODE_TYPE sct, + int sc) { + entry.dword3.status = 0x0000; + + entry.dword3.status = ((dnr ? 1 : 0) << 15); + entry.dword3.status |= ((more ? 1 : 0) << 14); + entry.dword3.status |= ((sct & 0x07) << 9); + entry.dword3.status |= ((sc & 0xFF) << 1); +} + +Queue::Queue(uint16_t qid, uint16_t length) + : id(qid), head(0), tail(0), size(length), stride(0), base(nullptr) {} + +Queue::~Queue() { + if (base) { + delete base; + } +} + +uint16_t Queue::getID() { + return id; +} + +uint16_t Queue::getItemCount() { + if (tail >= head) { + return tail - head; + } + else { + return (size - head) + tail; + } +} + +uint16_t Queue::getHead() { + return head; +} + +uint16_t Queue::getTail() { + return tail; +} + +uint16_t Queue::getSize() { + return size; +} + +void Queue::setBase(DMAInterface *p, uint64_t s) { + base = p; + stride = s; +} + +CQueue::CQueue(uint16_t iv, bool en, uint16_t qid, uint16_t size) + : Queue(qid, size), ien(en), phase(true), interruptVector(iv) {} + +void CQueue::setData(CQEntry *entry, DMAFunction func, void *context) { + if (entry) { + // Set phase + entry->dword3.status &= 0xFFFE; + entry->dword3.status |= (phase ? 0x0001 : 0x0000); + + // Write entry + base->write(tail * stride, 0x10, entry->data, func, context); + + // Increase tail + tail++; + + if (tail == size) { + tail = 0; + phase = !phase; + } + + if (head == tail) { + panic("Completion queue overflow"); + } + } +} + +uint16_t CQueue::incHead() { + head++; + + if (head == size) { + head = 0; + } + + return head; +} + +void CQueue::setHead(uint16_t newHead) { + head = newHead; +} + +bool CQueue::interruptEnabled() { + return ien; +} + +uint16_t CQueue::getInterruptVector() { + return interruptVector; +} + +SQueue::SQueue(uint16_t cqid, uint8_t pri, uint16_t qid, uint16_t size) + : Queue(qid, size), cqID(cqid), priority(pri) {} + +uint16_t SQueue::getCQID() { + return cqID; +} + +void SQueue::setTail(uint16_t newTail) { + tail = newTail; +} + +void SQueue::getData(SQEntry *entry, DMAFunction func, void *context) { + if (entry && head != tail) { + // Read entry + base->read(head * stride, 0x40, entry->data, func, context); + + // Increase head + head++; + + if (head == size) { + head = 0; + } + } +} + +uint8_t SQueue::getPriority() { + return priority; +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/queue.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/queue.hh new file mode 100644 index 0000000000..5846f292f4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/queue.hh @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_QUEUE__ +#define __HIL_NVME_QUEUE__ + +#include "hil/nvme/def.hh" +#include "hil/nvme/dma.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +typedef union _SQEntry { + uint8_t data[64]; + struct { + struct { + uint8_t opcode; + uint8_t fuse; + uint16_t commandID; + } dword0; + uint32_t namespaceID; + uint32_t reserved1; + uint32_t reserved2; + uint64_t metadata; + uint64_t data1; + uint64_t data2; + uint32_t dword10; + uint32_t dword11; + uint32_t dword12; + uint32_t dword13; + uint32_t dword14; + uint32_t dword15; + }; + + _SQEntry(); +} SQEntry; + +typedef union _CQEntry { + uint8_t data[16]; + struct { + uint32_t dword0; + uint32_t reserved; + struct { + uint16_t sqHead; + uint16_t sqID; + } dword2; + struct { + uint16_t commandID; + uint16_t status; + } dword3; + }; + + _CQEntry(); +} CQEntry; + +typedef struct _SQEntryWrapper { + SQEntry entry; + + uint16_t sqID; + uint16_t cqID; + uint16_t sqHead; + uint16_t sqUID; //!< HEAD - 1 + + bool useSGL; + + _SQEntryWrapper(SQEntry &, uint16_t, uint16_t, uint16_t, uint16_t); +} SQEntryWrapper; + +typedef struct _CQEntryWrapper { + CQEntry entry; + + uint64_t submitAt; + + uint16_t cqID; //!< sqID at entry.dword2 + uint16_t sqUID; //!< Head - 1 + + _CQEntryWrapper(SQEntryWrapper &); + void makeStatus(bool, bool, STATUS_CODE_TYPE, int); +} CQEntryWrapper; + +class Queue { + protected: + uint16_t id; + + uint16_t head; + uint16_t tail; + + uint16_t size; + uint64_t stride; + + DMAInterface *base; + + public: + Queue(uint16_t, uint16_t); + ~Queue(); + + uint16_t getID(); + uint16_t getItemCount(); + uint16_t getHead(); + uint16_t getTail(); + uint16_t getSize(); + void setBase(DMAInterface *, uint64_t); +}; + +class CQueue : public Queue { + protected: + bool ien; + bool phase; + uint16_t interruptVector; + + public: + CQueue(uint16_t, bool, uint16_t, uint16_t); + + void setData(CQEntry *, DMAFunction, void *); + uint16_t incHead(); + void setHead(uint16_t); + bool interruptEnabled(); + uint16_t getInterruptVector(); +}; + +class SQueue : public Queue { + protected: + uint16_t cqID; + uint8_t priority; + + public: + SQueue(uint16_t, uint8_t, uint16_t, uint16_t); + + uint16_t getCQID(); + void setTail(uint16_t); + void getData(SQEntry *, DMAFunction, void *); + uint8_t getPriority(); +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/subsystem.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/subsystem.cc new file mode 100644 index 0000000000..ae7cace698 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/subsystem.cc @@ -0,0 +1,1320 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/subsystem.hh" + +#include +#include + +#include "hil/nvme/controller.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +const uint32_t nLBAFormat = 4; +const uint32_t lbaFormat[nLBAFormat] = { + 0x02090000, // 512B + 0, Good performance + 0x020A0000, // 1KB + 0, Good performance + 0x010B0000, // 2KB + 0, Better performance + 0x000C0000, // 4KB + 0, Best performance +}; +const uint32_t lbaSize[nLBAFormat] = { + 512, // 512B + 1024, // 1KB + 2048, // 2KB + 4096, // 4KB +}; + +Subsystem::Subsystem(Controller *ctrl, ConfigData &cfg) + : AbstractSubsystem(ctrl, cfg), + pHIL(nullptr), + allocatedLogicalPages(0), + commandCount(0) {} + +Subsystem::~Subsystem() { + for (auto &iter : lNamespaces) { + delete iter; + } + + delete pHIL; +} + +void Subsystem::init() { + pHIL = new HIL(conf); + uint16_t nNamespaces = + (uint16_t)conf.readUint(CONFIG_NVME, NVME_ENABLE_DEFAULT_NAMESPACE); + + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + if (nNamespaces > 0) { + Namespace::Information info; + uint64_t totalSize; + uint32_t lba = (uint32_t)conf.readUint(CONFIG_NVME, NVME_LBA_SIZE); + + for (info.lbaFormatIndex = 0; info.lbaFormatIndex < nLBAFormat; + info.lbaFormatIndex++) { + if (lbaSize[info.lbaFormatIndex] == lba) { + info.lbaSize = lbaSize[info.lbaFormatIndex]; + + break; + } + } + + if (info.lbaFormatIndex == nLBAFormat) { + panic("Failed to setting LBA size (512B ~ 4KB)"); + } + + // Fill Namespace information + totalSize = totalLogicalPages * logicalPageSize / lba; + info.dataProtectionSettings = 0x00; + info.namespaceSharingCapabilities = 0x00; + + for (uint16_t i = 0; i < nNamespaces; i++) { + info.size = totalSize / nNamespaces; + info.capacity = info.size; + + if (createNamespace(NSID_LOWEST + i, &info)) { + lNamespaces.back()->attach(true); + } + else { + panic("Failed to create namespace"); + } + } + } +} + +void Subsystem::convertUnit(Namespace *ns, uint64_t slba, uint64_t nlblk, + Request &req) { + Namespace::Information *info = ns->getInfo(); + uint32_t lbaratio = logicalPageSize / info->lbaSize; + uint64_t slpn; + uint64_t nlp; + uint64_t off; + + if (lbaratio == 0) { + lbaratio = info->lbaSize / logicalPageSize; + + slpn = slba * lbaratio; + nlp = nlblk * lbaratio; + + req.range.slpn = slpn + info->range.slpn; + req.range.nlp = nlp; + req.offset = 0; + req.length = nlblk * info->lbaSize; + } + else { + slpn = slba / lbaratio; + off = slba % lbaratio; + nlp = (nlblk + off + lbaratio - 1) / lbaratio; + + req.range.slpn = slpn + info->range.slpn; + req.range.nlp = nlp; + req.offset = off * info->lbaSize; + req.length = nlblk * info->lbaSize; + } +} + +bool Subsystem::createNamespace(uint32_t nsid, Namespace::Information *info) { + std::list allocated; + std::list unallocated; + + // Allocate LPN + uint64_t requestedLogicalPages = + info->size / logicalPageSize * lbaSize[info->lbaFormatIndex]; + uint64_t unallocatedLogicalPages = totalLogicalPages - allocatedLogicalPages; + + if (requestedLogicalPages > unallocatedLogicalPages) { + return false; + } + + // Collect allocated slots + for (auto &iter : lNamespaces) { + allocated.push_back(iter->getInfo()->range); + } + + // Sort + allocated.sort([](const LPNRange &a, const LPNRange &b) -> bool { + return a.slpn < b.slpn; + }); + + // Merge + auto iter = allocated.begin(); + + if (iter != allocated.end()) { + auto next = iter; + + while (true) { + next++; + + if (iter != allocated.end() || next == allocated.end()) { + break; + } + + if (iter->slpn + iter->nlp == next->slpn) { + iter = allocated.erase(iter); + next = iter; + } + else { + iter++; + } + } + } + + // Invert + unallocated.push_back(LPNRange(0, totalLogicalPages)); + + for (auto &iter : allocated) { + // Split last item + auto &last = unallocated.back(); + + if (last.slpn <= iter.slpn && + last.slpn + last.nlp >= iter.slpn + iter.nlp) { + unallocated.push_back(LPNRange( + iter.slpn + iter.nlp, last.slpn + last.nlp - iter.slpn - iter.nlp)); + last.nlp = iter.slpn - last.slpn; + } + else { + panic("BUG"); + } + } + + // Allocated unallocated area to namespace + for (auto iter = unallocated.begin(); iter != unallocated.end(); iter++) { + if (iter->nlp >= requestedLogicalPages) { + info->range = *iter; + info->range.nlp = requestedLogicalPages; + + break; + } + } + + if (info->range.nlp == 0) { + return false; + } + + allocatedLogicalPages += requestedLogicalPages; + + // Fill Information + info->sizeInByteL = requestedLogicalPages * logicalPageSize; + info->sizeInByteH = 0; + + // Create namespace + Namespace *pNS = new Namespace(this, cfgdata); + pNS->setData(nsid, info); + + lNamespaces.push_back(pNS); + debugprint(LOG_HIL_NVME, + "NS %-5d| CREATE | LBA size %" PRIu32 " | Capacity %" PRIu64, nsid, + info->lbaSize, info->size); + + lNamespaces.sort([](Namespace *lhs, Namespace *rhs) -> bool { + return lhs->getNSID() < rhs->getNSID(); + }); + + return true; +} + +bool Subsystem::destroyNamespace(uint32_t nsid) { + bool found = false; + Namespace::Information *info; + + for (auto iter = lNamespaces.begin(); iter != lNamespaces.end(); iter++) { + if ((*iter)->getNSID() == nsid) { + found = true; + + debugprint(LOG_HIL_NVME, "NS %-5d| DELETE", nsid); + + info = (*iter)->getInfo(); + allocatedLogicalPages -= info->size * info->lbaSize / logicalPageSize; + + delete *iter; + + lNamespaces.erase(iter); + + break; + } + } + + return found; +} + +void Subsystem::fillIdentifyNamespace(uint8_t *buffer, + Namespace::Information *info) { + // Namespace Size + memcpy(buffer + 0, &info->size, 8); + + // Namespace Capacity + memcpy(buffer + 8, &info->capacity, 8); + + // Namespace Utilization + // This function also called from OpenChannelSSD subsystem + if (pHIL) { + info->utilization = + pHIL->getUsedPageCount(info->range.slpn, + info->range.slpn + info->range.nlp) * + logicalPageSize / info->lbaSize; + } + + memcpy(buffer + 16, &info->utilization, 8); + + // Namespace Features + // [Bits ] Description + // [07:05] Reserved + // [04:04] NVM Set capabilities + // [03:03] Reuse of NGUID field + // [02:02] 1 for Support Deallocated or Unwritten Logical Block error + // [01:01] 1 for NAWUN, NAWUPF, NACWU are defined + // [00:00] 1 for Support Thin Provisioning + buffer[24] = 0x04; // Trim supported + + // Number of LBA Formats + buffer[25] = nLBAFormat - 1; // 0's based + + // Formatted LBA Size + buffer[26] = info->lbaFormatIndex; + + // End-to-end Data Protection Capabilities + buffer[28] = info->dataProtectionSettings; + + // Namespace Multi-path I/O and Namespace Sharing Capabilities + buffer[30] = info->namespaceSharingCapabilities; + + // NVM capacity + memcpy(buffer + 48, &info->sizeInByteL, 8); + memcpy(buffer + 56, &info->sizeInByteH, 8); + + // LBA Formats + for (uint32_t i = 0; i < nLBAFormat; i++) { + memcpy(buffer + 128 + i * 4, lbaFormat + i, 4); + } + + // OpenChannel SSD + if (!pHIL) { + buffer[384] = 0x01; + } +} + +void Subsystem::submitCommand(SQEntryWrapper &req, RequestFunction func) { + struct CommandContext { + SQEntryWrapper req; + RequestFunction func; + + CommandContext(SQEntryWrapper &r, RequestFunction &f) : req(r), func(f) {} + }; + + CQEntryWrapper resp(req); + bool processed = false; + + commandCount++; + + // Admin command + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_DELETE_IO_SQUEUE: + processed = deleteSQueue(req, func); + break; + case OPCODE_CREATE_IO_SQUEUE: + processed = createSQueue(req, func); + break; + case OPCODE_GET_LOG_PAGE: + processed = getLogPage(req, func); + break; + case OPCODE_DELETE_IO_CQUEUE: + processed = deleteCQueue(req, func); + break; + case OPCODE_CREATE_IO_CQUEUE: + processed = createCQueue(req, func); + break; + case OPCODE_IDENTIFY: + processed = identify(req, func); + break; + case OPCODE_ABORT: + processed = abort(req, func); + break; + case OPCODE_SET_FEATURES: + processed = setFeatures(req, func); + break; + case OPCODE_GET_FEATURES: + processed = getFeatures(req, func); + break; + case OPCODE_ASYNC_EVENT_REQ: + break; + case OPCODE_NAMESPACE_MANAGEMENT: + processed = namespaceManagement(req, func); + break; + case OPCODE_NAMESPACE_ATTACHMENT: + processed = namespaceAttachment(req, func); + break; + case OPCODE_FORMAT_NVM: + processed = formatNVM(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + break; + } + } + + // NVM commands or Namespace specific Admin commands + if (!processed) { + if (req.entry.namespaceID < NSID_ALL) { + for (auto &iter : lNamespaces) { + if (iter->getNSID() == req.entry.namespaceID) { + auto pContext = new CommandContext(req, func); + DMAFunction doSubmit = [iter](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + iter->submitCommand(pContext->req, pContext->func); + + delete pContext; + }; + + execute(CPU::NVME__NAMESPACE, CPU::SUBMIT_COMMAND, doSubmit, + pContext); + + return; + } + } + } + else { + if (lNamespaces.size() > 0) { + auto pContext = new CommandContext(req, func); + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + lNamespaces.front()->submitCommand(pContext->req, pContext->func); + + delete pContext; + }; + + execute(CPU::NVME__NAMESPACE, CPU::SUBMIT_COMMAND, doSubmit, pContext); + + processed = true; + } + } + } + + // Invalid namespace + if (!processed) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + + func(resp); + } +} + +void Subsystem::getNVMCapacity(uint64_t &total, uint64_t &used) { + total = totalLogicalPages * logicalPageSize; + used = allocatedLogicalPages * logicalPageSize; +} + +uint32_t Subsystem::validNamespaceCount() { + return (uint32_t)lNamespaces.size(); +} + +void Subsystem::read(Namespace *ns, uint64_t slba, uint64_t nlblk, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doRead = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->read(*req); + + delete req; + }; + + convertUnit(ns, slba, nlblk, *req); + + execute(CPU::NVME__SUBSYSTEM, CPU::CONVERT_UNIT, doRead, req); +} + +void Subsystem::write(Namespace *ns, uint64_t slba, uint64_t nlblk, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doWrite = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->write(*req); + + delete req; + }; + + convertUnit(ns, slba, nlblk, *req); + + execute(CPU::NVME__SUBSYSTEM, CPU::CONVERT_UNIT, doWrite, req); +} + +void Subsystem::flush(Namespace *ns, DMAFunction &func, void *context) { + Request req(func, context); + Namespace::Information *info = ns->getInfo(); + + req.range.slpn = info->range.slpn; + req.range.nlp = info->range.nlp; + req.offset = 0; + req.length = info->range.nlp * logicalPageSize; + + pHIL->flush(req); +} + +void Subsystem::trim(Namespace *ns, uint64_t slba, uint64_t nlblk, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doTrim = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->trim(*req); + + delete req; + }; + + convertUnit(ns, slba, nlblk, *req); + + execute(CPU::NVME__SUBSYSTEM, CPU::CONVERT_UNIT, doTrim, req); +} + +bool Subsystem::deleteSQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t sqid = req.entry.dword10 & 0xFFFF; + + debugprint(LOG_HIL_NVME, "ADMIN | Delete I/O Submission Queue"); + + int ret = pParent->deleteSQueue(sqid); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + + func(resp); + + return true; +} + +bool Subsystem::createSQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + bool err = false; + + uint16_t sqid = req.entry.dword10 & 0xFFFF; + uint16_t entrySize = ((req.entry.dword10 & 0xFFFF0000) >> 16) + 1; + uint16_t cqid = (req.entry.dword11 & 0xFFFF0000) >> 16; + uint8_t priority = (req.entry.dword11 & 0x06) >> 1; + bool pc = req.entry.dword11 & 0x01; + + debugprint(LOG_HIL_NVME, "ADMIN | Create I/O Submission Queue"); + + if (entrySize > cfgdata.maxQueueEntry) { + err = true; + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_SIZE); + } + + if (!err) { + RequestContext *pContext = new RequestContext(func, resp); + static DMAFunction doQueue = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext; + }; + + int ret = pParent->createSQueue(sqid, cqid, entrySize, priority, pc, + req.entry.data1, doQueue, pContext); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + else if (ret == 2) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_COMPLETION_QUEUE); + } + } + else { + func(resp); + } + + return true; +} + +bool Subsystem::getLogPage(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t numdl = (req.entry.dword10 & 0xFFFF0000) >> 16; + uint16_t lid = req.entry.dword10 & 0xFFFF; + uint16_t numdu = req.entry.dword11 & 0xFFFF; + uint32_t lopl = req.entry.dword12; + uint32_t lopu = req.entry.dword13; + bool ret = false; + bool submit = true; + + uint32_t req_size = (((uint32_t)numdu << 16 | numdl) + 1) * 4; + uint64_t offset = ((uint64_t)lopu << 32) | lopl; + + debugprint(LOG_HIL_NVME, + "ADMIN | Get Log Page | Log %d | Size %d | NSID %d", lid, + req_size, req.entry.namespaceID); + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + DMAFunction smartInfo = [offset](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(offset, 512, pContext->buffer, dmaDone, context); + }; + + switch (lid) { + case LOG_ERROR_INFORMATION: + ret = true; + break; + case LOG_SMART_HEALTH_INFORMATION: { + if (req.entry.namespaceID == NSID_ALL) { + ret = true; + submit = false; + RequestContext *pContext = new RequestContext(func, resp); + + pContext->buffer = globalHealth.data; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2, (uint64_t)req_size); + } + } + } break; + case LOG_FIRMWARE_SLOT_INFORMATION: + ret = true; + break; + default: + ret = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_LOG_PAGE); + break; + } + + if (submit) { + func(resp); + } + + return ret; +} + +bool Subsystem::deleteCQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t cqid = req.entry.dword10 & 0xFFFF; + + debugprint(LOG_HIL_NVME, "ADMIN | Delete I/O Completion Queue"); + + int ret = pParent->deleteCQueue(cqid); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + else if (ret == 2) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_DELETE); + } + + func(resp); + + return true; +} + +bool Subsystem::createCQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + bool err = false; + + uint16_t cqid = req.entry.dword10 & 0xFFFF; + uint16_t entrySize = ((req.entry.dword10 & 0xFFFF0000) >> 16) + 1; + uint16_t iv = (req.entry.dword11 & 0xFFFF0000) >> 16; + bool ien = req.entry.dword11 & 0x02; + bool pc = req.entry.dword11 & 0x01; + + debugprint(LOG_HIL_NVME, "ADMIN | Create I/O Completion Queue"); + + if (entrySize > cfgdata.maxQueueEntry) { + err = true; + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_SIZE); + } + + if (!err) { + RequestContext *pContext = new RequestContext(func, resp); + static DMAFunction doQueue = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext; + }; + + int ret = pParent->createCQueue(cqid, entrySize, iv, ien, pc, + req.entry.data1, doQueue, pContext); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + } + else { + func(resp); + } + + return true; +} + +bool Subsystem::identify(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint8_t cns = req.entry.dword10 & 0xFF; + uint16_t cntid = (req.entry.dword10 & 0xFFFF0000) >> 16; + bool ret = true; + + RequestContext *pContext = new RequestContext(func, resp); + uint16_t idx = 0; + + pContext->buffer = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + debugprint(LOG_HIL_NVME, "ADMIN | Identify | CNS %d | CNTID %d | NSID %d", + cns, cntid, req.entry.namespaceID); + + switch (cns) { + case CNS_IDENTIFY_NAMESPACE: + if (req.entry.namespaceID == NSID_ALL) { + // FIXME: Not called by current(4.9.32) NVMe driver + } + else { + for (auto &iter : lNamespaces) { + if (iter->isAttached() && iter->getNSID() == req.entry.namespaceID) { + fillIdentifyNamespace(pContext->buffer, iter->getInfo()); + } + } + } + + break; + case CNS_IDENTIFY_CONTROLLER: + pParent->identify(pContext->buffer); + + break; + case CNS_ACTIVE_NAMESPACE_LIST: + if (req.entry.namespaceID >= NSID_ALL - 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + else { + for (auto &iter : lNamespaces) { + if (iter->isAttached() && iter->getNSID() > req.entry.namespaceID) { + ((uint32_t *)pContext->buffer)[idx++] = iter->getNSID(); + } + } + } + + break; + case CNS_ALLOCATED_NAMESPACE_LIST: + if (req.entry.namespaceID >= NSID_ALL - 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + else { + for (auto &iter : lNamespaces) { + if (iter->getNSID() > req.entry.namespaceID) { + ((uint32_t *)pContext->buffer)[idx++] = iter->getNSID(); + } + } + } + + break; + case CNS_IDENTIFY_ALLOCATED_NAMESPACE: + for (auto &iter : lNamespaces) { + if (iter->getNSID() == req.entry.namespaceID) { + fillIdentifyNamespace(pContext->buffer, iter->getInfo()); + } + } + + break; + case CNS_ATTACHED_CONTROLLER_LIST: + // Only one controller + if (cntid == 0) { + ((uint16_t *)pContext->buffer)[idx++] = 1; + } + + break; + case CNS_CONTROLLER_LIST: + // Only one controller + if (cntid == 0) { + ((uint16_t *)pContext->buffer)[idx++] = 1; + } + + break; + } + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + static DMAFunction doWrite = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + if (ret && !err) { + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + } + else { + func(resp); + free(pContext->buffer); + delete pContext; + } + + return ret; +} + +bool Subsystem::abort(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t sqid = req.entry.dword10 & 0xFFFF; + uint16_t cid = (req.entry.dword10 & 0xFFFF0000) >> 16; + + debugprint(LOG_HIL_NVME, "ADMIN | Abort | SQID %d | CID %d", sqid, cid); + + int ret = pParent->abort(sqid, cid); + + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, STATUS_SUCCESS); + + if (ret == 0) { + resp.entry.dword0 = 1; + } + else { + resp.entry.dword0 = 0; + } + + func(resp); + + return true; +} + +bool Subsystem::setFeatures(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + static uint32_t cqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_CQUEUE); + static uint32_t sqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_SQUEUE); + + CQEntryWrapper resp(req); + uint16_t fid = req.entry.dword10 & 0x00FF; + bool save = req.entry.dword10 & 0x80000000; + + debugprint(LOG_HIL_NVME, "ADMIN | Set Features | Feature %d | NSID %d", fid, + req.entry.namespaceID); + + if (save) { + err = true; + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_FEATURE_ID_NOT_SAVEABLE); + } + + if (!err) { + switch (fid) { + case FEATURE_NUMBER_OF_QUEUES: + if ((req.entry.dword11 & 0xFFFF) == 0xFFFF || + (req.entry.dword11 & 0xFFFF0000) == 0xFFFF0000) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + else { + if ((req.entry.dword11 & 0xFFFF) >= sqsize) { + req.entry.dword11 = (req.entry.dword11 & 0xFFFF0000) | (sqsize - 1); + } + if (((req.entry.dword11 & 0xFFFF0000) >> 16) >= cqsize) { + req.entry.dword11 = + (req.entry.dword11 & 0xFFFF) | ((uint32_t)(cqsize - 1) << 16); + } + + resp.entry.dword0 = req.entry.dword11; + queueAllocated = resp.entry.dword0; + } + + break; + case FEATURE_INTERRUPT_COALESCING: + pParent->setCoalescingParameter((req.entry.dword11 >> 8) & 0xFF, + req.entry.dword11 & 0xFF); + break; + case FEATURE_INTERRUPT_VECTOR_CONFIGURATION: + pParent->setCoalescing(req.entry.dword11 & 0xFFFF, + req.entry.dword11 & 0x10000); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + break; + } + } + + func(resp); + + return true; +} + +bool Subsystem::getFeatures(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t fid = req.entry.dword10 & 0x00FF; + + debugprint(LOG_HIL_NVME, "ADMIN | Get Features | Feature %d | NSID %d", fid, + req.entry.namespaceID); + + switch (fid) { + case FEATURE_ARBITRATION: + resp.entry.dword0 = + ((uint8_t)(conf.readUint(CONFIG_NVME, NVME_WRR_HIGH) * + conf.readUint(CONFIG_NVME, NVME_WRR_MEDIUM) - + 1) + << 24) | + ((conf.readUint(CONFIG_NVME, NVME_WRR_MEDIUM) - 1) << 16) | 0x03; + break; + case FEATURE_VOLATILE_WRITE_CACHE: + resp.entry.dword0 = + conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE) ? 0x01 : 0x00; + break; + case FEATURE_NUMBER_OF_QUEUES: + resp.entry.dword0 = queueAllocated; + break; + case FEATURE_INTERRUPT_COALESCING: + pParent->getCoalescingParameter(resp.entry.data + 1, resp.entry.data); + break; + case FEATURE_INTERRUPT_VECTOR_CONFIGURATION: + resp.entry.dword0 = (req.entry.dword11 & 0xFFFF) | 0; + + if (pParent->getCoalescing(req.entry.dword11 & 0xFFFF)) { + resp.entry.dword0 |= 0x10000; + } + + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + break; + } + + func(resp); + + return true; +} + +bool Subsystem::asyncEventReq(SQEntryWrapper &, RequestFunction &) { + // FIXME: Not implemented + return true; +} + +bool Subsystem::namespaceManagement(SQEntryWrapper &req, + RequestFunction &func) { + struct NamespaceManagementContext : public RequestContext { + uint32_t nsid; + + NamespaceManagementContext(RequestFunction &f, CQEntryWrapper &r) + : RequestContext(f, r), nsid(NSID_NONE) {} + }; + + bool err = false; + + CQEntryWrapper resp(req); + uint8_t sel = req.entry.dword10 & 0x0F; + + debugprint(LOG_HIL_NVME, "ADMIN | Namespace Management | OP %d | NSID %d", + sel, req.entry.namespaceID); + + static DMAFunction dmaDone = [this](uint64_t, void *context) { + Namespace::Information info; + NamespaceManagementContext *pContext = + (NamespaceManagementContext *)context; + + // Copy data + memcpy(&info.size, pContext->buffer + 0, 8); + memcpy(&info.capacity, pContext->buffer + 8, 8); + info.lbaFormatIndex = pContext->buffer[26]; + info.dataProtectionSettings = pContext->buffer[29]; + info.namespaceSharingCapabilities = pContext->buffer[30]; + + if (info.lbaFormatIndex >= nLBAFormat) { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_FORMAT); + } + else if (info.namespaceSharingCapabilities != 0x00) { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + else if (info.dataProtectionSettings != 0x00) { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + info.lbaSize = lbaSize[info.lbaFormatIndex]; + + bool ret = createNamespace(pContext->nsid, &info); + + if (ret) { + pContext->resp.entry.dword0 = pContext->nsid; + } + else { + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_INSUFFICIENT_CAPACITY); + } + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + static DMAFunction doRead = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->read(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + if ((sel == 0x00 && req.entry.namespaceID != NSID_NONE) || sel > 0x01) { + err = true; + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + err = false; + + if (sel == 0x00) { // Create + uint32_t nsid = NSID_LOWEST; + + for (auto &iter : lNamespaces) { + if (iter->getNSID() == nsid) { + nsid++; + } + else { + break; + } + } + + if (nsid == NSID_ALL) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_ID_UNAVAILABLE); + } + else { + // Do not response immediately + err = true; + + NamespaceManagementContext *pContext = + new NamespaceManagementContext(func, resp); + + pContext->buffer = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + pContext->nsid = nsid; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, doRead, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, doRead, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + } + } + else { // Delete + bool found = destroyNamespace(req.entry.namespaceID); + + if (!found) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + } + } + + if (!err) { + func(resp); + } + + return true; +} + +bool Subsystem::namespaceAttachment(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + uint8_t sel = req.entry.dword10 & 0x0F; + uint32_t nsid = req.entry.namespaceID; + + debugprint(LOG_HIL_NVME, "ADMIN | Namespace Attachment | OP %d | NSID %d", + req.entry.dword10 & 0x0F, req.entry.namespaceID); + + static DMAFunction dmaDone = [this](uint64_t, void *context) { + bool err = false; + IOContext *pContext = (IOContext *)context; + uint16_t *ctrlList = (uint16_t *)pContext->buffer; + std::vector list; + + uint8_t sel = (uint8_t)pContext->slba; + uint32_t nsid = (uint32_t)pContext->nlb; + + for (uint16_t i = 1; i <= ctrlList[0]; i++) { + list.push_back(ctrlList[i]); + } + + if (list.size() > 1 && sel == 0x00) { + err = true; + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_IS_PRIVATE); + } + else if (list.size() == 0) { + err = true; + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_CONTROLLER_LIST_INVALID); + } + else if (list.at(0) != 0) { // Controller ID is zero + err = true; + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_CONTROLLER_LIST_INVALID); + } + + if (!err) { + if (sel == 0x00) { // Attach + bool exist = false; + + for (auto &iter : lNamespaces) { + if (iter->getNSID() == nsid) { + exist = true; + + if (iter->isAttached()) { + err = true; + pContext->resp.makeStatus(true, false, + TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_ALREADY_ATTACHED); + } + else { + iter->attach(true); + } + } + } + + if (!exist) { + err = true; + pContext->resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + } + else if (sel == 0x01) { // Detach + for (auto &iter : lNamespaces) { + if (iter->getNSID() == nsid) { + if (iter->isAttached()) { + iter->attach(false); + } + else { + err = true; + pContext->resp.makeStatus(true, false, + TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + } + } + } + else { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + } + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + static DMAFunction doRead = [](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->dma->read(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->buffer = (uint8_t *)calloc(0x1000, 1); + pContext->slba = sel; + pContext->nlb = nsid; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doRead, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doRead, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + + return true; +} + +bool Subsystem::formatNVM(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint8_t ses = (req.entry.dword10 & 0x0E00) >> 9; + bool pil = req.entry.dword10 & 0x0100; + uint8_t pi = (req.entry.dword10 & 0xE0) >> 5; + bool mset = req.entry.dword10 & 0x10; + uint8_t lbaf = req.entry.dword10 & 0x0F; + bool submit = true; + + debugprint(LOG_HIL_NVME, "ADMIN | Format NVM | SES %d | NSID %d", ses, + req.entry.namespaceID); + + static DMAFunction doFormat = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext; + }; + + if (ses != 0x00 && ses != 0x01) { + err = true; + } + if (pil || mset) { + err = true; + } + if (pi != 0x00) { + err = true; + } + if (lbaf >= nLBAFormat) { + err = true; + } + + if (err) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FORMAT); + } + else { + // Update Namespace + auto iter = lNamespaces.begin(); + Namespace::Information *info = nullptr; + + for (; iter != lNamespaces.end(); iter++) { + if ((*iter)->getNSID() == req.entry.namespaceID) { + info = (*iter)->getInfo(); + + break; + } + } + + if (info) { + submit = false; + + info->lbaFormatIndex = lbaf; + info->lbaSize = lbaSize[lbaf]; + info->size = totalLogicalPages * logicalPageSize / info->lbaSize; + info->capacity = info->size; + + // Reset health stat and set format progress + (*iter)->format(getTick()); + + info->utilization = + pHIL->getUsedPageCount(info->range.slpn, + info->range.slpn + info->range.nlp) * + logicalPageSize / info->lbaSize; + + // Send format command to HIL + RequestContext *pContext = new RequestContext(func, resp); + Request *req = new Request(doFormat, pContext); + + req->range = info->range; + + DMAFunction job = [this, ses](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->format(*req, ses == 0x01); + + delete req; + }; + + execute(CPU::NVME__SUBSYSTEM, CPU::FORMAT_NVM, job, req); + } + else { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + } + + if (submit) { + func(resp); + } + + return true; +} + +void Subsystem::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "command_count"; + temp.desc = "Total number of NVMe command handled"; + list.push_back(temp); + + pHIL->getStatList(list, prefix); +} + +void Subsystem::getStatValues(std::vector &values) { + values.push_back(commandCount); + + pHIL->getStatValues(values); +} + +void Subsystem::resetStatValues() { + commandCount = 0; + + pHIL->resetStatValues(); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/subsystem.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/subsystem.hh new file mode 100644 index 0000000000..daf0536144 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/nvme/subsystem.hh @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_SUBSYSTEM__ +#define __HIL_NVME_SUBSYSTEM__ + +#include "hil/hil.hh" +#include "hil/nvme/abstract_subsystem.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Subsystem : public AbstractSubsystem { + protected: + HIL *pHIL; + + std::list lNamespaces; + uint32_t queueAllocated; + + HealthInfo globalHealth; + uint32_t logicalPageSize; + uint64_t totalLogicalPages; + uint64_t allocatedLogicalPages; + + // Stats + uint64_t commandCount; + + void convertUnit(Namespace *, uint64_t, uint64_t, Request &); + bool createNamespace(uint32_t, Namespace::Information *); + bool destroyNamespace(uint32_t); + void fillIdentifyNamespace(uint8_t *, Namespace::Information *); + + // Admin commands + bool deleteSQueue(SQEntryWrapper &, RequestFunction &); + bool createSQueue(SQEntryWrapper &, RequestFunction &); + bool getLogPage(SQEntryWrapper &, RequestFunction &); + bool deleteCQueue(SQEntryWrapper &, RequestFunction &); + bool createCQueue(SQEntryWrapper &, RequestFunction &); + bool identify(SQEntryWrapper &, RequestFunction &); + bool abort(SQEntryWrapper &, RequestFunction &); + bool setFeatures(SQEntryWrapper &, RequestFunction &); + bool getFeatures(SQEntryWrapper &, RequestFunction &); + bool asyncEventReq(SQEntryWrapper &, RequestFunction &); + bool namespaceManagement(SQEntryWrapper &, RequestFunction &); + bool namespaceAttachment(SQEntryWrapper &, RequestFunction &); + bool formatNVM(SQEntryWrapper &, RequestFunction &); + + public: + Subsystem(Controller *, ConfigData &); + ~Subsystem(); + + void init() override; + + void submitCommand(SQEntryWrapper &, RequestFunction) override; + void getNVMCapacity(uint64_t &, uint64_t &) override; + uint32_t validNamespaceCount() override; + + void read(Namespace *, uint64_t, uint64_t, DMAFunction &, void *); + void write(Namespace *, uint64_t, uint64_t, DMAFunction &, void *); + void flush(Namespace *, DMAFunction &, void *); + void trim(Namespace *, uint64_t, uint64_t, DMAFunction &, void *); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/config.cc new file mode 100644 index 0000000000..40f331cb57 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/config.cc @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/sata/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +const char NAME_PCIE_GEN[] = "PCIEGeneration"; +const char NAME_PCIE_LANE[] = "PCIELane"; +const char NAME_AXI_BUS_WIDTH[] = "AXIBusWidth"; +const char NAME_AXI_CLOCK[] = "AXIClock"; +const char NAME_SATA_MODE[] = "SATAMode"; +const char NAME_WORK_INTERVAL[] = "WorkInterval"; +const char NAME_MAX_REQUEST_COUNT[] = "MaxRequestCount"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_ENABLE_DISK_IMAGE[] = "EnableDiskImage"; +const char NAME_STRICT_DISK_SIZE[] = "StrictSizeCheck"; +const char NAME_DISK_IMAGE_PATH[] = "DiskImageFile"; +const char NAME_USE_COW_DISK[] = "UseCopyOnWriteDisk"; + +Config::Config() { + pcieGen = PCIExpress::PCIE_3_X; + pcieLane = 4; + axiWidth = ARM::AXI::BUS_128BIT; + axiClock = 250000000; + sataMode = SimpleSSD::SATA::SATA_3_0; + workInterval = 50000; + maxRequestCount = 4; + lbaSize = 512; + enableDiskImage = false; + strictDiskSize = false; + diskImagePath = ""; + useCopyOnWriteDisk = false; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_PCIE_GEN)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + pcieGen = PCIExpress::PCIE_1_X; + break; + case 1: + pcieGen = PCIExpress::PCIE_2_X; + break; + case 2: + pcieGen = PCIExpress::PCIE_3_X; + break; + default: + panic("Invalid PCI Express Generation"); + break; + } + } + else if (MATCH_NAME(NAME_PCIE_LANE)) { + pcieLane = (uint8_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_AXI_BUS_WIDTH)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + axiWidth = ARM::AXI::BUS_32BIT; + break; + case 1: + axiWidth = ARM::AXI::BUS_64BIT; + break; + case 2: + axiWidth = ARM::AXI::BUS_128BIT; + break; + case 3: + axiWidth = ARM::AXI::BUS_256BIT; + break; + case 4: + axiWidth = ARM::AXI::BUS_512BIT; + break; + case 5: + axiWidth = ARM::AXI::BUS_1024BIT; + break; + default: + panic("Invalid AXI Stream Bus Width"); + break; + } + } + else if (MATCH_NAME(NAME_AXI_CLOCK)) { + axiClock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SATA_MODE)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + sataMode = SimpleSSD::SATA::SATA_1_0; + break; + case 1: + sataMode = SimpleSSD::SATA::SATA_2_0; + break; + case 2: + sataMode = SimpleSSD::SATA::SATA_3_0; + break; + default: + panic("Invalid SATA Generation"); + break; + } + } + else if (MATCH_NAME(NAME_WORK_INTERVAL)) { + workInterval = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_REQUEST_COUNT)) { + maxRequestCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DISK_IMAGE)) { + enableDiskImage = convertBool(value); + } + else if (MATCH_NAME(NAME_STRICT_DISK_SIZE)) { + strictDiskSize = convertBool(value); + } + else if (MATCH_NAME(NAME_DISK_IMAGE_PATH)) { + diskImagePath = value; + } + else if (MATCH_NAME(NAME_USE_COW_DISK)) { + useCopyOnWriteDisk = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (popcount(lbaSize) != 1) { + panic("Invalid LBA size"); + } + if (maxRequestCount == 0) { + panic("MaxRequestCount should be larger then 0"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case SATA_PCIE_GEN: + ret = pcieGen; + break; + case SATA_AXI_BUS_WIDTH: + ret = axiWidth; + break; + case SATA_MODE: + ret = sataMode; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case SATA_PCIE_LANE: + ret = pcieLane; + break; + case SATA_AXI_CLOCK: + ret = axiClock; + break; + case SATA_WORK_INTERVAL: + ret = workInterval; + break; + case SATA_MAX_REQUEST_COUNT: + ret = maxRequestCount; + break; + case SATA_LBA_SIZE: + ret = lbaSize; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret(""); + + switch (idx) { + case SATA_DISK_IMAGE_PATH: + ret = diskImagePath; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case SATA_ENABLE_DISK_IMAGE: + ret = enableDiskImage; + break; + case SATA_STRICT_DISK_SIZE: + ret = strictDiskSize; + break; + case SATA_USE_COW_DISK: + ret = useCopyOnWriteDisk; + break; + } + + return ret; +} + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/config.hh new file mode 100644 index 0000000000..4f6b01f1e1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/config.hh @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_CONFIG__ +#define __HIL_SATA_CONFIG__ + +#include "sim/base_config.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +typedef enum { + SATA_PCIE_GEN, + SATA_PCIE_LANE, + SATA_AXI_BUS_WIDTH, + SATA_AXI_CLOCK, + SATA_MODE, + SATA_WORK_INTERVAL, + SATA_MAX_REQUEST_COUNT, + SATA_LBA_SIZE, + SATA_ENABLE_DISK_IMAGE, + SATA_STRICT_DISK_SIZE, + SATA_DISK_IMAGE_PATH, + SATA_USE_COW_DISK +} SATA_CONFIG; + +class Config : public BaseConfig { + private: + PCIExpress::PCIE_GEN pcieGen; //!< Default: PCIE_3_X + uint8_t pcieLane; //!< Default: 4 + ARM::AXI::BUS_WIDTH axiWidth; //!< Default: BUS_128BIT + uint64_t axiClock; //!< Default: 250000000 (250MHz) + SimpleSSD::SATA::SATA_GEN sataMode; //!< Default SATA_3_0 + uint64_t workInterval; //!< Default: 50000 (50ns) + uint64_t maxRequestCount; //!< Default: 4 + uint64_t lbaSize; //!< Default: 512 + bool enableDiskImage; //!< Default: False + bool strictDiskSize; //!< Default: False + bool useCopyOnWriteDisk; //!< Default: False + std::string diskImagePath; //!< Default: "" + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/def.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/def.hh new file mode 100644 index 0000000000..7d1035e870 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/def.hh @@ -0,0 +1,381 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_DEF__ +#define __HIL_SATA_DEF__ + +#include + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +// AHCI Generic Host Controller Register +typedef union { + uint8_t data[0x100]; + struct { + uint32_t capability; + uint32_t globalHBAControl; + uint32_t interruptStatus; + uint32_t portsImplemented; + uint32_t AHCIVersion; + uint32_t commandCompletionCoalescingControl; + uint32_t commandCompletionCoalescingPorts; + uint32_t enclosureManagementLocation; + uint32_t enclosureManagementControl; + uint32_t HBACapabilityExtended; + uint32_t handoffControlAndStatus; + }; +} AHCIGHCRegister; + +// AHCI Port Register +typedef union { + uint8_t data[0x80]; + struct { + uint64_t commandListBaseAddress; + uint64_t FISBaseAddress; + uint32_t interruptStatus; + uint32_t interruptEnable; + uint32_t commandAndStatus; + uint32_t reserved1; + uint32_t taskFileData; + uint32_t signature; + uint32_t status; + uint32_t control; + uint32_t error; + uint32_t active; + uint32_t commandIssue; + uint32_t notification; + uint32_t switchingControl; + uint32_t deviceSleep; + }; +} AHCIPortRegister; + +// Index of AHCI GHC Register +enum : uint8_t { + REG_CAP = 0x00, + REG_GHC = 0x04, + REG_IS = 0x08, + REG_PI = 0x0C, + REG_VS = 0x10, + REG_CCC_CTL = 0x14, + REG_CCC_PORTS = 0x18, + REG_EM_LOC = 0x1C, + REG_EM_CTL = 0x20, + REG_CAP2 = 0x24, + REG_BOHC = 0x28, +}; + +// Index of AHCI Port Register +enum : uint8_t { + REG_P0CLB = 0x00, + REG_P0CLBU = 0x04, + REG_P0FB = 0x08, + REG_P0FBU = 0x0C, + REG_P0IS = 0x10, + REG_P0IE = 0x14, + REG_P0CMD = 0x18, + REG_P0TFD = 0x20, + REG_P0SIG = 0x24, + REG_P0SSTS = 0x28, + REG_P0SCTL = 0x2C, + REG_P0SERR = 0x30, + REG_P0SACT = 0x34, + REG_P0CI = 0x38, + REG_P0SNTF = 0x3C, + REG_P0FBS = 0x40, + REG_P0DEVSLP = 0x44 +}; + +// Register bits +enum : uint32_t { + // GHC > GHC (Generic HBA Control) + HOST_RESET = (1 << 0), /* reset controller; self-clear */ + HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ + HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ + HOST_AHCI_EN = ((uint32_t)1 << 31), /* AHCI enabled */ + + // GHC > EM_CTL + EM_CTL_RST = (1 << 9), /* Reset */ + EM_CTL_TM = (1 << 8), /* Transmit Message */ + EM_CTL_MR = (1 << 0), /* Message Received */ + EM_CTL_ALHD = (1 << 26), /* Activity LED */ + EM_CTL_XMT = (1 << 25), /* Transmit Only */ + EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ + EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ + EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ + EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ + EM_CTL_LED = (1 << 16), /* LED messages supported */ + + // Port > IS/IE + PORT_IRQ_COLD_PRES = ((uint32_t)1 << 31), /* cold presence detect */ + PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ + PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ + PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ + PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ + PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ + PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ + PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ + + PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ + PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ + PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ + PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ + PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ + PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ + PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ + PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ + PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ + + // Port > CMD + PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ + PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ + PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ + PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ + PORT_CMD_ESP = (1 << 21), /* External Sata Port */ + PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ + PORT_CMD_PMP = (1 << 17), /* PMP attached */ + PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ + PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ + PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ + PORT_CMD_CLO = (1 << 3), /* Command list override */ + PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ + PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ + PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ + + // ATA Status + ATA_BUSY = (1 << 7), /* BSY status bit */ + ATA_DRDY = (1 << 6), /* device ready */ + ATA_DF = (1 << 5), /* device fault */ + ATA_DSC = (1 << 4), /* drive seek complete */ + ATA_DRQ = (1 << 3), /* data request i/o */ + ATA_CORR = (1 << 2), /* corrected data error */ + ATA_SENSE = (1 << 1), /* sense code available */ + ATA_ERR = (1 << 0), /* have an error */ + + // ATA Error + ATA_ICRC = (1 << 7), /* interface CRC error */ + ATA_BBK = ATA_ICRC, /* pre-EIDE: block marked bad */ + ATA_UNC = (1 << 6), /* uncorrectable media error */ + ATA_MC = (1 << 5), /* media changed */ + ATA_IDNF = (1 << 4), /* ID not found */ + ATA_MCR = (1 << 3), /* media change requested */ + ATA_ABORTED = (1 << 2), /* command aborted */ + ATA_TRK0NF = (1 << 1), /* track 0 not found */ + ATA_AMNF = (1 << 0), /* address mark not found */ +}; + +typedef union { + uint8_t data[32]; + struct { + uint16_t flags; + uint16_t prdtLength; + uint32_t prdByteCount; + uint64_t commandTableBaseAddress; + uint32_t reserved[4]; + }; +} CommandHeader; + +typedef union { + uint8_t data[16]; + struct { + uint64_t dataBaseAddress; + uint32_t reserved; + uint32_t dw3; + }; +} PRDT; + +// FIS Type +typedef enum : uint8_t { + FIS_TYPE_REG_H2D = 0x27, + FIS_TYPE_REG_D2H = 0x34, + FIS_TYPE_DMA_ACT = 0x39, + FIS_TYPE_DMA_SETUP = 0x41, + FIS_TYPE_DATA = 0x46, + FIS_TYPE_BIST = 0x58, + FIS_TYPE_PIO_SETUP = 0x5F, + FIS_TYPE_DEV_BITS = 0xA1, +} FIS_TYPE; + +// Register - H2D +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t command; + uint8_t featureL; + uint8_t lbaL[3]; + uint8_t device; + uint8_t lbaH[3]; + uint8_t featureH; + uint8_t countL; + uint8_t countH; + uint8_t icc; + uint8_t control; +} RegisterH2D; + +// Register - D2H +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t status; + uint8_t error; + uint8_t lbaL[3]; + uint8_t device; + uint8_t lbaH[3]; + uint8_t reserved; + uint8_t countL; + uint8_t countH; +} RegisterD2H; + +// Set Device Bits +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t status; + uint8_t command; + uint32_t payload; +} SetDeviceBits; + +// DMA Activate +typedef struct { + uint8_t type; + uint8_t flag; +} DMAActivate; + +// DMA Setup +typedef struct { + uint8_t type; + uint8_t flag; + uint16_t reserved1; + uint32_t reserved2[3]; + uint32_t bufferOffset; + uint32_t transferCount; +} DMASetup; + +// PIO Setup +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t status; + uint8_t error; + uint8_t lbaL[3]; + uint8_t device; + uint8_t lbaH[3]; + uint8_t reserved1; + uint8_t countL; + uint8_t countH; + uint8_t reserved2; + uint8_t e_status; + uint16_t transferCount; +} PIOSetup; + +// FIS +typedef union { + uint8_t data[64]; + union { + RegisterH2D regH2D; + RegisterD2H regD2H; + SetDeviceBits sdb; + DMAActivate dmaAct; + DMASetup dmaSetup; + PIOSetup pioSetup; + }; +} FIS; + +// ACS-2 IDENTIFY DEVICE +enum { + ATA_ID_CONFIG = 0, + ATA_ID_SERNO = 10, + ATA_ID_FW_REV = 23, + ATA_ID_PROD = 27, + ATA_ID_MAX_MULTSECT = 47, + ATA_ID_DWORD_IO = 48, + ATA_ID_CAPABILITY = 49, + ATA_ID_FIELD_VALID = 53, + ATA_ID_MULTSECT = 59, + ATA_ID_LBA_CAPACITY = 60, + ATA_ID_MWDMA_MODES = 63, + ATA_ID_PIO_MODES = 64, + ATA_ID_EIDE_DMA_MIN = 65, + ATA_ID_EIDE_DMA_TIME = 66, + ATA_ID_EIDE_PIO = 67, + ATA_ID_EIDE_PIO_IORDY = 68, + ATA_ID_QUEUE_DEPTH = 75, + ATA_ID_SATA_CAPABILITY = 76, + ATA_ID_SATA_CAPABILITY_2 = 77, + ATA_ID_FEATURE_SUPP = 78, + ATA_ID_MAJOR_VER = 80, + ATA_ID_COMMAND_SET_1 = 82, + ATA_ID_COMMAND_SET_2 = 83, + ATA_ID_CFSSE = 84, + ATA_ID_CFS_ENABLE_1 = 85, + ATA_ID_CFS_ENABLE_2 = 86, + ATA_ID_CSF_DEFAULT = 87, + ATA_ID_UDMA_MODES = 88, + ATA_ID_HW_CONFIG = 93, + ATA_ID_SPG = 98, + ATA_ID_LBA_CAPACITY_2 = 100, + ATA_ID_SECTOR_SIZE = 106, + ATA_ID_WWN = 108, + ATA_ID_LOGICAL_SECTOR_SIZE = 117, /* and 118 */ + ATA_ID_COMMAND_SET_3 = 119, + ATA_ID_COMMAND_SET_4 = 120, + ATA_ID_LAST_LUN = 126, + ATA_ID_DLF = 128, + ATA_ID_DATA_SET_MGMT = 169, +}; + +// ACS-2 Command Set +typedef enum : uint8_t { + OPCODE_DATASET_MANAGEMENT = 0x06, + OPCODE_EXECUTE_DEVICE_DIAGNOSTIC = 0x90, + OPCODE_FLUSH_CACHE = 0xE7, + OPCODE_FLUSH_CACHE_EXT = 0xEA, + OPCODE_IDENTIFY_DEVICE = 0xEC, + OPCODE_READ_DMA = 0xC8, + OPCODE_READ_DMA_EXT = 0x25, + OPCODE_READ_FPDMA_QUEUED = 0x60, + OPCODE_READ_SECTOR = 0x20, + OPCODE_READ_SECTOR_EXT = 0x24, + OPCODE_READ_VERIFY_SECTOR = 0x40, + OPCODE_READ_VERIFY_SECTOR_EXT = 0x42, + OPCODE_SET_FEATURE = 0xEF, + OPCODE_SET_MULTIPLE_MODE = 0xC6, + OPCODE_WRITE_DMA = 0xCA, + OPCODE_WRITE_DMA_EXT = 0x35, + OPCODE_WRITE_FPDMA_QUEUED = 0x61, + OPCODE_WRITE_SECTOR = 0x30, + OPCODE_WRITE_SECTOR_EXT = 0x34, +} OPCODE; + +// ACS-2 SET FEATURE Fields +enum : uint8_t { + FEATURE_ENABLE_VOLATILE_CACHE = 0x02, + FEATURE_SET_XFER_MODE, +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/device.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/device.cc new file mode 100644 index 0000000000..c45727e2bd --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/device.cc @@ -0,0 +1,931 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/sata/device.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +#define MAKE_LBA(req) \ + ((uint64_t)req.regH2D.lbaL[0] | ((uint64_t)req.regH2D.lbaL[1] << 8) | \ + ((uint64_t)req.regH2D.lbaL[2] << 16)) +#define MAKE_LBA_EXT(req) \ + (((uint64_t)req.regH2D.lbaH[0] << 24) | \ + ((uint64_t)req.regH2D.lbaH[1] << 32) | \ + ((uint64_t)req.regH2D.lbaH[2] << 40) | MAKE_LBA(req)) + +uint32_t makeCount(FIS &req) { + uint32_t count = req.regH2D.countL; + + if (count == 0) { + count = 0x100; + } + + return count; +} + +uint32_t makeCountExt(FIS &req) { + uint32_t count = ((uint16_t)req.regH2D.countH << 8) | req.regH2D.countL; + + if (count == 0) { + count = 0x10000; + } + + return count; +} + +Device::Device(HBA *p, DMAInterface *d, ConfigReader &c) + : pParent(p), pDMA(d), pDisk(nullptr), conf(c) { + pHIL = new HIL(c); + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + lbaSize = conf.readUint(CONFIG_SATA, SATA_LBA_SIZE); + + // DMA Handler for PRDT + dmaHandler = [](uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + delete pContext; + } + }; + writeDMASetup = [this](uint64_t tick, void *context) { + _writeDMASetup(tick, context); + }; + writeDMADone = [this](uint64_t tick, void *context) { + _writeDMADone(tick, context); + }; + readDMASetup = [this](uint64_t tick, void *context) { + _readDMASetup(tick, context); + }; + readDMADone = [this](uint64_t tick, void *context) { + _readDMADone(tick, context); + }; + + if (conf.readBoolean(CONFIG_SATA, SATA_ENABLE_DISK_IMAGE)) { + uint64_t diskSize; + uint64_t expected; + + expected = totalLogicalPages * logicalPageSize; + + if (conf.readBoolean(CONFIG_SATA, SATA_USE_COW_DISK)) { + pDisk = new CoWDisk(); + } + else { + pDisk = new Disk(); + } + + std::string filename = conf.readString(CONFIG_SATA, SATA_DISK_IMAGE_PATH); + + diskSize = pDisk->open(filename, expected, + conf.readUint(CONFIG_SATA, SATA_LBA_SIZE)); + + if (diskSize == 0) { + panic("Failed to open disk image"); + } + else if (diskSize != expected) { + if (conf.readBoolean(CONFIG_SATA, SATA_STRICT_DISK_SIZE)) { + panic("Disk size not match"); + } + } + } +} + +Device::~Device() { + delete pHIL; + delete pDisk; +} + +void Device::init() { + debugprint(LOG_HIL_SATA, "ATA | COMRESET"); + + // COMRESET received + Completion resp; + + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + resp.fis.regD2H.error = 0x01; + resp.fis.regD2H.lbaL[0] = 0x01; + resp.fis.regD2H.countL = 0x01; + + pParent->submitSignal(resp); +} + +void Device::prdtRead(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doRead = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t read = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - read); + + pContext->counter++; + pDMA->dmaRead(table[idx].dataBaseAddress, size, buffer + read, dmaHandler, + context); + + read += size; + + if (read >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::SATA__DEVICE, CPU::PRDT_READ, doRead, pContext); +} + +void Device::prdtWrite(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doWrite = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t written = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - written); + + pContext->counter++; + pDMA->dmaWrite(table[idx].dataBaseAddress, size, buffer + written, + dmaHandler, context); + + written += size; + + if (written >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::SATA__DEVICE, CPU::PRDT_WRITE, doWrite, pContext); +} + +void Device::convertUnit(uint64_t slba, uint64_t nlblk, Request &req) { + uint32_t lbaratio = logicalPageSize / lbaSize; + uint64_t slpn; + uint64_t nlp; + uint64_t off; + + slpn = slba / lbaratio; + off = slba % lbaratio; + nlp = (nlblk + off + lbaratio - 1) / lbaratio; + + req.range.slpn = slpn; + req.range.nlp = nlp; + req.offset = off * lbaSize; + req.length = nlblk * lbaSize; +} + +void Device::read(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doRead = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->read(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->read(slba, nlb, buffer); + } + + execute(CPU::SATA__DEVICE, CPU::READ, doRead, req); +} + +void Device::write(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doWrite = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->write(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->write(slba, nlb, buffer); + } + + execute(CPU::SATA__DEVICE, CPU::WRITE, doWrite, req); +} + +void Device::flush(DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doFlush = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->flush(*req); + + delete req; + }; + + req->range.slpn = 0; + req->range.nlp = totalLogicalPages; + req->offset = 0; + req->length = totalLogicalPages * logicalPageSize; + + execute(CPU::SATA__DEVICE, CPU::FLUSH, doFlush, req); +} + +void Device::_writeDMASetup(uint64_t, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, "ATA | WRITE FPDMA QUEUED | Tag %d | Setup DMA", + pContext->tag); + + Completion resp; + + resp.fis.dmaSetup.type = FIS_TYPE_DMA_SETUP; + resp.fis.dmaSetup.flag = 0x00; // DMA from Host to Device + resp.fis.dmaSetup.reserved2[0] = pContext->tag; + resp.fis.dmaSetup.transferCount = + pContext->nlb * lbaSize; // TODO: Unit correct? + pContext->buffer = (uint8_t *)calloc(pContext->nlb, lbaSize); + pContext->beginAt = getTick(); + + pParent->submitFIS(resp); + + // Begin DMA + CPUContext *pCPU = new CPUContext(writeDMADone, pContext, CPU::SATA__DEVICE, + CPU::WRITE_DMA_SETUP); + + prdtRead(pContext->prdt, pContext->prdtLength, pContext->nlb * lbaSize, + pContext->buffer, cpuHandler, pCPU); +} + +void Device::_writeDMADone(uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "NVM | WRITE FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | DMA %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->beginAt, + tick, tick - pContext->beginAt); + + DMAFunction nandDone = [this](uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "NVM | WRITE FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | NAND %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->tick, + tick, tick - pContext->tick); + + Completion resp; + + resp.fis.sdb.type = FIS_TYPE_DEV_BITS; + resp.fis.sdb.flag = 0x40; + resp.fis.sdb.payload = (1 << pContext->tag); + + pParent->submitFIS(resp); + pContext->release(); + }; + + pContext->tick = tick; + + CPUContext *pCPU = new CPUContext(nandDone, pContext, CPU::SATA__DEVICE, + CPU::WRITE_DMA_DONE); + + write(pContext->slba, pContext->nlb, pContext->buffer, cpuHandler, pCPU); +} + +void Device::_readDMASetup(uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | READ FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | NAND %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->beginAt, + tick, tick - pContext->beginAt); + + Completion resp; + + resp.fis.dmaSetup.type = FIS_TYPE_DMA_SETUP; + resp.fis.dmaSetup.flag = 0x20; // DMA from Device to Host + resp.fis.dmaSetup.reserved2[0] = pContext->tag; + resp.fis.dmaSetup.transferCount = + pContext->nlb * lbaSize; // TODO: Unit correct? + pContext->tick = tick; + + pParent->submitFIS(resp); + + // Begin DMA + CPUContext *pCPU = new CPUContext(readDMADone, pContext, CPU::SATA__DEVICE, + CPU::READ_DMA_SETUP); + + prdtWrite(pContext->prdt, pContext->prdtLength, pContext->nlb * lbaSize, + pContext->buffer, cpuHandler, pCPU); +} + +void Device::_readDMADone(uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "NVM | READ FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | DMA %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->beginAt, + tick, tick - pContext->beginAt); + + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (NCQContext *)context; + + Completion resp; + + resp.fis.sdb.type = FIS_TYPE_DEV_BITS; + resp.fis.sdb.flag = 0x40; + resp.fis.sdb.payload = (1 << pContext->tag); + + pParent->submitFIS(resp); + pContext->release(); + }; + + execute(CPU::SATA__DEVICE, CPU::READ_DMA_DONE, doSubmit, pContext); +} + +void Device::identifyDevice(CommandContext *cmd) { + static uint16_t data[256]; + uint64_t sectors = totalLogicalPages / lbaSize * logicalPageSize; + + debugprint(LOG_HIL_SATA, "ATA | IDENTIFY DEVICE"); + + // Fill IDENTIFY DEVICE structure based on ACS-2 + { + memset(data, 0, 512); + + // General configuration + data[ATA_ID_CONFIG] = 0x0000; + data[0x02] = 0xC837; + + strcpy((char *)(data + ATA_ID_SERNO), "00000000000000000000"); + strcpy((char *)(data + ATA_ID_FW_REV), "02.01.00"); + strcpy((char *)(data + ATA_ID_PROD), "SimpleSSD SATA Device by CAMELab"); + + for (int i = 10; i < 47; i++) { + data[i] = bswap16(data[i]); + } + + data[ATA_ID_MAX_MULTSECT] = 0x8000; + data[ATA_ID_CAPABILITY] = 0x0F00; + data[ATA_ID_FIELD_VALID] = 0x0006; + data[ATA_ID_MWDMA_MODES] = 0x0007; + data[ATA_ID_PIO_MODES] = 0x0003; + data[ATA_ID_EIDE_DMA_MIN] = 120; + data[ATA_ID_EIDE_DMA_TIME] = 120; + data[ATA_ID_EIDE_PIO] = 120; + data[ATA_ID_EIDE_PIO_IORDY] = 120; + data[ATA_ID_QUEUE_DEPTH] = 0x001F; + data[ATA_ID_SATA_CAPABILITY] = 0x010E; // Support 1.5/3/6Gbps + NCQ + data[ATA_ID_SATA_CAPABILITY_2] = 0x0006; // TODO: Set speed + data[ATA_ID_FEATURE_SUPP] = 0x0000; + data[ATA_ID_FEATURE_SUPP + 1] = 0x0000; + data[ATA_ID_MAJOR_VER] = 0x0300; // ACS-2 + ATA8-ACS + data[ATA_ID_COMMAND_SET_1] = 0x0020; + data[ATA_ID_COMMAND_SET_2] = 0x7400; // FLUSH CACHE [EXT] and 48bit + data[ATA_ID_CFSSE] = 0x4000; + + if (conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE)) { + data[ATA_ID_CFS_ENABLE_1] = 0x0020; + } + else { + data[ATA_ID_CFS_ENABLE_1] = 0x0000; + } + + data[ATA_ID_CFS_ENABLE_2] = 0x2400; + data[ATA_ID_CSF_DEFAULT] = 0x4000; + data[ATA_ID_UDMA_MODES] = 0x003F; + + if (sectors < 0x0FFFFFFF) { + *(uint32_t *)(data + ATA_ID_LBA_CAPACITY) = sectors; + } + else { + *(uint32_t *)(data + ATA_ID_LBA_CAPACITY) = 0x0FFFFFFF; + } + *(uint64_t *)(data + ATA_ID_LBA_CAPACITY_2) = sectors; + + if (logicalPageSize > lbaSize) { + data[ATA_ID_SECTOR_SIZE] |= 0x6000; + } + if (lbaSize > 512) { + data[ATA_ID_SECTOR_SIZE] |= 0x5000; + } + if (lbaSize != logicalPageSize) { + data[ATA_ID_SECTOR_SIZE] |= + ((uint8_t)log2(logicalPageSize / lbaSize)) & 0x0F; + } + + *(uint32_t *)(data + ATA_ID_LOGICAL_SECTOR_SIZE) = lbaSize / 2; + data[ATA_ID_DATA_SET_MGMT] = 0x0001; + + data[0xDE] = 0x1020; // Transport major version: SATA Rev 3.0 + } + + DMAFunction doWrite = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.maskIS |= PORT_IRQ_SG_DONE; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->release(); + }; + + prdtWrite(cmd->prdt, cmd->prdtLength, 512, (uint8_t *)data, doWrite, cmd); +} + +void Device::setMode(CommandContext *cmd) { + uint8_t fid = cmd->request.regH2D.featureL; + uint8_t id = cmd->request.regH2D.countL; + + switch (fid) { + case FEATURE_SET_XFER_MODE: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | Set Transfer Mode"); + + switch (id & 0xF8) { + case 0: + if (id & 0x01) { + debugprint(LOG_HIL_SATA, + "ATA | SET MODE | PIO default mode, disable IORDY"); + } + else { + debugprint(LOG_HIL_SATA, "ATA | SET MODE | PIO default mode"); + } + + break; + case 1: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | PIO%d", id & 0x07); + break; + case 4: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | MWDMA%d", id & 0x07); + break; + case 8: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | UDMA%d", id & 0x07); + break; + } + + break; + default: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | Not supported feature"); + break; + } + + Completion resp; + + resp.slotIndex = cmd->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + cmd->release(); +} + +void Device::readVerify(CommandContext *cmd) { + Request reqInternal; + uint64_t slba; + uint32_t nlb; + + if (cmd->request.regH2D.command == OPCODE_READ_VERIFY_SECTOR) { + debugprint(LOG_HIL_SATA, "ATA | READ VERIFY"); + + slba = MAKE_LBA(cmd->request); + nlb = makeCount(cmd->request); + } + else { + debugprint(LOG_HIL_SATA, "ATA | READ VERIFY EXT"); + + slba = MAKE_LBA_EXT(cmd->request); + nlb = makeCountExt(cmd->request); + } + + convertUnit(slba, nlb, reqInternal); + + // Check range + Completion resp; + + resp.slotIndex = cmd->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + if (reqInternal.range.nlp >= totalLogicalPages) { + resp.fis.regD2H.status = ATA_ERR; + resp.fis.regD2H.error = ATA_ABORTED; + } + + pParent->submitFIS(resp); + cmd->release(); +} + +void Device::readDMA(CommandContext *cmd, bool isPIO) { + uint64_t slba; + uint32_t nlb; + + if (cmd->request.regH2D.command == OPCODE_READ_SECTOR || + cmd->request.regH2D.command == OPCODE_READ_DMA) { + slba = MAKE_LBA(cmd->request); + nlb = makeCount(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "READ SECTOR" : "READ DMA", slba, nlb); + } + else { + slba = MAKE_LBA_EXT(cmd->request); + nlb = makeCountExt(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "READ SECTOR EXT" : "READ DMA EXT", slba, nlb); + } + + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | READ | %" PRIu64 " + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + Completion resp; + + resp.slotIndex = pContext->cmd->slotIndex; + resp.maskIS |= PORT_IRQ_SG_DONE; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + + pContext->cmd->release(); + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | READ | %" PRIu64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + prdtWrite(pContext->cmd->prdt, pContext->cmd->prdtLength, + pContext->nlb * lbaSize, pContext->buffer, doWrite, context); + }; + + IOContext *pContext = new IOContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->buffer = (uint8_t *)calloc(nlb, lbaSize); + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::SATA__DEVICE, CPU::READ_DMA); + + read(slba, nlb, pContext->buffer, cpuHandler, pCPU); +} + +void Device::readNCQ(CommandContext *cmd) { + uint64_t slba = MAKE_LBA_EXT(cmd->request); + uint32_t nlb = (cmd->request.regH2D.featureL | + ((uint32_t)cmd->request.regH2D.featureH << 8)); + uint8_t tag = (cmd->request.regH2D.countL >> 3) & 0x1F; + + if (nlb == 0) { + nlb = 0x10000; + } + + debugprint(LOG_HIL_SATA, + "ATA | READ FPDMA QUEUED | Tag %d | %" PRIu64 " + %d", tag, + slba, nlb); + + // Schedule read + NCQContext *pContext = new NCQContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->tag = tag; + pContext->buffer = (uint8_t *)calloc(pContext->nlb, lbaSize); + + read(slba, nlb, pContext->buffer, readDMASetup, pContext); + + // Send read scheduled + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->release(); + }; + + execute(CPU::SATA__DEVICE, CPU::READ_NCQ, doSubmit, cmd); +} + +void Device::writeDMA(CommandContext *cmd, bool isPIO) { + uint64_t slba; + uint32_t nlb; + + if (cmd->request.regH2D.command == OPCODE_WRITE_SECTOR || + cmd->request.regH2D.command == OPCODE_WRITE_DMA) { + slba = MAKE_LBA(cmd->request); + nlb = makeCount(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "WRITE SECTOR" : "WRITE DMA", slba, nlb); + } + else { + slba = MAKE_LBA_EXT(cmd->request); + nlb = makeCountExt(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "WRITE SECTOR EXT" : "WRITE DMA EXT", slba, nlb); + } + + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | WRITE | %" PRIu64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + Completion resp; + + resp.slotIndex = pContext->cmd->slotIndex; + resp.maskIS |= PORT_IRQ_SG_DONE; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + + pContext->cmd->release(); + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | WRITE | %" PRIu64 " + %d | DMA %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + write(pContext->slba, pContext->nlb, pContext->buffer, doWrite, context); + }; + + IOContext *pContext = new IOContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->buffer = (uint8_t *)calloc(nlb, lbaSize); + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::SATA__DEVICE, CPU::WRITE_DMA); + + prdtRead(pContext->cmd->prdt, pContext->cmd->prdtLength, nlb * lbaSize, + pContext->buffer, cpuHandler, pCPU); +} + +void Device::writeNCQ(CommandContext *cmd) { + struct Wrapper { + CommandContext *cmd; + NCQContext *ncq; + }; + + uint64_t slba = MAKE_LBA_EXT(cmd->request); + uint32_t nlb = (cmd->request.regH2D.featureL | + ((uint32_t)cmd->request.regH2D.featureH << 8)); + uint8_t tag = (cmd->request.regH2D.countL >> 3) & 0x1F; + + if (nlb == 0) { + nlb = 0x10000; + } + + debugprint(LOG_HIL_SATA, + "ATA | WRITE FPDMA QUEUED | Tag %d | %" PRIu64 " + %d", tag, + slba, nlb); + + // Schedule write + NCQContext *pContext = new NCQContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->tag = tag; + + // Send write scheduled + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (Wrapper *)context; + + Completion resp(writeDMASetup, pContext->ncq); + + resp.slotIndex = pContext->cmd->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->cmd->release(); + + delete pContext; + }; + + Wrapper *wrapper = new Wrapper(); + wrapper->cmd = cmd; + wrapper->ncq = pContext; + + execute(CPU::SATA__DEVICE, CPU::WRITE_NCQ, doSubmit, wrapper); +} + +void Device::flushCache(CommandContext *cmd) { + if (cmd->request.regH2D.command == OPCODE_READ_VERIFY_SECTOR) { + debugprint(LOG_HIL_SATA, "ATA | FLUSH CACHE"); + } + else { + debugprint(LOG_HIL_SATA, "ATA | FLUSH CACHE EXT"); + } + + DMAFunction doFlush = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->release(); + }; + + flush(doFlush, cmd); +} + +void Device::submitCommand(RequestContext *req) { + DMAFunction doRequest = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + bool processed = true; + + // Just use Register H2D because we are printing header only + debugprint(LOG_HIL_SATA, "QUEUE | FIS Type %02Xh | Command %02Xh", + pContext->request.regH2D.type, pContext->request.regH2D.command); + + switch (pContext->request.regH2D.command) { + case OPCODE_FLUSH_CACHE: + case OPCODE_FLUSH_CACHE_EXT: + flushCache(pContext); + break; + case OPCODE_IDENTIFY_DEVICE: + identifyDevice(pContext); + break; + case OPCODE_READ_DMA: + case OPCODE_READ_DMA_EXT: + readDMA(pContext); + break; + case OPCODE_READ_FPDMA_QUEUED: + readNCQ(pContext); + break; + case OPCODE_READ_SECTOR: + case OPCODE_READ_SECTOR_EXT: + readDMA(pContext, true); + break; + case OPCODE_READ_VERIFY_SECTOR: + case OPCODE_READ_VERIFY_SECTOR_EXT: + readVerify(pContext); + break; + case OPCODE_SET_FEATURE: + setMode(pContext); + break; + case OPCODE_WRITE_DMA: + case OPCODE_WRITE_DMA_EXT: + writeDMA(pContext); + break; + case OPCODE_WRITE_FPDMA_QUEUED: + writeNCQ(pContext); + break; + case OPCODE_WRITE_SECTOR: + case OPCODE_WRITE_SECTOR_EXT: + writeDMA(pContext, true); + break; + default: + processed = false; + break; + } + + if (!processed) { + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; // Type + resp.fis.regD2H.status = 0x01; // Status (Error) + resp.fis.regD2H.error = 0x04; // Error (Abort) + + pParent->submitFIS(resp); + pContext->release(); + } + }; + + CommandContext *pContext = new CommandContext(); + + pContext->slotIndex = req->idx; + + // Read Command Table from Command List + DMAFunction doReqRead = [doRequest](uint64_t now, void *context) { + auto pContext = (CommandContext *)context; + + pContext->reqDone = true; + + if (pContext->prdtDone) { + doRequest(now, context); + } + }; + + pDMA->dmaRead(req->header.commandTableBaseAddress, 64, pContext->request.data, + doReqRead, pContext); + + // We have PRDT + if (req->header.prdtLength > 0) { + DMAFunction doPRDTRead = [doRequest](uint64_t now, void *context) { + auto pContext = (CommandContext *)context; + + pContext->prdtDone = true; + + if (pContext->reqDone) { + doRequest(now, context); + } + }; + + pContext->prdtLength = req->header.prdtLength; + pContext->prdt = (uint8_t *)calloc(req->header.prdtLength, sizeof(PRDT)); + + pDMA->dmaRead(req->header.commandTableBaseAddress + 0x80, + pContext->prdtLength * sizeof(PRDT), pContext->prdt, + doPRDTRead, pContext); + } + else { + pContext->prdtDone = true; + } +} + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/device.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/device.hh new file mode 100644 index 0000000000..0d92b344ae --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/device.hh @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_DEVICE__ +#define __HIL_SATA_DEVICE__ + +#include "hil/hil.hh" +#include "hil/sata/def.hh" +#include "hil/sata/hba.hh" +#include "util/disk.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +struct CommandContext { + FIS request; + uint8_t *prdt; + uint16_t prdtLength; + + uint32_t slotIndex; + bool reqDone; + bool prdtDone; + + CommandContext() + : prdt(nullptr), + prdtLength(0), + slotIndex(0), + reqDone(false), + prdtDone(false) {} + + void release() { + if (prdtLength > 0) { + free(prdt); + } + + delete this; + } +}; + +struct IOContext { + uint64_t beginAt; + uint64_t tick; + uint64_t slba; + uint64_t nlb; + uint8_t *buffer; + + CommandContext *cmd; + + IOContext(CommandContext *c) + : beginAt(getTick()), tick(0), slba(0), nlb(0), buffer(nullptr), cmd(c) {} +}; + +struct NCQContext : public IOContext { + uint8_t tag; + + // Copy of PRDT + uint8_t *prdt; + uint16_t prdtLength; + + NCQContext(CommandContext *c) : IOContext(c), tag(0) { + prdt = c->prdt; + prdtLength = c->prdtLength; + + // Prevent prdt being freed + c->prdtLength = 0; + } + + void release() { + if (prdtLength > 0) { + free(prdt); + } + + delete this; + } +}; + +class Device : public StatObject { + private: + HBA *pParent; + DMAInterface *pDMA; + HIL *pHIL; + Disk *pDisk; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + uint32_t lbaSize; + + ConfigReader &conf; + + // Handlers + DMAFunction dmaHandler; + + // PRDT + void prdtRead(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void *); + void prdtWrite(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void *); + + // SimpleSSD + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void flush(DMAFunction &, void *); + void convertUnit(uint64_t, uint64_t, SimpleSSD::HIL::Request &); + + // FPDMA + DMAFunction writeDMASetup; + void _writeDMASetup(uint64_t, void *); + DMAFunction writeDMADone; + void _writeDMADone(uint64_t, void *); + DMAFunction readDMASetup; + void _readDMASetup(uint64_t, void *); + DMAFunction readDMADone; + void _readDMADone(uint64_t, void *); + + // SATA / ATA8-ACS commands + void identifyDevice(CommandContext *); + void setMode(CommandContext *); + void readVerify(CommandContext *); + void readDMA(CommandContext *, bool = false); + void readNCQ(CommandContext *); + void writeDMA(CommandContext *, bool = false); + void writeNCQ(CommandContext *); + void flushCache(CommandContext *); + + public: + Device(HBA *, DMAInterface *, ConfigReader &); + ~Device(); + + // For AHCI + void init(); + void submitCommand(RequestContext *); +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/hba.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/hba.cc new file mode 100644 index 0000000000..a55e1af433 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/hba.cc @@ -0,0 +1,532 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/sata/hba.hh" + +#include "hil/sata/device.hh" +#include "util/fifo.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +Completion::Completion() + : slotIndex(0), maskIS(0), func([](uint64_t, void *) {}), context(nullptr) { + memset(fis.data, 0, 64); +} + +Completion::Completion(DMAFunction &f, void *c) + : slotIndex(0), maskIS(0), func(f), context(c) { + memset(fis.data, 0, 64); +} + +HBA::HBA(Interface *i, ConfigReader &c) : pInterface(i), conf(c) { + ARM::AXI::BUS_WIDTH hostBusWidth; + SimpleSSD::SATA::SATA_GEN sataMode; + uint64_t hostBusClock; + + // Get AXI setting + hostBusWidth = + (ARM::AXI::BUS_WIDTH)conf.readInt(CONFIG_SATA, SATA_AXI_BUS_WIDTH); + hostBusClock = conf.readUint(CONFIG_SATA, SATA_AXI_CLOCK); + sataMode = (SimpleSSD::SATA::SATA_GEN)conf.readInt(CONFIG_SATA, SATA_MODE); + + memset(ghc.data, 0, 0x100); + memset(port.data, 0, 0x80); + + ghc.capability = 0xC0341F00; // NCQ with 32 entry, one port + ghc.globalHBAControl = 0x80000000; + ghc.portsImplemented = 0x00000001; // Bit 0 (Port 0) + ghc.AHCIVersion = 0x00010301; // AHCI version 1.3.1 + ghc.commandCompletionCoalescingControl = 0x00010100; + ghc.enclosureManagementLocation = 0x00280020; // 0xA0 + 0x20 + ghc.enclosureManagementControl = 0x03000000; + ghc.HBACapabilityExtended = 0x00000020; // BOHC not implemented + + port.commandAndStatus = 0x00000006; + port.taskFileData = 0x0000007F; + port.signature = 0xFFFFFFFF; + + workEvent = allocate([this](uint64_t) { work(); }); + requestEvent = allocate([this](uint64_t) { handleRequest(); }); + + maxRequest = conf.readUint(CONFIG_SATA, SATA_MAX_REQUEST_COUNT); + workInterval = conf.readUint(CONFIG_SATA, SATA_WORK_INTERVAL); + requestInterval = workInterval / maxRequest; + requestCounter = 0; + + submitFISPending = false; + + // FIFO + FIFOParam fifoParam; + + fifoParam.rqSize = 8192; + fifoParam.wqSize = 8192; + fifoParam.transferUnit = 2048; + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + pHostDMA = new FIFO(pInterface, fifoParam); + + fifoParam.latency = [sataMode](uint64_t size) -> uint64_t { + return SimpleSSD::SATA::calculateDelay(sataMode, size); + }; + + pPHY = new FIFO(pHostDMA, fifoParam); + + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + pDeviceDMA = new FIFO(pPHY, fifoParam); + + pDevice = new Device(this, pDeviceDMA, conf); +} + +HBA::~HBA() { + delete pDevice; + delete pDeviceDMA; + delete pPHY; + delete pHostDMA; +} + +void HBA::init() { + ghc.globalHBAControl = HOST_AHCI_EN; + ghc.interruptStatus = 0x00000000; + + // Reset is done + ghc.globalHBAControl &= ~HOST_RESET; + + // Port + deviceInited = false; +} + +void HBA::readAHCIRegister(uint32_t offset, uint32_t size, uint8_t *buffer) { + uint64_t temp = 0; + + for (uint32_t i = 0; i < size; i++) { + if (offset + i < 0x100) { + buffer[i] = ghc.data[offset + i]; + } + else if (offset + i < 0x180) { + buffer[i] = port.data[offset + i - 0x100]; + } + } + + if (size <= 8) { + memcpy(&temp, buffer, size); + } + else { + panic("Invalid register access size"); + } + + // debugprint(LOG_HIL_SATA, "REG | READ | %02Xh + %d | %08" PRIX64, + // offset, size, temp); +} + +void HBA::writeAHCIRegister(uint32_t offset, uint32_t size, uint8_t *buffer) { + uint32_t temp = 0; + + if (size <= 8) { + memcpy(&temp, buffer, 4); + } + else { + panic("Invalid register access size"); + } + + // debugprint(LOG_HIL_SATA, "REG | WRITE | %02Xh + %d | %08X", offset, + // size, temp); + + // Access to AHCI Generic Host Control Register + if (offset < 0x100) { + switch (offset) { + case REG_GHC: + ghc.globalHBAControl &= 0xFFFFFFFC; + ghc.globalHBAControl |= temp & 0x00000003; + + if (ghc.globalHBAControl & HOST_RESET) { + // HBA Reset + init(); + } + + break; + case REG_IS: + ghc.interruptStatus &= ~temp; + + break; + case REG_CCC_CTL: + ghc.commandCompletionCoalescingControl &= 0x000000FE; + ghc.commandCompletionCoalescingControl |= temp & 0xFFFFFF01; + + break; + case REG_CCC_PORTS: + ghc.commandCompletionCoalescingPorts = temp; + + break; + case REG_EM_CTL: + ghc.enclosureManagementControl &= 0xFFFFFCFE | ((~temp) & 0x00000001); + ghc.enclosureManagementControl |= temp & 0x00000300; + + if (ghc.enclosureManagementControl & EM_CTL_RST) { + // Reset EM message logic + ghc.enclosureManagementControl &= ~EM_CTL_RST; + } + + if (ghc.enclosureManagementControl & EM_CTL_TM) { + // Transmit message + ghc.enclosureManagementControl &= ~EM_CTL_TM; + } + + break; + case REG_BOHC: + ghc.handoffControlAndStatus &= 0xFFFFFFE0 | ((~temp) & 0x00000008); + ghc.handoffControlAndStatus |= temp & 0x00000017; + + break; + } + } + // Access to Port 0 Register + else if (offset < 0x180) { + offset -= 0x100; + + switch (offset) { + case REG_P0CLB: + port.commandListBaseAddress &= 0xFFFFFFFF00000000; + port.commandListBaseAddress |= temp & 0xFFFFFC00; + + break; + case REG_P0CLBU: + port.commandListBaseAddress &= 0xFFFFFFFF; + port.commandListBaseAddress |= (uint64_t)temp << 32; + + break; + case REG_P0FB: + port.FISBaseAddress &= 0xFFFFFFFF00000000; + port.FISBaseAddress |= temp & 0xFFFFFF00; + + break; + case REG_P0FBU: + port.FISBaseAddress &= 0xFFFFFFFF; + port.FISBaseAddress |= (uint64_t)temp << 32; + + break; + case REG_P0IS: + port.interruptStatus &= (~temp) & 0x037FFF50; + + interruptCleared(); + + break; + case REG_P0IE: + port.interruptEnable &= 0x823FFF80; + port.interruptEnable |= temp & 0x7DC0007F; + + updateInterrupt(); + + break; + case REG_P0CMD: + port.commandAndStatus &= 0x0CFFFFE6 | ((~temp) & 0x00000008); + port.commandAndStatus |= temp & 0xF3000011; + + if (port.commandAndStatus & PORT_CMD_START) { + if (!scheduled(workEvent) && !scheduled(requestEvent)) { + // Enable controller + schedule(workEvent, getTick() + workInterval); + + port.commandAndStatus |= PORT_CMD_LIST_ON; + } + } + else { + // Disable controller + deschedule(workEvent); + + port.commandAndStatus &= ~PORT_CMD_LIST_ON; + } + + // Set FR + if (port.commandAndStatus & PORT_CMD_FIS_RX) { + port.commandAndStatus |= PORT_CMD_FIS_ON; + } + else { + port.commandAndStatus &= ~PORT_CMD_FIS_ON; + } + + break; + case REG_P0SCTL: + port.control &= 0xFFFFF000; + port.control |= temp & 0x00000FFF; + + if ((port.control & 0x0F) == 0x01 && !deviceInited) { + deviceInited = true; + + pDevice->init(); + } + + break; + case REG_P0SERR: + port.error &= ~temp; + + break; + case REG_P0SACT: + port.active |= temp; + + break; + case REG_P0CI: { + uint32_t old = port.commandIssue; + port.commandIssue |= temp; + + processCommand(old ^ port.commandIssue); + + } break; + case REG_P0SNTF: + port.notification &= 0xFFFF0000 | ((~temp) & 0x0000FFFF); + + break; + case REG_P0FBS: + port.switchingControl &= 0xFFFFF0FC | ((~temp) & 0x00000002); + port.switchingControl |= temp & 0x00000F03; + + break; + default: + warn("Write to read only register 0x%X", offset); + + break; + } + } + + if (size > 4) { + writeAHCIRegister(offset + 4, size - 4, buffer + 4); + } +} + +void HBA::updateInterrupt() { + if (ghc.globalHBAControl & HOST_IRQ_EN) { + if ((ghc.interruptStatus & 0x01) && + (port.interruptStatus & port.interruptEnable)) { + pInterface->updateInterrupt(true); + } + } +} + +void HBA::processCommand(uint32_t ci) { + uint32_t bit = 0; + + for (int i = 0; i < 32; i++) { + bit = 1 << i; + + if (ci & bit) { + lRequestQueue.push(i); + } + } +} + +void HBA::work() { + lastWorkAt = getTick(); + + handleRequest(); +} + +void HBA::handleRequest() { + uint64_t tick = getTick(); + + if (lRequestQueue.size() > 0) { + auto pContext = new RequestContext(); + + pContext->idx = lRequestQueue.front(); + lRequestQueue.pop(); + + DMAFunction doRead = [this](uint64_t, void *context) { + auto pContext = (RequestContext *)context; + + debugprint(LOG_HIL_SATA, "QUEUE | Entry %d", pContext->idx); + pDevice->submitCommand(pContext); + + delete pContext; + }; + + uint64_t addr = + port.commandListBaseAddress + pContext->idx * sizeof(CommandHeader); + + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::SATA__DEVICE, + CPU::SUBMIT_COMMAND); + + pHostDMA->dmaRead(addr, sizeof(CommandHeader), pContext->header.data, + cpuHandler, pCPU); + } + + if (lRequestQueue.size() > 0 && requestCounter < maxRequest) { + schedule(requestEvent, tick + requestInterval); + } + else { + schedule(workEvent, MAX(tick + requestInterval, lastWorkAt + workInterval)); + } +} + +void HBA::submitFIS(Completion &resp) { + switch (resp.fis.data[0]) { + case FIS_TYPE_DMA_SETUP: + resp.maskIS |= PORT_IRQ_DMAS_FIS; + break; + case FIS_TYPE_PIO_SETUP: + resp.maskIS |= PORT_IRQ_PIOS_FIS; + break; + case FIS_TYPE_REG_D2H: + resp.maskIS |= PORT_IRQ_D2H_REG_FIS; + break; + case FIS_TYPE_DEV_BITS: + resp.maskIS |= PORT_IRQ_SDB_FIS; + break; + default: + resp.maskIS |= PORT_IRQ_UNK_FIS; + break; + } + + if (resp.fis.data[2] & ATA_ERR) { + resp.maskIS |= PORT_IRQ_TF_ERR; + } + + if (resp.fis.data[0] == FIS_TYPE_DEV_BITS) { + // Reset PxSACT + port.active &= ~resp.fis.sdb.payload; + } + + lResponseQueue.push(resp); + handleResponse(); +} + +void HBA::submitSignal(Completion &resp) { + if (resp.fis.data[0] != FIS_TYPE_REG_D2H) { + panic("Invalid FIS to submitSignal"); + } + + resp.maskIS = PORT_IRQ_TF_ERR | PORT_IRQ_D2H_REG_FIS; + + // Set PxSIG + port.signature = 0x00000101; // SATA drive + + // Set PxSSTS + // TODO: set interface speed + port.status = 0x00000133; + + lResponseQueue.push(resp); + + DMAFunction doCompletion = [this](uint64_t, void *context) { + uint32_t mask = (uint64_t)context; + + // Set interrupt mask + port.interruptStatus |= mask; + ghc.interruptStatus |= 0x01; // Port 0 has interrupt + + pInterface->updateInterrupt(true); + }; + + pHostDMA->dmaWrite(port.FISBaseAddress + 0x40, 0x14, resp.fis.data, + doCompletion, (void *)(uint64_t)resp.maskIS); +} + +void HBA::handleResponse() { + auto &iter = lResponseQueue.front(); + + // There is ongoing response + if (submitFISPending) { + return; + } + + // Write FIS entry + uint64_t base = port.FISBaseAddress; + uint64_t size; + + switch (iter.fis.data[0]) { + case FIS_TYPE_DMA_SETUP: + size = 0x1C; + break; + case FIS_TYPE_PIO_SETUP: + base += 0x20; + size = 0x14; + break; + case FIS_TYPE_REG_D2H: + base += 0x40; + size = 0x14; + break; + case FIS_TYPE_DEV_BITS: + base += 0x58; + size = 0x08; + break; + default: + base += 0x60; + size = 64; + break; + } + + DMAFunction doCompletion = [this](uint64_t, void *context) { + uint32_t mask = (uint64_t)context; + + // Set interrupt mask + port.interruptStatus |= mask; + ghc.interruptStatus |= 0x01; // Port 0 has interrupt + + updateInterrupt(); + }; + + debugprint(LOG_HIL_SATA, "QUEUE | submitting FIS for entry %d", + iter.slotIndex); + + pHostDMA->dmaWrite(base, size, iter.fis.data, doCompletion, + (void *)(uint64_t)iter.maskIS); +} + +void HBA::interruptCleared() { + if (lResponseQueue.size() > 0) { + auto &iter = lResponseQueue.front(); + + // Interrupt cleared + if (!(port.interruptStatus & iter.maskIS)) { + debugprint(LOG_HIL_SATA, "QUEUE | FIS completed for entry %d", + iter.slotIndex); + + pInterface->updateInterrupt(false); + + // Copy function + auto func = iter.func; + auto context = iter.context; + + // Clear PxCI + port.commandIssue &= ~((uint32_t)1 << iter.slotIndex); + + // Pop + submitFISPending = false; + lResponseQueue.pop(); + + if (lResponseQueue.size() > 0) { + handleResponse(); + } + + func(getTick(), context); + } + } +} + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/hba.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/hba.hh new file mode 100644 index 0000000000..cadc243606 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/hba.hh @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_HBA__ +#define __HIL_SATA_HBA__ + +#include + +#include "hil/sata/def.hh" +#include "hil/sata/interface.hh" +#include "sim/config_reader.hh" +#include "sim/simulator.hh" +#include "sim/statistics.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +class Device; + +class Completion { + public: + uint32_t slotIndex; // PxCI bit index + uint32_t maskIS; // PxIS bit mask + + // Received FIS + FIS fis; + + // Function handler when completion is done + // This only for NCQ operations (READ/WRITE FPDMA QUEUED) + DMAFunction func; + void *context; + + Completion(); + Completion(DMAFunction &, void *); +}; + +struct RequestContext { + uint32_t idx; + CommandHeader header; +}; + +typedef std::function RequestFunction; + +class HBA : public StatObject { + private: + Interface *pInterface; + Device *pDevice; + ConfigReader &conf; + + DMAInterface *pHostDMA; + DMAInterface *pPHY; + DMAInterface *pDeviceDMA; + + AHCIGHCRegister ghc; + AHCIPortRegister port; + + // Request handling + Event workEvent; + Event requestEvent; + uint64_t workInterval; + uint64_t requestInterval; + uint64_t maxRequest; + uint64_t requestCounter; + uint64_t lastWorkAt; + + bool submitFISPending; + std::queue lRequestQueue; + std::queue lResponseQueue; + + // Port state + bool deviceInited; + + void init(); + void updateInterrupt(); + + void processCommand(uint32_t); + void work(); + void handleRequest(); + void handleResponse(); + void interruptCleared(); + + public: + HBA(Interface *, ConfigReader &); + ~HBA(); + + // For Device + void submitFIS(Completion &); + void submitSignal(Completion &); + + // For Interface + void readAHCIRegister(uint32_t, uint32_t, uint8_t *); + void writeAHCIRegister(uint32_t, uint32_t, uint8_t *); +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/interface.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/interface.hh new file mode 100644 index 0000000000..7f3ef1d9f4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/sata/interface.hh @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_SATA_INTERFACE__ +#define __HIL_SATA_INTERFACE__ + +#include + +#include "sim/dma_interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +class HBA; + +class Interface : public SimpleSSD::DMAInterface { + protected: + HBA *pController; + + public: + virtual void updateInterrupt(bool) = 0; +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/config.cc new file mode 100644 index 0000000000..c5f5077d65 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/config.cc @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/ufs/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +const char NAME_WORK_INTERVAL[] = "WorkInterval"; +const char NAME_MAX_REQUEST_COUNT[] = "MaxRequestCount"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_ENABLE_DISK_IMAGE[] = "EnableDiskImage"; +const char NAME_STRICT_DISK_SIZE[] = "StrictSizeCheck"; +const char NAME_DISK_IMAGE_PATH[] = "DiskImageFile"; +const char NAME_USE_COW_DISK[] = "UseCopyOnWriteDisk"; +const char NAME_HOST_AXI_BUS_WIDTH[] = "AXIBusWidth"; +const char NAME_HOST_AXI_CLOCK[] = "AXIClock"; +const char NAME_MPHY_MODE[] = "MPHYMode"; +const char NAME_MPHY_LANE[] = "MPHYLane"; + +Config::Config() { + workInterval = 50000; + maxRequestCount = 4; + lbaSize = 512; + enableDiskImage = false; + strictDiskSize = false; + diskImagePath = ""; + useCopyOnWriteDisk = false; + axiWidth = ARM::AXI::BUS_64BIT; + axiClock = 300000000; + mphyMode = MIPI::M_PHY::HS_G3; + mphyLane = 2; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_WORK_INTERVAL)) { + workInterval = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_REQUEST_COUNT)) { + maxRequestCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DISK_IMAGE)) { + enableDiskImage = convertBool(value); + } + else if (MATCH_NAME(NAME_STRICT_DISK_SIZE)) { + strictDiskSize = convertBool(value); + } + else if (MATCH_NAME(NAME_DISK_IMAGE_PATH)) { + diskImagePath = value; + } + else if (MATCH_NAME(NAME_USE_COW_DISK)) { + useCopyOnWriteDisk = convertBool(value); + } + else if (MATCH_NAME(NAME_HOST_AXI_BUS_WIDTH)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + axiWidth = ARM::AXI::BUS_32BIT; + break; + case 1: + axiWidth = ARM::AXI::BUS_64BIT; + break; + case 2: + axiWidth = ARM::AXI::BUS_128BIT; + break; + case 3: + axiWidth = ARM::AXI::BUS_256BIT; + break; + case 4: + axiWidth = ARM::AXI::BUS_512BIT; + break; + case 5: + axiWidth = ARM::AXI::BUS_1024BIT; + break; + default: + panic("Invalid AXI Stream Bus Width"); + break; + } + } + else if (MATCH_NAME(NAME_HOST_AXI_CLOCK)) { + axiClock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MPHY_MODE)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + mphyMode = MIPI::M_PHY::HS_G1; + break; + case 1: + mphyMode = MIPI::M_PHY::HS_G2; + break; + case 2: + mphyMode = MIPI::M_PHY::HS_G3; + break; + case 3: + mphyMode = MIPI::M_PHY::HS_G4; + break; + default: + panic("Invalid M-PHY Mode"); + break; + } + } + else if (MATCH_NAME(NAME_MPHY_LANE)) { + mphyLane = (uint8_t)strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (popcount(lbaSize) != 1 || lbaSize < 512) { + panic("Invalid LBA size"); + } + if (maxRequestCount == 0) { + panic("MaxRequestCount should be larger then 0"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case UFS_HOST_AXI_BUS_WIDTH: + ret = axiWidth; + break; + case UFS_MPHY_MODE: + ret = mphyMode; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case UFS_WORK_INTERVAL: + ret = workInterval; + break; + case UFS_MAX_REQUEST_COUNT: + ret = maxRequestCount; + break; + case UFS_LBA_SIZE: + ret = lbaSize; + break; + case UFS_HOST_AXI_CLOCK: + ret = axiClock; + break; + case UFS_MPHY_LANE: + ret = mphyLane; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret(""); + + switch (idx) { + case UFS_DISK_IMAGE_PATH: + ret = diskImagePath; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case UFS_ENABLE_DISK_IMAGE: + ret = enableDiskImage; + break; + case UFS_STRICT_DISK_SIZE: + ret = strictDiskSize; + break; + case UFS_USE_COW_DISK: + ret = useCopyOnWriteDisk; + break; + } + + return ret; +} + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/config.hh new file mode 100644 index 0000000000..460af3bc10 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/config.hh @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_CONFIG__ +#define __HIL_UFS_CONFIG__ + +#include "sim/base_config.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +typedef enum { + UFS_WORK_INTERVAL, + UFS_MAX_REQUEST_COUNT, + UFS_LBA_SIZE, + UFS_ENABLE_DISK_IMAGE, + UFS_STRICT_DISK_SIZE, + UFS_DISK_IMAGE_PATH, + UFS_USE_COW_DISK, + UFS_HOST_AXI_BUS_WIDTH, + UFS_HOST_AXI_CLOCK, + UFS_MPHY_MODE, + UFS_MPHY_LANE, +} UFS_CONFIG; + +class Config : public BaseConfig { + private: + ARM::AXI::BUS_WIDTH axiWidth; //!< Default: BUS_64BIT + uint64_t axiClock; //!< Default: 300MHz + uint64_t workInterval; //!< Default: 50000 (50ns) + uint64_t maxRequestCount; //!< Default: 4 + uint64_t lbaSize; //!< Default: 512 + bool enableDiskImage; //!< Default: False + bool strictDiskSize; //!< Default: False + bool useCopyOnWriteDisk; //!< Default: False + std::string diskImagePath; //!< Default: "" + MIPI::M_PHY::M_PHY_MODE mphyMode; //!< Default: HS_G3 + uint8_t mphyLane; //!< Default: 2 + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/def.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/def.cc new file mode 100644 index 0000000000..5484d4cdac --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/def.cc @@ -0,0 +1,579 @@ +/* + * UFS Definitions + * + * Author: Donghyun Gouk + */ + +#include "hil/ufs/def.hh" + +#ifdef _MSC_VER +#define htobe16(x) ((x) >> 8 | ((x)&0xFF) << 8) +#define htobe32(x) (htobe16((x) >> 16) & 0xFFFF | htobe16((x)&0xFFFF) << 16) +#define be16toh(x) htobe16(x) +#define be32toh(x) htobe32(x) +#elif defined(__APPLE__) +#include +#define htobe16(x) OSSwapHostToBigInt16(x) +#define htobe32(x) OSSwapHostToBigInt32(x) +#define be16toh(x) OSSwapBigToHostInt16(x) +#define be32toh(x) OSSwapBigToHostInt32(x) +#else +#include +#endif + +#include +#include + +UFSHCIRegister::UFSHCIRegister() { + memset(data, 0, 0xB0); +} + +UPIU::UPIU() { + header.transactionType = 0; + header.flags = 0; + header.lun = 0; + header.taskTag = 0; + header.commandSetType = 0; + header.function = 0; + header.response = 0; + header.status = 0; + header.ehsLength = 0; + header.deviceInfo = 0; + header.dataSegmentLength = 0; +} + +UPIU::~UPIU() {} + +bool UPIU::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 11) { + header.transactionType = buffer[0]; + header.flags = buffer[1]; + header.lun = buffer[2]; + header.taskTag = buffer[3]; + header.commandSetType = buffer[4]; + header.function = buffer[5]; + header.response = buffer[6]; + header.status = buffer[7]; + header.ehsLength = buffer[8]; + header.deviceInfo = buffer[9]; + header.dataSegmentLength = ((uint16_t)buffer[10] << 8) | buffer[11]; + + ret = true; + } + + return ret; +} + +bool UPIU::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 11) { + buffer[0] = header.transactionType & 0x3F; + buffer[1] = header.flags; + buffer[2] = header.lun; + buffer[3] = header.taskTag; + buffer[4] = header.commandSetType; + buffer[5] = header.function; + buffer[6] = header.response; + buffer[7] = header.status; + buffer[8] = header.ehsLength; + buffer[9] = header.deviceInfo; + buffer[10] = header.dataSegmentLength >> 8; + buffer[11] = header.dataSegmentLength & 0xFF; + + ret = true; + } + + return ret; +} + +uint32_t UPIU::getLength() { + return 12; +} + +UPIUCommand::UPIUCommand() : UPIU(), expectedDataLength(0) { + memset(cdb, 0, 16); +} + +UPIUCommand::~UPIUCommand() {} + +bool UPIUCommand::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_COMMAND && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + expectedDataLength = be32toh(temp); + + memcpy(cdb, buffer + 16, 16); + } + + return ret; +} + +bool UPIUCommand::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_COMMAND; + ret = UPIU::get(buffer, length); + + temp = htobe32(expectedDataLength); + memcpy(buffer + 12, &temp, 4); + + memcpy(buffer + 16, cdb, 16); + } + + return ret; +} + +uint32_t UPIUCommand::getLength() { + return 32; +} + +UPIUResponse::UPIUResponse() : UPIU(), residualCount(0), senseLength(0) { + memset(senseData, 0, 18); +} + +UPIUResponse::~UPIUResponse() {} + +bool UPIUResponse::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_RESPONSE && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + residualCount = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31 + offset + header.dataSegmentLength) { + senseLength = + ((uint16_t)buffer[32 + offset] << 8) | buffer[33 + offset]; + memcpy(senseData, buffer + 34 + offset, senseLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUResponse::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_RESPONSE; + ret = UPIU::get(buffer, length); + + temp = htobe32(residualCount); + memcpy(buffer + 12, &temp, 4); + + memset(buffer + 16, 0, 16); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + buffer[32] = senseLength >> 8; + buffer[33] = senseLength & 0xFF; + memcpy(buffer + 34, senseData, senseLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUResponse::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUQueryReq::UPIUQueryReq() : UPIU(), data(nullptr) {} + +UPIUQueryReq::~UPIUQueryReq() { + if (data) { + free(data); + } +} + +bool UPIUQueryReq::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_QUERY_REQUEST && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + opcode = buffer[12]; + idn = buffer[13]; + index = buffer[14]; + selector = buffer[15]; + this->length = ((uint16_t)buffer[18] << 8) | buffer[19]; + + memcpy(&temp, buffer + 20, 4); + val1 = be32toh(temp); + + memcpy(&temp, buffer + 24, 4); + val2 = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUQueryReq::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_QUERY_REQUEST; + ret = UPIU::get(buffer, length); + + buffer[12] = opcode; + buffer[13] = idn; + buffer[14] = index; + buffer[15] = selector; + buffer[18] = this->length >> 8; + buffer[19] = this->length & 0xFF; + + temp = htobe32(val1); + memcpy(buffer + 20, &temp, 4); + + temp = htobe32(val2); + memcpy(buffer + 24, &temp, 4); + + memset(buffer + 28, 0, 4); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUQueryReq::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUQueryResp::UPIUQueryResp() : UPIU(), data(nullptr) {} + +UPIUQueryResp::~UPIUQueryResp() { + if (data) { + free(data); + } +} + +bool UPIUQueryResp::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_QUERY_RESPONSE && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + opcode = buffer[12]; + idn = buffer[13]; + index = buffer[14]; + selector = buffer[15]; + this->length = ((uint16_t)buffer[18] << 8) | buffer[19]; + + memcpy(&temp, buffer + 20, 4); + val1 = be32toh(temp); + + memcpy(&temp, buffer + 24, 4); + val2 = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUQueryResp::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_QUERY_RESPONSE; + ret = UPIU::get(buffer, length); + + buffer[12] = opcode; + buffer[13] = idn; + buffer[14] = index; + buffer[15] = selector; + buffer[18] = this->length >> 8; + buffer[19] = this->length & 0xFF; + + temp = htobe32(val1); + memcpy(buffer + 20, &temp, 4); + + temp = htobe32(val2); + memcpy(buffer + 24, &temp, 4); + + memset(buffer + 28, 0, 4); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUQueryResp::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUDataOut::UPIUDataOut() : UPIU(), offset(0), count(0), data(nullptr) {} + +UPIUDataOut::~UPIUDataOut() { + if (data) { + free(data); + } +} + +bool UPIUDataOut::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_DATA_OUT && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + offset = be32toh(temp); + + memcpy(&temp, buffer + 16, 4); + count = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUDataOut::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_DATA_OUT; + ret = UPIU::get(buffer, length); + + temp = htobe32(offset); + memcpy(buffer + 12, &temp, 4); + + temp = htobe32(count); + memcpy(buffer + 16, &temp, 4); + + memset(buffer + 20, 0, 12); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUDataOut::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUDataIn::UPIUDataIn() : UPIU(), offset(0), count(0), data(nullptr) {} + +UPIUDataIn::~UPIUDataIn() { + if (data) { + free(data); + } +} + +bool UPIUDataIn::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_DATA_IN && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + offset = be32toh(temp); + + memcpy(&temp, buffer + 16, 4); + count = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUDataIn::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_DATA_IN; + ret = UPIU::get(buffer, length); + + temp = htobe32(offset); + memcpy(buffer + 12, &temp, 4); + + temp = htobe32(count); + memcpy(buffer + 16, &temp, 4); + + memset(buffer + 20, 0, 12); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUDataIn::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUReadyToTransfer::UPIUReadyToTransfer() : UPIU(), offset(0), count(0) {} + +UPIUReadyToTransfer::~UPIUReadyToTransfer() {} + +bool UPIUReadyToTransfer::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_DATA_IN && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + offset = be32toh(temp); + + memcpy(&temp, buffer + 16, 4); + count = be32toh(temp); + } + + return ret; +} + +bool UPIUReadyToTransfer::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_READY_TO_TRANSFER; + ret = UPIU::get(buffer, length); + + temp = htobe32(offset); + memcpy(buffer + 12, &temp, 4); + + temp = htobe32(count); + memcpy(buffer + 16, &temp, 4); + + memset(buffer + 20, 0, 12); + } + + return ret; +} + +uint32_t UPIUReadyToTransfer::getLength() { + return 32; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/def.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/def.hh new file mode 100644 index 0000000000..35bb0c5b43 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/def.hh @@ -0,0 +1,416 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_DEF__ +#define __HIL_UFS_DEF__ + +#include + +union UFSHCIRegister { + uint8_t data[0xB0]; + struct { + /* Host Capabilities */ + uint32_t cap; + uint32_t reserved0; + uint32_t version; + uint32_t reserved1; + uint32_t hcddid; + uint32_t hcpmid; + uint32_t reserved2[2]; + + /* Operation Runtime */ + uint32_t is; + uint32_t ie; + uint32_t reserved3[2]; + uint32_t hcs; + uint32_t hce; + uint32_t uecpa; + uint32_t uecdl; + uint32_t uecn; + uint32_t uect; + uint32_t uecdme; + uint32_t utriacr; + + /* UFS Transport Protocol Transfer */ + uint64_t utrlba; + uint32_t utrldbr; + uint32_t utrlclr; + uint32_t utrlrsr; + uint32_t reserved4[3]; + + /* UFS Transport Protocol Task Management */ + uint64_t utmrlba; + uint32_t utmrldbr; + uint32_t utmrlclr; + uint32_t utmrlrsr; + uint32_t reserved5[3]; + + /* UFS InterConnect Command */ + uint32_t uiccmdr; + uint32_t ucmdarg1; + uint32_t ucmdarg2; + uint32_t ucmdarg3; + uint32_t reserved6[4]; + }; + + UFSHCIRegister(); +}; + +enum UFSHCIREG { + REG_CAP = 0x00, + REG_VER = 0x08, + REG_HCDDID = 0x10, + REG_HCPMID = 0x14, + REG_IS = 0x20, + REG_IE = 0x24, + REG_HCS = 0x30, + REG_HCE = 0x34, + REG_UECPA = 0x38, + REG_UECDL = 0x3C, + REG_UECN = 0x40, + REG_UECT = 0x44, + REG_UECDME = 0x48, + REG_UTRIACR = 0x4C, + REG_UTRLBA = 0x50, + REG_UTRLBAU = 0x54, + REG_UTRLDBR = 0x58, + REG_UTRLCLR = 0x5C, + REG_UTRLRSR = 0x60, + REG_UTMRLBA = 0x70, + REG_UTMRLBAU = 0x74, + REG_UTMRLDBR = 0x78, + REG_UTMRLCLR = 0x7C, + REG_UTMRLRSR = 0x80, + REG_UICCMDR = 0x90, + REG_UCMDARG1 = 0x94, + REG_UCMDARG2 = 0x98, + REG_UCMDARG3 = 0x9C, +}; + +enum DMECMD { + DME_GET = 0x01, + DME_SET, + DME_PEER_GET, + DME_PEER_SET, + DME_POWERON = 0x10, + DME_POWEROFF, + DME_ENABLE, + DME_RESET = 0x14, + DME_ENDPOINTRESET, + DME_LINKSTARTUP, + DME_HIBERNATE_ENTER, + DME_HIBERNATE_EXIT, + DME_TEST_MODE = 0x1A +}; + +enum DMEERR { + ERR_SUCCESS, + ERR_INVALID_MIB, + ERR_INVALID_MIB_VALUE, + ERR_READ_ONLY_MIB, + ERR_WRITE_ONLY_MIB, + ERR_BAD_INDEX, + ERR_LOCKED_MIB, + ERR_BAD_TEST_FEATURE_INDEX, + ERR_PEER_COMMUNICATION_FAILURE, + ERR_BUSY, + ERR_DME_FAILURE +}; + +enum MIB { + // See Linux kernel /drivers/scsi/ufs/unipro.h + MIB_VS_POWERSTATE = 0xD083 +}; + +enum UFSLINK { + // See Linux kernel /drivers/scsi/ufs/unihci.h + UFSHCD_LINK_IS_DOWN = 1, + UFSHCD_LINK_IS_UP +}; + +#define MAKE_UICARG(mib, selector) \ + (((uint32_t)(mib) << 16) | ((uint32_t)(selector)&0xFFFF)) + +#define UFS_BIT(x) (1L << (x)) + +#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0) +#define UIC_DME_END_PT_RESET UFS_BIT(1) +#define UIC_ERROR UFS_BIT(2) +#define UIC_TEST_MODE UFS_BIT(3) +#define UIC_POWER_MODE UFS_BIT(4) +#define UIC_HIBERNATE_EXIT UFS_BIT(5) +#define UIC_HIBERNATE_ENTER UFS_BIT(6) +#define UIC_LINK_LOST UFS_BIT(7) +#define UIC_LINK_STARTUP UFS_BIT(8) +#define UTP_TASK_REQ_COMPL UFS_BIT(9) +#define UIC_COMMAND_COMPL UFS_BIT(10) +#define DEVICE_FATAL_ERROR UFS_BIT(11) +#define CONTROLLER_FATAL_ERROR UFS_BIT(16) +#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17) + +#define UTP_TRANSFER_REQ_DESC_SIZE 32 + +union UTPTransferReqDesc { + uint8_t data[UTP_TRANSFER_REQ_DESC_SIZE]; + struct { + uint32_t dw0; + uint32_t dw1; + uint32_t dw2; + uint32_t dw3; + uint32_t cmdAddress; + uint32_t cmdAddressUpper; + uint16_t respUPIULength; + uint16_t respUPIUOffset; + uint16_t prdtLength; + uint16_t prdtOffset; + }; +}; + +enum UTP_TRANSFER_CMD { + CMD_SCSI, + CMD_NATIVE_UFS_COMMAND, + CMD_DEVICE_MGMT_FUNCTION +}; + +union PRDT { + uint8_t data[16]; + struct { + uint64_t dataAddress; + uint32_t dw2; + uint32_t dw3; + }; +}; + +enum UPIU_OPCODE { // Response OPCODE + OPCODE_NOP_OUT = 0x00, // OPCODE_NOP_IN + OPCODE_COMMAND, // OPCODE_RESPONSE + OPCODE_DATA_OUT, // OPCODE_RESPONSE + OPCODE_TASK_MGMT_REQ = 0x04, // OPCODE_TASK_MGMT_RESP + OPCODE_QUERY_REQUEST = 0x16, // OPCODE_QUERY_RESPONSE + OPCODE_NOP_IN = 0x20, + OPCODE_RESPONSE, + OPCODE_DATA_IN, + OPCODE_TASK_MGMT_RESP = 0x24, + OPCODE_READY_TO_TRANSFER = 0x31, + OPCODE_QUERY_RESPONSE = 0x36, + OPCODE_REJECT_UPIU = 0x3F +}; + +struct UPIUHeader { + uint8_t transactionType; + uint8_t flags; + uint8_t lun; + uint8_t taskTag; + uint8_t commandSetType; + uint8_t function; + uint8_t response; + uint8_t status; + uint8_t ehsLength; + uint8_t deviceInfo; + uint16_t dataSegmentLength; +}; + +struct UPIU { + UPIUHeader header; + + UPIU(); + virtual ~UPIU(); + + virtual bool set(uint8_t *, uint32_t); + virtual bool get(uint8_t *, uint32_t); + virtual uint32_t getLength(); +}; + +struct UPIUCommand : public UPIU { + uint32_t expectedDataLength; + uint8_t cdb[16]; + + UPIUCommand(); + ~UPIUCommand(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUResponse : public UPIU { + uint32_t residualCount; + + uint16_t senseLength; + uint8_t senseData[18]; + + UPIUResponse(); + ~UPIUResponse(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUQueryReq : public UPIU { + uint8_t opcode; + uint8_t idn; + uint8_t index; + uint8_t selector; + uint16_t length; + uint32_t val1; + uint32_t val2; + + uint8_t *data; + + UPIUQueryReq(); + ~UPIUQueryReq(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUQueryResp : public UPIU { + uint8_t opcode; + uint8_t idn; + uint8_t index; + uint8_t selector; + uint16_t length; + uint32_t val1; + uint32_t val2; + + uint8_t *data; + + UPIUQueryResp(); + ~UPIUQueryResp(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUDataOut : public UPIU { + uint32_t offset; + uint32_t count; + + uint8_t *data; + + UPIUDataOut(); + ~UPIUDataOut(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUDataIn : public UPIU { + uint32_t offset; + uint32_t count; + + uint8_t *data; + + UPIUDataIn(); + ~UPIUDataIn(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUReadyToTransfer : public UPIU { + uint32_t offset; + uint32_t count; + + UPIUReadyToTransfer(); + ~UPIUReadyToTransfer(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +enum QUERY_OPCODE { + OPCODE_NOP, + OPCODE_READ_DESCRIPTOR, + OPCODE_WRITE_DESCRIPTOR, + OPCODE_READ_ATTRIBUTE, + OPCODE_WRITE_ATTRIBUTE, + OPCODE_READ_FLAG, + OPCODE_SET_FLAG, + OPCODE_CLEAR_FLAG, + OPCODE_TOGGLE_FLAG +}; + +enum DESCRIPTOR_IDN { + IDN_DEVICE, + IDN_CONFIGURATION, + IDN_UNIT, + IDN_INTERCONNECT = 0x04, + IDN_STRING, + IDN_GEOMETRY = 0x07, + IDN_POWER, + IDN_DEVICE_HEALTH +}; + +#define IDN_DEVICE_LENGTH 0x1F // Linux kernel v4.9.30 /driver/scsi/ufs/ufs.h +#define IDN_POWER_LENGTH 0x62 +#define IDN_STRING_LENGTH 0xFE // Linux kernel v4.9.30 /driver/scsi/ufs/ufs.h +#define IDN_UNIT_LENGTH 0x23 + +enum SCSI_COMMAND { + /* SPC-4 */ + CMD_INQUIRY = 0x12, + CMD_MODE_SELECT_10 = 0x55, + CMD_MODE_SENSE_10 = 0x5A, + CMD_REPORT_LUNS = 0xA0, + CMD_REQUEST_SENSE = 0x03, + CMD_SECURITY_PROTOCOL_IN = 0xA2, + CMD_SECURITY_PROTOCOL_OUT = 0xB5, + CMD_SEND_DIAGNOSTIC = 0x1D, + CMD_TEST_UNIT_READY = 0x00, + + /* SBC-3 */ + CMD_FORMAT_UNIT = 0x04, + CMD_PREFETCH_10 = 0x34, + CMD_READ_6 = 0x08, + CMD_READ_10 = 0x28, + CMD_READ_CAPACITY_10 = 0x25, + CMD_READ_CAPACITY_16 = 0x9E, + CMD_START_STOP_UNIT = 0x1B, + CMD_VERIFY_10 = 0x2F, + CMD_WRITE_6 = 0x0A, + CMD_WRITE_10 = 0x2A, + CMD_SYNCHRONIZE_CACHE_10 = 0x35, +}; + +#define SCSI_INQUIRY_LENGTH 36 + +enum WLUN { + WLUN_REPORT_LUNS = 0x01, + WLUN_UFS_DEVICE = 0x50, + WLUN_BOOT = 0x30, + WLUN_RPMB = 0x44, +}; + +/* This is vendor specific */ +enum DEVICE_STRING_INDEX { + STRING_MANUFACTURER, + STRING_PRODUCT_NAME, + STRING_SERIAL_NUMBER, + STRING_OEM_ID, + STRING_PRODUCT_REVISION_LEVEL +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/device.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/device.cc new file mode 100644 index 0000000000..0746ca0a09 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/device.cc @@ -0,0 +1,969 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/ufs/device.hh" + +#include + +#include "hil/ufs/interface.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +struct IOContext { + uint64_t beginAt; + uint32_t slba; + uint32_t nlb; + uint64_t tick; + + uint8_t *buffer; + + uint8_t *prdt; + uint32_t prdtLength; + + DMAFunction func; + void *context; + + IOContext(DMAFunction &f) : beginAt(getTick()), func(f) {} +}; + +LUN::_LUN(bool b, uint8_t n, ConfigReader &cfg) : bWellknown(b), id(n) { + uint8_t wn = bWellknown ? 0x80 : 0x00; + + // Initialize unit descriptor + memset(unitDescriptor, 0, IDN_UNIT_LENGTH); + unitDescriptor[0x00] = IDN_UNIT_LENGTH; + unitDescriptor[0x01] = IDN_UNIT; + unitDescriptor[0x02] = wn | id; // Unit index + unitDescriptor[0x03] = 0x01; // LU enabled + unitDescriptor[0x04] = 0x01; // Boot LUN ID + unitDescriptor[0x05] = 0x00; // Write protect + unitDescriptor[0x06] = 0x00; // Queue depth + unitDescriptor[0x07] = 0x00; // PSA Sensitive + unitDescriptor[0x08] = 0x00; // Memory type + unitDescriptor[0x09] = 0x00; // Data reliability + + if (bWellknown) { + unitDescriptor[0x0A] = 0x00; // LBA size + *(uint64_t *)(unitDescriptor + 0x0B) = 0; // Total logical LBA + *(uint32_t *)(unitDescriptor + 0x13) = 0; // Total LBA in physical block + unitDescriptor[0x17] = 0x00; // Thin provisioning + *(uint64_t *)(unitDescriptor + 0x18) = 0; // Total physical LBA + } + else { + // TODO: Fix this code (duplicated) + uint64_t lbaSize = cfg.readUint(CONFIG_UFS, UFS_LBA_SIZE); + uint64_t blockSize = cfg.readUint(CONFIG_PAL, PAL::NAND_PAGE_SIZE); + uint64_t totalSize = cfg.readUint(CONFIG_PAL, PAL::PAL_CHANNEL); + + blockSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_PAGE); + + totalSize *= cfg.readUint(CONFIG_PAL, PAL::PAL_PACKAGE); + totalSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_DIE); + totalSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_PLANE); + totalSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_BLOCK); + totalSize *= blockSize; + + blockSize *= cfg.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP) + ? cfg.readUint(CONFIG_PAL, PAL::NAND_PLANE) + : 1; + + unitDescriptor[0x0A] = (uint8_t)log2f(lbaSize); // LBA size + *(uint64_t *)(unitDescriptor + 0x0B) = + (totalSize * + (1 - cfg.readFloat(CONFIG_FTL, FTL::FTL_OVERPROVISION_RATIO))) / + lbaSize; // Total logical LBA + *(uint32_t *)(unitDescriptor + 0x13) = + blockSize / lbaSize; // Total LBA in physical block + unitDescriptor[0x17] = 0x00; // Thin provisioning + *(uint64_t *)(unitDescriptor + 0x18) = + totalSize / lbaSize; // Total physical LBA + } + + unitDescriptor[0x20] = 0x00; + unitDescriptor[0x21] = 0x00; // Context capabilityes + unitDescriptor[0x22] = 0x00; // Large unit granuality + + // Initialize INQUIRY structure + memset(inquiry, 0, SCSI_INQUIRY_LENGTH); + inquiry[0] = bWellknown ? 0x1E : 0x00; + inquiry[2] = 0x06; + inquiry[3] = 0x02; + inquiry[4] = 31; + inquiry[7] = 0x02; + + snprintf((char *)inquiry + 8, 24, "SimpleSSD UFS Device"); +} + +Device::Device(DMAInterface *d, ConfigReader &c) + : pDMA(d), + pHIL(nullptr), + pDisk(nullptr), + conf(c), + lunReportLuns(true, WLUN_REPORT_LUNS, c), + lunUFSDevice(true, WLUN_UFS_DEVICE, c), + lunBoot(true, WLUN_BOOT, c), + lunRPMB(true, WLUN_RPMB, c), + lun(false, 0x00, c) { + // Initialize Strings + snprintf((char *)strManufacturer, sizeof(strManufacturer), "CAMELab"); + snprintf((char *)strProductName, sizeof(strProductName), "SimpleSSD UFS Device"); + snprintf((char *)strSerialNumber, sizeof(strSerialNumber), "000000000000"); + snprintf((char *)strOEMID, sizeof(strOEMID), "None"); + snprintf((char *)strProductRevision, sizeof(strProductRevision), "v02.01"); + + // Initialize device descriptor + memset(deviceDescriptor, 0, IDN_DEVICE_LENGTH); + deviceDescriptor[0x00] = IDN_DEVICE_LENGTH; // Length + deviceDescriptor[0x01] = IDN_DEVICE; // Descriptor IDN + deviceDescriptor[0x02] = 0x00; // Device Type + deviceDescriptor[0x03] = 0x00; // UFS Device Class + deviceDescriptor[0x04] = 0x00; // UFS Mass Storage Subclass + deviceDescriptor[0x05] = 0x00; // Protocol supported by UFS Device + deviceDescriptor[0x06] = 0x01; // Number of Logical Units + deviceDescriptor[0x07] = 0x04; // Number of Well known Logical Units + deviceDescriptor[0x08] = 0x01; // Boot Enable + deviceDescriptor[0x09] = 0x00; // Descriptor Access Enable + deviceDescriptor[0x0A] = 0x01; // Initial Power Mode + deviceDescriptor[0x0B] = 0x7F; // High Priority LUN + deviceDescriptor[0x0C] = 0x00; // Secure Removal Type + deviceDescriptor[0x0D] = 0x00; // Support for security LU + deviceDescriptor[0x0E] = 0x00; // Background Operations Termination Latency + deviceDescriptor[0x0F] = 0x00; // Initial Active ICC Level + deviceDescriptor[0x10] = 0x10; + deviceDescriptor[0x11] = 0x02; // UFS Version 2.1 + deviceDescriptor[0x12] = 0x00; + deviceDescriptor[0x13] = 0x00; // Manufacturing Date + deviceDescriptor[0x14] = STRING_MANUFACTURER; + deviceDescriptor[0x15] = STRING_PRODUCT_NAME; + deviceDescriptor[0x16] = STRING_SERIAL_NUMBER; + deviceDescriptor[0x17] = STRING_OEM_ID; + deviceDescriptor[0x18] = 0x00; + deviceDescriptor[0x19] = 0x00; // Manufacturer ID + deviceDescriptor[0x1A] = 0x10; // Unit Descriptor 0 Base Offset + deviceDescriptor[0x1B] = 0x10; // Unit Descriptor Config Parameter Length + deviceDescriptor[0x1C] = 0x02; // RTT Capability of device + deviceDescriptor[0x1D] = 0x00; + deviceDescriptor[0x1E] = 0x00; + // deviceDescriptor[0x1F] = 0x00; // UFS Features Support + // deviceDescriptor[0x20] = 0x00; // Field Firmware Update Timeout + // deviceDescriptor[0x21] = 0x20; // Queue Depth + // deviceDescriptor[0x22] = 0x00; + // deviceDescriptor[0x23] = 0x00; // Device version + // deviceDescriptor[0x24] = 0x00; // Number of Secure Write Protection Areas + // deviceDescriptor[0x25] = 0x00; + // deviceDescriptor[0x26] = 0x00; + // deviceDescriptor[0x27] = 0x00; + // deviceDescriptor[0x28] = 0x00; // PSA Maximum Data Size + // deviceDescriptor[0x29] = 0x00; // PSA State Timeout + // deviceDescriptor[0x2A] = STRING_PRODUCT_REVISION_LEVEL; + + // Initialize power descriptor + memset(powerDescriptor, 0, IDN_POWER_LENGTH); + powerDescriptor[0x00] = IDN_POWER_LENGTH; // Length + powerDescriptor[0x01] = IDN_POWER; // Descriptor IDN + *(uint16_t *)(powerDescriptor + 0x02) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x04) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x06) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x08) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x0A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x0C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x0E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x10) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x12) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x14) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x16) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x18) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x1A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x1C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x1E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x20) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x22) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x24) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x26) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x28) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x2A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x2C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x2E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x30) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x32) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x34) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x36) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x38) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x3A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x3C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x3E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x40) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x42) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x44) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x46) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x48) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x4A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x4C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x4E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x50) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x52) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x54) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x56) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x58) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x5A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x5C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x5E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x60) = 0x0100; + + // Create HIL + pHIL = new HIL(c); + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + // Create Disk + if (conf.readBoolean(CONFIG_UFS, UFS_ENABLE_DISK_IMAGE)) { + uint64_t diskSize; + uint64_t expected; + + expected = totalLogicalPages * logicalPageSize; + + if (conf.readBoolean(CONFIG_UFS, UFS_USE_COW_DISK)) { + pDisk = new CoWDisk(); + } + else { + pDisk = new Disk(); + } + + std::string filename = conf.readString(CONFIG_UFS, UFS_DISK_IMAGE_PATH); + + diskSize = pDisk->open(filename, expected, + conf.readUint(CONFIG_UFS, UFS_LBA_SIZE)); + + if (diskSize == 0) { + panic("Failed to open disk image"); + } + else if (diskSize != expected) { + if (conf.readBoolean(CONFIG_UFS, UFS_STRICT_DISK_SIZE)) { + panic("Disk size not match"); + } + } + } + + // Set cache info + bReadCache = conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_READ_CACHE); + bWriteCache = conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE); + + // DMA Handler for PRDT + dmaHandler = [](uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + delete pContext; + } + }; +} + +Device::~Device() { + delete pHIL; + delete pDisk; +} + +void Device::processQueryCommand(UPIUQueryReq *req, UPIUQueryResp *resp) { + resp->opcode = req->opcode; + resp->idn = req->idn; + resp->index = req->index; + resp->selector = req->selector; + resp->length = req->length; + + debugprint( + LOG_HIL_UFS, + "COMMAND | UPIU Query Request | OPCODE %d | IDN %d | LUN 0x%X | Tag " + "0x%X", + req->opcode, req->idn, req->header.lun, req->header.taskTag); + + switch (req->opcode) { + case OPCODE_NOP: + break; + case OPCODE_READ_DESCRIPTOR: { + switch (req->idn) { + case IDN_DEVICE: + resp->header.dataSegmentLength = req->length; + resp->length = IDN_DEVICE_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + memcpy(resp->data, deviceDescriptor, req->length); + break; + case IDN_UNIT: { + uint8_t *buffer = nullptr; + + switch (req->header.lun) { + case 0x80 | WLUN_REPORT_LUNS: + buffer = lunReportLuns.unitDescriptor; + break; + case 0x80 | WLUN_UFS_DEVICE: + buffer = lunUFSDevice.unitDescriptor; + break; + case 0x80 | WLUN_BOOT: + buffer = lunBoot.unitDescriptor; + break; + case 0x80 | WLUN_RPMB: + buffer = lunRPMB.unitDescriptor; + break; + case 0x00: + buffer = lun.unitDescriptor; + break; + default: + warn("Unknown LUN 0x%2X", req->header.lun); + } + + resp->header.dataSegmentLength = req->length; + resp->length = IDN_UNIT_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + + if (buffer) { + memcpy(resp->data, buffer, req->length); + } + } break; + case IDN_POWER: + resp->header.dataSegmentLength = req->length; + resp->length = IDN_POWER_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + memcpy(resp->data, powerDescriptor, req->length); + break; + case IDN_STRING: { + resp->header.dataSegmentLength = req->length; + resp->length = IDN_STRING_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + + resp->data[0] = IDN_STRING_LENGTH; + resp->data[1] = IDN_STRING; + + switch (req->index) { + case STRING_MANUFACTURER: + memcpy(resp->data + 2, strManufacturer, req->length - 2); + break; + case STRING_PRODUCT_NAME: + memcpy(resp->data + 2, strProductName, req->length - 2); + break; + case STRING_SERIAL_NUMBER: + memcpy(resp->data + 2, strSerialNumber, req->length - 2); + break; + case STRING_OEM_ID: + memcpy(resp->data + 2, strOEMID, req->length - 2); + break; + case STRING_PRODUCT_REVISION_LEVEL: + memcpy(resp->data + 2, strProductRevision, req->length - 2); + break; + default: + warn("Unknown string index %#x", req->index); + + break; + } + } break; + default: + warn("Not implemented descriptor idn %#x", req->idn); + + break; + } + } break; + default: + warn("Not implemented query opcode %#x", req->opcode); + + break; + } +} + +void Device::processCommand(UTP_TRANSFER_CMD cmd, UPIUCommand *req, + UPIUResponse *resp, uint8_t *prdt, + uint32_t prdtLength, DMAFunction &func, + void *context) { + static uint64_t lbaSize = conf.readUint(CONFIG_UFS, UFS_LBA_SIZE); + bool immediate = true; + uint8_t *buffer = nullptr; + uint64_t length = 0; + + resp->header.lun = req->header.lun; + + // debugprint(LOG_HIL_UFS, "COMMAND | UPIU Command | CT %d", + // cmd); + + // TODO: Check LUN for I/O + + switch (cmd) { + case CMD_SCSI: { + uint8_t opcode = req->cdb[0]; + uint32_t slba = 0; + uint16_t nlb = 0; + + debugprint(LOG_HIL_UFS, + "COMMAND | SCSI Command 0x%X | LUN 0x%X | Tag 0x%X", opcode, + req->header.lun, req->header.taskTag); + + switch (opcode) { + case CMD_INQUIRY: { + buffer = nullptr; + + switch (req->header.lun) { + case 0x80 | WLUN_REPORT_LUNS: + buffer = lunReportLuns.inquiry; + break; + case 0x80 | WLUN_UFS_DEVICE: + buffer = lunUFSDevice.inquiry; + break; + case 0x80 | WLUN_BOOT: + buffer = lunBoot.inquiry; + break; + case 0x80 | WLUN_RPMB: + buffer = lunRPMB.inquiry; + break; + case 0x00: + buffer = lun.inquiry; + break; + default: + warn("Unknown LUN 0x%2X", req->header.lun); + } + + if (buffer) { + prdtWrite(prdt, prdtLength, 36, buffer, func, context); + immediate = false; + } + } break; + case CMD_MODE_SELECT_10: + // Not Implemented + break; + case CMD_MODE_SENSE_10: { + uint32_t size = 0; + + switch (req->cdb[2] & 0x3F) { + case 0x0A: { + size = 20; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x12; // Length + + buffer[8] = 0x0A; // Control Page + buffer[9] = 0x0A; // Length + } break; + case 0x01: { + size = 20; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x12; // Length + + buffer[8] = 0x01; // Recovery Page + buffer[9] = 0x0A; // Length + } break; + case 0x08: { + size = 28; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x1A; // Length + + buffer[8] = 0x08; // Caching Page + buffer[9] = 0x12; // Length + buffer[10] = 0x00; + + buffer[10] |= bReadCache ? 0x00 : 0x01; // Set RCD + buffer[10] |= bWriteCache ? 0x04 : 0x00; // Set WCE + } break; + case 0x3F: { + size = 52; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x32; // Length + + buffer[8] = 0x01; // Recovery Page + buffer[9] = 0x0A; // Length + buffer[20] = 0x0A; // Control Page + buffer[21] = 0x0A; // Length + buffer[32] = 0x08; // Caching Page + buffer[33] = 0x12; // Length + buffer[34] = 0x00; + + buffer[34] |= bReadCache ? 0x00 : 0x01; // Set RCD + buffer[34] |= bWriteCache ? 0x04 : 0x00; // Set WCE + } break; + default: + warn("Not implemented mode page %#x", req->cdb[2] & 0x3F); + buffer = nullptr; + break; + } + + length = size; + } break; + case CMD_READ_6: { + slba = (((uint64_t)(req->cdb[1]) & 0x1F) << 16) | + ((uint64_t)req->cdb[2] << 8) | req->cdb[3]; + nlb = req->cdb[4] == 0 ? 256 : req->cdb[4]; + } break; + case CMD_READ_10: { + // bool fua = req->cdb[1] & 0x08; + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + } break; + case CMD_READ_CAPACITY_10: { + uint32_t temp; + // TODO: fill appropriate value for lba count + buffer = (uint8_t *)calloc(8, 1); + + temp = + (uint32_t)((totalLogicalPages * logicalPageSize / lbaSize) - 1); + temp = __builtin_bswap32(temp); + memcpy(buffer, &temp, 4); + + temp = lbaSize; + temp = __builtin_bswap32(temp); + memcpy(buffer + 4, &temp, 4); + + length = 8; + } break; + case CMD_READ_CAPACITY_16: { + uint32_t temp32; + uint64_t temp64; + + buffer = (uint8_t *)calloc(32, 1); + + temp64 = (totalLogicalPages * logicalPageSize) / lbaSize - 1; + temp64 = __builtin_bswap64(temp64); + memcpy(buffer, &temp64, 8); + + temp32 = lbaSize; + temp32 = __builtin_bswap32(temp32); + memcpy(buffer + 8, &temp32, 4); + + length = 32; + } break; + case CMD_START_STOP_UNIT: + // Just response + break; + case CMD_TEST_UNIT_READY: + // Just response + break; + case CMD_REPORT_LUNS: { + uint8_t sel = req->cdb[2]; + + buffer = (uint8_t *)calloc(40, 1); + + if (sel == 0) { + // Return one LUN + buffer[3] = 8; // 8 bytes in Big Endian + } + else if (sel == 1) { + // Return three LUN + buffer[3] = 24; + buffer[8] = 0xC1; + buffer[9] = WLUN_REPORT_LUNS; + buffer[16] = 0xC1; + buffer[17] = WLUN_UFS_DEVICE; + buffer[24] = 0xC1; + buffer[25] = WLUN_BOOT; + } + else if (sel == 2) { + // Return four LUN + buffer[3] = 32; + buffer[8] = 0xC1; + buffer[9] = WLUN_REPORT_LUNS; + buffer[16] = 0xC1; + buffer[17] = WLUN_UFS_DEVICE; + buffer[24] = 0xC1; + buffer[25] = WLUN_BOOT; + } + else { + warn("Unknown select report field %#x", sel); + } + + length = 40; + } break; + case CMD_VERIFY_10: { + uint32_t slba; + uint16_t nlb; + + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + + if (slba + nlb > totalLogicalPages * logicalPageSize) { + resp->header.status = 0x0; // Check condition + // Fill sense data + // TODO: modulize this error sense part + resp->header.dataSegmentLength = 20; + resp->senseLength = 18; + resp->senseData[0] = 0x70; + resp->senseData[2] = 0x05; // Illegal Request + resp->senseData[7] = 0x0A; + } + } break; + case CMD_WRITE_6: { + slba = (((uint64_t)(req->cdb[1]) & 0x1F) << 16) | + ((uint64_t)req->cdb[2] << 8) | req->cdb[3]; + nlb = req->cdb[4] == 0 ? 256 : req->cdb[4]; + } break; + case CMD_WRITE_10: { + // bool fua = req->cdb[1] & 0x08; + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + } break; + case CMD_REQUEST_SENSE: + case CMD_FORMAT_UNIT: + case CMD_PREFETCH_10: + case CMD_SECURITY_PROTOCOL_IN: + case CMD_SECURITY_PROTOCOL_OUT: + case CMD_SEND_DIAGNOSTIC: + // Not implemented + break; + case CMD_SYNCHRONIZE_CACHE_10: { + bool immed = req->cdb[1] & 0x10; + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + + if (immed) { + static DMAFunction dummy = [](uint64_t, void *) {}; + + flush(dummy, nullptr); + } + else { + flush(func, context); + + immediate = false; + } + } break; + default: + warn("Not implemented SCSI command %#x", opcode); + break; + } + + if (opcode == CMD_READ_10 || opcode == CMD_READ_6) { + if (nlb > 0) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | READ | %d + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->func(tick, pContext->context); + + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | READ | %d + %d | NAND %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + prdtWrite(pContext->prdt, pContext->prdtLength, + pContext->nlb * lbaSize, pContext->buffer, doWrite, + context); + }; + + IOContext *pContext = new IOContext(func); + + pContext->buffer = (uint8_t *)calloc(nlb * lbaSize, 1); + pContext->context = context; + pContext->slba = slba; + pContext->nlb = nlb; + pContext->prdt = prdt; + pContext->prdtLength = prdtLength; + + debugprint(LOG_HIL_UFS, "NVM | READ | %d + %d", pContext->slba, + pContext->nlb); + + read(slba, nlb, pContext->buffer, doRead, pContext); + + immediate = false; + } + } + else if (opcode == CMD_WRITE_10 || opcode == CMD_WRITE_6) { + if (nlb > 0) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | WRITE | %d + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->func(tick, pContext->context); + + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | WRITE | %d + %d | DMA %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + write(pContext->slba, pContext->nlb, pContext->buffer, doWrite, + context); + }; + + IOContext *pContext = new IOContext(func); + + pContext->buffer = (uint8_t *)calloc(nlb * lbaSize, 1); + pContext->context = context; + pContext->slba = slba; + pContext->nlb = nlb; + + debugprint(LOG_HIL_UFS, "NVM | WRITE | %d + %d", pContext->slba, + pContext->nlb); + + prdtRead(prdt, prdtLength, nlb * lbaSize, pContext->buffer, doRead, + pContext); + + immediate = false; + } + } + else if (opcode == CMD_MODE_SENSE_10 || opcode == CMD_READ_CAPACITY_10 || + opcode == CMD_READ_CAPACITY_16 || opcode == CMD_REPORT_LUNS) { + if (buffer) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->func(tick, pContext->context); + + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = new IOContext(func); + pContext->buffer = buffer; + pContext->context = context; + + prdtWrite(prdt, prdtLength, length, buffer, doWrite, pContext); + + immediate = false; + } + } + + if (immediate) { + func(getTick(), context); + } + } break; + case CMD_NATIVE_UFS_COMMAND: + // Not used in UFS v2.1 + break; + case CMD_DEVICE_MGMT_FUNCTION: + // Should processed in processQueryCommand + warn("Device management function on UPIU Command is not " + "defined operation"); + break; + } +} + +void Device::prdtRead(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doRead = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t read = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - read); + + pContext->counter++; + pDMA->dmaRead(table[idx].dataAddress, size, buffer + read, dmaHandler, + context); + + read += size; + + if (read >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::UFS__DEVICE, CPU::PRDT_READ, doRead, pContext); +} + +void Device::prdtWrite(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doWrite = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t written = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - written); + + pContext->counter++; + pDMA->dmaWrite(table[idx].dataAddress, size, buffer + written, dmaHandler, + context); + + written += size; + + if (written >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::UFS__DEVICE, CPU::PRDT_WRITE, doWrite, pContext); +} + +void Device::convertUnit(uint64_t slba, uint64_t nlblk, Request &req) { + static uint64_t lbaSize = conf.readUint(CONFIG_UFS, UFS_LBA_SIZE); + uint32_t lbaratio = logicalPageSize / lbaSize; + uint64_t slpn; + uint64_t nlp; + uint64_t off; + + slpn = slba / lbaratio; + off = slba % lbaratio; + nlp = (nlblk + off + lbaratio - 1) / lbaratio; + + req.range.slpn = slpn; + req.range.nlp = nlp; + req.offset = off * lbaSize; + req.length = nlblk * lbaSize; +} + +void Device::read(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doRead = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->read(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->read(slba, nlb, buffer); + } + + execute(CPU::UFS__DEVICE, CPU::READ, doRead, req); +} + +void Device::write(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doWrite = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->write(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->write(slba, nlb, buffer); + } + + execute(CPU::UFS__DEVICE, CPU::WRITE, doWrite, req); +} + +void Device::flush(DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doFlush = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->flush(*req); + + delete req; + }; + + req->range.slpn = 0; + req->range.nlp = totalLogicalPages; + req->offset = 0; + req->length = totalLogicalPages * logicalPageSize; + + execute(CPU::UFS__DEVICE, CPU::FLUSH, doFlush, req); +} + +void Device::getStatList(std::vector &list, std::string prefix) { + pHIL->getStatList(list, prefix); +} + +void Device::getStatValues(std::vector &values) { + pHIL->getStatValues(values); +} + +void Device::resetStatValues() { + pHIL->resetStatValues(); +} + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/device.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/device.hh new file mode 100644 index 0000000000..ef9ba9a3b8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/device.hh @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_DEVICE__ +#define __HIL_UFS_DEVICE__ + +#include + +#include "hil/hil.hh" +#include "hil/ufs/config.hh" +#include "hil/ufs/def.hh" +#include "hil/ufs/host.hh" +#include "util/disk.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +typedef struct _LUN { + bool bWellknown; + uint8_t id; + + uint8_t unitDescriptor[IDN_UNIT_LENGTH]; + uint8_t inquiry[SCSI_INQUIRY_LENGTH]; + + _LUN(bool, uint8_t, ConfigReader &); +} LUN; + +class Device : public StatObject { + private: + DMAInterface *pDMA; + HIL *pHIL; + Disk *pDisk; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + + ConfigReader &conf; + + // Cache info + bool bReadCache; + bool bWriteCache; + + // Well-known LUNs + LUN lunReportLuns; + LUN lunUFSDevice; + LUN lunBoot; + LUN lunRPMB; + + // LUN + LUN lun; + + // Descriptors + uint8_t deviceDescriptor[IDN_DEVICE_LENGTH]; + uint8_t powerDescriptor[IDN_POWER_LENGTH]; + + uint8_t strManufacturer[IDN_STRING_LENGTH - 2]; + uint8_t strProductName[IDN_STRING_LENGTH - 2]; + uint8_t strSerialNumber[IDN_STRING_LENGTH - 2]; + uint8_t strOEMID[IDN_STRING_LENGTH - 2]; + uint8_t strProductRevision[IDN_STRING_LENGTH - 2]; + + // PRDT + DMAFunction dmaHandler; + + void prdtRead(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void * = nullptr); + void prdtWrite(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void * = nullptr); + + // IO + void convertUnit(uint64_t, uint64_t, Request &); + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void flush(DMAFunction &, void *); + + public: + Device(DMAInterface *, ConfigReader &); + ~Device(); + + void processQueryCommand(UPIUQueryReq *, UPIUQueryResp *); + void processCommand(UTP_TRANSFER_CMD, UPIUCommand *, UPIUResponse *, + uint8_t *, uint32_t, DMAFunction &, void * = nullptr); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/host.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/host.cc new file mode 100644 index 0000000000..2d35a89305 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/host.cc @@ -0,0 +1,658 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/ufs/host.hh" + +#include "hil/ufs/device.hh" +#include "util/algorithm.hh" +#include "util/fifo.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +struct RequestContext { + uint32_t bitMask; + uint32_t index; + UTPTransferReqDesc transferReqDesc; +}; + +Host::Host(Interface *i, ConfigReader &c) + : pInterface(i), + conf(c), + requestCounter(0), + lastWorkAt(0), + pendingInterrupt(0) { + ARM::AXI::BUS_WIDTH hostBusWidth; + uint64_t hostBusClock; + + // Get AXI setting + hostBusWidth = + (ARM::AXI::BUS_WIDTH)conf.readInt(CONFIG_UFS, UFS_HOST_AXI_BUS_WIDTH); + hostBusClock = conf.readUint(CONFIG_UFS, UFS_HOST_AXI_CLOCK); + + FIFOParam fifoParam; + + fifoParam.rqSize = 8192; + fifoParam.wqSize = 8192; + fifoParam.transferUnit = 2048; + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + axiFIFO = new FIFO(pInterface, fifoParam); + + // Calculate AXI Stream bus width/speed for M-PHY layer + auto mode = (MIPI::M_PHY::M_PHY_MODE)conf.readInt(CONFIG_UFS, UFS_MPHY_MODE); + uint8_t lane = (uint8_t)conf.readUint(CONFIG_UFS, UFS_MPHY_LANE); + + // Assume maximum 2 lanes + switch (mode) { + case MIPI::M_PHY::HS_G1: // 1.248 Gbps + case MIPI::M_PHY::HS_G2: // 2.496 Gbps + case MIPI::M_PHY::HS_G3: // 4.992 Gbps + hostBusWidth = ARM::AXI::BUS_64BIT; + hostBusClock = 200000000; // 64Bit @ 200MHz -> 1.6GB/s + + break; + case MIPI::M_PHY::HS_G4: // 9.984 Gbps + hostBusWidth = ARM::AXI::BUS_128BIT; + hostBusClock = 200000000; // 128Bit @ 200MHz -> 3.2GB/s + + break; + default: // Suppress warning + break; + } + + fifoParam.latency = [mode, lane](uint64_t size) -> uint64_t { + return MIPI::M_PHY::calculateDelay(mode, lane, size); + }; + + mphyFIFO = new FIFO(axiFIFO, fifoParam); + + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + deviceFIFO = new FIFO(mphyFIFO, fifoParam); + + pDevice = new Device(deviceFIFO, c); + + // Initialize registers + register_table.cap = 0x0707001F; + register_table.version = 0x00010000; + register_table.hcddid = 0xAA003C3C; + register_table.hcpmid = 0x41524D48; + register_table.hcs = 0x00000008; + + memset(&stat, 0, sizeof(stat)); + + // Allocate events + workEvent = allocate([this](uint64_t) { work(); }); + requestEvent = allocate([this](uint64_t) { handleRequest(); }); + completionEvent = allocate([this](uint64_t) { completion(); }); + + maxRequest = conf.readUint(CONFIG_UFS, UFS_MAX_REQUEST_COUNT); + workInterval = conf.readUint(CONFIG_UFS, UFS_WORK_INTERVAL); + requestInterval = workInterval / maxRequest; +} + +Host::~Host() { + delete pDevice; + delete deviceFIFO; + delete mphyFIFO; + delete axiFIFO; +} + +void Host::processUIC() { + uint8_t opcode = register_table.uiccmdr & 0xFF; + + register_table.ucmdarg2 = ERR_SUCCESS; + + debugprint(LOG_HIL_UFS, + "COMMAND | UIC Command | CMD %08X | ARGS %08X, %08X, %08X", + register_table.uiccmdr, register_table.ucmdarg1, + register_table.ucmdarg2, register_table.ucmdarg3); + + switch (opcode) { + case DME_LINKSTARTUP: + register_table.hcs |= 0x0F; + + schedule(workEvent, getTick() + workInterval); + + break; + case DME_GET: + if (register_table.ucmdarg1 == MAKE_UICARG(MIB_VS_POWERSTATE, 0)) { + register_table.ucmdarg3 = UFSHCD_LINK_IS_UP; + } + + break; + default: + // Do Nothing + break; + } + + register_table.is |= UIC_COMMAND_COMPL; + + pInterface->generateInterrupt(); + + register_table.uiccmdr = 0; + + stat.uicCommand++; +} + +void Host::processUTPTask() { + // Not Implemented + panic("UTP Task is not implemented"); +} + +void Host::processUTPTransfer(uint64_t) { + uint32_t bit = 0; + + for (int i = 0; i < 32; i++) { + bit = 1 << i; + + if ((register_table.utrldbr & bit) && !(pendingInterrupt & bit)) { + pendingInterrupt |= bit; + + lRequestQueue.push(i); + } + } +} + +void Host::processUTPCommand(UTPTransferReqDesc &req, UTP_TRANSFER_CMD cmd, + DMAFunction &func, void *context) { + struct UTPCommandContext { + uint8_t *transferReq; + uint8_t *transferResp; + uint8_t *prdt; + UPIU *transferReqUPIU; + UPIU *transferRespUPIU; + + bool reqDone; + bool respDone; + bool prdtDone; + + uint64_t base; + uint32_t offUPIUResp; + uint32_t sizeUPIUResp; + + UTP_TRANSFER_CMD cmd; + + DMAFunction func; + void *context; + + UTPCommandContext(DMAFunction &f, void *c) + : transferReq(nullptr), + transferResp(nullptr), + prdt(nullptr), + reqDone(false), + respDone(false), + prdtDone(false), + func(f), + context(c) {} + }; + + uint32_t offPRDT = req.prdtOffset * 4; + uint32_t sizePRDT = req.prdtLength * sizeof(PRDT); + + UTPCommandContext *commandContext = new UTPCommandContext(func, context); + + DMAFunction doRequest = [this](uint64_t now, void *context) { + DMAFunction done = [this](uint64_t, void *context) { + DMAFunction doWrite = [](uint64_t now, void *context) { + auto pContext = (UTPCommandContext *)context; + auto pResult = (RequestContext *)pContext->context; + + // debugprint(LOG_HIL_UFS, + // "COMMAND | UPIU Transfer Response | TT 0x%X", + // transferRespUPIU->header.transactionType); + + // Write status to DW2 + pResult->transferReqDesc.dw2 = 0; + + // Cleanup + free(pContext->transferReq); + free(pContext->transferResp); + if (pContext->prdt) { + free(pContext->prdt); + } + + delete pContext->transferReqUPIU; + delete pContext->transferRespUPIU; + + pContext->func(now, pContext->context); + + delete pContext; + }; + + auto pContext = (UTPCommandContext *)context; + + // Transfer response + pContext->transferRespUPIU->header.taskTag = + pContext->transferReqUPIU->header.taskTag; + pContext->transferRespUPIU->get(pContext->transferResp, + pContext->sizeUPIUResp); + axiFIFO->dmaWrite(pContext->base + pContext->offUPIUResp, + pContext->sizeUPIUResp, pContext->transferResp, doWrite, + context); + }; + + auto pContext = (UTPCommandContext *)context; + auto pResult = (RequestContext *)pContext->context; + + // Create Request UPIU structure + uint8_t reqType = pContext->transferReq[0] & 0x3F; + pContext->transferReqUPIU = getUPIU((UPIU_OPCODE)reqType); + pContext->transferReqUPIU->set(pContext->transferReq, + pContext->offUPIUResp); + + // debugprint(LOG_HIL_UFS, + // "COMMAND | UPIU Transfer Request | TT 0x%X", reqType); + + // Process + switch (reqType) { + case OPCODE_NOP_OUT: + pContext->transferRespUPIU = getUPIU(OPCODE_NOP_IN); + + done(now, context); + + break; + case OPCODE_QUERY_REQUEST: + pContext->transferRespUPIU = getUPIU(OPCODE_QUERY_RESPONSE); + pDevice->processQueryCommand( + (UPIUQueryReq *)pContext->transferReqUPIU, + (UPIUQueryResp *)pContext->transferRespUPIU); + + execute(CPU::UFS__DEVICE, CPU::PROCESS_QUERY_COMMAND, done, context); + + break; + case OPCODE_COMMAND: + pContext->transferRespUPIU = getUPIU(OPCODE_RESPONSE); + + { + CPUContext *pCPU = new CPUContext(done, context, CPU::UFS__DEVICE, + CPU::PROCESS_COMMAND); + + pDevice->processCommand( + pContext->cmd, (UPIUCommand *)pContext->transferReqUPIU, + (UPIUResponse *)pContext->transferRespUPIU, pContext->prdt, + pResult->transferReqDesc.prdtLength, cpuHandler, pCPU); + } + + break; + default: + panic("Unapplicable UPIU command type"); + + break; + } + }; + DMAFunction doReqRead = [doRequest](uint64_t now, void *context) { + auto pContext = (UTPCommandContext *)context; + + pContext->reqDone = true; + + if (pContext->prdtDone) { + doRequest(now, context); + } + }; + + commandContext->offUPIUResp = req.respUPIUOffset * 4; + commandContext->sizeUPIUResp = req.respUPIULength * 4; + commandContext->cmd = cmd; + + // Retrive UTP Command Descriptor + commandContext->base = ((uint64_t)req.cmdAddressUpper << 32) | req.cmdAddress; + commandContext->transferReq = + (uint8_t *)calloc(commandContext->offUPIUResp, 1); + commandContext->transferResp = + (uint8_t *)calloc(commandContext->sizeUPIUResp, 1); + + axiFIFO->dmaRead(commandContext->base, commandContext->offUPIUResp, + commandContext->transferReq, doReqRead, commandContext); + + if (req.prdtLength > 0) { + DMAFunction doPRDTRead = [doRequest](uint64_t now, void *context) { + auto pContext = (UTPCommandContext *)context; + + pContext->prdtDone = true; + + if (pContext->reqDone) { + doRequest(now, context); + } + }; + + commandContext->prdt = (uint8_t *)calloc(sizePRDT, 1); + + axiFIFO->dmaRead(commandContext->base + offPRDT, sizePRDT, + commandContext->prdt, doPRDTRead, commandContext); + } + else { + commandContext->prdtDone = true; + } +} + +UPIU *Host::getUPIU(UPIU_OPCODE code) { + switch (code) { + case OPCODE_COMMAND: + return new UPIUCommand(); + case OPCODE_DATA_OUT: + return new UPIUDataOut(); + case OPCODE_QUERY_REQUEST: + return new UPIUQueryReq(); + case OPCODE_RESPONSE: + return new UPIUResponse(); + case OPCODE_DATA_IN: + return new UPIUDataIn(); + case OPCODE_READY_TO_TRANSFER: + return new UPIUReadyToTransfer(); + case OPCODE_QUERY_RESPONSE: + return new UPIUQueryResp(); + default: + break; + } + + UPIU *ret = new UPIU(); + ret->header.transactionType = code; + + return ret; +} + +void Host::readRegister(uint32_t offset, uint32_t &data) { + for (uint32_t i = 0; i < 4; i++) { + if (offset + i < 0xB0) { + data |= register_table.data[offset + i] << (i * 8); + } + } + + // debugprint(LOG_HIL_UFS, + // "REG | READ | Offset 0x%02X | Data %08X", offset, + // data); +} + +void Host::writeRegister(uint32_t offset, uint32_t data, uint64_t tick) { + // debugprint(LOG_HIL_UFS, + // "REG | WRITE | Offset 0x%02X | Data %08X", offset, + // data); + + switch (offset) { + case REG_IS: + register_table.is &= (~data) & 0x00030FFF; + + pInterface->clearInterrupt(); + + break; + case REG_IE: + register_table.ie &= 0x00000FFF; + register_table.ie |= data & 0x00030FFF; // Spec differs with Linux kernel + + break; + case REG_HCS: + register_table.hcs &= (~data) & 0x00000030; + register_table.hcs |= data & 0x00000700; + + break; + case REG_HCE: + register_table.hce = data & 0x00000001; + + break; + case REG_UTRIACR: + register_table.utriacr = data & 0x81111FFF; + + break; + case REG_UTRLBA: + register_table.utrlba &= 0xFFFFFFFF00000000; + register_table.utrlba |= data & 0xFFFFFC00; + + break; + case REG_UTRLBAU: + register_table.utrlba &= 0xFFFFFFFF; + register_table.utrlba |= (uint64_t)data << 32; + + break; + case REG_UTRLDBR: + register_table.utrldbr |= data; + + processUTPTransfer(tick); + + break; + case REG_UTRLCLR: + register_table.utrlclr = data; + // TODO: abort command + + break; + case REG_UTRLRSR: + register_table.utrlrsr = data & 0x00000001; + + break; + case REG_UTMRLBA: + register_table.utmrlba &= 0xFFFFFFFF00000000; + register_table.utmrlba |= data & 0xFFFFFC00; + + break; + case REG_UTMRLBAU: + register_table.utmrlba &= 0xFFFFFFFF; + register_table.utmrlba |= (uint64_t)data << 32; + + break; + case REG_UTMRLDBR: + register_table.utmrldbr |= data; + + processUTPTask(); + + break; + case REG_UTMRLCLR: + register_table.utmrlclr = data; + // TODO: abort command + + break; + case REG_UTMRLRSR: + register_table.utmrlrsr = data & 0x00000001; + + break; + case REG_UICCMDR: + register_table.uiccmdr = data & 0x000000FF; + + processUIC(); + + break; + case REG_UCMDARG1: + register_table.ucmdarg1 = data; + + break; + case REG_UCMDARG2: + register_table.ucmdarg2 = data; + + break; + case REG_UCMDARG3: + register_table.ucmdarg3 = data; + + break; + default: + warn("Write to read only register 0x%X", offset); + + break; + } +} + +void Host::completion() { + uint32_t count = 0; + uint64_t tick = getTick(); + bool intr = false; + + while (lResponseQueue.size() > 0) { + auto &iter = lResponseQueue.top(); + + if (iter.finishedAt <= tick) { + intr = true; + + // Clear doorbell + register_table.utrldbr &= ~iter.bitmask; + pendingInterrupt &= ~iter.bitmask; + + // Remove entry + lResponseQueue.pop(); + count++; + } + else { + break; + } + } + + if (intr) { + debugprint(LOG_HIL_UFS, "INTR | Completing %u requests", count); + + // Set Interrupt Status + register_table.is |= UTP_TRANSFER_REQ_COMPL; + + // Post interrupt + pInterface->generateInterrupt(); + } + + // Schedule for next interrupt + if (lResponseQueue.size() > 0) { + schedule(completionEvent, lResponseQueue.top().finishedAt); + } +} + +void Host::work() { + lastWorkAt = getTick(); + + // Queue is already collected. Just call handleRequest + handleRequest(); +} + +void Host::handleRequest() { + uint64_t tick = getTick(); + + if (lRequestQueue.size() > 0) { + RequestContext *reqContext = new RequestContext(); + reqContext->index = lRequestQueue.front(); + reqContext->bitMask = 1 << reqContext->index; + + lRequestQueue.pop(); + + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction doRequest = [this](uint64_t, void *context) { + DMAFunction doWrite = [this](uint64_t now, void *context) { + auto *pContext = (RequestContext *)context; + + // Schedule interrupt + lResponseQueue.push( + Completion(now, pContext->bitMask, + pContext->transferReqDesc.dw0 & 0x01000000)); + schedule(completionEvent, lResponseQueue.top().finishedAt); + + stat.utpCommand++; + + delete pContext; + }; + + auto *pContext = (RequestContext *)context; + + // Write result to descriptor (DW2) + uint64_t start = register_table.utrlba + + UTP_TRANSFER_REQ_DESC_SIZE * pContext->index; + + axiFIFO->dmaWrite(start, UTP_TRANSFER_REQ_DESC_SIZE, + pContext->transferReqDesc.data, doWrite, context); + }; + + auto *pContext = (RequestContext *)context; + + // Parse and process each commands + uint8_t ct = pContext->transferReqDesc.dw0 >> 28; + + debugprint(LOG_HIL_UFS, + "COMMAND | UTP Transfer Request | Entry %d | CT %d", + pContext->index, ct); + + switch (ct) { + case CMD_SCSI: + case CMD_NATIVE_UFS_COMMAND: + case CMD_DEVICE_MGMT_FUNCTION: + processUTPCommand(pContext->transferReqDesc, (UTP_TRANSFER_CMD)ct, + doRequest, context); + + break; + default: + panic("Undefined UTP Transfer command type %#x", ct); + + break; + } + }; + + // We have data at slot i + uint64_t start = + register_table.utrlba + UTP_TRANSFER_REQ_DESC_SIZE * reqContext->index; + + // Read description + axiFIFO->dmaRead(start, UTP_TRANSFER_REQ_DESC_SIZE, + reqContext->transferReqDesc.data, doRead, reqContext); + + requestCounter++; + } + + if (lRequestQueue.size() > 0 && requestCounter < maxRequest) { + schedule(requestEvent, tick + requestInterval); + } + else { + schedule(workEvent, MAX(tick + requestInterval, lastWorkAt + workInterval)); + } +} + +UFSHCIRegister &Host::getRegisterTable() { + return register_table; +} + +void Host::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "uic_count"; + temp.desc = "Total UIC Command handled"; + list.push_back(temp); + + temp.name = prefix + "utp_transfer_count"; + temp.desc = "Total UTP Transfer Command handled"; + list.push_back(temp); + + pDevice->getStatList(list, prefix); +} + +void Host::getStatValues(std::vector &values) { + values.push_back(stat.uicCommand); + values.push_back(stat.utpCommand); + + pDevice->getStatValues(values); +} + +void Host::resetStatValues() { + memset(&stat, 0, sizeof(stat)); + + pDevice->resetStatValues(); +} + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/host.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/host.hh new file mode 100644 index 0000000000..1e4c861564 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/host.hh @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_HOST__ +#define __HIL_UFS_HOST__ + +#include +#include +#include + +#include "hil/ufs/def.hh" +#include "hil/ufs/interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +class Device; + +typedef struct _Completion { + bool interruptEnable; + uint32_t bitmask; + uint64_t finishedAt; + + _Completion() : interruptEnable(false), bitmask(0), finishedAt(0) {} + + _Completion(uint64_t t, uint32_t b, bool i) + : interruptEnable(i), bitmask(b), finishedAt(t) {} + + bool operator()(const _Completion &a, const _Completion &b) { + return a.finishedAt > b.finishedAt; + } +} Completion; + +class Host : public StatObject { + private: + Interface *pInterface; + Device *pDevice; + + ConfigReader &conf; + + DMAInterface *axiFIFO; + DMAInterface *mphyFIFO; + DMAInterface *deviceFIFO; + + Event workEvent; + Event requestEvent; + Event completionEvent; + uint64_t workInterval; + uint64_t requestInterval; + uint64_t maxRequest; + uint64_t requestCounter; + uint64_t lastWorkAt; + + UFSHCIRegister register_table; + uint32_t pendingInterrupt; + + std::queue lRequestQueue; + std::priority_queue, Completion> + lResponseQueue; + + struct { + uint64_t uicCommand; + uint64_t utpCommand; + } stat; + + void processUIC(); + void processUTPTask(); + void processUTPTransfer(uint64_t); + + void processUTPCommand(UTPTransferReqDesc &, UTP_TRANSFER_CMD, DMAFunction &, + void * = nullptr); + + UPIU *getUPIU(UPIU_OPCODE); + + public: + Host(Interface *, ConfigReader &); + ~Host(); + + // For Interface + void readRegister(uint32_t, uint32_t &); + void writeRegister(uint32_t, uint32_t, uint64_t); + + void completion(); + void handleRequest(); + void work(); + + UFSHCIRegister &getRegisterTable(); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/interface.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/interface.hh new file mode 100644 index 0000000000..a9d6531ae8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/hil/ufs/interface.hh @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_INTERFACE__ +#define __HIL_UFS_INTERFACE__ + +#include + +#include "sim/dma_interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +class Host; + +class Interface : public SimpleSSD::DMAInterface { + protected: + Host *pController; + + public: + virtual void generateInterrupt() = 0; + virtual void clearInterrupt() = 0; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/abstract_cache.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/abstract_cache.cc new file mode 100644 index 0000000000..c5047498f4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/abstract_cache.cc @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/abstract_cache.hh" + +namespace SimpleSSD { + +namespace ICL { + +Line::_Line() + : tag(0), lastAccessed(0), insertedAt(0), dirty(false), valid(false) {} + +Line::_Line(uint64_t t, bool d) + : tag(t), lastAccessed(0), insertedAt(0), dirty(d), valid(true) {} + +AbstractCache::AbstractCache(ConfigReader &c, FTL::FTL *f, + DRAM::AbstractDRAM *d) + : conf(c), pFTL(f), pDRAM(d) {} + +AbstractCache::~AbstractCache() {} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/abstract_cache.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/abstract_cache.hh new file mode 100644 index 0000000000..31cd08935a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/abstract_cache.hh @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_CACHE__ +#define __ICL_CACHE__ + +#include "dram/abstract_dram.hh" +#include "ftl/ftl.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace ICL { + +typedef struct _Line { + uint64_t tag; + uint64_t lastAccessed; + uint64_t insertedAt; + bool dirty; + bool valid; + + _Line(); + _Line(uint64_t, bool); +} Line; + +class AbstractCache : public StatObject { + protected: + ConfigReader &conf; + FTL::FTL *pFTL; + DRAM::AbstractDRAM *pDRAM; + + public: + AbstractCache(ConfigReader &, FTL::FTL *, DRAM::AbstractDRAM *); + virtual ~AbstractCache(); + + virtual bool read(Request &, uint64_t &) = 0; + virtual bool write(Request &, uint64_t &) = 0; + + virtual void flush(LPNRange &, uint64_t &) = 0; + virtual void trim(LPNRange &, uint64_t &) = 0; + virtual void format(LPNRange &, uint64_t &) = 0; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/config.cc new file mode 100644 index 0000000000..3f199acc97 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/config.cc @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace ICL { + +const char NAME_USE_READ_CACHE[] = "EnableReadCache"; +const char NAME_USE_WRITE_CACHE[] = "EnableWriteCache"; +const char NAME_USE_READ_PREFETCH[] = "EnableReadPrefetch"; +const char NAME_EVICT_POLICY[] = "EvictPolicy"; +const char NAME_EVICT_MODE[] = "EvictMode"; +const char NAME_CACHE_SIZE[] = "CacheSize"; +const char NAME_WAY_SIZE[] = "CacheWaySize"; +const char NAME_PREFETCH_COUNT[] = "ReadPrefetchCount"; +const char NAME_PREFETCH_RATIO[] = "ReadPrefetchRatio"; +const char NAME_PREFETCH_MODE[] = "ReadPrefetchMode"; +const char NAME_CACHE_LATENCY[] = "CacheLatency"; + +Config::Config() { + readCaching = false; + writeCaching = true; + readPrefetch = false; + evictPolicy = POLICY_LEAST_RECENTLY_USED; + cacheSize = 33554432; + cacheWaySize = 1; + prefetchCount = 1; + prefetchRatio = 0.5; + prefetchMode = MODE_ALL; + evictMode = MODE_ALL; + cacheLatency = 10; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_USE_READ_CACHE)) { + readCaching = convertBool(value); + } + else if (MATCH_NAME(NAME_USE_WRITE_CACHE)) { + writeCaching = convertBool(value); + } + else if (MATCH_NAME(NAME_USE_READ_PREFETCH)) { + readPrefetch = convertBool(value); + } + else if (MATCH_NAME(NAME_PREFETCH_COUNT)) { + prefetchCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PREFETCH_RATIO)) { + prefetchRatio = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_EVICT_POLICY)) { + evictPolicy = (EVICT_POLICY)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_EVICT_MODE)) { + evictMode = (EVICT_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CACHE_SIZE)) { + cacheSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WAY_SIZE)) { + cacheWaySize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PREFETCH_MODE)) { + prefetchMode = (PREFETCH_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CACHE_LATENCY)) { + cacheLatency = strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (prefetchCount == 0) { + panic("Invalid ReadPrefetchCount"); + } + if (prefetchRatio <= 0.f) { + panic("Invalid ReadPrefetchRatio"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case ICL_EVICT_POLICY: + ret = evictPolicy; + break; + case ICL_PREFETCH_GRANULARITY: + ret = prefetchMode; + break; + case ICL_EVICT_GRANULARITY: + ret = evictMode; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case ICL_CACHE_SIZE: + ret = cacheSize; + break; + case ICL_WAY_SIZE: + ret = cacheWaySize; + break; + case ICL_PREFETCH_COUNT: + ret = prefetchCount; + break; + case ICL_CACHE_LATENCY: + ret = cacheLatency; + break; + } + + return ret; +} + +float Config::readFloat(uint32_t idx) { + float ret = 0.f; + + switch (idx) { + case ICL_PREFETCH_RATIO: + ret = prefetchRatio; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case ICL_USE_READ_CACHE: + ret = readCaching; + break; + case ICL_USE_WRITE_CACHE: + ret = writeCaching; + break; + case ICL_USE_READ_PREFETCH: + ret = readPrefetch; + break; + } + + return ret; +} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/config.hh new file mode 100644 index 0000000000..7ff581310f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/config.hh @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_CONFIG__ +#define __ICL_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace ICL { + +typedef enum { + /* Cache config */ + ICL_USE_READ_CACHE, + ICL_USE_WRITE_CACHE, + ICL_USE_READ_PREFETCH, + ICL_PREFETCH_COUNT, + ICL_PREFETCH_RATIO, + ICL_PREFETCH_GRANULARITY, + ICL_EVICT_POLICY, + ICL_EVICT_GRANULARITY, + ICL_CACHE_SIZE, + ICL_WAY_SIZE, + ICL_CACHE_LATENCY, +} ICL_CONFIG; + +typedef enum { + POLICY_RANDOM, //!< Select way in random + POLICY_FIFO, //!< Select way that lastly inserted + POLICY_LEAST_RECENTLY_USED, //!< Select way that least recently used +} EVICT_POLICY; + +typedef enum { + MODE_SUPERPAGE, //!< Read one page from one super block (super page) + MODE_ALL, //!< Read one page from all NAND flashes +} PREFETCH_MODE; + +typedef PREFETCH_MODE EVICT_MODE; + +class Config : public BaseConfig { + private: + bool readCaching; //!< Default: false + bool writeCaching; //!< Default: true + bool readPrefetch; //!< Default: false + EVICT_POLICY evictPolicy; //!< Default: POLICY_LEAST_RECENTLY_USED + uint64_t cacheWaySize; //!< Default: 1 + uint64_t cacheSize; //!< Default: 33554432 (32MiB) + uint64_t prefetchCount; //!< Default: 1 + float prefetchRatio; //!< Default: 0.5 + PREFETCH_MODE prefetchMode; //!< Default: MODE_ALL + EVICT_MODE evictMode; //!< Default: MODE_ALL + uint64_t cacheLatency; //!< Default: + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + float readFloat(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/generic_cache.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/generic_cache.cc new file mode 100644 index 0000000000..805e335bf1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/generic_cache.cc @@ -0,0 +1,877 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/generic_cache.hh" + +#include +#include +#include + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace ICL { + +GenericCache::GenericCache(ConfigReader &c, FTL::FTL *f, DRAM::AbstractDRAM *d) + : AbstractCache(c, f, d), + superPageSize(f->getInfo()->pageSize), + parallelIO(f->getInfo()->pageCountToMaxPerf), + lineCountInSuperPage(f->getInfo()->ioUnitInPage), + lineCountInMaxIO(parallelIO * lineCountInSuperPage), + waySize(conf.readUint(CONFIG_ICL, ICL_WAY_SIZE)), + prefetchIOCount(conf.readUint(CONFIG_ICL, ICL_PREFETCH_COUNT)), + prefetchIORatio(conf.readFloat(CONFIG_ICL, ICL_PREFETCH_RATIO)), + useReadCaching(conf.readBoolean(CONFIG_ICL, ICL_USE_READ_CACHE)), + useWriteCaching(conf.readBoolean(CONFIG_ICL, ICL_USE_WRITE_CACHE)), + useReadPrefetch(conf.readBoolean(CONFIG_ICL, ICL_USE_READ_PREFETCH)), + gen(rd()), + dist(std::uniform_int_distribution(0, waySize - 1)) { + uint64_t cacheSize = conf.readUint(CONFIG_ICL, ICL_CACHE_SIZE); + + lineSize = superPageSize / lineCountInSuperPage; + + if (lineSize != superPageSize) { + bSuperPage = true; + } + + if (!conf.readBoolean(CONFIG_FTL, FTL::FTL_USE_RANDOM_IO_TWEAK)) { + lineSize = superPageSize; + lineCountInSuperPage = 1; + lineCountInMaxIO = parallelIO; + } + + if (!useReadCaching && !useWriteCaching) { + return; + } + + // Fully-associated? + if (waySize == 0) { + setSize = 1; + waySize = MAX(cacheSize / lineSize, 1); + } + else { + setSize = MAX(cacheSize / lineSize / waySize, 1); + } + + debugprint( + LOG_ICL_GENERIC_CACHE, + "CREATE | Set size %u | Way size %u | Line size %u | Capacity %" PRIu64, + setSize, waySize, lineSize, (uint64_t)setSize * waySize * lineSize); + debugprint(LOG_ICL_GENERIC_CACHE, + "CREATE | line count in super page %u | line count in max I/O %u", + lineCountInSuperPage, lineCountInMaxIO); + + cacheData.resize(setSize); + + for (uint32_t i = 0; i < setSize; i++) { + cacheData[i] = new Line[waySize](); + } + + evictData.resize(lineCountInSuperPage); + + for (uint32_t i = 0; i < lineCountInSuperPage; i++) { + evictData[i] = (Line **)calloc(parallelIO, sizeof(Line *)); + } + + prefetchTrigger = std::numeric_limits::max(); + + evictMode = (EVICT_MODE)conf.readInt(CONFIG_ICL, ICL_EVICT_GRANULARITY); + prefetchMode = + (PREFETCH_MODE)conf.readInt(CONFIG_ICL, ICL_PREFETCH_GRANULARITY); + + // Set evict policy functional + policy = (EVICT_POLICY)conf.readInt(CONFIG_ICL, ICL_EVICT_POLICY); + + switch (policy) { + case POLICY_RANDOM: + evictFunction = [this](uint32_t, uint64_t &) -> uint32_t { + return dist(gen); + }; + compareFunction = [this](Line *a, Line *b) -> Line * { + if (a && b) { + return dist(gen) > waySize / 2 ? a : b; + } + else if (a || b) { + return a ? a : b; + } + else { + return nullptr; + } + }; + + break; + case POLICY_FIFO: + evictFunction = [this](uint32_t setIdx, uint64_t &tick) -> uint32_t { + uint32_t wayIdx = 0; + uint64_t min = std::numeric_limits::max(); + + for (uint32_t i = 0; i < waySize; i++) { + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, i, offsetof(Line, insertedAt)), + // 8, tick); + + if (cacheData[setIdx][i].insertedAt < min) { + min = cacheData[setIdx][i].insertedAt; + wayIdx = i; + } + } + + return wayIdx; + }; + compareFunction = [](Line *a, Line *b) -> Line * { + if (a && b) { + if (a->insertedAt < b->insertedAt) { + return a; + } + else { + return b; + } + } + else if (a || b) { + return a ? a : b; + } + else { + return nullptr; + } + }; + + break; + case POLICY_LEAST_RECENTLY_USED: + evictFunction = [this](uint32_t setIdx, uint64_t &tick) -> uint32_t { + uint32_t wayIdx = 0; + uint64_t min = std::numeric_limits::max(); + + for (uint32_t i = 0; i < waySize; i++) { + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, i, offsetof(Line, + // lastAccessed)), 8, tick); + + if (cacheData[setIdx][i].lastAccessed < min) { + min = cacheData[setIdx][i].lastAccessed; + wayIdx = i; + } + } + + return wayIdx; + }; + compareFunction = [](Line *a, Line *b) -> Line * { + if (a && b) { + if (a->lastAccessed < b->lastAccessed) { + return a; + } + else { + return b; + } + } + else if (a || b) { + return a ? a : b; + } + else { + return nullptr; + } + }; + + break; + default: + panic("Undefined cache evict policy"); + + break; + } + + memset(&stat, 0, sizeof(stat)); +} + +GenericCache::~GenericCache() { + if (!useReadCaching && !useWriteCaching) { + return; + } + + for (uint32_t i = 0; i < setSize; i++) { + delete[] cacheData[i]; + } + + for (uint32_t i = 0; i < lineCountInSuperPage; i++) { + free(evictData[i]); + } +} + +uint64_t GenericCache::getCacheLatency() { + static uint64_t latency = conf.readUint(CONFIG_ICL, ICL_CACHE_LATENCY); + static uint64_t core = conf.readUint(CONFIG_CPU, CPU::CPU_CORE_ICL); + + return (core == 0) ? 0 : latency / core; +} + +uint32_t GenericCache::calcSetIndex(uint64_t lca) { + return lca % setSize; +} + +void GenericCache::calcIOPosition(uint64_t lca, uint32_t &row, uint32_t &col) { + uint32_t tmp = lca % lineCountInMaxIO; + + row = tmp % lineCountInSuperPage; + col = tmp / lineCountInSuperPage; +} + +uint32_t GenericCache::getEmptyWay(uint32_t setIdx, uint64_t &tick) { + uint32_t retIdx = waySize; + uint64_t minInsertedAt = std::numeric_limits::max(); + + for (uint32_t wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + if (!line.valid) { + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, wayIdx, offsetof(Line, insertedAt)), + // 8, tick); + + if (minInsertedAt > line.insertedAt) { + minInsertedAt = line.insertedAt; + retIdx = wayIdx; + } + } + } + + return retIdx; +} + +uint32_t GenericCache::getValidWay(uint64_t lca, uint64_t &tick) { + uint32_t setIdx = calcSetIndex(lca); + uint32_t wayIdx; + + for (wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, wayIdx, offsetof(Line, tag)), 8, + // tick); + + if (line.valid && line.tag == lca) { + break; + } + } + + return wayIdx; +} + +void GenericCache::checkSequential(Request &req, SequentialDetect &data) { + if (data.lastRequest.reqID == req.reqID) { + data.lastRequest.range = req.range; + data.lastRequest.offset = req.offset; + data.lastRequest.length = req.length; + + return; + } + + if (data.lastRequest.range.slpn * lineSize + data.lastRequest.offset + + data.lastRequest.length == + req.range.slpn * lineSize + req.offset) { + if (!data.enabled) { + data.hitCounter++; + data.accessCounter += data.lastRequest.offset + data.lastRequest.length; + + if (data.hitCounter >= prefetchIOCount && + (float)data.accessCounter / superPageSize >= prefetchIORatio) { + data.enabled = true; + } + } + } + else { + data.enabled = false; + data.hitCounter = 0; + data.accessCounter = 0; + } + + data.lastRequest = req; +} + +void GenericCache::evictCache(uint64_t tick, bool flush) { + FTL::Request reqInternal(lineCountInSuperPage); + uint64_t beginAt; + uint64_t finishedAt = tick; + + debugprint(LOG_ICL_GENERIC_CACHE, "----- | Begin eviction"); + + for (uint32_t row = 0; row < lineCountInSuperPage; row++) { + for (uint32_t col = 0; col < parallelIO; col++) { + beginAt = tick; + + if (evictData[row][col] == nullptr) { + continue; + } + + if (evictData[row][col]->valid && evictData[row][col]->dirty) { + reqInternal.lpn = evictData[row][col]->tag / lineCountInSuperPage; + reqInternal.ioFlag.reset(); + reqInternal.ioFlag.set(row); + + pFTL->write(reqInternal, beginAt); + } + + if (flush) { + evictData[row][col]->valid = false; + evictData[row][col]->tag = 0; + } + + evictData[row][col]->insertedAt = beginAt; + evictData[row][col]->lastAccessed = beginAt; + evictData[row][col]->dirty = false; + evictData[row][col] = nullptr; + + finishedAt = MAX(finishedAt, beginAt); + } + } + + debugprint(LOG_ICL_GENERIC_CACHE, + "----- | End eviction | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + tick, finishedAt, finishedAt - tick); +} + +// True when hit +bool GenericCache::read(Request &req, uint64_t &tick) { + bool ret = false; + + debugprint(LOG_ICL_GENERIC_CACHE, + "READ | REQ %7u-%-4u | LCA %" PRIu64 " | SIZE %" PRIu64, + req.reqID, req.reqSubID, req.range.slpn, req.length); + + if (useReadCaching) { + uint32_t setIdx = calcSetIndex(req.range.slpn); + uint32_t wayIdx; + uint64_t arrived = tick; + + if (useReadPrefetch) { + checkSequential(req, readDetect); + } + + wayIdx = getValidWay(req.range.slpn, tick); + + // Do we have valid data? + if (wayIdx != waySize) { + uint64_t tickBackup = tick; + + // Wait cache to be valid + if (tick < cacheData[setIdx][wayIdx].insertedAt) { + tick = cacheData[setIdx][wayIdx].insertedAt; + } + + // Update last accessed time + cacheData[setIdx][wayIdx].lastAccessed = tick; + + // DRAM access + pDRAM->read(&cacheData[setIdx][wayIdx], req.length, tick); + + debugprint(LOG_ICL_GENERIC_CACHE, + "READ | Cache hit at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + setIdx, wayIdx, arrived, tick, tick - arrived); + + ret = true; + + // Do we need to prefetch data? + if (useReadPrefetch && req.range.slpn == prefetchTrigger) { + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Prefetch triggered"); + + req.range.slpn = lastPrefetched; + + // Backup tick + arrived = tick; + tick = tickBackup; + + goto ICL_GENERIC_CACHE_READ; + } + } + // We should read data from NVM + else { + ICL_GENERIC_CACHE_READ: + FTL::Request reqInternal(lineCountInSuperPage, req); + std::vector> readList; + uint32_t row, col; // Variable for I/O position (IOFlag) + uint64_t dramAt; + uint64_t beginLCA, endLCA; + uint64_t beginAt, finishedAt = tick; + + if (readDetect.enabled) { + // TEMP: Disable DRAM calculation for prevent conflict + pDRAM->setScheduling(false); + + if (!ret) { + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Read ahead triggered"); + } + + beginLCA = req.range.slpn; + + // If super-page is disabled, just read all pages from all planes + if (prefetchMode == MODE_ALL || !bSuperPage) { + endLCA = beginLCA + lineCountInMaxIO; + prefetchTrigger = beginLCA + lineCountInMaxIO / 2; + } + else { + endLCA = beginLCA + lineCountInSuperPage; + prefetchTrigger = beginLCA + lineCountInSuperPage / 2; + } + + lastPrefetched = endLCA; + } + else { + beginLCA = req.range.slpn; + endLCA = beginLCA + 1; + } + + for (uint64_t lca = beginLCA; lca < endLCA; lca++) { + beginAt = tick; + + // Check cache + if (getValidWay(lca, beginAt) != waySize) { + continue; + } + + // Find way to write data read from NVM + setIdx = calcSetIndex(lca); + wayIdx = getEmptyWay(setIdx, beginAt); + + if (wayIdx == waySize) { + wayIdx = evictFunction(setIdx, beginAt); + + if (cacheData[setIdx][wayIdx].dirty) { + // We need to evict data before write + calcIOPosition(cacheData[setIdx][wayIdx].tag, row, col); + evictData[row][col] = cacheData[setIdx] + wayIdx; + } + } + + cacheData[setIdx][wayIdx].insertedAt = beginAt; + cacheData[setIdx][wayIdx].lastAccessed = beginAt; + cacheData[setIdx][wayIdx].valid = true; + cacheData[setIdx][wayIdx].dirty = false; + + readList.push_back({lca, ((uint64_t)setIdx << 32) | wayIdx}); + + finishedAt = MAX(finishedAt, beginAt); + } + + tick = finishedAt; + + evictCache(tick); + + for (auto &iter : readList) { + Line *pLine = &cacheData[iter.second >> 32][iter.second & 0xFFFFFFFF]; + + // Read data + reqInternal.lpn = iter.first / lineCountInSuperPage; + reqInternal.ioFlag.reset(); + reqInternal.ioFlag.set(iter.first % lineCountInSuperPage); + + beginAt = tick; // Ignore cache metadata access + + // If superPageSizeData is true, read first LPN only + pFTL->read(reqInternal, beginAt); + + // DRAM delay + dramAt = pLine->insertedAt; + pDRAM->write(pLine, lineSize, dramAt); + + // Set cache data + beginAt = MAX(beginAt, dramAt); + + pLine->insertedAt = beginAt; + pLine->lastAccessed = beginAt; + pLine->tag = iter.first; + + if (pLine->tag == req.range.slpn) { + finishedAt = beginAt; + } + + debugprint(LOG_ICL_GENERIC_CACHE, + "READ | Cache miss at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + iter.second >> 32, iter.second & 0xFFFFFFFF, tick, beginAt, + beginAt - tick); + } + + tick = finishedAt; + + if (readDetect.enabled) { + if (ret) { + // This request was prefetch + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Prefetch done"); + + // Restore tick + tick = arrived; + } + else { + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Read ahead done"); + } + + // TEMP: Restore + pDRAM->setScheduling(true); + } + } + + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::READ); + } + else { + FTL::Request reqInternal(lineCountInSuperPage, req); + + pDRAM->write(nullptr, req.length, tick); + + pFTL->read(reqInternal, tick); + } + + stat.request[0]++; + + if (ret) { + stat.cache[0]++; + } + + return ret; +} + +// True when cold-miss/hit +bool GenericCache::write(Request &req, uint64_t &tick) { + bool ret = false; + uint64_t flash = tick; + bool dirty = false; + + debugprint(LOG_ICL_GENERIC_CACHE, + "WRITE | REQ %7u-%-4u | LCA %" PRIu64 " | SIZE %" PRIu64, + req.reqID, req.reqSubID, req.range.slpn, req.length); + + FTL::Request reqInternal(lineCountInSuperPage, req); + + if (req.length < lineSize) { + dirty = true; + } + else { + pFTL->write(reqInternal, flash); + } + + if (useWriteCaching) { + uint32_t setIdx = calcSetIndex(req.range.slpn); + uint32_t wayIdx; + + wayIdx = getValidWay(req.range.slpn, tick); + + // Can we update old data? + if (wayIdx != waySize) { + uint64_t arrived = tick; + + // Wait cache to be valid + if (tick < cacheData[setIdx][wayIdx].insertedAt) { + tick = cacheData[setIdx][wayIdx].insertedAt; + } + + // TODO: TEMPORAL CODE + // We should only show DRAM latency when cache become dirty + if (dirty) { + // Update last accessed time + cacheData[setIdx][wayIdx].insertedAt = tick; + cacheData[setIdx][wayIdx].lastAccessed = tick; + } + else { + cacheData[setIdx][wayIdx].insertedAt = flash; + cacheData[setIdx][wayIdx].lastAccessed = flash; + } + + // Update last accessed time + cacheData[setIdx][wayIdx].dirty = dirty; + + // DRAM access + pDRAM->write(&cacheData[setIdx][wayIdx], req.length, tick); + + debugprint(LOG_ICL_GENERIC_CACHE, + "WRITE | Cache hit at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + setIdx, wayIdx, arrived, tick, tick - arrived); + + ret = true; + } + else { + uint64_t arrived = tick; + + wayIdx = getEmptyWay(setIdx, tick); + + // Do we have place to write data? + if (wayIdx != waySize) { + // Wait cache to be valid + if (tick < cacheData[setIdx][wayIdx].insertedAt) { + tick = cacheData[setIdx][wayIdx].insertedAt; + } + + // TODO: TEMPORAL CODE + // We should only show DRAM latency when cache become dirty + if (dirty) { + // Update last accessed time + cacheData[setIdx][wayIdx].insertedAt = tick; + cacheData[setIdx][wayIdx].lastAccessed = tick; + } + else { + cacheData[setIdx][wayIdx].insertedAt = flash; + cacheData[setIdx][wayIdx].lastAccessed = flash; + } + + // Update last accessed time + cacheData[setIdx][wayIdx].valid = true; + cacheData[setIdx][wayIdx].dirty = dirty; + cacheData[setIdx][wayIdx].tag = req.range.slpn; + + // DRAM access + pDRAM->write(&cacheData[setIdx][wayIdx], req.length, tick); + + ret = true; + } + // We have to flush + else { + uint32_t row, col; // Variable for I/O position (IOFlag) + uint32_t setToFlush = calcSetIndex(req.range.slpn); + + for (setIdx = 0; setIdx < setSize; setIdx++) { + for (wayIdx = 0; wayIdx < waySize; wayIdx++) { + if (cacheData[setIdx][wayIdx].valid) { + calcIOPosition(cacheData[setIdx][wayIdx].tag, row, col); + + evictData[row][col] = compareFunction(evictData[row][col], + cacheData[setIdx] + wayIdx); + } + } + } + + if (evictMode == MODE_SUPERPAGE) { + uint32_t row, col; // Variable for I/O position (IOFlag) + + for (row = 0; row < lineCountInSuperPage; row++) { + for (col = 0; col < parallelIO - 1; col++) { + evictData[row][col + 1] = + compareFunction(evictData[row][col], evictData[row][col + 1]); + evictData[row][col] = nullptr; + } + } + } + + // We must flush setToFlush set + bool have = false; + + for (row = 0; row < lineCountInSuperPage; row++) { + for (col = 0; col < parallelIO; col++) { + if (evictData[row][col] && + calcSetIndex(evictData[row][col]->tag) == setToFlush) { + have = true; + } + } + } + + // We don't have setToFlush + if (!have) { + Line *pLineToFlush = nullptr; + + for (wayIdx = 0; wayIdx < waySize; wayIdx++) { + if (cacheData[setToFlush][wayIdx].valid) { + pLineToFlush = + compareFunction(pLineToFlush, cacheData[setToFlush] + wayIdx); + } + } + + if (pLineToFlush) { + calcIOPosition(pLineToFlush->tag, row, col); + + evictData[row][col] = pLineToFlush; + } + } + + tick += getCacheLatency() * setSize * waySize * 8; + + evictCache(tick, true); + + // Update cacheline of current request + setIdx = setToFlush; + wayIdx = getEmptyWay(setIdx, tick); + + if (wayIdx == waySize) { + panic("Cache corrupted!"); + } + + // DRAM latency + pDRAM->write(&cacheData[setIdx][wayIdx], req.length, tick); + + // Update cache data + cacheData[setIdx][wayIdx].insertedAt = tick; + cacheData[setIdx][wayIdx].lastAccessed = tick; + cacheData[setIdx][wayIdx].valid = true; + cacheData[setIdx][wayIdx].dirty = true; + cacheData[setIdx][wayIdx].tag = req.range.slpn; + } + + debugprint(LOG_ICL_GENERIC_CACHE, + "WRITE | Cache miss at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + setIdx, wayIdx, arrived, tick, tick - arrived); + } + + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::WRITE); + } + else { + if (dirty) { + pFTL->write(reqInternal, tick); + } + else { + tick = flash; + } + + // TEMP: Disable DRAM calculation for prevent conflict + pDRAM->setScheduling(false); + + pDRAM->read(nullptr, req.length, tick); + + pDRAM->setScheduling(true); + } + + stat.request[1]++; + + if (ret) { + stat.cache[1]++; + } + + return ret; +} + +// True when flushed +void GenericCache::flush(LPNRange &range, uint64_t &tick) { + if (useReadCaching || useWriteCaching) { + uint64_t ftlTick = tick; + uint64_t finishedAt = tick; + FTL::Request reqInternal(lineCountInSuperPage); + + for (uint32_t setIdx = 0; setIdx < setSize; setIdx++) { + for (uint32_t wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + tick += getCacheLatency() * 8; + + if (line.tag >= range.slpn && line.tag < range.slpn + range.nlp) { + if (line.dirty) { + reqInternal.lpn = line.tag / lineCountInSuperPage; + reqInternal.ioFlag.set(line.tag % lineCountInSuperPage); + + ftlTick = tick; + pFTL->write(reqInternal, ftlTick); + finishedAt = MAX(finishedAt, ftlTick); + } + + line.valid = false; + } + } + } + + tick = MAX(tick, finishedAt); + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::FLUSH); + } +} + +// True when hit +void GenericCache::trim(LPNRange &range, uint64_t &tick) { + if (useReadCaching || useWriteCaching) { + uint64_t ftlTick = tick; + uint64_t finishedAt = tick; + FTL::Request reqInternal(lineCountInSuperPage); + + for (uint32_t setIdx = 0; setIdx < setSize; setIdx++) { + for (uint32_t wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + tick += getCacheLatency() * 8; + + if (line.tag >= range.slpn && line.tag < range.slpn + range.nlp) { + reqInternal.lpn = line.tag / lineCountInSuperPage; + reqInternal.ioFlag.set(line.tag % lineCountInSuperPage); + + ftlTick = tick; + pFTL->trim(reqInternal, ftlTick); + finishedAt = MAX(finishedAt, ftlTick); + + line.valid = false; + } + } + } + + tick = MAX(tick, finishedAt); + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::TRIM); + } +} + +void GenericCache::format(LPNRange &range, uint64_t &tick) { + if (useReadCaching || useWriteCaching) { + uint64_t lpn; + uint32_t setIdx; + uint32_t wayIdx; + + for (uint64_t i = 0; i < range.nlp; i++) { + lpn = range.slpn + i; + setIdx = calcSetIndex(lpn); + wayIdx = getValidWay(lpn, tick); + + if (wayIdx != waySize) { + // Invalidate + cacheData[setIdx][wayIdx].valid = false; + } + } + } + + // Convert unit + range.slpn /= lineCountInSuperPage; + range.nlp = (range.nlp - 1) / lineCountInSuperPage + 1; + + pFTL->format(range, tick); + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::FORMAT); +} + +void GenericCache::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "generic_cache.read.request_count"; + temp.desc = "Read request count"; + list.push_back(temp); + + temp.name = prefix + "generic_cache.read.from_cache"; + temp.desc = "Read requests that served from cache"; + list.push_back(temp); + + temp.name = prefix + "generic_cache.write.request_count"; + temp.desc = "Write request count"; + list.push_back(temp); + + temp.name = prefix + "generic_cache.write.to_cache"; + temp.desc = "Write requests that served to cache"; + list.push_back(temp); +} + +void GenericCache::getStatValues(std::vector &values) { + values.push_back(stat.request[0]); + values.push_back(stat.cache[0]); + values.push_back(stat.request[1]); + values.push_back(stat.cache[1]); +} + +void GenericCache::resetStatValues() { + memset(&stat, 0, sizeof(stat)); +} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/generic_cache.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/generic_cache.hh new file mode 100644 index 0000000000..4a73cbde3d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/generic_cache.hh @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_GENERIC_CACHE__ +#define __ICL_GENERIC_CACHE__ + +#include +#include +#include + +#include "icl/abstract_cache.hh" + +namespace SimpleSSD { + +namespace ICL { + +class GenericCache : public AbstractCache { + private: + const uint32_t superPageSize; + const uint32_t parallelIO; + uint32_t lineCountInSuperPage; + uint32_t lineCountInMaxIO; + uint32_t lineSize; + uint32_t setSize; + uint32_t waySize; + + const uint32_t prefetchIOCount; + const float prefetchIORatio; + + const bool useReadCaching; + const bool useWriteCaching; + const bool useReadPrefetch; + + bool bSuperPage; + + struct SequentialDetect { + bool enabled; + Request lastRequest; + uint32_t hitCounter; + uint32_t accessCounter; + + SequentialDetect() : enabled(false), hitCounter(0), accessCounter(0) { + lastRequest.reqID = 1; + } + } readDetect; + + uint64_t prefetchTrigger; + uint64_t lastPrefetched; + + PREFETCH_MODE prefetchMode; + EVICT_MODE evictMode; + EVICT_POLICY policy; + std::function evictFunction; + std::function compareFunction; + std::random_device rd; + std::mt19937 gen; + std::uniform_int_distribution dist; + + std::vector cacheData; + std::vector evictData; + + uint64_t getCacheLatency(); + + uint32_t calcSetIndex(uint64_t); + void calcIOPosition(uint64_t, uint32_t &, uint32_t &); + + uint32_t getEmptyWay(uint32_t, uint64_t &); + uint32_t getValidWay(uint64_t, uint64_t &); + void checkSequential(Request &, SequentialDetect &); + + void evictCache(uint64_t, bool = true); + + // Stats + struct { + uint64_t request[2]; + uint64_t cache[2]; + } stat; + + public: + GenericCache(ConfigReader &, FTL::FTL *, DRAM::AbstractDRAM *); + ~GenericCache(); + + bool read(Request &, uint64_t &) override; + bool write(Request &, uint64_t &) override; + + void flush(LPNRange &, uint64_t &) override; + void trim(LPNRange &, uint64_t &) override; + void format(LPNRange &, uint64_t &) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/icl.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/icl.cc new file mode 100644 index 0000000000..1a7e5c068d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/icl.cc @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/icl.hh" + +#include "dram/simple.hh" +#include "icl/generic_cache.hh" +#include "util/algorithm.hh" +#include "util/def.hh" + +namespace SimpleSSD { + +namespace ICL { + +ICL::ICL(ConfigReader &c) : conf(c) { + switch (conf.readInt(CONFIG_DRAM, DRAM::DRAM_MODEL)) { + case DRAM::SIMPLE_MODEL: + pDRAM = new DRAM::SimpleDRAM(conf); + + break; + default: + panic("Undefined DRAM model"); + + break; + } + + pFTL = new FTL::FTL(conf, pDRAM); + + FTL::Parameter *param = pFTL->getInfo(); + + if (conf.readBoolean(CONFIG_FTL, FTL::FTL_USE_RANDOM_IO_TWEAK)) { + totalLogicalPages = + param->totalLogicalBlocks * param->pagesInBlock * param->ioUnitInPage; + logicalPageSize = param->pageSize / param->ioUnitInPage; + } + else { + totalLogicalPages = param->totalLogicalBlocks * param->pagesInBlock; + logicalPageSize = param->pageSize; + } + + pCache = new GenericCache(conf, pFTL, pDRAM); +} + +ICL::~ICL() { + delete pCache; + delete pFTL; + delete pDRAM; +} + +void ICL::read(Request &req, uint64_t &tick) { + uint64_t beginAt; + uint64_t finishedAt = tick; + uint64_t reqRemain = req.length; + Request reqInternal; + + reqInternal.reqID = req.reqID; + reqInternal.offset = req.offset; + + for (uint64_t i = 0; i < req.range.nlp; i++) { + beginAt = tick; + + reqInternal.reqSubID = i + 1; + reqInternal.range.slpn = req.range.slpn + i; + reqInternal.length = MIN(reqRemain, logicalPageSize - reqInternal.offset); + pCache->read(reqInternal, beginAt); + reqRemain -= reqInternal.length; + reqInternal.offset = 0; + + finishedAt = MAX(finishedAt, beginAt); + } + + debugprint(LOG_ICL, + "READ | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + req.range.slpn, req.range.nlp, tick, finishedAt, + finishedAt - tick); + + tick = finishedAt; + tick += applyLatency(CPU::ICL, CPU::READ); +} + +void ICL::write(Request &req, uint64_t &tick) { + uint64_t beginAt; + uint64_t finishedAt = tick; + uint64_t reqRemain = req.length; + Request reqInternal; + + reqInternal.reqID = req.reqID; + reqInternal.offset = req.offset; + + for (uint64_t i = 0; i < req.range.nlp; i++) { + beginAt = tick; + + reqInternal.reqSubID = i + 1; + reqInternal.range.slpn = req.range.slpn + i; + reqInternal.length = MIN(reqRemain, logicalPageSize - reqInternal.offset); + pCache->write(reqInternal, beginAt); + reqRemain -= reqInternal.length; + reqInternal.offset = 0; + + finishedAt = MAX(finishedAt, beginAt); + } + + debugprint(LOG_ICL, + "WRITE | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + req.range.slpn, req.range.nlp, tick, finishedAt, + finishedAt - tick); + + tick = finishedAt; + tick += applyLatency(CPU::ICL, CPU::WRITE); +} + +void ICL::flush(LPNRange &range, uint64_t &tick) { + uint64_t beginAt = tick; + + pCache->flush(range, tick); + + debugprint(LOG_ICL, + "FLUSH | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + range.slpn, range.nlp, beginAt, tick, tick - beginAt); + + tick += applyLatency(CPU::ICL, CPU::FLUSH); +} + +void ICL::trim(LPNRange &range, uint64_t &tick) { + uint64_t beginAt = tick; + + pCache->trim(range, tick); + + debugprint(LOG_ICL, + "TRIM | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + range.slpn, range.nlp, beginAt, tick, tick - beginAt); + + tick += applyLatency(CPU::ICL, CPU::TRIM); +} + +void ICL::format(LPNRange &range, uint64_t &tick) { + uint64_t beginAt = tick; + + pCache->format(range, tick); + + debugprint(LOG_ICL, + "FORMAT| LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + range.slpn, range.nlp, beginAt, tick, tick - beginAt); + + tick += applyLatency(CPU::ICL, CPU::FORMAT); +} + +void ICL::getLPNInfo(uint64_t &t, uint32_t &s) { + t = totalLogicalPages; + s = logicalPageSize; +} + +uint64_t ICL::getUsedPageCount(uint64_t lcaBegin, uint64_t lcaEnd) { + uint32_t ratio = pFTL->getInfo()->ioUnitInPage; + + return pFTL->getUsedPageCount(lcaBegin / ratio, lcaEnd / ratio) * ratio; +} + +void ICL::getStatList(std::vector &list, std::string prefix) { + pCache->getStatList(list, prefix + "icl."); + pDRAM->getStatList(list, prefix + "dram."); + pFTL->getStatList(list, prefix); +} + +void ICL::getStatValues(std::vector &values) { + pCache->getStatValues(values); + pDRAM->getStatValues(values); + pFTL->getStatValues(values); +} + +void ICL::resetStatValues() { + pCache->resetStatValues(); + pDRAM->resetStatValues(); + pFTL->resetStatValues(); +} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/icl.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/icl.hh new file mode 100644 index 0000000000..91ebc9b36a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/icl/icl.hh @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_ICL__ +#define __ICL_ICL__ + +#include "dram/abstract_dram.hh" +#include "ftl/ftl.hh" +#include "icl/abstract_cache.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace ICL { + +class ICL : public StatObject { + private: + FTL::FTL *pFTL; + DRAM::AbstractDRAM *pDRAM; + + ConfigReader &conf; + AbstractCache *pCache; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + + public: + ICL(ConfigReader &); + ~ICL(); + + void read(Request &, uint64_t &); + void write(Request &, uint64_t &); + + void flush(LPNRange &, uint64_t &); + void trim(LPNRange &, uint64_t &); + void format(LPNRange &, uint64_t &); + + void getLPNInfo(uint64_t &, uint32_t &); + uint64_t getUsedPageCount(uint64_t, uint64_t); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/LICENSE.txt b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/LICENSE.txt new file mode 100644 index 0000000000..cb7ee2d017 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/LICENSE.txt @@ -0,0 +1,27 @@ + +The "inih" library is distributed under the New BSD license: + +Copyright (c) 2009, Ben Hoyt +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Ben Hoyt nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY BEN HOYT ''AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL BEN HOYT BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/ini.c b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/ini.c new file mode 100644 index 0000000000..602908b926 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/ini.c @@ -0,0 +1,244 @@ +/* inih -- simple .INI file parser + +inih is released under the New BSD license (see LICENSE.txt). Go to the project +home page for more info: + +https://github.com/benhoyt/inih + +*/ + +#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS) +#define _CRT_SECURE_NO_WARNINGS +#endif + +#include +#include +#include + +#include "ini.h" + +#if !INI_USE_STACK +#include +#endif + +#define MAX_SECTION 50 +#define MAX_NAME 50 + +/* Used by ini_parse_string() to keep track of string parsing state. */ +typedef struct { + const char* ptr; + size_t num_left; +} ini_parse_string_ctx; + +/* Strip whitespace chars off end of given string, in place. Return s. */ +static char* rstrip(char* s) +{ + char* p = s + strlen(s); + while (p > s && isspace((unsigned char)(*--p))) + *p = '\0'; + return s; +} + +/* Return pointer to first non-whitespace char in given string. */ +static char* lskip(const char* s) +{ + while (*s && isspace((unsigned char)(*s))) + s++; + return (char*)s; +} + +/* Return pointer to first char (of chars) or inline comment in given string, + or pointer to null at end of string if neither found. Inline comment must + be prefixed by a whitespace character to register as a comment. */ +static char* find_chars_or_comment(const char* s, const char* chars) +{ +#if INI_ALLOW_INLINE_COMMENTS + int was_space = 0; + while (*s && (!chars || !strchr(chars, *s)) && + !(was_space && strchr(INI_INLINE_COMMENT_PREFIXES, *s))) { + was_space = isspace((unsigned char)(*s)); + s++; + } +#else + while (*s && (!chars || !strchr(chars, *s))) { + s++; + } +#endif + return (char*)s; +} + +/* Version of strncpy that ensures dest (size bytes) is null-terminated. */ +static char* strncpy0(char* dest, const char* src, size_t size) +{ + strncpy(dest, src, size); + dest[size - 1] = '\0'; + return dest; +} + +/* See documentation in header file. */ +int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler, + void* user) +{ + /* Uses a fair bit of stack (use heap instead if you need to) */ +#if INI_USE_STACK + char line[INI_MAX_LINE]; +#else + char* line; +#endif + char section[MAX_SECTION] = ""; + char prev_name[MAX_NAME] = ""; + + char* start; + char* end; + char* name; + char* value; + int lineno = 0; + int error = 0; + +#if !INI_USE_STACK + line = (char*)malloc(INI_MAX_LINE); + if (!line) { + return -2; + } +#endif + +#if INI_HANDLER_LINENO +#define HANDLER(u, s, n, v) handler(u, s, n, v, lineno) +#else +#define HANDLER(u, s, n, v) handler(u, s, n, v) +#endif + + /* Scan through stream line by line */ + while (reader(line, INI_MAX_LINE, stream) != NULL) { + lineno++; + + start = line; +#if INI_ALLOW_BOM + if (lineno == 1 && (unsigned char)start[0] == 0xEF && + (unsigned char)start[1] == 0xBB && (unsigned char)start[2] == 0xBF) { + start += 3; + } +#endif + start = lskip(rstrip(start)); + + if (*start == ';' || *start == '#') { + /* Per Python configparser, allow both ; and # comments at the + start of a line */ + } +#if INI_ALLOW_MULTILINE + else if (*prev_name && *start && start > line) { + /* Non-blank line with leading whitespace, treat as continuation + of previous name's value (as per Python configparser). */ + if (!HANDLER(user, section, prev_name, start) && !error) + error = lineno; + } +#endif + else if (*start == '[') { + /* A "[section]" line */ + end = find_chars_or_comment(start + 1, "]"); + if (*end == ']') { + *end = '\0'; + strncpy0(section, start + 1, sizeof(section)); + *prev_name = '\0'; + } + else if (!error) { + /* No ']' found on section line */ + error = lineno; + } + } + else if (*start) { + /* Not a comment, must be a name[=:]value pair */ + end = find_chars_or_comment(start, "=:"); + if (*end == '=' || *end == ':') { + *end = '\0'; + name = rstrip(start); + value = end + 1; +#if INI_ALLOW_INLINE_COMMENTS + end = find_chars_or_comment(value, NULL); + if (*end) + *end = '\0'; +#endif + value = lskip(value); + rstrip(value); + + /* Valid name[=:]value pair found, call handler */ + strncpy0(prev_name, name, sizeof(prev_name)); + if (!HANDLER(user, section, name, value) && !error) + error = lineno; + } + else if (!error) { + /* No '=' or ':' found on name[=:]value line */ + error = lineno; + } + } + +#if INI_STOP_ON_FIRST_ERROR + if (error) + break; +#endif + } + +#if !INI_USE_STACK + free(line); +#endif + + return error; +} + +/* See documentation in header file. */ +int ini_parse_file(FILE* file, ini_handler handler, void* user) +{ + return ini_parse_stream((ini_reader)fgets, file, handler, user); +} + +/* See documentation in header file. */ +int ini_parse(const char* filename, ini_handler handler, void* user) +{ + FILE* file; + int error; + + file = fopen(filename, "r"); + if (!file) + return -1; + error = ini_parse_file(file, handler, user); + fclose(file); + return error; +} + +/* An ini_reader function to read the next line from a string buffer. This + is the fgets() equivalent used by ini_parse_string(). */ +static char* ini_reader_string(char* str, int num, void* stream) +{ + ini_parse_string_ctx* ctx = (ini_parse_string_ctx*)stream; + const char* ctx_ptr = ctx->ptr; + size_t ctx_num_left = ctx->num_left; + char* strp = str; + char c; + + if (ctx_num_left == 0 || num < 2) + return NULL; + + while (num > 1 && ctx_num_left != 0) { + c = *ctx_ptr++; + ctx_num_left--; + *strp++ = c; + if (c == '\n') + break; + num--; + } + + *strp = '\0'; + ctx->ptr = ctx_ptr; + ctx->num_left = ctx_num_left; + return str; +} + +/* See documentation in header file. */ +int ini_parse_string(const char* string, ini_handler handler, void* user) +{ + ini_parse_string_ctx ctx; + + ctx.ptr = string; + ctx.num_left = strlen(string); + return ini_parse_stream((ini_reader)ini_reader_string, &ctx, handler, user); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/ini.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/ini.h new file mode 100644 index 0000000000..9e2808123f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/inih/ini.h @@ -0,0 +1,111 @@ +/* inih -- simple .INI file parser + +inih is released under the New BSD license (see LICENSE.txt). Go to the project +home page for more info: + +https://github.com/benhoyt/inih + +Modified by CAMELab + +*/ + +#ifndef __INI_H__ +#define __INI_H__ + +/* Make this header file easier to include in C++ code */ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Nonzero if ini_handler callback should accept lineno parameter. */ +#ifndef INI_HANDLER_LINENO +#define INI_HANDLER_LINENO 0 +#endif + +/* Typedef for prototype of handler function. */ +#if INI_HANDLER_LINENO +typedef int (*ini_handler)(void* user, const char* section, const char* name, + const char* value, int lineno); +#else +typedef int (*ini_handler)(void* user, const char* section, const char* name, + const char* value); +#endif + +/* Typedef for prototype of fgets-style reader function. */ +typedef char* (*ini_reader)(char* str, int num, void* stream); + +/* Parse given INI-style file. May have [section]s, name=value pairs + (whitespace stripped), and comments starting with ';' (semicolon). Section + is "" if name=value pair parsed before any section heading. name:value + pairs are also supported as a concession to Python's configparser. + + For each name=value pair parsed, call handler function with given user + pointer as well as section, name, and value (data only valid for duration + of handler call). Handler should return nonzero on success, zero on error. + + Returns 0 on success, line number of first error on parse error (doesn't + stop on first error), -1 on file open error, or -2 on memory allocation + error (only when INI_USE_STACK is zero). +*/ +int ini_parse(const char* filename, ini_handler handler, void* user); + +/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't + close the file when it's finished -- the caller must do that. */ +int ini_parse_file(FILE* file, ini_handler handler, void* user); + +/* Same as ini_parse(), but takes an ini_reader function pointer instead of + filename. Used for implementing custom or string-based I/O (see also + ini_parse_string). */ +int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler, + void* user); + +/* Same as ini_parse(), but takes a zero-terminated string with the INI data +instead of a file. Useful for parsing INI data from a network socket or +already in memory. */ +int ini_parse_string(const char* string, ini_handler handler, void* user); + +/* Nonzero to allow multi-line value parsing, in the style of Python's + configparser. If allowed, ini_parse() will call the handler with the same + name for each subsequent line parsed. */ +#ifndef INI_ALLOW_MULTILINE +#define INI_ALLOW_MULTILINE 1 +#endif + +/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of + the file. See http://code.google.com/p/inih/issues/detail?id=21 */ +#ifndef INI_ALLOW_BOM +#define INI_ALLOW_BOM 1 +#endif + +/* Nonzero to allow inline comments (with valid inline comment characters + specified by INI_INLINE_COMMENT_PREFIXES). Set to 0 to turn off and match + Python 3.2+ configparser behaviour. */ +#ifndef INI_ALLOW_INLINE_COMMENTS +#define INI_ALLOW_INLINE_COMMENTS 1 +#endif +#ifndef INI_INLINE_COMMENT_PREFIXES +#define INI_INLINE_COMMENT_PREFIXES "#" +#endif + +/* Nonzero to use stack, zero to use heap (malloc/free). */ +#ifndef INI_USE_STACK +#define INI_USE_STACK 1 +#endif + +/* Stop parsing on first error (default is to keep parsing). */ +#ifndef INI_STOP_ON_FIRST_ERROR +#define INI_STOP_ON_FIRST_ERROR 0 +#endif + +/* Maximum line length for any line in INI file. */ +#ifndef INI_MAX_LINE +#define INI_MAX_LINE 200 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __INI_H__ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/.clang-format b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/.clang-format new file mode 100644 index 0000000000..38a9d1af6b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/.clang-format @@ -0,0 +1,27 @@ +# Generated by clang-format v5.0.0 +--- +Language: Cpp +BasedOnStyle: Google +AllowShortFunctionsOnASingleLine: Inline +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakBeforeMultilineStrings: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + BeforeCatch: true + BeforeElse: true + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBraces: Custom +DerivePointerAlignment: false +PointerAlignment: Right +... diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/.gitignore b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/.gitignore new file mode 100644 index 0000000000..86443d979f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/.gitignore @@ -0,0 +1,56 @@ +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app + +# McPAT custom +mcpat +obj_opt/ + +# CMake Specific +CMakeCache.txt +CMakeFiles +CMakeScripts +Testing +Makefile +cmake_install.cmake +install_manifest.txt +compile_commands.json +CTestTestfile.cmake + +# Visual Studio Specific +.vs/ +*.sln +*.db +*.opendb +*.vcproj +*.filters +*.vcxproj +Debug/ +Release/ +x64/ +.vscode/ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/CMakeLists.txt b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/CMakeLists.txt new file mode 100644 index 0000000000..5e60892217 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/CMakeLists.txt @@ -0,0 +1,113 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# Set version and project name +cmake_minimum_required(VERSION 3.10) +project(mcpat) + +# Set output directory +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) + +# Set include directories +include_directories( + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/cacti +) + +# Platform specific settings +if (MSVC) + add_definitions(-D_CRT_SECURE_NO_WARNINGS) + add_compile_options(/wd4819) # Surpress unicode warning + add_compile_options(/wd4305) # Surpress truncation warning + add_compile_options(/wd4800) # Surpress int -> boolean waring + add_compile_options(/wd4129) # Surpress escape warning + add_compile_options(/wd4244) # Surpress conversion warning + add_compile_options(/wd4267) # Surpress conversion warning +else () + if (APPLE) + # macOS doesn't support -rdynamic flag + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS + "-O0 -g ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS + "-O2 ${CMAKE_CXX_FLAGS}") + endif () + else () + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS + "-O0 -g -rdynamic ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS + "-O2 -rdynamic ${CMAKE_CXX_FLAGS}") + endif () + endif () +endif () + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Specify source files +set(SRC_MCPAT_CACTI + cacti/arbiter.cc + cacti/area.cc + cacti/bank.cc + cacti/basic_circuit.cc + cacti/cacti_interface.cc + cacti/component.cc + cacti/crossbar.cc + cacti/decoder.cc + cacti/htree2.cc + cacti/io.cc + cacti/main.cc + cacti/mat.cc + cacti/nuca.cc + cacti/parameter.cc + cacti/powergating.cc + cacti/router.cc + cacti/subarray.cc + cacti/technology.cc + cacti/uca.cc + cacti/Ucache.cc + cacti/wire.cc +) +set(SRC_MCPAT + array.cc + basic_components.cc + core.cc + interconnect.cc + iocontrollers.cc + logic.cc + mcpat.cc + memoryctrl.cc + noc.cc + processor.cc + sharedcache.cc + XML_Parse.cc +) + +# Source group for MSVC +SOURCE_GROUP("Source Files\\" FILES ${SRC_MCPAT}) +SOURCE_GROUP("Source Files\\cacti" FILES ${SRC_MCPAT_CACTI}) + +# Define library +add_library(mcpat STATIC + ${SRC_MCPAT} + ${SRC_MCPAT_CACTI} +) diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz.xml b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz.xml new file mode 100644 index 0000000000..b97ddd97a0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz.xml @@ -0,0 +1,442 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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/dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1.xml @@ -0,0 +1,429 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_DC.xml b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_DC.xml new file mode 100644 index 0000000000..fa068d5189 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_DC.xml @@ -0,0 +1,440 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0000000000..d7b858f28f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Penryn.xml @@ -0,0 +1,446 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Xeon.xml b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Xeon.xml new file mode 100644 index 0000000000..7a16b62d12 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/ProcessorDescriptionFiles/Xeon.xml @@ -0,0 +1,454 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/README b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/README new file mode 100644 index 0000000000..d5473afe41 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/README @@ -0,0 +1,228 @@ + __ __ ____ _ _____ + | \/ | ___| _ \ / \|_ _| + | |\/| |/ __| |_) / _ \ | | + | | | | (__| __/ ___ \| | + |_| |_|\___|_| /_/ \_\_| + +McPAT: (M)ulti(c)ore (P)ower, (A)rea, and (T)iming +Current version 1.3 +================================================== + +* What McPAT is: + + --Architectural integrated power, area, and timing modeling framework, focuses on power and area modeling, with a target clock rate as a design constraint. + -Consider power, area, and timing simultaneously + -Complete power envelope + -Power management techniques + ---Manycore processor modeling framework + -Different cores, uncore, and system (I/O) components + -Holistically modeling across stacks: Technology models from ITRS projections (also supports user defined vdd), processor modeling based on modern processors + ---Flexible, extensible, and high (i.e., architecture) level framework + -A framework for architecture research + -Flexible to make researchers's life easier + Pre-populated micro-architecture configurations (can be changed by experienced users too!) + Multilevel automatic optimization + -Hierarchical modeling framework for easy extension and porting + Standalone for TDP + Paired up with performance simulators (or machine profiling statistics) for fine-grained study + +* What McPAT is NOT + + ---a hardware design EDA platform; nor a performance simulator + -Use RTL/SPICE/...(not McPAT) if focusing on details of complex logic or analog components + Empirical and curve-fitting based modeling for complex logic and analog building blocks (the most practical modeling methodology for high level framework). + Solution1: Users replace those models with in-house models obtained from EDA tools + Solution2: Users contribute their EDA based detailed models back to the community for sharing + -Use performance simulators for performance (McPAT cannot do performance simulations) + ---a restrictive environment + -It is a framework (rather than a black-box tool) + -Its built-in models are for references and for providing methodological examples. + McPAT's built-in model includes simplified assumptions (e.g. unified instruction window for all instruction types) + McPAT provides building blocks so that it is composable + Users should always understand the methodology when using the built-in models or compose their own models. + ---finished! + -There is always room for improvement . . . + -Thanks for the continueous contributing from the user community! + +==================== +For complete documentation of the McPAT, please refer to the following paper, +"McPAT: An Integrated Power, Area, and Timing Modeling + Framework for Multicore and Manycore Architectures", +that appears in MICRO 2009. Please cite the paper, if you use +McPAT in your work. The bibtex entry is provided below for your convenience. + + @inproceedings{mcpat:micro, + author = {Sheng Li and Jung Ho Ahn and Richard D. Strong and Jay B. Brockman and Dean M. Tullsen and Norman P. Jouppi}, + title = "{McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures}", + booktitle = {MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture}, + year = {2009}, + pages = {469--480}, + } + + +How to use the tool? +==================== + +McPAT takes input parameters from an XML-based interface, +then it computes area and peak power of the +Please note that the peak power is the absolute worst case power, +which could be even higher than TDP. + +1. Steps to run McPAT: + -> define the target processor using inorder.xml or OOO.xml + -> run the "mcpat" binary: + ./mcpat -infile <*.xml> -print_level < level of detailed output> + ./mcpat -h (or mcpat --help) will show the quick help message. + +2. Optimization: + McPAT will try its best to satisfy the target clock rate. + When it cannot find a valid solution, it gives out warnings, + while still giving a solution that is closest to the timing + constraints and calculate power based on it. The optimization + will lead to larger power/area numbers for target higher clock + rate. McPAT also provides the option "-opt_for_clk" to turn on + ("-opt_for_clk 1") and off this strict optimization for the + timing constraint. When it is off, McPAT always optimize + component for ED^2P without worrying about meeting the + target clock frequency. By turning it off, the computation time + can be reduced, which suites for situations where target clock rate + is conservative. + +3. Outputs: + McPAT outputs results in a hierarchical manner. Increasing + the "-print_level" will show detailed results inside each + component. For each component, major parts are shown, and associated + pipeline registers/control logic are added up in total area/power of each + components. In general, McPAT does not model the area/overhead of the pad + frame used in a processor die. + +4. How to use the XML interface for McPAT + 4.1 Set up the parameters + Parameters of target designs need to be set in the *.xml file for + entries tagged as "param". McPAT have very detailed parameter settings. + please remove the structure parameter from the file if you want + to use the default values. Otherwise, the parameters in the xml file + will override the default values. + + 4.2 Pass the statistics + There are two options to get the correct stats: a) the performance + simulator can capture all the stats in detail and pass them to McPAT; + b). Performance simulator can only capture partial stats and pass + them to McPAT, while McPAT can reason about the complete stats using + the partial information and the configuration. Therefore, there are + some overlap for the stats. + + 4.3 Interface XML file structures (PLEASE READ!) + The XML is hierarchical from processor level to micro-architecture + level. McPAT support both heterogeneous and homogeneous manycore processors. + + 1). For heterogeneous processor setup, each component (core, NoC, cache, + and etc) must have its own instantiations (core0, core1, ..., coreN). + Each instantiation will have different parameters as well as its stats. + Thus, the XML file must have multiple "instantiation" of each type of + heterogeneous components and the corresponding hetero flags must be set + in the XML file. Then state in the XML should be the stats of "a" instantiation + (e.g. "a" cores). The reported runtime dynamic is of a single instantiation + (e.g. "a" cores). Since the stats for each (e.g. "a" cores) may be different, + we will see a whole list of (e.g. "a" cores) with different dynamic power, + and total power is just a sum of them. + + 2). For homogeneous processors, the same method for heterogeneous can + also be used by treating all homogeneous instantiations as heterogeneous. + However, a preferred approach is to use a single representative for all + the same components (e.g. core0 to represent all cores) and set the + processor to have homogeneous components (e.g. ). Thus, the XML file only has one instantiation to represent + all others with the same architectural parameters. The corresponding homo + flags must be set in the XML file. Then, the stats in the XML should be + the aggregated stats of the sum of all instantiations (e.g. aggregated stats + of all cores). In the final results, McPAT will only report a single + instantiation of each type of component, and the reported runtime dynamic power + is the sum of all instantiations of the same type. This approach can run fast + and use much less memory. + +5. Guide for integrating McPAT into performance simulators and bypassing the XML interface + The detailed work flow of McPAT has two phases: the initialization phase and + the computation phase. Specifically, in order to start the initialization phase a + user specifies static configurations, including parameters at all three levels, + namely, architectural, circuit, and technology levels. During the initialization + phase, McPAT will generate the internal chip representation using the configurations + set by the user. + The computation phase of McPAT is called by McPAT or the performance simulator + during simulation to generate runtime power numbers. Before calling McPAT to + compute runtime power numbers, the performance simulator needs to pass the + statistics, namely, the activity factors of each individual components to McPAT + via the XML interface. + The initialization phase is very time-consuming, since it will repeat many + times until valid configurations are found or the possible configurations are + exhausted. To reduce the overhead, a user can let the simulator to call McPAT + directly for computation phase and only call initialization phase once at the + beginning of simulation. In this case, the XML interface file is bypassed, + please refer to processor.cc to see how the two phases are called. + +6. Sample input files: + This package provide sample XML files for validating target processors. Please find the + enclosed Niagara1.xml (for the Sun Niagara1 processor), Niagara2.xml (for the Sun Niagara2 + processor), Alpha21364.xml (for the Alpha21364 processor), Xeon.xml (for the Intel + Xeon Tulsa processor), and ARM_A9_2GHz.xml (for ARM Cortex A9 hard core 2GHz implementation from + ARM) + +7. Modeling of power management techniques: + McPAT supports both DVS and power-gating. For DVS, users can use default ITRS projected vdd + at each technology node as supply voltage at DVS level 0 (DVS0) or define voltage at DVS0. + For power-gating, McPAT supports both default power-saving virtual supply voltage computed + automatically using technology parameters. Default means using technology (ITRS based) + lowest value for state-retaining power-gating User can also defined voltage for Power-saving states, + as shown in example file of Xeon.xml (search for power_gating_vcc). When using user-defined power-saving + virtual supply voltage, please understand the implications when setting up voltage for different sleep states. + For example, when deep sleep state is used (voltage lower than the technology allowed state retaining supply voltage), + the effects of losing data and cold start effects (beyond the scope of McPAT) must be considered when waking up the architecture. + Power-gating and DVS cannot happen at the same time. Because power-gating happens when circuit is idle, while DVS happens when + circuit blocks are active. + + +==================== +McPAT includes its special version of Cacti (called Cacti-P) based on Cacti6.5 release. The major changes of +the special Cacti, called Cacti-P in this distro, (compared to cacti6.5) include the following new features. +The inclosed Cacti-P can run stand-alone if users want to use these features. + + * CAM and fully associative cache modeling + * Improved leakage power modeling with consideration of device/gate topology + * long channel device for reduce sub-threshold leakage power + * Sleep transistor based power-gating modeling + * gate leakage power + * Support user defined voltage supply (Vdd) + * Dynamic voltage scaling (DVS) + +For complete documentation of Cacti-P, please refer to the following paper, +"CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques", +that appeared in ICCAD2011. Please cite the paper, if you use +Cacti-P in your work. The bibtex entry is provided below for your convenience. + +@inproceedings{cacti-p:iccad, + author = {Sheng Li and Ke Chen and Jung Ho Ahn and Jay B. Brockman and Norman P. Jouppi}, + title = {CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques}, + booktitle = {ICCAD: International Conference on Computer-Aided Design}, + year = {2011}, + pages = {694-701}, +} + + +==================== +McPAT uses an opensource XML parser written and kindly specially licensed by Mr. Frank Vanden Berghen. +The detailed information about this XML parser can be found at the license information in xmlParse.cc/xmlParse.h + +==================== +McPAT is in its beginning stage. We are still improving the tool. +Please come back to its website for newer versions. +McPAT has been constantly and rapidly improved with new models and latest technology. +Please always refer to its code for most up-to-date and most accurate information. +If you have any comments, questions, or suggestions, please write to us: + + +Sheng Li +Sheng.sli@gmail.com + + + + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/XML_Parse.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/XML_Parse.cc new file mode 100644 index 0000000000..642f766bb3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/XML_Parse.cc @@ -0,0 +1,488 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "XML_Parse.h" +#include +#include +#include + +using namespace std; + +void ParseXML::parse(char *filepath) { + // Initialize all structures + ParseXML::initialize(); +} +void ParseXML::initialize() // Initialize all +{ + // All number_of_* at the level of 'system' 03/21/2009 + sys.number_of_cores = 1; + sys.number_of_L1Directories = 1; + sys.number_of_L2Directories = 1; + sys.number_of_L2s = 1; + sys.Private_L2 = false; + sys.number_of_L3s = 1; + sys.number_of_NoCs = 1; + // All params at the level of 'system' + // strcpy(sys.homogeneous_cores,"default"); + sys.core_tech_node = 1; + sys.target_core_clockrate = 1; + sys.target_chip_area = 1; + sys.temperature = 360; + sys.number_cache_levels = 1; + sys.homogeneous_cores = 1; + sys.homogeneous_L1Directories = 1; + sys.homogeneous_L2Directories = 1; + sys.homogeneous_L2s = 1; + sys.homogeneous_L3s = 1; + sys.homogeneous_NoCs = 1; + sys.homogeneous_ccs = 1; + + sys.Max_area_deviation = 1; + sys.Max_power_deviation = 1; + sys.device_type = 1; + sys.longer_channel_device = true; + sys.power_gating = false; + sys.Embedded = false; + sys.opt_dynamic_power = false; + sys.opt_lakage_power = false; + sys.opt_clockrate = true; + sys.opt_area = false; + sys.interconnect_projection_type = 1; + sys.vdd = 0; + sys.power_gating_vcc = -1; + int i, j; + for (i = 0; i <= 63; i++) { + sys.core[i].vdd = 0; + sys.core[i].power_gating_vcc = -1; + sys.core[i].clock_rate = 1; + sys.core[i].opt_local = true; + sys.core[i].x86 = false; + sys.core[i].machine_bits = 1; + sys.core[i].virtual_address_width = 1; + sys.core[i].physical_address_width = 1; + sys.core[i].opcode_width = 1; + sys.core[i].micro_opcode_width = 1; + // strcpy(sys.core[i].machine_type,"default"); + sys.core[i].internal_datapath_width = 1; + sys.core[i].number_hardware_threads = 1; + sys.core[i].fetch_width = 1; + sys.core[i].number_instruction_fetch_ports = 1; + sys.core[i].decode_width = 1; + sys.core[i].issue_width = 1; + sys.core[i].peak_issue_width = 1; + sys.core[i].commit_width = 1; + for (j = 0; j < 20; j++) + sys.core[i].pipelines_per_core[j] = 1; + for (j = 0; j < 20; j++) + sys.core[i].pipeline_depth[j] = 1; + strcpy(sys.core[i].FPU, "default"); + strcpy(sys.core[i].divider_multiplier, "default"); + sys.core[i].ALU_per_core = 1; + sys.core[i].FPU_per_core = 1.0; + sys.core[i].MUL_per_core = 1; + sys.core[i].instruction_buffer_size = 1; + sys.core[i].decoded_stream_buffer_size = 1; + // strcpy(sys.core[i].instruction_window_scheme,"default"); + sys.core[i].instruction_window_size = 1; + sys.core[i].ROB_size = 1; + sys.core[i].archi_Regs_IRF_size = 1; + sys.core[i].archi_Regs_FRF_size = 1; + sys.core[i].phy_Regs_IRF_size = 1; + sys.core[i].phy_Regs_FRF_size = 1; + // strcpy(sys.core[i].rename_scheme,"default"); + sys.core[i].checkpoint_depth = 1; + sys.core[i].register_windows_size = 1; + strcpy(sys.core[i].LSU_order, "default"); + sys.core[i].store_buffer_size = 1; + sys.core[i].load_buffer_size = 1; + sys.core[i].memory_ports = 1; + strcpy(sys.core[i].Dcache_dual_pump, "default"); + sys.core[i].RAS_size = 1; + // all stats at the level of system.core(0-n) + sys.core[i].total_instructions = 1; + sys.core[i].int_instructions = 1; + sys.core[i].fp_instructions = 1; + sys.core[i].branch_instructions = 1; + sys.core[i].branch_mispredictions = 1; + sys.core[i].committed_instructions = 1; + sys.core[i].load_instructions = 1; + sys.core[i].store_instructions = 1; + sys.core[i].total_cycles = 1; + sys.core[i].idle_cycles = 1; + sys.core[i].busy_cycles = 1; + sys.core[i].instruction_buffer_reads = 1; + sys.core[i].instruction_buffer_write = 1; + sys.core[i].ROB_reads = 1; + sys.core[i].ROB_writes = 1; + sys.core[i].rename_accesses = 1; + sys.core[i].inst_window_reads = 1; + sys.core[i].inst_window_writes = 1; + sys.core[i].inst_window_wakeup_accesses = 1; + sys.core[i].inst_window_selections = 1; + sys.core[i].archi_int_regfile_reads = 1; + sys.core[i].archi_float_regfile_reads = 1; + sys.core[i].phy_int_regfile_reads = 1; + sys.core[i].phy_float_regfile_reads = 1; + sys.core[i].windowed_reg_accesses = 1; + sys.core[i].windowed_reg_transports = 1; + sys.core[i].function_calls = 1; + sys.core[i].ialu_accesses = 1; + sys.core[i].fpu_accesses = 1; + sys.core[i].mul_accesses = 1; + sys.core[i].cdb_alu_accesses = 1; + sys.core[i].cdb_mul_accesses = 1; + sys.core[i].cdb_fpu_accesses = 1; + sys.core[i].load_buffer_reads = 1; + sys.core[i].load_buffer_writes = 1; + sys.core[i].load_buffer_cams = 1; + sys.core[i].store_buffer_reads = 1; + sys.core[i].store_buffer_writes = 1; + sys.core[i].store_buffer_cams = 1; + sys.core[i].store_buffer_forwards = 1; + sys.core[i].main_memory_access = 1; + sys.core[i].main_memory_read = 1; + sys.core[i].main_memory_write = 1; + sys.core[i].IFU_duty_cycle = 1; + sys.core[i].BR_duty_cycle = 1; + sys.core[i].LSU_duty_cycle = 1; + sys.core[i].MemManU_I_duty_cycle = 1; + sys.core[i].MemManU_D_duty_cycle = 1; + sys.core[i].ALU_duty_cycle = 1; + sys.core[i].MUL_duty_cycle = 1; + sys.core[i].FPU_duty_cycle = 1; + sys.core[i].ALU_cdb_duty_cycle = 1; + sys.core[i].MUL_cdb_duty_cycle = 1; + sys.core[i].FPU_cdb_duty_cycle = 1; + // system.core?.predictor + sys.core[i].predictor.prediction_width = 1; + strcpy(sys.core[i].predictor.prediction_scheme, "default"); + sys.core[i].predictor.predictor_size = 1; + sys.core[i].predictor.predictor_entries = 1; + sys.core[i].predictor.local_predictor_entries = 1; + for (j = 0; j < 20; j++) + sys.core[i].predictor.local_predictor_size[j] = 1; + sys.core[i].predictor.global_predictor_entries = 1; + sys.core[i].predictor.global_predictor_bits = 1; + sys.core[i].predictor.chooser_predictor_entries = 1; + sys.core[i].predictor.chooser_predictor_bits = 1; + sys.core[i].predictor.predictor_accesses = 1; + // system.core?.itlb + sys.core[i].itlb.number_entries = 1; + sys.core[i].itlb.total_hits = 1; + sys.core[i].itlb.total_accesses = 1; + sys.core[i].itlb.total_misses = 1; + // system.core?.icache + for (j = 0; j < 20; j++) + sys.core[i].icache.icache_config[j] = 1; + // strcpy(sys.core[i].icache.buffer_sizes,"default"); + sys.core[i].icache.total_accesses = 1; + sys.core[i].icache.read_accesses = 1; + sys.core[i].icache.read_misses = 1; + sys.core[i].icache.replacements = 1; + sys.core[i].icache.read_hits = 1; + sys.core[i].icache.total_hits = 1; + sys.core[i].icache.total_misses = 1; + sys.core[i].icache.miss_buffer_access = 1; + sys.core[i].icache.fill_buffer_accesses = 1; + sys.core[i].icache.prefetch_buffer_accesses = 1; + sys.core[i].icache.prefetch_buffer_writes = 1; + sys.core[i].icache.prefetch_buffer_reads = 1; + sys.core[i].icache.prefetch_buffer_hits = 1; + // system.core?.dtlb + sys.core[i].dtlb.number_entries = 1; + sys.core[i].dtlb.total_accesses = 1; + sys.core[i].dtlb.read_accesses = 1; + sys.core[i].dtlb.write_accesses = 1; + sys.core[i].dtlb.write_hits = 1; + sys.core[i].dtlb.read_hits = 1; + sys.core[i].dtlb.read_misses = 1; + sys.core[i].dtlb.write_misses = 1; + sys.core[i].dtlb.total_hits = 1; + sys.core[i].dtlb.total_misses = 1; + // system.core?.dcache + for (j = 0; j < 20; j++) + sys.core[i].dcache.dcache_config[j] = 1; + // strcpy(sys.core[i].dcache.buffer_sizes,"default"); + sys.core[i].dcache.total_accesses = 1; + sys.core[i].dcache.read_accesses = 1; + sys.core[i].dcache.write_accesses = 1; + sys.core[i].dcache.total_hits = 1; + sys.core[i].dcache.total_misses = 1; + sys.core[i].dcache.read_hits = 1; + sys.core[i].dcache.write_hits = 1; + sys.core[i].dcache.read_misses = 1; + sys.core[i].dcache.write_misses = 1; + sys.core[i].dcache.replacements = 1; + sys.core[i].dcache.write_backs = 1; + sys.core[i].dcache.miss_buffer_access = 1; + sys.core[i].dcache.fill_buffer_accesses = 1; + sys.core[i].dcache.prefetch_buffer_accesses = 1; + sys.core[i].dcache.prefetch_buffer_writes = 1; + sys.core[i].dcache.prefetch_buffer_reads = 1; + sys.core[i].dcache.prefetch_buffer_hits = 1; + sys.core[i].dcache.wbb_writes = 1; + sys.core[i].dcache.wbb_reads = 1; + // system.core?.BTB + for (j = 0; j < 20; j++) + sys.core[i].BTB.BTB_config[j] = 1; + sys.core[i].BTB.total_accesses = 1; + sys.core[i].BTB.read_accesses = 1; + sys.core[i].BTB.write_accesses = 1; + sys.core[i].BTB.total_hits = 1; + sys.core[i].BTB.total_misses = 1; + sys.core[i].BTB.read_hits = 1; + sys.core[i].BTB.write_hits = 1; + sys.core[i].BTB.read_misses = 1; + sys.core[i].BTB.write_misses = 1; + sys.core[i].BTB.replacements = 1; + } + + // system_L1directory + for (i = 0; i <= 63; i++) { + for (j = 0; j < 20; j++) + sys.L1Directory[i].Dir_config[j] = 1; + for (j = 0; j < 20; j++) + sys.L1Directory[i].buffer_sizes[j] = 1; + sys.L1Directory[i].clockrate = 1; + sys.L1Directory[i].ports[19] = 1; + sys.L1Directory[i].device_type = 1; + sys.L1Directory[i].vdd = 0; + sys.L1Directory[i].power_gating_vcc = -1; + strcpy(sys.L1Directory[i].threeD_stack, "default"); + sys.L1Directory[i].total_accesses = 1; + sys.L1Directory[i].read_accesses = 1; + sys.L1Directory[i].write_accesses = 1; + sys.L1Directory[i].duty_cycle = 1; + } + // system_L2directory + for (i = 0; i <= 63; i++) { + for (j = 0; j < 20; j++) + sys.L2Directory[i].Dir_config[j] = 1; + for (j = 0; j < 20; j++) + sys.L2Directory[i].buffer_sizes[j] = 1; + sys.L2Directory[i].clockrate = 1; + sys.L2Directory[i].ports[19] = 1; + sys.L2Directory[i].device_type = 1; + sys.L2Directory[i].vdd = 0; + sys.L2Directory[i].power_gating_vcc = -1; + strcpy(sys.L2Directory[i].threeD_stack, "default"); + sys.L2Directory[i].total_accesses = 1; + sys.L2Directory[i].read_accesses = 1; + sys.L2Directory[i].write_accesses = 1; + sys.L2Directory[i].duty_cycle = 1; + } + for (i = 0; i <= 63; i++) { + // system_L2 + for (j = 0; j < 20; j++) + sys.L2[i].L2_config[j] = 1; + sys.L2[i].clockrate = 1; + for (j = 0; j < 20; j++) + sys.L2[i].ports[j] = 1; + sys.L2[i].device_type = 1; + sys.L2[i].vdd = 0; + sys.L2[i].power_gating_vcc = -1; + strcpy(sys.L2[i].threeD_stack, "default"); + for (j = 0; j < 20; j++) + sys.L2[i].buffer_sizes[j] = 1; + sys.L2[i].total_accesses = 1; + sys.L2[i].read_accesses = 1; + sys.L2[i].write_accesses = 1; + sys.L2[i].total_hits = 1; + sys.L2[i].total_misses = 1; + sys.L2[i].read_hits = 1; + sys.L2[i].write_hits = 1; + sys.L2[i].read_misses = 1; + sys.L2[i].write_misses = 1; + sys.L2[i].replacements = 1; + sys.L2[i].write_backs = 1; + sys.L2[i].miss_buffer_accesses = 1; + sys.L2[i].fill_buffer_accesses = 1; + sys.L2[i].prefetch_buffer_accesses = 1; + sys.L2[i].prefetch_buffer_writes = 1; + sys.L2[i].prefetch_buffer_reads = 1; + sys.L2[i].prefetch_buffer_hits = 1; + sys.L2[i].wbb_writes = 1; + sys.L2[i].wbb_reads = 1; + sys.L2[i].duty_cycle = 1; + sys.L2[i].merged_dir = false; + sys.L2[i].homenode_read_accesses = 1; + sys.L2[i].homenode_write_accesses = 1; + sys.L2[i].homenode_read_hits = 1; + sys.L2[i].homenode_write_hits = 1; + sys.L2[i].homenode_read_misses = 1; + sys.L2[i].homenode_write_misses = 1; + sys.L2[i].dir_duty_cycle = 1; + } + for (i = 0; i <= 63; i++) { + // system_L3 + for (j = 0; j < 20; j++) + sys.L3[i].L3_config[j] = 1; + sys.L3[i].clockrate = 1; + for (j = 0; j < 20; j++) + sys.L3[i].ports[j] = 1; + sys.L3[i].device_type = 1; + sys.L3[i].vdd = 0; + sys.L2[i].power_gating_vcc = -1; + strcpy(sys.L3[i].threeD_stack, "default"); + for (j = 0; j < 20; j++) + sys.L3[i].buffer_sizes[j] = 1; + sys.L3[i].total_accesses = 1; + sys.L3[i].read_accesses = 1; + sys.L3[i].write_accesses = 1; + sys.L3[i].total_hits = 1; + sys.L3[i].total_misses = 1; + sys.L3[i].read_hits = 1; + sys.L3[i].write_hits = 1; + sys.L3[i].read_misses = 1; + sys.L3[i].write_misses = 1; + sys.L3[i].replacements = 1; + sys.L3[i].write_backs = 1; + sys.L3[i].miss_buffer_accesses = 1; + sys.L3[i].fill_buffer_accesses = 1; + sys.L3[i].prefetch_buffer_accesses = 1; + sys.L3[i].prefetch_buffer_writes = 1; + sys.L3[i].prefetch_buffer_reads = 1; + sys.L3[i].prefetch_buffer_hits = 1; + sys.L3[i].wbb_writes = 1; + sys.L3[i].wbb_reads = 1; + sys.L3[i].duty_cycle = 1; + sys.L3[i].merged_dir = false; + sys.L3[i].homenode_read_accesses = 1; + sys.L3[i].homenode_write_accesses = 1; + sys.L3[i].homenode_read_hits = 1; + sys.L3[i].homenode_write_hits = 1; + sys.L3[i].homenode_read_misses = 1; + sys.L3[i].homenode_write_misses = 1; + sys.L3[i].dir_duty_cycle = 1; + } + // system_NoC + for (i = 0; i <= 63; i++) { + sys.NoC[i].clockrate = 1; + sys.NoC[i].type = true; + sys.NoC[i].chip_coverage = 1; + sys.NoC[i].vdd = 0; + sys.NoC[i].power_gating_vcc = -1; + sys.NoC[i].has_global_link = true; + strcpy(sys.NoC[i].topology, "default"); + sys.NoC[i].horizontal_nodes = 1; + sys.NoC[i].vertical_nodes = 1; + sys.NoC[i].input_ports = 1; + sys.NoC[i].output_ports = 1; + sys.NoC[i].virtual_channel_per_port = 1; + sys.NoC[i].flit_bits = 1; + sys.NoC[i].input_buffer_entries_per_vc = 1; + sys.NoC[i].total_accesses = 1; + sys.NoC[i].duty_cycle = 1; + sys.NoC[i].route_over_perc = 0.5; + for (j = 0; j < 20; j++) + sys.NoC[i].ports_of_input_buffer[j] = 1; + sys.NoC[i].number_of_crossbars = 1; + strcpy(sys.NoC[i].crossbar_type, "default"); + strcpy(sys.NoC[i].crosspoint_type, "default"); + // system.NoC?.xbar0; + sys.NoC[i].xbar0.number_of_inputs_of_crossbars = 1; + sys.NoC[i].xbar0.number_of_outputs_of_crossbars = 1; + sys.NoC[i].xbar0.flit_bits = 1; + sys.NoC[i].xbar0.input_buffer_entries_per_port = 1; + sys.NoC[i].xbar0.ports_of_input_buffer[19] = 1; + sys.NoC[i].xbar0.crossbar_accesses = 1; + } + // system_mem + sys.mem.mem_tech_node = 1; + sys.mem.device_clock = 1; + sys.mem.capacity_per_channel = 1; + sys.mem.number_ranks = 1; + sys.mem.peak_transfer_rate = 1; + sys.mem.num_banks_of_DRAM_chip = 1; + sys.mem.Block_width_of_DRAM_chip = 1; + sys.mem.output_width_of_DRAM_chip = 1; + sys.mem.page_size_of_DRAM_chip = 1; + sys.mem.burstlength_of_DRAM_chip = 1; + sys.mem.internal_prefetch_of_DRAM_chip = 1; + sys.mem.memory_accesses = 1; + sys.mem.memory_reads = 1; + sys.mem.memory_writes = 1; + // system_mc + sys.mc.mc_clock = 1; + sys.mc.number_mcs = 1; + sys.mc.peak_transfer_rate = 1; + sys.mc.memory_channels_per_mc = 1; + sys.mc.number_ranks = 1; + sys.mc.req_window_size_per_channel = 1; + sys.mc.IO_buffer_size_per_channel = 1; + sys.mc.databus_width = 1; + sys.mc.addressbus_width = 1; + sys.mc.memory_accesses = 1; + sys.mc.memory_reads = 1; + sys.mc.memory_writes = 1; + sys.mc.LVDS = true; + sys.mc.type = 1; + sys.mc.vdd = 0; + sys.mc.power_gating_vcc = -1; + // system_niu + sys.niu.clockrate = 1; + sys.niu.number_units = 1; + sys.niu.type = 1; + sys.niu.vdd = 0; + sys.niu.power_gating_vcc = -1; + sys.niu.duty_cycle = 1; + sys.niu.total_load_perc = 1; + // system_pcie + sys.pcie.clockrate = 1; + sys.pcie.number_units = 1; + sys.pcie.num_channels = 1; + sys.pcie.type = 1; + sys.pcie.vdd = 0; + sys.pcie.power_gating_vcc = -1; + sys.pcie.withPHY = false; + sys.pcie.duty_cycle = 1; + sys.pcie.total_load_perc = 1; + // system_flash_controller + sys.flashc.mc_clock = 1; + sys.flashc.number_mcs = 1; + sys.flashc.vdd = 0; + sys.flashc.power_gating_vcc = -1; + sys.flashc.peak_transfer_rate = 1; + sys.flashc.memory_channels_per_mc = 1; + sys.flashc.number_ranks = 1; + sys.flashc.req_window_size_per_channel = 1; + sys.flashc.IO_buffer_size_per_channel = 1; + sys.flashc.databus_width = 1; + sys.flashc.addressbus_width = 1; + sys.flashc.memory_accesses = 1; + sys.flashc.memory_reads = 1; + sys.flashc.memory_writes = 1; + sys.flashc.LVDS = true; + sys.flashc.withPHY = false; + sys.flashc.type = 1; + sys.flashc.duty_cycle = 1; + sys.flashc.total_load_perc = 1; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/XML_Parse.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/XML_Parse.h new file mode 100644 index 0000000000..539deb5391 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/XML_Parse.h @@ -0,0 +1,614 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef XML_PARSE_H_ +#define XML_PARSE_H_ + +//#ifdef WIN32 +//#define _CRT_SECURE_NO_DEPRECATE +//#endif + +#include +#include +#include +using namespace std; + +/* +void myfree(char *t); // {free(t);} +ToXMLStringTool tx,tx2; +*/ +// all subnodes at the level of system.core(0-n) +// cache_policy is added into cache property arrays;//0 no write or write-though +// with non-write allocate;1 write-back with write-allocate + +typedef struct { + int prediction_width; + char prediction_scheme[20]; + int predictor_size; + int predictor_entries; + int local_predictor_size[20]; + int local_predictor_entries; + int global_predictor_entries; + int global_predictor_bits; + int chooser_predictor_entries; + int chooser_predictor_bits; + double predictor_accesses; +} predictor_systemcore; +typedef struct { + int number_entries; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + double total_hits; + double total_accesses; + double total_misses; + double conflicts; +} itlb_systemcore; +typedef struct { + // params + double icache_config[20]; + int buffer_sizes[20]; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + // stats + double total_accesses; + double read_accesses; + double read_misses; + double replacements; + double read_hits; + double total_hits; + double total_misses; + double miss_buffer_access; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double conflicts; +} icache_systemcore; +typedef struct { + // params + int number_entries; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double write_hits; + double read_hits; + double read_misses; + double write_misses; + double total_hits; + double total_misses; + double conflicts; +} dtlb_systemcore; +typedef struct { + // params + double dcache_config[20]; + int buffer_sizes[20]; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; + double write_backs; + double miss_buffer_access; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double wbb_writes; + double wbb_reads; + double conflicts; +} dcache_systemcore; +typedef struct { + // params + int BTB_config[20]; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; +} BTB_systemcore; +typedef struct { + // all params at the level of system.core(0-n) + int clock_rate; + bool opt_local; + bool x86; + int machine_bits; + int virtual_address_width; + int physical_address_width; + int opcode_width; + int micro_opcode_width; + int instruction_length; + int machine_type; + int internal_datapath_width; + int number_hardware_threads; + int fetch_width; + int number_instruction_fetch_ports; + int decode_width; + int issue_width; + int peak_issue_width; + int commit_width; + int pipelines_per_core[20]; + int pipeline_depth[20]; + char FPU[20]; + char divider_multiplier[20]; + int ALU_per_core; + double FPU_per_core; + int MUL_per_core; + int instruction_buffer_size; + int decoded_stream_buffer_size; + int instruction_window_scheme; + int instruction_window_size; + int fp_instruction_window_size; + int ROB_size; + int archi_Regs_IRF_size; + int archi_Regs_FRF_size; + int phy_Regs_IRF_size; + int phy_Regs_FRF_size; + int rename_scheme; + int checkpoint_depth; + int register_windows_size; + char LSU_order[20]; + int store_buffer_size; + int load_buffer_size; + int memory_ports; + char Dcache_dual_pump[20]; + int RAS_size; + int fp_issue_width; + int prediction_width; + int number_of_BTB; + int number_of_BPT; + + // all stats at the level of system.core(0-n) + double total_instructions; + double int_instructions; + double fp_instructions; + double branch_instructions; + double branch_mispredictions; + double committed_instructions; + double committed_int_instructions; + double committed_fp_instructions; + double load_instructions; + double store_instructions; + double total_cycles; + double idle_cycles; + double busy_cycles; + double instruction_buffer_reads; + double instruction_buffer_write; + double ROB_reads; + double ROB_writes; + double rename_accesses; + double fp_rename_accesses; + double rename_reads; + double rename_writes; + double fp_rename_reads; + double fp_rename_writes; + double inst_window_reads; + double inst_window_writes; + double inst_window_wakeup_accesses; + double inst_window_selections; + double fp_inst_window_reads; + double fp_inst_window_writes; + double fp_inst_window_wakeup_accesses; + double fp_inst_window_selections; + double archi_int_regfile_reads; + double archi_float_regfile_reads; + double phy_int_regfile_reads; + double phy_float_regfile_reads; + double phy_int_regfile_writes; + double phy_float_regfile_writes; + double archi_int_regfile_writes; + double archi_float_regfile_writes; + double int_regfile_reads; + double float_regfile_reads; + double int_regfile_writes; + double float_regfile_writes; + double windowed_reg_accesses; + double windowed_reg_transports; + double function_calls; + double context_switches; + double ialu_accesses; + double fpu_accesses; + double mul_accesses; + double cdb_alu_accesses; + double cdb_mul_accesses; + double cdb_fpu_accesses; + double load_buffer_reads; + double load_buffer_writes; + double load_buffer_cams; + double store_buffer_reads; + double store_buffer_writes; + double store_buffer_cams; + double store_buffer_forwards; + double main_memory_access; + double main_memory_read; + double main_memory_write; + double pipeline_duty_cycle; + + double IFU_duty_cycle; + double BR_duty_cycle; + double LSU_duty_cycle; + double MemManU_I_duty_cycle; + double MemManU_D_duty_cycle; + double ALU_duty_cycle; + double MUL_duty_cycle; + double FPU_duty_cycle; + double ALU_cdb_duty_cycle; + double MUL_cdb_duty_cycle; + double FPU_cdb_duty_cycle; + + double vdd; + double power_gating_vcc; + + // all subnodes at the level of system.core(0-n) + predictor_systemcore predictor; + itlb_systemcore itlb; + icache_systemcore icache; + dtlb_systemcore dtlb; + dcache_systemcore dcache; + BTB_systemcore BTB; + +} system_core; +typedef struct { + // params + int Directory_type; + double Dir_config[20]; + int buffer_sizes[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double read_misses; + double write_misses; + double conflicts; + double duty_cycle; +} system_L1Directory; +typedef struct { + // params + int Directory_type; + double Dir_config[20]; + int buffer_sizes[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double read_misses; + double write_misses; + double conflicts; + double duty_cycle; +} system_L2Directory; +typedef struct { + // params + double L2_config[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + int buffer_sizes[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; + double write_backs; + double miss_buffer_accesses; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double wbb_writes; + double wbb_reads; + double conflicts; + double duty_cycle; + + bool merged_dir; + double homenode_read_accesses; + double homenode_write_accesses; + double homenode_read_hits; + double homenode_write_hits; + double homenode_read_misses; + double homenode_write_misses; + double dir_duty_cycle; +} system_L2; +typedef struct { + // params + double L3_config[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + int buffer_sizes[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; + double write_backs; + double miss_buffer_accesses; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double wbb_writes; + double wbb_reads; + double conflicts; + double duty_cycle; + + bool merged_dir; + double homenode_read_accesses; + double homenode_write_accesses; + double homenode_read_hits; + double homenode_write_hits; + double homenode_read_misses; + double homenode_write_misses; + double dir_duty_cycle; +} system_L3; +typedef struct { + // params + int number_of_inputs_of_crossbars; + int number_of_outputs_of_crossbars; + int flit_bits; + int input_buffer_entries_per_port; + int ports_of_input_buffer[20]; + // stats + double crossbar_accesses; +} xbar0_systemNoC; +typedef struct { + // params + int clockrate; + bool type; + bool has_global_link; + char topology[20]; + int horizontal_nodes; + int vertical_nodes; + int link_throughput; + int link_latency; + int input_ports; + int output_ports; + int virtual_channel_per_port; + int flit_bits; + int input_buffer_entries_per_vc; + int ports_of_input_buffer[20]; + int dual_pump; + int number_of_crossbars; + char crossbar_type[20]; + char crosspoint_type[20]; + xbar0_systemNoC xbar0; + int arbiter_type; + double chip_coverage; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double duty_cycle; + double route_over_perc; +} system_NoC; +typedef struct { + // params + int mem_tech_node; + int device_clock; + int peak_transfer_rate; + int internal_prefetch_of_DRAM_chip; + int capacity_per_channel; + int number_ranks; + int num_banks_of_DRAM_chip; + int Block_width_of_DRAM_chip; + int output_width_of_DRAM_chip; + int page_size_of_DRAM_chip; + int burstlength_of_DRAM_chip; + // stats + double memory_accesses; + double memory_reads; + double memory_writes; +} system_mem; +typedef struct { + // params + // Common Param for mc and fc + double peak_transfer_rate; + int number_mcs; + bool withPHY; + int type; + + // FCParam + // stats + double duty_cycle; + double total_load_perc; + + // McParam + int mc_clock; + int llc_line_length; + int memory_channels_per_mc; + int number_ranks; + int req_window_size_per_channel; + int IO_buffer_size_per_channel; + int databus_width; + int addressbus_width; + bool LVDS; + double vdd; + double power_gating_vcc; + + // stats + double memory_accesses; + double memory_reads; + double memory_writes; +} system_mc; + +typedef struct { + // params + int clockrate; + int number_units; + int type; + double vdd; + double power_gating_vcc; + // stats + double duty_cycle; + double total_load_perc; +} system_niu; + +typedef struct { + // params + int clockrate; + int number_units; + int num_channels; + int type; + bool withPHY; + double vdd; + double power_gating_vcc; + // stats + double duty_cycle; + double total_load_perc; +} system_pcie; + +typedef struct { + // All number_of_* at the level of 'system' Ying 03/21/2009 + int number_of_cores; + int number_of_L1Directories; + int number_of_L2Directories; + int number_of_L2s; + bool Private_L2; + int number_of_L3s; + int number_of_NoCs; + int number_of_dir_levels; + int domain_size; + int first_level_dir; + // All params at the level of 'system' + int homogeneous_cores; + int homogeneous_L1Directories; + int homogeneous_L2Directories; + double core_tech_node; + int target_core_clockrate; + int target_chip_area; + int temperature; + int number_cache_levels; + int L1_property; + int L2_property; + int homogeneous_L2s; + int L3_property; + int homogeneous_L3s; + int homogeneous_NoCs; + int homogeneous_ccs; + int Max_area_deviation; + int Max_power_deviation; + int device_type; + bool longer_channel_device; + bool power_gating; + bool Embedded; + bool opt_dynamic_power; + bool opt_lakage_power; + bool opt_clockrate; + bool opt_area; + int interconnect_projection_type; + int machine_bits; + int virtual_address_width; + int physical_address_width; + int virtual_memory_page_size; + double total_cycles; + double vdd; + double power_gating_vcc; + // system.core(0-n):3rd level + system_core core[64]; + system_L1Directory L1Directory[64]; + system_L2Directory L2Directory[64]; + system_L2 L2[64]; + system_L3 L3[64]; + system_NoC NoC[64]; + system_mem mem; + system_mc mc; + system_mc flashc; + system_niu niu; + system_pcie pcie; +} root_system; + +class ParseXML { + public: + void parse(char *filepath); + void initialize(); + + public: + root_system sys; +}; + +#endif /* XML_PARSE_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/arch_const.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/arch_const.h new file mode 100644 index 0000000000..32c60b3102 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/arch_const.h @@ -0,0 +1,255 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef ARCH_CONST_H_ +#define ARCH_CONST_H_ + +typedef struct { + unsigned int capacity; + unsigned int assoc; // fully + unsigned int blocksize; +} array_inputs; + +// Do Not change, unless you want to bypass the XML interface and do not care +// about the default values. Global parameters +const int number_of_cores = 8; +const int number_of_L2s = 1; +const int number_of_L3s = 1; +const int number_of_NoCs = 1; + +const double archi_F_sz_nm = 90.0; +const unsigned int dev_type = 0; +const double CLOCKRATE = 1.2 * 1e9; +const double AF = 0.5; +// const bool inorder = true; +const bool embedded = false; // NEW + +const bool homogeneous_cores = true; +const bool temperature = 360; +const int number_cache_levels = 3; +const int L1_property = 0; // private 0; coherent 1, shared 2. +const int L2_property = 2; +const bool homogeneous_L2s = true; +const bool L3_property = 2; +const bool homogeneous_L3s = true; +const double Max_area_deviation = 50; +const double Max_dynamic_deviation = 50; // New +const int opt_dynamic_power = 1; +const int opt_lakage_power = 0; +const int opt_area = 0; +const int interconnect_projection_type = 0; + +//******************************Core Parameters +const int opcode_length = 8; // 16;//Niagara +const int reg_length = 7; // Niagara +const int instruction_length = 32; // Niagara +const int data_width = 64; + +// Caches +// itlb +const int itlbsize = 512; +const int itlbassoc = 0; // fully +const int itlbblocksize = 8; +// icache +const int icachesize = 32768; +const int icacheassoc = 4; +const int icacheblocksize = 32; +// dtlb +const int dtlbsize = 512; +const int dtlbassoc = 0; // fully +const int dtlbblocksize = 8; +// dcache +const int dcachesize = 32768; +const int dcacheassoc = 4; +const int dcacheblocksize = 32; +const int dcache_write_buffers = 8; + +// cache controllers +// IB, +const int numIBEntries = 64; +const int IBsize = 64; // 2*4*instruction_length/8*2; +const int IBassoc = 0; // In Niagara it is still fully associ +const int IBblocksize = 4; + +// IFB and MIL should have the same parameters CAM +const int IFBsize = 128; // +const int IFBassoc = 0; // In Niagara it is still fully associ +const int IFBblocksize = 4; + +const int icache_write_buffers = 8; + +// register file RAM +const int regfilesize = 5760; +const int regfileassoc = 1; +const int regfileblocksize = 18; +// regwin RAM +const int regwinsize = 256; +const int regwinassoc = 1; +const int regwinblocksize = 8; + +// store buffer, lsq +const int lsqsize = 512; +const int lsqassoc = 0; +const int lsqblocksize = 8; + +// data fill queue RAM +const int dfqsize = 1024; +const int dfqassoc = 1; +const int dfqblocksize = 16; + +// outside the cores +// L2 cache bank +const int l2cachesize = 262144; +const int l2cacheassoc = 16; +const int l2cacheblocksize = 64; + +// L2 directory +const int l2dirsize = 1024; +const int l2dirassoc = 0; +const int l2dirblocksize = 2; + +// crossbar +// PCX +const int PCX_NUMBER_INPUT_PORTS_CROSSBAR = 8; +const int PCX_NUMBER_OUTPUT_PORTS_CROSSBAR = 9; +const int PCX_NUMBER_SIGNALS_PER_PORT_CROSSBAR = 144; +// PCX buffer RAM +const int pcx_buffersize = 1024; +const int pcx_bufferassoc = 1; +const int pcx_bufferblocksize = 32; +const int pcx_numbuffer = 5; +// pcx arbiter +const int pcx_arbsize = 128; +const int pcx_arbassoc = 1; +const int pcx_arbblocksize = 2; +const int pcx_numarb = 5; + +// CPX +const int CPX_NUMBER_INPUT_PORTS_CROSSBAR = 5; +const int CPX_NUMBER_OUTPUT_PORTS_CROSSBAR = 8; +const int CPX_NUMBER_SIGNALS_PER_PORT_CROSSBAR = 150; +// CPX buffer RAM +const int cpx_buffersize = 1024; +const int cpx_bufferassoc = 1; +const int cpx_bufferblocksize = 32; +const int cpx_numbuffer = 8; +// cpx arbiter +const int cpx_arbsize = 128; +const int cpx_arbassoc = 1; +const int cpx_arbblocksize = 2; +const int cpx_numarb = 8; + +const int numPhysFloatRegs = 256; +const int numPhysIntRegs = 32; +const int numROBEntries = 192; +const int umRobs = 1; + +const int BTBEntries = 4096; +const int BTBTagSize = 16; +const int LFSTSize = 1024; +const int LQEntries = 32; +const int RASSize = 16; +const int SQEntries = 32; +const int SSITSize = 1024; +const int activity = 0; +const int backComSize = 5; +const int cachePorts = 200; +const int choiceCtrBits = 2; +const int choicePredictorSize = 8192; + +const int commitWidth = 8; +const int decodeWidth = 8; +const int dispatchWidth = 8; +const int fetchWidth = 8; +const int issueWidth = 1; +const int renameWidth = 8; +// what is this forwardComSize=5?? + +const int globalCtrBits = 2; +const int globalHistoryBits = 13; +const int globalPredictorSize = 8192; + +const int localCtrBits = 2; +const int localHistoryBits = 11; +const int localHistoryTableSize = 2048; +const int localPredictorSize = 2048; + +const double Woutdrvnandn = 30 * 0.09; //(24.0 * LSCALE) +const double Woutdrvnandp = 12.5 * 0.09; //(10.0 * LSCALE) +const double Woutdrvnorn = 7.5 * 0.09; //(6.0 * LSCALE) +const double Woutdrvnorp = 50 * 0.09; // (40.0 * LSCALE) +const double Woutdrivern = 60 * 0.09; //(48.0 * LSCALE) +const double Woutdriverp = 100 * 0.09; //(80.0 * LSCALE) + +/* +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +*/ + +/* +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null + + +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false + +cpu_side=system.cpu0.dcache_port +mem_side=system.tol2bus.port[2] +*/ + +//[system.cpu0.dtb] +// type=AlphaDT + +#endif /* ARCH_CONST_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/array.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/array.cc new file mode 100644 index 0000000000..2d425ab120 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/array.cc @@ -0,0 +1,379 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#define GLOBALVAR +#include "array.h" +#include +#include +#include +#include "cacti/area.h" +#include "cacti/decoder.h" +#include "cacti/parameter.h" +#include "globalvar.h" + +using namespace std; + +ArrayST::ArrayST(const InputParameter *configure_interface, string _name, + enum Device_ty device_ty_, bool opt_local_, + enum Core_type core_ty_, bool _is_default) + : l_ip(*configure_interface), + name(_name), + device_ty(device_ty_), + opt_local(opt_local_), + core_ty(core_ty_), + is_default(_is_default) { + if (l_ip.cache_sz < 64) + l_ip.cache_sz = 64; + if (l_ip.power_gating && (l_ip.assoc == 0)) { + l_ip.power_gating = false; + } + l_ip.error_checking(); // not only do the error checking but also fill some + // missing parameters + optimize_array(); +} + +void ArrayST::compute_base_power() { + // l_ip.out_w =l_ip.line_sz*8; + local_result = cacti_interface(&l_ip); + assert(local_result.cycle_time > 0); + assert(local_result.access_time > 0); + // if (name == "Int FrontRAT") + // { + // cout< (candidate_iter)->power.readOp.dynamic) { + min_dynamic_energy = (candidate_iter)->power.readOp.dynamic; + min_dynamic_energy_iter = candidate_iter; + local_result = *(min_dynamic_energy_iter); + // TODO: since results are reordered results and l_ip may miss match. + // Therefore, the final output spread sheets may show the miss match. + } + else { + candidate_iter->cleanup(); + } + } + } + candidate_solutions.clear(); + } + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + double pg_reduction = power_gating_leakage_reduction( + false); // array structure all retain state; + + double macro_layout_overhead = g_tp.macro_layout_overhead; + double chip_PR_overhead = g_tp.chip_layout_overhead; + double total_overhead = macro_layout_overhead * chip_PR_overhead; + local_result.area *= total_overhead; + + // maintain constant power density + double pppm_t[4] = {total_overhead, 1, 1, total_overhead}; + + double sckRation = g_tp.sckt_co_eff; + local_result.power.readOp.dynamic *= sckRation; + local_result.power.writeOp.dynamic *= sckRation; + local_result.power.searchOp.dynamic *= sckRation; + local_result.power.readOp.leakage *= l_ip.nbanks; + local_result.power.readOp.longer_channel_leakage = + local_result.power.readOp.leakage * long_channel_device_reduction; + + if (l_ip.assoc == 0) // only use this function for CAM/FA since other array + // types compute pg leakage automatically + { + local_result.power.readOp.power_gated_leakage = + local_result.power.readOp.leakage * pg_reduction; + } + else { + local_result.power.readOp.power_gated_leakage *= + l_ip.nbanks; // normal array types + } + + local_result.power.readOp.power_gated_with_long_channel_leakage = + local_result.power.readOp.power_gated_leakage * + long_channel_device_reduction; // power-gating atop long channel + + local_result.power = local_result.power * pppm_t; + + local_result.data_array2->power.readOp.dynamic *= sckRation; + local_result.data_array2->power.writeOp.dynamic *= sckRation; + local_result.data_array2->power.searchOp.dynamic *= sckRation; + local_result.data_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.data_array2->power.readOp.longer_channel_leakage = + local_result.data_array2->power.readOp.leakage * + long_channel_device_reduction; + if (l_ip.assoc == 0) // only use this function for CAM/FA since other array + // types compute pg leakage automatically + { + local_result.data_array2->power.readOp.power_gated_leakage = + local_result.data_array2->power.readOp.leakage * pg_reduction; + } + else { + local_result.data_array2->power.readOp.power_gated_leakage *= + l_ip.nbanks; // normal array types + } + local_result.data_array2->power.readOp.power_gated_with_long_channel_leakage = + local_result.data_array2->power.readOp.power_gated_leakage * + long_channel_device_reduction; + + local_result.data_array2->power = local_result.data_array2->power * pppm_t; + + if (!(l_ip.pure_cam || l_ip.pure_ram || l_ip.fully_assoc) && l_ip.is_cache) { + local_result.tag_array2->power.readOp.dynamic *= sckRation; + local_result.tag_array2->power.writeOp.dynamic *= sckRation; + local_result.tag_array2->power.searchOp.dynamic *= sckRation; + local_result.tag_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.tag_array2->power.readOp.power_gated_leakage *= l_ip.nbanks; + local_result.tag_array2->power.readOp.longer_channel_leakage = + local_result.tag_array2->power.readOp.leakage * + long_channel_device_reduction; + + local_result.tag_array2->power.readOp + .power_gated_with_long_channel_leakage = + local_result.tag_array2->power.readOp.power_gated_leakage * + long_channel_device_reduction; + local_result.tag_array2->power = local_result.tag_array2->power * pppm_t; + } +} + +void ArrayST::leakage_feedback( + double temperature) // TODO: add the code to process power-gating leakage +{ + // Update the temperature. l_ip is already set and error-checked in the + // creator function. + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + + // This corresponds to cacti_interface() in the initialization process. + // Leakage power is updated here. + reconfigure(&l_ip, &local_result); + + // Scale the power values. This is part of ArrayST::optimize_array(). + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + + double macro_layout_overhead = g_tp.macro_layout_overhead; + double chip_PR_overhead = g_tp.chip_layout_overhead; + double total_overhead = macro_layout_overhead * chip_PR_overhead; + + double pppm_t[4] = {total_overhead, 1, 1, total_overhead}; + + double sckRation = g_tp.sckt_co_eff; + local_result.power.readOp.dynamic *= sckRation; + local_result.power.writeOp.dynamic *= sckRation; + local_result.power.searchOp.dynamic *= sckRation; + local_result.power.readOp.leakage *= l_ip.nbanks; + local_result.power.readOp.longer_channel_leakage = + local_result.power.readOp.leakage * long_channel_device_reduction; + local_result.power = local_result.power * pppm_t; + + local_result.data_array2->power.readOp.dynamic *= sckRation; + local_result.data_array2->power.writeOp.dynamic *= sckRation; + local_result.data_array2->power.searchOp.dynamic *= sckRation; + local_result.data_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.data_array2->power.readOp.longer_channel_leakage = + local_result.data_array2->power.readOp.leakage * + long_channel_device_reduction; + local_result.data_array2->power = local_result.data_array2->power * pppm_t; + + if (!(l_ip.pure_cam || l_ip.pure_ram || l_ip.fully_assoc) && l_ip.is_cache) { + local_result.tag_array2->power.readOp.dynamic *= sckRation; + local_result.tag_array2->power.writeOp.dynamic *= sckRation; + local_result.tag_array2->power.searchOp.dynamic *= sckRation; + local_result.tag_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.tag_array2->power.readOp.longer_channel_leakage = + local_result.tag_array2->power.readOp.leakage * + long_channel_device_reduction; + local_result.tag_array2->power = local_result.tag_array2->power * pppm_t; + } +} + +ArrayST::~ArrayST() { + local_result.cleanup(); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/array.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/array.h new file mode 100644 index 0000000000..539c1df860 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/array.h @@ -0,0 +1,118 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef ARRAY_H_ +#define ARRAY_H_ + +#include +#include +#include "basic_components.h" +#include "cacti/cacti_interface.h" +#include "cacti/component.h" +#include "cacti/const.h" +#include "cacti/parameter.h" + +using namespace std; +using namespace cacti; + +class ArrayST : public Component { + public: + ArrayST(){}; + ArrayST(const InputParameter *configure_interface, string _name, + enum Device_ty device_ty_, bool opt_local_ = true, + enum Core_type core_ty_ = Inorder, bool _is_default = true); + + InputParameter l_ip; + string name; + enum Device_ty device_ty; + bool opt_local; + enum Core_type core_ty; + bool is_default; + uca_org_t local_result; + + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + + virtual void optimize_array(); + virtual void compute_base_power(); + virtual ~ArrayST(); + + void leakage_feedback(double temperature); +}; + +class InstCache : public Component { + public: + ArrayST *caches; + ArrayST *missb; + ArrayST *ifb; + ArrayST *prefetchb; + powerDef power_t; // temp value holder for both (max) power and runtime power + InstCache() { + caches = 0; + missb = 0; + ifb = 0; + prefetchb = 0; + }; + ~InstCache() { + if (caches) { // caches->local_result.cleanup(); + delete caches; + caches = 0; + } + if (missb) { // missb->local_result.cleanup(); + delete missb; + missb = 0; + } + if (ifb) { // ifb->local_result.cleanup(); + delete ifb; + ifb = 0; + } + if (prefetchb) { // prefetchb->local_result.cleanup(); + delete prefetchb; + prefetchb = 0; + } + }; +}; + +class DataCache : public InstCache { + public: + ArrayST *wbb; + DataCache() { wbb = 0; }; + ~DataCache() { + if (wbb) { // wbb->local_result.cleanup(); + delete wbb; + wbb = 0; + } + }; +}; + +#endif /* TLB_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/basic_components.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/basic_components.cc new file mode 100644 index 0000000000..f3e197a4b8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/basic_components.cc @@ -0,0 +1,138 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "basic_components.h" +#include +#include +#include + +using namespace cacti; + +double longer_channel_device_reduction(enum Device_ty device_ty, + enum Core_type core_ty) { + double longer_channel_device_percentage_core; + double longer_channel_device_percentage_uncore; + double longer_channel_device_percentage_llc; + + double long_channel_device_reduction; + + longer_channel_device_percentage_llc = 1.0; + longer_channel_device_percentage_uncore = 0.82; + if (core_ty == OOO) { + longer_channel_device_percentage_core = + 0.56; // 0.54 Xeon Tulsa //0.58 Nehelam + // longer_channel_device_percentage_uncore = 0.76;//0.85 Nehelam + } + else { + longer_channel_device_percentage_core = 0.8; // 0.8;//Niagara + // longer_channel_device_percentage_uncore = 0.9;//Niagara + } + + if (device_ty == Core_device) { + long_channel_device_reduction = + (1 - longer_channel_device_percentage_core) + + longer_channel_device_percentage_core * + g_tp.peri_global.long_channel_leakage_reduction; + } + else if (device_ty == Uncore_device) { + long_channel_device_reduction = + (1 - longer_channel_device_percentage_uncore) + + longer_channel_device_percentage_uncore * + g_tp.peri_global.long_channel_leakage_reduction; + } + else if (device_ty == LLC_device) { + long_channel_device_reduction = + (1 - longer_channel_device_percentage_llc) + + longer_channel_device_percentage_llc * + g_tp.peri_global.long_channel_leakage_reduction; + } + else { + cout << "unknown device category" << endl; + exit(0); + } + + return long_channel_device_reduction; +} + +double power_gating_leakage_reduction(bool retain_state) { + double state_retain_deduction = 1 - 0.43; + + double powergating_leakage_reduction; + + if (retain_state) { + powergating_leakage_reduction = + state_retain_deduction; // 0.55 based on most runs of cactip + } + else { + powergating_leakage_reduction = + g_tp.peri_global.Vcc_min / g_tp.peri_global.Vdd; + } + + return powergating_leakage_reduction; +} + +statsComponents operator+(const statsComponents &x, const statsComponents &y) { + statsComponents z; + + z.access = x.access + y.access; + z.hit = x.hit + y.hit; + z.miss = x.miss + y.miss; + + return z; +} + +statsComponents operator*(const statsComponents &x, double const *const y) { + statsComponents z; + + z.access = x.access * y[0]; + z.hit = x.hit * y[1]; + z.miss = x.miss * y[2]; + + return z; +} + +statsDef operator+(const statsDef &x, const statsDef &y) { + statsDef z; + + z.readAc = x.readAc + y.readAc; + z.writeAc = x.writeAc + y.writeAc; + z.searchAc = x.searchAc + y.searchAc; + return z; +} + +statsDef operator*(const statsDef &x, double const *const y) { + statsDef z; + + z.readAc = x.readAc * y; + z.writeAc = x.writeAc * y; + z.searchAc = x.searchAc * y; + return z; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/basic_components.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/basic_components.h new file mode 100644 index 0000000000..2fac864ce8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/basic_components.h @@ -0,0 +1,262 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef BASIC_COMPONENTS_H_ +#define BASIC_COMPONENTS_H_ + +#include +#include "XML_Parse.h" +#include "cacti/parameter.h" + +const double cdb_overhead = 1.1; + +enum FU_type { FPU, ALU, MUL }; + +enum Renaming_type { RAMbased, CAMbased }; + +enum Scheduler_type { PhysicalRegFile, ReservationStation }; + +enum cache_level { L2, L3, L1Directory, L2Directory }; + +enum MemoryCtrl_type { + MC, // memory controller + FLASHC // flash controller +}; + +enum Dir_type { + ST, // shadowed tag + DC, // directory cache + SBT, // static bank tag + NonDir + +}; + +enum Cache_policy { Write_through, Write_back }; + +enum Device_ty { Core_device, Uncore_device, LLC_device }; + +enum Core_type { OOO, Inorder }; + +class statsComponents { + public: + double access; + double hit; + double miss; + + statsComponents() : access(0), hit(0), miss(0) {} + statsComponents(const statsComponents &obj) { *this = obj; } + statsComponents &operator=(const statsComponents &rhs) { + access = rhs.access; + hit = rhs.hit; + miss = rhs.miss; + return *this; + } + void reset() { + access = 0; + hit = 0; + miss = 0; + } + + friend statsComponents operator+(const statsComponents &x, + const statsComponents &y); + friend statsComponents operator*(const statsComponents &x, + double const *const y); +}; + +class statsDef { + public: + statsComponents readAc; + statsComponents writeAc; + statsComponents searchAc; + + statsDef() : readAc(), writeAc(), searchAc() {} + void reset() { + readAc.reset(); + writeAc.reset(); + searchAc.reset(); + } + + friend statsDef operator+(const statsDef &x, const statsDef &y); + friend statsDef operator*(const statsDef &x, double const *const y); +}; + +double longer_channel_device_reduction(enum Device_ty device_ty = Core_device, + enum Core_type core_ty = Inorder); + +double power_gating_leakage_reduction(bool retain_state = false); + +class CoreDynParam { + public: + CoreDynParam(){}; + CoreDynParam(ParseXML *XML_interface, int ithCore_); + // :XML(XML_interface), + // ithCore(ithCore_) + // core_ty(inorder), + // rm_ty(CAMbased), + // scheu_ty(PhysicalRegFile), + // clockRate(1e9),//1GHz + // arch_ireg_width(32), + // arch_freg_width(32), + // phy_ireg_width(128), + // phy_freg_width(128), + // perThreadState(8), + // globalCheckpoint(32), + // instructionLength(32){}; + // ParseXML * XML; + bool opt_local; + bool x86; + bool Embedded; + enum Core_type core_ty; + enum Renaming_type rm_ty; + enum Scheduler_type scheu_ty; + double clockRate, executionTime; + int arch_ireg_width, arch_freg_width, phy_ireg_width, phy_freg_width, + hthread_width; + int num_IRF_entry, num_FRF_entry, num_ifreelist_entries, + num_ffreelist_entries; + int fetchW, decodeW, issueW, peak_issueW, commitW, peak_commitW, predictionW, + fp_issueW, fp_decodeW; + int perThreadState, globalCheckpoint, instruction_length, pc_width, + opcode_length, micro_opcode_length; + int num_hthreads, pipeline_stages, fp_pipeline_stages, num_pipelines, + num_fp_pipelines; + int num_alus, num_muls; + double num_fpus; + int int_data_width, fp_data_width, v_address_width, p_address_width; + double pipeline_duty_cycle, total_cycles, busy_cycles, idle_cycles; + bool regWindowing, multithreaded; + double pppm_lkg_multhread[4]; + double IFU_duty_cycle, BR_duty_cycle, LSU_duty_cycle, MemManU_I_duty_cycle, + MemManU_D_duty_cycle, ALU_duty_cycle, MUL_duty_cycle, FPU_duty_cycle, + ALU_cdb_duty_cycle, MUL_cdb_duty_cycle, FPU_cdb_duty_cycle; + double vdd; + double power_gating_vcc; + ~CoreDynParam(){}; +}; + +class CacheDynParam { + public: + CacheDynParam(){}; + CacheDynParam(ParseXML *XML_interface, int ithCache_); + string name; + enum Dir_type dir_ty; + double clockRate, executionTime; + double capacity, blockW, assoc, nbanks; + double throughput, latency; + double duty_cycle, dir_duty_cycle; + // double duty_cycle; + int missb_size, fu_size, prefetchb_size, wbb_size; + double vdd; + double power_gating_vcc; + ~CacheDynParam(){}; +}; + +class MCParam { + public: + MCParam(){}; + MCParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate, num_mcs, peakDataTransferRate, num_channels; + // double mcTEPowerperGhz; + // double mcPHYperGbit; + // double area; + int llcBlockSize, dataBusWidth, addressBusWidth; + int opcodeW; + int memAccesses; + int memRank; + int type; + double frontend_duty_cycle, duty_cycle, perc_load; + double executionTime, reads, writes; + bool LVDS, withPHY; + double vdd; + double power_gating_vcc; + ~MCParam(){}; +}; + +class NoCParam { + public: + NoCParam(){}; + NoCParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate; + int flit_size; + int input_ports, output_ports, min_ports, global_linked_ports; + int virtual_channel_per_port, input_buffer_entries_per_vc; + int horizontal_nodes, vertical_nodes, total_nodes; + double executionTime, total_access, link_throughput, link_latency, duty_cycle, + chip_coverage, route_over_perc; + bool has_global_link, type; + double vdd; + double power_gating_vcc; + ~NoCParam(){}; +}; + +class ProcParam { + public: + ProcParam(){}; + ProcParam(ParseXML *XML_interface, int ithCache_); + string name; + int numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir, numMC, numMCChannel; + bool homoCore, homoL2, homoL3, homoNOC, homoL1Dir, homoL2Dir; + double vdd; + double power_gating_vcc; + ~ProcParam(){}; +}; + +class NIUParam { + public: + NIUParam(){}; + NIUParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate; + int num_units; + int type; + double duty_cycle, perc_load; + double vdd; + double power_gating_vcc; + ~NIUParam(){}; +}; + +class PCIeParam { + public: + PCIeParam(){}; + PCIeParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate; + int num_channels, num_units; + bool withPHY; + int type; + double duty_cycle, perc_load; + double vdd; + double power_gating_vcc; + ~PCIeParam(){}; +}; +#endif /* BASIC_COMPONENTS_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/README b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/README new file mode 100644 index 0000000000..43ff59f27d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/README @@ -0,0 +1,131 @@ +----------------------------------------------------------- + ____ _ ____ _____ ___ ____ + / ___| / \ / ___|_ _|_ _| | _ \ + | | / _ \| | | | | |_____| |_) | + | |___ / ___ \ |___ | | | |_____| __/ + \____/_/ \_\____| |_| |___| |_| + + + A Tool to Model Caches/Memories +----------------------------------------------------------- + +CACTI is an analytical tool that takes a set of cache/memory para- +meters as input and calculates its access time, power, cycle +time, and area. +CACTI was originally developed by Dr. Jouppi and Dr. Wilton +in 1993 and since then it has undergone five major +revisions. + +About Cacti-P (contact: sheng.sli@gmail.com) +=================== +This is a special version of Cacti based on Cacti6.5 release for McPAT. The major +changes of this special Cacti, called Cacti-P in this distro, +(compared to cacti6.5) includes the following new features. +The inclosed Cacti-P can run stand-alone if users want to use these features. + + * CAM and fully associative cache modeling + * Improved leakage power modeling with consideration of device/gate topology + * long channel device for reduce sub-threshold leakage power + * Sleep transistor based power-gating modeling + * gate leakage power + * Support user defined voltage supply (Vdd) + * Dynamic voltage scaling (DVS) + +In the output results, either ITRS default or user defined vdd is used as baseline supply vdd. +When DVS is enabled, this vdd is denoted as @DVS_Level0. The user defined DVS voltage levels are +denoted as @DVS_Level1~@DVS_Leveln. + +Power-gating and DVS cannot happen at the same time. Because power-gating happens when circuit is idle, +while DVS happens when circuit is active. +When waking up from power-gating status, it is assumed that the system will first wakeup to DVS0 (full speed) state, +if DVS is enabled in the system. + +For complete documentation of Cacti-P, please refer to the following paper, +"CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques", +that appeared in ICCAD2011. Please cite the paper, if you use +Cacti-P in your work. The bibtex entry is provided below for your convenience. + +@inproceedings{cacti-p:iccad, + author = {Sheng Li and Ke Chen and Jung Ho Ahn and Jay B. Brockman and Norman P. Jouppi}, + title = {CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques}, + booktitle = {ICCAD: International Conference on Computer-Aided Design}, + year = {2011}, + pages = {694-701}, +} + +List of features (version 1-6.5): +=============================== +The following is the list of features supported by the tool. + +* Power, delay, area, and cycle time model for + direct mapped caches + set-associative caches + fully associative caches + Embedded DRAM memories + Commodity DRAM memories + +* Support for modeling multi-ported uniform cache access (UCA) + and multi-banked, multi-ported non-uniform cache access (NUCA). + +* Leakage power calculation that also considers the operating + temperature of the cache. + +* Router power model. + +* Interconnect model with different delay, power, and area + properties including low-swing wire model. + +* An interface to perform trade-off analysis involving power, delay, + area, and bandwidth. + +* All process specific values used by the tool are obtained + from ITRS and currently, the tool supports 90nm, 65nm, 45nm, + and 32nm technology nodes. + +Version 6.5 has a new c++ code base and includes numerous bug fixes. +CACTI 5.3 and 6.0 activate an entire row of mats to read/write a single +block of data. This technique improves reliability at the cost of +power. CACTI 6.5 activates minimum number of mats just enough to retrieve +a block to minimize power. + +How to use the tool? +==================== +Prior versions of CACTI take input parameters such as cache +size and technology node as a set of command line arguments. +To avoid a long list of command line arguments, +CACTI 6.5 lets users specify their cache model in a more +detailed manner by using a config file (cache.cfg). + +-> define the cache model using cache.cfg +-> run the "cacti" binary <./cacti -infile cache.cfg> + +CACTI6.5 also provides a command line interface similar to earlier versions +of CACTI. The command line interface can be used as + +./cacti cache_size line_size associativity rw_ports excl_read_ports excl_write_ports + single_ended_read_ports search_ports banks tech_node output_width specific_tag tag_width + access_mode cache main_mem obj_func_delay obj_func_dynamic_power obj_func_leakage_power + obj_func_cycle_time obj_func_area dev_func_delay dev_func_dynamic_power dev_func_leakage_power + dev_func_area dev_func_cycle_time ed_ed2_none temp wt data_arr_ram_cell_tech_flavor_in + data_arr_peri_global_tech_flavor_in tag_arr_ram_cell_tech_flavor_in tag_arr_peri_global_tech_flavor_in + interconnect_projection_type_in wire_inside_mat_type_in wire_outside_mat_type_in + REPEATERS_IN_HTREE_SEGMENTS_in VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in + BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in PAGE_SIZE_BITS_in BURST_LENGTH_in + INTERNAL_PREFETCH_WIDTH_in force_wiretype wiretype force_config ndwl ndbl nspd ndcm + ndsam1 ndsam2 ecc + +For complete documentation of the tool, please refer CACTI-5.3 and 6.0 +technical reports and the following paper, +"Optimizing NUCA Organizations and Wiring Alternatives for +Large Caches With CACTI 6.0", that appears in MICRO 2007. + +We are still improving the tool and refining the code. If you +have any comments, questions, or suggestions please write to +us. + +Naveen Muralimanohar Jung Ho Ahn Sheng Li +naveen.muralimanohar@hp.com gajh@snu.ac.kr sheng.li@hp.com + + + + diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/Ucache.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/Ucache.cc new file mode 100644 index 0000000000..74750568b9 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/Ucache.cc @@ -0,0 +1,1140 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include + +#include "Ucache.h" +#include "area.h" +#include "bank.h" +#include "basic_circuit.h" +#include "component.h" +#include "const.h" +#include "decoder.h" +#include "parameter.h" +#include "subarray.h" +#include "uca.h" + +#include +#include +#include +#include + +using namespace std; + +#ifndef NTHREADS +#define NTHREADS 4 +#endif + +namespace cacti { + +const uint32_t nthreads = NTHREADS; + +void min_values_t::update_min_values(const min_values_t *val) { + min_delay = (min_delay > val->min_delay) ? val->min_delay : min_delay; + min_dyn = (min_dyn > val->min_dyn) ? val->min_dyn : min_dyn; + min_leakage = + (min_leakage > val->min_leakage) ? val->min_leakage : min_leakage; + min_area = (min_area > val->min_area) ? val->min_area : min_area; + min_cyc = (min_cyc > val->min_cyc) ? val->min_cyc : min_cyc; +} + +void min_values_t::update_min_values(const uca_org_t &res) { + min_delay = (min_delay > res.access_time) ? res.access_time : min_delay; + min_dyn = + (min_dyn > res.power.readOp.dynamic) ? res.power.readOp.dynamic : min_dyn; + min_leakage = (min_leakage > res.power.readOp.leakage) + ? res.power.readOp.leakage + : min_leakage; + min_area = (min_area > res.area) ? res.area : min_area; + min_cyc = (min_cyc > res.cycle_time) ? res.cycle_time : min_cyc; +} + +void min_values_t::update_min_values(const nuca_org_t *res) { + min_delay = + (min_delay > res->nuca_pda.delay) ? res->nuca_pda.delay : min_delay; + min_dyn = (min_dyn > res->nuca_pda.power.readOp.dynamic) + ? res->nuca_pda.power.readOp.dynamic + : min_dyn; + min_leakage = (min_leakage > res->nuca_pda.power.readOp.leakage) + ? res->nuca_pda.power.readOp.leakage + : min_leakage; + min_area = (min_area > res->nuca_pda.area.get_area()) + ? res->nuca_pda.area.get_area() + : min_area; + min_cyc = + (min_cyc > res->nuca_pda.cycle_time) ? res->nuca_pda.cycle_time : min_cyc; +} + +void min_values_t::update_min_values(const mem_array *res) { + min_delay = (min_delay > res->access_time) ? res->access_time : min_delay; + min_dyn = (min_dyn > res->power.readOp.dynamic) ? res->power.readOp.dynamic + : min_dyn; + min_leakage = (min_leakage > res->power.readOp.leakage) + ? res->power.readOp.leakage + : min_leakage; + min_area = (min_area > res->area) ? res->area : min_area; + min_cyc = (min_cyc > res->cycle_time) ? res->cycle_time : min_cyc; +} + +void calc_time_mt_wrapper(void *void_obj) { + calc_time_mt_wrapper_struct *calc_obj = + (calc_time_mt_wrapper_struct *)void_obj; + uint32_t tid = calc_obj->tid; + list &data_arr = calc_obj->data_arr; + list &tag_arr = calc_obj->tag_arr; + bool is_tag = calc_obj->is_tag; + bool pure_ram = calc_obj->pure_ram; + bool pure_cam = calc_obj->pure_cam; + bool is_main_mem = calc_obj->is_main_mem; + double Nspd_min = calc_obj->Nspd_min; + min_values_t *data_res = calc_obj->data_res; + min_values_t *tag_res = calc_obj->tag_res; + + data_arr.clear(); + data_arr.push_back(new mem_array); + tag_arr.clear(); + tag_arr.push_back(new mem_array); + + uint32_t Ndwl_niter = _log2(MAXDATAN) + 1; + uint32_t Ndbl_niter = _log2(MAXDATAN) + 1; + uint32_t Ndcm_niter = _log2(MAX_COL_MUX) + 1; + uint32_t niter = Ndwl_niter * Ndbl_niter * Ndcm_niter; + + bool is_valid_partition; + int wt_min, wt_max; + + if (g_ip->force_wiretype) { + if (g_ip->wt == 0) { + wt_min = Low_swing; + wt_max = Low_swing; + } + else { + wt_min = Global; + wt_max = Low_swing - 1; + } + } + else { + wt_min = Global; + wt_max = Low_swing; + } + + for (double Nspd = Nspd_min; Nspd <= MAXDATASPD; Nspd *= 2) { + for (int wr = wt_min; wr <= wt_max; wr++) { + for (uint32_t iter = tid; iter < niter; iter += nthreads) { + // reconstruct Ndwl, Ndbl, Ndcm + unsigned int Ndwl = 1 << (iter / (Ndbl_niter * Ndcm_niter)); + unsigned int Ndbl = 1 << ((iter / (Ndcm_niter)) % Ndbl_niter); + unsigned int Ndcm = 1 << (iter % Ndcm_niter); + for (unsigned int Ndsam_lev_1 = 1; Ndsam_lev_1 <= MAX_COL_MUX; + Ndsam_lev_1 *= 2) { + for (unsigned int Ndsam_lev_2 = 1; Ndsam_lev_2 <= MAX_COL_MUX; + Ndsam_lev_2 *= 2) { + // for debuging + if (g_ip->force_cache_config && is_tag == false) { + wr = g_ip->wt; + Ndwl = g_ip->ndwl; + Ndbl = g_ip->ndbl; + Ndcm = g_ip->ndcm; + if (g_ip->nspd != 0) { + Nspd = g_ip->nspd; + } + if (g_ip->ndsam1 != 0) { + Ndsam_lev_1 = g_ip->ndsam1; + Ndsam_lev_2 = g_ip->ndsam2; + } + } + + if (is_tag == true) { + is_valid_partition = + calculate_time(is_tag, pure_ram, pure_cam, Nspd, Ndwl, Ndbl, + Ndcm, Ndsam_lev_1, Ndsam_lev_2, tag_arr.back(), + 0, NULL, NULL, is_main_mem); + } + // If it's a fully-associative cache, the data array partition + // parameters are identical to that of the tag array, so compute + // data array partition properties also here. + if (is_tag == false || g_ip->fully_assoc) { + is_valid_partition = + calculate_time(is_tag /*false*/, pure_ram, pure_cam, Nspd, + Ndwl, Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, + data_arr.back(), 0, NULL, NULL, is_main_mem); + } + + if (is_valid_partition) { + if (is_tag == true) { + tag_arr.back()->wt = (enum Wire_type)wr; + tag_res->update_min_values(tag_arr.back()); + tag_arr.push_back(new mem_array); + } + if (is_tag == false || g_ip->fully_assoc) { + data_arr.back()->wt = (enum Wire_type)wr; + data_res->update_min_values(data_arr.back()); + data_arr.push_back(new mem_array); + } + } + + if (g_ip->force_cache_config && is_tag == false) { + wr = wt_max; + iter = niter; + if (g_ip->nspd != 0) { + Nspd = MAXDATASPD; + } + if (g_ip->ndsam1 != 0) { + Ndsam_lev_1 = MAX_COL_MUX + 1; + Ndsam_lev_2 = MAX_COL_MUX + 1; + } + } + } + } + } + } + } + + delete data_arr.back(); + delete tag_arr.back(); + data_arr.pop_back(); + tag_arr.pop_back(); +} + +bool calculate_time(bool is_tag, int pure_ram, bool pure_cam, double Nspd, + unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, + mem_array *ptr_array, int flag_results_populate, + results_mem_array *ptr_results, uca_org_t *ptr_fin_res, + bool is_main_mem) { + DynamicParameter dyn_p(is_tag, pure_ram, pure_cam, Nspd, Ndwl, Ndbl, Ndcm, + Ndsam_lev_1, Ndsam_lev_2, is_main_mem); + + if (dyn_p.is_valid == false) { + return false; + } + + UCA *uca = new UCA(dyn_p); + + if (flag_results_populate) { // For the final solution, populate the + // ptr_results data structure -- TODO: copy + // only necessary variables + } + else { + collect_uca_results(Nspd, Ndwl, Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, uca, + ptr_array, is_main_mem); + } + + delete uca; + return true; +} + +void collect_uca_results( + // bool is_tag, + // int pure_ram, + // bool pure_cam, + double Nspd, unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, UCA const *const uca, + mem_array *const ptr_array, + // int flag_results_populate, + // results_mem_array *ptr_results, + // uca_org_t *ptr_fin_res, + bool is_main_mem) { + int num_act_mats_hor_dir = uca->bank.dp.num_act_mats_hor_dir; + int num_mats = uca->bank.dp.num_mats; + bool is_fa = uca->bank.dp.fully_assoc; + bool pure_cam = uca->bank.dp.pure_cam; + ptr_array->Ndwl = Ndwl; + ptr_array->Ndbl = Ndbl; + ptr_array->Nspd = Nspd; + ptr_array->deg_bl_muxing = uca->bank.dp.deg_bl_muxing; + ptr_array->Ndsam_lev_1 = Ndsam_lev_1; + ptr_array->Ndsam_lev_2 = Ndsam_lev_2; + ptr_array->access_time = uca->access_time; + ptr_array->cycle_time = uca->cycle_time; + ptr_array->multisubbank_interleave_cycle_time = + uca->multisubbank_interleave_cycle_time; + ptr_array->area_ram_cells = uca->area_all_dataramcells; + ptr_array->area = uca->area.get_area(); + ptr_array->height = uca->area.h; + ptr_array->width = uca->area.w; + ptr_array->mat_height = uca->bank.mat.area.h; + ptr_array->mat_length = uca->bank.mat.area.w; + ptr_array->subarray_height = uca->bank.mat.subarray.area.h; + ptr_array->subarray_length = uca->bank.mat.subarray.area.w; + ptr_array->power = uca->power; + ptr_array->delay_senseamp_mux_decoder = + MAX(uca->delay_array_to_sa_mux_lev_1_decoder, + uca->delay_array_to_sa_mux_lev_2_decoder); + ptr_array->delay_before_subarray_output_driver = + uca->delay_before_subarray_output_driver; + ptr_array->delay_from_subarray_output_driver_to_output = + uca->delay_from_subarray_out_drv_to_out; + + ptr_array->delay_route_to_bank = uca->htree_in_add->delay; + ptr_array->delay_input_htree = uca->bank.htree_in_add->delay; + ptr_array->delay_row_predecode_driver_and_block = + uca->bank.mat.r_predec->delay; + ptr_array->delay_row_decoder = uca->bank.mat.row_dec->delay; + ptr_array->delay_bitlines = uca->bank.mat.delay_bitline; + ptr_array->delay_matchlines = uca->bank.mat.delay_matchchline; + ptr_array->delay_sense_amp = uca->bank.mat.delay_sa; + ptr_array->delay_subarray_output_driver = + uca->bank.mat.delay_subarray_out_drv_htree; + ptr_array->delay_dout_htree = uca->bank.htree_out_data->delay; + ptr_array->delay_comparator = uca->bank.mat.delay_comparator; + + ptr_array->all_banks_height = uca->area.h; + ptr_array->all_banks_width = uca->area.w; + ptr_array->area_efficiency = + uca->area_all_dataramcells * 100 / (uca->area.get_area()); + + ptr_array->power_routing_to_bank = uca->power_routing_to_bank; + ptr_array->power_addr_input_htree = uca->bank.htree_in_add->power; + ptr_array->power_data_input_htree = uca->bank.htree_in_data->power; + // cout<<"power_data_input_htree"<bank.htree_in_data->power.readOp.leakage<power_data_output_htree = uca->bank.htree_out_data->power; + // cout<<"power_data_output_htree"<bank.htree_out_data->power.readOp.leakage<power_row_predecoder_drivers = + uca->bank.mat.r_predec->driver_power; + ptr_array->power_row_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_row_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_row_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_row_predecoder_blocks = uca->bank.mat.r_predec->block_power; + ptr_array->power_row_predecoder_blocks.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_row_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_row_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_row_decoders = uca->bank.mat.power_row_decoders; + ptr_array->power_row_decoders.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_row_decoders.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_row_decoders.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_bit_mux_predecoder_drivers = + uca->bank.mat.b_mux_predec->driver_power; + ptr_array->power_bit_mux_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_bit_mux_predecoder_blocks = + uca->bank.mat.b_mux_predec->block_power; + ptr_array->power_bit_mux_predecoder_blocks.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_bit_mux_decoders = uca->bank.mat.power_bit_mux_decoders; + ptr_array->power_bit_mux_decoders.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bit_mux_decoders.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bit_mux_decoders.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers = + uca->bank.mat.sa_mux_lev_1_predec->driver_power; + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks = + uca->bank.mat.sa_mux_lev_1_predec->block_power; + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_1_decoders = + uca->bank.mat.power_sa_mux_lev_1_decoders; + ptr_array->power_senseamp_mux_lev_1_decoders.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_decoders.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_decoders.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers = + uca->bank.mat.sa_mux_lev_2_predec->driver_power; + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks = + uca->bank.mat.sa_mux_lev_2_predec->block_power; + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_2_decoders = + uca->bank.mat.power_sa_mux_lev_2_decoders; + ptr_array->power_senseamp_mux_lev_2_decoders.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_decoders.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_decoders.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_bitlines = uca->bank.mat.power_bitline; + ptr_array->power_bitlines.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bitlines.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bitlines.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_sense_amps = uca->bank.mat.power_sa; + ptr_array->power_sense_amps.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_sense_amps.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_sense_amps.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_prechg_eq_drivers = uca->bank.mat.power_bl_precharge_eq_drv; + ptr_array->power_prechg_eq_drivers.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_prechg_eq_drivers.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_prechg_eq_drivers.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_output_drivers_at_subarray = + uca->bank.mat.power_subarray_out_drv; + ptr_array->power_output_drivers_at_subarray.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_output_drivers_at_subarray.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_output_drivers_at_subarray.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_comparators = uca->bank.mat.power_comparator; + ptr_array->power_comparators.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_comparators.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_comparators.searchOp.dynamic *= num_act_mats_hor_dir; + + // cout << " num of mats: " << dyn_p.num_mats << endl; + if (is_fa || pure_cam) { + ptr_array->power_htree_in_search = uca->bank.htree_in_search->power; + // cout<<"power_htree_in_search"<bank.htree_in_search->power.readOp.leakage<power_htree_out_search = uca->bank.htree_out_search->power; + // cout<<"power_htree_out_search"<bank.htree_out_search->power.readOp.leakage<power_searchline = uca->bank.mat.power_searchline; + // cout<<"power_searchlineh"<bank.mat.power_searchline.readOp.leakage<power_searchline.searchOp.dynamic *= num_mats; + ptr_array->power_searchline_precharge = + uca->bank.mat.power_searchline_precharge; + ptr_array->power_searchline_precharge.searchOp.dynamic *= num_mats; + ptr_array->power_matchlines = uca->bank.mat.power_matchline; + ptr_array->power_matchlines.searchOp.dynamic *= num_mats; + ptr_array->power_matchline_precharge = + uca->bank.mat.power_matchline_precharge; + ptr_array->power_matchline_precharge.searchOp.dynamic *= num_mats; + ptr_array->power_matchline_to_wordline_drv = + uca->bank.mat.power_ml_to_ram_wl_drv; + // cout<<"power_matchline.searchOp.leakage"<bank.mat.power_matchline.searchOp.leakage<activate_energy = uca->activate_energy; + ptr_array->read_energy = uca->read_energy; + ptr_array->write_energy = uca->write_energy; + ptr_array->precharge_energy = uca->precharge_energy; + ptr_array->refresh_power = uca->refresh_power; + ptr_array->leak_power_subbank_closed_page = + uca->leak_power_subbank_closed_page; + ptr_array->leak_power_subbank_open_page = uca->leak_power_subbank_open_page; + ptr_array->leak_power_request_and_reply_networks = + uca->leak_power_request_and_reply_networks; + + ptr_array->precharge_delay = uca->precharge_delay; + + // cout<<"power_matchline.searchOp.leakage"<bank.mat.<bank.mat.subarray.get_total_cell_area()<array_leakage = uca->bank.array_leakage; + ptr_array->wl_leakage = uca->bank.wl_leakage; + ptr_array->cl_leakage = uca->bank.cl_leakage; + if (g_ip->power_gating) { + ptr_array->sram_sleep_tx_width = uca->bank.mat.sram_sleep_tx->width; + ptr_array->sram_sleep_tx_area = uca->bank.mat.array_sleep_tx_area; + ptr_array->sram_sleep_wakeup_latency = uca->bank.mat.array_wakeup_t; + ptr_array->sram_sleep_wakeup_energy = + uca->bank.mat.array_wakeup_e.readOp.dynamic; + + ptr_array->wl_sleep_tx_width = uca->bank.mat.row_dec->sleeptx->width; + ptr_array->wl_sleep_tx_area = uca->bank.mat.wl_sleep_tx_area; + ptr_array->wl_sleep_wakeup_latency = uca->bank.mat.wl_wakeup_t; + ptr_array->wl_sleep_wakeup_energy = + uca->bank.mat.wl_wakeup_e.readOp.dynamic; + + ptr_array->bl_floating_wakeup_latency = uca->bank.mat.blfloating_wakeup_t; + ptr_array->bl_floating_wakeup_energy = + uca->bank.mat.blfloating_wakeup_e.readOp.dynamic; + } + + ptr_array->num_active_mats = uca->bank.dp.num_act_mats_hor_dir; + ptr_array->num_submarray_mats = uca->bank.mat.num_subarrays_per_mat; + // cout<<"array_leakage"<array_leakage<wl_leakage<cl_leakage<long_channel_leakage_reduction_periperal = + uca->long_channel_leakage_reduction_periperal; + ptr_array->long_channel_leakage_reduction_memcell = + uca->long_channel_leakage_reduction_memcell; +} + +bool check_uca_org(uca_org_t &u, min_values_t *minval) { + if (((u.access_time - minval->min_delay) * 100 / minval->min_delay) > + g_ip->delay_dev) { + return false; + } + if (((u.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn) * 100 > + g_ip->dynamic_power_dev) { + return false; + } + if (((u.power.readOp.leakage - minval->min_leakage) / minval->min_leakage) * + 100 > + g_ip->leakage_power_dev) { + return false; + } + if (((u.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > + g_ip->cycle_time_dev) { + return false; + } + if (((u.area - minval->min_area) / minval->min_area) * 100 > g_ip->area_dev) { + return false; + } + return true; +} + +bool check_mem_org(mem_array &u, const min_values_t *minval) { + if (((u.access_time - minval->min_delay) * 100 / minval->min_delay) > + g_ip->delay_dev) { + return false; + } + if (((u.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn) * 100 > + g_ip->dynamic_power_dev) { + return false; + } + if (((u.power.readOp.leakage - minval->min_leakage) / minval->min_leakage) * + 100 > + g_ip->leakage_power_dev) { + return false; + } + if (((u.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > + g_ip->cycle_time_dev) { + return false; + } + if (((u.area - minval->min_area) / minval->min_area) * 100 > g_ip->area_dev) { + return false; + } + return true; +} + +void find_optimal_uca(uca_org_t *res, min_values_t *minval, + list &ulist) { + double cost = 0; + double min_cost = BIGNUM; + float d, a, dp, lp, c; + + dp = g_ip->dynamic_power_wt; + lp = g_ip->leakage_power_wt; + a = g_ip->area_wt; + d = g_ip->delay_wt; + c = g_ip->cycle_time_wt; + + if (ulist.empty() == true) { + cout << "ERROR: no valid cache organizations found" << endl; + exit(0); + } + + for (list::iterator niter = ulist.begin(); niter != ulist.end(); + niter++) { + if (g_ip->ed == 1) { + cost = ((niter)->access_time / minval->min_delay) * + ((niter)->power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + *res = (*(niter)); + } + } + else if (g_ip->ed == 2) { + cost = ((niter)->access_time / minval->min_delay) * + ((niter)->access_time / minval->min_delay) * + ((niter)->power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + *res = (*(niter)); + } + } + else { + /* + * check whether the current organization + * meets the input deviation constraints + */ + bool v = check_uca_org(*niter, minval); + // if (minval->min_leakage == 0) minval->min_leakage = 0.1; //FIXME remove + // this after leakage modeling + + if (v) { + cost = (d * ((niter)->access_time / minval->min_delay) + + c * ((niter)->cycle_time / minval->min_cyc) + + dp * ((niter)->power.readOp.dynamic / minval->min_dyn) + + lp * ((niter)->power.readOp.leakage / minval->min_leakage) + + a * ((niter)->area / minval->min_area)); + // fprintf(stderr, "cost = %g\n", cost); + + if (min_cost > cost) { + min_cost = cost; + *res = (*(niter)); + niter = ulist.erase(niter); + if (niter != ulist.begin()) + niter--; + } + } + else { + niter = ulist.erase(niter); + if (niter != ulist.begin()) + niter--; + } + } + } + + if (min_cost == BIGNUM) { + cout << "ERROR: no cache organizations met optimization criteria" << endl; + exit(0); + } +} + +void filter_tag_arr(const min_values_t *min, list &list) { + double cost = BIGNUM; + double cur_cost; + double wt_delay = g_ip->delay_wt, wt_dyn = g_ip->dynamic_power_wt, + wt_leakage = g_ip->leakage_power_wt, wt_cyc = g_ip->cycle_time_wt, + wt_area = g_ip->area_wt; + mem_array *res = NULL; + + if (list.empty() == true) { + cout << "ERROR: no valid tag organizations found" << endl; + exit(1); + } + + while (list.empty() != true) { + bool v = check_mem_org(*list.back(), min); + if (v) { + cur_cost = + wt_delay * (list.back()->access_time / min->min_delay) + + wt_dyn * (list.back()->power.readOp.dynamic / min->min_dyn) + + wt_leakage * (list.back()->power.readOp.leakage / min->min_leakage) + + wt_area * (list.back()->area / min->min_area) + + wt_cyc * (list.back()->cycle_time / min->min_cyc); + } + else { + cur_cost = BIGNUM; + } + if (cur_cost < cost) { + if (res != NULL) { + delete res; + } + cost = cur_cost; + res = list.back(); + } + else { + delete list.back(); + } + list.pop_back(); + } + if (!res) { + cout << "ERROR: no valid tag organizations found" << endl; + exit(0); + } + + list.push_back(res); +} + +void filter_data_arr(list &curr_list) { + if (curr_list.empty() == true) { + cout << "ERROR: no valid data array organizations found" << endl; + exit(1); + } + + list::iterator iter; + + for (iter = curr_list.begin(); iter != curr_list.end(); ++iter) { + mem_array *m = *iter; + + if (m == NULL) + exit(1); + + if (((m->access_time - m->arr_min->min_delay) / m->arr_min->min_delay > + 0.5) && + ((m->power.readOp.dynamic - m->arr_min->min_dyn) / m->arr_min->min_dyn > + 0.5)) { + delete m; + iter = curr_list.erase(iter); + iter--; + } + } +} + +/* + * Performs exhaustive search across different sub-array sizes, + * wire types and aspect ratios to find an optimal UCA organization + * 1. First different valid tag array organizations are calculated + * and stored in tag_arr array + * 2. The exhaustive search is repeated to find valid data array + * organizations and stored in data_arr array + * 3. Cache area, delay, power, and cycle time for different + * cache organizations are calculated based on the + * above results + * 4. Cache model with least cost is picked from sol_list + */ +void solve(uca_org_t *fin_res) { + // bool is_dram = false; + int pure_ram = g_ip->pure_ram; + bool pure_cam = g_ip->pure_cam; + + init_tech_params(g_ip->F_sz_um, false); + + list tag_arr(0); + list data_arr(0); + list::iterator miter; + list sol_list(1, uca_org_t()); + + fin_res->tag_array.access_time = 0; + fin_res->tag_array.Ndwl = 0; + fin_res->tag_array.Ndbl = 0; + fin_res->tag_array.Nspd = 0; + fin_res->tag_array.deg_bl_muxing = 0; + fin_res->tag_array.Ndsam_lev_1 = 0; + fin_res->tag_array.Ndsam_lev_2 = 0; + + // distribute calculate_time() execution to multiple threads + calc_time_mt_wrapper_struct *calc_array = + new calc_time_mt_wrapper_struct[nthreads]; + std::thread threads[nthreads]; + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].tid = t; + calc_array[t].pure_ram = pure_ram; + calc_array[t].pure_cam = pure_cam; + calc_array[t].data_res = new min_values_t(); + calc_array[t].tag_res = new min_values_t(); + } + + bool is_tag; + // uint32_t ram_cell_tech_type; + + // If it's a cache, first calculate the area, delay and power for all tag + // array partitions. + if (!(pure_ram || pure_cam || g_ip->fully_assoc)) { // cache + is_tag = true; + // ram_cell_tech_type = g_ip->tag_arr_ram_cell_tech_type; + // is_dram = + // ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == + // comm_dram)); + init_tech_params(g_ip->F_sz_um, is_tag); + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].is_tag = is_tag; + calc_array[t].is_main_mem = false; + calc_array[t].Nspd_min = 0.125; + threads[t] = std::thread(calc_time_mt_wrapper,(void *)(&(calc_array[t]))); + } + + for (uint32_t t = 0; t < nthreads; t++) { + threads[t].join(); + } + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].data_arr.sort(mem_array::lt); + data_arr.merge(calc_array[t].data_arr, mem_array::lt); + calc_array[t].tag_arr.sort(mem_array::lt); + tag_arr.merge(calc_array[t].tag_arr, mem_array::lt); + } + } + + // calculate the area, delay and power for all data array partitions (for + // cache or plain RAM). + // if (!g_ip->fully_assoc) + // {//in the new cacti, cam, fully_associative cache are processed as single + // array in the data portion + is_tag = false; + // ram_cell_tech_type = g_ip->data_arr_ram_cell_tech_type; + // is_dram = + // ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram)); + init_tech_params(g_ip->F_sz_um, is_tag); + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].is_tag = is_tag; + calc_array[t].is_main_mem = g_ip->is_main_mem; + if (!(pure_cam || g_ip->fully_assoc)) { + calc_array[t].Nspd_min = + (double)(g_ip->out_w) / (double)(g_ip->block_sz * 8); + } + else { + calc_array[t].Nspd_min = 1; + } + + threads[t] = std::thread(calc_time_mt_wrapper,(void *)(&(calc_array[t]))); + } + + for (uint32_t t = 0; t < nthreads; t++) { + threads[t].join(); + } + + data_arr.clear(); + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].data_arr.sort(mem_array::lt); + data_arr.merge(calc_array[t].data_arr, mem_array::lt); + } + // } + + min_values_t *d_min = new min_values_t(); + min_values_t *t_min = new min_values_t(); + min_values_t *cache_min = new min_values_t(); + + for (uint32_t t = 0; t < nthreads; t++) { + d_min->update_min_values(calc_array[t].data_res); + t_min->update_min_values(calc_array[t].tag_res); + } + + for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { + (*miter)->arr_min = d_min; + } + + // cout << data_arr.size() << "\t" << tag_arr.size() <<" before\n"; + filter_data_arr(data_arr); + if (!(pure_ram || pure_cam || g_ip->fully_assoc)) { + filter_tag_arr(t_min, tag_arr); + } + // cout << data_arr.size() << "\t" << tag_arr.size() <<" after\n"; + + if (pure_ram || pure_cam || g_ip->fully_assoc) { + for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { + uca_org_t &curr_org = sol_list.back(); // essentially adds value to + // sol_list, with no extra memory + // copying. + curr_org.tag_array2 = NULL; + curr_org.data_array2 = (*miter); + + curr_org.find_delay(); + curr_org.find_energy(); + curr_org.find_area(); + curr_org.find_cyc(); + + // update min values for the entire cache + cache_min->update_min_values(curr_org); + + sol_list.push_back(uca_org_t()); // add a new node to the back + } + } + else { + while (tag_arr.empty() != true) { + mem_array *arr_temp = (tag_arr.back()); + // delete tag_arr.back(); + tag_arr + .pop_back(); // this causes double free problem if uca_org_t has a + // destructor to release all contained pointers---when + // called by sol_list.clear(); so uca_org_t does not + // use destructor to delete contained pointers + + for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { + uca_org_t &curr_org = sol_list.back(); + curr_org.tag_array2 = arr_temp; + curr_org.data_array2 = + (*miter); // try all combinations of tag and data array + + curr_org.find_delay(); + curr_org.find_energy(); + curr_org.find_area(); + curr_org.find_cyc(); + + // update min values for the entire cache + cache_min->update_min_values(curr_org); + + sol_list.push_back(uca_org_t()); + } + } + } + + sol_list.pop_back(); // delete the last unused node added in the loop above + + find_optimal_uca(fin_res, cache_min, sol_list); + + sol_list.clear(); + + for (miter = data_arr.begin(); miter != data_arr.end(); ++miter) { + if (*miter != fin_res->data_array2) { + delete *miter; + } + } + data_arr.clear(); + + for (uint32_t t = 0; t < nthreads; t++) { + delete calc_array[t].data_res; + delete calc_array[t].tag_res; + } + + delete[] calc_array; + delete cache_min; + delete d_min; + delete t_min; +} + +void update_dvs(uca_org_t *fin_res) { + if (fin_res->tag_array2 || fin_res->data_array2) { + // Wire::print_wire(); + Wire winit; // init before changing dvs + // fin_res->uca_q = vector(g_ip->dvs_voltage.size()); + for (unsigned int i = 0; i < g_ip->dvs_voltage.size(); i++) { + fin_res->uca_q.push_back(new uca_org_t()); + + g_ip->hp_Vdd = g_ip->dvs_voltage[i]; + g_ip->specific_hp_vdd = true; + g_ip->lstp_Vdd = g_ip->dvs_voltage[i]; + g_ip->specific_lstp_vdd = true; + g_ip->lop_Vdd = g_ip->dvs_voltage[i]; + g_ip->specific_lop_vdd = true; + // g_ip->power_gating = false; + // g_ip->bitline_floating = false; + // g_ip->wl_power_gated = false; + // g_ip->interconect_power_gated = false; + // g_ip->cl_power_gated = false; + // g_ip->array_power_gated = false; + + init_tech_params(g_ip->F_sz_um, true); + winit.wire_dvs_update(); // Wire::wire_dvs_update();//Wire winit (1,1, + // false); + // Wire::print_wire(); + + if (fin_res->tag_array2) { + DynamicParameter tag_arr_dyn_p( + true, g_ip->pure_ram, g_ip->pure_cam, fin_res->tag_array2->Nspd, + fin_res->tag_array2->Ndwl, fin_res->tag_array2->Ndbl, + fin_res->tag_array2->deg_bl_muxing, + fin_res->tag_array2->Ndsam_lev_1, fin_res->tag_array2->Ndsam_lev_2, + g_ip->is_main_mem); + if (tag_arr_dyn_p.is_valid) { + UCA *tag_arr = new UCA(tag_arr_dyn_p); + fin_res->uca_q[i]->tag_array2 = new mem_array(); + + collect_uca_results( + fin_res->tag_array2->Nspd, fin_res->tag_array2->Ndwl, + fin_res->tag_array2->Ndbl, fin_res->tag_array2->deg_bl_muxing, + fin_res->tag_array2->Ndsam_lev_1, + fin_res->tag_array2->Ndsam_lev_2, tag_arr, + fin_res->uca_q[i]->tag_array2, g_ip->is_main_mem); + delete tag_arr; + } + } + DynamicParameter data_arr_dyn_p( + false, g_ip->pure_ram, g_ip->pure_cam, fin_res->data_array2->Nspd, + fin_res->data_array2->Ndwl, fin_res->data_array2->Ndbl, + fin_res->data_array2->deg_bl_muxing, + fin_res->data_array2->Ndsam_lev_1, fin_res->data_array2->Ndsam_lev_2, + g_ip->is_main_mem); + if (data_arr_dyn_p.is_valid) { + UCA *data_arr = new UCA(data_arr_dyn_p); + fin_res->uca_q[i]->data_array2 = new mem_array(); + collect_uca_results( + fin_res->data_array2->Nspd, fin_res->data_array2->Ndwl, + fin_res->data_array2->Ndbl, fin_res->data_array2->deg_bl_muxing, + fin_res->data_array2->Ndsam_lev_1, + fin_res->data_array2->Ndsam_lev_2, data_arr, + fin_res->uca_q[i]->data_array2, g_ip->is_main_mem); + delete data_arr; + } + + fin_res->uca_q[i]->find_delay(); + fin_res->uca_q[i]->find_energy(); + fin_res->uca_q[i]->find_area(); + fin_res->uca_q[i]->find_cyc(); + + // output_UCA(fin_res->uca_q[i]); + // Wire::print_wire(); + } + // reset input to original values in *.cfg file + g_ip->specific_hp_vdd = false; + g_ip->specific_lstp_vdd = false; + g_ip->specific_lop_vdd = false; + init_tech_params(g_ip->F_sz_um, true); + } + else { + cout << "ERROR: Cannot retrieve array structure for tag and data array" + << endl; + exit(1); + } +} + +void update_pg(uca_org_t *fin_res) { + if (fin_res->tag_array2 || fin_res->data_array2) { + Wire winit; + fin_res->uca_pg_reference = new uca_org_t(); + /* + if (i == 0) {g_ip->hp_Vdd = 0.8; } + else g_ip->hp_Vdd = 1.1; + g_ip->specific_hp_vdd = true; + cout<<"VDD=====" << g_ip->hp_Vdd <F_sz_um,true); + winit.wire_dvs_update();//Wire::wire_dvs_update();//Wire winit (1,1, + false); Wire::print_wire(); + */ + g_ip->array_power_gated = false; + g_ip->bitline_floating = false; + g_ip->wl_power_gated = false; + g_ip->cl_power_gated = false; + g_ip->interconect_power_gated = false; + g_ip->power_gating = false; + // winit.wire_dvs_update(); + // Wire::print_wire(); + // init_tech_params(g_ip->F_sz_um,true); + // winit.wire_dvs_update();//Wire::wire_dvs_update();//Wire winit + //(1,1, false); Wire::print_wire(); + if (fin_res->tag_array2) { + // init_tech_params(g_ip->F_sz_um,true); + DynamicParameter tag_arr_dyn_p( + true, g_ip->pure_ram, g_ip->pure_cam, fin_res->tag_array2->Nspd, + fin_res->tag_array2->Ndwl, fin_res->tag_array2->Ndbl, + fin_res->tag_array2->deg_bl_muxing, fin_res->tag_array2->Ndsam_lev_1, + fin_res->tag_array2->Ndsam_lev_2, g_ip->is_main_mem); + if (tag_arr_dyn_p.is_valid) { + UCA *tag_arr = new UCA(tag_arr_dyn_p); + fin_res->uca_pg_reference->tag_array2 = new mem_array(); + + collect_uca_results( + fin_res->tag_array2->Nspd, fin_res->tag_array2->Ndwl, + fin_res->tag_array2->Ndbl, fin_res->tag_array2->deg_bl_muxing, + fin_res->tag_array2->Ndsam_lev_1, fin_res->tag_array2->Ndsam_lev_2, + tag_arr, fin_res->uca_pg_reference->tag_array2, g_ip->is_main_mem); + delete tag_arr; + } + } + // init_tech_params(g_ip->F_sz_um,false); + DynamicParameter data_arr_dyn_p( + false, g_ip->pure_ram, g_ip->pure_cam, fin_res->data_array2->Nspd, + fin_res->data_array2->Ndwl, fin_res->data_array2->Ndbl, + fin_res->data_array2->deg_bl_muxing, fin_res->data_array2->Ndsam_lev_1, + fin_res->data_array2->Ndsam_lev_2, g_ip->is_main_mem); + if (data_arr_dyn_p.is_valid) { + UCA *data_arr = new UCA(data_arr_dyn_p); + fin_res->uca_pg_reference->data_array2 = new mem_array(); + collect_uca_results( + fin_res->data_array2->Nspd, fin_res->data_array2->Ndwl, + fin_res->data_array2->Ndbl, fin_res->data_array2->deg_bl_muxing, + fin_res->data_array2->Ndsam_lev_1, fin_res->data_array2->Ndsam_lev_2, + data_arr, fin_res->uca_pg_reference->data_array2, g_ip->is_main_mem); + delete data_arr; + } + + fin_res->uca_pg_reference->find_delay(); + fin_res->uca_pg_reference->find_energy(); + fin_res->uca_pg_reference->find_area(); + fin_res->uca_pg_reference->find_cyc(); + + // output_UCA(fin_res->uca_pg_reference); + // Wire::print_wire(); + } + else { + cout << "ERROR: Cannot retrieve array structure for tag and data array" + << endl; + exit(1); + } + // reset input to original values in *.cfg file + g_ip->array_power_gated = true; + g_ip->bitline_floating = true; + g_ip->wl_power_gated = true; + g_ip->cl_power_gated = true; + g_ip->interconect_power_gated = true; + g_ip->power_gating = true; +} + +/* update for thermal +void update(uca_org_t *fin_res) +{ + if(fin_res->tag_array2) + { + init_tech_params(g_ip->F_sz_um,true); + DynamicParameter tag_arr_dyn_p(true, g_ip->pure_ram, g_ip->pure_cam, +fin_res->tag_array2->Nspd, fin_res->tag_array2->Ndwl, fin_res->tag_array2->Ndbl, +fin_res->tag_array2->Ndcm, fin_res->tag_array2->Ndsam_lev_1, +fin_res->tag_array2->Ndsam_lev_2, g_ip->is_main_mem); if(tag_arr_dyn_p.is_valid) + { + UCA * tag_arr = new UCA(tag_arr_dyn_p); + fin_res->tag_array2->power = tag_arr->power; + } + else + { + cout << "ERROR: Cannot retrieve array structure for leakage feedback" << +endl; exit(1); + } + } + init_tech_params(g_ip->F_sz_um,false); + DynamicParameter data_arr_dyn_p(false, g_ip->pure_ram, g_ip->pure_cam, +fin_res->data_array2->Nspd, fin_res->data_array2->Ndwl, +fin_res->data_array2->Ndbl, fin_res->data_array2->Ndcm, +fin_res->data_array2->Ndsam_lev_1, fin_res->data_array2->Ndsam_lev_2, +g_ip->is_main_mem); if(data_arr_dyn_p.is_valid) + { + UCA * data_arr = new UCA(data_arr_dyn_p); + fin_res->data_array2->power = data_arr->power; + } + else + { + cout << "ERROR: Cannot retrieve array structure for leakage feedback" << +endl; exit(1); + } + + fin_res->find_energy(); +} +*/ + +} // namespace cacti diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/Ucache.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/Ucache.h new file mode 100644 index 0000000000..15efbbcfea --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/Ucache.h @@ -0,0 +1,120 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __UCACHE_H__ +#define __UCACHE_H__ + +#include +#include "area.h" +#include "nuca.h" +#include "router.h" +#include "uca.h" + +namespace cacti { + +class min_values_t { + public: + double min_delay; + double min_dyn; + double min_leakage; + double min_area; + double min_cyc; + + min_values_t() + : min_delay(BIGNUM), + min_dyn(BIGNUM), + min_leakage(BIGNUM), + min_area(BIGNUM), + min_cyc(BIGNUM) {} + + void update_min_values(const min_values_t *val); + void update_min_values(const uca_org_t &res); + void update_min_values(const nuca_org_t *res); + void update_min_values(const mem_array *res); +}; + +struct solution { + int tag_array_index; + int data_array_index; + list::iterator tag_array_iter; + list::iterator data_array_iter; + double access_time; + double cycle_time; + double area; + double efficiency; + powerDef total_power; +}; + +bool calculate_time(bool is_tag, int pure_ram, bool pure_cam, double Nspd, + unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, + mem_array *ptr_array, int flag_results_populate, + results_mem_array *ptr_results, uca_org_t *ptr_fin_res, + bool is_main_mem); + +void collect_uca_results( + // bool is_tag, + // int pure_ram, + // bool pure_cam, + double Nspd, unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, UCA const *const uca, + mem_array *const ptr_array, + // int flag_results_populate, + // results_mem_array *ptr_results, + // uca_org_t *ptr_fin_res, + bool is_main_mem); + +void update_dvs(uca_org_t *fin_res); +void update_pg(uca_org_t *fin_res); + +void solve(uca_org_t *fin_res); +void init_tech_params(double tech, bool is_tag); + +struct calc_time_mt_wrapper_struct { + uint32_t tid; + bool is_tag; + bool pure_ram; + bool pure_cam; + bool is_main_mem; + double Nspd_min; + + min_values_t *data_res; + min_values_t *tag_res; + + list data_arr; + list tag_arr; +}; + +void calc_time_mt_wrapper(void *void_obj); + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/arbiter.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/arbiter.cc new file mode 100644 index 0000000000..e7698cb981 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/arbiter.cc @@ -0,0 +1,131 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "arbiter.h" +using namespace cacti; + +Arbiter::Arbiter(double n_req, double flit_size_, double output_len, + TechnologyParameter::DeviceType *dt) + : R(n_req), flit_size(flit_size_), o_len(output_len), deviceType(dt) { + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + Vdd = dt->Vdd; + double technology = g_ip->F_sz_um; + NTn1 = 13.5 * technology / 2; + PTn1 = 76 * technology / 2; + NTn2 = 13.5 * technology / 2; + PTn2 = 76 * technology / 2; + NTi = 12.5 * technology / 2; + PTi = 25 * technology / 2; + NTtr = 10 * technology / 2; /*Transmission gate's nmos tr. length*/ + PTtr = 20 * technology / 2; /* pmos tr. length*/ +} + +Arbiter::~Arbiter() {} + +double Arbiter::arb_req() { + double temp = ((R - 1) * (2 * gate_C(NTn1, 0) + gate_C(PTn1, 0)) + + 2 * gate_C(NTn2, 0) + gate_C(PTn2, 0) + gate_C(NTi, 0) + + gate_C(PTi, 0) + drain_C_(NTi, 0, 1, 1, g_tp.cell_h_def) + + drain_C_(PTi, 1, 1, 1, g_tp.cell_h_def)); + return temp; +} + +double Arbiter::arb_pri() { + double temp = + 2 * (2 * gate_C(NTn1, 0) + gate_C(PTn1, 0)); /* switching capacitance + of flip-flop is ignored */ + return temp; +} + +double Arbiter::arb_grant() { + double temp = drain_C_(NTn1, 0, 1, 1, g_tp.cell_h_def) * 2 + + drain_C_(PTn1, 1, 1, 1, g_tp.cell_h_def) + crossbar_ctrline(); + return temp; +} + +double Arbiter::arb_int() { + double temp = (drain_C_(NTn1, 0, 1, 1, g_tp.cell_h_def) * 2 + + drain_C_(PTn1, 1, 1, 1, g_tp.cell_h_def) + + 2 * gate_C(NTn2, 0) + gate_C(PTn2, 0)); + return temp; +} + +void Arbiter::compute_power() { + power.readOp.dynamic = + (R * arb_req() * Vdd * Vdd / 2 + R * arb_pri() * Vdd * Vdd / 2 + + arb_grant() * Vdd * Vdd + arb_int() * 0.5 * Vdd * Vdd); + double nor1_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTn1 * 2, + min_w_pmos * PTn1 * 2, 2, nor); + double nor2_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTn2 * R, + min_w_pmos * PTn2 * R, 2, nor); + double not_leak = + cmos_Isub_leakage(g_tp.min_w_nmos_ * NTi, min_w_pmos * PTi, 1, inv); + double nor1_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTn1 * 2, + min_w_pmos * PTn1 * 2, 2, nor); + double nor2_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTn2 * R, + min_w_pmos * PTn2 * R, 2, nor); + double not_leak_gate = + cmos_Ig_leakage(g_tp.min_w_nmos_ * NTi, min_w_pmos * PTi, 1, inv); + power.readOp.leakage = (nor1_leak + nor2_leak + not_leak) * + Vdd; // FIXME include priority table leakage + power.readOp.gate_leakage = + nor1_leak_gate * Vdd + nor2_leak_gate * Vdd + not_leak_gate * Vdd; +} + +double // wire cap with triple spacing +Arbiter::Cw3(double length) { + Wire wc(g_ip->wt, length, 1, 3, 3); + double temp = (wc.wire_cap(length, true)); + return temp; +} + +double Arbiter::crossbar_ctrline() { + double temp = + (Cw3(o_len * 1e-6 /* m */) + drain_C_(NTi, 0, 1, 1, g_tp.cell_h_def) + + drain_C_(PTi, 1, 1, 1, g_tp.cell_h_def) + gate_C(NTi, 0) + + gate_C(PTi, 0)); + return temp; +} + +double Arbiter::transmission_buf_ctrcap() { + double temp = gate_C(NTtr, 0) + gate_C(PTtr, 0); + return temp; +} + +void Arbiter::print_arbiter() { + cout << "\nArbiter Stats (" << R << " input arbiter" + << ")\n\n"; + cout << "Flit size : " << flit_size << " bits" << endl; + cout << "Dynamic Power : " << power.readOp.dynamic * 1e9 << " (nJ)" + << endl; + cout << "Leakage Power : " << power.readOp.leakage * 1e3 << " (mW)" + << endl; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/arbiter.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/arbiter.h new file mode 100644 index 0000000000..be6320ebd4 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/arbiter.h @@ -0,0 +1,74 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __ARBITER__ +#define __ARBITER__ + +#include +#include +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "mat.h" +#include "parameter.h" +#include "wire.h" + +namespace cacti { + +class Arbiter : public Component { + public: + Arbiter(double Req, double flit_sz, double output_len, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + ~Arbiter(); + + void print_arbiter(); + double arb_req(); + double arb_pri(); + double arb_grant(); + double arb_int(); + void compute_power(); + double Cw3(double len); + double crossbar_ctrline(); + double transmission_buf_ctrcap(); + + private: + double NTn1, PTn1, NTn2, PTn2, R, PTi, NTi; + double flit_size; + double NTtr, PTtr; + double o_len; + TechnologyParameter::DeviceType *deviceType; + double TriS1, TriS2; + double min_w_pmos, Vdd; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/area.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/area.cc new file mode 100644 index 0000000000..b125106496 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/area.cc @@ -0,0 +1,41 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "area.h" +#include +#include +#include +#include "basic_circuit.h" +#include "component.h" +#include "decoder.h" +#include "parameter.h" + +using namespace std; diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/area.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/area.h new file mode 100644 index 0000000000..1927338998 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/area.h @@ -0,0 +1,68 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __AREA_H__ +#define __AREA_H__ + +#include "basic_circuit.h" +#include "cacti_interface.h" + +using namespace std; + +namespace cacti { + +class Area { + public: + double w; + double h; + + Area() : w(0), h(0), area(0) {} + double get_w() const { return w; } + double get_h() const { return h; } + double get_area() const { + if (w == 0 && h == 0) { + return area; + } + else { + return w * h; + } + } + void set_w(double w_) { w = w_; } + void set_h(double h_) { h = h_; } + void set_area(double a_) { area = a_; } + + private: + double area; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/bank.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/bank.cc new file mode 100644 index 0000000000..dfffc77d5a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/bank.cc @@ -0,0 +1,211 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "bank.h" +#include +using namespace cacti; + +Bank::Bank(const DynamicParameter &dyn_p) + : dp(dyn_p), + mat(dp), + num_addr_b_mat(dyn_p.number_addr_bits_mat), + num_mats_hor_dir(dyn_p.num_mats_h_dir), + num_mats_ver_dir(dyn_p.num_mats_v_dir), + array_leakage(0), + wl_leakage(0), + cl_leakage(0) { + int RWP; + int ERP; + int EWP; + int SCHP; + + if (dp.use_inp_params) { + RWP = dp.num_rw_ports; + ERP = dp.num_rd_ports; + EWP = dp.num_wr_ports; + SCHP = dp.num_search_ports; + } + else { + RWP = g_ip->num_rw_ports; + ERP = g_ip->num_rd_ports; + EWP = g_ip->num_wr_ports; + SCHP = g_ip->num_search_ports; + } + + int total_addrbits = + (dp.number_addr_bits_mat + dp.number_subbanks_decode) * (RWP + ERP + EWP); + int datainbits = dp.num_di_b_bank_per_port * (RWP + EWP); + int dataoutbits = dp.num_do_b_bank_per_port * (RWP + ERP); + int searchinbits; + int searchoutbits; + + if (dp.fully_assoc || dp.pure_cam) { + datainbits = dp.num_di_b_bank_per_port * (RWP + EWP); + dataoutbits = dp.num_do_b_bank_per_port * (RWP + ERP); + searchinbits = dp.num_si_b_bank_per_port * SCHP; + searchoutbits = dp.num_so_b_bank_per_port * SCHP; + } + + if (!(dp.fully_assoc || dp.pure_cam)) { + if (g_ip->fast_access && dp.is_tag == false) { + dataoutbits *= g_ip->data_assoc; + } + + htree_in_add = + new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, 0, dataoutbits, 0, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Add_htree); + htree_in_data = + new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, 0, dataoutbits, 0, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_in_htree); + htree_out_data = + new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, 0, dataoutbits, 0, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_out_htree); + + // htree_out_data = new Htree2 (g_ip->wt,(double) 100, (double)100, + // total_addrbits, datainbits, 0,dataoutbits,0, + // num_mats_ver_dir*2, num_mats_hor_dir*2, Data_out_htree); + + area.w = htree_in_data->area.w; + area.h = htree_in_data->area.h; + } + else { + htree_in_add = new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, searchinbits, + dataoutbits, searchoutbits, num_mats_ver_dir * 2, + num_mats_hor_dir * 2, Add_htree); + htree_in_data = new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, searchinbits, + dataoutbits, searchoutbits, num_mats_ver_dir * 2, + num_mats_hor_dir * 2, Data_in_htree); + htree_out_data = new Htree2( + g_ip->wt, (double)mat.area.w, (double)mat.area.h, total_addrbits, + datainbits, searchinbits, dataoutbits, searchoutbits, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_out_htree); + htree_in_search = new Htree2( + g_ip->wt, (double)mat.area.w, (double)mat.area.h, total_addrbits, + datainbits, searchinbits, dataoutbits, searchoutbits, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_in_htree, true, true); + htree_out_search = new Htree2( + g_ip->wt, (double)mat.area.w, (double)mat.area.h, total_addrbits, + datainbits, searchinbits, dataoutbits, searchoutbits, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_out_htree, true); + + area.w = htree_in_data->area.w; + area.h = htree_in_data->area.h; + } + + num_addr_b_row_dec = _log2(mat.subarray.num_rows); + num_addr_b_routed_to_mat_for_act = num_addr_b_row_dec; + num_addr_b_routed_to_mat_for_rd_or_wr = num_addr_b_mat - num_addr_b_row_dec; +} + +Bank::~Bank() { + delete htree_in_add; + delete htree_out_data; + delete htree_in_data; + if (dp.fully_assoc || dp.pure_cam) { + delete htree_in_search; + delete htree_out_search; + } +} + +double Bank::compute_delays(double inrisetime) { + return mat.compute_delays(inrisetime); +} + +void Bank::compute_power_energy() { + mat.compute_power_energy(); + + if (!(dp.fully_assoc || dp.pure_cam)) { + power.readOp.dynamic += mat.power.readOp.dynamic * dp.num_act_mats_hor_dir; + power.readOp.leakage += mat.power.readOp.leakage * dp.num_mats; + power.readOp.gate_leakage += mat.power.readOp.gate_leakage * dp.num_mats; + power.readOp.power_gated_leakage += + mat.power.readOp.power_gated_leakage * dp.num_mats; + + power.readOp.dynamic += htree_in_add->power.readOp.dynamic; + power.readOp.dynamic += htree_out_data->power.readOp.dynamic; + + array_leakage += mat.array_leakage * dp.num_mats; + wl_leakage += mat.wl_leakage * dp.num_mats; + cl_leakage += mat.cl_leakage * dp.num_mats; + + power.readOp.leakage += htree_in_add->power.readOp.leakage; + power.readOp.leakage += htree_in_data->power.readOp.leakage; + power.readOp.leakage += htree_out_data->power.readOp.leakage; + + power.readOp.power_gated_leakage += + htree_in_add->power.readOp.power_gated_leakage; + power.readOp.power_gated_leakage += + htree_in_data->power.readOp.power_gated_leakage; + power.readOp.power_gated_leakage += + htree_out_data->power.readOp.power_gated_leakage; + + power.readOp.gate_leakage += htree_in_add->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_in_data->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_out_data->power.readOp.gate_leakage; + } + else { + power.readOp.dynamic += + mat.power.readOp + .dynamic; // for fa and cam num_act_mats_hor_dir is 1 for plain r/w + power.readOp.leakage += mat.power.readOp.leakage * dp.num_mats; + power.readOp.gate_leakage += mat.power.readOp.gate_leakage * dp.num_mats; + + power.searchOp.dynamic += mat.power.searchOp.dynamic * dp.num_mats; + power.searchOp.dynamic += mat.power_bl_precharge_eq_drv.searchOp.dynamic + + mat.power_sa.searchOp.dynamic + + mat.power_bitline.searchOp.dynamic + + mat.power_subarray_out_drv.searchOp.dynamic + + mat.ml_to_ram_wl_drv->power.readOp.dynamic; + + power.readOp.dynamic += htree_in_add->power.readOp.dynamic; + power.readOp.dynamic += htree_out_data->power.readOp.dynamic; + + power.searchOp.dynamic += htree_in_search->power.searchOp.dynamic; + power.searchOp.dynamic += htree_out_search->power.searchOp.dynamic; + + power.readOp.leakage += htree_in_add->power.readOp.leakage; + power.readOp.leakage += htree_in_data->power.readOp.leakage; + power.readOp.leakage += htree_out_data->power.readOp.leakage; + power.readOp.leakage += htree_in_search->power.readOp.leakage; + power.readOp.leakage += htree_out_search->power.readOp.leakage; + + power.readOp.gate_leakage += htree_in_add->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_in_data->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_out_data->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_in_search->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_out_search->power.readOp.gate_leakage; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/bank.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/bank.h new file mode 100644 index 0000000000..928993a048 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/bank.h @@ -0,0 +1,72 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __BANK_H__ +#define __BANK_H__ + +#include "component.h" +#include "decoder.h" +#include "htree2.h" +#include "mat.h" + +namespace cacti { + +class Bank : public Component { + public: + Bank(const DynamicParameter &dyn_p); + ~Bank(); + double compute_delays(double inrisetime); // return outrisetime + void compute_power_energy(); + + const DynamicParameter &dp; + Mat mat; + Htree2 *htree_in_add; + Htree2 *htree_in_data; + Htree2 *htree_out_data; + Htree2 *htree_in_search; + Htree2 *htree_out_search; + + int num_addr_b_mat; + int num_mats_hor_dir; + int num_mats_ver_dir; + + int num_addr_b_row_dec; + int num_addr_b_routed_to_mat_for_act; + int num_addr_b_routed_to_mat_for_rd_or_wr; + + double array_leakage; + double wl_leakage; + double cl_leakage; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/basic_circuit.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/basic_circuit.cc new file mode 100644 index 0000000000..abbffe7ab1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/basic_circuit.cc @@ -0,0 +1,823 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "basic_circuit.h" +#include +#include +#include +#include "parameter.h" +using namespace cacti; + +uint32_t _log2(uint64_t num) { + uint32_t log2 = 0; + + if (num == 0) { + std::cerr << "log0?" << std::endl; + exit(1); + } + + while (num > 1) { + num = (num >> 1); + log2++; + } + + return log2; +} + +bool is_pow2(int64_t val) { + if (val <= 0) { + return false; + } + else if (val == 1) { + return true; + } + else { + return (_log2(val) != _log2(val - 1)); + } +} + +int powers(int base, int n) { + int i, p; + + p = 1; + for (i = 1; i <= n; ++i) + p *= base; + return p; +} + +/*----------------------------------------------------------------------*/ + +double logtwo(double x) { + assert(x > 0); + return ((double)(log(x) / log(2.0))); +} + +/*----------------------------------------------------------------------*/ + +double gate_C(double width, double wirelength, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + const TechnologyParameter::DeviceType *dt; + + if (_is_dram && _is_cell) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if (_is_dram && _is_wl_tr) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if (!_is_dram && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + return (dt->C_g_ideal + dt->C_overlap + 3 * dt->C_fringe) * width + + dt->l_phy * Cpolywire; +} + +// returns gate capacitance in Farads +// actually this function is the same as gate_C() now +double gate_C_pass( + double width, // gate width in um (length is Lphy_periph_global) + double wirelength, // poly wire length going to gate in lambda + bool _is_dram, bool _is_cell, bool _is_wl_tr, bool _is_sleep_tx) { + // v5.0 + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + return (dt->C_g_ideal + dt->C_overlap + 3 * dt->C_fringe) * width + + dt->l_phy * Cpolywire; +} + +double drain_C_(double width, int nchannel, int stack, + int next_arg_thresh_folding_width_or_height_cell, + double fold_dimension, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + double w_folded_tr; + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + double c_junc_area = dt->C_junc; + double c_junc_sidewall = dt->C_junc_sidewall; + double c_fringe = 2 * dt->C_fringe; + double c_overlap = 2 * dt->C_overlap; + double drain_C_metal_connecting_folded_tr = 0; + + // determine the width of the transistor after folding (if it is getting + // folded) + if (next_arg_thresh_folding_width_or_height_cell == + 0) { // interpret fold_dimension as the the folding width threshold + // i.e. the value of transistor width above which the transistor gets folded + w_folded_tr = fold_dimension; + } + else { // interpret fold_dimension as the height of the cell that this + // transistor is part of. + double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL; + // TODO : w_folded_tr must come from Component::compute_gate_area() + double ratio_p_to_n = 2.0 / (2.0 + 1.0); + if (nchannel) { + w_folded_tr = + (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS); + } + else { + w_folded_tr = + ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS); + } + } + int num_folded_tr = (int)(ceil(width / w_folded_tr)); + + if (num_folded_tr < 2) { + w_folded_tr = width; + } + + double total_drain_w = (g_tp.w_poly_contact + + 2 * g_tp.spacing_poly_to_contact) + // only for drain + (stack - 1) * g_tp.spacing_poly_to_poly; + double drain_h_for_sidewall = w_folded_tr; + double total_drain_height_for_cap_wrt_gate = + w_folded_tr + 2 * w_folded_tr * (stack - 1); + if (num_folded_tr > 1) { + total_drain_w += + (num_folded_tr - 2) * + (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + + (num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly); + + if (num_folded_tr % 2 == 0) { + drain_h_for_sidewall = 0; + } + total_drain_height_for_cap_wrt_gate *= num_folded_tr; + drain_C_metal_connecting_folded_tr = + g_tp.wire_local.C_per_um * total_drain_w; + } + + double drain_C_area = c_junc_area * total_drain_w * w_folded_tr; + double drain_C_sidewall = + c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w); + double drain_C_wrt_gate = + (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate; + + return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + + drain_C_metal_connecting_folded_tr); +} + +double tr_R_on(double width, int nchannel, int stack, bool _is_dram, + bool _is_cell, bool _is_wl_tr, bool _is_sleep_tx) { + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on; + return (stack * restrans / width); +} + +/* This routine operates in reverse: given a resistance, it finds + * the transistor width that would have this R. It is used in the + * data wordline to estimate the wordline driver size. */ + +// returns width in um +double R_to_w(double res, int nchannel, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && (_is_cell)) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on; + return (restrans / res); +} + +double pmos_to_nmos_sz_ratio(bool _is_dram, bool _is_wl_tr, bool _is_sleep_tx) { + double p_to_n_sizing_ratio; + if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio; + } + else if (_is_sleep_tx) { + p_to_n_sizing_ratio = + g_tp.sleep_tx.n_to_p_eff_curr_drv_ratio; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio; + } + return p_to_n_sizing_ratio; +} + +// "Timing Models for MOS Circuits" by Mark Horowitz, 1984 +double horowitz(double inputramptime, // input rise time + double tf, // time constant of gate + double vs1, // threshold voltage1/Vdd + double vs2, // threshold voltage2/vdd + int rise) // whether input rises or fall +{ + if (inputramptime == 0 && vs1 == vs2) { + return tf * (vs1 < 1 ? -log(vs1) : log(vs1)); + } + double a, b, td; + + a = inputramptime / tf; + if (rise == RISE) { + b = 0.5; + td = tf * sqrt(log(vs1) * log(vs1) + 2 * a * b * (1.0 - vs1)) + + tf * (log(vs1) - log(vs2)); + } + else { + b = 0.4; + td = tf * sqrt(log(1.0 - vs1) * log(1.0 - vs1) + 2 * a * b * (vs1)) + + tf * (log(1.0 - vs1) - log(1.0 - vs2)); + } + return (td); +} + +double cmos_Ileak(double nWidth, double pWidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nWidth * dt->I_off_n + pWidth * dt->I_off_p; +} + +int factorial(int n, int m) { + int fa = m, i; + for (i = m + 1; i <= n; i++) + fa *= i; + return fa; +} + +int combination(int n, int m) { + int ret; + ret = factorial(n, m + 1) / factorial(n - m); + return ret; +} + +double simplified_nmos_Isat(double nwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nwidth * dt->I_on_n; +} + +double simplified_pmos_Isat(double pwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return pwidth * dt->I_on_n / dt->n_to_p_eff_curr_drv_ratio; +} + +double simplified_nmos_leakage(double nwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nwidth * dt->I_off_n; +} + +double simplified_pmos_leakage(double pwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return pwidth * dt->I_off_p; +} + +double cmos_Ig_n(double nWidth, bool _is_dram, bool _is_cell, bool _is_wl_tr, + bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nWidth * dt->I_g_on_n; +} + +double cmos_Ig_p(double pWidth, bool _is_dram, bool _is_cell, bool _is_wl_tr, + bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return pWidth * dt->I_g_on_p; +} + +double cmos_Isub_leakage(double nWidth, double pWidth, int fanin, + enum Gate_type g_type, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx, + enum Half_net_topology topo) { + assert(fanin >= 1); + double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, + _is_wl_tr, _is_sleep_tx); + double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, + _is_wl_tr, _is_sleep_tx); + double Isub = 0; + int num_states; + int num_off_tx; + + num_states = int(pow(2.0, fanin)); + + switch (g_type) { + case nmos: + if (fanin == 1) { + Isub = nmos_leak / num_states; + } + else { + if (topo == parallel) { + Isub = nmos_leak * fanin / num_states; // only when all tx are off, + // leakage power is non-zero. + // The possibility of this + // state is 1/num_states + } + else { + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // when num_off_tx ==0 there is no leakage power + { + // Isub += + // nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub /= num_states; + } + } + break; + case pmos: + if (fanin == 1) { + Isub = pmos_leak / num_states; + } + else { + if (topo == parallel) { + Isub = pmos_leak * fanin / num_states; // only when all tx are off, + // leakage power is non-zero. + // The possibility of this + // state is 1/num_states + } + else { + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // when num_off_tx ==0 there is no leakage power + { + // Isub += + // pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub /= num_states; + } + } + break; + case inv: + Isub = (nmos_leak + pmos_leak) / 2; + break; + case nand: + Isub += fanin * pmos_leak; // the pullup network + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // the pulldown network + { + // Isub += + // nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub /= num_states; + break; + case nor: + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // the pullup network + { + // Isub += + // pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub += fanin * nmos_leak; // the pulldown network + Isub /= num_states; + break; + case tri: + Isub += (nmos_leak + pmos_leak) / 2; // enabled + Isub += nmos_leak * + UNI_LEAK_STACK_FACTOR; // disabled upper bound of leakage power + Isub /= 2; + break; + case tg: + Isub = (nmos_leak + pmos_leak) / 2; + break; + default: + assert(0); + break; + } + + return Isub; +} + +double cmos_Ig_leakage(double nWidth, double pWidth, int fanin, + enum Gate_type g_type, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx, + enum Half_net_topology topo) { + assert(fanin >= 1); + double nmos_leak = + cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr, _is_sleep_tx); + double pmos_leak = + cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr, _is_sleep_tx); + double Ig_on = 0; + int num_states; + int num_on_tx; + + num_states = int(pow(2.0, fanin)); + + switch (g_type) { + case nmos: + if (fanin == 1) { + Ig_on = nmos_leak / num_states; + } + else { + if (topo == parallel) { + for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + } + else { + Ig_on += nmos_leak * fanin; // pull down network when all TXs are on. + // num_on_tx is the number of on tx + for (num_on_tx = 1; num_on_tx < fanin; + num_on_tx++) // when num_on_tx=[1,n-1] + { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx / + 2; // TODO: this is a approximation now, a precise + // computation will be very complicated. + } + Ig_on /= num_states; + } + } + break; + case pmos: + if (fanin == 1) { + Ig_on = pmos_leak / num_states; + } + else { + if (topo == parallel) { + for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + } + else { + Ig_on += pmos_leak * fanin; // pull down network when all TXs are on. + // num_on_tx is the number of on tx + for (num_on_tx = 1; num_on_tx < fanin; + num_on_tx++) // when num_on_tx=[1,n-1] + { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx / + 2; // TODO: this is a approximation now, a precise + // computation will be very complicated. + } + Ig_on /= num_states; + } + } + break; + + case inv: + Ig_on = (nmos_leak + pmos_leak) / 2; + break; + case nand: + // pull up network + for (num_on_tx = 1; num_on_tx <= fanin; + num_on_tx++) // when num_on_tx=[1,n] + { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + + // pull down network + Ig_on += nmos_leak * fanin; // pull down network when all TXs are on. + // num_on_tx is the number of on tx + for (num_on_tx = 1; num_on_tx < fanin; + num_on_tx++) // when num_on_tx=[1,n-1] + { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx / + 2; // TODO: this is a approximation now, a precise computation + // will be very complicated. + } + Ig_on /= num_states; + break; + case nor: + // num_on_tx is the number of on tx in pull up network + Ig_on += pmos_leak * fanin; // pull up network when all TXs are on. + for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx / 2; + } + // pull down network + for (num_on_tx = 1; num_on_tx <= fanin; + num_on_tx++) // when num_on_tx=[1,n] + { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + Ig_on /= num_states; + break; + case tri: + Ig_on += (2 * nmos_leak + 2 * pmos_leak) / 2; // enabled + Ig_on += + (nmos_leak + pmos_leak) / 2; // disabled upper bound of leakage power + Ig_on /= 2; + break; + case tg: + Ig_on = (nmos_leak + pmos_leak) / 2; + break; + default: + assert(0); + break; + } + + return Ig_on; +} + +double shortcircuit_simple(double vt, double velocity_index, double c_in, + double c_out, double w_nmos, double w_pmos, + double i_on_n, double i_on_p, double i_on_n_in, + double i_on_p_in, double vdd) { + double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, + p_short_circuit_discharge_low, // p_short_circuit_discharge_high, + p_short_circuit_charge_low; //, + // p_short_circuit_charge_high; // this is actually energy + double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio; + + fo_n = i_on_n / i_on_n_in; + fo_p = i_on_p / i_on_p_in; + fanout = c_out / c_in; + beta_ratio = i_on_p / i_on_n; + vt_to_vdd_ratio = vt / vdd; + + // p_short_circuit_discharge_low = + // 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio; + p_short_circuit_discharge_low = + 10 / 3 * + (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) / pow(velocity_index, 2.0) / + pow(2.0, 3 * vt_to_vdd_ratio * vt_to_vdd_ratio)) * + c_in * vdd * vdd * fo_p * fo_p / fanout / beta_ratio; + p_short_circuit_charge_low = + 10 / 3 * + (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) / pow(velocity_index, 2.0) / + pow(2.0, 3 * vt_to_vdd_ratio * vt_to_vdd_ratio)) * + c_in * vdd * vdd * fo_n * fo_n / fanout * beta_ratio; + // double t1, t2, t3, t4, t5; + // t1=pow(((vdd-vt)-vt_to_vdd_ratio),3); + // t2=pow(velocity_index,2.0); + // t3=pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio); + // t4=t1/t2/t3; + // cout < +#include + +#include "Ucache.h" +#include "area.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "const.h" +#include "parameter.h" + +#include +#include + +using namespace std; +using namespace cacti; + +bool mem_array::lt(const mem_array *m1, const mem_array *m2) { + if (m1->Nspd < m2->Nspd) + return true; + else if (m1->Nspd > m2->Nspd) + return false; + else if (m1->Ndwl < m2->Ndwl) + return true; + else if (m1->Ndwl > m2->Ndwl) + return false; + else if (m1->Ndbl < m2->Ndbl) + return true; + else if (m1->Ndbl > m2->Ndbl) + return false; + else if (m1->deg_bl_muxing < m2->deg_bl_muxing) + return true; + else if (m1->deg_bl_muxing > m2->deg_bl_muxing) + return false; + else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) + return true; + else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) + return false; + else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) + return true; + else + return false; +} + +void uca_org_t::find_delay() { + mem_array *data_arr = data_array2; + mem_array *tag_arr = tag_array2; + + // check whether it is a regular cache or scratch ram + if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) { + access_time = data_arr->access_time; + } + // Both tag and data lookup happen in parallel + // and the entire set is sent over the data array h-tree without + // waiting for the way-select signal --TODO add the corresponding + // power overhead Nav + else if (g_ip->fast_access == true) { + access_time = MAX(tag_arr->access_time, data_arr->access_time); + } + // Tag is accessed first. On a hit, way-select signal along with the + // address is sent to read/write the appropriate block in the data + // array + else if (g_ip->is_seq_acc == true) { + access_time = tag_arr->access_time + data_arr->access_time; + } + // Normal access: tag array access and data array access happen in parallel. + // But, the data array will wait for the way-select and transfer only the + // appropriate block over the h-tree. + else { + access_time = + MAX(tag_arr->access_time + data_arr->delay_senseamp_mux_decoder, + data_arr->delay_before_subarray_output_driver) + + data_arr->delay_from_subarray_output_driver_to_output; + } +} + +void uca_org_t::find_energy() { + if (!(g_ip->pure_ram || g_ip->pure_cam || + g_ip->fully_assoc)) //(g_ip->is_cache) + power = data_array2->power + tag_array2->power; + else + power = data_array2->power; +} + +void uca_org_t::find_area() { + if (g_ip->pure_ram || g_ip->pure_cam || + g_ip->fully_assoc) //(g_ip->is_cache == false) + { + cache_ht = data_array2->height; + cache_len = data_array2->width; + } + else { + cache_ht = MAX(tag_array2->height, data_array2->height); + cache_len = tag_array2->width + data_array2->width; + } + area = cache_ht * cache_len; +} + +void uca_org_t::adjust_area() { + double area_adjust; + if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) { + if (data_array2->area_efficiency / 100.0 < 0.2) { + // area_adjust = + // sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2)); + area_adjust = sqrt(0.2 / (data_array2->area_efficiency / 100.0)); + cache_ht = cache_ht / area_adjust; + cache_len = cache_len / area_adjust; + } + } + area = cache_ht * cache_len; +} + +void uca_org_t::find_cyc() { + if ((g_ip->pure_ram || g_ip->pure_cam || + g_ip->fully_assoc)) //(g_ip->is_cache == false) + { + cycle_time = data_array2->cycle_time; + } + else { + cycle_time = MAX(tag_array2->cycle_time, data_array2->cycle_time); + } +} + +uca_org_t ::uca_org_t() : tag_array2(0), data_array2(0), uca_pg_reference(0) { + uca_q = vector(0); +} + +void uca_org_t ::cleanup() { + // uca_org_t * it_uca_org; + if (data_array2 != 0) { + delete data_array2; + data_array2 = 0; + } + + if (tag_array2 != 0) { + delete tag_array2; + tag_array2 = 0; + } + + std::vector::size_type sz = uca_q.size(); + for (int i = sz - 1; i >= 0; i--) { + if (uca_q[i]->data_array2 != 0) { + delete uca_q[i]->data_array2; + uca_q[i]->data_array2 = 0; + } + if (uca_q[i]->tag_array2 != 0) { + delete uca_q[i]->tag_array2; + uca_q[i]->tag_array2 = 0; + } + delete uca_q[i]; + uca_q[i] = 0; + uca_q.pop_back(); + } + + if (uca_pg_reference != 0) { + if (uca_pg_reference->data_array2 != 0) { + delete uca_pg_reference->data_array2; + uca_pg_reference->data_array2 = 0; + } + if (uca_pg_reference->tag_array2 != 0) { + delete uca_pg_reference->tag_array2; + uca_pg_reference->tag_array2 = 0; + } + delete uca_pg_reference; + uca_pg_reference = 0; + } +} + +uca_org_t ::~uca_org_t() { + // cleanup(); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/cacti_interface.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/cacti_interface.h new file mode 100644 index 0000000000..c4cfd18fe3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/cacti_interface.h @@ -0,0 +1,635 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __CACTI_INTERFACE_H__ +#define __CACTI_INTERFACE_H__ + +#include +#include +#include +#include +#include +#include "const.h" + +using namespace std; + +namespace cacti { + +class min_values_t; +class mem_array; +class uca_org_t; + +class powerComponents { + public: + double dynamic; + double leakage; + double gate_leakage; + double short_circuit; + double longer_channel_leakage; + double power_gated_leakage; + double power_gated_with_long_channel_leakage; + + powerComponents() + : dynamic(0), + leakage(0), + gate_leakage(0), + short_circuit(0), + longer_channel_leakage(0), + power_gated_leakage(0), + power_gated_with_long_channel_leakage(0) {} + powerComponents(const powerComponents &obj) { *this = obj; } + powerComponents &operator=(const powerComponents &rhs) { + dynamic = rhs.dynamic; + leakage = rhs.leakage; + gate_leakage = rhs.gate_leakage; + short_circuit = rhs.short_circuit; + longer_channel_leakage = rhs.longer_channel_leakage; + power_gated_leakage = rhs.power_gated_leakage; + power_gated_with_long_channel_leakage = + rhs.power_gated_with_long_channel_leakage; + return *this; + } + void reset() { + dynamic = 0; + leakage = 0; + gate_leakage = 0; + short_circuit = 0; + longer_channel_leakage = 0; + power_gated_leakage = 0; + power_gated_with_long_channel_leakage = 0; + } + + friend powerComponents operator+(const powerComponents &x, + const powerComponents &y); + friend powerComponents operator*(const powerComponents &x, + double const *const y); +}; + +class powerDef { + public: + powerComponents readOp; + powerComponents writeOp; + powerComponents searchOp; // Sheng: for CAM and FA + + powerDef() : readOp(), writeOp(), searchOp() {} + void reset() { + readOp.reset(); + writeOp.reset(); + searchOp.reset(); + } + + friend powerDef operator+(const powerDef &x, const powerDef &y); + friend powerDef operator*(const powerDef &x, double const *const y); +}; + +enum Wire_type { + Global /* gloabl wires with repeaters */, + Global_5 /* 5% delay penalty */, + Global_10 /* 10% delay penalty */, + Global_20 /* 20% delay penalty */, + Global_30 /* 30% delay penalty */, + Low_swing /* differential low power wires with high area overhead */, + Semi_global /* mid-level wires with repeaters*/, + Transmission /* tranmission lines with high area overhead */, + Optical /* optical wires */, + Invalid_wtype +}; + +class InputParameter { + public: + InputParameter(); + void parse_cfg(const string &infile); + + bool + error_checking(); // return false if the input parameters are problematic + void display_ip(); + + unsigned int cache_sz; // in bytes + unsigned int line_sz; + unsigned int assoc; + unsigned int nbanks; + unsigned int out_w; // == nr_bits_out + bool specific_tag; + unsigned int tag_w; + unsigned int access_mode; + unsigned int obj_func_dyn_energy; + unsigned int obj_func_dyn_power; + unsigned int obj_func_leak_power; + unsigned int obj_func_cycle_t; + + double F_sz_nm; // feature size in nm + double F_sz_um; // feature size in um + bool specific_hp_vdd; // whether to have user defined vdd that is different + // from ITRS + double hp_Vdd; // user specified vdd + bool specific_lstp_vdd; // whether to have user defined vdd that is different + // from ITRS + double lstp_Vdd; + bool specific_lop_vdd; // whether to have user defined vdd that is different + // from ITRS + double lop_Vdd; + bool specific_vcc_min; // whether to have user defined vcc_min for + // power-gating that is different from the value + // constrained by technology for maintaining states + double user_defined_vcc_min; + bool user_defined_vcc_underflow; // flag to indicate when user defined vcc is + // too low for the circuit to retain state + unsigned int num_rw_ports; + unsigned int num_rd_ports; + unsigned int num_wr_ports; + unsigned int num_se_rd_ports; // number of single ended read ports + unsigned int num_search_ports; // number of search ports for CAM + bool is_main_mem; + bool is_cache; + bool pure_ram; + bool pure_cam; + bool rpters_in_htree; // if there are repeaters in htree segment + unsigned int ver_htree_wires_over_array; + unsigned int broadcast_addr_din_over_ver_htrees; + unsigned int temp; + + unsigned int ram_cell_tech_type; + unsigned int peri_global_tech_type; + unsigned int data_arr_ram_cell_tech_type; + unsigned int data_arr_peri_global_tech_type; + unsigned int tag_arr_ram_cell_tech_type; + unsigned int tag_arr_peri_global_tech_type; + + unsigned int burst_len; + unsigned int int_prefetch_w; + unsigned int page_sz_bits; + + unsigned int ic_proj_type; // interconnect_projection_type + unsigned int wire_is_mat_type; // wire_inside_mat_type + unsigned int wire_os_mat_type; // wire_outside_mat_type + enum Wire_type wt; + int force_wiretype; + bool print_input_args; + unsigned int nuca_cache_sz; // TODO + int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm; + bool force_cache_config; + + int cache_level; + int cores; + int nuca_bank_count; + int force_nuca_bank; + + int delay_wt, dynamic_power_wt, leakage_power_wt, cycle_time_wt, area_wt; + int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca, + cycle_time_wt_nuca, area_wt_nuca; + + int delay_dev, dynamic_power_dev, leakage_power_dev, cycle_time_dev, area_dev; + int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca, + cycle_time_dev_nuca, area_dev_nuca; + int ed; // ED or ED2 optimization + int nuca; + + bool fast_access; + unsigned int block_sz; // bytes + unsigned int tag_assoc; + unsigned int data_assoc; + bool is_seq_acc; + bool fully_assoc; + unsigned int nsets; // == number_of_sets + int print_detail; + + bool add_ecc_b_; + // parameters for design constraint + double throughput; + double latency; + bool pipelinable; + int pipeline_stages; + int per_stage_vector; + bool with_clock_grid; + + bool array_power_gated; + bool bitline_floating; + bool wl_power_gated; + bool cl_power_gated; + bool interconect_power_gated; + bool power_gating; + + double perfloss; + + bool cl_vertical; + + std::vector dvs_voltage; + + bool long_channel_device; +}; + +typedef struct { + int Ndwl; + int Ndbl; + double Nspd; + int deg_bl_muxing; + int Ndsam_lev_1; + int Ndsam_lev_2; + int number_activated_mats_horizontal_direction; + int number_subbanks; + int page_size_in_bits; + double delay_route_to_bank; + double delay_crossbar; + double delay_addr_din_horizontal_htree; + double delay_addr_din_vertical_htree; + double delay_row_predecode_driver_and_block; + double delay_row_decoder; + double delay_bitlines; + double delay_sense_amp; + double delay_subarray_output_driver; + double delay_bit_mux_predecode_driver_and_block; + double delay_bit_mux_decoder; + double delay_senseamp_mux_lev_1_predecode_driver_and_block; + double delay_senseamp_mux_lev_1_decoder; + double delay_senseamp_mux_lev_2_predecode_driver_and_block; + double delay_senseamp_mux_lev_2_decoder; + double delay_input_htree; + double delay_output_htree; + double delay_dout_vertical_htree; + double delay_dout_horizontal_htree; + double delay_comparator; + double access_time; + double cycle_time; + double multisubbank_interleave_cycle_time; + double delay_request_network; + double delay_inside_mat; + double delay_reply_network; + double trcd; + double cas_latency; + double precharge_delay; + powerDef power_routing_to_bank; + powerDef power_addr_input_htree; + powerDef power_data_input_htree; + powerDef power_data_output_htree; + powerDef power_addr_horizontal_htree; + powerDef power_datain_horizontal_htree; + powerDef power_dataout_horizontal_htree; + powerDef power_addr_vertical_htree; + powerDef power_datain_vertical_htree; + powerDef power_row_predecoder_drivers; + powerDef power_row_predecoder_blocks; + powerDef power_row_decoders; + powerDef power_bit_mux_predecoder_drivers; + powerDef power_bit_mux_predecoder_blocks; + powerDef power_bit_mux_decoders; + powerDef power_senseamp_mux_lev_1_predecoder_drivers; + powerDef power_senseamp_mux_lev_1_predecoder_blocks; + powerDef power_senseamp_mux_lev_1_decoders; + powerDef power_senseamp_mux_lev_2_predecoder_drivers; + powerDef power_senseamp_mux_lev_2_predecoder_blocks; + powerDef power_senseamp_mux_lev_2_decoders; + powerDef power_bitlines; + powerDef power_sense_amps; + powerDef power_prechg_eq_drivers; + powerDef power_output_drivers_at_subarray; + powerDef power_dataout_vertical_htree; + powerDef power_comparators; + powerDef power_crossbar; + powerDef total_power; + double area; + double all_banks_height; + double all_banks_width; + double bank_height; + double bank_width; + double subarray_memory_cell_area_height; + double subarray_memory_cell_area_width; + double mat_height; + double mat_width; + double routing_area_height_within_bank; + double routing_area_width_within_bank; + double area_efficiency; + // double perc_power_dyn_routing_to_bank; + // double perc_power_dyn_addr_horizontal_htree; + // double perc_power_dyn_datain_horizontal_htree; + // double perc_power_dyn_dataout_horizontal_htree; + // double perc_power_dyn_addr_vertical_htree; + // double perc_power_dyn_datain_vertical_htree; + // double perc_power_dyn_row_predecoder_drivers; + // double perc_power_dyn_row_predecoder_blocks; + // double perc_power_dyn_row_decoders; + // double perc_power_dyn_bit_mux_predecoder_drivers; + // double perc_power_dyn_bit_mux_predecoder_blocks; + // double perc_power_dyn_bit_mux_decoders; + // double perc_power_dyn_senseamp_mux_lev_1_predecoder_drivers; + // double perc_power_dyn_senseamp_mux_lev_1_predecoder_blocks; + // double perc_power_dyn_senseamp_mux_lev_1_decoders; + // double perc_power_dyn_senseamp_mux_lev_2_predecoder_drivers; + // double perc_power_dyn_senseamp_mux_lev_2_predecoder_blocks; + // double perc_power_dyn_senseamp_mux_lev_2_decoders; + // double perc_power_dyn_bitlines; + // double perc_power_dyn_sense_amps; + // double perc_power_dyn_prechg_eq_drivers; + // double perc_power_dyn_subarray_output_drivers; + // double perc_power_dyn_dataout_vertical_htree; + // double perc_power_dyn_comparators; + // double perc_power_dyn_crossbar; + // double perc_power_dyn_spent_outside_mats; + // double perc_power_leak_routing_to_bank; + // double perc_power_leak_addr_horizontal_htree; + // double perc_power_leak_datain_horizontal_htree; + // double perc_power_leak_dataout_horizontal_htree; + // double perc_power_leak_addr_vertical_htree; + // double perc_power_leak_datain_vertical_htree; + // double perc_power_leak_row_predecoder_drivers; + // double perc_power_leak_row_predecoder_blocks; + // double perc_power_leak_row_decoders; + // double perc_power_leak_bit_mux_predecoder_drivers; + // double perc_power_leak_bit_mux_predecoder_blocks; + // double perc_power_leak_bit_mux_decoders; + // double perc_power_leak_senseamp_mux_lev_1_predecoder_drivers; + // double perc_power_leak_senseamp_mux_lev_1_predecoder_blocks; + // double perc_power_leak_senseamp_mux_lev_1_decoders; + // double perc_power_leak_senseamp_mux_lev_2_predecoder_drivers; + // double perc_power_leak_senseamp_mux_lev_2_predecoder_blocks; + // double perc_power_leak_senseamp_mux_lev_2_decoders; + // double perc_power_leak_bitlines; + // double perc_power_leak_sense_amps; + // double perc_power_leak_prechg_eq_drivers; + // double perc_power_leak_subarray_output_drivers; + // double perc_power_leak_dataout_vertical_htree; + // double perc_power_leak_comparators; + // double perc_power_leak_crossbar; + // double perc_leak_mats; + // double perc_active_mats; + double refresh_power; + double dram_refresh_period; + double dram_array_availability; + double dyn_read_energy_from_closed_page; + double dyn_read_energy_from_open_page; + double leak_power_subbank_closed_page; + double leak_power_subbank_open_page; + double leak_power_request_and_reply_networks; + double activate_energy; + double read_energy; + double write_energy; + double precharge_energy; +} results_mem_array; + +class uca_org_t { + public: + mem_array *tag_array2; + mem_array *data_array2; + double access_time; + double cycle_time; + double area; + double area_efficiency; + powerDef power; + double leak_power_with_sleep_transistors_in_mats; + double cache_ht; + double cache_len; + char file_n[100]; + double vdd_periph_global; + bool valid; + results_mem_array tag_array; + results_mem_array data_array; + std::vector + uca_q; // for results share the same settings (g_ip + // and dyn_p) but with different tech settings + // such as DVFS + uca_org_t * + uca_pg_reference; // for references results when power gating is enabled. + uca_org_t(); + void find_delay(); + void find_energy(); + void find_area(); + void find_cyc(); + void adjust_area(); // for McPAT only to adjust routing overhead + void cleanup(); + ~uca_org_t(); +}; + +void reconfigure(InputParameter *local_interface, uca_org_t *fin_res); + +uca_org_t cacti_interface(const string &infile_name); +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface(InputParameter *const local_interface); +// McPAT's plain interface, please keep !!! +uca_org_t init_interface(InputParameter *const local_interface); +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, int excl_write_ports, int single_ended_read_ports, + int search_ports, int banks, double tech_node, int output_width, + int specific_tag, int tag_width, int access_mode, int cache, int main_mem, + int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, + int obj_func_cycle_time, int obj_func_area, int dev_func_delay, + int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, + int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, int wire_inside_mat_type_in, + int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, + int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, + int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, int PAGE_SIZE_BITS_in, + int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, + int wiretype, int force_config, int ndwl, int ndbl, int nspd, int ndcm, + int ndsam1, int ndsam2, int ecc); +// int cache_size, +// int line_size, +// int associativity, +// int rw_ports, +// int excl_read_ports, +// int excl_write_ports, +// int single_ended_read_ports, +// int banks, +// double tech_node, +// int output_width, +// int specific_tag, +// int tag_width, +// int access_mode, +// int cache, +// int main_mem, +// int obj_func_delay, +// int obj_func_dynamic_power, +// int obj_func_leakage_power, +// int obj_func_area, +// int obj_func_cycle_time, +// int dev_func_delay, +// int dev_func_dynamic_power, +// int dev_func_leakage_power, +// int dev_func_area, +// int dev_func_cycle_time, +// int temp, +// int data_arr_ram_cell_tech_flavor_in, +// int data_arr_peri_global_tech_flavor_in, +// int tag_arr_ram_cell_tech_flavor_in, +// int tag_arr_peri_global_tech_flavor_in, +// int interconnect_projection_type_in, +// int wire_inside_mat_type_in, +// int wire_outside_mat_type_in, +// int REPEATERS_IN_HTREE_SEGMENTS_in, +// int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, +// int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, +//// double MAXAREACONSTRAINT_PERC_in, +//// double MAXACCTIMECONSTRAINT_PERC_in, +//// double MAX_PERC_DIFF_IN_DELAY_FROM_BEST_DELAY_REPEATER_SOLUTION_in, +// int PAGE_SIZE_BITS_in, +// int BURST_LENGTH_in, +// int INTERNAL_PREFETCH_WIDTH_in); + +// Naveen's interface +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, int excl_write_ports, int single_ended_read_ports, + int banks, double tech_node, int page_sz, int burst_length, int pre_width, + int output_width, int specific_tag, int tag_width, + int access_mode, // 0 normal, 1 seq, 2 fast + int cache, // scratch ram or cache + int main_mem, int obj_func_delay, int obj_func_dynamic_power, + int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, + int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, + int dev_func_area, int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, // 0 - aggressive, 1 - normal + int wire_inside_mat_type_in, int wire_outside_mat_type_in, + int is_nuca, // 0 - UCA, 1 - NUCA + int core_count, + int cache_level, // 0 - L2, 1 - L3 + int nuca_bank_count, int nuca_obj_func_delay, + int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, + int nuca_obj_func_area, int nuca_obj_func_cycle_time, + int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, + int nuca_dev_func_leakage_power, int nuca_dev_func_area, + int nuca_dev_func_cycle_time, + int REPEATERS_IN_HTREE_SEGMENTS_in, // TODO for now only wires with + // repeaters are supported + int p_input); + +class mem_array { + public: + int Ndcm; + int Ndwl; + int Ndbl; + double Nspd; + int deg_bl_muxing; + int Ndsam_lev_1; + int Ndsam_lev_2; + double access_time; + double cycle_time; + double multisubbank_interleave_cycle_time; + double area_ram_cells; + double area; + powerDef power; + double delay_senseamp_mux_decoder; + double delay_before_subarray_output_driver; + double delay_from_subarray_output_driver_to_output; + double height; + double width; + + double mat_height; + double mat_length; + double subarray_length; + double subarray_height; + + double delay_route_to_bank, delay_input_htree, + delay_row_predecode_driver_and_block, delay_row_decoder, delay_bitlines, + delay_sense_amp, delay_subarray_output_driver, delay_dout_htree, + delay_comparator, delay_matchlines; + + double all_banks_height, all_banks_width, area_efficiency; + + powerDef power_routing_to_bank; + powerDef power_addr_input_htree; + powerDef power_data_input_htree; + powerDef power_data_output_htree; + powerDef power_htree_in_search; + powerDef power_htree_out_search; + powerDef power_row_predecoder_drivers; + powerDef power_row_predecoder_blocks; + powerDef power_row_decoders; + powerDef power_bit_mux_predecoder_drivers; + powerDef power_bit_mux_predecoder_blocks; + powerDef power_bit_mux_decoders; + powerDef power_senseamp_mux_lev_1_predecoder_drivers; + powerDef power_senseamp_mux_lev_1_predecoder_blocks; + powerDef power_senseamp_mux_lev_1_decoders; + powerDef power_senseamp_mux_lev_2_predecoder_drivers; + powerDef power_senseamp_mux_lev_2_predecoder_blocks; + powerDef power_senseamp_mux_lev_2_decoders; + powerDef power_bitlines; + powerDef power_sense_amps; + powerDef power_prechg_eq_drivers; + powerDef power_output_drivers_at_subarray; + powerDef power_dataout_vertical_htree; + powerDef power_comparators; + + powerDef power_cam_bitline_precharge_eq_drv; + powerDef power_searchline; + powerDef power_searchline_precharge; + powerDef power_matchlines; + powerDef power_matchline_precharge; + powerDef power_matchline_to_wordline_drv; + + min_values_t *arr_min; + enum Wire_type wt; + + // dram stats + double activate_energy, read_energy, write_energy, precharge_energy, + refresh_power, leak_power_subbank_closed_page, + leak_power_subbank_open_page, leak_power_request_and_reply_networks; + + double precharge_delay; + + // Power-gating stats + double array_leakage; + double wl_leakage; + double cl_leakage; + + double sram_sleep_tx_width, wl_sleep_tx_width, cl_sleep_tx_width; + double sram_sleep_tx_area, wl_sleep_tx_area, cl_sleep_tx_area; + double sram_sleep_wakeup_latency, wl_sleep_wakeup_latency, + cl_sleep_wakeup_latency, bl_floating_wakeup_latency; + double sram_sleep_wakeup_energy, wl_sleep_wakeup_energy, + cl_sleep_wakeup_energy, bl_floating_wakeup_energy; + + int num_active_mats; + int num_submarray_mats; + + double long_channel_leakage_reduction_periperal; + double long_channel_leakage_reduction_memcell; + + static bool lt(const mem_array *m1, const mem_array *m2); +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/component.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/component.cc new file mode 100644 index 0000000000..d076e6bfc2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/component.cc @@ -0,0 +1,203 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include +#include + +#include "bank.h" +#include "component.h" +#include "decoder.h" + +using namespace std; +using namespace cacti; + +Component::Component() : area(), power(), rt_power(), delay(0) {} + +Component::~Component() {} + +double Component::compute_diffusion_width(int num_stacked_in, + int num_folded_tr) { + double w_poly = g_ip->F_sz_um; + double spacing_poly_to_poly = + g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact; + double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain + num_stacked_in * w_poly + + (num_stacked_in - 1) * g_tp.spacing_poly_to_poly; + + if (num_folded_tr > 1) { + total_diff_w += + (num_folded_tr - 2) * 2 * spacing_poly_to_poly + + (num_folded_tr - 1) * num_stacked_in * w_poly + + (num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly; + } + + return total_diff_w; +} + +double Component::compute_gate_area(int gate_type, int num_inputs, + double w_pmos, double w_nmos, + double h_gate) { + if (w_pmos <= 0.0 || w_nmos <= 0.0) { + return 0.0; + } + + double w_folded_pmos, w_folded_nmos; + int num_folded_pmos, num_folded_nmos; + double total_ndiff_w, total_pdiff_w; + Area gate; + + double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL; + double ratio_p_to_n = w_pmos / (w_pmos + w_nmos); + + if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0) { + return 0.0; + } + + w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n; + w_folded_nmos = + (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n); + assert(w_folded_pmos > 0); + + num_folded_pmos = (int)(ceil(w_pmos / w_folded_pmos)); + num_folded_nmos = (int)(ceil(w_nmos / w_folded_nmos)); + + switch (gate_type) { + case INV: + total_ndiff_w = compute_diffusion_width(1, num_folded_nmos); + total_pdiff_w = compute_diffusion_width(1, num_folded_pmos); + break; + + case NOR: + total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos); + total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos); + break; + + case NAND: + total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos); + total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos); + break; + default: + cout << "Unknown gate type: " << gate_type << endl; + exit(1); + } + + gate.w = MAX(total_ndiff_w, total_pdiff_w); + + if (w_folded_nmos > w_nmos) { + // means that the height of the gate can + // be made smaller than the input height specified, so calculate the height + // of the gate. + gate.h = + w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL; + } + else { + gate.h = h_gate; + } + return gate.get_area(); +} + +double Component::compute_tr_width_after_folding( + double input_width, + double threshold_folding_width) { // This is actually the width of the cell + // not the width of a device. + // The width of a cell and the width of a device is orthogonal. + if (input_width <= 0) { + return 0; + } + + int num_folded_tr = (int)(ceil(input_width / threshold_folding_width)); + double spacing_poly_to_poly = + g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact; + double width_poly = g_ip->F_sz_um; + double total_diff_width = + num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly; + + return total_diff_width; +} + +double Component::height_sense_amplifier(double pitch_sense_amp) { + // compute the height occupied by all PMOS transistors + double h_pmos_tr = + compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 + + compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) + + 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS; + + // compute the height occupied by all NMOS transistors + double h_nmos_tr = + compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 + + compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) + + 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS; + + // compute total height by considering gap between the p and n diffusion areas + return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS; +} + +int Component::logical_effort(int num_gates_min, double g, double F, + double *w_n, double *w_p, double C_load, + double p_to_n_sz_ratio, bool is_dram_, + bool is_wl_tr_, double max_w_nmos) { + int num_gates = (int)(log(F) / log(fopt)); + + // check if num_gates is odd. if so, add 1 to make it even + num_gates += (num_gates % 2) ? 1 : 0; + num_gates = MAX(num_gates, num_gates_min); + + // recalculate the effective fanout of each stage + double f = pow(F, 1.0 / num_gates); + int i = num_gates - 1; + double C_in = C_load / f; + w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / + gate_C(1, 0, is_dram_, false, is_wl_tr_); + w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_); + w_p[i] = p_to_n_sz_ratio * w_n[i]; + + if (w_n[i] > max_w_nmos) { + double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, + is_wl_tr_); + F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_); + num_gates = (int)(log(F) / log(fopt)) + 1; + num_gates += (num_gates % 2) ? 1 : 0; + num_gates = MAX(num_gates, num_gates_min); + f = pow(F, 1.0 / (num_gates - 1)); + i = num_gates - 1; + w_n[i] = max_w_nmos; + w_p[i] = p_to_n_sz_ratio * w_n[i]; + } + + for (i = num_gates - 2; i >= 1; i--) { + w_n[i] = MAX(w_n[i + 1] / f, g_tp.min_w_nmos_); + w_p[i] = p_to_n_sz_ratio * w_n[i]; + } + + assert(num_gates <= MAX_NUMBER_GATES_STAGE); + return num_gates; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/component.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/component.h new file mode 100644 index 0000000000..713fe4b086 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/component.h @@ -0,0 +1,73 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __COMPONENT_H__ +#define __COMPONENT_H__ + +#include "area.h" +#include "parameter.h" + +using namespace std; + +namespace cacti { + +class Crossbar; +class Bank; + +class Component { + public: + Component(); + ~Component(); + + Area area; + powerDef power, rt_power; + double delay; + double cycle_time; + + double compute_gate_area(int gate_type, int num_inputs, double w_pmos, + double w_nmos, double h_gate); + + double compute_tr_width_after_folding(double input_width, + double threshold_folding_width); + double height_sense_amplifier(double pitch_sense_amp); + + protected: + int logical_effort(int num_gates_min, double g, double F, double *w_n, + double *w_p, double C_load, double p_to_n_sz_ratio, + bool is_dram_, bool is_wl_tr_, double max_w_nmos); + + private: + double compute_diffusion_width(int num_stacked_in, int num_folded_tr); +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/const.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/const.h new file mode 100644 index 0000000000..b92ffeb3a9 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/const.h @@ -0,0 +1,271 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __CONST_H__ +#define __CONST_H__ + +#include +#include +#include +#include +#include + +/* The following are things you might want to change + * when compiling + */ + +/* + * Address bits in a word, and number of output bits from the cache + */ + +/* +was: #define ADDRESS_BITS 32 +now: I'm using 42 bits as in the Power4, +since that's bigger then the 36 bits on the Pentium 4 +and 40 bits on the Opteron +*/ +const int ADDRESS_BITS = 42; + +/*dt: In addition to the tag bits, the tags also include 1 valid bit, 1 dirty + bit, 2 bits for a 4-state cache coherency protocoll (MESI), 1 bit for MRU + (change this to log(ways) for full LRU). So in total we have 1 + 1 + 2 + 1 = 5 +*/ +const int EXTRA_TAG_BITS = 5; + +/* limits on the various N parameters */ + +const unsigned int MAXDATAN = 512; // maximum for Ndwl and Ndbl +const unsigned int MAXSUBARRAYS = + 1048576; // maximum subarrays for data and tag arrays +const unsigned int MAXDATASPD = 256; // maximum for Nspd +const unsigned int MAX_COL_MUX = 256; + +#define ROUTER_TYPES 3 +#define WIRE_TYPES 6 + +const double Cpolywire = 0; + +/* Threshold voltages (as a proportion of Vdd) + If you don't know them, set all values to 0.5 */ +#define VTHFA1 0.452 +#define VTHFA2 0.304 +#define VTHFA3 0.420 +#define VTHFA4 0.413 +#define VTHFA5 0.405 +#define VTHFA6 0.452 +#define VSINV 0.452 +#define VTHCOMPINV 0.437 +#define VTHMUXNAND 0.548 // TODO : this constant must be revisited +#define VTHEVALINV 0.452 +#define VTHSENSEEXTDRV 0.438 + +// WmuxdrvNANDn and WmuxdrvNANDp are no longer being used but it's part of the +// old delay_comparator function which we are using exactly as it used to be, +// so just setting these to 0 +const double WmuxdrvNANDn = 0; +const double WmuxdrvNANDp = 0; + +/*===================================================================*/ +/* + * The following are things you probably wouldn't want to change. + */ + +#define BIGNUM 1e30 +#define INF 9999999 +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/* Used to communicate with the horowitz model */ +#define RISE 1 +#define FALL 0 +#define NCH 1 +#define PCH 0 + +#define EPSILON \ + 0.5 // v4.1: This constant is being used in order to fix floating point -> + // integer +// conversion problems that were occuring within CACTI. Typical problem that was +// occuring was that with different compilers a floating point number like 3.0 +// would get represented as either 2.9999....or 3.00000001 and then the integer +// part of the floating point number (3.0) would be computed differently +// depending on the compiler. What we are doing now is to replace int (x) with +// (int) (x+EPSILON) where EPSILON is 0.5. This would fix such problems. Note +// that this works only when x is an integer >= 0. +/* + * Sheng thinks this is more a solution to solve the simple truncate problem + * (http://www.cs.tut.fi/~jkorpela/round.html) rather than the problem mentioned + * above. Unfortunately, this solution causes nasty bugs (different results when + * using O0 and O3). Moreover, round is not correct in CACTI since when an extra + * fraction of bit/line is needed, we need to provide a complete bit/line even + * the fraction is just 0.01. So, in later version than 6.5 we use (int)ceil() + * to get double to int conversion. + */ + +#define EPSILON2 0.1 +#define EPSILON3 0.6 + +#define MINSUBARRAYROWS \ + 16 // For simplicity in modeling, for the row decoding structure, we assume +// that each row predecode block is composed of at least one 2-4 decoder. When +// the outputs from the row predecode blocks are combined this means that there +// are at least 4*4=16 row decode outputs +#define MAXSUBARRAYROWS \ + 262144 // Each row predecode block produces a max of 2^9 outputs. So +// the maximum number of row decode outputs will be 2^9*2^9 +#define MINSUBARRAYCOLS 2 +#define MAXSUBARRAYCOLS 262144 + +#define INV 0 +#define NOR 1 +#define NAND 2 + +#define NUMBER_TECH_FLAVORS 4 + +#define NUMBER_INTERCONNECT_PROJECTION_TYPES 2 // aggressive and conservative +// 0 = Aggressive projections, 1 = Conservative projections +#define NUMBER_WIRE_TYPES 4 // local, semi-global and global +// 1 = 'Semi-global' wire type, 2 = 'Global' wire type + +const int dram_cell_tech_flavor = 3; + +#define VBITSENSEMIN \ + 0.08 // minimum bitline sense voltage is fixed to be 80 + // mV. + +#define fopt 4.0 + +#define INPUT_WIRE_TO_INPUT_GATE_CAP_RATIO 0 +#define BUFFER_SEPARATION_LENGTH_MULTIPLIER 1 +#define NUMBER_MATS_PER_REDUNDANT_MAT 8 + +#define NUMBER_STACKED_DIE_LAYERS 1 + +// this variable can be set to carry out solution optimization for +// a maximum area allocation. +#define STACKED_DIE_LAYER_ALLOTED_AREA_mm2 0 // 6.24 //6.21//71.5 + +// this variable can also be employed when solution optimization +// with maximum area allocation is carried out. +#define MAX_PERCENT_AWAY_FROM_ALLOTED_AREA 50 + +// this variable can also be employed when solution optimization +// with maximum area allocation is carried out. +#define MIN_AREA_EFFICIENCY 20 + +// this variable can be employed when solution with a desired +// aspect ratio is required. +#define STACKED_DIE_LAYER_ASPECT_RATIO 1 + +// this variable can be employed when solution with a desired +// aspect ratio is required. +#define MAX_PERCENT_AWAY_FROM_ASPECT_RATIO 101 + +// this variable can be employed to carry out solution optimization +// for a certain target random cycle time. +#define TARGET_CYCLE_TIME_ns 1000000000 + +#define NUMBER_PIPELINE_STAGES 4 + +// this can be used to model the length of interconnect +// between a bank and a crossbar +#define LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR 0 // 3791 // 2880//micron + +#define IS_CROSSBAR 0 +#define NUMBER_INPUT_PORTS_CROSSBAR 8 +#define NUMBER_OUTPUT_PORTS_CROSSBAR 8 +#define NUMBER_SIGNALS_PER_PORT_CROSSBAR 256 + +#define MAT_LEAKAGE_REDUCTION_DUE_TO_SLEEP_TRANSISTORS_FACTOR 1 +#define LEAKAGE_REDUCTION_DUE_TO_LONG_CHANNEL_HP_TRANSISTORS_FACTOR 1 + +#define PAGE_MODE 0 + +#define MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA 60 +// We are actually not using this variable in the CACTI code. We just want to +// acknowledge that this current should be multiplied by the DDR(n) system VDD +// value to compute the standby power consumed during precharge. + +const double VDD_STORAGE_LOSS_FRACTION_WORST = 0.125; +const double CU_RESISTIVITY = 0.022; // ohm-micron +const double BULK_CU_RESISTIVITY = 0.018; // ohm-micron +const double PERMITTIVITY_FREE_SPACE = 8.854e-18; // F/micron + +const static uint32_t sram_num_cells_wl_stitching_ = 16; +const static uint32_t dram_num_cells_wl_stitching_ = 64; +const static uint32_t comm_dram_num_cells_wl_stitching_ = 256; +const static double num_bits_per_ecc_b_ = 8.0; + +const double bit_to_byte = 8.0; + +#define MAX_NUMBER_GATES_STAGE 20 +#define MAX_NUMBER_HTREE_NODES 20 +#define NAND2_LEAK_STACK_FACTOR 0.2 +#define NAND3_LEAK_STACK_FACTOR 0.2 +#define NOR2_LEAK_STACK_FACTOR 0.2 +#define INV_LEAK_STACK_FACTOR 0.5 +#define MAX_NUMBER_ARRAY_PARTITIONS 1000000 + +// abbreviations used in this project +// ---------------------------------- +// +// num : number +// rw : read/write +// rd : read +// wr : write +// se : single-ended +// sz : size +// F : feature +// w : width +// h : height or horizontal +// v : vertical or velocity + +enum ram_cell_tech_type_num { + itrs_hp = 0, + itrs_lstp = 1, + itrs_lop = 2, + lp_dram = 3, + comm_dram = 4 +}; + +const double pppm[4] = {1, 1, 1, 1}; +const double pppm_lkg[4] = {0, 1, 1, 0}; +const double pppm_dyn[4] = {1, 0, 0, 0}; +const double pppm_Isub[4] = {0, 1, 0, 0}; +const double pppm_Ig[4] = {0, 0, 1, 0}; +const double pppm_sc[4] = {0, 0, 0, 1}; + +const double Ilinear_to_Isat_ratio = 2.0; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/crossbar.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/crossbar.cc new file mode 100644 index 0000000000..e8566672ca --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/crossbar.cc @@ -0,0 +1,183 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "crossbar.h" + +#define ASPECT_THRESHOLD .8 +#define ADJ 1 +using namespace cacti; + +Crossbar::Crossbar(double n_inp_, double n_out_, double flit_size_, + TechnologyParameter::DeviceType *dt) + : n_inp(n_inp_), n_out(n_out_), flit_size(flit_size_), deviceType(dt) { + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + Vdd = dt->Vdd; + CB_ADJ = 1; +} + +Crossbar::~Crossbar() {} + +double Crossbar::output_buffer() { + // Wire winit(4, 4); + double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; + Wire w1(g_ip->wt, l_eff); + // double s1 = w1.repeater_size *l_eff*ADJ/w1.repeater_spacing; + double s1 = + w1.repeater_size * + (l_eff < w1.repeater_spacing ? l_eff * ADJ / w1.repeater_spacing : ADJ); + double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; + // the model assumes input capacitance of the wire driver = input capacitance + // of nand + nor = input cap of the driver transistor + TriS1 = s1 * (1 + pton_size) / (2 + pton_size + 1 + 2 * pton_size); + TriS2 = s1; // driver transistor + + if (TriS1 < 1) + TriS1 = 1; + + double input_cap = gate_C(TriS1 * (2 * min_w_pmos + g_tp.min_w_nmos_), 0) + + gate_C(TriS1 * (min_w_pmos + 2 * g_tp.min_w_nmos_), 0); + // input_cap += drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + // + + // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 + + // gate_C(TriS2*g_tp.min_w_nmos_, 0)+ + // drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 + + // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + // gate_C(TriS2*min_w_pmos, 0); + tri_int_cap = drain_C_(TriS1 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 + + gate_C(TriS2 * g_tp.min_w_nmos_, 0) + + drain_C_(TriS1 * min_w_pmos, NCH, 1, 1, g_tp.cell_h_def) * 2 + + drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(TriS2 * min_w_pmos, 0); + double output_cap = + drain_C_(TriS2 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(TriS2 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def); + double ctr_cap = gate_C(TriS2 * (min_w_pmos + g_tp.min_w_nmos_), 0); + + tri_inp_cap = input_cap; + tri_out_cap = output_cap; + tri_ctr_cap = ctr_cap; + return input_cap + output_cap + ctr_cap; +} + +void Crossbar::compute_power() { + Wire winit(4, 4); + double tri_cap = output_buffer(); + assert(tri_cap > 0); + // area of a tristate logic + double g_area = compute_gate_area(INV, 1, TriS2 * g_tp.min_w_nmos_, + TriS2 * min_w_pmos, g_tp.cell_h_def); + g_area *= 2; // to model area of output transistors + g_area += compute_gate_area(NAND, 2, TriS1 * 2 * g_tp.min_w_nmos_, + TriS1 * min_w_pmos, g_tp.cell_h_def); + g_area += compute_gate_area(NOR, 2, TriS1 * g_tp.min_w_nmos_, + TriS1 * 2 * min_w_pmos, g_tp.cell_h_def); + double width /*per tristate*/ = g_area / (CB_ADJ * g_tp.cell_h_def); + // effective no. of tristate buffers that need to be laid side by side + int ntri = (int)ceil(g_tp.cell_h_def / (g_tp.wire_outside_mat.pitch)); + double wire_len = MAX(width * ntri * n_out, + flit_size * g_tp.wire_outside_mat.pitch * n_out); + Wire w1(g_ip->wt, wire_len); + + area.w = wire_len; + area.h = g_tp.wire_outside_mat.pitch * n_inp * flit_size * CB_ADJ; + Wire w2(g_ip->wt, area.h); + + double aspect_ratio_cb = (area.h / area.w) * (n_out / n_inp); + if (aspect_ratio_cb > 1) + aspect_ratio_cb = 1 / aspect_ratio_cb; + + if (aspect_ratio_cb < ASPECT_THRESHOLD) { + if (n_out > 2 && n_inp > 2) { + CB_ADJ += 0.2; + // cout << "CB ADJ " << CB_ADJ << endl; + if (CB_ADJ < 4) { + this->compute_power(); + } + } + } + + power.readOp.dynamic = + (w1.power.readOp.dynamic + w2.power.readOp.dynamic + + (tri_inp_cap * n_out + tri_out_cap * n_inp + tri_ctr_cap + tri_int_cap) * + Vdd * Vdd) * + flit_size; + power.readOp.leakage = n_inp * n_out * flit_size * + (cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS2 * 2, + min_w_pmos * TriS2 * 2, 1, inv) * + Vdd + + cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, + min_w_pmos * TriS1 * 3, 2, nand) * + Vdd + + cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, + min_w_pmos * TriS1 * 3, 2, nor) * + Vdd + + w1.power.readOp.leakage + w2.power.readOp.leakage); + power.readOp.gate_leakage = + n_inp * n_out * flit_size * + (cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2, 1, + inv) * + Vdd + + cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 2, + nand) * + Vdd + + cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 2, + nor) * + Vdd + + w1.power.readOp.gate_leakage + w2.power.readOp.gate_leakage); + + // delay calculation + double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; + Wire wdriver(g_ip->wt, l_eff); + double res = g_tp.wire_outside_mat.R_per_um * (area.w + area.h) + + tr_R_on(g_tp.min_w_nmos_ * wdriver.repeater_size, NCH, 1); + double cap = g_tp.wire_outside_mat.C_per_um * (area.w + area.h) + + n_out * tri_inp_cap + n_inp * tri_out_cap; + delay = horowitz(w1.signal_rise_time(), res * cap, + deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + + // Wire wreset(); +} + +void Crossbar::print_crossbar() { + cout << "\nCrossbar Stats (" << n_inp << "x" << n_out << ")\n\n"; + cout << "Flit size : " << flit_size << " bits" << endl; + cout << "Width : " << area.w << " u" << endl; + cout << "Height : " << area.h << " u" << endl; + cout << "Dynamic Power : " + << power.readOp.dynamic * 1e9 * MIN(n_inp, n_out) << " (nJ)" << endl; + cout << "Leakage Power : " << power.readOp.leakage * 1e3 << " (mW)" + << endl; + cout << "Gate Leakage Power : " << power.readOp.gate_leakage * 1e3 + << " (mW)" << endl; + cout << "Crossbar Delay : " << delay * 1e12 << " ps\n"; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/crossbar.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/crossbar.h new file mode 100644 index 0000000000..db4b342377 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/crossbar.h @@ -0,0 +1,80 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __CROSSBAR__ +#define __CROSSBAR__ + +#include +#include +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "mat.h" +#include "parameter.h" +#include "wire.h" + +namespace cacti { + +class Crossbar : public Component { + public: + Crossbar(double in, double out, double flit_sz, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + ~Crossbar(); + + void print_crossbar(); + double output_buffer(); + void compute_power(); + + double n_inp, n_out; + double flit_size; + double tri_inp_cap, tri_out_cap, tri_ctr_cap, tri_int_cap; + + private: + double CB_ADJ; + /* + * Adjust factor of the height of the cross-point (tri-state buffer) cell + * (layout) in crossbar buffer is adjusted to get an aspect ratio of whole + * cross bar close to one; when adjust the ratio, the number of wires route + * over the tri-state buffers does not change, however, the effective wiring + * pitch changes. Specifically, since CB_ADJ will increase during the adjust, + * the tri-state buffer will become taller and thiner, and the effective + * wiring pitch will increase. As a result, the height of the crossbar + * (area.h) will increase. + */ + + TechnologyParameter::DeviceType *deviceType; + double TriS1, TriS2; + double min_w_pmos, Vdd; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/decoder.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/decoder.cc new file mode 100644 index 0000000000..7cd202a8d2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/decoder.cc @@ -0,0 +1,1646 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "decoder.h" +#include +#include +#include +#include "area.h" +#include "parameter.h" + +using namespace std; +using namespace cacti; + +Decoder::Decoder(int _num_dec_signals, bool flag_way_select, + double _C_ld_dec_out, double _R_wire_dec_out, + bool fully_assoc_, bool is_dram_, bool is_wl_tr_, + const Area &cell_, bool power_gating_, int nodes_DSTN_) + : exist(false), + C_ld_dec_out(_C_ld_dec_out), + R_wire_dec_out(_R_wire_dec_out), + num_gates(0), + num_gates_min(2), + delay(0), + // power(), + fully_assoc(fully_assoc_), + is_dram(is_dram_), + is_wl_tr(is_wl_tr_), + total_driver_nwidth(0), + total_driver_pwidth(0), + sleeptx(NULL), + cell(cell_), + nodes_DSTN(nodes_DSTN_), + power_gating(power_gating_) { + for (int i = 0; i < MAX_NUMBER_GATES_STAGE; i++) { + w_dec_n[i] = 0; + w_dec_p[i] = 0; + } + + /* + * _num_dec_signals is the number of decoded signal as output + * num_addr_bits_dec is the number of signal to be decoded + * as the decoders input. + */ + int num_addr_bits_dec = _log2(_num_dec_signals); + + if (num_addr_bits_dec < 4) { + if (flag_way_select) { + exist = true; + num_in_signals = 2; + } + else { + num_in_signals = 0; + } + } + else { + exist = true; + + if (flag_way_select) { + num_in_signals = 3; + } + else { + num_in_signals = 2; + } + } + + assert(cell.h > 0); + assert(cell.w > 0); + // the height of a row-decoder-driver cell is fixed to be 4 * cell.h; + // area.h = 4 * cell.h; + area.h = g_tp.h_dec * cell.h; + + compute_widths(); + compute_area(); +} + +void Decoder::compute_widths() { + double F; + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram, is_wl_tr); + double gnand2 = (2 + p_to_n_sz_ratio) / (1 + p_to_n_sz_ratio); + double gnand3 = (3 + p_to_n_sz_ratio) / (1 + p_to_n_sz_ratio); + + if (exist) { + if (num_in_signals == 2 || fully_assoc) { + w_dec_n[0] = 2 * g_tp.min_w_nmos_; + w_dec_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_; + F = gnand2; + } + else { + w_dec_n[0] = 3 * g_tp.min_w_nmos_; + w_dec_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_; + F = gnand3; + } + + F *= C_ld_dec_out / (gate_C(w_dec_n[0], 0, is_dram, false, is_wl_tr) + + gate_C(w_dec_p[0], 0, is_dram, false, is_wl_tr)); + num_gates = + logical_effort(num_gates_min, num_in_signals == 2 ? gnand2 : gnand3, F, + w_dec_n, w_dec_p, C_ld_dec_out, p_to_n_sz_ratio, is_dram, + is_wl_tr, g_tp.max_w_nmos_dec); + } +} + +void Decoder::compute_area() { + double cumulative_area = 0; + double cumulative_curr = 0; // cumulative leakage current + double cumulative_curr_Ig = 0; // cumulative leakage current + + if (exist) { // First check if this decoder exists + if (num_in_signals == 2) { + cumulative_area = + compute_gate_area(NAND, 2, w_dec_p[0], w_dec_n[0], area.h); + cumulative_curr = + cmos_Isub_leakage(w_dec_n[0], w_dec_p[0], 2, nand, is_dram); + cumulative_curr_Ig = + cmos_Ig_leakage(w_dec_n[0], w_dec_p[0], 2, nand, is_dram); + } + else if (num_in_signals == 3) { + cumulative_area = + compute_gate_area(NAND, 3, w_dec_p[0], w_dec_n[0], area.h); + cumulative_curr = + cmos_Isub_leakage(w_dec_n[0], w_dec_p[0], 3, nand, is_dram); + ; + cumulative_curr_Ig = + cmos_Ig_leakage(w_dec_n[0], w_dec_p[0], 3, nand, is_dram); + } + + for (int i = 1; i < num_gates; i++) { + cumulative_area += + compute_gate_area(INV, 1, w_dec_p[i], w_dec_n[i], area.h); + cumulative_curr += + cmos_Isub_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram); + cumulative_curr_Ig = + cmos_Ig_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram); + } + power.readOp.leakage = cumulative_curr * g_tp.peri_global.Vdd; + power.readOp.power_gated_leakage = + cumulative_curr * g_tp.peri_global.Vcc_min; + power.readOp.gate_leakage = cumulative_curr_Ig * g_tp.peri_global.Vdd; + + area.w = (cumulative_area / area.h); + if (power_gating) { + compute_power_gating(); + cumulative_area += sleeptx->area.get_area(); + area.w = (cumulative_area / area.h); + } + } +} + +void Decoder::compute_power_gating() { + // For all driver chains there is only one sleep transistors to save area + // Total transistor width for sleep tx calculation + for (int i = 0; i < num_gates; i++) { + total_driver_nwidth += w_dec_n[i]; + total_driver_pwidth += w_dec_p[i]; + } + + // compute sleep tx + bool is_footer = false; + double Isat_subarray = simplified_nmos_Isat(total_driver_nwidth); + double detalV; + double c_wakeup; + + c_wakeup = drain_C_(total_driver_pwidth, PCH, 1, 1, cell.h); // Psleep tx + detalV = g_tp.peri_global.Vdd - g_tp.peri_global.Vcc_min; + // if (g_ip->power_gating) + sleeptx = new Sleep_tx(g_ip->perfloss, Isat_subarray, is_footer, c_wakeup, + detalV, nodes_DSTN, area); +} + +double Decoder::compute_delays(double inrisetime) { + if (exist) { + double ret_val = 0; // outrisetime + int i; + double rd, tf, this_delay, c_load, c_intrinsic, Vpp; + double Vdd = g_tp.peri_global.Vdd; + + if ((is_wl_tr) && (is_dram)) { + Vpp = g_tp.vpp; + } + else if (is_wl_tr) { + Vpp = g_tp.sram_cell.Vdd; + } + else { + Vpp = g_tp.peri_global.Vdd; + } + + // first check whether a decoder is required at all + rd = tr_R_on(w_dec_n[0], NCH, num_in_signals, is_dram, false, is_wl_tr); + c_load = gate_C(w_dec_n[1] + w_dec_p[1], 0.0, is_dram, false, is_wl_tr); + c_intrinsic = + drain_C_(w_dec_p[0], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) * + num_in_signals + + drain_C_(w_dec_n[0], NCH, num_in_signals, 1, area.h, is_dram, false, + is_wl_tr); + tf = rd * (c_intrinsic + c_load); + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay += this_delay; + inrisetime = this_delay / (1.0 - 0.5); + power.readOp.dynamic += (c_load + c_intrinsic) * Vdd * Vdd; + // cout<<"w_dec_n["<<0<<"] = "<blk), blk2(drv2_->blk), drv1(drv1_), drv2(drv2_) { + driver_power.readOp.leakage = drv1->power_nand2_path.readOp.leakage + + drv1->power_nand3_path.readOp.leakage + + drv2->power_nand2_path.readOp.leakage + + drv2->power_nand3_path.readOp.leakage; + block_power.readOp.leakage = + blk1->power_nand2_path.readOp.leakage + + blk1->power_nand3_path.readOp.leakage + blk1->power_L2.readOp.leakage + + blk2->power_nand2_path.readOp.leakage + + blk2->power_nand3_path.readOp.leakage + blk2->power_L2.readOp.leakage; + + driver_power.readOp.power_gated_leakage = + drv1->power_nand2_path.readOp.power_gated_leakage + + drv1->power_nand3_path.readOp.power_gated_leakage + + drv2->power_nand2_path.readOp.power_gated_leakage + + drv2->power_nand3_path.readOp.power_gated_leakage; + block_power.readOp.power_gated_leakage = + blk1->power_nand2_path.readOp.power_gated_leakage + + blk1->power_nand3_path.readOp.power_gated_leakage + + blk1->power_L2.readOp.power_gated_leakage + + blk2->power_nand2_path.readOp.power_gated_leakage + + blk2->power_nand3_path.readOp.power_gated_leakage + + blk2->power_L2.readOp.power_gated_leakage; + + power.readOp.leakage = + driver_power.readOp.leakage + block_power.readOp.leakage; + + power.readOp.power_gated_leakage = driver_power.readOp.power_gated_leakage + + block_power.readOp.power_gated_leakage; + + driver_power.readOp.gate_leakage = + drv1->power_nand2_path.readOp.gate_leakage + + drv1->power_nand3_path.readOp.gate_leakage + + drv2->power_nand2_path.readOp.gate_leakage + + drv2->power_nand3_path.readOp.gate_leakage; + block_power.readOp.gate_leakage = blk1->power_nand2_path.readOp.gate_leakage + + blk1->power_nand3_path.readOp.gate_leakage + + blk1->power_L2.readOp.gate_leakage + + blk2->power_nand2_path.readOp.gate_leakage + + blk2->power_nand3_path.readOp.gate_leakage + + blk2->power_L2.readOp.gate_leakage; + power.readOp.gate_leakage = + driver_power.readOp.gate_leakage + block_power.readOp.gate_leakage; +} + +void PredecBlkDrv::leakage_feedback(double temperature) { + double leak_nand2_path = 0; + double leak_nand3_path = 0; + double gate_leak_nand2_path = 0; + double gate_leak_nand3_path = 0; + + if (flag_driver_exists) { // first check whether a predecoder block driver is + // needed + for (int i = 0; i < number_gates_nand2_path; ++i) { + leak_nand2_path += cmos_Isub_leakage( + width_nand2_path_n[i], width_nand2_path_p[i], 1, inv, is_dram_); + gate_leak_nand2_path += cmos_Ig_leakage( + width_nand2_path_n[i], width_nand2_path_p[i], 1, inv, is_dram_); + } + leak_nand2_path *= + (num_buffers_driving_1_nand2_load + num_buffers_driving_2_nand2_load + + num_buffers_driving_4_nand2_load); + gate_leak_nand2_path *= + (num_buffers_driving_1_nand2_load + num_buffers_driving_2_nand2_load + + num_buffers_driving_4_nand2_load); + + for (int i = 0; i < number_gates_nand3_path; ++i) { + leak_nand3_path += cmos_Isub_leakage( + width_nand3_path_n[i], width_nand3_path_p[i], 1, inv, is_dram_); + gate_leak_nand3_path += cmos_Ig_leakage( + width_nand3_path_n[i], width_nand3_path_p[i], 1, inv, is_dram_); + } + leak_nand3_path *= + (num_buffers_driving_2_nand3_load + num_buffers_driving_8_nand3_load); + gate_leak_nand3_path *= + (num_buffers_driving_2_nand3_load + num_buffers_driving_8_nand3_load); + + power_nand2_path.readOp.leakage = leak_nand2_path * g_tp.peri_global.Vdd; + power_nand3_path.readOp.leakage = leak_nand3_path * g_tp.peri_global.Vdd; + power_nand2_path.readOp.gate_leakage = + gate_leak_nand2_path * g_tp.peri_global.Vdd; + power_nand3_path.readOp.gate_leakage = + gate_leak_nand3_path * g_tp.peri_global.Vdd; + } +} + +double Predec::compute_delays(double inrisetime) { + // TODO: Jung Ho thinks that predecoder block driver locates between decoder + // and predecoder block. + pair tmp_pair1, tmp_pair2; + tmp_pair1 = drv1->compute_delays(inrisetime, inrisetime); + tmp_pair1 = blk1->compute_delays(tmp_pair1); + tmp_pair2 = drv2->compute_delays(inrisetime, inrisetime); + tmp_pair2 = blk2->compute_delays(tmp_pair2); + tmp_pair1 = get_max_delay_before_decoder(tmp_pair1, tmp_pair2); + + driver_power.readOp.dynamic = + drv1->num_addr_bits_nand2_path() * drv1->power_nand2_path.readOp.dynamic + + drv1->num_addr_bits_nand3_path() * drv1->power_nand3_path.readOp.dynamic + + drv2->num_addr_bits_nand2_path() * drv2->power_nand2_path.readOp.dynamic + + drv2->num_addr_bits_nand3_path() * drv2->power_nand3_path.readOp.dynamic; + + block_power.readOp.dynamic = + blk1->power_nand2_path.readOp.dynamic * blk1->num_L1_active_nand2_path + + blk1->power_nand3_path.readOp.dynamic * blk1->num_L1_active_nand3_path + + blk1->power_L2.readOp.dynamic + + blk2->power_nand2_path.readOp.dynamic * blk1->num_L1_active_nand2_path + + blk2->power_nand3_path.readOp.dynamic * blk1->num_L1_active_nand3_path + + blk2->power_L2.readOp.dynamic; + + power.readOp.dynamic = + driver_power.readOp.dynamic + block_power.readOp.dynamic; + + delay = tmp_pair1.first; + return tmp_pair1.second; +} + +void Predec::leakage_feedback(double temperature) { + drv1->leakage_feedback(temperature); + drv2->leakage_feedback(temperature); + blk1->leakage_feedback(temperature); + blk2->leakage_feedback(temperature); + + driver_power.readOp.leakage = drv1->power_nand2_path.readOp.leakage + + drv1->power_nand3_path.readOp.leakage + + drv2->power_nand2_path.readOp.leakage + + drv2->power_nand3_path.readOp.leakage; + block_power.readOp.leakage = + blk1->power_nand2_path.readOp.leakage + + blk1->power_nand3_path.readOp.leakage + blk1->power_L2.readOp.leakage + + blk2->power_nand2_path.readOp.leakage + + blk2->power_nand3_path.readOp.leakage + blk2->power_L2.readOp.leakage; + power.readOp.leakage = + driver_power.readOp.leakage + block_power.readOp.leakage; + + driver_power.readOp.gate_leakage = + drv1->power_nand2_path.readOp.gate_leakage + + drv1->power_nand3_path.readOp.gate_leakage + + drv2->power_nand2_path.readOp.gate_leakage + + drv2->power_nand3_path.readOp.gate_leakage; + block_power.readOp.gate_leakage = blk1->power_nand2_path.readOp.gate_leakage + + blk1->power_nand3_path.readOp.gate_leakage + + blk1->power_L2.readOp.gate_leakage + + blk2->power_nand2_path.readOp.gate_leakage + + blk2->power_nand3_path.readOp.gate_leakage + + blk2->power_L2.readOp.gate_leakage; + power.readOp.gate_leakage = + driver_power.readOp.gate_leakage + block_power.readOp.gate_leakage; +} + +// returns +pair Predec::get_max_delay_before_decoder( + pair input_pair1, pair input_pair2) { + pair ret_val; + double delay; + + delay = drv1->delay_nand2_path + blk1->delay_nand2_path; + ret_val.first = delay; + ret_val.second = input_pair1.first; + delay = drv1->delay_nand3_path + blk1->delay_nand3_path; + if (ret_val.first < delay) { + ret_val.first = delay; + ret_val.second = input_pair1.second; + } + delay = drv2->delay_nand2_path + blk2->delay_nand2_path; + if (ret_val.first < delay) { + ret_val.first = delay; + ret_val.second = input_pair2.first; + } + delay = drv2->delay_nand3_path + blk2->delay_nand3_path; + if (ret_val.first < delay) { + ret_val.first = delay; + ret_val.second = input_pair2.second; + } + + return ret_val; +} + +Driver::Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, + bool is_dram, bool power_gating_, int nodes_DSTN_) + : number_gates(0), + min_number_gates(2), + c_gate_load(c_gate_load_), + c_wire_load(c_wire_load_), + r_wire_load(r_wire_load_), + delay(0), + // power(), + is_dram_(is_dram), + total_driver_nwidth(0), + total_driver_pwidth(0), + sleeptx(NULL), + nodes_DSTN(nodes_DSTN_), + power_gating(power_gating_) { + for (int i = 0; i < MAX_NUMBER_GATES_STAGE; i++) { + width_n[i] = 0; + width_p[i] = 0; + } + + compute_widths(); + compute_area(); +} + +void Driver::compute_widths() { + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram_); + double c_load = c_gate_load + c_wire_load; + width_n[0] = g_tp.min_w_nmos_; + width_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_; + + double F = c_load / gate_C(width_n[0] + width_p[0], 0, is_dram_); + number_gates = + logical_effort(min_number_gates, 1, F, width_n, width_p, c_load, + p_to_n_sz_ratio, is_dram_, false, g_tp.max_w_nmos_); +} + +void Driver::compute_area() { + double cumulative_area = 0; + + area.h = g_tp.cell_h_def; + for (int i = 0; i < number_gates; i++) { + cumulative_area += + compute_gate_area(INV, 1, width_p[i], width_n[i], area.h); + } + area.w = (cumulative_area / area.h); + if (power_gating) { + compute_power_gating(); + cumulative_area += sleeptx->area.get_area(); + area.w = (cumulative_area / area.h); + } +} + +void Driver::compute_power_gating() { + // For all driver chains there is only one sleep transistors to save area + // Total transistor width for sleep tx calculation + for (int i = 0; i < number_gates; i++) { + total_driver_nwidth += width_n[i]; + total_driver_pwidth += width_p[i]; + } + + // compute sleep tx + bool is_footer = false; + double Isat_subarray = simplified_nmos_Isat(total_driver_nwidth); + double detalV; + double c_wakeup; + + c_wakeup = drain_C_(total_driver_pwidth, PCH, 1, 1, area.h); // Psleep tx + detalV = g_tp.peri_global.Vdd - g_tp.peri_global.Vcc_min; + // if (g_ip->power_gating) + sleeptx = + new Sleep_tx(g_ip->perfloss, Isat_subarray, is_footer, c_wakeup, detalV, + nodes_DSTN, // default is 1 for drivers + area); +} + +double Driver::compute_delay(double inrisetime) { + int i; + double rd, c_load, c_intrinsic, tf; + double this_delay = 0; + + for (i = 0; i < number_gates - 1; ++i) { + rd = tr_R_on(width_n[i], NCH, 1, is_dram_); + c_load = gate_C(width_n[i + 1] + width_p[i + 1], 0.0, is_dram_); + c_intrinsic = drain_C_(width_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) + + drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_); + tf = rd * (c_intrinsic + c_load); + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay += this_delay; + inrisetime = this_delay / (1.0 - 0.5); + power.readOp.dynamic += + (c_intrinsic + c_load) * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + power.readOp.leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + power.readOp.power_gated_leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vcc_min; + power.readOp.gate_leakage += + cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + } + + i = number_gates - 1; + c_load = c_gate_load + c_wire_load; + rd = tr_R_on(width_n[i], NCH, 1, is_dram_); + c_intrinsic = drain_C_(width_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) + + drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_); + tf = rd * (c_intrinsic + c_load) + + r_wire_load * (c_wire_load / 2 + c_gate_load); + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay += this_delay; + power.readOp.dynamic += + (c_intrinsic + c_load) * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + power.readOp.leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + power.readOp.power_gated_leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vcc_min; + power.readOp.gate_leakage += + cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + + return this_delay / (1.0 - 0.5); +} + +// TODO: add sleep tx in predec/predecblk/predecdriver diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/decoder.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/decoder.h new file mode 100644 index 0000000000..ff3265dc45 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/decoder.h @@ -0,0 +1,244 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __DECODER_H__ +#define __DECODER_H__ + +#include +#include "area.h" +#include "component.h" +#include "parameter.h" +#include "powergating.h" + +using namespace std; + +namespace cacti { + +class Decoder : public Component { + public: + Decoder(int _num_dec_signals, bool flag_way_select, double _C_ld_dec_out, + double _R_wire_dec_out, bool fully_assoc_, bool is_dram_, + bool is_wl_tr_, const Area &cell_, bool power_gating_ = false, + int nodes_DSTN_ = 1); + + bool exist; + int num_in_signals; + double C_ld_dec_out; + double R_wire_dec_out; + int num_gates; + int num_gates_min; + double w_dec_n[MAX_NUMBER_GATES_STAGE]; + double w_dec_p[MAX_NUMBER_GATES_STAGE]; + double delay; + // powerDef power; + bool fully_assoc; + bool is_dram; + bool is_wl_tr; + + double total_driver_nwidth; + double total_driver_pwidth; + Sleep_tx *sleeptx; + + const Area &cell; + int nodes_DSTN; + bool power_gating; + + void compute_widths(); + void compute_area(); + double compute_delays(double inrisetime); // return outrisetime + void compute_power_gating(); + + void leakage_feedback(double temperature); + + ~Decoder() { + if (sleeptx != 0) + delete sleeptx; + }; +}; + +class PredecBlk : public Component { + public: + PredecBlk(int num_dec_signals, Decoder *dec, double C_wire_predec_blk_out, + double R_wire_predec_blk_out, int num_dec_per_predec, bool is_dram_, + bool is_blk1); + + Decoder *dec; + bool exist; + int number_input_addr_bits; + double C_ld_predec_blk_out; + double R_wire_predec_blk_out; + int branch_effort_nand2_gate_output; + int branch_effort_nand3_gate_output; + bool flag_two_unique_paths; + int flag_L2_gate; + int number_inputs_L1_gate; + int number_gates_L1_nand2_path; + int number_gates_L1_nand3_path; + int number_gates_L2; + int min_number_gates_L1; + int min_number_gates_L2; + int num_L1_active_nand2_path; + int num_L1_active_nand3_path; + double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE]; + double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE]; + double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE]; + double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE]; + double w_L2_n[MAX_NUMBER_GATES_STAGE]; + double w_L2_p[MAX_NUMBER_GATES_STAGE]; + double delay_nand2_path; + double delay_nand3_path; + powerDef power_nand2_path; + powerDef power_nand3_path; + powerDef power_L2; + + bool is_dram_; + + void compute_widths(); + void compute_area(); + + void leakage_feedback(double temperature); + + pair compute_delays( + pair inrisetime); // + // return +}; + +class PredecBlkDrv : public Component { + public: + PredecBlkDrv(int way_select, PredecBlk *blk_, bool is_dram); + + int flag_driver_exists; + int number_input_addr_bits; + int number_gates_nand2_path; + int number_gates_nand3_path; + int min_number_gates; + int num_buffers_driving_1_nand2_load; + int num_buffers_driving_2_nand2_load; + int num_buffers_driving_4_nand2_load; + int num_buffers_driving_2_nand3_load; + int num_buffers_driving_8_nand3_load; + int num_buffers_nand3_path; + double c_load_nand2_path_out; + double c_load_nand3_path_out; + double r_load_nand2_path_out; + double r_load_nand3_path_out; + double width_nand2_path_n[MAX_NUMBER_GATES_STAGE]; + double width_nand2_path_p[MAX_NUMBER_GATES_STAGE]; + double width_nand3_path_n[MAX_NUMBER_GATES_STAGE]; + double width_nand3_path_p[MAX_NUMBER_GATES_STAGE]; + double delay_nand2_path; + double delay_nand3_path; + powerDef power_nand2_path; + powerDef power_nand3_path; + + PredecBlk *blk; + Decoder *dec; + bool is_dram_; + int way_select; + + void compute_widths(); + void compute_area(); + + void leakage_feedback(double temperature); + + pair compute_delays( + double inrisetime_nand2_path, + double inrisetime_nand3_path); // return + + inline int num_addr_bits_nand2_path() { + return num_buffers_driving_1_nand2_load + num_buffers_driving_2_nand2_load + + num_buffers_driving_4_nand2_load; + } + inline int num_addr_bits_nand3_path() { + return num_buffers_driving_2_nand3_load + num_buffers_driving_8_nand3_load; + } + double get_rdOp_dynamic_E(int num_act_mats_hor_dir); +}; + +class Predec : public Component { + public: + Predec(PredecBlkDrv *drv1, PredecBlkDrv *drv2); + + double compute_delays(double inrisetime); // return outrisetime + + void leakage_feedback(double temperature); + PredecBlk *blk1; + PredecBlk *blk2; + PredecBlkDrv *drv1; + PredecBlkDrv *drv2; + + powerDef block_power; + powerDef driver_power; + + private: + // returns + pair get_max_delay_before_decoder( + pair input_pair1, pair input_pair2); +}; + +class Driver : public Component { + public: + Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, + bool is_dram, bool power_gating_ = false, int nodes_DSTN_ = 1); + + int number_gates; + int min_number_gates; + double width_n[MAX_NUMBER_GATES_STAGE]; + double width_p[MAX_NUMBER_GATES_STAGE]; + double c_gate_load; + double c_wire_load; + double r_wire_load; + double delay; + // powerDef power; + bool is_dram_; + + double total_driver_nwidth; + double total_driver_pwidth; + Sleep_tx *sleeptx; + + int nodes_DSTN; + bool power_gating; + + void compute_widths(); + void compute_area(); + double compute_delay(double inrisetime); + + void compute_power_gating(); + + ~Driver() { + if (sleeptx != 0) + delete sleeptx; + }; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/htree2.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/htree2.cc new file mode 100644 index 0000000000..ab45c501d2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/htree2.cc @@ -0,0 +1,758 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "htree2.h" +#include +#include +#include "wire.h" +using namespace cacti; + +Htree2::Htree2(enum Wire_type wire_model, double mat_w, double mat_h, + int a_bits, int d_inbits, int search_data_in, int d_outbits, + int search_data_out, int bl, int wl, enum Htree_type htree_type, + bool uca_tree_, bool search_tree_, + TechnologyParameter::DeviceType *dt) + : in_rise_time(0), + out_rise_time(0), + tree_type(htree_type), + mat_width(mat_w), + mat_height(mat_h), + add_bits(a_bits), + data_in_bits(d_inbits), + search_data_in_bits(search_data_in), + data_out_bits(d_outbits), + search_data_out_bits(search_data_out), + ndbl(bl), + ndwl(wl), + uca_tree(uca_tree_), + search_tree(search_tree_), + wt(wire_model), + deviceType(dt) { + assert(ndbl >= 2 && ndwl >= 2); + + // if (ndbl == 1 && ndwl == 1) + // { + // delay = 0; + // power.readOp.dynamic = 0; + // power.readOp.leakage = 0; + // area.w = mat_w; + // area.h = mat_h; + // return; + // } + // if (ndwl == 1) ndwl++; + // if (ndbl == 1) ndbl++; + + max_unpipelined_link_delay = 0; // TODO + min_w_nmos = g_tp.min_w_nmos_; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos; + + switch (htree_type) { + case Add_htree: + wire_bw = init_wire_bw = add_bits; + in_htree(); + break; + case Data_in_htree: + wire_bw = init_wire_bw = data_in_bits; + in_htree(); + break; + case Data_out_htree: + wire_bw = init_wire_bw = data_out_bits; + out_htree(); + break; + case Search_in_htree: + wire_bw = init_wire_bw = search_data_in_bits; // in_search_tree is broad + // cast, out_htree is not. + in_htree(); + break; + case Search_out_htree: + wire_bw = init_wire_bw = search_data_out_bits; + out_htree(); + break; + default: + assert(0); + break; + } + + power_bit = power; + power.readOp.dynamic *= init_wire_bw; + + assert(power.readOp.dynamic >= 0); + assert(power.readOp.leakage >= 0); +} + +// nand gate sizing calculation +void Htree2::input_nand(double s1, double s2, double l_eff) { + Wire w1(wt, l_eff); + double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; + // input capacitance of a repeater = input capacitance of nand. + double nsize = s1 * (1 + pton_size) / (2 + pton_size); + nsize = (nsize < 1) ? 1 : nsize; + + double tc = 2 * tr_R_on(nsize * min_w_nmos, NCH, 1) * + (drain_C_(nsize * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) * 2 + + 2 * gate_C(s2 * (min_w_nmos + min_w_pmos), 0)); + delay += horowitz(w1.out_rise_time, tc, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + power.readOp.dynamic += + 0.5 * + (2 * drain_C_(pton_size * nsize * min_w_pmos, PCH, 1, 1, + g_tp.cell_h_def) + + drain_C_(nsize * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + 2 * gate_C(s2 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (2 * drain_C_(pton_size * nsize * min_w_pmos, PCH, 1, 1, + g_tp.cell_h_def) + + drain_C_(nsize * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + 2 * gate_C(s2 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * wire_bw; + power.readOp.leakage += + (wire_bw * cmos_Isub_leakage(min_w_nmos * (nsize * 2), + min_w_pmos * nsize * 2, 2, nand)) * + deviceType->Vdd; + power.readOp.power_gated_leakage += + (wire_bw * cmos_Isub_leakage(min_w_nmos * (nsize * 2), + min_w_pmos * nsize * 2, 2, nand)) * + deviceType->Vcc_min; + power.readOp.gate_leakage += + (wire_bw * cmos_Ig_leakage(min_w_nmos * (nsize * 2), + min_w_pmos * nsize * 2, 2, nand)) * + deviceType->Vdd; +} + +// tristate buffer model consisting of not, nand, nor, and driver transistors +void Htree2::output_buffer(double s1, double s2, double l_eff) { + Wire w1(wt, l_eff); + double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; + // input capacitance of repeater = input capacitance of nand + nor. + double size = s1 * (1 + pton_size) / (2 + pton_size + 1 + 2 * pton_size); + double s_eff = // stage eff of a repeater in a wire + (gate_C(s2 * (min_w_nmos + min_w_pmos), 0) + + w1.wire_cap(l_eff * 1e-6, true)) / + gate_C(s2 * (min_w_nmos + min_w_pmos), 0); + double tr_size = gate_C(s1 * (min_w_nmos + min_w_pmos), 0) * 1 / 2 / + (s_eff * gate_C(min_w_pmos, 0)); + size = (size < 1) ? 1 : size; + + double res_nor = 2 * tr_R_on(size * min_w_pmos, PCH, 1); + double res_ptrans = tr_R_on(tr_size * min_w_nmos, NCH, 1); + double cap_nand_out = + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 + + gate_C(tr_size * min_w_pmos, 0); + double cap_ptrans_out = + 2 * (drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(tr_size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) + + gate_C(s1 * (min_w_nmos + min_w_pmos), 0); + + double tc = res_nor * cap_nand_out + (res_nor + res_ptrans) * cap_ptrans_out; + + delay += horowitz(w1.out_rise_time, tc, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + + // nand + power.readOp.dynamic += + 0.5 * + (2 * drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (2 * drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + // not + power.readOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + // nor + power.readOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + 2 * drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + 2 * drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + // output transistor + power.readOp.dynamic += + 0.5 * + ((drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(tr_size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) * + 2 + + gate_C(s1 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + ((drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(tr_size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) * + 2 + + gate_C(s1 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + if (uca_tree) { + power.readOp.leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vcc_min * wire_bw; /*inverter + output tr*/ + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nand) * + deviceType->Vcc_min * wire_bw; // nand + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nor) * + deviceType->Vcc_min * wire_bw; // nor + + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + // power.readOp.gate_leakage *=; + } + else { + power.readOp.leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vcc_min * wire_bw; /*inverter + output tr*/ + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nand) * + deviceType->Vcc_min * wire_bw; // nand + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nor) * + deviceType->Vcc_min * wire_bw; // nor + + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + // power.readOp.gate_leakage *=deviceType->Vdd*wire_bw; + } +} + +/* calculates the input h-tree delay/power + * A nand gate is used at each node to + * limit the signal + * The area of an unbalanced htree (rows != columns) + * depends on how data is traversed. + * In the following function, if ( no. of rows < no. of columns), + * then data first traverse in excess hor. links until vertical + * and horizontal nodes are same. + * If no. of rows is bigger, then data traverse in + * a hor. link followed by a ver. link in a repeated + * fashion (similar to a balanced tree) until there are no + * hor. links left. After this it goes through the remaining vertical + * links. + */ +void Htree2::in_htree() { + // temp var + double s1 = 0, s2 = 0, s3 = 0; + double l_eff = 0; + Wire *wtemp1 = 0, *wtemp2 = 0, *wtemp3 = 0; + double len = 0, ht = 0; + int option = 0; + + int h = (int)_log2(ndwl / 2); // horizontal nodes + int v = (int)_log2(ndbl / 2); // vertical nodes + double len_temp; + double ht_temp; + if (uca_tree) { // Sheng: this computation do not consider the wires that + // route from edge to middle. + ht_temp = (mat_height * ndbl / 2 + /* since uca_tree models interbank tree, + mat_height => bank height */ + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, h)))) / + 2; + len_temp = (mat_width * ndwl / 2 + + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, v)))) / + 2; + } + else { + if (ndwl == ndbl) { + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndbl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else if (ndwl > ndbl) { + double excess_part = (_log2(ndwl / 2) - _log2(ndbl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + +(search_data_in_bits + search_data_out_bits)) * + ((ndbl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (2 * (1 - pow(0.5, h - v)) + pow(0.5, v - h) * v)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else { + double excess_part = (_log2(ndbl / 2) - _log2(ndwl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (h + 2 * (1 - pow(0.5, v - h)))) / + 2; + } + } + + area.h = ht_temp * 2; + area.w = len_temp * 2; + delay = 0; + power.readOp.dynamic = 0; + power.readOp.leakage = 0; + power.readOp.power_gated_leakage = 0; + power.searchOp.dynamic = 0; + len = len_temp; + ht = ht_temp / 2; + + while (v > 0 || h > 0) { + if (wtemp1) + delete wtemp1; + if (wtemp2) + delete wtemp2; + if (wtemp3) + delete wtemp3; + + if (h > v) { + // the iteration considers only one horizontal link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, len / 2); // ver + len_temp = len; + len /= 2; + wtemp3 = 0; + h--; + option = 0; + } + else if (v > 0 && h > 0) { + // considers one horizontal link and one vertical link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, ht); // ver + wtemp3 = new Wire(wt, len / 2); // next hor + len_temp = len; + ht_temp = ht; + len /= 2; + ht /= 2; + v--; + h--; + option = 1; + } + else { + // considers only one vertical link + assert(h == 0); + wtemp1 = new Wire(wt, ht); // ver + wtemp2 = new Wire(wt, ht / 2); // hor + ht_temp = ht; + ht /= 2; + wtemp3 = 0; + v--; + option = 2; + } + + delay += wtemp1->delay; + power.readOp.dynamic += wtemp1->power.readOp.dynamic; + power.searchOp.dynamic += wtemp1->power.readOp.dynamic * wire_bw; + power.readOp.leakage += wtemp1->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp1->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp1->power.readOp.gate_leakage * wire_bw; + if ((uca_tree == false && option == 2) || search_tree == true) { + wire_bw *= 2; // wire bandwidth doubles only for vertical branches + } + + if (uca_tree == false) { + if (len_temp > wtemp1->repeater_spacing) { + s1 = wtemp1->repeater_size; + l_eff = wtemp1->repeater_spacing; + } + else { + s1 = (len_temp / wtemp1->repeater_spacing) * wtemp1->repeater_size; + l_eff = len_temp; + } + + if (ht_temp > wtemp2->repeater_spacing) { + s2 = wtemp2->repeater_size; + } + else { + s2 = (len_temp / wtemp2->repeater_spacing) * wtemp2->repeater_size; + } + // first level + input_nand(s1, s2, l_eff); + } + + if (option != 1) { + continue; + } + + // second level + delay += wtemp2->delay; + power.readOp.dynamic += wtemp2->power.readOp.dynamic; + power.searchOp.dynamic += wtemp2->power.readOp.dynamic * wire_bw; + power.readOp.leakage += wtemp2->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp2->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + + if (uca_tree) { + power.readOp.leakage += (wtemp2->power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + } + else { + power.readOp.leakage += (wtemp2->power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + wire_bw *= 2; + + if (ht_temp > wtemp3->repeater_spacing) { + s3 = wtemp3->repeater_size; + l_eff = wtemp3->repeater_spacing; + } + else { + s3 = (len_temp / wtemp3->repeater_spacing) * wtemp3->repeater_size; + l_eff = ht_temp; + } + + input_nand(s2, s3, l_eff); + } + } + + if (wtemp1) + delete wtemp1; + if (wtemp2) + delete wtemp2; + if (wtemp3) + delete wtemp3; +} + +/* a tristate buffer is used to handle fan-ins + * The area of an unbalanced htree (rows != columns) + * depends on how data is traversed. + * In the following function, if ( no. of rows < no. of columns), + * then data first traverse in excess hor. links until vertical + * and horizontal nodes are same. + * If no. of rows is bigger, then data traverse in + * a hor. link followed by a ver. link in a repeated + * fashion (similar to a balanced tree) until there are no + * hor. links left. After this it goes through the remaining vertical + * links. + */ +void Htree2::out_htree() { + // temp var + double s1 = 0, s2 = 0, s3 = 0; + double l_eff = 0; + Wire *wtemp1 = 0, *wtemp2 = 0, *wtemp3 = 0; + double len = 0, ht = 0; + int option = 0; + + int h = (int)_log2(ndwl / 2); + int v = (int)_log2(ndbl / 2); + double len_temp; + double ht_temp; + if (uca_tree) { + ht_temp = (mat_height * ndbl / 2 + /* since uca_tree models interbank tree, + mat_height => bank height */ + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, h)))) / + 2; + len_temp = (mat_width * ndwl / 2 + + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, v)))) / + 2; + } + else { + if (ndwl == ndbl) { + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndbl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else if (ndwl > ndbl) { + double excess_part = (_log2(ndwl / 2) - _log2(ndbl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndbl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (2 * (1 - pow(0.5, h - v)) + pow(0.5, v - h) * v)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else { + double excess_part = (_log2(ndbl / 2) - _log2(ndwl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (h + 2 * (1 - pow(0.5, v - h)))) / + 2; + } + } + area.h = ht_temp * 2; + area.w = len_temp * 2; + delay = 0; + power.readOp.dynamic = 0; + power.readOp.leakage = 0; + power.readOp.power_gated_leakage = 0; + power.readOp.gate_leakage = 0; + // cout<<"power.readOp.gate_leakage"< 0 || h > 0) { // finds delay/power of each link in the tree + if (wtemp1) + delete wtemp1; + if (wtemp2) + delete wtemp2; + if (wtemp3) + delete wtemp3; + + if (h > v) { + // the iteration considers only one horizontal link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, len / 2); // ver + len_temp = len; + len /= 2; + wtemp3 = 0; + h--; + option = 0; + } + else if (v > 0 && h > 0) { + // considers one horizontal link and one vertical link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, ht); // ver + wtemp3 = new Wire(wt, len / 2); // next hor + len_temp = len; + ht_temp = ht; + len /= 2; + ht /= 2; + v--; + h--; + option = 1; + } + else { + // considers only one vertical link + assert(h == 0); + wtemp1 = new Wire(wt, ht); // hor + wtemp2 = new Wire(wt, ht / 2); // ver + ht_temp = ht; + ht /= 2; + wtemp3 = 0; + v--; + option = 2; + } + delay += wtemp1->delay; + power.readOp.dynamic += wtemp1->power.readOp.dynamic; + power.searchOp.dynamic += wtemp1->power.readOp.dynamic * init_wire_bw; + power.readOp.leakage += wtemp1->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp1->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp1->power.readOp.gate_leakage * wire_bw; + // cout<<"power.readOp.gate_leakage"< wtemp1->repeater_spacing) { + s1 = wtemp1->repeater_size; + l_eff = wtemp1->repeater_spacing; + } + else { + s1 = (len_temp / wtemp1->repeater_spacing) * wtemp1->repeater_size; + l_eff = len_temp; + } + if (ht_temp > wtemp2->repeater_spacing) { + s2 = wtemp2->repeater_size; + } + else { + s2 = (len_temp / wtemp2->repeater_spacing) * wtemp2->repeater_size; + } + // first level + output_buffer(s1, s2, l_eff); + } + + if (option != 1) { + continue; + } + + // second level + delay += wtemp2->delay; + power.readOp.dynamic += wtemp2->power.readOp.dynamic; + power.searchOp.dynamic += wtemp2->power.readOp.dynamic * init_wire_bw; + power.readOp.leakage += wtemp2->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp2->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + // cout<<"power.readOp.gate_leakage"<power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + } + else { + power.readOp.leakage += (wtemp2->power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + wire_bw *= 2; + + if (ht_temp > wtemp3->repeater_spacing) { + s3 = wtemp3->repeater_size; + l_eff = wtemp3->repeater_spacing; + } + else { + s3 = (len_temp / wtemp3->repeater_spacing) * wtemp3->repeater_size; + l_eff = ht_temp; + } + + output_buffer(s2, s3, l_eff); + } + // cout<<"power.readOp.leakage"<power.readOp.gate_leakage"<power.readOp.gate_leakage< +#include +#include +#include + +#include "Ucache.h" +#include "arbiter.h" +#include "area.h" +#include "basic_circuit.h" +#include "crossbar.h" +#include "io.h" +#include "nuca.h" +#include "parameter.h" +#include "version_cacti.h" +//#include "highradix.h" + +using namespace std; + +namespace cacti { + +InputParameter::InputParameter() + : array_power_gated(false), + bitline_floating(false), + wl_power_gated(false), + cl_power_gated(false), + interconect_power_gated(false), + power_gating(false), + perfloss(0.01), + cl_vertical(true), + long_channel_device(false) { + dvs_voltage = std::vector(0); +} + +/* Parses "cache.cfg" file */ +void InputParameter::parse_cfg(const string &in_file) { + FILE *fp = fopen(in_file.c_str(), "r"); + char line[5000]; + char jk[5000]; + char temp_var[5000]; + double temp_double; + char *data = line; + int offset = 0; + + if (!fp) { + cout << in_file << " is missing!\n"; + exit(-1); + } + + while (fscanf(fp, "%[^\n]\n", line) != EOF) { + if (!strncmp("-size", line, strlen("-size"))) { + sscanf(line, "-size %[(:-~)*]%u", jk, &(cache_sz)); + continue; + } + + if (!strncmp("-page size", line, strlen("-page size"))) { + sscanf(line, "-page size %[(:-~)*]%u", jk, &(page_sz_bits)); + continue; + } + + if (!strncmp("-burst length", line, strlen("-burst length"))) { + sscanf(line, "-burst %[(:-~)*]%u", jk, &(burst_len)); + continue; + } + + if (!strncmp("-internal prefetch width", line, + strlen("-internal prefetch width"))) { + sscanf(line, "-internal prefetch %[(:-~)*]%u", jk, &(int_prefetch_w)); + continue; + } + + if (!strncmp("-block", line, strlen("-block"))) { + sscanf(line, "-block size (bytes) %d", &(line_sz)); + continue; + } + + if (!strncmp("-associativity", line, strlen("-associativity"))) { + sscanf(line, "-associativity %d", &(assoc)); + continue; + } + + if (!strncmp("-read-write", line, strlen("-read-write"))) { + sscanf(line, "-read-write port %d", &(num_rw_ports)); + continue; + } + + if (!strncmp("-exclusive read", line, strlen("exclusive read"))) { + sscanf(line, "-exclusive read port %d", &(num_rd_ports)); + continue; + } + + if (!strncmp("-exclusive write", line, strlen("-exclusive write"))) { + sscanf(line, "-exclusive write port %d", &(num_wr_ports)); + continue; + } + + if (!strncmp("-single ended", line, strlen("-single ended"))) { + sscanf(line, "-single %[(:-~)*]%d", jk, &(num_se_rd_ports)); + continue; + } + + if (!strncmp("-search", line, strlen("-search"))) { + sscanf(line, "-search port %d", &(num_search_ports)); + continue; + } + + if (!strncmp("-UCA bank", line, strlen("-UCA bank"))) { + sscanf(line, "-UCA bank%[((:-~)| )*]%d", jk, &(nbanks)); + continue; + } + + if (!strncmp("-technology", line, strlen("-technology"))) { + sscanf(line, "-technology (u) %lf", &(F_sz_um)); + F_sz_nm = F_sz_um * 1000; + continue; + } + + if (!strncmp("-hp Vdd", line, strlen("-hp Vdd"))) { + sscanf(line, "-hp Vdd%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_hp_vdd = false; + hp_Vdd = 1.0; /* + * if this is by default, then the vdd value in g_ip here + * does not matter + */ + } + else { + specific_hp_vdd = true; + sscanf(line, "-hp Vdd (V) %lf", &(hp_Vdd)); + } + continue; + } + + if (!strncmp("-lstp Vdd", line, strlen("-lstp Vdd"))) { + sscanf(line, "-lstp Vdd%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_lstp_vdd = false; + lstp_Vdd = 1.0; /* + * if this is by default, then the vdd value in g_ip + * here does not matter + */ + } + else { + specific_lstp_vdd = true; + sscanf(line, "-lstp Vdd (V) %lf", &(lstp_Vdd)); + } + continue; + } + + if (!strncmp("-lop Vdd", line, strlen("-lop Vdd"))) { + sscanf(line, "-lop Vdd%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_lop_vdd = false; + lop_Vdd = 1.0; /* + * if this is by default, then the vdd value in g_ip here + * does not matter + */ + } + else { + specific_lop_vdd = true; + sscanf(line, "-lop Vdd (V) %lf", &(lop_Vdd)); + } + continue; + } + + if (!strncmp("-DVS(V):", line, strlen("-DVS(V):"))) { + memmove(line, line + 9, strlen(line)); + while (1 == sscanf(data, "%lf%n", &temp_double, &offset)) { + data += offset; + dvs_voltage.push_back(temp_double); + } + // dvs_levels = dvs_voltage.size(); + continue; + } + + if (!strncmp("-Powergating voltage", line, + strlen("-Powergating voltage"))) { + sscanf(line, "-Powergating voltage%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_vcc_min = false; + user_defined_vcc_min = 1.0; /* + * if this is by default, then the vdd value + * in g_ip here does not matter + */ + } + else { + specific_vcc_min = true; + sscanf(line, "-Powergating voltage (V) %lf", &(user_defined_vcc_min)); + } + continue; + } + + if (!strncmp("-output/input", line, strlen("-output/input"))) { + sscanf(line, "-output/input bus %[(:-~)*]%d", jk, &(out_w)); + continue; + } + + if (!strncmp("-operating temperature", line, + strlen("-operating temperature"))) { + sscanf(line, "-operating temperature %[(:-~)*]%d", jk, &(temp)); + continue; + } + + if (!strncmp("-cache type", line, strlen("-cache type"))) { + sscanf(line, "-cache type%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("cache", temp_var, sizeof("cache"))) { + is_cache = true; + } + else { + is_cache = false; + } + + if (!strncmp("main memory", temp_var, sizeof("main memory"))) { + is_main_mem = true; + } + else { + is_main_mem = false; + } + + if (!strncmp("cam", temp_var, sizeof("cam"))) { + pure_cam = true; + } + else { + pure_cam = false; + } + + if (!strncmp("ram", temp_var, sizeof("ram"))) { + pure_ram = true; + } + else { + if (!is_main_mem) + pure_ram = false; + else + pure_ram = true; + } + + continue; + } + + if (!strncmp("-tag size", line, strlen("-tag size"))) { + sscanf(line, "-tag size%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_tag = false; + tag_w = + 42; /* the acutal value is calculated + * later based on the cache size, bank count, and associativity + */ + } + else { + specific_tag = true; + sscanf(line, "-tag size (b) %d", &(tag_w)); + } + continue; + } + + if (!strncmp("-access mode", line, strlen("-access mode"))) { + sscanf(line, "-access %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("fast", temp_var, strlen("fast"))) { + access_mode = 2; + } + else if (!strncmp("sequential", temp_var, strlen("sequential"))) { + access_mode = 1; + } + else if (!strncmp("normal", temp_var, strlen("normal"))) { + access_mode = 0; + } + else { + cout << "ERROR: Invalid access mode!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Data array cell type", line, + strlen("-Data array cell type"))) { + sscanf(line, "-Data array cell type %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + data_arr_ram_cell_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + data_arr_ram_cell_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + data_arr_ram_cell_tech_type = 2; + } + else if (!strncmp("lp-dram", temp_var, strlen("lp-dram"))) { + data_arr_ram_cell_tech_type = 3; + } + else if (!strncmp("comm-dram", temp_var, strlen("comm-dram"))) { + data_arr_ram_cell_tech_type = 4; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Data array peripheral type", line, + strlen("-Data array peripheral type"))) { + sscanf(line, "-Data array peripheral type %[^\"]\"%[^\"]\"", jk, + temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + data_arr_peri_global_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + data_arr_peri_global_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + data_arr_peri_global_tech_type = 2; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Tag array cell type", line, + strlen("-Tag array cell type"))) { + sscanf(line, "-Tag array cell type %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + tag_arr_ram_cell_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + tag_arr_ram_cell_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + tag_arr_ram_cell_tech_type = 2; + } + else if (!strncmp("lp-dram", temp_var, strlen("lp-dram"))) { + tag_arr_ram_cell_tech_type = 3; + } + else if (!strncmp("comm-dram", temp_var, strlen("comm-dram"))) { + tag_arr_ram_cell_tech_type = 4; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Tag array peripheral type", line, + strlen("-Tag array peripheral type"))) { + sscanf(line, "-Tag array peripheral type %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + tag_arr_peri_global_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + tag_arr_peri_global_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + tag_arr_peri_global_tech_type = 2; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + if (!strncmp("-design", line, strlen("-design"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_wt), + &(dynamic_power_wt), &(leakage_power_wt), &(cycle_time_wt), + &(area_wt)); + continue; + } + + if (!strncmp("-deviate", line, strlen("-deviate"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_dev), + &(dynamic_power_dev), &(leakage_power_dev), &(cycle_time_dev), + &(area_dev)); + continue; + } + + if (!strncmp("-Optimize", line, strlen("-Optimize"))) { + sscanf(line, "-Optimize %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("ED^2", temp_var, strlen("ED^2"))) { + ed = 2; + } + else if (!strncmp("ED", temp_var, strlen("ED"))) { + ed = 1; + } + else { + ed = 0; + } + } + + if (!strncmp("-NUCAdesign", line, strlen("-NUCAdesign"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_wt_nuca), + &(dynamic_power_wt_nuca), &(leakage_power_wt_nuca), + &(cycle_time_wt_nuca), &(area_wt_nuca)); + continue; + } + + if (!strncmp("-NUCAdeviate", line, strlen("-NUCAdeviate"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_dev_nuca), + &(dynamic_power_dev_nuca), &(leakage_power_dev_nuca), + &(cycle_time_dev_nuca), &(area_dev_nuca)); + continue; + } + + if (!strncmp("-Cache model", line, strlen("-cache model"))) { + sscanf(line, "-Cache model %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("UCA", temp_var, strlen("UCA"))) { + nuca = 0; + } + else { + nuca = 1; + } + continue; + } + + if (!strncmp("-NUCA bank", line, strlen("-NUCA bank"))) { + sscanf(line, "-NUCA bank count %d", &(nuca_bank_count)); + + if (nuca_bank_count != 0) { + force_nuca_bank = 1; + } + continue; + } + + if (!strncmp("-Wire inside mat", line, strlen("-Wire inside mat"))) { + sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("global", temp_var, strlen("global"))) { + wire_is_mat_type = 2; + continue; + } + else if (!strncmp("local", temp_var, strlen("local"))) { + wire_is_mat_type = 0; + continue; + } + else { + wire_is_mat_type = 1; + continue; + } + } + + if (!strncmp("-Wire outside mat", line, strlen("-Wire outside mat"))) { + sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("global", temp_var, strlen("global"))) { + wire_os_mat_type = 2; + } + else { + wire_os_mat_type = 1; + } + continue; + } + + if (!strncmp("-Interconnect projection", line, + strlen("-Interconnect projection"))) { + sscanf(line, "-Interconnect projection%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("aggressive", temp_var, strlen("aggressive"))) { + ic_proj_type = 0; + } + else { + ic_proj_type = 1; + } + continue; + } + + if (!strncmp("-Wire signalling", line, strlen("-wire signalling"))) { + sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("default", temp_var, strlen("default"))) { + force_wiretype = 0; + wt = Global; + } + else if (!(strncmp("Global_10", temp_var, strlen("Global_10")))) { + force_wiretype = 1; + wt = Global_10; + } + else if (!(strncmp("Global_20", temp_var, strlen("Global_20")))) { + force_wiretype = 1; + wt = Global_20; + } + else if (!(strncmp("Global_30", temp_var, strlen("Global_30")))) { + force_wiretype = 1; + wt = Global_30; + } + else if (!(strncmp("Global_5", temp_var, strlen("Global_5")))) { + force_wiretype = 1; + wt = Global_5; + } + else if (!(strncmp("Global", temp_var, strlen("Global")))) { + force_wiretype = 1; + wt = Global; + } + else { + wt = Low_swing; + force_wiretype = 1; + } + continue; + } + + if (!strncmp("-Core", line, strlen("-Core"))) { + sscanf(line, "-Core count %d\n", &(cores)); + if (cores > 16) { + printf("No. of cores should be less than 16!\n"); + } + continue; + } + + if (!strncmp("-Cache level", line, strlen("-Cache level"))) { + sscanf(line, "-Cache l%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("L2", temp_var, strlen("L2"))) { + cache_level = 0; + } + else { + cache_level = 1; + } + } + + if (!strncmp("-Print level", line, strlen("-Print level"))) { + sscanf(line, "-Print l%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("DETAILED", temp_var, strlen("DETAILED"))) { + print_detail = 1; + } + else { + print_detail = 0; + } + } + if (!strncmp("-Add ECC", line, strlen("-Add ECC"))) { + sscanf(line, "-Add ECC %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + add_ecc_b_ = true; + } + else { + add_ecc_b_ = false; + } + } + + if (!strncmp("-CLDriver vertical", line, strlen("-CLDriver vertical"))) { + sscanf(line, "-CLDriver vertical %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + cl_vertical = true; + } + else { + cl_vertical = false; + } + } + + if (!strncmp("-Array Power Gating", line, strlen("-Array Power Gating"))) { + sscanf(line, "-Array Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + array_power_gated = true; + } + else { + array_power_gated = false; + } + } + + if (!strncmp("-Bitline floating", line, strlen("-Bitline floating"))) { + sscanf(line, "-Bitline floating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + bitline_floating = true; + } + else { + bitline_floating = false; + } + } + + if (!strncmp("-WL Power Gating", line, strlen("-WL Power Gating"))) { + sscanf(line, "-WL Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + wl_power_gated = true; + } + else { + wl_power_gated = false; + } + } + + if (!strncmp("-CL Power Gating", line, strlen("-CL Power Gating"))) { + sscanf(line, "-CL Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + cl_power_gated = true; + } + else { + cl_power_gated = false; + } + } + + if (!strncmp("-Interconnect Power Gating", line, + strlen("-Interconnect Power Gating"))) { + sscanf(line, "-Interconnect Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + interconect_power_gated = true; + } + else { + interconect_power_gated = false; + } + } + + if (!strncmp("-Power Gating Performance Loss", line, + strlen("-Power Gating Performance Loss"))) { + sscanf(line, "-Power Gating Performance Loss %lf", &(perfloss)); + continue; + } + + if (!strncmp("-Power Gating", line, strlen("-Power Gating"))) { + sscanf(line, "-Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + power_gating = true; + } + else { + power_gating = false; + } + } + + if (!strncmp("-Long channel devices", line, + strlen("-Long channel devices"))) { + sscanf(line, "-Long channel devices %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + long_channel_device = true; + } + else { + long_channel_device = false; + } + } + + if (!strncmp("-Print input parameters", line, + strlen("-Print input parameters"))) { + sscanf(line, "-Print input %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + print_input_args = true; + } + else { + print_input_args = false; + } + } + + if (!strncmp("-Force cache config", line, strlen("-Force cache config"))) { + sscanf(line, "-Force cache %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + force_cache_config = true; + } + else { + force_cache_config = false; + } + } + + if (!strncmp("-Ndbl", line, strlen("-Ndbl"))) { + sscanf(line, "-Ndbl %d\n", &(ndbl)); + continue; + } + if (!strncmp("-Ndwl", line, strlen("-Ndwl"))) { + sscanf(line, "-Ndwl %d\n", &(ndwl)); + continue; + } + if (!strncmp("-Nspd", line, strlen("-Nspd"))) { + sscanf(line, "-Nspd %d\n", &(nspd)); + continue; + } + if (!strncmp("-Ndsam1", line, strlen("-Ndsam1"))) { + sscanf(line, "-Ndsam1 %d\n", &(ndsam1)); + continue; + } + if (!strncmp("-Ndsam2", line, strlen("-Ndsam2"))) { + sscanf(line, "-Ndsam2 %d\n", &(ndsam2)); + continue; + } + if (!strncmp("-Ndcm", line, strlen("-Ndcm"))) { + sscanf(line, "-Ndcm %d\n", &(ndcm)); + continue; + } + } + rpters_in_htree = true; + fclose(fp); +} + +void InputParameter::display_ip() { + cout << "Cache size : " << cache_sz << endl; + cout << "Block size : " << line_sz << endl; + cout << "Associativity : " << assoc << endl; + cout << "Read only ports : " << num_rd_ports << endl; + cout << "Write only ports : " << num_wr_ports << endl; + cout << "Read write ports : " << num_rw_ports << endl; + cout << "Single ended read ports : " << num_se_rd_ports << endl; + if (fully_assoc || pure_cam) { + cout << "Search ports : " << num_search_ports << endl; + } + cout << "Cache banks (UCA) : " << nbanks << endl; + cout << "Technology : " << F_sz_um << endl; + cout << "User specified HP Vdd (v)? : " << std::boolalpha + << specific_hp_vdd << endl; + if (specific_hp_vdd) { + cout << "User defined HP Vdd (v) : " << hp_Vdd << endl; + } + cout << "User specified LSTP Vdd (v)? : " << std::boolalpha + << specific_lstp_vdd << endl; + if (specific_lstp_vdd) { + cout << "User defined HP Vdd (v) : " << lstp_Vdd << endl; + } + cout << "User specified LOP Vdd (v)? : " << std::boolalpha + << specific_lop_vdd << endl; + if (specific_lop_vdd) { + cout << "User defined HP Vdd (v) : " << lop_Vdd << endl; + } + cout << "Temperature : " << temp << endl; + cout << "Tag size : " << tag_w << endl; + if (is_cache) { + cout << "array type : " + << "Cache" << endl; + } + if (pure_ram) { + cout << "array type : " + << "Scratch RAM" << endl; + } + if (pure_cam) { + cout << "array type : " + << "CAM" << endl; + } + cout << "Model as memory : " << is_main_mem << endl; + cout << "Access mode : " << access_mode << endl; + cout << "Data array cell type : " << data_arr_ram_cell_tech_type + << endl; + cout << "Data array peripheral type : " << data_arr_peri_global_tech_type + << endl; + cout << "Tag array cell type : " << tag_arr_ram_cell_tech_type + << endl; + cout << "Tag array peripheral type : " << tag_arr_peri_global_tech_type + << endl; + cout << "Optimization target : " << ed << endl; + cout << "Design objective (UCA wt) : " << delay_wt << " " + << dynamic_power_wt << " " << leakage_power_wt << " " << cycle_time_wt + << " " << area_wt << endl; + cout << "Design objective (UCA dev) : " << delay_dev << " " + << dynamic_power_dev << " " << leakage_power_dev << " " << cycle_time_dev + << " " << area_dev << endl; + if (nuca) { + cout << "Cores : " << cores << endl; + + cout << "Design objective (NUCA wt) : " << delay_wt_nuca << " " + << dynamic_power_wt_nuca << " " << leakage_power_wt_nuca << " " + << cycle_time_wt_nuca << " " << area_wt_nuca << endl; + cout << "Design objective (NUCA dev) : " << delay_dev_nuca << " " + << dynamic_power_dev_nuca << " " << leakage_power_dev_nuca << " " + << cycle_time_dev_nuca << " " << area_dev_nuca << endl; + } + cout << "Cache model : " << nuca << endl; + cout << "Nuca bank : " << nuca_bank_count << endl; + cout << "Wire inside mat : " << wire_is_mat_type << endl; + cout << "Wire outside mat : " << wire_os_mat_type << endl; + cout << "Interconnect projection : " << ic_proj_type << endl; + cout << "Wire signalling : " << force_wiretype << endl; + cout << "Print level : " << print_detail << endl; + cout << "ECC overhead : " << add_ecc_b_ << endl; + cout << "Page size : " << page_sz_bits << endl; + cout << "Burst length : " << burst_len << endl; + cout << "Internal prefetch width : " << int_prefetch_w << endl; + cout << "Force cache config : " << g_ip->force_cache_config + << endl; + if (g_ip->force_cache_config) { + cout << "Ndwl : " << g_ip->ndwl << endl; + cout << "Ndbl : " << g_ip->ndbl << endl; + cout << "Nspd : " << g_ip->nspd << endl; + cout << "Ndcm : " << g_ip->ndcm << endl; + cout << "Ndsam1 : " << g_ip->ndsam1 << endl; + cout << "Ndsam2 : " << g_ip->ndsam2 << endl; + } + // cout << "Placing subarray out driver vertical? : " << g_ip->cl_vertical + // << endl; +} + +powerComponents operator+(const powerComponents &x, const powerComponents &y) { + powerComponents z; + + z.dynamic = x.dynamic + y.dynamic; + z.leakage = x.leakage + y.leakage; + z.gate_leakage = x.gate_leakage + y.gate_leakage; + z.short_circuit = x.short_circuit + y.short_circuit; + z.longer_channel_leakage = + x.longer_channel_leakage + y.longer_channel_leakage; + z.power_gated_leakage = x.power_gated_leakage + y.power_gated_leakage; + z.power_gated_with_long_channel_leakage = + x.power_gated_with_long_channel_leakage + + y.power_gated_with_long_channel_leakage; + + return z; +} + +powerComponents operator*(const powerComponents &x, double const *const y) { + powerComponents z; + + z.dynamic = x.dynamic * y[0]; + z.leakage = x.leakage * y[1]; + z.gate_leakage = x.gate_leakage * y[2]; + z.short_circuit = x.short_circuit * y[3]; + z.longer_channel_leakage = + x.longer_channel_leakage * + y[1]; // longer channel leakage has the same behavior as normal leakage + z.power_gated_leakage = + x.power_gated_leakage * + y[1]; // power_gated_leakage has the same behavior as normal leakage + z.power_gated_with_long_channel_leakage = + x.power_gated_with_long_channel_leakage * + y[1]; // power_gated_with_long_channel_leakage has the same behavior as + // normal leakage + return z; +} + +powerDef operator+(const powerDef &x, const powerDef &y) { + powerDef z; + + z.readOp = x.readOp + y.readOp; + z.writeOp = x.writeOp + y.writeOp; + z.searchOp = x.searchOp + y.searchOp; + return z; +} + +powerDef operator*(const powerDef &x, double const *const y) { + powerDef z; + + z.readOp = x.readOp * y; + z.writeOp = x.writeOp * y; + z.searchOp = x.searchOp * y; + return z; +} + +uca_org_t cacti_interface(const string &infile_name) { + uca_org_t fin_res; + // uca_org_t result; + fin_res.valid = false; + + g_ip = new InputParameter(); + g_ip->parse_cfg(infile_name); + if (!g_ip->error_checking()) + exit(0); + if (g_ip->print_input_args) + g_ip->display_ip(); + + init_tech_params(g_ip->F_sz_um, false); // this init is for initializing + // wires + Wire winit; // Do not delete this line. It initializes wires. + // g_tp.peri_global.display(); + // g_tp.sram_cell.display(); + + // For HighRadix Only + // //// Wire wirea(g_ip->wt, 1000); + // //// wirea.print_wire(); + // //// cout << "Wire Area " << wirea.area.get_area() << " sq. u" << endl; + // // winit.print_wire(); + // // + // HighRadix *hr; + // hr = new HighRadix(); + // hr->compute_power(); + // hr->print_router(); + // exit(0); + // + // double sub_switch_sz = 2; + // double rows = 32; + // for (int i=0; i<6; i++) { + // sub_switch_sz = pow(2, i); + // rows = 64/sub_switch_sz; + // hr = new HighRadix(sub_switch_sz, rows, .8/* freq */, 64, 2, 64, 0.7); + // hr->compute_power(); + // hr->print_router(); + // delete hr; + // } + // // HighRadix yarc; + // // yarc.compute_power(); + // // yarc.print_router(); + // winit.print_wire(); + // exit(0); + // For HighRadix Only End + + if (g_ip->nuca == 1) { + Nuca n(&g_tp.peri_global); + n.sim_nuca(); + } + + // g_ip->display_ip(); + + solve(&fin_res); + // output_UCA(&fin_res); + // Wire::print_wire(); + output_data_csv(fin_res); + + if (!g_ip->dvs_voltage.empty()) { + update_dvs(&fin_res); + } + if (g_ip->power_gating) { + update_pg(&fin_res); // this is needed for compute area overhead of + // power-gating, even the gated power is calculated + // together un-gated leakage + } + output_UCA(&fin_res); + + Wire wprint; // reset wires to original configuration as in *.cfg file (dvs + // level 0) + Wire::print_wire(); + + delete (g_ip); + return fin_res; +} + +// cacti6.5's plain interface, please keep !!! +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, int excl_write_ports, int single_ended_read_ports, + int banks, + double tech_node, // in nm + int page_sz, int burst_length, int pre_width, int output_width, + int specific_tag, int tag_width, + int access_mode, // 0 normal, 1 seq, 2 fast + int cache, // scratch ram or cache + int main_mem, int obj_func_delay, int obj_func_dynamic_power, + int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, + int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, + int dev_func_area, int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, // 0-4 + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, // 0 - aggressive, 1 - normal + int wire_inside_mat_type_in, int wire_outside_mat_type_in, + int is_nuca, // 0 - UCA, 1 - NUCA + int core_count, + int cache_level, // 0 - L2, 1 - L3 + int nuca_bank_count, int nuca_obj_func_delay, + int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, + int nuca_obj_func_area, int nuca_obj_func_cycle_time, + int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, + int nuca_dev_func_leakage_power, int nuca_dev_func_area, + int nuca_dev_func_cycle_time, + int REPEATERS_IN_HTREE_SEGMENTS_in, // TODO for now only wires with + // repeaters are supported + int p_input) { + g_ip = new InputParameter(); + g_ip->add_ecc_b_ = true; + + g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in; + g_ip->tag_arr_ram_cell_tech_type = tag_arr_ram_cell_tech_flavor_in; + g_ip->tag_arr_peri_global_tech_type = tag_arr_peri_global_tech_flavor_in; + + g_ip->ic_proj_type = interconnect_projection_type_in; + g_ip->wire_is_mat_type = wire_inside_mat_type_in; + g_ip->wire_os_mat_type = wire_outside_mat_type_in; + g_ip->burst_len = burst_length; + g_ip->int_prefetch_w = pre_width; + g_ip->page_sz_bits = page_sz; + + g_ip->cache_sz = cache_size; + g_ip->line_sz = line_size; + g_ip->assoc = associativity; + g_ip->nbanks = banks; + g_ip->out_w = output_width; + g_ip->specific_tag = specific_tag; + if (tag_width == 0) { + g_ip->tag_w = 42; + } + else { + g_ip->tag_w = tag_width; + } + + g_ip->access_mode = access_mode; + g_ip->delay_wt = obj_func_delay; + g_ip->dynamic_power_wt = obj_func_dynamic_power; + g_ip->leakage_power_wt = obj_func_leakage_power; + g_ip->area_wt = obj_func_area; + g_ip->cycle_time_wt = obj_func_cycle_time; + g_ip->delay_dev = dev_func_delay; + g_ip->dynamic_power_dev = dev_func_dynamic_power; + g_ip->leakage_power_dev = dev_func_leakage_power; + g_ip->area_dev = dev_func_area; + g_ip->cycle_time_dev = dev_func_cycle_time; + g_ip->ed = ed_ed2_none; + + switch (wt) { + case (0): + g_ip->force_wiretype = 0; + g_ip->wt = Global; + break; + case (1): + g_ip->force_wiretype = 1; + g_ip->wt = Global; + break; + case (2): + g_ip->force_wiretype = 1; + g_ip->wt = Global_5; + break; + case (3): + g_ip->force_wiretype = 1; + g_ip->wt = Global_10; + break; + case (4): + g_ip->force_wiretype = 1; + g_ip->wt = Global_20; + break; + case (5): + g_ip->force_wiretype = 1; + g_ip->wt = Global_30; + break; + case (6): + g_ip->force_wiretype = 1; + g_ip->wt = Low_swing; + break; + default: + cout << "Unknown wire type!\n"; + exit(0); + } + + g_ip->delay_wt_nuca = nuca_obj_func_delay; + g_ip->dynamic_power_wt_nuca = nuca_obj_func_dynamic_power; + g_ip->leakage_power_wt_nuca = nuca_obj_func_leakage_power; + g_ip->area_wt_nuca = nuca_obj_func_area; + g_ip->cycle_time_wt_nuca = nuca_obj_func_cycle_time; + g_ip->delay_dev_nuca = dev_func_delay; + g_ip->dynamic_power_dev_nuca = nuca_dev_func_dynamic_power; + g_ip->leakage_power_dev_nuca = nuca_dev_func_leakage_power; + g_ip->area_dev_nuca = nuca_dev_func_area; + g_ip->cycle_time_dev_nuca = nuca_dev_func_cycle_time; + g_ip->nuca = is_nuca; + g_ip->nuca_bank_count = nuca_bank_count; + if (nuca_bank_count > 0) { + g_ip->force_nuca_bank = 1; + } + g_ip->cores = core_count; + g_ip->cache_level = cache_level; + + g_ip->temp = temp; + + g_ip->F_sz_nm = tech_node; + g_ip->F_sz_um = tech_node / 1000; + g_ip->is_main_mem = (main_mem != 0) ? true : false; + g_ip->is_cache = (cache != 0) ? true : false; + g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false; + + g_ip->num_rw_ports = rw_ports; + g_ip->num_rd_ports = excl_read_ports; + g_ip->num_wr_ports = excl_write_ports; + g_ip->num_se_rd_ports = single_ended_read_ports; + g_ip->print_detail = 1; + g_ip->nuca = 0; + + g_ip->wt = Global_5; + g_ip->force_cache_config = false; + g_ip->force_wiretype = false; + g_ip->print_input_args = p_input; + + uca_org_t fin_res; + fin_res.valid = false; + + if (g_ip->error_checking() == false) + exit(0); + if (g_ip->print_input_args) + g_ip->display_ip(); + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + + if (g_ip->nuca == 1) { + Nuca n(&g_tp.peri_global); + n.sim_nuca(); + } + solve(&fin_res); + + output_UCA(&fin_res); + + delete (g_ip); + return fin_res; +} + +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, // para5 + int excl_write_ports, int single_ended_read_ports, int search_ports, + int banks, + double tech_node, // para10 + int output_width, int specific_tag, int tag_width, int access_mode, + int cache, // para15 + int main_mem, int obj_func_delay, int obj_func_dynamic_power, + int obj_func_leakage_power, + int obj_func_cycle_time, // para20 + int obj_func_area, int dev_func_delay, int dev_func_dynamic_power, + int dev_func_leakage_power, + int dev_func_area, // para25 + int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, // para30 + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, + int wire_inside_mat_type_in, // para35 + int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, + int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, + int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, + int PAGE_SIZE_BITS_in, // para40 + int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, + int wiretype, + int force_config, // para45 + int ndwl, int ndbl, int nspd, int ndcm, + int ndsam1, // para50 + int ndsam2, int ecc) { + g_ip = new InputParameter(); + + uca_org_t fin_res; + fin_res.valid = false; + + g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in; + g_ip->tag_arr_ram_cell_tech_type = tag_arr_ram_cell_tech_flavor_in; + g_ip->tag_arr_peri_global_tech_type = tag_arr_peri_global_tech_flavor_in; + + g_ip->ic_proj_type = interconnect_projection_type_in; + g_ip->wire_is_mat_type = wire_inside_mat_type_in; + g_ip->wire_os_mat_type = wire_outside_mat_type_in; + g_ip->burst_len = BURST_LENGTH_in; + g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; + g_ip->page_sz_bits = PAGE_SIZE_BITS_in; + + g_ip->cache_sz = cache_size; + g_ip->line_sz = line_size; + g_ip->assoc = associativity; + g_ip->nbanks = banks; + g_ip->out_w = output_width; + g_ip->specific_tag = specific_tag; + if (specific_tag == 0) { + g_ip->tag_w = 42; + } + else { + g_ip->tag_w = tag_width; + } + + g_ip->access_mode = access_mode; + g_ip->delay_wt = obj_func_delay; + g_ip->dynamic_power_wt = obj_func_dynamic_power; + g_ip->leakage_power_wt = obj_func_leakage_power; + g_ip->area_wt = obj_func_area; + g_ip->cycle_time_wt = obj_func_cycle_time; + g_ip->delay_dev = dev_func_delay; + g_ip->dynamic_power_dev = dev_func_dynamic_power; + g_ip->leakage_power_dev = dev_func_leakage_power; + g_ip->area_dev = dev_func_area; + g_ip->cycle_time_dev = dev_func_cycle_time; + g_ip->temp = temp; + g_ip->ed = ed_ed2_none; + + g_ip->F_sz_nm = tech_node; + g_ip->F_sz_um = tech_node / 1000; + g_ip->is_main_mem = (main_mem != 0) ? true : false; + g_ip->is_cache = (cache == 1) ? true : false; + g_ip->pure_ram = (cache == 0) ? true : false; + g_ip->pure_cam = (cache == 2) ? true : false; + g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false; + g_ip->ver_htree_wires_over_array = VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; + g_ip->broadcast_addr_din_over_ver_htrees = + BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; + + g_ip->num_rw_ports = rw_ports; + g_ip->num_rd_ports = excl_read_ports; + g_ip->num_wr_ports = excl_write_ports; + g_ip->num_se_rd_ports = single_ended_read_ports; + g_ip->num_search_ports = search_ports; + + g_ip->print_detail = 1; + g_ip->nuca = 0; + + if (force_wiretype == 0) { + g_ip->wt = Global; + g_ip->force_wiretype = false; + } + else { + g_ip->force_wiretype = true; + if (wiretype == 10) { + g_ip->wt = Global_10; + } + if (wiretype == 20) { + g_ip->wt = Global_20; + } + if (wiretype == 30) { + g_ip->wt = Global_30; + } + if (wiretype == 5) { + g_ip->wt = Global_5; + } + if (wiretype == 0) { + g_ip->wt = Low_swing; + } + } + // g_ip->wt = Global_5; + if (force_config == 0) { + g_ip->force_cache_config = false; + } + else { + g_ip->force_cache_config = true; + g_ip->ndbl = ndbl; + g_ip->ndwl = ndwl; + g_ip->nspd = nspd; + g_ip->ndcm = ndcm; + g_ip->ndsam1 = ndsam1; + g_ip->ndsam2 = ndsam2; + } + + if (ecc == 0) { + g_ip->add_ecc_b_ = false; + } + else { + g_ip->add_ecc_b_ = true; + } + + if (!g_ip->error_checking()) + exit(0); + + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + + g_ip->display_ip(); + solve(&fin_res); + output_UCA(&fin_res); + output_data_csv(fin_res); + delete (g_ip); + + return fin_res; +} + +bool InputParameter::error_checking() { + int A; + bool seq_access = false; + fast_access = true; + fully_assoc = false; + + switch (access_mode) { + case 0: + seq_access = false; + fast_access = false; + break; + case 1: + seq_access = true; + fast_access = false; + break; + case 2: + seq_access = false; + fast_access = true; + break; + } + + if (is_main_mem) { + if (ic_proj_type == 0) { + cerr << "DRAM model supports only conservative interconnect " + "projection!\n\n"; + return false; + } + } + + uint32_t B = line_sz; + + if (B < 1) { + cerr << "Block size must >= 1" << endl; + return false; + } + else if (B * 8 < out_w) { + cerr << "Block size must be at least " << out_w / 8 << endl; + return false; + } + + if (F_sz_um <= 0) { + cerr << "Feature size must be > 0" << endl; + return false; + } + else if (F_sz_um > 0.181) { + cerr << "Feature size must be <= 180 nm" << endl; + return false; + } + else if (F_sz_um > 0.091 && (data_arr_ram_cell_tech_type != itrs_hp || + tag_arr_ram_cell_tech_type != itrs_hp || + data_arr_peri_global_tech_type != itrs_hp || + tag_arr_peri_global_tech_type != itrs_hp)) { + cerr << "Feature size from 90nm to 180 nm only support the ITRS HP device " + "type" + << endl; + return false; + } + + uint32_t RWP = num_rw_ports; + uint32_t ERP = num_rd_ports; + uint32_t EWP = num_wr_ports; + uint32_t NSER = num_se_rd_ports; + uint32_t SCHP = num_search_ports; + + // TODO: revisit this. This is an important feature. Sheng thought this should + // be used + // // If multiple banks and multiple ports are specified, then if number of + // ports is less than or equal to + // // the number of banks, we assume that the multiple ports are implemented + // via the multiple banks. + // // In such a case we assume that each bank has 1 RWP port. + // if ((RWP + ERP + EWP) <= nbanks && nbanks>1) + // { + // RWP = 1; + // ERP = 0; + // EWP = 0; + // NSER = 0; + // } + // else if ((RWP < 0) || (EWP < 0) || (ERP < 0)) + // { + // cerr << "Ports must >=0" << endl; + // return false; + // } + // else if (RWP > 2) + // { + // cerr << "Maximum of 2 read/write ports" << endl; + // return false; + // } + // else if ((RWP+ERP+EWP) < 1) + // Changed to new implementation: + // The number of ports specified at input is per bank + if ((RWP + ERP + EWP) < 1) { + cerr << "Must have at least one port" << endl; + return false; + } + + if (is_pow2(nbanks) == false) { + cerr << "Number of subbanks should be greater than or equal to 1 and " + "should be a power of 2" + << endl; + return false; + } + + int C = cache_sz / nbanks; + if (C < 64) { + cerr << "Cache size must >=64" << endl; + return false; + } + + // TODO: revisit this + // if (pure_ram==true && assoc!=1) + // { + // cerr << "Pure RAM must have assoc as 1" << endl; + // return false; + // } + + // fully assoc and cam check + if (is_cache && assoc == 0) + fully_assoc = true; + else + fully_assoc = false; + + if (pure_cam == true && assoc != 0) { + cerr << "Pure CAM must have associativity as 0" << endl; + return false; + } + + if (assoc == 0 && (pure_cam == false && is_cache == false)) { + cerr << "Only CAM or Fully associative cache can have associativity as 0" + << endl; + return false; + } + + if ((fully_assoc == true || pure_cam == true) && + (data_arr_ram_cell_tech_type != tag_arr_ram_cell_tech_type || + data_arr_peri_global_tech_type != tag_arr_peri_global_tech_type)) { + cerr << "CAM and fully associative cache must have same device type for " + "both data and tag array" + << endl; + return false; + } + + if ((fully_assoc == true || pure_cam == true) && + (data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram)) { + cerr << "DRAM based CAM and fully associative cache are not supported" + << endl; + return false; + } + + if ((fully_assoc == true || pure_cam == true) && (is_main_mem == true)) { + cerr << "CAM and fully associative cache cannot be as main memory" << endl; + return false; + } + + if ((fully_assoc || pure_cam) && SCHP < 1) { + cerr << "CAM and fully associative must have at least 1 search port" + << endl; + return false; + } + + if (RWP == 0 && ERP == 0 && SCHP > 0 && ((fully_assoc || pure_cam))) { + ERP = SCHP; + } + + // if ((!(fully_assoc || pure_cam)) && SCHP>=1) + // { + // cerr << "None CAM and fully associative cannot have search ports" << + // endl; return false; + // } + + if (assoc == 0) { + A = C / B; + // fully_assoc = true; + } + else { + if (assoc == 1) { + A = 1; + // fully_assoc = false; + } + else { + // fully_assoc = false; + A = assoc; + if (is_pow2(A) == false) { + cerr << "Associativity must be a power of 2" << endl; + return false; + } + } + } + + if (C / (B * A) <= 1 && assoc != 0) { + cerr << "Number of sets is too small: " << endl; + cerr << " Need to either increase cache size, or decrease associativity or " + "block size" + << endl; + cerr << " (or use fully associative cache)" << endl; + return false; + } + + block_sz = B; + + /*dt: testing sequential access mode*/ + if (seq_access) { + tag_assoc = A; + data_assoc = 1; + is_seq_acc = true; + } + else { + tag_assoc = A; + data_assoc = A; + is_seq_acc = false; + } + + if (assoc == 0) { + data_assoc = 1; + } + num_rw_ports = RWP; + num_rd_ports = ERP; + num_wr_ports = EWP; + num_se_rd_ports = NSER; + if (!(fully_assoc || pure_cam)) + num_search_ports = 0; + nsets = C / (B * A); + + if (temp < 300 || temp > 400 || temp % 10 != 0) { + cerr + << temp + << " Temperature must be between 300 and 400 Kelvin and multiple of 10." + << endl; + return false; + } + + if (nsets < 1) { + cerr << "Less than one set..." << endl; + return false; + } + + // power_gating = (array_power_gated + // || bitline_floating + // || wl_power_gated + // || cl_power_gated + // || interconect_power_gated)?true:false; + + if (power_gating) { + array_power_gated = true; + bitline_floating = true; + wl_power_gated = true; + cl_power_gated = true; + interconect_power_gated = true; + } + else { + array_power_gated = false; + bitline_floating = false; + wl_power_gated = false; + cl_power_gated = false; + interconect_power_gated = false; + } + + // if (power_gating && (!dvs_voltage.empty())) + // { + // cerr << "Power gating and DVS cannot be active simultaneously, please + // model them in two runs.\n\n"; return false; + // } + + if (power_gating && (pure_cam || fully_assoc)) { + cerr << "Power gating in CAM is not supported yet.\n\n" << endl; + return false; + } + + if (power_gating && (is_main_mem || data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram || + tag_arr_ram_cell_tech_type == lp_dram || + tag_arr_ram_cell_tech_type == comm_dram || + data_arr_peri_global_tech_type == lp_dram || + data_arr_peri_global_tech_type == comm_dram || + tag_arr_peri_global_tech_type == lp_dram || + tag_arr_peri_global_tech_type == comm_dram)) { + cerr << "Power gating in DRAM is not supported. \n\n" << endl; + return false; + } + + if (long_channel_device && + (is_main_mem || data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram || + tag_arr_ram_cell_tech_type == lp_dram || + tag_arr_ram_cell_tech_type == comm_dram || + data_arr_peri_global_tech_type == lp_dram || + data_arr_peri_global_tech_type == comm_dram || + tag_arr_peri_global_tech_type == lp_dram || + tag_arr_peri_global_tech_type == comm_dram)) { + cerr << "Long Channel Device in DRAM is not supported. \n\n" << endl; + return false; + } + + if ((!dvs_voltage.empty()) && + (is_main_mem || data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram || + tag_arr_ram_cell_tech_type == lp_dram || + tag_arr_ram_cell_tech_type == comm_dram || + data_arr_peri_global_tech_type == lp_dram || + data_arr_peri_global_tech_type == comm_dram || + tag_arr_peri_global_tech_type == lp_dram || + tag_arr_peri_global_tech_type == comm_dram)) { + cerr << "DVS in DRAM is not supported. \n\n" << endl; + return false; + } + + // if (power_gating && (specific_hp_vdd + // || specific_lstp_vdd + // || specific_lop_vdd)) + // { + // cerr << "Default Vdd is recommended when enabling power gating.\n\n"<< + // endl; return false; + // } + + if ((!dvs_voltage.empty()) && + ((data_arr_ram_cell_tech_type != data_arr_peri_global_tech_type) || + (tag_arr_peri_global_tech_type != tag_arr_ram_cell_tech_type) || + (data_arr_ram_cell_tech_type != tag_arr_ram_cell_tech_type))) { + cerr << "Same device types is recommended for tag/data/cell/peripheral for " + "DVS. Same DVS voltage will be applied to different device " + "types\n\n"; + return false; + } + + return true; +} + +void output_data_csv(const uca_org_t &fin_res) { + // TODO: the csv output should remain + fstream file("out.csv", ios::in); + bool print_index = file.fail(); + file.close(); + + file.open("out.csv", ios::out | ios::app); + if (file.fail() == true) { + cerr << "File out.csv could not be opened successfully" << endl; + } + else { + if (print_index == true) { + file << "Tech node (nm), "; + file << "Capacity (bytes), "; + file << "Number of banks, "; + file << "Associativity, "; + file << "Output width (bits), "; + file << "Access time (ns), "; + file << "Random cycle time (ns), "; + // file << "Multisubbank interleave cycle time (ns), "; + + // file << "Delay request network (ns), "; + // file << "Delay inside mat (ns), "; + // file << "Delay reply network (ns), "; + // file << "Tag array access time (ns), "; + // file << "Data array access time (ns), "; + // file << "Refresh period (microsec), "; + // file << "DRAM array availability (%), "; + file << "Dynamic search energy (nJ), "; + file << "Dynamic read energy (nJ), "; + file << "Dynamic write energy (nJ), "; + // file << "Tag Dynamic read energy (nJ), "; + // file << "Data Dynamic read energy (nJ), "; + // file << "Dynamic read power (mW), "; + file << "Standby leakage per bank(mW), "; + // file << "Leakage per bank with leak power management (mW), "; + // file << "Leakage per bank with leak power management (mW), "; + // file << "Refresh power as percentage of standby leakage, "; + file << "Area (mm2), "; + file << "Ndwl, "; + file << "Ndbl, "; + file << "Nspd, "; + file << "Ndcm, "; + file << "Ndsam_level_1, "; + file << "Ndsam_level_2, "; + file << "Data arrary area efficiency %, "; + file << "Ntwl, "; + file << "Ntbl, "; + file << "Ntspd, "; + file << "Ntcm, "; + file << "Ntsam_level_1, "; + file << "Ntsam_level_2, "; + file << "Tag arrary area efficiency %, "; + + // file << "Resistance per unit micron (ohm-micron), "; + // file << "Capacitance per unit micron (fF per micron), "; + // file << "Unit-length wire delay (ps), "; + // file << "FO4 delay (ps), "; + // file << "delay route to bank (including crossb delay) (ps), "; + // file << "Crossbar delay (ps), "; + // file << "Dyn read energy per access from closed page (nJ), "; + // file << "Dyn read energy per access from open page (nJ), "; + // file << "Leak power of an subbank with page closed (mW), "; + // file << "Leak power of a subbank with page open (mW), "; + // file << "Leak power of request and reply networks (mW), "; + // file << "Number of subbanks, "; + // file << "Page size in bits, "; + // file << "Activate power, "; + // file << "Read power, "; + // file << "Write power, "; + // file << "Precharge power, "; + // file << "tRCD, "; + // file << "CAS latency, "; + // file << "Precharge delay, "; + // file << "Perc dyn energy bitlines, "; + // file << "perc dyn energy wordlines, "; + // file << "perc dyn energy outside mat, "; + // file << "Area opt (perc), "; + // file << "Delay opt (perc), "; + // file << "Repeater opt (perc), "; + // file << "Aspect ratio"; + file << endl; + } + file << g_ip->F_sz_nm << ", "; + file << g_ip->cache_sz << ", "; + file << g_ip->nbanks << ", "; + file << g_ip->tag_assoc << ", "; + file << g_ip->out_w << ", "; + file << fin_res.access_time * 1e+9 << ", "; + file << fin_res.cycle_time * 1e+9 << ", "; + // file << fin_res.data_array2->multisubbank_interleave_cycle_time*1e+9 + // << ", "; file << fin_res.data_array2->delay_request_network*1e+9 << ", + // "; file << fin_res.data_array2->delay_inside_mat*1e+9 << ", "; file + // << fin_res.data_array2.delay_reply_network*1e+9 << ", "; + + // if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) + // { + // file << fin_res.tag_array2->access_time*1e+9 << ", "; + // } + // else + // { + // file << 0 << ", "; + // } + // file << fin_res.data_array2->access_time*1e+9 << ", "; + // file << fin_res.data_array2->dram_refresh_period*1e+6 << ", "; + // file << fin_res.data_array2->dram_array_availability << ", "; + if (g_ip->fully_assoc || g_ip->pure_cam) { + file << fin_res.power.searchOp.dynamic * 1e+9 << ", "; + } + else { + file << "N/A" + << ", "; + } + file << fin_res.power.readOp.dynamic * 1e+9 << ", "; + file << fin_res.power.writeOp.dynamic * 1e+9 << ", "; + // if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) + // { + // file << fin_res.tag_array2->power.readOp.dynamic*1e+9 << ", "; + // } + // else + // { + // file << "NA" << ", "; + // } + // file << fin_res.data_array2->power.readOp.dynamic*1e+9 << ", "; + // if (g_ip->fully_assoc || g_ip->pure_cam) + // { + // file << + // fin_res.power.searchOp.dynamic*1000/fin_res.cycle_time << ", "; + // } + // else + // { + // file << fin_res.power.readOp.dynamic*1000/fin_res.cycle_time << + // ", "; + // } + + file << (fin_res.power.readOp.leakage + fin_res.power.readOp.gate_leakage) * + 1000 + << ", "; + // file << fin_res.leak_power_with_sleep_transistors_in_mats*1000 << ", + // "; file << fin_res.data_array.refresh_power / + // fin_res.data_array.total_power.readOp.leakage << ", "; + file << fin_res.area * 1e-6 << ", "; + + file << fin_res.data_array2->Ndwl << ", "; + file << fin_res.data_array2->Ndbl << ", "; + file << fin_res.data_array2->Nspd << ", "; + file << fin_res.data_array2->deg_bl_muxing << ", "; + file << fin_res.data_array2->Ndsam_lev_1 << ", "; + file << fin_res.data_array2->Ndsam_lev_2 << ", "; + file << fin_res.data_array2->area_efficiency << ", "; + if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) { + file << fin_res.tag_array2->Ndwl << ", "; + file << fin_res.tag_array2->Ndbl << ", "; + file << fin_res.tag_array2->Nspd << ", "; + file << fin_res.tag_array2->deg_bl_muxing << ", "; + file << fin_res.tag_array2->Ndsam_lev_1 << ", "; + file << fin_res.tag_array2->Ndsam_lev_2 << ", "; + file << fin_res.tag_array2->area_efficiency << ", "; + } + else { + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + } + + // file << g_tp.wire_inside_mat.R_per_um << ", "; + // file << g_tp.wire_inside_mat.C_per_um / 1e-15 << ", "; + // file << g_tp.unit_len_wire_del / 1e-12 << ", "; + // file << g_tp.FO4 / 1e-12 << ", "; + // file << fin_res.data_array.delay_route_to_bank / 1e-9 << ", "; + // file << fin_res.data_array.delay_crossbar / 1e-9 << ", "; + // file << fin_res.data_array.dyn_read_energy_from_closed_page / 1e-9 << + // ", "; file << fin_res.data_array.dyn_read_energy_from_open_page / 1e-9 + // << ", "; file << fin_res.data_array.leak_power_subbank_closed_page / + // 1e-3 << ", "; file << fin_res.data_array.leak_power_subbank_open_page + // / 1e-3 << ", "; file << + // fin_res.data_array.leak_power_request_and_reply_networks / 1e-3 << ", + // "; file << fin_res.data_array.number_subbanks << ", " ; file << + // fin_res.data_array.page_size_in_bits << ", " ; file << + // fin_res.data_array.activate_energy * 1e9 << ", " ; file << + // fin_res.data_array.read_energy * 1e9 << ", " ; file << + // fin_res.data_array.write_energy * 1e9 << ", " ; file << + // fin_res.data_array.precharge_energy * 1e9 << ", " ; file << + // fin_res.data_array.trcd * 1e9 << ", " ; file << + // fin_res.data_array.cas_latency * 1e9 << ", " ; file << + // fin_res.data_array.precharge_delay * 1e9 << ", " ; file << + // fin_res.data_array.all_banks_height / + // fin_res.data_array.all_banks_width; + file << endl; + } + file.close(); +} + +void output_UCA(uca_org_t *fr) { + double long_channel_leakage_reduction = + 0.1 + + 0.9 * (0.8 * fr->data_array2->long_channel_leakage_reduction_memcell + + 0.2 * fr->data_array2 + ->long_channel_leakage_reduction_periperal); // TODO + double areaoverhead, overhead_data, overhead_tag; + double wakeup_E, wakeup_T, wakeup_E_data, wakeup_T_data = 0., wakeup_E_tag, + wakeup_T_tag = 0.; + int dvs_levels = g_ip->dvs_voltage.size(); + int i; + bool dvs = !g_ip->dvs_voltage.empty(); + // if (NUCA) + if (0) { + cout << "\n\n Detailed Bank Stats:\n"; + cout << " Bank Size (bytes): %d\n" << (int)(g_ip->cache_sz); + } + else { + if (g_ip->data_arr_ram_cell_tech_type == 3) { + cout << "\n---------- CACTI-P, with new features: " << VER_COMMENT_CACTI + << " of " << VER_UPDATE_CACTI << "), Uniform Cache Access " + << "Logic Process Based DRAM Model ----------\n"; + } + else if (g_ip->data_arr_ram_cell_tech_type == 4) { + cout << "\n---------- CACTI-P, with new features: " << VER_COMMENT_CACTI + << " of " << VER_UPDATE_CACTI << "), Uniform" + << "Cache Access Commodity DRAM Model ----------\n"; + } + else { + cout << "\n---------- CACTI-P, with new features: " << VER_COMMENT_CACTI + << " of " << VER_UPDATE_CACTI + << "), Uniform Cache Access " + "SRAM Model ----------\n"; + } + // (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<< + // VER_postfix_CACTI<<"; (version "<< VER_MAJOR_CACTI <<"."<< + // VER_MINOR_CACTI<<"."VER_COMMENT_CACTI << VER_postfix_CACTI + // << " of + // " + // << VER_UPDATE_CACTI << ") + cout << "\nCache Parameters:\n"; + cout << " Total cache size (bytes): " << (int)(g_ip->cache_sz) << endl; + } + + cout << " Number of banks: " << (int)g_ip->nbanks << endl; + if (g_ip->fully_assoc || g_ip->pure_cam) + cout << " Associativity: fully associative\n"; + else { + if (g_ip->tag_assoc == 1) + cout << " Associativity: direct mapped\n"; + else + cout << " Associativity: " << g_ip->tag_assoc << endl; + } + + cout << " Block size (bytes): " << g_ip->line_sz << endl; + cout << " Read/write Ports: " << g_ip->num_rw_ports << endl; + cout << " Read ports: " << g_ip->num_rd_ports << endl; + cout << " Write ports: " << g_ip->num_wr_ports << endl; + if (g_ip->fully_assoc || g_ip->pure_cam) + cout << " search ports: " << g_ip->num_search_ports << endl; + cout << " Technology size (nm): " << g_ip->F_sz_nm << endl << endl; + + cout << " Access time (ns): " << fr->access_time * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->access_time * 1e9 << " (@DVS_Level" << i + 1 + << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + + cout << " Cycle time (ns): " << fr->cycle_time * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->cycle_time * 1e9 << " (@DVS_Level" << i + 1 + << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + if (g_ip->data_arr_ram_cell_tech_type >= 4) { + cout << " Precharge Delay (ns): " + << fr->data_array2->precharge_delay * 1e9 << endl; + cout << " Activate Energy (nJ): " + << fr->data_array2->activate_energy * 1e9 << endl; + cout << " Read Energy (nJ): " << fr->data_array2->read_energy * 1e9 + << endl; + cout << " Write Energy (nJ): " << fr->data_array2->write_energy * 1e9 + << endl; + cout << " Precharge Energy (nJ): " + << fr->data_array2->precharge_energy * 1e9 << endl; + cout << " Leakage Power Closed Page (mW): " + << fr->data_array2->leak_power_subbank_closed_page * 1e3 << endl; + cout << " Leakage Power Open Page (mW): " + << fr->data_array2->leak_power_subbank_open_page * 1e3 << endl; + cout << " Leakage Power I/O (mW): " + << fr->data_array2->leak_power_request_and_reply_networks * 1e3 + << endl; + cout << " Refresh power (mW): " << fr->data_array2->refresh_power * 1e3 + << endl; + } + else { + if ((g_ip->fully_assoc || g_ip->pure_cam)) { + cout << " Total dynamic associative search energy per access (nJ): " + << fr->power.searchOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->power.searchOp.dynamic * 1e9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + // cout << " Total dynamic read energy per access + //(nJ): " << fr->power.readOp.dynamic*1e9 << endl; + // cout << " Total dynamic write energy per access + //(nJ): " << fr->power.writeOp.dynamic*1e9 << endl; + } + // else + // { + cout << " Total dynamic read energy per access (nJ): " + << fr->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->power.readOp.dynamic * 1e9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + cout << " Total dynamic write energy per access (nJ): " + << fr->power.writeOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->power.writeOp.dynamic * 1e9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + // } + if (g_ip->power_gating) { + cout << " Total leakage power of a bank, with power-gating "; + if (!g_ip->user_defined_vcc_underflow) { + cout << "(state retained)"; + } + else { + cout << "(non state retained)"; + } + + cout << ", including its network outside" // power gated with retaining + // memory content + " (mW): " + << (g_ip->long_channel_device + ? fr->power.readOp.power_gated_leakage * + long_channel_leakage_reduction + : fr->power.readOp.power_gated_leakage) * + 1e3 + << endl; + } + cout << " Total leakage power of a bank without power gating, including " + "its network outside" + " (mW): " + << (g_ip->long_channel_device + ? fr->power.readOp.leakage * long_channel_leakage_reduction + : fr->power.readOp.leakage) * + 1e3; + + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + if (g_ip->data_arr_ram_cell_tech_type == 3 || + g_ip->data_arr_ram_cell_tech_type == 4) { + } + cout << " Cache height x width (mm): " << fr->cache_ht * 1e-3 << " x " + << fr->cache_len * 1e-3 << endl; + cout << endl; + + if (g_ip->power_gating) { + /* Energy/Power stats */ + cout << " Power-gating results (The virtual power supply for gated " + "circuit can only retain the state of idle circuit, not for " + "operating the circuit):" + << endl; + /* Data array power-gating stats */ + if (g_ip->user_defined_vcc_underflow) { + cout << " Warning: user defined power gating voltage is too low to " + "retain state; Please understand the implications of deep sleep " + "state on non state retaining and cold start effects when waking " + "up the structure." + << endl; + } + else { + cout << " Power-gating results when retaining state" << endl; + } + areaoverhead = + (fr->cache_ht * fr->cache_len / fr->uca_pg_reference->cache_ht / + fr->uca_pg_reference->cache_len - + 1) * + 100; //% + cout << " \tPower gating circuits (sleep transistors) induced area " + "overhead: " + << areaoverhead << " % " << endl; + wakeup_E = wakeup_E_data = fr->data_array2->sram_sleep_wakeup_energy + + fr->data_array2->wl_sleep_wakeup_energy + + fr->data_array2->bl_floating_wakeup_energy; + wakeup_T = wakeup_T_data = + MAX(fr->data_array2->sram_sleep_wakeup_latency, + MAX(fr->data_array2->wl_sleep_wakeup_latency, + fr->data_array2->bl_floating_wakeup_latency)); + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + wakeup_E_tag = fr->tag_array2->sram_sleep_wakeup_energy + + fr->tag_array2->wl_sleep_wakeup_energy + + fr->tag_array2->bl_floating_wakeup_energy; + wakeup_T_tag = MAX(fr->tag_array2->sram_sleep_wakeup_latency, + MAX(fr->tag_array2->wl_sleep_wakeup_latency, + fr->tag_array2->bl_floating_wakeup_latency)); + + wakeup_E += wakeup_E_tag; + wakeup_T = MAX(wakeup_T_tag, wakeup_T_data); + } + cout << " \tPower gating Wakeup Latency (ns): " << wakeup_T * 1e9 + << endl; + cout << " \tPower gating Wakeup Energy (nJ): " << wakeup_E * 1e9 << endl; + } + cout << endl << endl; + cout << " Best Ndwl : " << fr->data_array2->Ndwl << endl; + cout << " Best Ndbl : " << fr->data_array2->Ndbl << endl; + cout << " Best Nspd : " << fr->data_array2->Nspd << endl; + cout << " Best Ndcm : " << fr->data_array2->deg_bl_muxing << endl; + cout << " Best Ndsam L1 : " << fr->data_array2->Ndsam_lev_1 << endl; + cout << " Best Ndsam L2 : " << fr->data_array2->Ndsam_lev_2 << endl + << endl; + + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << " Best Ntwl : " << fr->tag_array2->Ndwl << endl; + cout << " Best Ntbl : " << fr->tag_array2->Ndbl << endl; + cout << " Best Ntspd : " << fr->tag_array2->Nspd << endl; + cout << " Best Ntcm : " << fr->tag_array2->deg_bl_muxing << endl; + cout << " Best Ntsam L1 : " << fr->tag_array2->Ndsam_lev_1 << endl; + cout << " Best Ntsam L2 : " << fr->tag_array2->Ndsam_lev_2 << endl; + } + + switch (fr->data_array2->wt) { + case (0): + cout + << " Data array, H-tree wire type: Delay optimized global wires\n"; + break; + case (1): + cout << " Data array, H-tree wire type: Global wires with 5\% delay " + "penalty\n"; + break; + case (2): + cout << " Data array, H-tree wire type: Global wires with 10\% delay " + "penalty\n"; + break; + case (3): + cout << " Data array, H-tree wire type: Global wires with 20\% delay " + "penalty\n"; + break; + case (4): + cout << " Data array, H-tree wire type: Global wires with 30\% delay " + "penalty\n"; + break; + case (5): + cout << " Data array, wire type: Low swing wires\n"; + break; + default: + cout << "ERROR - Unknown wire type " << (int)fr->data_array2->wt << endl; + exit(0); + } + + if (!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) { + switch (fr->tag_array2->wt) { + case (0): + cout << " Tag array, H-tree wire type: Delay optimized global " + "wires\n"; + break; + case (1): + cout << " Tag array, H-tree wire type: Global wires with 5\% delay " + "penalty\n"; + break; + case (2): + cout << " Tag array, H-tree wire type: Global wires with 10\% delay " + "penalty\n"; + break; + case (3): + cout << " Tag array, H-tree wire type: Global wires with 20\% delay " + "penalty\n"; + break; + case (4): + cout << " Tag array, H-tree wire type: Global wires with 30\% delay " + "penalty\n"; + break; + case (5): + cout << " Tag array, wire type: Low swing wires\n"; + break; + default: + cout << "ERROR - Unknown wire type " << (int)fr->tag_array2->wt << endl; + exit(-1); + } + } + + if (g_ip->print_detail) { + // if(g_ip->fully_assoc) return; + if (0) { // detailed power-gating output + if (g_ip->power_gating) { + /* Energy/Power stats */ + cout << endl << endl << "Power-gating Components:" << endl << endl; + /* Data array power-gating stats */ + areaoverhead = fr->cache_ht * fr->cache_len / + fr->uca_pg_reference->cache_ht / + fr->uca_pg_reference->cache_len - + 1; + cout << " Power gating circuits (sleep transistors) induced area " + "overhead: " + << areaoverhead << " % " << endl; + wakeup_E = wakeup_E_data = fr->data_array2->sram_sleep_wakeup_energy + + fr->data_array2->wl_sleep_wakeup_energy + + fr->data_array2->bl_floating_wakeup_energy; + wakeup_T = wakeup_T_data = + MAX(fr->data_array2->sram_sleep_wakeup_latency, + MAX(fr->data_array2->wl_sleep_wakeup_latency, + fr->data_array2->bl_floating_wakeup_latency)); + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + wakeup_E_tag = fr->tag_array2->sram_sleep_wakeup_energy + + fr->tag_array2->wl_sleep_wakeup_energy + + fr->tag_array2->bl_floating_wakeup_energy; + wakeup_T_tag = MAX(fr->tag_array2->sram_sleep_wakeup_latency, + MAX(fr->tag_array2->wl_sleep_wakeup_latency, + fr->tag_array2->bl_floating_wakeup_latency)); + + wakeup_E += wakeup_E_tag; + wakeup_T = MAX(wakeup_T_tag, wakeup_T_data); + } + cout << " Power gating Wakeup Latency (ns): " << wakeup_T * 1e9 + << endl; + cout << " Power gating Wakeup Energy (nJ): " << wakeup_E * 1e9 + << endl; + + // extra power gating details + if (!(g_ip->pure_cam || g_ip->fully_assoc)) + cout << " Data array: " << endl; + else if (g_ip->pure_cam) + cout << " CAM array: " << endl; + else + cout << " Fully associative cache array: " << endl; + + cout << "\t Sub-array Sleep Tx size (um) - " + << fr->data_array2->sram_sleep_tx_width << endl; + + // cout << "\t Sub-array Sleep Tx total size (um) - " << + // fr->data_array2->sram_sleep_tx_width << endl; + + cout << "\t Sub-array Sleep Tx total area (mm^2) - " + << fr->data_array2->sram_sleep_tx_area * 1e-6 << endl; + + cout << "\t Sub-array wakeup time (ns) - " + << fr->data_array2->sram_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t Sub-array Tx energy (nJ) - " + << fr->data_array2->sram_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t WL Sleep Tx size (um) - " + << fr->data_array2->wl_sleep_tx_width << endl; + + // cout << "\t WL Sleep total Tx size (um) - " << + // fr->data_array2->wl_sleep_tx_width << endl; + + cout << "\t WL Sleep Tx total area (mm^2) - " + << fr->data_array2->wl_sleep_tx_area * 1e-6 << endl; + + cout << "\t WL wakeup time (ns) - " + << fr->data_array2->wl_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t WL Tx energy (nJ) - " + << fr->data_array2->wl_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t BL floating wakeup time (ns) - " + << fr->data_array2->bl_floating_wakeup_latency * 1e9 << endl; + + cout << "\t BL floating Tx energy (nJ) - " + << fr->data_array2->bl_floating_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + cout << endl; + + cout << "\t Active mats per access - " + << fr->data_array2->num_active_mats << endl; + cout << "\t Active subarrays per mat - " + << fr->data_array2->num_submarray_mats << endl; + cout << endl; + /* Tag array area stats */ + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << " Tag array: " << endl; + cout << "\t Sub-array Sleep Tx size (um) - " + << fr->tag_array2->sram_sleep_tx_width << endl; + + // cout << "\t Sub-array Sleep Tx total size (um) - " << + // fr->tag_array2->sram_sleep_tx_width << endl; + + cout << "\t Sub-array Sleep Tx total area (mm^2) - " + << fr->tag_array2->sram_sleep_tx_area * 1e-6 << endl; + + cout << "\t Sub-array wakeup time (ns) - " + << fr->tag_array2->sram_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t Sub-array Tx energy (nJ) - " + << fr->tag_array2->sram_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t WL Sleep Tx size (um) - " + << fr->tag_array2->wl_sleep_tx_width << endl; + + // cout << "\t WL Sleep total Tx size (um) - " << + // fr->tag_array2->wl_sleep_tx_width << endl; + + cout << "\t WL Sleep Tx total area (mm^2) - " + << fr->tag_array2->wl_sleep_tx_area * 1e-6 << endl; + + cout << "\t WL wakeup time (ns) - " + << fr->tag_array2->wl_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t WL Tx energy (nJ) - " + << fr->tag_array2->wl_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t BL floating wakeup time (ns) - " + << fr->tag_array2->bl_floating_wakeup_latency * 1e9 << endl; + + cout << "\t BL floating Tx energy (nJ) - " + << fr->tag_array2->bl_floating_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + + cout << "\t Active mats per access - " + << fr->tag_array2->num_active_mats << endl; + cout << "\t Active subarrays per mat - " + << fr->tag_array2->num_submarray_mats << endl; + cout << endl; + } + } + } + /* Delay stats */ + /* data array stats */ + cout << endl << "Time Components:" << endl << endl; + + cout << " Data side (with Output driver) (ns): " + << fr->data_array2->access_time / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->access_time / 1e-9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + + cout << "\tH-tree delay outside banks (ns): " + << fr->data_array2->delay_route_to_bank * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_route_to_bank * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree input delay (inside a bank) (ns): " + << fr->data_array2->delay_input_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_input_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (!(g_ip->pure_cam || g_ip->fully_assoc)) { + cout << "\tDecoder + wordline delay (ns): " + << fr->data_array2->delay_row_predecode_driver_and_block * 1e9 + + fr->data_array2->delay_row_decoder * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2 + ->delay_row_predecode_driver_and_block * + 1e9 + + fr->uca_q[i]->data_array2->delay_row_decoder * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + else { + cout << "\tCAM search delay (ns): " + << fr->data_array2->delay_matchlines * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_matchlines * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + cout << "\tBitline delay (ns): " << fr->data_array2->delay_bitlines / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_bitlines / 1e-9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense Amplifier delay (ns): " + << fr->data_array2->delay_sense_amp * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_sense_amp * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree output delay (inside a bank) (ns): " + << fr->data_array2->delay_subarray_output_driver * 1e9 + + fr->data_array2->delay_dout_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_subarray_output_driver * 1e9 + + fr->uca_q[i]->data_array2->delay_dout_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + if (g_ip->power_gating) { + cout << "\tPower gating wakeup time (ns) - " << wakeup_T_data * 1e9 + << endl; + } + + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + /* tag array stats */ + cout << endl + << " Tag side (with Output driver) (ns): " + << fr->tag_array2->access_time / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->access_time / 1e-9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + cout << "\tH-tree delay outside banks (ns): " + << fr->tag_array2->delay_route_to_bank * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_route_to_bank * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree input delay (inside a bank) (ns): " + << fr->tag_array2->delay_input_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_input_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder + wordline delay (ns): " + << fr->tag_array2->delay_row_predecode_driver_and_block * 1e9 + + fr->tag_array2->delay_row_decoder * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2 + ->delay_row_predecode_driver_and_block * + 1e9 + + fr->uca_q[i]->tag_array2->delay_row_decoder * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline delay (ns): " << fr->tag_array2->delay_bitlines / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_bitlines * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense Amplifier delay (ns): " + << fr->tag_array2->delay_sense_amp * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_sense_amp * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tComparator delay (ns): " + << fr->tag_array2->delay_comparator * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_comparator * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree output delay (inside a bank) (ns): " + << fr->tag_array2->delay_subarray_output_driver * 1e9 + + fr->tag_array2->delay_dout_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_subarray_output_driver * 1e9 + + fr->uca_q[i]->tag_array2->delay_dout_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + if (g_ip->power_gating) { + cout << "\tPower gating wakeup time (ns) - " << wakeup_T_tag * 1e9 + << endl; + } + } + + /* Energy/Power stats */ + cout << endl << endl << "Power Components:" << endl << endl; + + if (!(g_ip->pure_cam || g_ip->fully_assoc)) { + cout << " Data array: Total dynamic read energy/access (nJ): " + << fr->data_array2->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power of a bank, power gated "; + + if (!g_ip->user_defined_vcc_underflow) { + cout << "with "; + } + else { + cout << "without "; + } + cout << "retaining memory content, including its network outside (mW): " + << (g_ip->long_channel_device + ? fr->data_array2->power.readOp.power_gated_leakage * + long_channel_leakage_reduction + : fr->data_array2->power.readOp.power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power of a bank without power gating, including " + "its network outside (mW): " + << (g_ip->long_channel_device + ? fr->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->data_array2->power.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->data_array2->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + // } + + cout << "\tTotal energy in H-tree outside banks (that includes both " + "address and data transfer) (nJ): " + << (fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tInput H-tree inside bank Energy (nJ): " + << (fr->data_array2->power_addr_input_htree.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_addr_input_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tOutput Htree inside bank Energy (nJ): " + << fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_data_output_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder (nJ): " + << fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2->power_row_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_row_predecoder_blocks.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tWordline (nJ): " + << fr->data_array2->power_row_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_row_decoders.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline mux & associated drivers (nJ): " + << fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << (fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_decoders.readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amp mux & associated drivers (nJ): " + << fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp + .dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_1_decoders + .readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_2_decoders + .readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines precharge and equalization circuit (nJ): " + << fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_prechg_eq_drivers.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines (nJ): " + << fr->data_array2->power_bitlines.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_bitlines.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->data_array2->power_sense_amps.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_sense_amps.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSub-array output driver (nJ): " + << fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_output_drivers_at_subarray.readOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power in H-tree outside a bank when power " + "gated (that includes both " + "address and data network) ((mW)): " + << (g_ip->long_channel_device + ? fr->data_array2->power_routing_to_bank.readOp + .power_gated_leakage * + long_channel_leakage_reduction + : fr->data_array2->power_routing_to_bank.readOp + .power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power in H-tree outside a bank (that includes " + "both " + "address and data network) ((mW)): " + << (g_ip->long_channel_device + ? fr->data_array2->power_routing_to_bank.readOp.leakage * + long_channel_leakage_reduction + : fr->data_array2->power_routing_to_bank.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp + .leakage * + long_channel_leakage_reduction + : fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp + .leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + // } + // cout << "\tTotal leakage power in H-tree (that includes both " + // "address and data network) ((mW)): " << + // (fr->data_array2->power_addr_input_htree.readOp.leakage + // + fr->data_array2->power_data_output_htree.readOp.leakage + // + fr->data_array2->power_routing_to_bank.readOp.leakage) + // * 1e3 << endl; + + // cout << "\tTotal leakage power in cells (mW): " << + // (fr->data_array2->array_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in row logic(mW): " << + // (fr->data_array2->wl_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in column logic(mW): " << + // (fr->data_array2->cl_leakage) * 1e3 << endl; + // + // cout << "\tTotal gate leakage power in H-tree (that includes + // both " "address and data network) ((mW)): " << + // (fr->data_array2->power_addr_input_htree.readOp.gate_leakage + // + + // fr->data_array2->power_data_output_htree.readOp.gate_leakage + // + + // fr->data_array2->power_routing_to_bank.readOp.gate_leakage) + // * 1e3 << endl; + } + + if (g_ip->pure_cam || g_ip->fully_assoc) { + if (g_ip->pure_cam) + cout << " CAM array:" << endl; + // cout << " Total dynamic associative search + // energy/access (nJ): " << + // fr->data_array2->power.searchOp.dynamic * 1e9 << + // endl; + // cout << "\tTotal energy in H-tree (that includes both " + // "match key and data transfer) (nJ): " << + // (fr->data_array2->power_htree_in_search.searchOp.dynamic + // + + // fr->data_array2->power_htree_out_search.searchOp.dynamic + // + + // fr->data_array2->power_routing_to_bank.searchOp.dynamic) + // * 1e9 << endl; cout << "\tKeyword input and result + // output Htrees inside bank Energy (nJ): " << + // (fr->data_array2->power_htree_in_search.searchOp.dynamic + // + + // fr->data_array2->power_htree_out_search.searchOp.dynamic) + // * 1e9 << endl; cout << "\tSearchlines (nJ): " << + // fr->data_array2->power_searchline.searchOp.dynamic + // * 1e9 + + // fr->data_array2->power_searchline_precharge.searchOp.dynamic + // * 1e9 << endl; cout << "\tMatchlines (nJ): " << + // fr->data_array2->power_matchlines.searchOp.dynamic + // * 1e9 + + // fr->data_array2->power_matchline_precharge.searchOp.dynamic + // * 1e9 << endl; cout << "\tSub-array output driver + // (nJ): " << + // fr->data_array2->power_output_drivers_at_subarray.searchOp.dynamic + // * 1e9 << endl; + // + // + // cout <data_array2->power.readOp.dynamic * + // 1e9 << endl; + // cout << "\tTotal energy in H-tree (that includes both " + // "address and data transfer) (nJ): " << + // (fr->data_array2->power_addr_input_htree.readOp.dynamic + // + + // fr->data_array2->power_data_output_htree.readOp.dynamic + // + + // fr->data_array2->power_routing_to_bank.readOp.dynamic) + // * 1e9 << endl; cout << "\tOutput Htree inside bank + // Energy (nJ): " << + // fr->data_array2->power_data_output_htree.readOp.dynamic + // * 1e9 << endl; cout << "\tDecoder (nJ): " << + // fr->data_array2->power_row_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_row_predecoder_blocks.readOp.dynamic + // * 1e9 << endl; cout << "\tWordline (nJ): " << + // fr->data_array2->power_row_decoders.readOp.dynamic + // * 1e9 << endl; cout << "\tBitline mux & associated + // drivers (nJ): " << + // fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_bit_mux_decoders.readOp.dynamic + // * 1e9 << endl; cout << "\tSense amp mux & associated + // drivers (nJ): " << + // fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic + // * 1e9 << endl; cout << "\tBitlines (nJ): " << + // fr->data_array2->power_bitlines.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_prechg_eq_drivers.readOp.dynamic + // * 1e9<< endl; cout << "\tSense amplifier energy (nJ): + // " << + // fr->data_array2->power_sense_amps.readOp.dynamic + // * 1e9 << endl; cout << "\tSub-array output driver + // (nJ): " << + // fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic + // * 1e9 << endl; + // + // cout << endl <<" Total leakage power of a bank (mW): " + // << + // fr->data_array2->power.readOp.leakage * 1e3 << + // endl; + // } + // else + // { + if (g_ip->fully_assoc) + cout << " Fully associative array:" << endl; + + cout << " Total dynamic associative search energy/access (nJ): " + << fr->data_array2->power.searchOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power.searchOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tTotal energy in H-tree outside banks(that includes both " + "match key and data transfer) (nJ): " + << (fr->data_array2->power_routing_to_bank.searchOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_routing_to_bank.searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tMatch Key input Htrees inside bank Energy (nJ): " + << (fr->data_array2->power_htree_in_search.searchOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_htree_in_search.searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tResult output Htrees inside bank Energy (nJ): " + << (fr->data_array2->power_htree_out_search.searchOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_htree_out_search.searchOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSearchlines (nJ): " + << fr->data_array2->power_searchline.searchOp.dynamic * 1e9 + + fr->data_array2->power_searchline_precharge.searchOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_searchline.searchOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_searchline_precharge.searchOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tMatchlines (nJ): " + << fr->data_array2->power_matchlines.searchOp.dynamic * 1e9 + + fr->data_array2->power_matchline_precharge.searchOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_matchlines.searchOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_matchline_precharge.searchOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->fully_assoc) { + cout << "\tData portion wordline (nJ): " + << fr->data_array2->power_matchline_to_wordline_drv.searchOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_matchline_to_wordline_drv + .searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tData Bitlines (nJ): " + << fr->data_array2->power_bitlines.searchOp.dynamic * 1e9 + + fr->data_array2->power_prechg_eq_drivers.searchOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << (fr->uca_q[i]->data_array2->power_bitlines.searchOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_prechg_eq_drivers.searchOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->data_array2->power_sense_amps.searchOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_sense_amps.searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + cout << "\tSub-array output driver (nJ): " + << fr->data_array2->power_output_drivers_at_subarray.searchOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_output_drivers_at_subarray + .searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << endl + << " Total dynamic read energy/access (nJ): " + << fr->data_array2->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tTotal energy in H-tree outside banks(that includes both " + "address and data transfer) (nJ): " + << (fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tInput Htree inside bank Energy (nJ): " + << (fr->data_array2->power_addr_input_htree.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_addr_input_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tOutput Htree inside bank Energy (nJ): " + << fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_data_output_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder (nJ): " + << fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2->power_row_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_row_predecoder_blocks.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tWordline (nJ): " + << fr->data_array2->power_row_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_row_decoders.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline mux & associated drivers (nJ): " + << fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << (fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_decoders.readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amp mux & associated drivers (nJ): " + << fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp + .dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_1_decoders + .readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_2_decoders + .readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines (nJ): " + << fr->data_array2->power_bitlines.readOp.dynamic * 1e9 + + fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i]->data_array2->power_bitlines.readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_prechg_eq_drivers.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->data_array2->power_sense_amps.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_sense_amps.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSub-array output driver (nJ): " + << fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_output_drivers_at_subarray.readOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << endl + << " Total leakage power of a bank, including its network outside " + "(mW): " + << (g_ip->long_channel_device + ? fr->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->data_array2->power.readOp.leakage) * + 1e3; // CAM/FA does not support PG yet + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->data_array2->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << endl + << " Tag array: Total dynamic read energy/access (nJ): " + << fr->tag_array2->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power of a bank, power gated "; + if (!g_ip->user_defined_vcc_underflow) { + cout << "with "; + } + else { + cout << "without "; + } + cout << "retaining memory content, including its network outside (mW): " + << (g_ip->long_channel_device + ? fr->tag_array2->power.readOp.power_gated_leakage * + long_channel_leakage_reduction + : fr->tag_array2->power.readOp.power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power of a bank without power gating, including " + "its network outside (mW): " + << (g_ip->long_channel_device + ? fr->tag_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->tag_array2->power.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->tag_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->tag_array2->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + // } + // cout << "\tTotal leakage read/write power of a bank (mW): " << + // fr->tag_array2->power.readOp.leakage * 1e3 << endl; + cout << "\tTotal energy in H-tree outside banks (that includes both " + "address and data transfer) (nJ): " + << (fr->tag_array2->power_routing_to_bank.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_routing_to_bank.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tInput H-tree inside banks Energy (nJ): " + << (fr->tag_array2->power_addr_input_htree.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_addr_input_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tOutput Htree inside a bank Energy (nJ): " + << fr->tag_array2->power_data_output_htree.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_data_output_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder (nJ): " + << fr->tag_array2->power_row_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->tag_array2->power_row_predecoder_blocks.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->tag_array2->power_row_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_row_predecoder_blocks.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tWordline (nJ): " + << fr->tag_array2->power_row_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power_row_decoders.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline mux & associated drivers (nJ): " + << fr->tag_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->tag_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->tag_array2->power_bit_mux_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->tag_array2->power_bit_mux_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_bit_mux_decoders.readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amp mux & associated drivers (nJ): " + << fr->tag_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_1_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_1_decoders.readOp + .dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_2_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_2_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_2_decoders.readOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_1_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_senseamp_mux_lev_1_decoders + .readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_2_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_2_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_senseamp_mux_lev_2_decoders + .readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines precharge and equalization circuit (nJ): " + << fr->tag_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_prechg_eq_drivers.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + cout << "\tBitlines (nJ): " + << fr->tag_array2->power_bitlines.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power_bitlines.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->tag_array2->power_sense_amps.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power_sense_amps.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSub-array output driver (nJ): " + << fr->tag_array2->power_output_drivers_at_subarray.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_output_drivers_at_subarray.readOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power in H-tree outside a bank when power " + "gated (that includes both " + "address and data network) ((mW)): " + << (g_ip->long_channel_device + ? fr->tag_array2->power_routing_to_bank.readOp + .power_gated_leakage * + long_channel_leakage_reduction + : fr->tag_array2->power_routing_to_bank.readOp + .power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power in H-tree outside a bank (that includes " + "both " + "address and data network) without power gating((mW)): " + << (g_ip->long_channel_device + ? fr->tag_array2->power_routing_to_bank.readOp.leakage * + long_channel_leakage_reduction + : fr->tag_array2->power_routing_to_bank.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i] + ->tag_array2->power_routing_to_bank.readOp + .leakage * + long_channel_leakage_reduction + : fr->uca_q[i] + ->tag_array2->power_routing_to_bank.readOp + .leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + // } + + // cout << "\tTotal leakage power of a bank (mW): " << + // fr->tag_array2->power.readOp.leakage * 1e3 << endl; + // cout << "\tTotal leakage power in H-tree (that includes both " + // "address and data network) ((mW)): " << + // (fr->tag_array2->power_addr_input_htree.readOp.leakage + + // fr->tag_array2->power_data_output_htree.readOp.leakage + // + fr->tag_array2->power_routing_to_bank.readOp.leakage) * + // 1e3 << endl; + // + // cout << "\tTotal leakage power in cells (mW): " << + // (fr->tag_array2->array_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in row logic(mW): " << + // (fr->tag_array2->wl_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in column logic(mW): " << + // (fr->tag_array2->cl_leakage) * 1e3 << endl; + // cout << "\tTotal gate leakage power in H-tree (that includes + // both " "address and data network) ((mW)): " << + // (fr->tag_array2->power_addr_input_htree.readOp.gate_leakage + // + + // fr->tag_array2->power_data_output_htree.readOp.gate_leakage + // + + // fr->tag_array2->power_routing_to_bank.readOp.gate_leakage) + // * 1e3 << endl; + } + + cout << endl << endl << "Area Components:" << endl << endl; + /* Data array area stats */ + if (!(g_ip->pure_cam || g_ip->fully_assoc)) + cout << " Data array: Area (mm2): " << fr->data_array2->area * 1e-6 + << endl; + else if (g_ip->pure_cam) + cout << " CAM array: Area (mm2): " << fr->data_array2->area * 1e-6 + << endl; + else + cout << " Fully associative cache array: Area (mm2): " + << fr->data_array2->area * 1e-6 << endl; + + cout << "\tHeight (mm): " << fr->data_array2->all_banks_height * 1e-3 + << endl; + cout << "\tWidth (mm): " << fr->data_array2->all_banks_width * 1e-3 << endl; + if (g_ip->print_detail) { + cout << "\tArea efficiency (Memory cell area/Total area) - " + << fr->data_array2->area_efficiency << " %" << endl; + cout << "\t\tMAT Height (mm): " << fr->data_array2->mat_height * 1e-3 + << endl; + cout << "\t\tMAT Length (mm): " << fr->data_array2->mat_length * 1e-3 + << endl; + cout << "\t\tSubarray Height (mm): " + << fr->data_array2->subarray_height * 1e-3 << endl; + cout << "\t\tSubarray Length (mm): " + << fr->data_array2->subarray_length * 1e-3 << endl; + if (g_ip->power_gating) { + overhead_data = + (fr->data_array2->area / fr->uca_pg_reference->data_array2->area - + 1) * + 100; //%; + cout << " Power gating circuits (sleep transistors) induced area " + "overhead: " + << overhead_data << "%" << endl; + } + } + + /* Tag array area stats */ + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << endl + << " Tag array: Area (mm2): " << fr->tag_array2->area * 1e-6 + << endl; + cout << "\tHeight (mm): " << fr->tag_array2->all_banks_height * 1e-3 + << endl; + cout << "\tWidth (mm): " << fr->tag_array2->all_banks_width * 1e-3 + << endl; + + if (g_ip->print_detail) { + cout << "\tArea efficiency (Memory cell area/Total area) - " + << fr->tag_array2->area_efficiency << " %" << endl; + cout << "\t\tMAT Height (mm): " << fr->tag_array2->mat_height * 1e-3 + << endl; + cout << "\t\tMAT Length (mm): " << fr->tag_array2->mat_length * 1e-3 + << endl; + cout << "\t\tSubarray Height (mm): " + << fr->tag_array2->subarray_height * 1e-3 << endl; + cout << "\t\tSubarray Length (mm): " + << fr->tag_array2->subarray_length * 1e-3 << endl; + } + + if (g_ip->power_gating) { + overhead_tag = + (fr->tag_array2->area / fr->uca_pg_reference->tag_array2->area - + 1) * + 100; //%; + cout << " Power gating circuits (sleep transistors) induced area " + "overhead: " + << overhead_tag << "%" << endl + << endl; + } + } + + // Wire wpr; //TODO: this must change, since this changes the wire value + // during dvs loop. Wire::print_wire();//move outside output UCA + + // cout << "FO4 = " << g_tp.FO4 << endl; + } +} + +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface(InputParameter *const local_interface) { + // g_ip = new InputParameter(); + // g_ip->add_ecc_b_ = true; + + uca_org_t fin_res; + fin_res.valid = false; + + g_ip = local_interface; + + // g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + // g_ip->data_arr_peri_global_tech_type = + // data_arr_peri_global_tech_flavor_in; g_ip->tag_arr_ram_cell_tech_type + // = tag_arr_ram_cell_tech_flavor_in; g_ip->tag_arr_peri_global_tech_type = + // tag_arr_peri_global_tech_flavor_in; + // + // g_ip->ic_proj_type = interconnect_projection_type_in; + // g_ip->wire_is_mat_type = wire_inside_mat_type_in; + // g_ip->wire_os_mat_type = wire_outside_mat_type_in; + // g_ip->burst_len = BURST_LENGTH_in; + // g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; + // g_ip->page_sz_bits = PAGE_SIZE_BITS_in; + // + // g_ip->cache_sz = cache_size; + // g_ip->line_sz = line_size; + // g_ip->assoc = associativity; + // g_ip->nbanks = banks; + // g_ip->out_w = output_width; + // g_ip->specific_tag = specific_tag; + // if (tag_width == 0) { + // g_ip->tag_w = 42; + // } + // else { + // g_ip->tag_w = tag_width; + // } + // + // g_ip->access_mode = access_mode; + // g_ip->delay_wt = obj_func_delay; + // g_ip->dynamic_power_wt = obj_func_dynamic_power; + // g_ip->leakage_power_wt = obj_func_leakage_power; + // g_ip->area_wt = obj_func_area; + // g_ip->cycle_time_wt = obj_func_cycle_time; + // g_ip->delay_dev = dev_func_delay; + // g_ip->dynamic_power_dev = dev_func_dynamic_power; + // g_ip->leakage_power_dev = dev_func_leakage_power; + // g_ip->area_dev = dev_func_area; + // g_ip->cycle_time_dev = dev_func_cycle_time; + // g_ip->temp = temp; + // + // g_ip->F_sz_nm = tech_node; + // g_ip->F_sz_um = tech_node / 1000; + // g_ip->is_main_mem = (main_mem != 0) ? true : false; + // g_ip->is_cache = (cache ==1) ? true : false; + // g_ip->pure_ram = (cache ==0) ? true : false; + // g_ip->pure_cam = (cache ==2) ? true : false; + // g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : + // false; g_ip->ver_htree_wires_over_array = + // VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; + // g_ip->broadcast_addr_din_over_ver_htrees = + // BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; + // + // g_ip->num_rw_ports = rw_ports; + // g_ip->num_rd_ports = excl_read_ports; + // g_ip->num_wr_ports = excl_write_ports; + // g_ip->num_se_rd_ports = single_ended_read_ports; + // g_ip->num_search_ports = search_ports; + // + // g_ip->print_detail = 1; + // g_ip->nuca = 0; + // g_ip->is_cache=true; + // + // if (force_wiretype == 0) + // { + // g_ip->wt = Global; + // g_ip->force_wiretype = false; + // } + // else + // { g_ip->force_wiretype = true; + // if (wiretype==10) { + // g_ip->wt = Global_10; + // } + // if (wiretype==20) { + // g_ip->wt = Global_20; + // } + // if (wiretype==30) { + // g_ip->wt = Global_30; + // } + // if (wiretype==5) { + // g_ip->wt = Global_5; + // } + // if (wiretype==0) { + // g_ip->wt = Low_swing; + // } + // } + // //g_ip->wt = Global_5; + // if (force_config == 0) + // { + // g_ip->force_cache_config = false; + // } + // else + // { + // g_ip->force_cache_config = true; + // g_ip->ndbl=ndbl; + // g_ip->ndwl=ndwl; + // g_ip->nspd=nspd; + // g_ip->ndcm=ndcm; + // g_ip->ndsam1=ndsam1; + // g_ip->ndsam2=ndsam2; + // + // + // } + // + // if (ecc==0){ + // g_ip->add_ecc_b_=false; + // } + // else + // { + // g_ip->add_ecc_b_=true; + // } + + if (!g_ip->error_checking()) + exit(0); + + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + + solve(&fin_res); + + if (!g_ip->dvs_voltage.empty()) { + update_dvs(&fin_res); + } + if (g_ip->power_gating) { + update_pg(&fin_res); // this is needed for compute area overhead of + // power-gating, even the gated power is calculated + // together un-gated leakage + } + + // g_ip->display_ip(); + // output_UCA(&fin_res); + // output_data_csv(fin_res); + // Wire wprint;//reset wires to original configuration as in *.cfg file (dvs + // level 0) Wire::print_wire(); + // delete (g_ip); + + return fin_res; +} + +// McPAT's plain interface, please keep !!! +uca_org_t init_interface(InputParameter *const local_interface) { + // g_ip = new InputParameter(); + // g_ip->add_ecc_b_ = true; + + uca_org_t fin_res; + fin_res.valid = false; + + g_ip = local_interface; + + // g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + // g_ip->data_arr_peri_global_tech_type = + // data_arr_peri_global_tech_flavor_in; g_ip->tag_arr_ram_cell_tech_type + // = tag_arr_ram_cell_tech_flavor_in; g_ip->tag_arr_peri_global_tech_type = + // tag_arr_peri_global_tech_flavor_in; + // + // g_ip->ic_proj_type = interconnect_projection_type_in; + // g_ip->wire_is_mat_type = wire_inside_mat_type_in; + // g_ip->wire_os_mat_type = wire_outside_mat_type_in; + // g_ip->burst_len = BURST_LENGTH_in; + // g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; + // g_ip->page_sz_bits = PAGE_SIZE_BITS_in; + // + // g_ip->cache_sz = cache_size; + // g_ip->line_sz = line_size; + // g_ip->assoc = associativity; + // g_ip->nbanks = banks; + // g_ip->out_w = output_width; + // g_ip->specific_tag = specific_tag; + // if (tag_width == 0) { + // g_ip->tag_w = 42; + // } + // else { + // g_ip->tag_w = tag_width; + // } + // + // g_ip->access_mode = access_mode; + // g_ip->delay_wt = obj_func_delay; + // g_ip->dynamic_power_wt = obj_func_dynamic_power; + // g_ip->leakage_power_wt = obj_func_leakage_power; + // g_ip->area_wt = obj_func_area; + // g_ip->cycle_time_wt = obj_func_cycle_time; + // g_ip->delay_dev = dev_func_delay; + // g_ip->dynamic_power_dev = dev_func_dynamic_power; + // g_ip->leakage_power_dev = dev_func_leakage_power; + // g_ip->area_dev = dev_func_area; + // g_ip->cycle_time_dev = dev_func_cycle_time; + // g_ip->temp = temp; + // + // g_ip->F_sz_nm = tech_node; + // g_ip->F_sz_um = tech_node / 1000; + // g_ip->is_main_mem = (main_mem != 0) ? true : false; + // g_ip->is_cache = (cache ==1) ? true : false; + // g_ip->pure_ram = (cache ==0) ? true : false; + // g_ip->pure_cam = (cache ==2) ? true : false; + // g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : + // false; g_ip->ver_htree_wires_over_array = + // VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; + // g_ip->broadcast_addr_din_over_ver_htrees = + // BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; + // + // g_ip->num_rw_ports = rw_ports; + // g_ip->num_rd_ports = excl_read_ports; + // g_ip->num_wr_ports = excl_write_ports; + // g_ip->num_se_rd_ports = single_ended_read_ports; + // g_ip->num_search_ports = search_ports; + // + // g_ip->print_detail = 1; + // g_ip->nuca = 0; + // + // if (force_wiretype == 0) + // { + // g_ip->wt = Global; + // g_ip->force_wiretype = false; + // } + // else + // { g_ip->force_wiretype = true; + // if (wiretype==10) { + // g_ip->wt = Global_10; + // } + // if (wiretype==20) { + // g_ip->wt = Global_20; + // } + // if (wiretype==30) { + // g_ip->wt = Global_30; + // } + // if (wiretype==5) { + // g_ip->wt = Global_5; + // } + // if (wiretype==0) { + // g_ip->wt = Low_swing; + // } + // } + // //g_ip->wt = Global_5; + // if (force_config == 0) + // { + // g_ip->force_cache_config = false; + // } + // else + // { + // g_ip->force_cache_config = true; + // g_ip->ndbl=ndbl; + // g_ip->ndwl=ndwl; + // g_ip->nspd=nspd; + // g_ip->ndcm=ndcm; + // g_ip->ndsam1=ndsam1; + // g_ip->ndsam2=ndsam2; + // + // + // } + // + // if (ecc==0){ + // g_ip->add_ecc_b_=false; + // } + // else + // { + // g_ip->add_ecc_b_=true; + // } + + g_ip->error_checking(); + + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + // solve(&fin_res); + // g_ip->display_ip(); + + // solve(&fin_res); + // output_UCA(&fin_res); + // output_data_csv(fin_res); + // delete (g_ip); + + return fin_res; +} + +void reconfigure(InputParameter *local_interface, uca_org_t *fin_res) { + // Copy the InputParameter to global interface (g_ip) and do error checking. + g_ip = local_interface; + g_ip->error_checking(); + + // Initialize technology parameters + init_tech_params(g_ip->F_sz_um, false); + + Wire winit; // Do not delete this line. It initializes wires. + + // This corresponds to solve() in the initialization process. + update_dvs(fin_res); +} + +} // namespace cacti diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/io.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/io.h new file mode 100644 index 0000000000..601e92d99a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/io.h @@ -0,0 +1,45 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __IO_H__ +#define __IO_H__ + +#include "cacti_interface.h" +#include "const.h" + +namespace cacti { + +void output_data_csv(const cacti::uca_org_t &fin_res); +void output_UCA(cacti::uca_org_t *fin_res); + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/main.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/main.cc new file mode 100644 index 0000000000..8a9ed400e3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/main.cc @@ -0,0 +1,115 @@ +/*------------------------------------------------------------ + * CACTI 6.5 + * Copyright 2008 Hewlett-Packard Development Corporation + * All Rights Reserved + * + * Permission to use, copy, and modify this software and its documentation is + * hereby granted only under the following terms and conditions. Both the + * above copyright notice and this permission notice must appear in all copies + * of the software, derivative works or modified versions, and any portions + * thereof, and both notices must appear in supporting documentation. + * + * Users of this software agree to the terms and conditions set forth herein, + *and hereby grant back to Hewlett-Packard Company and its affiliated companies + *("HP") a non-exclusive, unrestricted, royalty-free right and license under + *any changes, enhancements or extensions made to the core functions of the + *software, including but not limited to those affording compatibility with + *other hardware or software environments, but excluding applications which + *incorporate this software. Users further agree to use their best efforts to + *return to HP any such changes, enhancements or extensions that they make and + *inform HP of noteworthy uses of this software. Correspondence should be + *provided to HP at: + * + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * This software may be distributed (but not offered for sale or transferred + * for compensation) to third parties, provided such third parties agree to + * abide by the terms and conditions of this notice. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL HP + * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS + * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + *------------------------------------------------------------*/ + +#include +#include "io.h" + +using namespace std; +using namespace cacti; + +int main(int argc, char *argv[]) { + uca_org_t result; + if (argc != 53 && argc != 55) { + bool infile_specified = false; + string infile_name(""); + + for (int32_t i = 0; i < argc; i++) { + if (argv[i] == string("-infile")) { + infile_specified = true; + i++; + infile_name = argv[i]; + } + } + + if (infile_specified == false) { + cerr << " Invalid arguments -- how to use CACTI:" << endl; + cerr << " 1) cacti -infile " << endl; + cerr << " 2) cacti arg1 ... arg52 -- please refer to the README file" + << endl; + cerr << " No. of arguments input - " << argc << endl; + exit(1); + } + else { + result = cacti_interface(infile_name); + } + } + else if (argc == 53) { + result = cacti_interface( + atoi(argv[1]), atoi(argv[2]), atoi(argv[3]), atoi(argv[4]), + atoi(argv[5]), atoi(argv[6]), atoi(argv[7]), atoi(argv[8]), + atoi(argv[9]), atof(argv[10]), atoi(argv[11]), atoi(argv[12]), + atoi(argv[13]), atoi(argv[14]), atoi(argv[15]), atoi(argv[16]), + atoi(argv[17]), atoi(argv[18]), atoi(argv[19]), atoi(argv[20]), + atoi(argv[21]), atoi(argv[22]), atoi(argv[23]), atoi(argv[24]), + atoi(argv[25]), atoi(argv[26]), atoi(argv[27]), atoi(argv[28]), + atoi(argv[29]), atoi(argv[30]), atoi(argv[31]), atoi(argv[32]), + atoi(argv[33]), atoi(argv[34]), atoi(argv[35]), atoi(argv[36]), + atoi(argv[37]), atoi(argv[38]), atoi(argv[39]), atoi(argv[40]), + atoi(argv[41]), atoi(argv[42]), atoi(argv[43]), atoi(argv[44]), + atoi(argv[45]), atoi(argv[46]), atoi(argv[47]), atoi(argv[48]), + atoi(argv[49]), atoi(argv[50]), atoi(argv[51]), atoi(argv[52])); + } + else { + result = cacti_interface( + atoi(argv[1]), atoi(argv[2]), atoi(argv[3]), atoi(argv[4]), + atoi(argv[5]), atoi(argv[6]), atoi(argv[7]), atoi(argv[8]), + atof(argv[9]), atoi(argv[10]), atoi(argv[11]), atoi(argv[12]), + atoi(argv[13]), atoi(argv[14]), atoi(argv[15]), atoi(argv[16]), + atoi(argv[17]), atoi(argv[18]), atoi(argv[19]), atoi(argv[20]), + atoi(argv[21]), atoi(argv[22]), atoi(argv[23]), atoi(argv[24]), + atoi(argv[25]), atoi(argv[26]), atoi(argv[27]), atoi(argv[28]), + atoi(argv[29]), atoi(argv[30]), atoi(argv[31]), atoi(argv[32]), + atoi(argv[33]), atoi(argv[34]), atoi(argv[35]), atoi(argv[36]), + atoi(argv[37]), atoi(argv[38]), atoi(argv[39]), atoi(argv[40]), + atoi(argv[41]), atoi(argv[42]), atoi(argv[43]), atoi(argv[44]), + atoi(argv[45]), atoi(argv[46]), atoi(argv[47]), atoi(argv[48]), + atoi(argv[49]), atoi(argv[50]), atoi(argv[51]), atoi(argv[52]), + atoi(argv[53]), atoi(argv[54])); + } + + result.cleanup(); + // delete result.data_array2; + // if (result.tag_array2!=NULL) + // delete result.tag_array2; + + return 0; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/mat.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/mat.cc new file mode 100644 index 0000000000..48eae4d292 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/mat.cc @@ -0,0 +1,2427 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "mat.h" +#include +using namespace cacti; + +Mat::Mat(const DynamicParameter &dyn_p) + : dp(dyn_p), + power_subarray_out_drv(), + delay_fa_tag(0), + delay_cam(0), + delay_before_decoder(0), + delay_bitline(0), + delay_wl_reset(0), + delay_bl_restore(0), + delay_searchline(0), + delay_matchchline(0), + delay_cam_sl_restore(0), + delay_cam_ml_reset(0), + delay_fa_ram_wl(0), + delay_hit_miss_reset(0), + delay_hit_miss(0), + subarray(dp, dp.fully_assoc), + power_bitline(), + per_bitline_read_energy(0), + deg_bl_muxing(dp.deg_bl_muxing), + num_act_mats_hor_dir(dyn_p.num_act_mats_hor_dir), + delay_writeback(0), + cell(subarray.cell), + cam_cell(subarray.cam_cell), + is_dram(dyn_p.is_dram), + pure_cam(dyn_p.pure_cam), + num_mats(dp.num_mats), + power_sa(), + delay_sa(0), + leak_power_sense_amps_closed_page_state(0), + leak_power_sense_amps_open_page_state(0), + delay_subarray_out_drv(0), + delay_comparator(0), + power_comparator(), + num_do_b_mat(dyn_p.num_do_b_mat), + num_so_b_mat(dyn_p.num_so_b_mat), + num_subarrays_per_mat(dp.num_subarrays / dp.num_mats), + num_subarrays_per_row(dp.Ndwl / dp.num_mats_h_dir), + array_leakage(0), + wl_leakage(0), + cl_leakage(0), + sram_sleep_tx(0) { + assert(num_subarrays_per_mat <= 4); + assert(num_subarrays_per_row <= 2); + is_fa = (dp.fully_assoc) ? true : false; + camFlag = (is_fa || pure_cam); // although cam_cell.w = cell.w for fa, we + // still differentiate them. + + if (is_fa || pure_cam) + num_subarrays_per_row = num_subarrays_per_mat > 2 + ? num_subarrays_per_mat / 2 + : num_subarrays_per_mat; + + if (dp.use_inp_params == 1) { + RWP = dp.num_rw_ports; + ERP = dp.num_rd_ports; + EWP = dp.num_wr_ports; + SCHP = dp.num_search_ports; + } + else { + RWP = g_ip->num_rw_ports; + ERP = g_ip->num_rd_ports; + EWP = g_ip->num_wr_ports; + SCHP = g_ip->num_search_ports; + } + + double number_sa_subarray; + + if (!is_fa && !pure_cam) { + number_sa_subarray = subarray.num_cols / deg_bl_muxing; + } + else if (is_fa && !pure_cam) { + number_sa_subarray = + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram) / deg_bl_muxing; + } + + else { + number_sa_subarray = (subarray.num_cols_fa_cam) / deg_bl_muxing; + } + + int num_dec_signals = subarray.num_rows; + double C_ld_bit_mux_dec_out = 0; + double C_ld_sa_mux_lev_1_dec_out = 0; + double C_ld_sa_mux_lev_2_dec_out = 0; + double R_wire_wl_drv_out; + + if (!is_fa && !pure_cam) { + R_wire_wl_drv_out = subarray.num_cols * cell.w * g_tp.wire_local.R_per_um; + } + else if (is_fa && !pure_cam) { + R_wire_wl_drv_out = (subarray.num_cols_fa_cam * cam_cell.w + + subarray.num_cols_fa_ram * cell.w) * + g_tp.wire_local.R_per_um; + } + else { + R_wire_wl_drv_out = + (subarray.num_cols_fa_cam * cam_cell.w) * g_tp.wire_local.R_per_um; + } + + double R_wire_bit_mux_dec_out = num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.R_per_um * + cell.w; // TODO:revisit for FA + double R_wire_sa_mux_dec_out = num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.R_per_um * cell.w; + + if (deg_bl_muxing > 1) { + C_ld_bit_mux_dec_out = + (2 * num_subarrays_per_mat * subarray.num_cols / deg_bl_muxing) * + gate_C(g_tp.w_nmos_b_mux, 0, is_dram) + // 2 transistor per cell + num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.C_per_um * cell.get_w(); + } + + if (dp.Ndsam_lev_1 > 1) { + C_ld_sa_mux_lev_1_dec_out = + (num_subarrays_per_mat * number_sa_subarray / dp.Ndsam_lev_1) * + gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) + + num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.C_per_um * cell.get_w(); + } + if (dp.Ndsam_lev_2 > 1) { + C_ld_sa_mux_lev_2_dec_out = (num_subarrays_per_mat * number_sa_subarray / + (dp.Ndsam_lev_1 * dp.Ndsam_lev_2)) * + gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) + + num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.C_per_um * + cell.get_w(); + } + + if (num_subarrays_per_row >= 2) { + // wire heads for both right and left side of a mat, so half the resistance + R_wire_bit_mux_dec_out /= 2.0; + R_wire_sa_mux_dec_out /= 2.0; + } + + row_dec = + new Decoder(num_dec_signals, false, subarray.C_wl, R_wire_wl_drv_out, + false /*is_fa*/, is_dram, true, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false, subarray.num_rows); + + // row_dec->nodes_DSTN = subarray.num_rows;//TODO: this is not a good way for + // OOO programming if (is_fa && (!dp.is_tag)) + // { + // row_dec->exist = true; + // } + bit_mux_dec = + new Decoder(deg_bl_muxing, // This number is 1 for FA or CAM + false, C_ld_bit_mux_dec_out, R_wire_bit_mux_dec_out, + false /*is_fa*/, is_dram, false, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false); + sa_mux_lev_1_dec = + new Decoder(dp.deg_senseamp_muxing_non_associativity, // This number is 1 + // for FA or CAM + dp.number_way_select_signals_mat + ? true + : false, // only sa_mux_lev_1_dec needs way select signal + C_ld_sa_mux_lev_1_dec_out, R_wire_sa_mux_dec_out, + false /*is_fa*/, is_dram, false, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false); + sa_mux_lev_2_dec = + new Decoder(dp.Ndsam_lev_2, // This number is 1 for FA or CAM + false, C_ld_sa_mux_lev_2_dec_out, R_wire_sa_mux_dec_out, + false /*is_fa*/, is_dram, false, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false); + + double C_wire_predec_blk_out; + double R_wire_predec_blk_out; + + if (!is_fa && !pure_cam) { + C_wire_predec_blk_out = num_subarrays_per_row * subarray.num_rows * + g_tp.wire_inside_mat.C_per_um * cell.h; + R_wire_predec_blk_out = num_subarrays_per_row * subarray.num_rows * + g_tp.wire_inside_mat.R_per_um * cell.h; + } + else // for pre-decode block's load is same for both FA and CAM + { + C_wire_predec_blk_out = + subarray.num_rows * g_tp.wire_inside_mat.C_per_um * cam_cell.h; + R_wire_predec_blk_out = + subarray.num_rows * g_tp.wire_inside_mat.R_per_um * cam_cell.h; + } + + if (is_fa || pure_cam) + num_dec_signals += _log2(num_subarrays_per_mat); + + PredecBlk *r_predec_blk1 = new PredecBlk( + num_dec_signals, row_dec, C_wire_predec_blk_out, R_wire_predec_blk_out, + num_subarrays_per_mat, is_dram, true); + PredecBlk *r_predec_blk2 = new PredecBlk( + num_dec_signals, row_dec, C_wire_predec_blk_out, R_wire_predec_blk_out, + num_subarrays_per_mat, is_dram, false); + PredecBlk *b_mux_predec_blk1 = + new PredecBlk(deg_bl_muxing, bit_mux_dec, 0, 0, 1, is_dram, true); + PredecBlk *b_mux_predec_blk2 = + new PredecBlk(deg_bl_muxing, bit_mux_dec, 0, 0, 1, is_dram, false); + PredecBlk *sa_mux_lev_1_predec_blk1 = + new PredecBlk(dyn_p.deg_senseamp_muxing_non_associativity, + sa_mux_lev_1_dec, 0, 0, 1, is_dram, true); + PredecBlk *sa_mux_lev_1_predec_blk2 = + new PredecBlk(dyn_p.deg_senseamp_muxing_non_associativity, + sa_mux_lev_1_dec, 0, 0, 1, is_dram, false); + PredecBlk *sa_mux_lev_2_predec_blk1 = + new PredecBlk(dp.Ndsam_lev_2, sa_mux_lev_2_dec, 0, 0, 1, is_dram, true); + PredecBlk *sa_mux_lev_2_predec_blk2 = + new PredecBlk(dp.Ndsam_lev_2, sa_mux_lev_2_dec, 0, 0, 1, is_dram, false); + dummy_way_sel_predec_blk1 = + new PredecBlk(1, sa_mux_lev_1_dec, 0, 0, 0, is_dram, true); + dummy_way_sel_predec_blk2 = + new PredecBlk(1, sa_mux_lev_1_dec, 0, 0, 0, is_dram, false); + + PredecBlkDrv *r_predec_blk_drv1 = new PredecBlkDrv(0, r_predec_blk1, is_dram); + PredecBlkDrv *r_predec_blk_drv2 = new PredecBlkDrv(0, r_predec_blk2, is_dram); + PredecBlkDrv *b_mux_predec_blk_drv1 = + new PredecBlkDrv(0, b_mux_predec_blk1, is_dram); + PredecBlkDrv *b_mux_predec_blk_drv2 = + new PredecBlkDrv(0, b_mux_predec_blk2, is_dram); + PredecBlkDrv *sa_mux_lev_1_predec_blk_drv1 = + new PredecBlkDrv(0, sa_mux_lev_1_predec_blk1, is_dram); + PredecBlkDrv *sa_mux_lev_1_predec_blk_drv2 = + new PredecBlkDrv(0, sa_mux_lev_1_predec_blk2, is_dram); + PredecBlkDrv *sa_mux_lev_2_predec_blk_drv1 = + new PredecBlkDrv(0, sa_mux_lev_2_predec_blk1, is_dram); + PredecBlkDrv *sa_mux_lev_2_predec_blk_drv2 = + new PredecBlkDrv(0, sa_mux_lev_2_predec_blk2, is_dram); + way_sel_drv1 = new PredecBlkDrv(dyn_p.number_way_select_signals_mat, + dummy_way_sel_predec_blk1, is_dram); + dummy_way_sel_predec_blk_drv2 = + new PredecBlkDrv(1, dummy_way_sel_predec_blk2, is_dram); + + r_predec = new Predec(r_predec_blk_drv1, r_predec_blk_drv2); + b_mux_predec = new Predec(b_mux_predec_blk_drv1, b_mux_predec_blk_drv2); + sa_mux_lev_1_predec = + new Predec(sa_mux_lev_1_predec_blk_drv1, sa_mux_lev_1_predec_blk_drv2); + sa_mux_lev_2_predec = + new Predec(sa_mux_lev_2_predec_blk_drv1, sa_mux_lev_2_predec_blk_drv2); + + subarray_out_wire = + new Wire(Global, (g_ip->cl_vertical ? subarray.area.w : subarray.area.h), + 1, 1, inside_mat); // should be subarray.area.w; if with /2 + // means average length + + double driver_c_gate_load; + double driver_c_wire_load; + double driver_r_wire_load; + + if (is_fa || pure_cam) + + { // Although CAM and RAM use different bl pre-charge driver, assuming the + // precharge p size is the same + driver_c_gate_load = + (subarray.num_cols_fa_cam) * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, + false, false); + driver_c_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.R_per_um; + cam_bl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + if (!pure_cam) { + // This is only used for fully asso not pure CAM + driver_c_gate_load = + (subarray.num_cols_fa_ram) * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, + false, false); + driver_c_wire_load = + subarray.num_cols_fa_ram * cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols_fa_ram * cell.w * g_tp.wire_outside_mat.R_per_um; + bl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + } + } + + else { + driver_c_gate_load = + subarray.num_cols * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, + false, false); + driver_c_wire_load = + subarray.num_cols * cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols * cell.w * g_tp.wire_outside_mat.R_per_um; + bl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + } + double area_row_decoder = + row_dec->area.get_area() * subarray.num_rows * (RWP + ERP + EWP); + double w_row_decoder = area_row_decoder / subarray.area.get_h(); + + double h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux = + compute_bit_mux_sa_precharge_sa_mux_wr_drv_wr_mux_h(); + + /* This means the subarray drivers are along the vertical (y) direction since + * / subarray.area.get_w() is used; so the subarray_out_wire (actually the + * drivers) under the subarray and along the horizontal (x) direction So as + * mentioned above @ line 271 subarray_out_wire = new Wire(g_ip->wt, + * subarray.area.h);//should be subarray.area.w change the out_wire (driver to + * along y direction need carefully rethinking rather than just simply switch + * w with h ) + * */ + double h_subarray_out_drv = + subarray_out_wire->area.get_area() * + (subarray.num_cols / (deg_bl_muxing * dp.Ndsam_lev_1 * dp.Ndsam_lev_2)) / + subarray.area.get_w(); + + h_subarray_out_drv *= (RWP + ERP + SCHP); + + double h_comparators = 0.0; + double w_row_predecode_output_wires = 0.0; + double h_bit_mux_dec_out_wires = 0.0; + double h_senseamp_mux_dec_out_wires = 0.0; + + if ((!is_fa) && (dp.is_tag)) { + // tagbits = (4 * num_cols_subarray / (deg_bl_muxing * dp.Ndsam_lev_1 * + // dp.Ndsam_lev_2)) / num_do_b_mat; + h_comparators = compute_comparators_height(dp.tagbits, dyn_p.num_do_b_mat, + subarray.area.get_w()); + h_comparators *= (RWP + ERP); + } + + // power-gating circuit + bool is_footer = false; + double Isat_subarray = + 2 * simplified_nmos_Isat(g_tp.sram.cell_nmos_w, is_dram, + true); // only one wordline active in a subarray + // 2 means two inverters in an SRAM cell + double detalV_array; //, deltaV_wl, deltaV_floatingBL; + double c_wakeup_array; + + if (!(is_fa || pure_cam) && + g_ip->power_gating) { // for SRAM only at this moment + c_wakeup_array = drain_C_(g_tp.sram.cell_pmos_w, PCH, 1, 1, cell.h, is_dram, + true); // 1 inv + c_wakeup_array += + 2 * drain_C_(g_tp.sram.cell_pmos_w, PCH, 1, 1, cell.h, is_dram, true) + + drain_C_(g_tp.sram.cell_nmos_w, NCH, 1, 1, cell.h, is_dram, + true); // 1 inv + c_wakeup_array *= subarray.num_rows; // all the SRAM cells in a bitline is + // connected to the sleep tx to + // provide Vcc_min + detalV_array = g_tp.sram_cell.Vdd - g_tp.sram_cell.Vcc_min; + + sram_sleep_tx = new Sleep_tx(g_ip->perfloss, Isat_subarray, is_footer, + c_wakeup_array, detalV_array, 1, cell); + + subarray.area.set_h(subarray.area.h + sram_sleep_tx->area.h); + + // TODO: add the sleep tx in the wl driver and + } + + int branch_effort_predec_blk1_out = + (1 << r_predec_blk2->number_input_addr_bits); + int branch_effort_predec_blk2_out = + (1 << r_predec_blk1->number_input_addr_bits); + w_row_predecode_output_wires = + (branch_effort_predec_blk1_out + branch_effort_predec_blk2_out) * + g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP); + + double h_non_cell_area = + (num_subarrays_per_mat / num_subarrays_per_row) * + (h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux + + h_subarray_out_drv + h_comparators); + + double w_non_cell_area = + MAX(w_row_predecode_output_wires, num_subarrays_per_row * w_row_decoder); + + if (deg_bl_muxing > 1) { + h_bit_mux_dec_out_wires = + deg_bl_muxing * g_tp.wire_inside_mat.pitch * (RWP + ERP); + } + if (dp.Ndsam_lev_1 > 1) { + h_senseamp_mux_dec_out_wires = + dp.Ndsam_lev_1 * g_tp.wire_inside_mat.pitch * (RWP + ERP); + } + if (dp.Ndsam_lev_2 > 1) { + h_senseamp_mux_dec_out_wires += + dp.Ndsam_lev_2 * g_tp.wire_inside_mat.pitch * (RWP + ERP); + } + + double h_addr_datain_wires; + if (!g_ip->ver_htree_wires_over_array) { + h_addr_datain_wires = + (dp.number_addr_bits_mat + dp.number_way_select_signals_mat + + (dp.num_di_b_mat + dp.num_do_b_mat) / num_subarrays_per_row) * + g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP); + + if (is_fa || pure_cam) { + h_addr_datain_wires = + (dp.number_addr_bits_mat + + dp.number_way_select_signals_mat + // TODO: revisit + (dp.num_di_b_mat + dp.num_do_b_mat) / num_subarrays_per_row) * + g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP) + + (dp.num_si_b_mat + dp.num_so_b_mat) / num_subarrays_per_row * + g_tp.wire_inside_mat.pitch * SCHP; + } + // h_non_cell_area = 2 * h_bit_mux_sense_amp_precharge_sa_mux + + // MAX(h_addr_datain_wires, 2 * h_subarray_out_drv); + h_non_cell_area = + (h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux + + h_comparators + h_subarray_out_drv) * + (num_subarrays_per_mat / num_subarrays_per_row) + + h_addr_datain_wires + h_bit_mux_dec_out_wires + + h_senseamp_mux_dec_out_wires; + } + + // double area_rectangle_center_mat = h_non_cell_area * w_non_cell_area; + double area_mat_center_circuitry = + (r_predec_blk_drv1->area.get_area() + + b_mux_predec_blk_drv1->area.get_area() + + sa_mux_lev_1_predec_blk_drv1->area.get_area() + + sa_mux_lev_2_predec_blk_drv1->area.get_area() + + way_sel_drv1->area.get_area() + r_predec_blk_drv2->area.get_area() + + b_mux_predec_blk_drv2->area.get_area() + + sa_mux_lev_1_predec_blk_drv2->area.get_area() + + sa_mux_lev_2_predec_blk_drv2->area.get_area() + + r_predec_blk1->area.get_area() + b_mux_predec_blk1->area.get_area() + + sa_mux_lev_1_predec_blk1->area.get_area() + + sa_mux_lev_2_predec_blk1->area.get_area() + + r_predec_blk2->area.get_area() + b_mux_predec_blk2->area.get_area() + + sa_mux_lev_1_predec_blk2->area.get_area() + + sa_mux_lev_2_predec_blk2->area.get_area() + + bit_mux_dec->area.get_area() + sa_mux_lev_1_dec->area.get_area() + + sa_mux_lev_2_dec->area.get_area()) * + (RWP + ERP + EWP); + + // double area_efficiency_mat; + + // if (!is_fa) + // { + assert(num_subarrays_per_mat / num_subarrays_per_row > 0); + area.h = (num_subarrays_per_mat / num_subarrays_per_row) * subarray.area.h + + h_non_cell_area; + area.w = num_subarrays_per_row * subarray.area.get_w() + w_non_cell_area; + area.w = (area.h * area.w + area_mat_center_circuitry) / area.h; + // area_efficiency_mat = subarray.area.get_area() * num_subarrays_per_mat * + // 100.0 / area.get_area(); + + // cout<<"h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux"< 0); + assert(area.w > 0); + // } + // else + // { + // area.h = (num_subarrays_per_mat / num_subarrays_per_row) * + // subarray.area.get_h() + h_non_cell_area; area.w = num_subarrays_per_row + // * subarray.area.get_w() + w_non_cell_area; area.w = (area.h*area.w + + // area_mat_center_circuitry) / area.h; area_efficiency_mat = + // subarray.area.get_area() * num_subarrays_per_row * 100.0 / + // area.get_area(); + // } +} + +Mat::~Mat() { + delete row_dec; + delete bit_mux_dec; + delete sa_mux_lev_1_dec; + delete sa_mux_lev_2_dec; + + delete r_predec->blk1; + delete r_predec->blk2; + delete b_mux_predec->blk1; + delete b_mux_predec->blk2; + delete sa_mux_lev_1_predec->blk1; + delete sa_mux_lev_1_predec->blk2; + delete sa_mux_lev_2_predec->blk1; + delete sa_mux_lev_2_predec->blk2; + delete dummy_way_sel_predec_blk1; + delete dummy_way_sel_predec_blk2; + + delete r_predec->drv1; + delete r_predec->drv2; + delete b_mux_predec->drv1; + delete b_mux_predec->drv2; + delete sa_mux_lev_1_predec->drv1; + delete sa_mux_lev_1_predec->drv2; + delete sa_mux_lev_2_predec->drv1; + delete sa_mux_lev_2_predec->drv2; + delete way_sel_drv1; + delete dummy_way_sel_predec_blk_drv2; + + delete r_predec; + delete b_mux_predec; + delete sa_mux_lev_1_predec; + delete sa_mux_lev_2_predec; + + delete subarray_out_wire; + if (!pure_cam) + delete bl_precharge_eq_drv; + + if (is_fa || pure_cam) { + delete sl_precharge_eq_drv; + delete sl_data_drv; + delete cam_bl_precharge_eq_drv; + delete ml_precharge_drv; + delete ml_to_ram_wl_drv; + } + if (sram_sleep_tx != 0) { + delete sram_sleep_tx; + } +} + +double Mat::compute_delays(double inrisetime) { + int k; + double rd, C_intrinsic, C_ld, tf, R_bl_precharge, r_b_metal, R_bl, C_bl; + double outrisetime_search, outrisetime, row_dec_outrisetime; + // delay calculation for tags of fully associative cache + if (is_fa || pure_cam) { + // Compute search access time + outrisetime_search = compute_cam_delay(inrisetime); + if (is_fa) { + bl_precharge_eq_drv->compute_delay(0); + k = ml_to_ram_wl_drv->number_gates - 1; + rd = tr_R_on(ml_to_ram_wl_drv->width_n[k], NCH, 1, is_dram, false, true); + C_intrinsic = drain_C_(ml_to_ram_wl_drv->width_n[k], PCH, 1, 1, + 4 * cell.h, is_dram, false, true) + + drain_C_(ml_to_ram_wl_drv->width_n[k], NCH, 1, 1, + 4 * cell.h, is_dram, false, true); + C_ld = ml_to_ram_wl_drv->c_gate_load + ml_to_ram_wl_drv->c_wire_load; + tf = rd * (C_intrinsic + C_ld) + ml_to_ram_wl_drv->r_wire_load * C_ld / 2; + delay_wl_reset = horowitz(0, tf, 0.5, 0.5, RISE); + + R_bl_precharge = + tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false); + r_b_metal = cam_cell.h * + g_tp.wire_local.R_per_um; // dummy rows in sram are filled in + R_bl = subarray.num_rows * r_b_metal; + C_bl = subarray.C_bl; + delay_bl_restore = bl_precharge_eq_drv->delay + + log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) / + (g_tp.sram.Vbitpre - dp.V_b_sense)) * + (R_bl_precharge * C_bl + R_bl * C_bl / 2); + + outrisetime_search = compute_bitline_delay(outrisetime_search); + outrisetime_search = compute_sa_delay(outrisetime_search); + } + outrisetime_search = compute_subarray_out_drv(outrisetime_search); + subarray_out_wire->set_in_rise_time(outrisetime_search); + outrisetime_search = subarray_out_wire->signal_rise_time(); + delay_subarray_out_drv_htree = + delay_subarray_out_drv + subarray_out_wire->delay; + + // TODO: this is just for compute plain read/write energy for fa and cam, + // plain read/write access timing need to be revisited. + outrisetime = r_predec->compute_delays(inrisetime); + row_dec_outrisetime = row_dec->compute_delays(outrisetime); + + outrisetime = b_mux_predec->compute_delays(inrisetime); + bit_mux_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_1_predec->compute_delays(inrisetime); + sa_mux_lev_1_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_2_predec->compute_delays(inrisetime); + sa_mux_lev_2_dec->compute_delays(outrisetime); + + if (pure_cam) { + outrisetime = compute_bitline_delay(row_dec_outrisetime); + outrisetime = compute_sa_delay(outrisetime); + } + return outrisetime_search; + } + else { + bl_precharge_eq_drv->compute_delay(0); + if (row_dec->exist == true) { + int k = row_dec->num_gates - 1; + double rd = tr_R_on(row_dec->w_dec_n[k], NCH, 1, is_dram, false, true); + // TODO: this 4*cell.h number must be revisited + double C_intrinsic = drain_C_(row_dec->w_dec_p[k], PCH, 1, 1, 4 * cell.h, + is_dram, false, true) + + drain_C_(row_dec->w_dec_n[k], NCH, 1, 1, 4 * cell.h, + is_dram, false, true); + double C_ld = row_dec->C_ld_dec_out; + double tf = + rd * (C_intrinsic + C_ld) + row_dec->R_wire_dec_out * C_ld / 2; + delay_wl_reset = horowitz(0, tf, 0.5, 0.5, RISE); + } + double R_bl_precharge = + tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false); + double r_b_metal = cell.h * g_tp.wire_local.R_per_um; + double R_bl = subarray.num_rows * r_b_metal; + double C_bl = subarray.C_bl; + + if (is_dram) { + delay_bl_restore = bl_precharge_eq_drv->delay + + 2.3 * (R_bl_precharge * C_bl + R_bl * C_bl / 2); + } + else { + delay_bl_restore = bl_precharge_eq_drv->delay + + log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) / + (g_tp.sram.Vbitpre - dp.V_b_sense)) * + (R_bl_precharge * C_bl + R_bl * C_bl / 2); + } + } + + outrisetime = r_predec->compute_delays(inrisetime); + row_dec_outrisetime = row_dec->compute_delays(outrisetime); + + outrisetime = b_mux_predec->compute_delays(inrisetime); + bit_mux_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_1_predec->compute_delays(inrisetime); + sa_mux_lev_1_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_2_predec->compute_delays(inrisetime); + sa_mux_lev_2_dec->compute_delays(outrisetime); + + outrisetime = compute_bitline_delay(row_dec_outrisetime); + outrisetime = compute_sa_delay(outrisetime); + outrisetime = compute_subarray_out_drv(outrisetime); + subarray_out_wire->set_in_rise_time(outrisetime); + outrisetime = subarray_out_wire->signal_rise_time(); + + delay_subarray_out_drv_htree = + delay_subarray_out_drv + subarray_out_wire->delay; + + if (dp.is_tag == true && dp.fully_assoc == false) { + compute_comparator_delay(0); + } + + if (row_dec->exist == false) { + delay_wl_reset = MAX(r_predec->blk1->delay, r_predec->blk2->delay); + } + + // cout<<"r_predec delay=" <delay<<" row_dec delay = " + // <delay< 1) { + height += compute_tr_width_after_folding( + g_tp.w_nmos_b_mux, cell.w / (2 * (RWP + ERP))); // col mux tr height + // height += deg_bl_muxing * g_tp.wire_inside_mat.pitch * (RWP + ERP); // + // bit mux dec out wires height + } + + height += + height_sense_amplifier(/*camFlag? sram_cell.w:*/ cell.w * deg_bl_muxing / + (RWP + ERP)); // sense_amp_height + + if (dp.Ndsam_lev_1 > 1) { + height += compute_tr_width_after_folding( + g_tp.w_nmos_sa_mux, + cell.w * dp.Ndsam_lev_1 / (RWP + ERP)); // sense_amp_mux_height + // height_senseamp_mux_decode_output_wires = Ndsam * wire_inside_mat_pitch + // * (RWP + ERP); + } + + if (dp.Ndsam_lev_2 > 1) { + height += compute_tr_width_after_folding( + g_tp.w_nmos_sa_mux, cell.w * deg_bl_muxing * dp.Ndsam_lev_1 / + (RWP + ERP)); // sense_amp_mux_height + // height_senseamp_mux_decode_output_wires = Ndsam * wire_inside_mat_pitch + // * (RWP + ERP); + + // add height of inverter-buffers between the two levels (pass-transistors) + // of sense-amp mux + height += 2 * compute_tr_width_after_folding( + pmos_to_nmos_sz_ratio(is_dram) * g_tp.min_w_nmos_, + cell.w * dp.Ndsam_lev_2 / (RWP + ERP)); + height += 2 * compute_tr_width_after_folding( + g_tp.min_w_nmos_, cell.w * dp.Ndsam_lev_2 / (RWP + ERP)); + } + + // TODO: this should be uncommented... + /*if (deg_bl_muxing * dp.Ndsam_lev_1 * dp.Ndsam_lev_2 > 1) + { + //height_write_mux_decode_output_wires = deg_bl_muxing * Ndsam * + g_tp.wire_inside_mat.pitch * (RWP + EWP); double width_write_driver_write_mux + = width_write_driver_or_write_mux(); double height_write_driver_write_mux = + compute_tr_width_after_folding(2 * width_write_driver_write_mux, cell.w * + // deg_bl_muxing * + dp.Ndsam_lev_1 * dp.Ndsam_lev_2 / (RWP + EWP)); + height += height_write_driver_write_mux; + }*/ + + return height; +} + +double Mat::compute_cam_delay(double inrisetime) { + double out_time_ramp, this_delay; + double Rwire, tf, c_intrinsic, rd, Cwire, c_gate_load; + + double // Wdecdrivep, Wdecdriven, Wfadriven, Wfadrivep, Wfadrive2n, + // Wfadrive2p, Wfadecdrive1n, Wfadecdrive1p, Wfadecdrive2n, + // Wfadecdrive2p, Wfadecdriven, Wfadecdrivep, Wfaprechn, + Wfaprechp, + Wdummyn, Wdummyinvn, Wdummyinvp, + // Wfainvn, Wfainvp, + Waddrnandn, Waddrnandp, + // Wfanandn, Wfanandp, + Wfanorn, Wfanorp, + // Wdecnandn, Wdecnandp, + W_hit_miss_n, W_hit_miss_p; + + double c_matchline_metal, r_matchline_metal, c_searchline_metal, + r_searchline_metal, dynSearchEng; + int Htagbits; + + double driver_c_gate_load; + double driver_c_wire_load; + double driver_r_wire_load; + // double searchline_precharge_time; + + double leak_power_cc_inverters_sram_cell = 0; + double leak_power_acc_tr_RW_or_WR_port_sram_cell = 0; + double leak_power_RD_port_sram_cell = 0; + double leak_power_SCHP_port_sram_cell = 0; + double leak_comparator_cam_cell = 0; + + double gate_leak_comparator_cam_cell = 0; + double gate_leak_power_cc_inverters_sram_cell = 0; + double gate_leak_power_RD_port_sram_cell = 0; + double gate_leak_power_SCHP_port_sram_cell = 0; + + c_matchline_metal = cam_cell.get_w() * g_tp.wire_local.C_per_um; + c_searchline_metal = cam_cell.get_h() * g_tp.wire_local.C_per_um; + r_matchline_metal = cam_cell.get_w() * g_tp.wire_local.R_per_um; + r_searchline_metal = cam_cell.get_h() * g_tp.wire_local.R_per_um; + + dynSearchEng = 0.0; + delay_matchchline = 0.0; + double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(is_dram); + bool linear_scaling = false; + + if (linear_scaling) { + // Wdecdrivep = + // 450 * g_ip->F_sz_um; // this was 360 micron for the 0.8 micron + // process + // Wdecdriven = + // 300 * g_ip->F_sz_um; // this was 240 micron for the 0.8 micron + // process + // Wfadriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfadrive2n = + // 250 * g_ip->F_sz_um; // this was 200 micron for the 0.8 micron + // process + // Wfadrive2p = + // 500 * g_ip->F_sz_um; // this was 400 micron for the 0.8 micron + // process + // Wfadecdrive1n = + // 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron + // process + // Wfadecdrive1p = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfadecdrive2n = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfadecdrive2p = + // 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron + // process + // Wfadecdriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadecdrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfaprechn = + // 7.5 * g_ip->F_sz_um; // this was 6 micron for the 0.8 micron + // process + // Wfainvn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfainvp = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandn = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + // Wdecnandn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wdecnandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + + Wfaprechp = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + Wdummyn = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + Wdummyinvn = + 75 * g_ip->F_sz_um; // this was 60 micron for the 0.8 micron process + Wdummyinvp = + 100 * g_ip->F_sz_um; // this was 80 micron for the 0.8 micron process + Waddrnandn = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Waddrnandp = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Wfanorn = + 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron process + Wfanorp = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + W_hit_miss_n = Wdummyn; + W_hit_miss_p = g_tp.min_w_nmos_ * p_to_n_sizing_r; + // TODO: this number should updated using new layout; from the NAND to + // output NOR should be computed using logical effort + } + else { + // Wdecdrivep = + // 450 * g_ip->F_sz_um; // this was 360 micron for the 0.8 micron + // process + // Wdecdriven = + // 300 * g_ip->F_sz_um; // this was 240 micron for the 0.8 micron + // process + // Wfadriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfadrive2n = + // 250 * g_ip->F_sz_um; // this was 200 micron for the 0.8 micron + // process + // Wfadrive2p = + // 500 * g_ip->F_sz_um; // this was 400 micron for the 0.8 micron + // process + // Wfadecdrive1n = + // 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron + // process + // Wfadecdrive1p = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfadecdrive2n = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfadecdrive2p = + // 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron + // process + // Wfadecdriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadecdrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfaprechn = + // 7.5 * g_ip->F_sz_um; // this was 6 micron for the 0.8 micron + // process + // Wfainvn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfainvp = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandn = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + // Wdecnandn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wdecnandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + + Wfaprechp = g_tp.w_pmos_bl_precharge; // this was 10 micron for the 0.8 + // micron process + Wdummyn = g_tp.cam.cell_nmos_w; + Wdummyinvn = + 75 * g_ip->F_sz_um; // this was 60 micron for the 0.8 micron process + Wdummyinvp = + 100 * g_ip->F_sz_um; // this was 80 micron for the 0.8 micron process + Waddrnandn = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Waddrnandp = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Wfanorn = + 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron process + Wfanorp = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + W_hit_miss_n = Wdummyn; + W_hit_miss_p = g_tp.min_w_nmos_ * p_to_n_sizing_r; + } + + Htagbits = (int)(ceil((double)(subarray.num_cols_fa_cam) / 2.0)); + + /* First stage, searchline is precharged. searchline data driver drives the + searchline to open (if miss) the comparators. search_line_delay, + search_line_power, search_line_restore_delay for cycle time computation. + From the driver(am and an) to the comparators in all the rows including the + dummy row, Assuming that comparators in both the normal matching line and + the dummy matching line have the same sizing */ + + // Searchline precharge circuitry is same as that of bitline. However, no + // sharing between search ports and r/w ports Searchline precharge routes + // horizontally + driver_c_gate_load = subarray.num_cols_fa_cam * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, + 0, is_dram, false, false); + driver_c_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.R_per_um; + + sl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + // searchline data driver ; subarray.num_rows + 1 is because of the dummy row + // data drv should only have gate_C not 2*gate_C since the two searchlines are + // differential--same as bitlines + driver_c_gate_load = + (subarray.num_rows + 1) * gate_C(Wdummyn, 0, is_dram, false, false); + driver_c_wire_load = (subarray.num_rows + 1) * c_searchline_metal; + driver_r_wire_load = (subarray.num_rows + 1) * r_searchline_metal; + sl_data_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + sl_precharge_eq_drv->compute_delay(0); + double R_bl_precharge = + tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, + false); // Assuming CAM and SRAM have same Pre_eq_dr + double r_b_metal = cam_cell.h * g_tp.wire_local.R_per_um; + double R_bl = (subarray.num_rows + 1) * r_b_metal; + double C_bl = subarray.C_bl_cam; + delay_cam_sl_restore = + sl_precharge_eq_drv->delay + + log(g_tp.cam.Vbitpre) * (R_bl_precharge * C_bl + R_bl * C_bl / 2); + + out_time_ramp = sl_data_drv->compute_delay( + inrisetime); // After entering one mat, start + // to consider the inrisetime from + // 0(0 is passed from outside) + + // matchline ops delay + delay_matchchline += sl_data_drv->delay; + + /* second stage, from the trasistors in the comparators(both normal row and + * dummy row) to the NAND gates that combins both half*/ + // matchline delay, matchline power, matchline_reset for cycle time + // computation, + + ////matchline precharge circuitry routes vertically + // There are two matchline precharge driver chains per subarray. + driver_c_gate_load = (subarray.num_rows + 1) * gate_C(Wfaprechp, 0, is_dram); + driver_c_wire_load = (subarray.num_rows + 1) * c_searchline_metal; + driver_r_wire_load = (subarray.num_rows + 1) * r_searchline_metal; + + ml_precharge_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + ml_precharge_drv->compute_delay(0); + + rd = tr_R_on(Wdummyn, NCH, 2, is_dram); + c_intrinsic = + Htagbits * + (2 * drain_C_(Wdummyn, NCH, 2, 1, g_tp.cell_h_def, + is_dram) // TODO: the cell_h_def should be revisit + + drain_C_(Wfaprechp, PCH, 1, 1, g_tp.cell_h_def, is_dram) / + Htagbits); // since each halve only has one precharge tx per + // matchline + + Cwire = c_matchline_metal * Htagbits; + Rwire = r_matchline_metal * Htagbits; + c_gate_load = gate_C(Waddrnandn + Waddrnandp, 0, is_dram); + + double R_ml_precharge = tr_R_on(Wfaprechp, PCH, 1, is_dram); + // double r_ml_metal = cam_cell.w * g_tp.wire_local.R_per_um; + double R_ml = Rwire; + double C_ml = Cwire + c_intrinsic; + delay_cam_ml_reset = + ml_precharge_drv->delay + + log(g_tp.cam.Vbitpre) * + (R_ml_precharge * C_ml + + R_ml * C_ml / + 2); // TODO: latest CAM has sense amps on matchlines too + + // matchline ops delay + tf = rd * (c_intrinsic + Cwire / 2 + c_gate_load) + + Rwire * (Cwire / 2 + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, VTHFA2, VTHFA3, FALL); + delay_matchchline += this_delay; + out_time_ramp = this_delay / VTHFA3; + + dynSearchEng += + ((c_intrinsic + Cwire + c_gate_load) * + (subarray.num_rows + 1)) //+ 2*drain_C_(Wdummyn, NCH, 2, 1, + // g_tp.cell_h_def, is_dram))//TODO: + // need to be precise + * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * + 2; //* Ntbl;//each subarry has two halves + + /* third stage, from the NAND2 gates to the drivers in the dummy row */ + rd = tr_R_on(Waddrnandn, NCH, 2, is_dram); + c_intrinsic = drain_C_(Waddrnandn, NCH, 2, 1, g_tp.cell_h_def, is_dram) + + drain_C_(Waddrnandp, PCH, 1, 1, g_tp.cell_h_def, is_dram) * 2; + c_gate_load = gate_C(Wdummyinvn + Wdummyinvp, 0, is_dram); + tf = rd * (c_intrinsic + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, VTHFA3, VTHFA4, RISE); + out_time_ramp = this_delay / (1 - VTHFA4); + delay_matchchline += this_delay; + + // only the dummy row has the extra inverter between NAND and NOR gates + dynSearchEng += (c_intrinsic * (subarray.num_rows + 1) + c_gate_load * 2) * + g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; // * Ntbl; + + /* fourth stage, from the driver in dummy matchline to the NOR2 gate which + * drives the wordline of the data portion */ + rd = tr_R_on(Wdummyinvn, NCH, 1, is_dram); + c_intrinsic = drain_C_(Wdummyinvn, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(Wdummyinvp, NCH, 1, 1, g_tp.cell_h_def, is_dram); + Cwire = c_matchline_metal * Htagbits + + c_searchline_metal * (subarray.num_rows + 1) / 2; + Rwire = r_matchline_metal * Htagbits + + r_searchline_metal * (subarray.num_rows + 1) / 2; + c_gate_load = gate_C(Wfanorn + Wfanorp, 0, is_dram); + tf = rd * (c_intrinsic + Cwire + c_gate_load) + + Rwire * (Cwire / 2 + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, VTHFA4, VTHFA5, FALL); + out_time_ramp = this_delay / VTHFA5; + delay_matchchline += this_delay; + + dynSearchEng += (c_intrinsic + Cwire + subarray.num_rows * c_gate_load) * + g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; //* Ntbl; + + /*final statge from the NOR gate to drive the wordline of the data portion */ + + // searchline data driver There are two matchline precharge driver chains per + // subarray. + driver_c_gate_load = gate_C(W_hit_miss_n, 0, is_dram, false, + false); // nmos of the pull down logic + driver_c_wire_load = subarray.C_wl_ram; + driver_r_wire_load = subarray.R_wl_ram; + + ml_to_ram_wl_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + rd = tr_R_on(Wfanorn, NCH, 1, is_dram); + c_intrinsic = 2 * drain_C_(Wfanorn, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(Wfanorp, NCH, 1, 1, g_tp.cell_h_def, is_dram); + c_gate_load = gate_C( + ml_to_ram_wl_drv->width_n[0] + ml_to_ram_wl_drv->width_p[0], 0, is_dram); + tf = rd * (c_intrinsic + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, 0.5, 0.5, RISE); + out_time_ramp = this_delay / (1 - 0.5); + delay_matchchline += this_delay; + + out_time_ramp = ml_to_ram_wl_drv->compute_delay(out_time_ramp); + + // c_gate_load energy is computed in ml_to_ram_wl_drv + dynSearchEng += + (c_intrinsic)*g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; //* Ntbl; + + /* peripheral-- hitting logic "CMOS VLSI Design Fig11.51*/ + /*Precharge the hitting logic */ + c_intrinsic = 2 * drain_C_(W_hit_miss_p, NCH, 2, 1, g_tp.cell_h_def, is_dram); + Cwire = c_searchline_metal * subarray.num_rows; + Rwire = r_searchline_metal * subarray.num_rows; + c_gate_load = drain_C_(W_hit_miss_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) * + subarray.num_rows; + + rd = tr_R_on(W_hit_miss_p, PCH, 1, is_dram, false, false); + // double r_ml_metal = cam_cell.w * g_tp.wire_local.R_per_um; + double R_hit_miss = Rwire; + double C_hit_miss = Cwire + c_intrinsic; + delay_hit_miss_reset = + log(g_tp.cam.Vbitpre) * (rd * C_hit_miss + R_hit_miss * C_hit_miss / 2); + dynSearchEng += (c_intrinsic + Cwire + c_gate_load) * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd; + + /*hitting logic evaluation */ + c_intrinsic = 2 * drain_C_(W_hit_miss_n, NCH, 2, 1, g_tp.cell_h_def, is_dram); + Cwire = c_searchline_metal * subarray.num_rows; + Rwire = r_searchline_metal * subarray.num_rows; + c_gate_load = drain_C_(W_hit_miss_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) * + subarray.num_rows; + + rd = tr_R_on(W_hit_miss_n, PCH, 1, is_dram, false, false); + tf = rd * (c_intrinsic + Cwire / 2 + c_gate_load) + + Rwire * (Cwire / 2 + c_gate_load); + + delay_hit_miss = horowitz(0, tf, 0.5, 0.5, FALL); + + if (is_fa) + delay_matchchline += MAX(ml_to_ram_wl_drv->delay, delay_hit_miss); + + dynSearchEng += (c_intrinsic + Cwire + c_gate_load) * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd; + + /* TODO: peripheral-- Priority Encoder, usually this is not necessary in + * processor components*/ + + power_matchline.searchOp.dynamic = dynSearchEng; + + // leakage in one subarray + double Iport = + cmos_Isub_leakage(g_tp.cam.cell_a_w, 0, 1, nmos, false, + true); // TODO: how much is the idle time? just by *2? + double Iport_erp = + cmos_Isub_leakage(g_tp.cam.cell_a_w, 0, 2, nmos, false, true); + double Icell = cmos_Isub_leakage(g_tp.cam.cell_nmos_w, g_tp.cam.cell_pmos_w, + 1, inv, false, true) * + 2; + double Icell_comparator = + cmos_Isub_leakage(Wdummyn, Wdummyn, 1, inv, false, true) * + 2; // approx XOR with Inv + + leak_power_cc_inverters_sram_cell = Icell * g_tp.cam_cell.Vdd; + leak_comparator_cam_cell = Icell_comparator * g_tp.cam_cell.Vdd; + leak_power_acc_tr_RW_or_WR_port_sram_cell = Iport * g_tp.cam_cell.Vdd; + leak_power_RD_port_sram_cell = Iport_erp * g_tp.cam_cell.Vdd; + leak_power_SCHP_port_sram_cell = + 0; // search port and r/w port are sperate, + // therefore no access txs in search ports + + power_matchline.searchOp.leakage += + leak_power_cc_inverters_sram_cell + leak_comparator_cam_cell + + leak_power_acc_tr_RW_or_WR_port_sram_cell + + leak_power_acc_tr_RW_or_WR_port_sram_cell * (RWP + EWP - 1) + + leak_power_RD_port_sram_cell * ERP + + leak_power_SCHP_port_sram_cell * SCHP; + // power_matchline.searchOp.leakage += leak_comparator_cam_cell; + power_matchline.searchOp.leakage *= + (subarray.num_rows + 1) * + subarray.num_cols_fa_cam; // TODO:dumy line precise + power_matchline.searchOp.leakage += (subarray.num_rows + 1) * + cmos_Isub_leakage(0, Wfaprechp, 1, pmos) * + g_tp.cam_cell.Vdd; + power_matchline.searchOp.leakage += + (subarray.num_rows + 1) * + cmos_Isub_leakage(Waddrnandn, Waddrnandp, 2, nand) * g_tp.cam_cell.Vdd; + power_matchline.searchOp.leakage += + (subarray.num_rows + 1) * cmos_Isub_leakage(Wfanorn, Wfanorp, 2, nor) * + g_tp.cam_cell.Vdd; + // In idle states, the hit/miss txs are closed (on) therefore no Isub + power_matchline.searchOp.leakage += + 0; // subarray.num_rows * cmos_Isub_leakage(W_hit_miss_n, 0,1, nmos) * + // g_tp.cam_cell.Vdd+ + // + cmos_Isub_leakage(0, W_hit_miss_p,1, pmos) * g_tp.cam_cell.Vdd; + + // in idle state, Ig_on only possibly exist in access transistors of read only + // ports + double Ig_port_erp = + cmos_Ig_leakage(g_tp.cam.cell_a_w, 0, 1, nmos, false, true); + double Ig_cell = cmos_Ig_leakage(g_tp.cam.cell_nmos_w, g_tp.cam.cell_pmos_w, + 1, inv, false, true) * + 2; + double Ig_cell_comparator = + cmos_Ig_leakage(Wdummyn, Wdummyn, 1, inv, false, true) * + 2; // cmos_Ig_leakage(Wdummyn, 0, 2, nmos)*2; + + gate_leak_comparator_cam_cell = Ig_cell_comparator * g_tp.cam_cell.Vdd; + gate_leak_power_cc_inverters_sram_cell = Ig_cell * g_tp.cam_cell.Vdd; + gate_leak_power_RD_port_sram_cell = Ig_port_erp * g_tp.sram_cell.Vdd; + gate_leak_power_SCHP_port_sram_cell = 0; + + // cout<<"power_matchline.searchOp.leakage"<array_power_gated? g_tp.sram_cell.Vcc_min : + // g_tp.sram_cell.Vdd); leak_power_acc_tr_RW_or_WR_port_sram_cell = Iport + // * (g_ip->bitline_floating? g_tp.sram.Vbitfloating : + // g_tp.sram_cell.Vdd); leak_power_RD_port_sram_cell = + // Iport_erp * (g_ip->bitline_floating? g_tp.sram.Vbitfloating : + // g_tp.sram_cell.Vdd); + + leak_power_cc_inverters_sram_cell_gated = Icell * g_tp.sram_cell.Vcc_min; + leak_power_acc_tr_RW_or_WR_port_sram_cell_gated = + Iport * g_tp.sram.Vbitfloating; + leak_power_RD_port_sram_cell_gated = Iport_erp * g_tp.sram.Vbitfloating; + // + // leak_power_cc_inverters_sram_cell_gated = + // leak_power_cc_inverters_sram_cell/g_tp.sram_cell.Vdd*g_tp.sram_cell.Vcc_min; + // leak_power_acc_tr_RW_or_WR_port_sram_cell_floating = + // leak_power_acc_tr_RW_or_WR_port_sram_cell/g_tp.sram_cell.Vdd*g_tp.sram.Vbitfloating; + // leak_power_RD_port_sram_cell_floating = + // leak_power_RD_port_sram_cell_floating/g_tp.sram_cell.Vdd*g_tp.sram.Vbitfloating; + // + + // in idle state, Ig_on only possibly exist in access transistors of read + // only ports + double Ig_port_erp = + cmos_Ig_leakage(g_tp.sram.cell_a_w, 0, 1, nmos, false, true); + double Ig_cell = cmos_Ig_leakage( + g_tp.sram.cell_nmos_w, g_tp.sram.cell_pmos_w, 1, inv, false, true); + + gate_leak_power_cc_inverters_sram_cell = Ig_cell * g_tp.sram_cell.Vdd; + gate_leak_power_RD_port_sram_cell = Ig_port_erp * g_tp.sram_cell.Vdd; + } + + double C_drain_bit_mux = drain_C_( + g_tp.w_nmos_b_mux, NCH, 1, 0, + camFlag ? cam_cell.w : cell.w / (2 * (RWP + ERP + SCHP)), is_dram); + double R_bit_mux = tr_R_on(g_tp.w_nmos_b_mux, NCH, 1, is_dram); + double C_drain_sense_amp_iso = drain_C_( + g_tp.w_iso, PCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram); + double R_sense_amp_iso = tr_R_on(g_tp.w_iso, PCH, 1, is_dram); + double C_sense_amp_latch = + gate_C(g_tp.w_sense_p + g_tp.w_sense_n, 0, is_dram) + + drain_C_( + g_tp.w_sense_n, NCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram) + + drain_C_( + g_tp.w_sense_p, PCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram); + double C_drain_sense_amp_mux = drain_C_( + g_tp.w_nmos_sa_mux, NCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram); + + if (is_dram) { + double fraction = + dp.V_b_sense / ((g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_C / + (g_tp.dram_cell_C + C_bl)); + tstep = 2.3 * fraction * r_dev * + (g_tp.dram_cell_C * (C_bl + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux)) / + (g_tp.dram_cell_C + (C_bl + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux)); + delay_writeback = tstep; + dynRdEnergy += + (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + (g_tp.dram_cell_Vdd / 2) * + g_tp.dram_cell_Vdd /* subarray.num_cols * num_subarrays_per_mat*/; + dynWriteEnergy += + (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch) * + (g_tp.dram_cell_Vdd / 2) * + g_tp.dram_cell_Vdd /* subarray.num_cols * num_subarrays_per_mat*/ * + num_act_mats_hor_dir * 100; + per_bitline_read_energy = (C_bl + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) * + (g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_Vdd; + } + else { + double tau; + + if (deg_bl_muxing > 1) { + tau = (R_cell_pull_down + R_cell_acc) * + (C_bl + 2 * C_drain_bit_mux + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) + + R_bl * (C_bl / 2 + 2 * C_drain_bit_mux + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) + + R_bit_mux * (C_drain_bit_mux + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) + + R_sense_amp_iso * (C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux); + dynRdEnergy += (C_bl + 2 * C_drain_bit_mux) * 2 * dp.V_b_sense * + g_tp.sram_cell.Vdd /* + subarray.num_cols * num_subarrays_per_mat*/ + ; + blfloating_c += (C_bl + 2 * C_drain_bit_mux) * 2; + dynRdEnergy += + (2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2 * dp.V_b_sense * g_tp.sram_cell.Vdd * + (1.0 /*subarray.num_cols * num_subarrays_per_mat*/ / deg_bl_muxing); + blfloating_c += (2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2; + dynWriteEnergy += + ((1.0 /*subarray.num_cols *num_subarrays_per_mat*/ / deg_bl_muxing) / + deg_senseamp_muxing) * + num_act_mats_hor_dir * (C_bl + 2 * C_drain_bit_mux) * + g_tp.sram_cell.Vdd * g_tp.sram_cell.Vdd * 2; + // Write Ops are differential for SRAM + } + else { + tau = (R_cell_pull_down + R_cell_acc) * + (C_bl + C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) + + R_bl * C_bl / 2 + + R_sense_amp_iso * (C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux); + dynRdEnergy += + (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2 * dp.V_b_sense * + g_tp.sram_cell.Vdd /* subarray.num_cols * num_subarrays_per_mat*/; + + blfloating_c += (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2; + dynWriteEnergy += (((1.0 /*subarray.num_cols * num_subarrays_per_mat*/ / + deg_bl_muxing) / + deg_senseamp_muxing) * + num_act_mats_hor_dir * C_bl) * + g_tp.sram_cell.Vdd * g_tp.sram_cell.Vdd * 2; + } + tstep = tau * log(V_b_pre / (V_b_pre - dp.V_b_sense)); + // cout<<"R_cell_pull_down ="<repeater_size * g_tp.min_w_nmos_ * (1 + + // p_to_n_sz_r), 0.0, is_dram); + gate_C(subarray_out_wire->repeater_size * + (subarray_out_wire->wire_length / + subarray_out_wire->repeater_spacing) * + g_tp.min_w_nmos_ * (1 + p_to_n_sz_r), + 0.0, is_dram); + tf = rd * C_ld; + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay_subarray_out_drv += this_delay; + inrisetime = this_delay / (1.0 - 0.5); + power_subarray_out_drv.readOp.dynamic += + C_ld * 0.5 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + power_subarray_out_drv.readOp.leakage += + 0; // for now, let leakage of the pass transistor be 0 + power_subarray_out_drv.readOp.power_gated_leakage += 0; + power_subarray_out_drv.readOp.gate_leakage += + cmos_Ig_leakage(g_tp.w_nmos_sa_mux, 0, 1, nmos) * g_tp.peri_global.Vdd; + + return inrisetime; +} + +double Mat::compute_comparator_delay(double inrisetime) { + int A = g_ip->tag_assoc; + + int tagbits_ = + dp.tagbits / + 4; // Assuming there are 4 quarter comparators. input tagbits is already + // a multiple of 4. + + /* First Inverter */ + double Ceq = + gate_C(g_tp.w_comp_inv_n2 + g_tp.w_comp_inv_p2, 0, is_dram) + + drain_C_(g_tp.w_comp_inv_p1, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_inv_n1, NCH, 1, 1, g_tp.cell_h_def, is_dram); + double Req = tr_R_on(g_tp.w_comp_inv_p1, PCH, 1, is_dram); + double tf = Req * Ceq; + double st1del = horowitz(inrisetime, tf, VTHCOMPINV, VTHCOMPINV, FALL); + double nextinputtime = st1del / VTHCOMPINV; + power_comparator.readOp.dynamic += + 0.5 * Ceq * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + + // For each degree of associativity + // there are 4 such quarter comparators + double lkgCurrent = cmos_Isub_leakage(g_tp.w_comp_inv_n1, g_tp.w_comp_inv_p1, + 1, inv, is_dram) * + 4 * A; + double gatelkgCurrent = + cmos_Ig_leakage(g_tp.w_comp_inv_n1, g_tp.w_comp_inv_p1, 1, inv, is_dram) * + 4 * A; + /* Second Inverter */ + Ceq = gate_C(g_tp.w_comp_inv_n3 + g_tp.w_comp_inv_p3, 0, is_dram) + + drain_C_(g_tp.w_comp_inv_p2, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_inv_n2, NCH, 1, 1, g_tp.cell_h_def, is_dram); + Req = tr_R_on(g_tp.w_comp_inv_n2, NCH, 1, is_dram); + tf = Req * Ceq; + double st2del = horowitz(nextinputtime, tf, VTHCOMPINV, VTHCOMPINV, RISE); + nextinputtime = st2del / (1.0 - VTHCOMPINV); + power_comparator.readOp.dynamic += + 0.5 * Ceq * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + lkgCurrent += cmos_Isub_leakage(g_tp.w_comp_inv_n2, g_tp.w_comp_inv_p2, 1, + inv, is_dram) * + 4 * A; + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_comp_inv_n2, g_tp.w_comp_inv_p2, 1, inv, is_dram) * + 4 * A; + + /* Third Inverter */ + Ceq = gate_C(g_tp.w_eval_inv_n + g_tp.w_eval_inv_p, 0, is_dram) + + drain_C_(g_tp.w_comp_inv_p3, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_inv_n3, NCH, 1, 1, g_tp.cell_h_def, is_dram); + Req = tr_R_on(g_tp.w_comp_inv_p3, PCH, 1, is_dram); + tf = Req * Ceq; + double st3del = horowitz(nextinputtime, tf, VTHCOMPINV, VTHEVALINV, FALL); + nextinputtime = st3del / (VTHEVALINV); + power_comparator.readOp.dynamic += + 0.5 * Ceq * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + lkgCurrent += cmos_Isub_leakage(g_tp.w_comp_inv_n3, g_tp.w_comp_inv_p3, 1, + inv, is_dram) * + 4 * A; + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_comp_inv_n3, g_tp.w_comp_inv_p3, 1, inv, is_dram) * + 4 * A; + + /* Final Inverter (virtual ground driver) discharging compare part */ + double r1 = tr_R_on(g_tp.w_comp_n, NCH, 2, is_dram); + double r2 = tr_R_on(g_tp.w_eval_inv_n, NCH, 1, is_dram); /* was switch */ + double c2 = + (tagbits_) * + (drain_C_(g_tp.w_comp_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_n, NCH, 2, 1, g_tp.cell_h_def, is_dram)) + + drain_C_(g_tp.w_eval_inv_p, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_eval_inv_n, NCH, 1, 1, g_tp.cell_h_def, is_dram); + double c1 = + (tagbits_) * + (drain_C_(g_tp.w_comp_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_n, NCH, 2, 1, g_tp.cell_h_def, is_dram)) + + drain_C_(g_tp.w_comp_p, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + gate_C(WmuxdrvNANDn + WmuxdrvNANDp, 0, is_dram); + power_comparator.readOp.dynamic += + 0.5 * c2 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + power_comparator.readOp.dynamic += + c1 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * (A - 1); + lkgCurrent += + cmos_Isub_leakage(g_tp.w_eval_inv_n, g_tp.w_eval_inv_p, 1, inv, is_dram) * + 4 * A; + lkgCurrent += + cmos_Isub_leakage(g_tp.w_comp_n, g_tp.w_comp_n, 1, inv, is_dram) * 4 * + A; // stack factor of 0.2 + + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_eval_inv_n, g_tp.w_eval_inv_p, 1, inv, is_dram) * + 4 * A; + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_comp_n, g_tp.w_comp_n, 1, inv, is_dram) * 4 * + A; // for gate leakage this equals to a inverter + + /* time to go to threshold of mux driver */ + double tstep = (r2 * c2 + (r1 + r2) * c1) * log(1.0 / VTHMUXNAND); + /* take into account non-zero input rise time */ + double m = g_tp.peri_global.Vdd / nextinputtime; + double Tcomparatorni; + + if ((tstep) <= (0.5 * (g_tp.peri_global.Vdd - g_tp.peri_global.Vth) / m)) { + double a = m; + double b = 2 * ((g_tp.peri_global.Vdd * VTHEVALINV) - g_tp.peri_global.Vth); + double c = + -2 * (tstep) * (g_tp.peri_global.Vdd - g_tp.peri_global.Vth) + + 1 / m * ((g_tp.peri_global.Vdd * VTHEVALINV) - g_tp.peri_global.Vth) * + ((g_tp.peri_global.Vdd * VTHEVALINV) - g_tp.peri_global.Vth); + Tcomparatorni = (-b + sqrt(b * b - 4 * a * c)) / (2 * a); + } + else { + Tcomparatorni = (tstep) + + (g_tp.peri_global.Vdd + g_tp.peri_global.Vth) / (2 * m) - + (g_tp.peri_global.Vdd * VTHEVALINV) / m; + } + delay_comparator = Tcomparatorni + st1del + st2del + st3del; + power_comparator.readOp.leakage = lkgCurrent * g_tp.peri_global.Vdd; + power_comparator.readOp.power_gated_leakage = + lkgCurrent * g_tp.peri_global.Vcc_min; + power_comparator.readOp.gate_leakage = gatelkgCurrent * g_tp.peri_global.Vdd; + + return Tcomparatorni / (1.0 - VTHMUXNAND); + ; +} + +void Mat::compute_power_energy() { + // for cam and FA, power.readOp is the plain read power, power.searchOp is the + // associative search related power + // when search all subarrays and all mats are fully active + // when plain read/write only one subarray in a single mat is active. + + // add energy consumed in predecoder drivers. This unit is shared by all + // subarrays in a mat. + power.readOp.dynamic += r_predec->power.readOp.dynamic + + b_mux_predec->power.readOp.dynamic + + sa_mux_lev_1_predec->power.readOp.dynamic + + sa_mux_lev_2_predec->power.readOp.dynamic; + + // add energy consumed in decoders + power_row_decoders.readOp.dynamic = row_dec->power.readOp.dynamic; + if (!(is_fa || pure_cam)) + power_row_decoders.readOp.dynamic *= num_subarrays_per_mat; + + // add energy consumed in bitline prechagers, SAs, and bitlines + if (!(is_fa || pure_cam)) { + // add energy consumed in bitline prechagers + power_bl_precharge_eq_drv.readOp.dynamic = + bl_precharge_eq_drv->power.readOp.dynamic; + power_bl_precharge_eq_drv.readOp.dynamic *= num_subarrays_per_mat; + + // Add sense amps energy + num_sa_subarray = subarray.num_cols / deg_bl_muxing; + power_sa.readOp.dynamic *= num_sa_subarray * num_subarrays_per_mat; + + // add energy consumed in bitlines + // cout<<"bitline power"<power.readOp.dynamic) * + num_do_b_mat; + + power.readOp.dynamic += + power_bl_precharge_eq_drv.readOp.dynamic + power_sa.readOp.dynamic + + power_bitline.readOp.dynamic + power_subarray_out_drv.readOp.dynamic; + + power.readOp.dynamic += power_row_decoders.readOp.dynamic + + bit_mux_dec->power.readOp.dynamic + + sa_mux_lev_1_dec->power.readOp.dynamic + + sa_mux_lev_2_dec->power.readOp.dynamic + + power_comparator.readOp.dynamic; + } + + else if (is_fa) { + // for plain read/write only one subarray in a mat is active + // add energy consumed in bitline prechagers + power_bl_precharge_eq_drv.readOp.dynamic = + bl_precharge_eq_drv->power.readOp.dynamic + + cam_bl_precharge_eq_drv->power.readOp.dynamic; + power_bl_precharge_eq_drv.searchOp.dynamic = + bl_precharge_eq_drv->power.readOp.dynamic; + + // Add sense amps energy + num_sa_subarray = + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram) / deg_bl_muxing; + num_sa_subarray_search = subarray.num_cols_fa_ram / deg_bl_muxing; + power_sa.searchOp.dynamic = + power_sa.readOp.dynamic * num_sa_subarray_search; + power_sa.readOp.dynamic *= num_sa_subarray; + + // add energy consumed in bitlines + power_bitline.searchOp.dynamic = power_bitline.readOp.dynamic; + power_bitline.readOp.dynamic *= + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram); + power_bitline.writeOp.dynamic *= + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram); + power_bitline.searchOp.dynamic *= subarray.num_cols_fa_ram; + + // Add subarray output energy + power_subarray_out_drv.searchOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_so_b_mat; + power_subarray_out_drv.readOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_do_b_mat; + + power.readOp.dynamic += + power_bl_precharge_eq_drv.readOp.dynamic + power_sa.readOp.dynamic + + power_bitline.readOp.dynamic + power_subarray_out_drv.readOp.dynamic; + + power.readOp.dynamic += power_row_decoders.readOp.dynamic + + bit_mux_dec->power.readOp.dynamic + + sa_mux_lev_1_dec->power.readOp.dynamic + + sa_mux_lev_2_dec->power.readOp.dynamic + + power_comparator.readOp.dynamic; + + // add energy consumed inside cam + power_matchline.searchOp.dynamic *= num_subarrays_per_mat; + power_searchline_precharge = sl_precharge_eq_drv->power; + power_searchline_precharge.searchOp.dynamic = + power_searchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_searchline = sl_data_drv->power; + power_searchline.searchOp.dynamic = power_searchline.readOp.dynamic * + subarray.num_cols_fa_cam * + num_subarrays_per_mat; + ; + power_matchline_precharge = ml_precharge_drv->power; + power_matchline_precharge.searchOp.dynamic = + power_matchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_ml_to_ram_wl_drv = ml_to_ram_wl_drv->power; + power_ml_to_ram_wl_drv.searchOp.dynamic = + ml_to_ram_wl_drv->power.readOp.dynamic; + + power_cam_all_active.searchOp.dynamic = power_matchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_searchline_precharge.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += power_searchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_matchline_precharge.searchOp.dynamic; + + power.searchOp.dynamic += power_cam_all_active.searchOp.dynamic; + // power.searchOp.dynamic += ml_to_ram_wl_drv->power.readOp.dynamic; + } + else { + // add energy consumed in bitline prechagers + power_bl_precharge_eq_drv.readOp.dynamic = + cam_bl_precharge_eq_drv->power.readOp.dynamic; + // power_bl_precharge_eq_drv.readOp.dynamic *= num_subarrays_per_mat; + // power_bl_precharge_eq_drv.searchOp.dynamic = + // cam_bl_precharge_eq_drv->power.readOp.dynamic; + // power_bl_precharge_eq_drv.searchOp.dynamic *= num_subarrays_per_mat; + + // Add sense amps energy + num_sa_subarray = subarray.num_cols_fa_cam / deg_bl_muxing; + power_sa.readOp.dynamic *= num_sa_subarray; //*num_subarrays_per_mat; + power_sa.searchOp.dynamic = 0; + + power_bitline.readOp.dynamic *= subarray.num_cols_fa_cam; + power_bitline.searchOp.dynamic = 0; + power_bitline.writeOp.dynamic *= subarray.num_cols_fa_cam; + + power_subarray_out_drv.searchOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_so_b_mat; + power_subarray_out_drv.readOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_do_b_mat; + + power.readOp.dynamic += + power_bl_precharge_eq_drv.readOp.dynamic + power_sa.readOp.dynamic + + power_bitline.readOp.dynamic + power_subarray_out_drv.readOp.dynamic; + + power.readOp.dynamic += power_row_decoders.readOp.dynamic + + bit_mux_dec->power.readOp.dynamic + + sa_mux_lev_1_dec->power.readOp.dynamic + + sa_mux_lev_2_dec->power.readOp.dynamic + + power_comparator.readOp.dynamic; + + ////add energy consumed inside cam + power_matchline.searchOp.dynamic *= num_subarrays_per_mat; + power_searchline_precharge = sl_precharge_eq_drv->power; + power_searchline_precharge.searchOp.dynamic = + power_searchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_searchline = sl_data_drv->power; + power_searchline.searchOp.dynamic = power_searchline.readOp.dynamic * + subarray.num_cols_fa_cam * + num_subarrays_per_mat; + ; + power_matchline_precharge = ml_precharge_drv->power; + power_matchline_precharge.searchOp.dynamic = + power_matchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_ml_to_ram_wl_drv = ml_to_ram_wl_drv->power; + power_ml_to_ram_wl_drv.searchOp.dynamic = + ml_to_ram_wl_drv->power.readOp.dynamic; + + power_cam_all_active.searchOp.dynamic = power_matchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_searchline_precharge.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += power_searchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_matchline_precharge.searchOp.dynamic; + + power.searchOp.dynamic += power_cam_all_active.searchOp.dynamic; + // power.searchOp.dynamic += ml_to_ram_wl_drv->power.readOp.dynamic; + } + + int number_output_drivers_subarray; + // // calculate leakage power + if (!(is_fa || pure_cam)) { + number_output_drivers_subarray = + num_sa_subarray / (dp.Ndsam_lev_1 * dp.Ndsam_lev_2); + + power_bitline.readOp.leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bitline.readOp.power_gated_leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bl_precharge_eq_drv.readOp.leakage = + bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + // bl precharge drv is not power gated to turn off the precharge and + // equalization circuit (PMOS, thus turn-off signal is "1") for bitline + // floating + power_bl_precharge_eq_drv.readOp.power_gated_leakage = + bl_precharge_eq_drv->power.readOp.power_gated_leakage * + num_subarrays_per_mat; + power_sa.readOp.leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP); + + // num_sa_subarray = subarray.num_cols / deg_bl_muxing; + power_subarray_out_drv.readOp.leakage = + (power_subarray_out_drv.readOp.leakage + + subarray_out_wire->power.readOp.leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * (RWP + ERP); + + power_subarray_out_drv.readOp.power_gated_leakage = + (power_subarray_out_drv.readOp.power_gated_leakage + + subarray_out_wire->power.readOp.power_gated_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * (RWP + ERP); + + power.readOp.leakage += power_bitline.readOp.leakage + + power_bl_precharge_eq_drv.readOp.leakage + + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage; + + power.readOp.power_gated_leakage += + power_bitline.readOp.power_gated_leakage + + power_bl_precharge_eq_drv.readOp.power_gated_leakage + + power_sa.readOp.power_gated_leakage + + power_subarray_out_drv.readOp.power_gated_leakage; + + power_comparator.readOp.leakage *= num_do_b_mat * (RWP + ERP); + power.readOp.leakage += power_comparator.readOp.leakage; + + power_comparator.readOp.power_gated_leakage *= num_do_b_mat * (RWP + ERP); + power.readOp.power_gated_leakage += + power_comparator.readOp.power_gated_leakage; + + array_leakage = power_bitline.readOp.leakage; + + cl_leakage = + power_bl_precharge_eq_drv.readOp.leakage + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage + power_comparator.readOp.leakage; + + // Decoder blocks + power_row_decoders.readOp.leakage = row_dec->power.readOp.leakage * + subarray.num_rows * + num_subarrays_per_mat; + power_bit_mux_decoders.readOp.leakage = + bit_mux_dec->power.readOp.leakage * deg_bl_muxing; + power_sa_mux_lev_1_decoders.readOp.leakage = + sa_mux_lev_1_dec->power.readOp.leakage * dp.Ndsam_lev_1; + power_sa_mux_lev_2_decoders.readOp.leakage = + sa_mux_lev_2_dec->power.readOp.leakage * dp.Ndsam_lev_2; + + power_row_decoders.readOp.power_gated_leakage = + row_dec->power.readOp.power_gated_leakage * subarray.num_rows * + num_subarrays_per_mat; + power_bit_mux_decoders.readOp.power_gated_leakage = + bit_mux_dec->power.readOp.power_gated_leakage * deg_bl_muxing; + power_sa_mux_lev_1_decoders.readOp.power_gated_leakage = + sa_mux_lev_1_dec->power.readOp.power_gated_leakage * dp.Ndsam_lev_1; + power_sa_mux_lev_2_decoders.readOp.power_gated_leakage = + sa_mux_lev_2_dec->power.readOp.power_gated_leakage * dp.Ndsam_lev_2; + + // if (!g_ip->wl_power_gated) + // { + power.readOp.leakage += r_predec->power.readOp.leakage + + b_mux_predec->power.readOp.leakage + + sa_mux_lev_1_predec->power.readOp.leakage + + sa_mux_lev_2_predec->power.readOp.leakage + + power_row_decoders.readOp.leakage + + power_bit_mux_decoders.readOp.leakage + + power_sa_mux_lev_1_decoders.readOp.leakage + + power_sa_mux_lev_2_decoders.readOp.leakage; + + power.readOp.power_gated_leakage += + r_predec->power.readOp.power_gated_leakage + + b_mux_predec->power.readOp.power_gated_leakage + + sa_mux_lev_1_predec->power.readOp.power_gated_leakage + + sa_mux_lev_2_predec->power.readOp.power_gated_leakage + + power_row_decoders.readOp.power_gated_leakage + + power_bit_mux_decoders.readOp.power_gated_leakage + + power_sa_mux_lev_1_decoders.readOp.power_gated_leakage + + power_sa_mux_lev_2_decoders.readOp.power_gated_leakage; + + // } + // else + // { + // power.readOp.power_gated_leakage += + // (r_predec->power.readOp.leakage + + // + // b_mux_predec->power.readOp.leakage + + // sa_mux_lev_1_predec->power.readOp.leakage + + // sa_mux_lev_2_predec->power.readOp.leakage + + // power_row_decoders.readOp.leakage + + // power_bit_mux_decoders.readOp.leakage + + // power_sa_mux_lev_1_decoders.readOp.leakage + + // power_sa_mux_lev_2_decoders.readOp.leakage)/g_tp.peri_global.Vdd*g_tp.peri_global.Vcc_min; + + // } + + wl_leakage = r_predec->power.readOp.leakage + + b_mux_predec->power.readOp.leakage + + sa_mux_lev_1_predec->power.readOp.leakage + + sa_mux_lev_2_predec->power.readOp.leakage + + power_row_decoders.readOp.leakage + + power_bit_mux_decoders.readOp.leakage + + power_sa_mux_lev_1_decoders.readOp.leakage + + power_sa_mux_lev_2_decoders.readOp.leakage; + + //++++Below is gate leakage + power_bitline.readOp.gate_leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bl_precharge_eq_drv.readOp.gate_leakage = + bl_precharge_eq_drv->power.readOp.gate_leakage * num_subarrays_per_mat; + power_sa.readOp.gate_leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP); + + // num_sa_subarray = subarray.num_cols / deg_bl_muxing; + power_subarray_out_drv.readOp.gate_leakage = + (power_subarray_out_drv.readOp.gate_leakage + + subarray_out_wire->power.readOp.gate_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * (RWP + ERP); + + power.readOp.gate_leakage += power_bitline.readOp.gate_leakage + + power_bl_precharge_eq_drv.readOp.gate_leakage + + power_sa.readOp.gate_leakage + + power_subarray_out_drv.readOp.gate_leakage; + // cout<<"leakage"<power_gating) { + // cout<<"leakage1"<area.get_area() * subarray.num_cols * + num_subarrays_per_mat * dp.num_mats; + array_wakeup_e.readOp.dynamic = + sram_sleep_tx->wakeup_power.readOp.dynamic * num_subarrays_per_mat * + subarray.num_cols * dp.num_act_mats_hor_dir; + array_wakeup_t = sram_sleep_tx->wakeup_delay; + + wl_sleep_tx_area = + (row_dec->exist ? row_dec->sleeptx->area.get_area() : 0) * + subarray.num_rows * num_subarrays_per_mat * dp.num_mats + + (bit_mux_dec->exist ? bit_mux_dec->sleeptx->area.get_area() : 0) * + dp.num_mats + + (sa_mux_lev_1_dec->exist ? sa_mux_lev_1_dec->sleeptx->area.get_area() + : 0) * + dp.num_mats + + (sa_mux_lev_2_dec->exist ? sa_mux_lev_2_dec->sleeptx->area.get_area() + : 0) * + dp.num_mats; + wl_wakeup_e.readOp.dynamic = + (row_dec->exist ? row_dec->sleeptx->wakeup_power.readOp.dynamic : 0) * + num_subarrays_per_mat * subarray.num_rows * + dp.num_act_mats_hor_dir + + (bit_mux_dec->exist + ? bit_mux_dec->sleeptx->wakeup_power.readOp.dynamic + : 0) * + dp.num_mats + + (sa_mux_lev_1_dec->exist + ? sa_mux_lev_1_dec->sleeptx->wakeup_power.readOp.dynamic + : 0) * + dp.num_mats + + (sa_mux_lev_2_dec->exist + ? sa_mux_lev_2_dec->sleeptx->wakeup_power.readOp.dynamic + : 0) * + dp.num_mats; + wl_wakeup_t = + (row_dec->exist ? row_dec->sleeptx->wakeup_delay : 0) + + (bit_mux_dec->exist ? bit_mux_dec->sleeptx->wakeup_delay : 0) * + dp.num_mats + + (sa_mux_lev_1_dec->exist ? sa_mux_lev_1_dec->sleeptx->wakeup_delay + : 0) * + dp.num_mats + + (sa_mux_lev_2_dec->exist ? sa_mux_lev_2_dec->sleeptx->wakeup_delay + : 0) * + dp.num_mats; + ; + } + + // gate_leakage power + power_row_decoders.readOp.gate_leakage = + row_dec->power.readOp.gate_leakage * subarray.num_rows * + num_subarrays_per_mat; + power_bit_mux_decoders.readOp.gate_leakage = + bit_mux_dec->power.readOp.gate_leakage * deg_bl_muxing; + power_sa_mux_lev_1_decoders.readOp.gate_leakage = + sa_mux_lev_1_dec->power.readOp.gate_leakage * dp.Ndsam_lev_1; + power_sa_mux_lev_2_decoders.readOp.gate_leakage = + sa_mux_lev_2_dec->power.readOp.gate_leakage * dp.Ndsam_lev_2; + + power.readOp.gate_leakage += + r_predec->power.readOp.gate_leakage + + b_mux_predec->power.readOp.gate_leakage + + sa_mux_lev_1_predec->power.readOp.gate_leakage + + sa_mux_lev_2_predec->power.readOp.gate_leakage + + power_row_decoders.readOp.gate_leakage + + power_bit_mux_decoders.readOp.gate_leakage + + power_sa_mux_lev_1_decoders.readOp.gate_leakage + + power_sa_mux_lev_2_decoders.readOp.gate_leakage; + } + else if (is_fa) // fully assoc + { + int number_output_drivers_subarray = + num_sa_subarray; // / (dp.Ndsam_lev_1 * dp.Ndsam_lev_2); + + power_bitline.readOp.leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bl_precharge_eq_drv.readOp.leakage = + bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_bl_precharge_eq_drv.searchOp.leakage = + cam_bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_sa.readOp.leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + // cout<<"leakage3"<power.readOp.leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp.leakage += power_bitline.readOp.leakage + + power_bl_precharge_eq_drv.readOp.leakage + + power_bl_precharge_eq_drv.searchOp.leakage + + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage; + + // cout<<"leakage4"<power.readOp.leakage * + subarray.num_rows * + num_subarrays_per_mat; + power.readOp.leakage += + r_predec->power.readOp.leakage + power_row_decoders.readOp.leakage; + + // cout<<"leakage5"<power.readOp.leakage; + power_cam_all_active.searchOp.leakage += + sl_data_drv->power.readOp.leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.leakage *= num_subarrays_per_mat; + + power.readOp.leakage += power_cam_all_active.searchOp.leakage; + + // cout<<"leakage6"<power.readOp.gate_leakage * num_subarrays_per_mat; + power_bl_precharge_eq_drv.searchOp.gate_leakage = + cam_bl_precharge_eq_drv->power.readOp.gate_leakage * + num_subarrays_per_mat; + power_sa.readOp.gate_leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + // cout<<"leakage3"<power.readOp.gate_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp.gate_leakage += + power_bitline.readOp.gate_leakage + + power_bl_precharge_eq_drv.readOp.gate_leakage + + power_bl_precharge_eq_drv.searchOp.gate_leakage + + power_sa.readOp.gate_leakage + + power_subarray_out_drv.readOp.gate_leakage; + + // cout<<"leakage4"<power.readOp.gate_leakage * subarray.num_rows * + num_subarrays_per_mat; + power.readOp.gate_leakage += r_predec->power.readOp.gate_leakage + + power_row_decoders.readOp.gate_leakage; + + // cout<<"leakage5"<power.readOp.gate_leakage; + power_cam_all_active.searchOp.gate_leakage += + sl_data_drv->power.readOp.gate_leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.gate_leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.gate_leakage *= num_subarrays_per_mat; + + power.readOp.gate_leakage += power_cam_all_active.searchOp.gate_leakage; + } + else // pure CAM + { + int number_output_drivers_subarray = + num_sa_subarray; // / (dp.Ndsam_lev_1 * dp.Ndsam_lev_2); + + // power_bitline.readOp.leakage *= subarray.num_rows * + // subarray.num_cols * num_subarrays_per_mat; + // power_bl_precharge_eq_drv.readOp.leakage = + // bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_bl_precharge_eq_drv.searchOp.leakage = + cam_bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_sa.readOp.leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + power_subarray_out_drv.readOp.leakage = + (power_subarray_out_drv.readOp.leakage + + subarray_out_wire->power.readOp.leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp.leakage += // power_bitline.readOp.leakage + + // power_bl_precharge_eq_drv.readOp.leakage + + power_bl_precharge_eq_drv.searchOp.leakage + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage; + + // leakage power + power_row_decoders.readOp.leakage = + row_dec->power.readOp.leakage * subarray.num_rows * + num_subarrays_per_mat * (RWP + ERP + EWP); + power.readOp.leakage += + r_predec->power.readOp.leakage + power_row_decoders.readOp.leakage; + + // inside cam + power_cam_all_active.searchOp.leakage = power_matchline.searchOp.leakage; + power_cam_all_active.searchOp.leakage += + sl_precharge_eq_drv->power.readOp.leakage; + power_cam_all_active.searchOp.leakage += + sl_data_drv->power.readOp.leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.leakage *= num_subarrays_per_mat; + + power.readOp.leakage += power_cam_all_active.searchOp.leakage; + + //+++Below is gate leakage + power_bl_precharge_eq_drv.searchOp.gate_leakage = + cam_bl_precharge_eq_drv->power.readOp.gate_leakage * + num_subarrays_per_mat; + power_sa.readOp.gate_leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + power_subarray_out_drv.readOp.gate_leakage = + (power_subarray_out_drv.readOp.gate_leakage + + subarray_out_wire->power.readOp.gate_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp + .gate_leakage += // power_bitline.readOp.gate_leakage + + // power_bl_precharge_eq_drv.readOp.gate_leakage + + power_bl_precharge_eq_drv.searchOp.gate_leakage + + power_sa.readOp.gate_leakage + + power_subarray_out_drv.readOp.gate_leakage; + + // gate_leakage power + power_row_decoders.readOp.gate_leakage = + row_dec->power.readOp.gate_leakage * subarray.num_rows * + num_subarrays_per_mat * (RWP + ERP + EWP); + power.readOp.gate_leakage += r_predec->power.readOp.gate_leakage + + power_row_decoders.readOp.gate_leakage; + + // inside cam + power_cam_all_active.searchOp.gate_leakage = + power_matchline.searchOp.gate_leakage; + power_cam_all_active.searchOp.gate_leakage += + sl_precharge_eq_drv->power.readOp.gate_leakage; + power_cam_all_active.searchOp.gate_leakage += + sl_data_drv->power.readOp.gate_leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.gate_leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.gate_leakage *= num_subarrays_per_mat; + + power.readOp.gate_leakage += power_cam_all_active.searchOp.gate_leakage; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/mat.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/mat.h new file mode 100644 index 0000000000..e8886bca55 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/mat.h @@ -0,0 +1,173 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __MAT_H__ +#define __MAT_H__ + +#include "component.h" +#include "decoder.h" +#include "powergating.h" +#include "subarray.h" +#include "wire.h" + +namespace cacti { + +class Mat : public Component { + public: + Mat(const DynamicParameter &dyn_p); + ~Mat(); + double compute_delays(double inrisetime); // return outrisetime + void compute_power_energy(); + + const DynamicParameter &dp; + + // TODO: clean up pointers and powerDefs below + Decoder *row_dec; + Decoder *bit_mux_dec; + Decoder *sa_mux_lev_1_dec; + Decoder *sa_mux_lev_2_dec; + PredecBlk *dummy_way_sel_predec_blk1; + PredecBlk *dummy_way_sel_predec_blk2; + PredecBlkDrv *way_sel_drv1; + PredecBlkDrv *dummy_way_sel_predec_blk_drv2; + + Predec *r_predec; + Predec *b_mux_predec; + Predec *sa_mux_lev_1_predec; + Predec *sa_mux_lev_2_predec; + + Wire *subarray_out_wire; + Driver *bl_precharge_eq_drv; + Driver *cam_bl_precharge_eq_drv; // bitline pre-charge circuit is separated + // for CAM and RAM arrays. + Driver *ml_precharge_drv; // matchline prechange driver + Driver *sl_precharge_eq_drv; // searchline prechage driver + Driver *sl_data_drv; // search line data driver + Driver *ml_to_ram_wl_drv; // search line data driver + + powerDef power_row_decoders; + powerDef power_bit_mux_decoders; + powerDef power_sa_mux_lev_1_decoders; + powerDef power_sa_mux_lev_2_decoders; + powerDef power_fa_cam; // TODO: leakage power is not computed yet + powerDef power_bl_precharge_eq_drv; + powerDef power_subarray_out_drv; + powerDef power_cam_all_active; + powerDef power_searchline_precharge; + powerDef power_matchline_precharge; + powerDef power_ml_to_ram_wl_drv; + + double delay_fa_tag, delay_cam; + double delay_before_decoder; + double delay_bitline; + double delay_wl_reset; + double delay_bl_restore; + + double delay_searchline; + double delay_matchchline; + double delay_cam_sl_restore; + double delay_cam_ml_reset; + double delay_fa_ram_wl; + + double delay_hit_miss_reset; + double delay_hit_miss; + + Subarray subarray; + powerDef power_bitline, power_searchline, power_matchline, + power_bitline_gated; + double per_bitline_read_energy; + int deg_bl_muxing; + int num_act_mats_hor_dir; + double delay_writeback; + Area cell, cam_cell; + bool is_dram, is_fa, pure_cam, camFlag; + int num_mats; + powerDef power_sa; + double delay_sa; + double leak_power_sense_amps_closed_page_state; + double leak_power_sense_amps_open_page_state; + double delay_subarray_out_drv; + double delay_subarray_out_drv_htree; + double delay_comparator; + powerDef power_comparator; + int num_do_b_mat; + int num_so_b_mat; + int num_sa_subarray; + int num_sa_subarray_search; + double C_bl; + + uint32_t num_subarrays_per_mat; // the number of subarrays in a mat + uint32_t num_subarrays_per_row; // the number of subarrays in a row of a mat + + double array_leakage; + double wl_leakage; + double cl_leakage; + + Sleep_tx *sram_sleep_tx; + Sleep_tx *wl_sleep_tx; + Sleep_tx *cl_sleep_tx; + + powerDef array_wakeup_e; + double array_wakeup_t; + double array_sleep_tx_area; + + powerDef blfloating_wakeup_e; + double blfloating_wakeup_t; + double blfloating_sleep_tx_area; + + powerDef wl_wakeup_e; + double wl_wakeup_t; + double wl_sleep_tx_area; + + powerDef cl_wakeup_e; + double cl_wakeup_t; + double cl_sleep_tx_area; + + private: + double compute_bit_mux_sa_precharge_sa_mux_wr_drv_wr_mux_h(); + double width_write_driver_or_write_mux(); + double compute_comparators_height(int tagbits, int number_ways_in_mat, + double subarray_mem_cell_area_w); + double compute_cam_delay(double inrisetime); + double compute_bitline_delay(double inrisetime); + double compute_sa_delay(double inrisetime); + double compute_subarray_out_drv(double inrisetime); + double compute_comparator_delay(double inrisetime); + + int RWP; + int ERP; + int EWP; + int SCHP; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/nuca.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/nuca.cc new file mode 100644 index 0000000000..e946bc2cfa --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/nuca.cc @@ -0,0 +1,596 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "nuca.h" +#include +#include "Ucache.h" +using namespace cacti; + +unsigned int MIN_BANKSIZE = 65536; +#define FIXED_OVERHEAD \ + 55e-12 /* clock skew and jitter in s. Ref: Hrishikesh et al ISCA 01 */ +#define LATCH_DELAY 28e-12 /* latch delay in s (later should use FO4 TODO) */ +#define CONTR_2_BANK_LAT 0 + +int cont_stats[2 /*l2 or l3*/][5 /* cores */][ROUTER_TYPES][8 /*banks*/] + [8 /* cycle time */]; + +Nuca::Nuca(TechnologyParameter::DeviceType *dt) + : deviceType(dt) { + init_cont(); +} + +void Nuca::init_cont() { + FILE *cont; + char line[5000]; + char jk[5000]; + cont = fopen("contention.dat", "r"); + if (!cont) { + cout << "contention.dat file is missing!\n"; + exit(0); + } + + for (int i = 0; i < 2; i++) { + for (int j = 2; j < 5; j++) { + for (int k = 0; k < ROUTER_TYPES; k++) { + for (int l = 0; l < 7; l++) { + int *temp = + cont_stats[i /*l2 or l3*/][j /*core*/] + [k /*64 or 128 or 256 link bw*/][l /* no banks*/]; + assert(fscanf(cont, "%[^\n]\n", line) != EOF); + sscanf(line, "%[^:]: %d %d %d %d %d %d %d %d", jk, &temp[0], &temp[1], + &temp[2], &temp[3], &temp[4], &temp[5], &temp[6], &temp[7]); + } + } + } + } + fclose(cont); +} + +void Nuca::print_cont_stats() { + for (int i = 0; i < 2; i++) { + for (int j = 2; j < 5; j++) { + for (int k = 0; k < ROUTER_TYPES; k++) { + for (int l = 0; l < 7; l++) { + for (int m = 0; l < 7; l++) { + cout << cont_stats[i][j][k][l][m] << " "; + } + cout << endl; + } + } + } + } + cout << endl; +} + +Nuca::~Nuca() { + for (int i = wt_min; i <= wt_max; i++) { + delete wire_vertical[i]; + delete wire_horizontal[i]; + } +} + +/* converts latency (in s) to cycles depending upon the FREQUENCY (in GHz) */ +int Nuca::calc_cycles(double lat, double oper_freq) { + // TODO: convert latch delay to FO4 */ + double cycle_time = (1.0 / (oper_freq * 1e9)); /*s*/ + cycle_time -= LATCH_DELAY; + cycle_time -= FIXED_OVERHEAD; + + return (int)ceil(lat / cycle_time); +} + +nuca_org_t::~nuca_org_t() { + // if(h_wire) delete h_wire; + // if(v_wire) delete v_wire; + // if(router) delete router; +} + +/* + * Version - 6.0 + * + * Perform exhaustive search across different bank organizatons, + * router configurations, grid organizations, and wire models and + * find an optimal NUCA organization + * For different bank count values + * 1. Optimal bank organization is calculated + * 2. For each bank organization, find different NUCA organizations + * using various router configurations, grid organizations, + * and wire models. + * 3. NUCA model with the least cost is picked for + * this particular bank count + * Finally include contention statistics and find the optimal + * NUCA configuration + */ +void Nuca::sim_nuca() { + /* temp variables */ + int it, ro, wr; + int num_cyc; + unsigned int i, j; + unsigned int r, c; + int l2_c; + int bank_count = 0; + uca_org_t ures; + nuca_org_t *opt_n; + mem_array tag, data; + list nuca_list; + Router *router_s[ROUTER_TYPES]; + router_s[0] = new Router(64.0, 8, 4, &(g_tp.peri_global)); + router_s[0]->print_router(); + router_s[1] = new Router(128.0, 8, 4, &(g_tp.peri_global)); + router_s[1]->print_router(); + router_s[2] = new Router(256.0, 8, 4, &(g_tp.peri_global)); + router_s[2]->print_router(); + + int core_in; // to store no. of cores + + /* to search diff grid organizations */ + double curr_hop, totno_hops, totno_hhops, totno_vhops, tot_lat, curr_acclat; + double avg_lat, avg_hop, avg_hhop, avg_vhop, avg_dyn_power, avg_leakage_power; + + double opt_acclat = INF; //, opt_avg_lat = INF, opt_tot_lat = INF; + int opt_rows = 0; + int opt_columns = 0; + // double opt_totno_hops = 0; + double opt_avg_hop = 0; + double opt_dyn_power = 0, opt_leakage_power = 0; + min_values_t minval; + + int bank_start = 0; + + int flit_width = 0; + + /* vertical and horizontal hop latency values */ + int ver_hop_lat, hor_hop_lat; /* in cycles */ + + /* no. of different bank sizes to consider */ + int iterations; + + g_ip->nuca_cache_sz = g_ip->cache_sz; + nuca_list.push_back(new nuca_org_t()); + + if (g_ip->cache_level == 0) + l2_c = 1; + else + l2_c = 0; + + if (g_ip->cores <= 4) + core_in = 2; + else if (g_ip->cores <= 8) + core_in = 3; + else if (g_ip->cores <= 16) + core_in = 4; + else { + cout << "Number of cores should be <= 16!\n"; + exit(0); + } + + // set the lower bound to an appropriate value. this depends on cache + // associativity + if (g_ip->assoc > 2) { + i = 2; + while (i != g_ip->assoc) { + MIN_BANKSIZE *= 2; + i *= 2; + } + } + + iterations = (int)logtwo((int)g_ip->cache_sz / MIN_BANKSIZE); + + if (g_ip->force_wiretype) { + if (g_ip->wt == Low_swing) { + wt_min = Low_swing; + wt_max = Low_swing; + } + else { + wt_min = Global; + wt_max = Low_swing - 1; + } + } + else { + wt_min = Global; + wt_max = Low_swing; + } + if (g_ip->nuca_bank_count != 0) { // simulate just one bank + if (g_ip->nuca_bank_count != 2 && g_ip->nuca_bank_count != 4 && + g_ip->nuca_bank_count != 8 && g_ip->nuca_bank_count != 16 && + g_ip->nuca_bank_count != 32 && g_ip->nuca_bank_count != 64) { + fprintf( + stderr, + "Incorrect bank count value! Please fix the value in cache.cfg\n"); + } + bank_start = (int)logtwo((double)g_ip->nuca_bank_count); + iterations = bank_start + 1; + g_ip->cache_sz = g_ip->cache_sz / g_ip->nuca_bank_count; + } + cout << "Simulating various NUCA configurations\n"; + for (it = bank_start; it < iterations; + it++) { /* different bank count values */ + ures.tag_array2 = &tag; + ures.data_array2 = &data; + /* + * find the optimal bank organization + */ + solve(&ures); + // output_UCA(&ures); + bank_count = g_ip->nuca_cache_sz / g_ip->cache_sz; + cout << "====" << g_ip->cache_sz << "\n"; + + for (wr = wt_min; wr <= wt_max; wr++) { + for (ro = 0; ro < ROUTER_TYPES; ro++) { + flit_width = (int)router_s[ro]->flit_size; // initialize router + nuca_list.back()->nuca_pda.cycle_time = router_s[ro]->cycle_time; + + /* calculate router and wire parameters */ + + double vlength = ures.cache_ht; /* length of the wire (u)*/ + double hlength = ures.cache_len; // u + + /* find delay, area, and power for wires */ + wire_vertical[wr] = new Wire((enum Wire_type)wr, vlength); + wire_horizontal[wr] = new Wire((enum Wire_type)wr, hlength); + + hor_hop_lat = + calc_cycles(wire_horizontal[wr]->delay, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001)); + ver_hop_lat = + calc_cycles(wire_vertical[wr]->delay, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001)); + + /* + * assume a grid like topology and explore for optimal network + * configuration using different row and column count values. + */ + for (c = 1; c <= (unsigned int)bank_count; c++) { + while (bank_count % c != 0) + c++; + r = bank_count / c; + + /* + * to find the avg access latency of a NUCA cache, uncontended + * access time to each bank from the + * cache controller is calculated. + * avg latency = + * sum of the access latencies to individual banks)/bank + * count value. + */ + totno_hops = totno_hhops = totno_vhops = tot_lat = 0; + for (i = 0; i < r; i++) { + for (j = 0; j < c; j++) { + /* + * vertical hops including the + * first hop from the cache controller + */ + curr_hop = i + 1; + curr_hop += j; /* horizontal hops */ + totno_hhops += j; + totno_vhops += (i + 1); + curr_acclat = + (i * ver_hop_lat + CONTR_2_BANK_LAT + j * hor_hop_lat); + + tot_lat += curr_acclat; + totno_hops += curr_hop; + } + } + avg_lat = tot_lat / bank_count; + avg_hop = totno_hops / bank_count; + avg_hhop = totno_hhops / bank_count; + avg_vhop = totno_vhops / bank_count; + + /* net access latency */ + curr_acclat = + 2 * avg_lat + 2 * (router_s[ro]->delay * avg_hop) + + calc_cycles(ures.access_time, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001)); + + /* avg access lat of nuca */ + avg_dyn_power = avg_hop * (router_s[ro]->power.readOp.dynamic) + + avg_hhop * + (wire_horizontal[wr]->power.readOp.dynamic) * + (g_ip->block_sz * 8 + 64) + + avg_vhop * (wire_vertical[wr]->power.readOp.dynamic) * + (g_ip->block_sz * 8 + 64) + + ures.power.readOp.dynamic; + + avg_leakage_power = + bank_count * router_s[ro]->power.readOp.leakage + + avg_hhop * + (wire_horizontal[wr]->power.readOp.leakage * + wire_horizontal[wr]->delay) * + flit_width + + avg_vhop * (wire_vertical[wr]->power.readOp.leakage * + wire_horizontal[wr]->delay); + + if (curr_acclat < opt_acclat) { + opt_acclat = curr_acclat; + // opt_tot_lat = tot_lat; + // opt_avg_lat = avg_lat; + // opt_totno_hops = totno_hops; + opt_avg_hop = avg_hop; + opt_rows = r; + opt_columns = c; + opt_dyn_power = avg_dyn_power; + opt_leakage_power = avg_leakage_power; + } + totno_hops = 0; + tot_lat = 0; + totno_hhops = 0; + totno_vhops = 0; + } + nuca_list.back()->wire_pda.power.readOp.dynamic = + opt_avg_hop * flit_width * + (wire_horizontal[wr]->power.readOp.dynamic + + wire_vertical[wr]->power.readOp.dynamic); + nuca_list.back()->avg_hops = opt_avg_hop; + /* network delay/power */ + nuca_list.back()->h_wire = wire_horizontal[wr]; + nuca_list.back()->v_wire = wire_vertical[wr]; + nuca_list.back()->router = router_s[ro]; + /* bank delay/power */ + + nuca_list.back()->bank_pda.delay = ures.access_time; + nuca_list.back()->bank_pda.power = ures.power; + nuca_list.back()->bank_pda.area.h = ures.cache_ht; + nuca_list.back()->bank_pda.area.w = ures.cache_len; + nuca_list.back()->bank_pda.cycle_time = ures.cycle_time; + + num_cyc = calc_cycles( + nuca_list.back()->bank_pda.delay /*s*/, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001 /*GHz*/)); + if (num_cyc % 2 != 0) + num_cyc++; + if (num_cyc > 16) + num_cyc = 16; // we have data only up to 16 cycles + + if (it < 7) { + nuca_list.back()->nuca_pda.delay = + opt_acclat + cont_stats[l2_c][core_in][ro][it][num_cyc / 2 - 1]; + nuca_list.back()->contention = + cont_stats[l2_c][core_in][ro][it][num_cyc / 2 - 1]; + } + else { + nuca_list.back()->nuca_pda.delay = + opt_acclat + cont_stats[l2_c][core_in][ro][7][num_cyc / 2 - 1]; + nuca_list.back()->contention = + cont_stats[l2_c][core_in][ro][7][num_cyc / 2 - 1]; + } + nuca_list.back()->nuca_pda.power.readOp.dynamic = opt_dyn_power; + nuca_list.back()->nuca_pda.power.readOp.leakage = opt_leakage_power; + + /* array organization */ + nuca_list.back()->bank_count = bank_count; + nuca_list.back()->rows = opt_rows; + nuca_list.back()->columns = opt_columns; + calculate_nuca_area(nuca_list.back()); + + minval.update_min_values(nuca_list.back()); + nuca_list.push_back(new nuca_org_t()); + opt_acclat = BIGNUM; + } + } + g_ip->cache_sz /= 2; + } + + delete (nuca_list.back()); + nuca_list.pop_back(); + opt_n = find_optimal_nuca(&nuca_list, &minval); + print_nuca(opt_n); + g_ip->cache_sz = g_ip->nuca_cache_sz / opt_n->bank_count; + + list::iterator niter; + for (niter = nuca_list.begin(); niter != nuca_list.end(); ++niter) { + delete *niter; + } + nuca_list.clear(); + + for (int i = 0; i < ROUTER_TYPES; i++) { + delete router_s[i]; + } + g_ip->display_ip(); + // g_ip->force_cache_config = true; + // g_ip->ndwl = 8; + // g_ip->ndbl = 16; + // g_ip->nspd = 4; + // g_ip->ndcm = 1; + // g_ip->ndsam1 = 8; + // g_ip->ndsam2 = 32; +} + +void Nuca::print_nuca(nuca_org_t *fr) { + printf("\n---------- CACTI version 6.5, Non-uniform Cache Access " + "----------\n\n"); + printf("Optimal number of banks - %d\n", fr->bank_count); + printf("Grid organization rows x columns - %d x %d\n", fr->rows, fr->columns); + printf("Network frequency - %g GHz\n", (1 / fr->nuca_pda.cycle_time) * 1e3); + printf("Cache dimension (mm x mm) - %g x %g\n", fr->nuca_pda.area.h * 1e-3, + fr->nuca_pda.area.w * 1e-3); + + fr->router->print_router(); + + printf("\n\nWire stats:\n"); + if (fr->h_wire->wt == Global) { + printf("\tWire type - Full swing global wires with least " + "possible delay\n"); + } + else if (fr->h_wire->wt == Global_5) { + printf("\tWire type - Full swing global wires with " + "5%% delay penalty\n"); + } + else if (fr->h_wire->wt == Global_10) { + printf("\tWire type - Full swing global wires with " + "10%% delay penalty\n"); + } + else if (fr->h_wire->wt == Global_20) { + printf("\tWire type - Full swing global wires with " + "20%% delay penalty\n"); + } + else if (fr->h_wire->wt == Global_30) { + printf("\tWire type - Full swing global wires with " + "30%% delay penalty\n"); + } + else if (fr->h_wire->wt == Low_swing) { + printf("\tWire type - Low swing wires\n"); + } + + printf("\tHorizontal link delay - %g (ns)\n", fr->h_wire->delay * 1e9); + printf("\tVertical link delay - %g (ns)\n", fr->v_wire->delay * 1e9); + printf("\tDelay/length - %g (ns/mm)\n", + fr->h_wire->delay * 1e9 / fr->bank_pda.area.w); + printf("\tHorizontal link energy -dynamic/access %g (nJ)\n" + "\t -leakage %g (nW)\n\n", + fr->h_wire->power.readOp.dynamic * 1e9, + fr->h_wire->power.readOp.leakage * 1e9); + printf("\tVertical link energy -dynamic/access %g (nJ)\n" + "\t -leakage %g (nW)\n\n", + fr->v_wire->power.readOp.dynamic * 1e9, + fr->v_wire->power.readOp.leakage * 1e9); + printf("\n\n"); + fr->v_wire->print_wire(); + printf("\n\nBank stats:\n"); +} + +nuca_org_t *Nuca::find_optimal_nuca(list *n, + min_values_t *minval) { + double cost = 0; + double min_cost = BIGNUM; + nuca_org_t *res = NULL; + float d, a, dp, lp, c; + int v; + dp = g_ip->dynamic_power_wt_nuca; + lp = g_ip->leakage_power_wt_nuca; + a = g_ip->area_wt_nuca; + d = g_ip->delay_wt_nuca; + c = g_ip->cycle_time_wt_nuca; + + list::iterator niter; + + for (niter = n->begin(); niter != n->end(); niter++) { + fprintf(stderr, "\n-----------------------------" + "---------------\n"); + + printf("NUCA___stats %d \tbankcount: lat = %g \tdynP = %g \twt = %d\t " + "bank_dpower = %g \tleak = %g \tcycle = %g\n", + (*niter)->bank_count, (*niter)->nuca_pda.delay, + (*niter)->nuca_pda.power.readOp.dynamic, (*niter)->h_wire->wt, + (*niter)->bank_pda.power.readOp.dynamic, + (*niter)->nuca_pda.power.readOp.leakage, + (*niter)->nuca_pda.cycle_time); + + if (g_ip->ed == 1) { + cost = ((*niter)->nuca_pda.delay / minval->min_delay) * + ((*niter)->nuca_pda.power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + res = ((*niter)); + } + } + else if (g_ip->ed == 2) { + cost = ((*niter)->nuca_pda.delay / minval->min_delay) * + ((*niter)->nuca_pda.delay / minval->min_delay) * + ((*niter)->nuca_pda.power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + res = ((*niter)); + } + } + else { + /* + * check whether the current organization + * meets the input deviation constraints + */ + v = check_nuca_org((*niter), minval); + if (minval->min_leakage == 0) + minval->min_leakage = 0.1; // FIXME remove this after leakage modeling + + if (v) { + cost = + (d * ((*niter)->nuca_pda.delay / minval->min_delay) + + c * ((*niter)->nuca_pda.cycle_time / minval->min_cyc) + + dp * ((*niter)->nuca_pda.power.readOp.dynamic / minval->min_dyn) + + lp * ((*niter)->nuca_pda.power.readOp.leakage / + minval->min_leakage) + + a * ((*niter)->nuca_pda.area.get_area() / minval->min_area)); + fprintf(stderr, "cost = %g\n", cost); + + if (min_cost > cost) { + min_cost = cost; + res = ((*niter)); + } + } + else { + niter = n->erase(niter); + if (niter != n->begin()) + niter--; + } + } + } + return res; +} + +int Nuca::check_nuca_org(nuca_org_t *n, min_values_t *minval) { + if (((n->nuca_pda.delay - minval->min_delay) * 100 / minval->min_delay) > + g_ip->delay_dev_nuca) { + return 0; + } + if (((n->nuca_pda.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn) * + 100 > + g_ip->dynamic_power_dev_nuca) { + return 0; + } + if (((n->nuca_pda.power.readOp.leakage - minval->min_leakage) / + minval->min_leakage) * + 100 > + g_ip->leakage_power_dev_nuca) { + return 0; + } + if (((n->nuca_pda.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > + g_ip->cycle_time_dev_nuca) { + return 0; + } + if (((n->nuca_pda.area.get_area() - minval->min_area) / minval->min_area) * + 100 > + g_ip->area_dev_nuca) { + return 0; + } + return 1; +} + +void Nuca::calculate_nuca_area(nuca_org_t *nuca) { + nuca->nuca_pda.area.h = + nuca->rows * ((nuca->h_wire->wire_width + nuca->h_wire->wire_spacing) * + nuca->router->flit_size + + nuca->bank_pda.area.h); + + nuca->nuca_pda.area.w = + nuca->columns * ((nuca->v_wire->wire_width + nuca->v_wire->wire_spacing) * + nuca->router->flit_size + + nuca->bank_pda.area.w); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/nuca.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/nuca.h new file mode 100644 index 0000000000..01e7e6ae0a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/nuca.h @@ -0,0 +1,94 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __NUCA_H__ +#define __NUCA_H__ + +#include +#include "assert.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "io.h" +#include "mat.h" +#include "parameter.h" +#include "router.h" +#include "wire.h" + +namespace cacti { + +class nuca_org_t { + public: + ~nuca_org_t(); + // int size; + /* area, power, access time, and cycle time stats */ + Component nuca_pda; + Component bank_pda; + Component wire_pda; + Wire *h_wire; + Wire *v_wire; + Router *router; + /* for particular network configuration + * calculated based on a cycle accurate + * simulation Ref: CACTI 6 - Tech report + */ + double contention; + + /* grid network stats */ + double avg_hops; + int rows; + int columns; + int bank_count; +}; + +class Nuca : public Component { + public: + Nuca(TechnologyParameter::DeviceType *dt); + void print_router(); + ~Nuca(); + void sim_nuca(); + void init_cont(); + int calc_cycles(double lat, double oper_freq); + void calculate_nuca_area(nuca_org_t *nuca); + int check_nuca_org(nuca_org_t *n, min_values_t *minval); + nuca_org_t *find_optimal_nuca(list *n, min_values_t *minval); + void print_nuca(nuca_org_t *n); + void print_cont_stats(); + + private: + TechnologyParameter::DeviceType *deviceType; + int wt_min, wt_max; + Wire *wire_vertical[WIRE_TYPES], *wire_horizontal[WIRE_TYPES]; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/parameter.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/parameter.cc new file mode 100644 index 0000000000..1fb3993a92 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/parameter.cc @@ -0,0 +1,781 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include +#include + +#include "area.h" +#include "parameter.h" + +using namespace std; +using namespace cacti; + +namespace cacti { +InputParameter *g_ip; +TechnologyParameter g_tp; +} // namespace cacti + +void TechnologyParameter::DeviceType::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "C_g_ideal = " << setw(12) << C_g_ideal << " F/um" + << endl; + cout << indent_str << "C_fringe = " << setw(12) << C_fringe << " F/um" + << endl; + cout << indent_str << "C_overlap = " << setw(12) << C_overlap << " F/um" + << endl; + cout << indent_str << "C_junc = " << setw(12) << C_junc << " F/um^2" + << endl; + cout << indent_str << "l_phy = " << setw(12) << l_phy << " um" << endl; + cout << indent_str << "l_elec = " << setw(12) << l_elec << " um" << endl; + cout << indent_str << "R_nch_on = " << setw(12) << R_nch_on << " ohm-um" + << endl; + cout << indent_str << "R_pch_on = " << setw(12) << R_pch_on << " ohm-um" + << endl; + cout << indent_str << "Vdd = " << setw(12) << Vdd << " V" << endl; + cout << indent_str << "Vth = " << setw(12) << Vth << " V" << endl; + cout << indent_str << "Vdd_default = " << setw(12) << Vdd_default << " V" + << endl; + cout << indent_str << "I_on_n = " << setw(12) << I_on_n << " A/um" << endl; + cout << indent_str << "I_on_p = " << setw(12) << I_on_p << " A/um" << endl; + cout << indent_str << "I_off_n = " << setw(12) << I_off_n << " A/um" + << endl; + cout << indent_str << "I_off_p = " << setw(12) << I_off_p << " A/um" + << endl; + cout << indent_str << "C_ox = " << setw(12) << C_ox << " F/um^2" << endl; + cout << indent_str << "t_ox = " << setw(12) << t_ox << " um" << endl; + cout << indent_str + << "n_to_p_eff_curr_drv_ratio = " << n_to_p_eff_curr_drv_ratio << endl; +} + +void TechnologyParameter::InterconnectType::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "pitch = " << setw(12) << pitch << " um" << endl; + cout << indent_str << "R_per_um = " << setw(12) << R_per_um << " ohm/um" + << endl; + cout << indent_str << "C_per_um = " << setw(12) << C_per_um << " F/um" + << endl; +} + +void TechnologyParameter::ScalingFactor::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "logic_scaling_co_eff = " << setw(12) + << logic_scaling_co_eff << endl; + cout << indent_str << "curr_core_tx_density = " << setw(12) << core_tx_density + << " # of tx/um^2" << endl; +} + +void TechnologyParameter::MemoryType::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "b_w = " << setw(12) << b_w << " um" << endl; + cout << indent_str << "b_h = " << setw(12) << b_h << " um" << endl; + cout << indent_str << "cell_a_w = " << setw(12) << cell_a_w << " um" + << endl; + cout << indent_str << "cell_pmos_w = " << setw(12) << cell_pmos_w << " um" + << endl; + cout << indent_str << "cell_nmos_w = " << setw(12) << cell_nmos_w << " um" + << endl; + cout << indent_str << "Vbitpre = " << setw(12) << Vbitpre << " V" << endl; +} + +void TechnologyParameter::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "ram_wl_stitching_overhead_ = " << setw(12) + << ram_wl_stitching_overhead_ << " um" << endl; + cout << indent_str << "min_w_nmos_ = " << setw(12) + << min_w_nmos_ << " um" << endl; + cout << indent_str << "max_w_nmos_ = " << setw(12) + << max_w_nmos_ << " um" << endl; + cout << indent_str << "unit_len_wire_del = " << setw(12) + << unit_len_wire_del << " s/um^2" << endl; + cout << indent_str << "FO4 = " << setw(12) << FO4 + << " s" << endl; + cout << indent_str << "kinv = " << setw(12) << kinv + << " s" << endl; + cout << indent_str << "vpp = " << setw(12) << vpp + << " V" << endl; + cout << indent_str << "w_sense_en = " << setw(12) + << w_sense_en << " um" << endl; + cout << indent_str << "w_sense_n = " << setw(12) << w_sense_n + << " um" << endl; + cout << indent_str << "w_sense_p = " << setw(12) << w_sense_p + << " um" << endl; + cout << indent_str << "w_iso = " << setw(12) << w_iso + << " um" << endl; + cout << indent_str << "w_poly_contact = " << setw(12) + << w_poly_contact << " um" << endl; + cout << indent_str << "spacing_poly_to_poly = " << setw(12) + << spacing_poly_to_poly << " um" << endl; + cout << indent_str << "spacing_poly_to_contact = " << setw(12) + << spacing_poly_to_contact << " um" << endl; + cout << endl; + cout << indent_str << "w_comp_inv_p1 = " << setw(12) + << w_comp_inv_p1 << " um" << endl; + cout << indent_str << "w_comp_inv_p2 = " << setw(12) + << w_comp_inv_p2 << " um" << endl; + cout << indent_str << "w_comp_inv_p3 = " << setw(12) + << w_comp_inv_p3 << " um" << endl; + cout << indent_str << "w_comp_inv_n1 = " << setw(12) + << w_comp_inv_n1 << " um" << endl; + cout << indent_str << "w_comp_inv_n2 = " << setw(12) + << w_comp_inv_n2 << " um" << endl; + cout << indent_str << "w_comp_inv_n3 = " << setw(12) + << w_comp_inv_n3 << " um" << endl; + cout << indent_str << "w_eval_inv_p = " << setw(12) + << w_eval_inv_p << " um" << endl; + cout << indent_str << "w_eval_inv_n = " << setw(12) + << w_eval_inv_n << " um" << endl; + cout << indent_str << "w_comp_n = " << setw(12) << w_comp_n + << " um" << endl; + cout << indent_str << "w_comp_p = " << setw(12) << w_comp_p + << " um" << endl; + cout << endl; + cout << indent_str << "dram_cell_I_on = " << setw(12) + << dram_cell_I_on << " A/um" << endl; + cout << indent_str << "dram_cell_Vdd = " << setw(12) + << dram_cell_Vdd << " V" << endl; + cout << indent_str << "dram_cell_I_off_worst_case_len_temp = " << setw(12) + << dram_cell_I_off_worst_case_len_temp << " A/um" << endl; + cout << indent_str << "dram_cell_C = " << setw(12) + << dram_cell_C << " F" << endl; + cout << indent_str << "gm_sense_amp_latch = " << setw(12) + << gm_sense_amp_latch << " F/s" << endl; + cout << endl; + cout << indent_str << "w_nmos_b_mux = " << setw(12) + << w_nmos_b_mux << " um" << endl; + cout << indent_str << "w_nmos_sa_mux = " << setw(12) + << w_nmos_sa_mux << " um" << endl; + cout << indent_str << "w_pmos_bl_precharge = " << setw(12) + << w_pmos_bl_precharge << " um" << endl; + cout << indent_str << "w_pmos_bl_eq = " << setw(12) + << w_pmos_bl_eq << " um" << endl; + cout << indent_str << "MIN_GAP_BET_P_AND_N_DIFFS = " << setw(12) + << MIN_GAP_BET_P_AND_N_DIFFS << " um" << endl; + cout << indent_str << "HPOWERRAIL = " << setw(12) + << HPOWERRAIL << " um" << endl; + cout << indent_str << "cell_h_def = " << setw(12) + << cell_h_def << " um" << endl; + + cout << endl; + cout << indent_str << "SRAM cell transistor: " << endl; + sram_cell.display(indent + 2); + + cout << endl; + cout << indent_str << "DRAM access transistor: " << endl; + dram_acc.display(indent + 2); + + cout << endl; + cout << indent_str << "DRAM wordline transistor: " << endl; + dram_wl.display(indent + 2); + + cout << endl; + cout << indent_str << "peripheral global transistor: " << endl; + peri_global.display(indent + 2); + + cout << endl; + cout << indent_str << "wire local" << endl; + wire_local.display(indent + 2); + + cout << endl; + cout << indent_str << "wire inside mat" << endl; + wire_inside_mat.display(indent + 2); + + cout << endl; + cout << indent_str << "wire outside mat" << endl; + wire_outside_mat.display(indent + 2); + + cout << endl; + cout << indent_str << "SRAM" << endl; + sram.display(indent + 2); + + cout << endl; + cout << indent_str << "DRAM" << endl; + dram.display(indent + 2); +} + +DynamicParameter::DynamicParameter() + : use_inp_params(0), cell(), is_valid(true) {} + +DynamicParameter::DynamicParameter(bool is_tag_, int pure_ram_, int pure_cam_, + double Nspd_, unsigned int Ndwl_, + unsigned int Ndbl_, unsigned int Ndcm_, + unsigned int Ndsam_lev_1_, + unsigned int Ndsam_lev_2_, bool is_main_mem_) + : is_tag(is_tag_), + pure_ram(pure_ram_), + pure_cam(pure_cam_), + tagbits(0), + Nspd(Nspd_), + Ndwl(Ndwl_), + Ndbl(Ndbl_), + Ndcm(Ndcm_), + Ndsam_lev_1(Ndsam_lev_1_), + Ndsam_lev_2(Ndsam_lev_2_), + number_way_select_signals_mat(0), + V_b_sense(0), + use_inp_params(0), + is_main_mem(is_main_mem_), + cell(), + is_valid(false) { + ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type + : g_ip->data_arr_ram_cell_tech_type; + is_dram = + ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram)); + + unsigned int capacity_per_die = + g_ip->cache_sz / + NUMBER_STACKED_DIE_LAYERS; // capacity per stacked die layer + const TechnologyParameter::InterconnectType &wire_local = g_tp.wire_local; + fully_assoc = (g_ip->fully_assoc) ? true : false; + + if (fully_assoc || + pure_cam) { // fully-assocative cache -- ref: CACTi 2.0 report + if (Ndwl != 1 || // Ndwl is fixed to 1 for FA + Ndcm != 1 || // Ndcm is fixed to 1 for FA + Nspd < 1 || Nspd > 1 || // Nspd is fixed to 1 for FA + Ndsam_lev_1 != 1 || // Ndsam_lev_1 is fixed to one + Ndsam_lev_2 != 1 || // Ndsam_lev_2 is fixed to one + Ndbl < 2) { + return; + } + } + + if ((is_dram) && (!is_tag) && (Ndcm > 1)) { + return; // For a DRAM array, each bitline has its own sense-amp + } + + // If it's not an FA tag/data array, Ndwl should be at least two and Ndbl + // should be at least two because an array is assumed to have at least one + // mat. And a mat is formed out of two horizontal subarrays and two vertical + // subarrays + if (fully_assoc == false && (Ndwl < 1 || Ndbl < 1)) { + return; + } + + //***********compute row, col of an subarray + if (!(fully_assoc || pure_cam)) // Not fully_asso nor cam + { + // if data array, let tagbits = 0 + if (is_tag) { + if (g_ip->specific_tag) { + tagbits = g_ip->tag_w; + } + else { + tagbits = ADDRESS_BITS + EXTRA_TAG_BITS - _log2(capacity_per_die) + + _log2(g_ip->tag_assoc * 2 - 1) - _log2(g_ip->nbanks); + } + tagbits = (((tagbits + 3) >> 2) << 2); + + num_r_subarray = (int)ceil( + capacity_per_die / (g_ip->nbanks * g_ip->block_sz * g_ip->tag_assoc * + Ndbl * Nspd)); // + EPSILON); + num_c_subarray = + (int)ceil((tagbits * g_ip->tag_assoc * Nspd / Ndwl)); // + EPSILON); + // burst_length = 1; + } + else { + num_r_subarray = (int)ceil( + capacity_per_die / (g_ip->nbanks * g_ip->block_sz * g_ip->data_assoc * + Ndbl * Nspd)); // + EPSILON); + num_c_subarray = (int)ceil((8 * g_ip->block_sz * g_ip->data_assoc * Nspd / + Ndwl)); // + EPSILON); + EPSILON); + // burst_length = g_ip->block_sz * 8 / g_ip->out_w; + } + + if (num_r_subarray < MINSUBARRAYROWS) + return; + if (num_r_subarray == 0) + return; + if (num_r_subarray > MAXSUBARRAYROWS) + return; + if (num_c_subarray < MINSUBARRAYCOLS) + return; + if (num_c_subarray > MAXSUBARRAYCOLS) + return; + } + + else { // either fully-asso or cam + if (pure_cam) { + if (g_ip->specific_tag) { + tagbits = int(ceil(g_ip->tag_w / 8.0) * 8); + } + else { + tagbits = int(ceil((ADDRESS_BITS + EXTRA_TAG_BITS) / 8.0) * 8); + // cout<<"Pure CAM needs tag width to be + // specified"<> 2) << 2); + + tag_num_r_subarray = (int)ceil(capacity_per_die / + (g_ip->nbanks * tagbits / 8.0 * + Ndbl)); // TODO: error check input of + // tagbits and blocksize //TODO: + // for pure CAM, g_ip->block + // should be number of entries. + // tag_num_c_subarray = (int)(tagbits + EPSILON); + tag_num_c_subarray = tagbits; + if (tag_num_r_subarray == 0) + return; + if (tag_num_r_subarray > MAXSUBARRAYROWS) + return; + if (tag_num_c_subarray < MINSUBARRAYCOLS) + return; + if (tag_num_c_subarray > MAXSUBARRAYCOLS) + return; + num_r_subarray = tag_num_r_subarray; + } + else // fully associative + { + if (g_ip->specific_tag) { + tagbits = g_ip->tag_w; + } + else { + tagbits = ADDRESS_BITS + EXTRA_TAG_BITS - + _log2(g_ip->block_sz); // TODO: should be the + // page_offset=log2(page size), but + // this info is not avail with CACTI, + // for McPAT this is no problem. + } + tagbits = (((tagbits + 3) >> 2) << 2); + + tag_num_r_subarray = + (int)(capacity_per_die / (g_ip->nbanks * g_ip->block_sz * Ndbl)); + tag_num_c_subarray = (int)ceil((tagbits * Nspd / Ndwl)); // + EPSILON); + if (tag_num_r_subarray == 0) + return; + if (tag_num_r_subarray > MAXSUBARRAYROWS) + return; + if (tag_num_c_subarray < MINSUBARRAYCOLS) + return; + if (tag_num_c_subarray > MAXSUBARRAYCOLS) + return; + + data_num_r_subarray = tag_num_r_subarray; + data_num_c_subarray = 8 * g_ip->block_sz; + if (data_num_r_subarray == 0) + return; + if (data_num_r_subarray > MAXSUBARRAYROWS) + return; + if (data_num_c_subarray < MINSUBARRAYCOLS) + return; + if (data_num_c_subarray > MAXSUBARRAYCOLS) + return; + num_r_subarray = tag_num_r_subarray; + } + } + + num_subarrays = Ndwl * Ndbl; + //****************end of computation of row, col of an subarray + + // calculate wire parameters + if (fully_assoc || pure_cam) { + cam_cell.h = + g_tp.cam.b_h + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + g_ip->num_rd_ports + g_ip->num_wr_ports) + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) + + wire_local.pitch * g_ip->num_se_rd_ports; + cam_cell.w = + g_tp.cam.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + g_ip->num_rd_ports + g_ip->num_wr_ports) + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) + + wire_local.pitch * g_ip->num_se_rd_ports; + + cell.h = + g_tp.sram.b_h + + 2 * wire_local.pitch * + (g_ip->num_wr_ports + g_ip->num_rw_ports - 1 + g_ip->num_rd_ports) + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1); + cell.w = g_tp.sram.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + + (g_ip->num_rd_ports - g_ip->num_se_rd_ports) + + g_ip->num_wr_ports) + + g_tp.wire_local.pitch * g_ip->num_se_rd_ports + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1); + } + else { + if (is_tag) { + cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + + g_ip->num_rd_ports + g_ip->num_wr_ports); + cell.w = g_tp.sram.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + g_ip->num_wr_ports + + (g_ip->num_rd_ports - g_ip->num_se_rd_ports)) + + wire_local.pitch * g_ip->num_se_rd_ports; + } + else { + if (is_dram) { + cell.h = g_tp.dram.b_h; + cell.w = g_tp.dram.b_w; + } + else { + cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * + (g_ip->num_wr_ports + g_ip->num_rw_ports - + 1 + g_ip->num_rd_ports); + cell.w = g_tp.sram.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + + (g_ip->num_rd_ports - g_ip->num_se_rd_ports) + + g_ip->num_wr_ports) + + g_tp.wire_local.pitch * g_ip->num_se_rd_ports; + } + } + } + + double c_b_metal = cell.h * wire_local.C_per_um; + double C_bl; + + if (!(fully_assoc || pure_cam)) { + if (is_dram) { + deg_bl_muxing = 1; + if (ram_cell_tech_type == comm_dram) { + C_bl = num_r_subarray * c_b_metal; + V_b_sense = (g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_C / + (g_tp.dram_cell_C + C_bl); + if (V_b_sense < VBITSENSEMIN) { + return; + } + V_b_sense = VBITSENSEMIN; // in any case, we fix sense amp input signal + // to a constant value + dram_refresh_period = 64e-3; + } + else { + double Cbitrow_drain_cap = + drain_C_(g_tp.dram.cell_a_w, NCH, 1, 0, cell.w, true, true) / 2.0; + C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); + V_b_sense = (g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_C / + (g_tp.dram_cell_C + C_bl); + + if (V_b_sense < VBITSENSEMIN) { + return; // Sense amp input signal is smaller that minimum allowable + // sense amp input signal + } + V_b_sense = VBITSENSEMIN; // in any case, we fix sense amp input signal + // to a constant value + // v_storage_worst = g_tp.dram_cell_Vdd / 2 - VBITSENSEMIN * + // (g_tp.dram_cell_C + C_bl) / g_tp.dram_cell_C; dram_refresh_period + // = 1.1 * g_tp.dram_cell_C * v_storage_worst / + // g_tp.dram_cell_I_off_worst_case_len_temp; + dram_refresh_period = + 0.9 * g_tp.dram_cell_C * VDD_STORAGE_LOSS_FRACTION_WORST * + g_tp.dram_cell_Vdd / g_tp.dram_cell_I_off_worst_case_len_temp; + } + } + else { // SRAM + V_b_sense = (0.05 * g_tp.sram_cell.Vdd > VBITSENSEMIN) + ? 0.05 * g_tp.sram_cell.Vdd + : VBITSENSEMIN; + deg_bl_muxing = Ndcm; + // "/ 2.0" below is due to the fact that two adjacent access transistors + // share drain contacts in a physical layout + double Cbitrow_drain_cap = + drain_C_(g_tp.sram.cell_a_w, NCH, 1, 0, cell.w, false, true) / 2.0; + C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); + dram_refresh_period = 0; + } + } + else { + c_b_metal = cam_cell.h * wire_local.C_per_um; // IBM and SUN design, SRAM + // array uses dummy cells to + // fill the blank space due + // to mismatch on CAM-RAM + V_b_sense = (0.05 * g_tp.sram_cell.Vdd > VBITSENSEMIN) + ? 0.05 * g_tp.sram_cell.Vdd + : VBITSENSEMIN; + deg_bl_muxing = 1; // FA fix as 1 + // "/ 2.0" below is due to the fact that two adjacent access transistors + // share drain contacts in a physical layout + double Cbitrow_drain_cap = + drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / + 2.0; // TODO: comment out these two lines + C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); + dram_refresh_period = 0; + } + + // do/di: data in/out, for fully associative they are the data width for + // normal read and write so/si: search data in/out, for fully associative they + // are the data width for the search ops for CAM, si=di, but so = matching + // address. do = data out = di (for normal read/write) so/si needs broadcase + // while do/di do not + + if (fully_assoc || pure_cam) { + switch (Ndbl) { + case (0): + cout << " Invalid Ndbl \n" << endl; + exit(0); + break; + case (1): + num_mats_h_dir = 1; // one subarray per mat + num_mats_v_dir = 1; + break; + case (2): + num_mats_h_dir = 1; // two subarrays per mat + num_mats_v_dir = 1; + break; + default: + num_mats_h_dir = int(floor(sqrt(Ndbl / 4.0))); // 4 subbarrys per mat + num_mats_v_dir = int(Ndbl / 4.0 / num_mats_h_dir); + } + num_mats = num_mats_h_dir * num_mats_v_dir; + + if (fully_assoc) { + num_so_b_mat = data_num_c_subarray; + num_do_b_mat = data_num_c_subarray + tagbits; + } + else { + num_so_b_mat = int( + ceil(log2(num_r_subarray)) + + ceil(log2(num_subarrays))); // the address contains the matched data + num_do_b_mat = tagbits; + } + } + else { + num_mats_h_dir = MAX(Ndwl / 2, 1); + num_mats_v_dir = MAX(Ndbl / 2, 1); + num_mats = num_mats_h_dir * num_mats_v_dir; + num_do_b_mat = MAX((num_subarrays / num_mats) * num_c_subarray / + (deg_bl_muxing * Ndsam_lev_1 * Ndsam_lev_2), + 1); + } + + if (!(fully_assoc || pure_cam) && + (num_do_b_mat < (num_subarrays / num_mats))) { + return; + } + + int deg_sa_mux_l1_non_assoc; + // TODO:the i/o for subbank is not necessary and should be removed. + if (!(fully_assoc || pure_cam)) { + if (!is_tag) { + if (is_main_mem == true) { + num_do_b_subbank = g_ip->int_prefetch_w * g_ip->out_w; + deg_sa_mux_l1_non_assoc = Ndsam_lev_1; + } + else { + if (g_ip->fast_access == true) { + num_do_b_subbank = g_ip->out_w * g_ip->data_assoc; + deg_sa_mux_l1_non_assoc = Ndsam_lev_1; + } + else { + num_do_b_subbank = g_ip->out_w; + deg_sa_mux_l1_non_assoc = Ndsam_lev_1 / g_ip->data_assoc; + if (deg_sa_mux_l1_non_assoc < 1) { + return; + } + } + } + } + else { + num_do_b_subbank = tagbits * g_ip->tag_assoc; + if (num_do_b_mat < tagbits) { + return; + } + deg_sa_mux_l1_non_assoc = Ndsam_lev_1; + // num_do_b_mat = g_ip->tag_assoc / num_mats_h_dir; + } + } + else { + if (fully_assoc) { + num_so_b_subbank = 8 * g_ip->block_sz; // TODO:internal perfetch should + // be considered also for fa + num_do_b_subbank = num_so_b_subbank + tag_num_c_subarray; + } + else { + num_so_b_subbank = int( + ceil(log2(num_r_subarray)) + + ceil(log2(num_subarrays))); // the address contains the matched data + num_do_b_subbank = tag_num_c_subarray; + } + + deg_sa_mux_l1_non_assoc = 1; + } + + deg_senseamp_muxing_non_associativity = deg_sa_mux_l1_non_assoc; + + if (fully_assoc || pure_cam) { + num_act_mats_hor_dir = 1; + num_act_mats_hor_dir_sl = num_mats_h_dir; // TODO: this is unnecessary, + // since search op, num_mats is + // used + } + else { + num_act_mats_hor_dir = num_do_b_subbank / num_do_b_mat; + if (num_act_mats_hor_dir == 0) { + return; + } + } + + // compute num_do_mat for tag + if (is_tag) { + if (!(fully_assoc || pure_cam)) { + num_do_b_mat = g_ip->tag_assoc / num_act_mats_hor_dir; + num_do_b_subbank = num_act_mats_hor_dir * num_do_b_mat; + } + } + + if ((g_ip->is_cache == false && is_main_mem == true) || + (PAGE_MODE == 1 && is_dram)) { + if (num_act_mats_hor_dir * num_do_b_mat * Ndsam_lev_1 * Ndsam_lev_2 != + (int)g_ip->page_sz_bits) { + return; + } + } + + // if (is_tag == false && g_ip->is_cache == true && !fully_assoc && !pure_cam + // && //TODO: TODO burst transfer should also apply to RAM arrays + if (is_tag == false && g_ip->is_main_mem == true && + num_act_mats_hor_dir * num_do_b_mat * Ndsam_lev_1 * Ndsam_lev_2 < + ((int)g_ip->out_w * (int)g_ip->burst_len * (int)g_ip->data_assoc)) { + return; + } + + if (num_act_mats_hor_dir > num_mats_h_dir) { + return; + } + + // compute di for mat subbank and bank + if (!(fully_assoc || pure_cam)) { + if (!is_tag) { + if (g_ip->fast_access == true) { + num_di_b_mat = num_do_b_mat / g_ip->data_assoc; + } + else { + num_di_b_mat = num_do_b_mat; + } + } + else { + num_di_b_mat = tagbits; + } + } + else { + if (fully_assoc) { + num_di_b_mat = num_do_b_mat; + //*num_subarrays/num_mats; bits per mat of CAM/FA is as same as cache, + // but inside the mat wire tracks need to be reserved for search data bus + num_si_b_mat = tagbits; + } + else { + num_di_b_mat = tagbits; + num_si_b_mat = tagbits; //*num_subarrays/num_mats; + } + } + + num_di_b_subbank = + num_di_b_mat * num_act_mats_hor_dir; // normal cache or normal r/w for FA + num_si_b_subbank = + num_si_b_mat; //* num_act_mats_hor_dir_sl; inside the data is broadcast + + int num_addr_b_row_dec = _log2(num_r_subarray); + if ((fully_assoc || pure_cam)) + num_addr_b_row_dec += _log2(num_subarrays / num_mats); + int number_subbanks = num_mats / num_act_mats_hor_dir; + number_subbanks_decode = _log2( + number_subbanks); // TODO: add log2(num_subarray_per_bank) to FA/CAM + + num_rw_ports = g_ip->num_rw_ports; + num_rd_ports = g_ip->num_rd_ports; + num_wr_ports = g_ip->num_wr_ports; + num_se_rd_ports = g_ip->num_se_rd_ports; + num_search_ports = g_ip->num_search_ports; + + if (is_dram && is_main_mem) { + number_addr_bits_mat = + MAX((unsigned int)num_addr_b_row_dec, + _log2(deg_bl_muxing) + _log2(deg_sa_mux_l1_non_assoc) + + _log2(Ndsam_lev_2)); + } + else { + number_addr_bits_mat = num_addr_b_row_dec + _log2(deg_bl_muxing) + + _log2(deg_sa_mux_l1_non_assoc) + _log2(Ndsam_lev_2); + } + + if (!(fully_assoc || pure_cam)) { + if (is_tag) { + num_di_b_bank_per_port = tagbits; + num_do_b_bank_per_port = g_ip->data_assoc; + } + else { + num_di_b_bank_per_port = g_ip->out_w + g_ip->data_assoc; + num_do_b_bank_per_port = g_ip->out_w; + } + } + else { + if (fully_assoc) { + num_di_b_bank_per_port = + g_ip->out_w + tagbits; // TODO: out_w or block_sz? + num_si_b_bank_per_port = tagbits; + num_do_b_bank_per_port = g_ip->out_w + tagbits; + num_so_b_bank_per_port = g_ip->out_w; + } + else { + num_di_b_bank_per_port = tagbits; + num_si_b_bank_per_port = tagbits; + num_do_b_bank_per_port = tagbits; + num_so_b_bank_per_port = + int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays))); + } + } + + if ((!is_tag) && (g_ip->data_assoc > 1) && (!g_ip->fast_access)) { + number_way_select_signals_mat = g_ip->data_assoc; + } + + // add ECC adjustment to all data signals that traverse on H-trees. + if (g_ip->add_ecc_b_ == true) { + num_do_b_mat += (int)(ceil(num_do_b_mat / num_bits_per_ecc_b_)); + num_di_b_mat += (int)(ceil(num_di_b_mat / num_bits_per_ecc_b_)); + num_di_b_subbank += (int)(ceil(num_di_b_subbank / num_bits_per_ecc_b_)); + num_do_b_subbank += (int)(ceil(num_do_b_subbank / num_bits_per_ecc_b_)); + num_di_b_bank_per_port += + (int)(ceil(num_di_b_bank_per_port / num_bits_per_ecc_b_)); + num_do_b_bank_per_port += + (int)(ceil(num_do_b_bank_per_port / num_bits_per_ecc_b_)); + + num_so_b_mat += (int)(ceil(num_so_b_mat / num_bits_per_ecc_b_)); + num_si_b_mat += (int)(ceil(num_si_b_mat / num_bits_per_ecc_b_)); + num_si_b_subbank += (int)(ceil(num_si_b_subbank / num_bits_per_ecc_b_)); + num_so_b_subbank += (int)(ceil(num_so_b_subbank / num_bits_per_ecc_b_)); + num_si_b_bank_per_port += + (int)(ceil(num_si_b_bank_per_port / num_bits_per_ecc_b_)); + num_so_b_bank_per_port += + (int)(ceil(num_so_b_bank_per_port / num_bits_per_ecc_b_)); + } + + is_valid = true; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/parameter.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/parameter.h new file mode 100644 index 0000000000..4d0b426bab --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/parameter.h @@ -0,0 +1,391 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __PARAMETER_H__ +#define __PARAMETER_H__ + +#include "area.h" +#include "cacti_interface.h" +#include "const.h" +#include "io.h" + +namespace cacti { + +// parameters which are functions of certain device technology +class TechnologyParameter { + public: + class DeviceType { + public: + double C_g_ideal; + double C_fringe; + double C_overlap; + double C_junc; // C_junc_area + double C_junc_sidewall; + double l_phy; + double l_elec; + double R_nch_on; + double R_pch_on; + double Vdd; + double Vdd_default; + double Vth; + double Vcc_min_default; // allowed min vcc; for memory cell it is the + // lowest vcc for data retention. for logic it is + // the vcc to balance the leakage reduction and + // wakeup latency; This is the value constrained by + // the IC technology and cannot by changed by + // external/user voltage supply + double Vcc_min; // same meaning as Vcc_min_default, however, this value is + // set by user, once it is lower than Vcc_min_default; + // circuit (e.g. SRAM cells) cannot retain state. + double I_on_n; + double I_on_p; + double I_off_n; + double I_off_p; + double I_g_on_n; + double I_g_on_p; + double C_ox; + double t_ox; + double n_to_p_eff_curr_drv_ratio; + double long_channel_leakage_reduction; + double Mobility_n; + + DeviceType() + : C_g_ideal(0), + C_fringe(0), + C_overlap(0), + C_junc(0), + C_junc_sidewall(0), + l_phy(0), + l_elec(0), + R_nch_on(0), + R_pch_on(0), + Vdd(0), + Vdd_default(0), + Vth(0), + Vcc_min(0), + I_on_n(0), + I_on_p(0), + I_off_n(0), + I_off_p(0), + I_g_on_n(0), + I_g_on_p(0), + C_ox(0), + t_ox(0), + n_to_p_eff_curr_drv_ratio(0), + long_channel_leakage_reduction(0), + Mobility_n(0){}; + void reset() { + C_g_ideal = 0; + C_fringe = 0; + C_overlap = 0; + C_junc = 0; + l_phy = 0; + l_elec = 0; + R_nch_on = 0; + R_pch_on = 0; + Vdd = 0; + Vdd_default = 0; + Vth = 0; + Vcc_min_default = 0; + Vcc_min = 0; + I_on_n = 0; + I_on_p = 0; + I_off_n = 0; + I_off_p = 0; + I_g_on_n = 0; + I_g_on_p = 0; + C_ox = 0; + t_ox = 0; + n_to_p_eff_curr_drv_ratio = 0; + long_channel_leakage_reduction = 0; + Mobility_n = 0; + } + + void display(uint32_t indent = 0); + }; + class InterconnectType { + public: + double pitch; + double R_per_um; + double C_per_um; + double horiz_dielectric_constant; + double vert_dielectric_constant; + double aspect_ratio; + double miller_value; + double ild_thickness; + + InterconnectType() : pitch(0), R_per_um(0), C_per_um(0){}; + + void reset() { + pitch = 0; + R_per_um = 0; + C_per_um = 0; + horiz_dielectric_constant = 0; + vert_dielectric_constant = 0; + aspect_ratio = 0; + miller_value = 0; + ild_thickness = 0; + } + + void display(uint32_t indent = 0); + }; + class MemoryType { + public: + double b_w; + double b_h; + double cell_a_w; + double cell_pmos_w; + double cell_nmos_w; + double Vbitpre; + double Vbitfloating; // voltage when floating bitline is supported + + void reset() { + b_w = 0; + b_h = 0; + cell_a_w = 0; + cell_pmos_w = 0; + cell_nmos_w = 0; + Vbitpre = 0; + Vbitfloating = 0; + } + + void display(uint32_t indent = 0); + }; + + class ScalingFactor { + public: + double logic_scaling_co_eff; + double core_tx_density; + double long_channel_leakage_reduction; + + ScalingFactor() + : logic_scaling_co_eff(0), + core_tx_density(0), + long_channel_leakage_reduction(0){}; + + void reset() { + logic_scaling_co_eff = 0; + core_tx_density = 0; + long_channel_leakage_reduction = 0; + } + + void display(uint32_t indent = 0); + }; + + double ram_wl_stitching_overhead_; + double min_w_nmos_; + double max_w_nmos_; + double max_w_nmos_dec; + double unit_len_wire_del; + double FO4; + double kinv; + double vpp; + double w_sense_en; + double w_sense_n; + double w_sense_p; + double sense_delay; + double sense_dy_power; + double w_iso; + double w_poly_contact; + double spacing_poly_to_poly; + double spacing_poly_to_contact; + + double w_comp_inv_p1; + double w_comp_inv_p2; + double w_comp_inv_p3; + double w_comp_inv_n1; + double w_comp_inv_n2; + double w_comp_inv_n3; + double w_eval_inv_p; + double w_eval_inv_n; + double w_comp_n; + double w_comp_p; + + double dram_cell_I_on; + double dram_cell_Vdd; + double dram_cell_I_off_worst_case_len_temp; + double dram_cell_C; + double gm_sense_amp_latch; + + double w_nmos_b_mux; + double w_nmos_sa_mux; + double w_pmos_bl_precharge; + double w_pmos_bl_eq; + double MIN_GAP_BET_P_AND_N_DIFFS; + double MIN_GAP_BET_SAME_TYPE_DIFFS; + double HPOWERRAIL; + double cell_h_def; + + double chip_layout_overhead; + double macro_layout_overhead; + double sckt_co_eff; + + double fringe_cap; + + uint64_t h_dec; + + DeviceType sram_cell; // SRAM cell transistor + DeviceType dram_acc; // DRAM access transistor + DeviceType dram_wl; // DRAM wordline transistor + DeviceType peri_global; // peripheral global + DeviceType cam_cell; // SRAM cell transistor + + DeviceType sleep_tx; // Sleep transistor cell transistor + + InterconnectType wire_local; + InterconnectType wire_inside_mat; + InterconnectType wire_outside_mat; + + ScalingFactor scaling_factor; + + MemoryType sram; + MemoryType dram; + MemoryType cam; + + void display(uint32_t indent = 0); + + void reset() { + dram_cell_Vdd = 0; + dram_cell_I_on = 0; + dram_cell_C = 0; + vpp = 0; + + sense_delay = 0; + sense_dy_power = 0; + fringe_cap = 0; + // horiz_dielectric_constant = 0; + // vert_dielectric_constant = 0; + // aspect_ratio = 0; + // miller_value = 0; + // ild_thickness = 0; + + dram_cell_I_off_worst_case_len_temp = 0; + + sram_cell.reset(); + dram_acc.reset(); + dram_wl.reset(); + peri_global.reset(); + cam_cell.reset(); + sleep_tx.reset(); + + scaling_factor.reset(); + + wire_local.reset(); + wire_inside_mat.reset(); + wire_outside_mat.reset(); + + sram.reset(); + dram.reset(); + cam.reset(); + + chip_layout_overhead = 0; + macro_layout_overhead = 0; + sckt_co_eff = 0; + } +}; + +class DynamicParameter { + public: + bool is_tag; + bool pure_ram; + bool pure_cam; + bool fully_assoc; + int tagbits; + int num_subarrays; // only for leakage computation -- the number of + // subarrays per bank + int num_mats; // only for leakage computation -- the number of mats per bank + double Nspd; + int Ndwl; + int Ndbl; + int Ndcm; + int deg_bl_muxing; + int deg_senseamp_muxing_non_associativity; + int Ndsam_lev_1; + int Ndsam_lev_2; + int number_addr_bits_mat; // per port + int number_subbanks_decode; // per_port + int num_di_b_bank_per_port; + int num_do_b_bank_per_port; + int num_di_b_mat; + int num_do_b_mat; + int num_di_b_subbank; + int num_do_b_subbank; + + int num_si_b_mat; + int num_so_b_mat; + int num_si_b_subbank; + int num_so_b_subbank; + int num_si_b_bank_per_port; + int num_so_b_bank_per_port; + + int number_way_select_signals_mat; + int num_act_mats_hor_dir; + + int num_act_mats_hor_dir_sl; + bool is_dram; + double V_b_sense; + unsigned int num_r_subarray; + unsigned int num_c_subarray; + int tag_num_r_subarray; // sheng: fully associative cache tag and data must + // be computed together, data and tag must be + // separate + int tag_num_c_subarray; + int data_num_r_subarray; + int data_num_c_subarray; + int num_mats_h_dir; + int num_mats_v_dir; + uint32_t ram_cell_tech_type; + double dram_refresh_period; + + DynamicParameter(); + DynamicParameter(bool is_tag_, int pure_ram_, int pure_cam_, double Nspd_, + unsigned int Ndwl_, unsigned int Ndbl_, unsigned int Ndcm_, + unsigned int Ndsam_lev_1_, unsigned int Ndsam_lev_2_, + bool is_main_mem_); + + int use_inp_params; + unsigned int num_rw_ports; + unsigned int num_rd_ports; + unsigned int num_wr_ports; + unsigned int num_se_rd_ports; // number of single ended read ports + unsigned int num_search_ports; + unsigned int out_w; // == nr_bits_out + bool is_main_mem; + Area cell, cam_cell; // cell is the sram_cell in both nomal cache/ram and FA. + bool is_valid; +}; + +extern InputParameter *g_ip; +extern TechnologyParameter g_tp; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/powergating.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/powergating.cc new file mode 100644 index 0000000000..de39bf37d3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/powergating.cc @@ -0,0 +1,163 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "powergating.h" +#include +#include +#include +#include "area.h" +#include "parameter.h" + +using namespace std; +using namespace cacti; + +/* + * Sizing of sleep tx is independent of sleep/power-saving supply voltage, + * sleep/power-saving supply voltage only affects wake-up energy and time + * + * While using DSTN (Distributed sleep tx network), worst case sizing is used. + * For DSTN, the network can help to reduce the runtime latency (or achieve the + * same latency with smaller transistor size) For example, during write access, + * if not all bits are toggled, the sleep tx in the non-toggled path can work as + * the extra discharge paths of all the toggled bits, in addition to the sleep + * tx in the bitlines with the toggled bits. Since CACTI itself assumes worst + * case with all bits toggled, sleep txs are assumed to work all the time with + * all bits toggled, Therefore, although DTSN is used, for memory array, the + * number of sleep txs is related to the number of rows and cols., and all + * calculations are still base on single sleep tx for each discharge case. Of + * couse in each discharge path, the sleep tx is the charge path of all the + * devices in the same path (row or col). + * + * Even in the worse case sizing, the wakeup time will not change + * since all paths need to charge/discharge---each sleep tx is just do its own + * portion of the work during wakeup or entering sleep state. + * + * Power-gating and DVS cannot happen at the same time! Because power-gating + * happens when circuit is idle, while DVS happens when circuit is active. When + * waking up from power-gating status, it is assumed that the system will first + * wakeup to DVS0 (full speed) state, if DVS is enabled in the system. + * + * + * + */ +Sleep_tx::Sleep_tx(double _perf_with_sleep_tx, + double _active_Isat, // of circuit block, not sleep tx + bool _is_footer, double _c_circuit_wakeup, double _V_delta, + int _num_sleep_tx, + // double _vt_circuit, + // double _vt_sleep_tx, + // double _mobility,//of sleep tx + // double _c_ox,//of sleep tx + const Area &cell_) + : perf_with_sleep_tx(_perf_with_sleep_tx), + active_Isat(_active_Isat), + is_footer(_is_footer), + num_sleep_tx(_num_sleep_tx), + c_circuit_wakeup(_c_circuit_wakeup), + // vt_circuit(_vt_circuit), + // vt_sleep_tx(_vt_sleep_tx), + // mobility(_mobility), + // c_ox(_c_ox) + cell(cell_), + is_sleep_tx(true), + V_delta(_V_delta) { + // a single sleep tx in a network + double raw_area, raw_width, raw_hight; + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(false, false, true); + vdd = g_tp.peri_global.Vdd; + vt_circuit = g_tp.peri_global.Vth; + vt_sleep_tx = g_tp.sleep_tx.Vth; + mobility = g_tp.sleep_tx.Mobility_n; + c_ox = g_tp.sleep_tx.C_ox; + + width = active_Isat / + (perf_with_sleep_tx * mobility * c_ox * (vdd - vt_circuit) * + (vdd - vt_sleep_tx)) * + g_ip->F_sz_um; // W/L uses physical numbers + width /= num_sleep_tx; + + // double cell_hight = MAX(cell.w*2, g_tp.cell_h_def); + raw_area = compute_gate_area(INV, 1, width, p_to_n_sz_ratio * width, cell.h) / + 2; // Only single device, assuming device is laid on the side of + // the circuit block without changing the height of the + // standard library cells (using the standard cell approach). + raw_width = cell.w; + raw_hight = raw_area / cell.w; + area.set_h(raw_hight); + area.set_w(raw_width); + + compute_penalty(); +} + +double Sleep_tx::compute_penalty() { + // V_delta = VDD - VCCmin nothing to do with threshold of sleep tx. Although + // it might be OK to use sleep tx to control the V_delta + // double c_load; + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(false, false, true); + + if (is_footer) { + c_intrinsic_sleep = + drain_C_(width, NCH, 1, 1, area.h, false, false, false, is_sleep_tx); + // V_delta = _V_delta; + wakeup_delay = + (c_circuit_wakeup + c_intrinsic_sleep) * V_delta / + (simplified_nmos_Isat(width, false, false, false, is_sleep_tx) / + Ilinear_to_Isat_ratio); + wakeup_power.readOp.dynamic = + (c_circuit_wakeup + c_intrinsic_sleep) * g_tp.sram_cell.Vdd * V_delta; + // no 0.5 because the half of the energy spend in entering sleep and half of + // the energy will be spent in waking up. And they are pairs + } + else { + c_intrinsic_sleep = drain_C_(width * p_to_n_sz_ratio, PCH, 1, 1, area.h, + false, false, false, is_sleep_tx); + // V_delta = _V_delta; + wakeup_delay = + (c_circuit_wakeup + c_intrinsic_sleep) * V_delta / + (simplified_pmos_Isat(width, false, false, false, is_sleep_tx) / + Ilinear_to_Isat_ratio); + wakeup_power.readOp.dynamic = + (c_circuit_wakeup + c_intrinsic_sleep) * g_tp.sram_cell.Vdd * V_delta; + } + + /* + The number of cycles in the wake-up latency set the constraint on the + minimum number of idle clock cycles needed before a processor + can enter in the corresponding sleep mode without any wakeup + overhead. + + If the circuit is half way to sleep then waken up, it is still OK + just the wakeup latency will be shorter than the wakeup time from full + asleep. So, the sleep time and energy does not matter + */ + + return 0.; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/powergating.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/powergating.h new file mode 100644 index 0000000000..c4709c1c01 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/powergating.h @@ -0,0 +1,81 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef POWERGATING_H_ +#define POWERGATING_H_ + +#include "component.h" + +namespace cacti { + +class Sleep_tx : public Component { + public: + Sleep_tx(double _perf_with_sleep_tx, + double _active_Isat, // of circuit block, not sleep tx + bool _is_footer, double _c_circuit_wakeup, double _V_delta, + int _num_sleep_tx, + // double _vt_circuit, + // double _vt_sleep_tx, + // double _mobility,//of sleep tx + // double _c_ox,//of sleep tx + const Area &cell_); + + double perf_with_sleep_tx; + double active_Isat; + bool is_footer; + int num_sleep_tx; + double vt_circuit; + double vt_sleep_tx; + double vdd; // of circuit block not sleep tx + double mobility; // of sleep tx + double c_ox; + double width; + double c_circuit_wakeup; + double c_intrinsic_sleep; + double delay, wakeup_delay; + powerDef power, wakeup_power; + // double c_circuit_sleep; + // double sleep_delay; + // powerDef sleep_power; + const Area &cell; + bool is_sleep_tx; + double V_delta; + + // void compute_area(); + double compute_penalty(); // return outrisetime + + void leakage_feedback(double){}; + ~Sleep_tx(){}; +}; + +} // namespace cacti + +#endif /* POWERGATING_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/router.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/router.cc new file mode 100644 index 0000000000..7949ee6fc8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/router.cc @@ -0,0 +1,291 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "router.h" +using namespace cacti; + +Router::Router(double flit_size_, + double vc_buf, /* vc size = vc_buffer_size * flit_size */ + double vc_c, TechnologyParameter::DeviceType *dt, double I_, + double O_, double M_) + : flit_size(flit_size_), deviceType(dt), I(I_), O(O_), M(M_) { + vc_buffer_size = vc_buf; + vc_count = vc_c; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + double technology = g_ip->F_sz_um; + + Vdd = dt->Vdd; + + /*Crossbar parameters. Transmisson gate is employed for connector*/ + NTtr = 10 * technology * 1e-6 / 2; /*Transmission gate's nmos tr. length*/ + PTtr = 20 * technology * 1e-6 / 2; /* pmos tr. length*/ + wt = 15 * technology * 1e-6 / 2; /*track width*/ + ht = 15 * technology * 1e-6 / 2; /*track height*/ + // I = 5; /*Number of crossbar input ports*/ + // O = 5; /*Number of crossbar output ports*/ + NTi = 12.5 * technology * 1e-6 / 2; + PTi = 25 * technology * 1e-6 / 2; + + NTid = 60 * technology * 1e-6 / 2; // m + PTid = 120 * technology * 1e-6 / 2; // m + NTod = 60 * technology * 1e-6 / 2; // m + PTod = 120 * technology * 1e-6 / 2; // m + + calc_router_parameters(); +} + +Router::~Router() {} + +double // wire cap with triple spacing +Router::Cw3(double length) { + Wire wc(g_ip->wt, length, 1, 3, 3); + return (wc.wire_cap(length)); +} + +/*Function to calculate the gate capacitance*/ +double Router::gate_cap(double w) { + return (double)gate_C(w * 1e6 /*u*/, 0); +} + +/*Function to calculate the diffusion capacitance*/ +double Router::diff_cap(double w, int type /*0 for n-mos and 1 for p-mos*/, + double s /*number of stacking transistors*/) { + return (double)drain_C_(w * 1e6 /*u*/, type, (int)s, 1, g_tp.cell_h_def); +} + +/*crossbar related functions */ + +// Model for simple transmission gate +double Router::transmission_buf_inpcap() { + return diff_cap(NTtr, 0, 1) + diff_cap(PTtr, 1, 1); +} + +double Router::transmission_buf_outcap() { + return diff_cap(NTtr, 0, 1) + diff_cap(PTtr, 1, 1); +} + +double Router::transmission_buf_ctrcap() { + return gate_cap(NTtr) + gate_cap(PTtr); +} + +double Router::crossbar_inpline() { + return (Cw3(O * flit_size * wt) + O * transmission_buf_inpcap() + + gate_cap(NTid) + gate_cap(PTid) + diff_cap(NTid, 0, 1) + + diff_cap(PTid, 1, 1)); +} + +double Router::crossbar_outline() { + return (Cw3(I * flit_size * ht) + I * transmission_buf_outcap() + + gate_cap(NTod) + gate_cap(PTod) + diff_cap(NTod, 0, 1) + + diff_cap(PTod, 1, 1)); +} + +double Router::crossbar_ctrline() { + return (Cw3(0.5 * O * flit_size * wt) + + flit_size * transmission_buf_ctrcap() + diff_cap(NTi, 0, 1) + + diff_cap(PTi, 1, 1) + gate_cap(NTi) + gate_cap(PTi)); +} + +double Router::tr_crossbar_power() { + return (crossbar_inpline() * Vdd * Vdd * flit_size / 2 + + crossbar_outline() * Vdd * Vdd * flit_size / 2) * + 2; +} + +void Router::buffer_stats() { + DynamicParameter dyn_p; + dyn_p.is_tag = false; + dyn_p.pure_cam = false; + dyn_p.fully_assoc = false; + dyn_p.pure_ram = true; + dyn_p.is_dram = false; + dyn_p.is_main_mem = false; + dyn_p.num_subarrays = 1; + dyn_p.num_mats = 1; + dyn_p.Ndbl = 1; + dyn_p.Ndwl = 1; + dyn_p.Nspd = 1; + dyn_p.deg_bl_muxing = 1; + dyn_p.deg_senseamp_muxing_non_associativity = 1; + dyn_p.Ndsam_lev_1 = 1; + dyn_p.Ndsam_lev_2 = 1; + dyn_p.Ndcm = 1; + dyn_p.number_addr_bits_mat = 8; + dyn_p.number_way_select_signals_mat = 1; + dyn_p.number_subbanks_decode = 0; + dyn_p.num_act_mats_hor_dir = 1; + dyn_p.V_b_sense = Vdd; // FIXME check power calc. + dyn_p.ram_cell_tech_type = 0; + dyn_p.num_r_subarray = (int)vc_buffer_size; + dyn_p.num_c_subarray = (int)flit_size * (int)vc_count; + dyn_p.num_mats_h_dir = 1; + dyn_p.num_mats_v_dir = 1; + dyn_p.num_do_b_subbank = (int)flit_size; + dyn_p.num_di_b_subbank = (int)flit_size; + dyn_p.num_do_b_mat = (int)flit_size; + dyn_p.num_di_b_mat = (int)flit_size; + dyn_p.num_do_b_mat = (int)flit_size; + dyn_p.num_di_b_mat = (int)flit_size; + dyn_p.num_do_b_bank_per_port = (int)flit_size; + dyn_p.num_di_b_bank_per_port = (int)flit_size; + dyn_p.out_w = (int)flit_size; + + dyn_p.use_inp_params = 1; + dyn_p.num_wr_ports = (unsigned int)vc_count; + dyn_p.num_rd_ports = + 1; //(unsigned int) vc_count;//based on Bill Dally's book + dyn_p.num_rw_ports = 0; + dyn_p.num_se_rd_ports = 0; + dyn_p.num_search_ports = 0; + + dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * + (dyn_p.num_wr_ports + dyn_p.num_rw_ports - + 1 + dyn_p.num_rd_ports); + dyn_p.cell.w = + g_tp.sram.b_w + + 2 * g_tp.wire_outside_mat.pitch * + (dyn_p.num_rw_ports - 1 + + (dyn_p.num_rd_ports - dyn_p.num_se_rd_ports) + dyn_p.num_wr_ports) + + g_tp.wire_outside_mat.pitch * dyn_p.num_se_rd_ports; + + Mat buff(dyn_p); + buff.compute_delays(0); + buff.compute_power_energy(); + buffer.power.readOp = buff.power.readOp; + buffer.power.writeOp = buffer.power.readOp; // FIXME + buffer.area = buff.area; +} + +void Router::cb_stats() { + if (1) { + Crossbar c_b(I, O, flit_size); + c_b.compute_power(); + crossbar.delay = c_b.delay; + crossbar.power.readOp.dynamic = c_b.power.readOp.dynamic; + crossbar.power.readOp.leakage = c_b.power.readOp.leakage; + crossbar.power.readOp.gate_leakage = c_b.power.readOp.gate_leakage; + crossbar.area = c_b.area; + // c_b.print_crossbar(); + } + else { + crossbar.power.readOp.dynamic = tr_crossbar_power(); + crossbar.power.readOp.leakage = + flit_size * I * O * + cmos_Isub_leakage(NTtr * g_tp.min_w_nmos_, PTtr * min_w_pmos, 1, tg); + crossbar.power.readOp.gate_leakage = + flit_size * I * O * + cmos_Ig_leakage(NTtr * g_tp.min_w_nmos_, PTtr * min_w_pmos, 1, tg); + } +} + +void Router::get_router_power() { + /* calculate buffer stats */ + buffer_stats(); + + /* calculate cross-bar stats */ + cb_stats(); + + /* calculate arbiter stats */ + Arbiter vcarb(vc_count, flit_size, buffer.area.w); + Arbiter cbarb(I, flit_size, crossbar.area.w); + vcarb.compute_power(); + cbarb.compute_power(); + arbiter.power.readOp.dynamic = + vcarb.power.readOp.dynamic * I + cbarb.power.readOp.dynamic * O; + arbiter.power.readOp.leakage = + vcarb.power.readOp.leakage * I + cbarb.power.readOp.leakage * O; + arbiter.power.readOp.gate_leakage = + vcarb.power.readOp.gate_leakage * I + cbarb.power.readOp.gate_leakage * O; + + // arb_stats(); + power.readOp.dynamic = + ((buffer.power.readOp.dynamic + buffer.power.writeOp.dynamic) + + crossbar.power.readOp.dynamic + arbiter.power.readOp.dynamic) * + MIN(I, O) * M; + double pppm_t[4] = {1, I, I, 1}; + power = power + + (buffer.power * pppm_t + crossbar.power + arbiter.power) * pppm_lkg; +} + +void Router::get_router_delay() { + FREQUENCY = 5; // move this to config file --TODO + cycle_time = (1 / (double)FREQUENCY) * 1e3; // ps + delay = 4; + max_cyc = 17 * g_tp.FO4; // s + max_cyc *= 1e12; // ps + if (cycle_time < max_cyc) { + FREQUENCY = (1 / max_cyc) * 1e3; // GHz + } +} + +void Router::get_router_area() { + area.h = I * buffer.area.h; + area.w = buffer.area.w + crossbar.area.w; +} + +void Router::calc_router_parameters() { + /* calculate router frequency and pipeline cycles */ + get_router_delay(); + + /* router power stats */ + get_router_power(); + + /* area stats */ + get_router_area(); +} + +void Router::print_router() { + cout << "\n\nRouter stats:\n"; + cout << "\tRouter Area - " << area.get_area() * 1e-6 << "(mm^2)\n"; + cout << "\tMaximum possible network frequency - " << (1 / max_cyc) * 1e3 + << "GHz\n"; + cout << "\tNetwork frequency - " << FREQUENCY << " GHz\n"; + cout << "\tNo. of Virtual channels - " << vc_count << "\n"; + cout << "\tNo. of pipeline stages - " << delay << endl; + cout << "\tLink bandwidth - " << flit_size << " (bits)\n"; + cout << "\tNo. of buffer entries per virtual channel - " << vc_buffer_size + << "\n"; + cout << "\tSimple buffer Area - " << buffer.area.get_area() * 1e-6 + << "(mm^2)\n"; + cout << "\tSimple buffer access (Read) - " + << buffer.power.readOp.dynamic * 1e9 << " (nJ)\n"; + cout << "\tSimple buffer leakage - " << buffer.power.readOp.leakage * 1e3 + << " (mW)\n"; + cout << "\tCrossbar Area - " << crossbar.area.get_area() * 1e-6 << "(mm^2)\n"; + cout << "\tCross bar access energy - " << crossbar.power.readOp.dynamic * 1e9 + << " (nJ)\n"; + cout << "\tCross bar leakage power - " << crossbar.power.readOp.leakage * 1e3 + << " (mW)\n"; + cout << "\tArbiter access energy (VC arb + Crossbar arb) - " + << arbiter.power.readOp.dynamic * 1e9 << " (nJ)\n"; + cout << "\tArbiter leakage (VC arb + Crossbar arb) - " + << arbiter.power.readOp.leakage * 1e3 << " (mW)\n"; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/router.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/router.h new file mode 100644 index 0000000000..feed61fe94 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/router.h @@ -0,0 +1,109 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __ROUTER_H__ +#define __ROUTER_H__ + +#include +#include +#include "arbiter.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "crossbar.h" +#include "mat.h" +#include "parameter.h" +#include "wire.h" + +namespace cacti { + +class Router : public Component { + public: + Router(double flit_size_, + double vc_buf, /* vc size = vc_buffer_size * flit_size */ + double vc_count, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global), + double I_ = 5, double O_ = 5, double M_ = 0.6); + ~Router(); + + void print_router(); + + Component arbiter, crossbar, buffer; + + double cycle_time, max_cyc; + double flit_size; + double vc_count; + double vc_buffer_size; /* vc size = vc_buffer_size * flit_size */ + + private: + TechnologyParameter::DeviceType *deviceType; + double FREQUENCY; // move this to config file --TODO + double Cw3(double len); + double gate_cap(double w); + double diff_cap(double w, int type /*0 for n-mos and 1 for p-mos*/, + double stack); + enum Wire_type wtype; + enum Wire_placement wire_placement; + // corssbar + double NTtr, PTtr, wt, ht, I, O, NTi, PTi, NTid, PTid, NTod, PTod, TriS1, + TriS2; + double M; // network load + double transmission_buf_inpcap(); + double transmission_buf_outcap(); + double transmission_buf_ctrcap(); + double crossbar_inpline(); + double crossbar_outline(); + double crossbar_ctrline(); + double tr_crossbar_power(); + void cb_stats(); + double arb_power(); + void arb_stats(); + double buffer_params(); + void buffer_stats(); + + // arbiter + + // buffer + + // router params + double Vdd; + + void calc_router_parameters(); + void get_router_area(); + void get_router_power(); + void get_router_delay(); + + double min_w_pmos; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/subarray.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/subarray.cc new file mode 100644 index 0000000000..41ba1db5e8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/subarray.cc @@ -0,0 +1,222 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include +#include + +#include "subarray.h" +using namespace cacti; + +Subarray::Subarray(const DynamicParameter &dp_, bool is_fa_) + : dp(dp_), + num_rows(dp.num_r_subarray), + num_cols(dp.num_c_subarray), + num_cols_fa_cam(dp.tag_num_c_subarray), + num_cols_fa_ram(dp.data_num_c_subarray), + cell(dp.cell), + cam_cell(dp.cam_cell), + is_fa(is_fa_) { + // num_cols=7; + // cout<<"num_cols ="<< num_cols <add_ecc_b_ ? (int)ceil(num_cols / num_bits_per_ecc_b_) + : 0); // ECC overhead + uint32_t ram_num_cells_wl_stitching = + (dp.ram_cell_tech_type == lp_dram) + ? dram_num_cells_wl_stitching_ + : (dp.ram_cell_tech_type == comm_dram) + ? comm_dram_num_cells_wl_stitching_ + : sram_num_cells_wl_stitching_; + + area.h = cell.h * num_rows; + + area.w = cell.w * num_cols + + ceil(num_cols / ram_num_cells_wl_stitching) * + g_tp.ram_wl_stitching_overhead_; // stitching overhead + } + else // cam fa + { + // should not add dummy row here since the dummy row do not need decoder + if (is_fa) // fully associative cache + { + num_cols_fa_cam += g_ip->add_ecc_b_ + ? (int)ceil(num_cols_fa_cam / num_bits_per_ecc_b_) + : 0; + num_cols_fa_ram += + (g_ip->add_ecc_b_ ? (int)ceil(num_cols_fa_ram / num_bits_per_ecc_b_) + : 0); + num_cols = num_cols_fa_cam + num_cols_fa_ram; + } + else { + num_cols_fa_cam += g_ip->add_ecc_b_ + ? (int)ceil(num_cols_fa_cam / num_bits_per_ecc_b_) + : 0; + num_cols_fa_ram = 0; + num_cols = num_cols_fa_cam; + } + + area.h = cam_cell.h * (num_rows + 1); // height of subarray is decided by + // CAM array. blank space in sram + // array are filled with dummy cells + area.w = cam_cell.w * num_cols_fa_cam + cell.w * num_cols_fa_ram + + ceil((num_cols_fa_cam + num_cols_fa_ram) / + sram_num_cells_wl_stitching_) * + g_tp.ram_wl_stitching_overhead_ + + 16 * g_tp.wire_local.pitch // the overhead for the NAND gate to + // connect the two halves + + + 128 * g_tp.wire_local.pitch; // the overhead for the drivers + // from matchline to wordline of RAM + } + + assert(area.h > 0); + assert(area.w > 0); + compute_C(); +} + +Subarray::~Subarray() {} + +double Subarray::get_total_cell_area() { + // return (is_fa==false? cell.get_area() * num_rows * num_cols + // //: cam_cell.h*(num_rows+1)*(num_cols_fa_cam + + // sram_cell.get_area()*num_cols_fa_ram)); : + // cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + num_cols_fa_ram)); + // //: cam_cell.get_area()*(num_rows+1)*num_cols_fa_cam + + // sram_cell.get_area()*(num_rows+1)*num_cols_fa_ram);//for FA, this area does + // not include the dummy cells in SRAM arrays. + + if (!(is_fa || dp.pure_cam)) + return (cell.get_area() * num_rows * num_cols); + else if (is_fa) { // for FA, this area includes the dummy cells in SRAM + // arrays. + // return (cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + + // num_cols_fa_ram)); cout<<"diff" + // < +#include "basic_circuit.h" + +#include "parameter.h" + +namespace cacti { + +double wire_resistance(double resistivity, double wire_width, + double wire_thickness, double barrier_thickness, + double dishing_thickness, double alpha_scatter) { + double resistance; + resistance = alpha_scatter * resistivity / + ((wire_thickness - barrier_thickness - dishing_thickness) * + (wire_width - 2 * barrier_thickness)); + return (resistance); +} + +double wire_capacitance(double wire_width, double wire_thickness, + double wire_spacing, double ild_thickness, + double miller_value, double horiz_dielectric_constant, + double vert_dielectric_constant, double fringe_cap) { + double vertical_cap, sidewall_cap, total_cap; + vertical_cap = 2 * PERMITTIVITY_FREE_SPACE * vert_dielectric_constant * + wire_width / ild_thickness; + sidewall_cap = 2 * PERMITTIVITY_FREE_SPACE * miller_value * + horiz_dielectric_constant * wire_thickness / wire_spacing; + total_cap = vertical_cap + sidewall_cap + fringe_cap; + return (total_cap); +} + +void init_tech_params(double technology, bool is_tag) { + int iter, tech, tech_lo, tech_hi; + double curr_alpha, curr_vpp = 0.; + double wire_width, wire_thickness, wire_spacing, fringe_cap, + pmos_to_nmos_sizing_r; + // double aspect_ratio,ild_thickness, miller_value = 1.5, + // horiz_dielectric_constant, vert_dielectric_constant; + double barrier_thickness, dishing_thickness, alpha_scatter; + double curr_vdd_dram_cell = 0.; + double curr_v_th_dram_access_transistor = 0.; + double curr_I_on_dram_cell = 0.; + double curr_c_dram_cell = 0.; + + uint32_t ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type + : g_ip->data_arr_ram_cell_tech_type; + uint32_t peri_global_tech_type = (is_tag) + ? g_ip->tag_arr_peri_global_tech_type + : g_ip->data_arr_peri_global_tech_type; + + technology = technology * 1000.0; // in the unit of nm + + // initialize parameters + g_tp.reset(); + double gmp_to_gmn_multiplier_periph_global = 0; + + double curr_Wmemcella_dram = 0.; + double curr_Wmemcellpmos_dram = 0.; + double curr_Wmemcellnmos_dram = 0.; + double curr_area_cell_dram = 0.; + double curr_asp_ratio_cell_dram = 0.; + double curr_Wmemcella_sram = 0.; + double curr_Wmemcellpmos_sram = 0.; + double curr_Wmemcellnmos_sram = 0.; + double curr_area_cell_sram = 0.; + double curr_asp_ratio_cell_sram = 0.; + double curr_I_off_dram_cell_worst_case_length_temp = 0.; + double curr_Wmemcella_cam = 0.; + double curr_Wmemcellpmos_cam = 0.; + double curr_Wmemcellnmos_cam = 0.; + double curr_area_cell_cam = 0.; + double curr_asp_ratio_cell_cam = 0.; + double SENSE_AMP_D = 0.; + double SENSE_AMP_P = 0.; + double area_cell_dram = 0; + double asp_ratio_cell_dram = 0; + double area_cell_sram = 0; + double asp_ratio_cell_sram = 0; + double area_cell_cam = 0; + double asp_ratio_cell_cam = 0; + double mobility_eff_periph_global = 0; + double Vdsat_periph_global = 0; + double nmos_effective_resistance_multiplier; + double width_dram_access_transistor; + + double curr_logic_scaling_co_eff = + 0; // This is based on the reported + // numbers of Intel Merom 65nm, + // Penryn45nm and IBM cell 90/65/45 date + double curr_core_tx_density = + 0; // this is density per um^2; 90, ...22nm based on Intel Penryn + double curr_chip_layout_overhead = 0; + double curr_macro_layout_overhead = 0; + double curr_sckt_co_eff = 0; + + if (technology < 181 && technology > 179) { + tech_lo = 180; + tech_hi = 180; + } + else if (technology < 91 && technology > 89) { + tech_lo = 90; + tech_hi = 90; + } + else if (technology < 66 && technology > 64) { + tech_lo = 65; + tech_hi = 65; + } + else if (technology < 46 && technology > 44) { + tech_lo = 45; + tech_hi = 45; + } + else if (technology < 33 && technology > 31) { + tech_lo = 32; + tech_hi = 32; + } + else if (technology < 23 && technology > 21) { + tech_lo = 22; + tech_hi = 22; + if (ram_cell_tech_type == 3) { + cout << "current version does not support eDRAM technologies at 22nm" + << endl; + exit(0); + } + } + // else if (technology < 17 && technology > 15) + // { + // tech_lo = 16; + // tech_hi = 16; + // } + else if (technology < 180 && technology > 90) { + tech_lo = 180; + tech_hi = 90; + } + else if (technology < 90 && technology > 65) { + tech_lo = 90; + tech_hi = 65; + } + else if (technology < 65 && technology > 45) { + tech_lo = 65; + tech_hi = 45; + } + else if (technology < 45 && technology > 32) { + tech_lo = 45; + tech_hi = 32; + } + else if (technology < 32 && technology > 22) { + tech_lo = 32; + tech_hi = 22; + } + // else if (technology < 22 && technology > 16) + // { + // tech_lo = 22; + // tech_hi = 16; + // } + else { + cout << "Invalid technology nodes" << endl; + exit(0); + } + + double vdd[NUMBER_TECH_FLAVORS]; // default vdd from itrs + double vdd_real[NUMBER_TECH_FLAVORS]; // real vdd defined by user, this is + // for changing vdd from itrs; it + // actually does not dependent on + // technology node since it is user + // defined + double alpha_power_law[NUMBER_TECH_FLAVORS]; // co-efficient for ap-law + double Lphy[NUMBER_TECH_FLAVORS]; + double Lelec[NUMBER_TECH_FLAVORS]; + double t_ox[NUMBER_TECH_FLAVORS]; + double v_th[NUMBER_TECH_FLAVORS]; + double c_ox[NUMBER_TECH_FLAVORS]; + double mobility_eff[NUMBER_TECH_FLAVORS]; + double Vdsat[NUMBER_TECH_FLAVORS]; + double c_g_ideal[NUMBER_TECH_FLAVORS]; + double c_fringe[NUMBER_TECH_FLAVORS]; + double c_junc[NUMBER_TECH_FLAVORS]; + double I_on_n[NUMBER_TECH_FLAVORS]; + // double I_on_p[NUMBER_TECH_FLAVORS]; + double Rnchannelon[NUMBER_TECH_FLAVORS]; + double Rpchannelon[NUMBER_TECH_FLAVORS]; + double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS]; + double I_off_n[NUMBER_TECH_FLAVORS][101]; + double I_g_on_n[NUMBER_TECH_FLAVORS][101]; + // double I_off_p[NUMBER_TECH_FLAVORS][101]; + double gmp_to_gmn_multiplier[NUMBER_TECH_FLAVORS]; + // double curr_sckt_co_eff[NUMBER_TECH_FLAVORS]; + double long_channel_leakage_reduction[NUMBER_TECH_FLAVORS]; + + for (iter = 0; iter <= 1; ++iter) { + // linear interpolation + if (iter == 0) { + tech = tech_lo; + if (tech_lo == tech_hi) { + curr_alpha = 1; + } + else { + curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); + } + } + else { + tech = tech_hi; + if (tech_lo == tech_hi) { + break; + } + else { + curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); + } + } + + if (tech == 180) { + // 180nm technology-node. Corresponds to year 1999 in ITRS + // Only HP transistor was of interest that 180nm since leakage power was + // not a big issue. Performance was the king MASTAR does not contain data + // for 0.18um process. The following parameters are projected based on + // ITRS 2000 update and IBM 0.18 Cu Spice input 180nm does not support + // DVS + bool Aggre_proj = false; + SENSE_AMP_D = .28e-9; // s + SENSE_AMP_P = 14.7e-15; // J + vdd[0] = 1.5; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.4; + Lphy[0] = 0.12; // Lphy is the physical gate-length. micron + Lelec[0] = 0.10; // Lelec is the electrical gate-length. micron + t_ox[0] = 1.2e-3 * (Aggre_proj ? 1.9 / 1.2 : 2); // micron + v_th[0] = Aggre_proj ? 0.36 : 0.4407; // V + c_ox[0] = 1.79e-14 * (Aggre_proj ? 1.9 / 1.2 : 2); // F/micron2 + mobility_eff[0] = 302.16 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 0.128 * 2; // V + c_g_ideal[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 6.64e-16; // F/micron + c_fringe[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 0.08e-15; // F/micron + c_junc[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 1e-15; // F/micron2 + I_on_n[0] = 750e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); // A/micron + // I_on_p[0] = 350e-6; // A/micron + // Note that nmos_effective_resistance_multiplier, + // n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are + // calculated offline + nmos_effective_resistance_multiplier = 1.54; + n_to_p_eff_curr_drv_ratio[0] = 2.45; + gmp_to_gmn_multiplier[0] = 1.22; + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1; + I_off_n[0][0] = 7e-10; // A/micron + I_off_n[0][10] = 8.26e-10; + I_off_n[0][20] = 9.74e-10; + I_off_n[0][30] = 1.15e-9; + I_off_n[0][40] = 1.35e-9; + I_off_n[0][50] = 1.60e-9; + I_off_n[0][60] = 1.88e-9; + I_off_n[0][70] = 2.29e-9; + I_off_n[0][80] = 2.70e-9; + I_off_n[0][90] = 3.19e-9; + I_off_n[0][100] = 3.76e-9; + + I_g_on_n[0][0] = 1.65e-10; // A/micron + I_g_on_n[0][10] = 1.65e-10; + I_g_on_n[0][20] = 1.65e-10; + I_g_on_n[0][30] = 1.65e-10; + I_g_on_n[0][40] = 1.65e-10; + I_g_on_n[0][50] = 1.65e-10; + I_g_on_n[0][60] = 1.65e-10; + I_g_on_n[0][70] = 1.65e-10; + I_g_on_n[0][80] = 1.65e-10; + I_g_on_n[0][90] = 1.65e-10; + I_g_on_n[0][100] = 1.65e-10; + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; // 360 + curr_asp_ratio_cell_cam = 2.92; // 2.5 + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 1.5; // linear scaling from 90nm + curr_core_tx_density = 1.25 * 0.7 * 0.7 * 0.4; + curr_sckt_co_eff = 1.11; + curr_chip_layout_overhead = + 1.0; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.0; // EDA placement and routing tool rule of thumb + } + + if (tech == 90) { + SENSE_AMP_D = .28e-9; // s + SENSE_AMP_P = 14.7e-15; // J + // 90nm technology-node. Corresponds to year 2004 in ITRS + // ITRS HP device type + vdd[0] = 1.2; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.34; + Lphy[0] = 0.037; // Lphy is the physical gate-length. micron + Lelec[0] = 0.0266; // Lelec is the electrical gate-length. micron + t_ox[0] = 1.2e-3; // micron + v_th[0] = 0.23707; // V + c_ox[0] = 1.79e-14; // F/micron2 + mobility_eff[0] = 342.16 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 0.128; // V + c_g_ideal[0] = 6.64e-16; // F/micron + c_fringe[0] = 0.08e-15; // F/micron + c_junc[0] = 1e-15; // F/micron2 + I_on_n[0] = 1076.9e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); // A/micron with ap-law + // applied for dvs and + // arbitrary vdd + // I_on_p[0] = 712.6e-6; // A/micron + // Note that nmos_effective_resistance_multiplier, + // n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are + // calculated offline + nmos_effective_resistance_multiplier = 1.54; + n_to_p_eff_curr_drv_ratio[0] = 2.45; + gmp_to_gmn_multiplier[0] = 1.22; + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd_real[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1; + I_off_n[0][0] = 3.24e-8 * pow(vdd_real[0] / (vdd[0]), 4); // A/micron + I_off_n[0][10] = 4.01e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][20] = 4.90e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][30] = 5.92e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][40] = 7.08e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][50] = 8.38e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][60] = 9.82e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][70] = 1.14e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][80] = 1.29e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][90] = 1.43e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][100] = 1.54e-7 * pow(vdd_real[0] / (vdd[0]), 4); + + I_g_on_n[0][0] = 1.65e-8; // A/micron + I_g_on_n[0][10] = 1.65e-8; + I_g_on_n[0][20] = 1.65e-8; + I_g_on_n[0][30] = 1.65e-8; + I_g_on_n[0][40] = 1.65e-8; + I_g_on_n[0][50] = 1.65e-8; + I_g_on_n[0][60] = 1.65e-8; + I_g_on_n[0][70] = 1.65e-8; + I_g_on_n[0][80] = 1.65e-8; + I_g_on_n[0][90] = 1.65e-8; + I_g_on_n[0][100] = 1.65e-8; + + // ITRS LSTP device type + vdd[1] = 1.3; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; + alpha_power_law[1] = 1.47; + Lphy[1] = 0.075; + Lelec[1] = 0.0486; + t_ox[1] = 2.2e-3; + v_th[1] = 0.48203; + c_ox[1] = 1.22e-14; + mobility_eff[1] = 356.76 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 0.373; + c_g_ideal[1] = 9.15e-16; + c_fringe[1] = 0.08e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 503.6e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = 235.1e-6; + nmos_effective_resistance_multiplier = 1.92; + n_to_p_eff_curr_drv_ratio[1] = 2.44; + gmp_to_gmn_multiplier[1] = 0.88; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1; + I_off_n[1][0] = 2.81e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][10] = 4.76e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][20] = 7.82e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][30] = 1.25e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][40] = 1.94e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][50] = 2.94e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][60] = 4.36e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][70] = 6.32e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][80] = 8.95e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][90] = 1.25e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][100] = 1.7e-10 * pow(vdd_real[1] / (vdd[1]), 4); + + I_g_on_n[1][0] = 3.87e-11; // A/micron + I_g_on_n[1][10] = 3.87e-11; + I_g_on_n[1][20] = 3.87e-11; + I_g_on_n[1][30] = 3.87e-11; + I_g_on_n[1][40] = 3.87e-11; + I_g_on_n[1][50] = 3.87e-11; + I_g_on_n[1][60] = 3.87e-11; + I_g_on_n[1][70] = 3.87e-11; + I_g_on_n[1][80] = 3.87e-11; + I_g_on_n[1][90] = 3.87e-11; + I_g_on_n[1][100] = 3.87e-11; + + // ITRS LOP device type + vdd[2] = 0.9; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; + alpha_power_law[2] = 1.55; + Lphy[2] = 0.053; + Lelec[2] = 0.0354; + t_ox[2] = 1.5e-3; + v_th[2] = 0.30764; + c_ox[2] = 1.59e-14; + mobility_eff[2] = 460.39 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 0.113; + c_g_ideal[2] = 8.45e-16; + c_fringe[2] = 0.08e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 386.6e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = 209.7e-6; + nmos_effective_resistance_multiplier = 1.77; + n_to_p_eff_curr_drv_ratio[2] = 2.54; + gmp_to_gmn_multiplier[2] = 0.98; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1; + I_off_n[2][0] = 2.14e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 2.9e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 3.87e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 5.07e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 6.54e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 8.27e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 1.02e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.20e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 1.36e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 1.52e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 1.73e-8 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 4.31e-8; // A/micron + I_g_on_n[2][10] = 4.31e-8; + I_g_on_n[2][20] = 4.31e-8; + I_g_on_n[2][30] = 4.31e-8; + I_g_on_n[2][40] = 4.31e-8; + I_g_on_n[2][50] = 4.31e-8; + I_g_on_n[2][60] = 4.31e-8; + I_g_on_n[2][70] = 4.31e-8; + I_g_on_n[2][80] = 4.31e-8; + I_g_on_n[2][90] = 4.31e-8; + I_g_on_n[2][100] = 4.31e-8; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.2; + Lphy[3] = 0.12; + Lelec[3] = 0.0756; + curr_v_th_dram_access_transistor = 0.4545; + width_dram_access_transistor = 0.14; + curr_I_on_dram_cell = 45e-6; + curr_I_off_dram_cell_worst_case_length_temp = 21.1e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 0.168; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.6; + t_ox[3] = 2.2e-3; + v_th[3] = 0.4545; + c_ox[3] = 1.22e-14; + mobility_eff[3] = 323.95 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.3; + c_g_ideal[3] = 1.47e-15; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 321.6e-6; + // I_on_p[3] = 203.3e-6; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 1.95; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.42e-11; + I_off_n[3][10] = 2.25e-11; + I_off_n[3][20] = 3.46e-11; + I_off_n[3][30] = 5.18e-11; + I_off_n[3][40] = 7.58e-11; + I_off_n[3][50] = 1.08e-10; + I_off_n[3][60] = 1.51e-10; + I_off_n[3][70] = 2.02e-10; + I_off_n[3][80] = 2.57e-10; + I_off_n[3][90] = 3.14e-10; + I_off_n[3][100] = 3.85e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.6; + Lphy[3] = 0.09; + Lelec[3] = 0.0576; + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.09; + curr_I_on_dram_cell = 20e-6; + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.09 * 0.09; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 3.7; + t_ox[3] = 5.5e-3; + v_th[3] = 1.0; + c_ox[3] = 5.65e-15; + mobility_eff[3] = 302.2 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.32; + c_g_ideal[3] = 5.08e-16; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1094.3e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.62; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 5.80e-15; + I_off_n[3][10] = 1.21e-14; + I_off_n[3][20] = 2.42e-14; + I_off_n[3][30] = 4.65e-14; + I_off_n[3][40] = 8.60e-14; + I_off_n[3][50] = 1.54e-13; + I_off_n[3][60] = 2.66e-13; + I_off_n[3][70] = 4.45e-13; + I_off_n[3][80] = 7.17e-13; + I_off_n[3][90] = 1.11e-12; + I_off_n[3][100] = 1.67e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; // 360 + curr_asp_ratio_cell_cam = 2.92; // 2.5 + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 1; + curr_core_tx_density = 1.25 * 0.7 * 0.7; + curr_sckt_co_eff = 1.1539; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 65) { // 65nm technology-node. Corresponds to year 2007 in ITRS + // ITRS HP device type + SENSE_AMP_D = .2e-9; // s + SENSE_AMP_P = 5.7e-15; // J + vdd[0] = 1.1; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.27; + Lphy[0] = 0.025; + Lelec[0] = 0.019; + t_ox[0] = 1.1e-3; + v_th[0] = .19491; + c_ox[0] = 1.88e-14; + mobility_eff[0] = 436.24 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[0] = 7.71e-2; + c_g_ideal[0] = 4.69e-16; + c_fringe[0] = 0.077e-15; + c_junc[0] = 1e-15; + I_on_n[0] = 1197.2e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); + // I_on_p[0] = 870.8e-6; + nmos_effective_resistance_multiplier = 1.50; + n_to_p_eff_curr_drv_ratio[0] = 2.41; + gmp_to_gmn_multiplier[0] = 1.38; + Rnchannelon[0] = + nmos_effective_resistance_multiplier * vdd_real[0] / I_on_n[0]; + Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; + long_channel_leakage_reduction[0] = 1 / 3.74; + // Using MASTAR, @380K, increase Lgate until Ion reduces to 90% or Lgate + // increase by 10%, whichever comes first Ioff(Lgate normal)/Ioff(Lgate + // long)= 3.74. + I_off_n[0][0] = 1.96e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][10] = 2.29e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][20] = 2.66e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][30] = 3.05e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][40] = 3.49e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][50] = 3.95e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][60] = 4.45e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][70] = 4.97e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][80] = 5.48e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][90] = 5.94e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][100] = 6.3e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_g_on_n[0][0] = 4.09e-8; // A/micron + I_g_on_n[0][10] = 4.09e-8; + I_g_on_n[0][20] = 4.09e-8; + I_g_on_n[0][30] = 4.09e-8; + I_g_on_n[0][40] = 4.09e-8; + I_g_on_n[0][50] = 4.09e-8; + I_g_on_n[0][60] = 4.09e-8; + I_g_on_n[0][70] = 4.09e-8; + I_g_on_n[0][80] = 4.09e-8; + I_g_on_n[0][90] = 4.09e-8; + I_g_on_n[0][100] = 4.09e-8; + + // ITRS LSTP device type + vdd[1] = 1.2; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; // TODO + alpha_power_law[1] = 1.40; + Lphy[1] = 0.045; + Lelec[1] = 0.0298; + t_ox[1] = 1.9e-3; + v_th[1] = 0.52354; + c_ox[1] = 1.36e-14; + mobility_eff[1] = 341.21 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 0.128; + c_g_ideal[1] = 6.14e-16; + c_fringe[1] = 0.08e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 519.2e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = 266e-6; + nmos_effective_resistance_multiplier = 1.96; + n_to_p_eff_curr_drv_ratio[1] = 2.23; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1 / 2.82; + I_off_n[1][0] = 9.12e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][10] = 1.49e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][20] = 2.36e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][30] = 3.64e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][40] = 5.48e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][50] = 8.05e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][60] = 1.15e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][70] = 1.59e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][80] = 2.1e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][90] = 2.62e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][100] = 3.21e-10 * pow(vdd_real[1] / (vdd[1]), 4); + + I_g_on_n[1][0] = 1.09e-10; // A/micron + I_g_on_n[1][10] = 1.09e-10; + I_g_on_n[1][20] = 1.09e-10; + I_g_on_n[1][30] = 1.09e-10; + I_g_on_n[1][40] = 1.09e-10; + I_g_on_n[1][50] = 1.09e-10; + I_g_on_n[1][60] = 1.09e-10; + I_g_on_n[1][70] = 1.09e-10; + I_g_on_n[1][80] = 1.09e-10; + I_g_on_n[1][90] = 1.09e-10; + I_g_on_n[1][100] = 1.09e-10; + + // ITRS LOP device type + vdd[2] = 0.8; + alpha_power_law[2] = 1.43; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; + Lphy[2] = 0.032; + Lelec[2] = 0.0216; + t_ox[2] = 1.2e-3; + v_th[2] = 0.28512; + c_ox[2] = 1.87e-14; + mobility_eff[2] = 495.19 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 0.292; + c_g_ideal[2] = 6e-16; + c_fringe[2] = 0.08e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 573.1e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = 340.6e-6; + nmos_effective_resistance_multiplier = 1.82; + n_to_p_eff_curr_drv_ratio[2] = 2.28; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1 / 2.05; + I_off_n[2][0] = 4.9e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 6.49e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 8.45e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 1.08e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 1.37e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 1.71e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 2.09e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 2.48e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 2.84e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 3.13e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 3.42e-8 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 9.61e-9; // A/micron + I_g_on_n[2][10] = 9.61e-9; + I_g_on_n[2][20] = 9.61e-9; + I_g_on_n[2][30] = 9.61e-9; + I_g_on_n[2][40] = 9.61e-9; + I_g_on_n[2][50] = 9.61e-9; + I_g_on_n[2][60] = 9.61e-9; + I_g_on_n[2][70] = 9.61e-9; + I_g_on_n[2][80] = 9.61e-9; + I_g_on_n[2][90] = 9.61e-9; + I_g_on_n[2][100] = 9.61e-9; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.2; + Lphy[3] = 0.12; + Lelec[3] = 0.0756; + curr_v_th_dram_access_transistor = 0.43806; + width_dram_access_transistor = 0.09; + curr_I_on_dram_cell = 36e-6; + curr_I_off_dram_cell_worst_case_length_temp = 19.6e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 0.11; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.6; + t_ox[3] = 2.2e-3; + v_th[3] = 0.43806; + c_ox[3] = 1.22e-14; + mobility_eff[3] = 328.32 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.43806; + c_g_ideal[3] = 1.46e-15; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 399.8e-6; + // I_on_p[3] = 243.4e-6; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 2.23e-11; + I_off_n[3][10] = 3.46e-11; + I_off_n[3][20] = 5.24e-11; + I_off_n[3][30] = 7.75e-11; + I_off_n[3][40] = 1.12e-10; + I_off_n[3][50] = 1.58e-10; + I_off_n[3][60] = 2.18e-10; + I_off_n[3][70] = 2.88e-10; + I_off_n[3][80] = 3.63e-10; + I_off_n[3][90] = 4.41e-10; + I_off_n[3][100] = 5.36e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.3; + Lphy[3] = 0.065; + Lelec[3] = 0.0426; + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.065; + curr_I_on_dram_cell = 20e-6; + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.065 * 0.065; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 3.3; + t_ox[3] = 5e-3; + v_th[3] = 1.0; + c_ox[3] = 6.16e-15; + mobility_eff[3] = 303.44 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.385; + c_g_ideal[3] = 4e-16; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1031e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.69; + n_to_p_eff_curr_drv_ratio[3] = 2.39; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.80e-14; + I_off_n[3][10] = 3.64e-14; + I_off_n[3][20] = 7.03e-14; + I_off_n[3][30] = 1.31e-13; + I_off_n[3][40] = 2.35e-13; + I_off_n[3][50] = 4.09e-13; + I_off_n[3][60] = 6.89e-13; + I_off_n[3][70] = 1.13e-12; + I_off_n[3][80] = 1.78e-12; + I_off_n[3][90] = 2.71e-12; + I_off_n[3][100] = 3.99e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = + 0.7; // Rather than scale proportionally to square of feature size, + // only scale linearly according to IBM cell processor + curr_core_tx_density = 1.25 * 0.7; + curr_sckt_co_eff = 1.1359; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 45) { // 45nm technology-node. Corresponds to year 2010 in ITRS + // ITRS HP device type + SENSE_AMP_D = .04e-9; // s + SENSE_AMP_P = 2.7e-15; // J + vdd[0] = 1.0; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; // TODO + alpha_power_law[0] = 1.21; + Lphy[0] = 0.018; + Lelec[0] = 0.01345; + t_ox[0] = 0.65e-3; + v_th[0] = .18035; + c_ox[0] = 3.77e-14; + mobility_eff[0] = 266.68 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[0] = 9.38E-2; + c_g_ideal[0] = 6.78e-16; + c_fringe[0] = 0.05e-15; + c_junc[0] = 1e-15; + I_on_n[0] = 2046.6e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); + // There are certain problems with the ITRS PMOS numbers in MASTAR for + // 45nm. So we are using 65nm values of n_to_p_eff_curr_drv_ratio and + // gmp_to_gmn_multiplier for 45nm + // I_on_p[0] = I_on_n[0] / 2; // This value is fixed arbitrarily + // but I_on_p + // is not being used in CACTI + nmos_effective_resistance_multiplier = 1.51; + n_to_p_eff_curr_drv_ratio[0] = 2.41; + gmp_to_gmn_multiplier[0] = 1.38; + Rnchannelon[0] = + nmos_effective_resistance_multiplier * vdd_real[0] / I_on_n[0]; + Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; + long_channel_leakage_reduction[0] = + 1 / 3.546; // Using MASTAR, @380K, increase Lgate until Ion reduces + // to 90%, Ioff(Lgate normal)/Ioff(Lgate long)= 3.74 + I_off_n[0][0] = 2.8e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][10] = 3.28e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][20] = 3.81e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][30] = 4.39e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][40] = 5.02e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][50] = 5.69e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][60] = 6.42e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][70] = 7.2e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][80] = 8.03e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][90] = 8.91e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][100] = 9.84e-7 * pow(vdd_real[0] / (vdd[0]), 4); + + I_g_on_n[0][0] = 3.59e-8; // A/micron + I_g_on_n[0][10] = 3.59e-8; + I_g_on_n[0][20] = 3.59e-8; + I_g_on_n[0][30] = 3.59e-8; + I_g_on_n[0][40] = 3.59e-8; + I_g_on_n[0][50] = 3.59e-8; + I_g_on_n[0][60] = 3.59e-8; + I_g_on_n[0][70] = 3.59e-8; + I_g_on_n[0][80] = 3.59e-8; + I_g_on_n[0][90] = 3.59e-8; + I_g_on_n[0][100] = 3.59e-8; + + // ITRS LSTP device type + vdd[1] = 1.1; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; + alpha_power_law[1] = 1.33; + Lphy[1] = 0.028; + Lelec[1] = 0.0212; + t_ox[1] = 1.4e-3; + v_th[1] = 0.50245; + c_ox[1] = 2.01e-14; + mobility_eff[1] = 363.96 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 9.12e-2; + c_g_ideal[1] = 5.18e-16; + c_fringe[1] = 0.08e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 666.2e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = I_on_n[1] / 2; + nmos_effective_resistance_multiplier = 1.99; + n_to_p_eff_curr_drv_ratio[1] = 2.23; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1 / 2.08; + I_off_n[1][0] = 1.01e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][10] = 1.65e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][20] = 2.62e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][30] = 4.06e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][40] = 6.12e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][50] = 9.02e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][60] = 1.3e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][70] = 1.83e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][80] = 2.51e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][90] = 3.29e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][100] = 4.1e-10 * pow(vdd_real[1] / (vdd[1]), 4); + + I_g_on_n[1][0] = 9.47e-12; // A/micron + I_g_on_n[1][10] = 9.47e-12; + I_g_on_n[1][20] = 9.47e-12; + I_g_on_n[1][30] = 9.47e-12; + I_g_on_n[1][40] = 9.47e-12; + I_g_on_n[1][50] = 9.47e-12; + I_g_on_n[1][60] = 9.47e-12; + I_g_on_n[1][70] = 9.47e-12; + I_g_on_n[1][80] = 9.47e-12; + I_g_on_n[1][90] = 9.47e-12; + I_g_on_n[1][100] = 9.47e-12; + + // ITRS LOP device type + vdd[2] = 0.7; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; // TODO + alpha_power_law[2] = 1.39; + Lphy[2] = 0.022; + Lelec[2] = 0.016; + t_ox[2] = 0.9e-3; + v_th[2] = 0.22599; + c_ox[2] = 2.82e-14; // F/micron2 + mobility_eff[2] = 508.9 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 5.71e-2; + c_g_ideal[2] = 6.2e-16; + c_fringe[2] = 0.073e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 748.9e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = I_on_n[2] / 2; + nmos_effective_resistance_multiplier = 1.76; + n_to_p_eff_curr_drv_ratio[2] = 2.28; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1 / 1.92; + I_off_n[2][0] = 4.03e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 5.02e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 6.18e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 7.51e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 9.04e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 1.08e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 1.27e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.47e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 1.66e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 1.84e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 2.03e-8 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 3.24e-8; // A/micron + I_g_on_n[2][10] = 4.01e-8; + I_g_on_n[2][20] = 4.90e-8; + I_g_on_n[2][30] = 5.92e-8; + I_g_on_n[2][40] = 7.08e-8; + I_g_on_n[2][50] = 8.38e-8; + I_g_on_n[2][60] = 9.82e-8; + I_g_on_n[2][70] = 1.14e-7; + I_g_on_n[2][80] = 1.29e-7; + I_g_on_n[2][90] = 1.43e-7; + I_g_on_n[2][100] = 1.54e-7; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.1; + Lphy[3] = 0.078; + Lelec[3] = 0.0504; // Assume Lelec is 30% lesser than Lphy for DRAM + // access and wordline transistors. + curr_v_th_dram_access_transistor = 0.44559; + width_dram_access_transistor = 0.079; + curr_I_on_dram_cell = 36e-6; // A + curr_I_off_dram_cell_worst_case_length_temp = 19.5e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.5; + t_ox[3] = 2.1e-3; + v_th[3] = 0.44559; + c_ox[3] = 1.41e-14; + mobility_eff[3] = 426.30 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.181; + c_g_ideal[3] = 1.10e-15; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 456e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 2.54e-11; + I_off_n[3][10] = 3.94e-11; + I_off_n[3][20] = 5.95e-11; + I_off_n[3][30] = 8.79e-11; + I_off_n[3][40] = 1.27e-10; + I_off_n[3][50] = 1.79e-10; + I_off_n[3][60] = 2.47e-10; + I_off_n[3][70] = 3.31e-10; + I_off_n[3][80] = 4.26e-10; + I_off_n[3][90] = 5.27e-10; + I_off_n[3][100] = 6.46e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.1; + Lphy[3] = 0.045; + Lelec[3] = 0.0298; + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.045; + curr_I_on_dram_cell = 20e-6; // A + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.045 * 0.045; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 2.7; + t_ox[3] = 4e-3; + v_th[3] = 1.0; + c_ox[3] = 7.98e-15; + mobility_eff[3] = 368.58 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.147; + c_g_ideal[3] = 3.59e-16; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 999.4e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.69; + n_to_p_eff_curr_drv_ratio[3] = 1.95; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.31e-14; + I_off_n[3][10] = 2.68e-14; + I_off_n[3][20] = 5.25e-14; + I_off_n[3][30] = 9.88e-14; + I_off_n[3][40] = 1.79e-13; + I_off_n[3][50] = 3.15e-13; + I_off_n[3][60] = 5.36e-13; + I_off_n[3][70] = 8.86e-13; + I_off_n[3][80] = 1.42e-12; + I_off_n[3][90] = 2.20e-12; + I_off_n[3][100] = 3.29e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7; + curr_core_tx_density = 1.25; + curr_sckt_co_eff = 1.1387; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 32) { + SENSE_AMP_D = .03e-9; // s + SENSE_AMP_P = 2.16e-15; // J + // For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is + // 32 nm technology i.e. FEATURESIZE = 0.032). Using the SOI process + // numbers for HP and LSTP. + vdd[0] = 0.9; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.19; + Lphy[0] = 0.013; + Lelec[0] = 0.01013; + t_ox[0] = 0.5e-3; + v_th[0] = 0.21835; + c_ox[0] = 4.11e-14; + mobility_eff[0] = 361.84 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[0] = 5.09E-2; + c_g_ideal[0] = 5.34e-16; + c_fringe[0] = 0.04e-15; + c_junc[0] = 1e-15; + I_on_n[0] = 2211.7e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); + // I_on_p[0] = I_on_n[0] / 2; + nmos_effective_resistance_multiplier = 1.49; + n_to_p_eff_curr_drv_ratio[0] = 2.41; + gmp_to_gmn_multiplier[0] = 1.38; + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd_real[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1 / 3.706; + // Using MASTAR, @300K (380K does not work in MASTAR), increase Lgate + // until Ion reduces to 95% or Lgate increase by 5% (DG device can only + // increase by 5%), whichever comes first + I_off_n[0][0] = 1.52e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][10] = 1.55e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][20] = 1.59e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][30] = 1.68e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][40] = 1.90e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][50] = 2.69e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][60] = 5.32e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][70] = 1.02e-6 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][80] = 1.62e-6 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][90] = 2.73e-6 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][100] = 6.1e-6 * pow(vdd_real[0] / (vdd[0]), 2); + + I_g_on_n[0][0] = 6.55e-8; // A/micron + I_g_on_n[0][10] = 6.55e-8; + I_g_on_n[0][20] = 6.55e-8; + I_g_on_n[0][30] = 6.55e-8; + I_g_on_n[0][40] = 6.55e-8; + I_g_on_n[0][50] = 6.55e-8; + I_g_on_n[0][60] = 6.55e-8; + I_g_on_n[0][70] = 6.55e-8; + I_g_on_n[0][80] = 6.55e-8; + I_g_on_n[0][90] = 6.55e-8; + I_g_on_n[0][100] = 6.55e-8; + + // 32 DG + // I_g_on_n[0][0] = 2.71e-9;//A/micron + // I_g_on_n[0][10] = 2.71e-9; + // I_g_on_n[0][20] = 2.71e-9; + // I_g_on_n[0][30] = 2.71e-9; + // I_g_on_n[0][40] = 2.71e-9; + // I_g_on_n[0][50] = 2.71e-9; + // I_g_on_n[0][60] = 2.71e-9; + // I_g_on_n[0][70] = 2.71e-9; + // I_g_on_n[0][80] = 2.71e-9; + // I_g_on_n[0][90] = 2.71e-9; + // I_g_on_n[0][100] = 2.71e-9; + + // LSTP device type + vdd[1] = 1; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; + alpha_power_law[1] = 1.27; + Lphy[1] = 0.020; + Lelec[1] = 0.0173; + t_ox[1] = 1.2e-3; + v_th[1] = 0.513; + c_ox[1] = 2.29e-14; + mobility_eff[1] = 347.46 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 8.64e-2; + c_g_ideal[1] = 4.58e-16; + c_fringe[1] = 0.053e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 683.6e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = I_on_n[1] / 2; + nmos_effective_resistance_multiplier = 1.99; + n_to_p_eff_curr_drv_ratio[1] = 2.23; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1 / 1.93; + I_off_n[1][0] = 2.06e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][10] = 3.30e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][20] = 5.15e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][30] = 7.83e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][40] = 1.16e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][50] = 1.69e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][60] = 2.40e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][70] = 3.34e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][80] = 4.54e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][90] = 5.96e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][100] = 7.44e-10 * pow(vdd_real[1] / (vdd[1]), 1); + + I_g_on_n[1][0] = 3.73e-11; // A/micron + I_g_on_n[1][10] = 3.73e-11; + I_g_on_n[1][20] = 3.73e-11; + I_g_on_n[1][30] = 3.73e-11; + I_g_on_n[1][40] = 3.73e-11; + I_g_on_n[1][50] = 3.73e-11; + I_g_on_n[1][60] = 3.73e-11; + I_g_on_n[1][70] = 3.73e-11; + I_g_on_n[1][80] = 3.73e-11; + I_g_on_n[1][90] = 3.73e-11; + I_g_on_n[1][100] = 3.73e-11; + + // LOP device type + vdd[2] = 0.6; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; // TODO + alpha_power_law[2] = 1.26; + Lphy[2] = 0.016; + Lelec[2] = 0.01232; + t_ox[2] = 0.9e-3; + v_th[2] = 0.24227; + c_ox[2] = 2.84e-14; + mobility_eff[2] = 513.52 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 4.64e-2; + c_g_ideal[2] = 4.54e-16; + c_fringe[2] = 0.057e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 827.8e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = I_on_n[2] / 2; + nmos_effective_resistance_multiplier = 1.73; + n_to_p_eff_curr_drv_ratio[2] = 2.28; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1 / 1.89; + I_off_n[2][0] = 5.94e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 7.23e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 8.7e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 1.04e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 1.22e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 1.43e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 1.65e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.90e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 2.15e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 2.39e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 2.63e-7 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 2.93e-9; // A/micron + I_g_on_n[2][10] = 2.93e-9; + I_g_on_n[2][20] = 2.93e-9; + I_g_on_n[2][30] = 2.93e-9; + I_g_on_n[2][40] = 2.93e-9; + I_g_on_n[2][50] = 2.93e-9; + I_g_on_n[2][60] = 2.93e-9; + I_g_on_n[2][70] = 2.93e-9; + I_g_on_n[2][80] = 2.93e-9; + I_g_on_n[2][90] = 2.93e-9; + I_g_on_n[2][100] = 2.93e-9; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.0; + Lphy[3] = 0.056; + Lelec[3] = 0.0419; // Assume Lelec is 30% lesser than Lphy for DRAM + // access and wordline transistors. + curr_v_th_dram_access_transistor = 0.44129; + width_dram_access_transistor = 0.056; + curr_I_on_dram_cell = 36e-6; + curr_I_off_dram_cell_worst_case_length_temp = 18.9e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.5; + t_ox[3] = 2e-3; + v_th[3] = 0.44467; + c_ox[3] = 1.48e-14; + mobility_eff[3] = 408.12 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.174; + c_g_ideal[3] = 7.45e-16; + c_fringe[3] = 0.053e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1055.4e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 3.57e-11; + I_off_n[3][10] = 5.51e-11; + I_off_n[3][20] = 8.27e-11; + I_off_n[3][30] = 1.21e-10; + I_off_n[3][40] = 1.74e-10; + I_off_n[3][50] = 2.45e-10; + I_off_n[3][60] = 3.38e-10; + I_off_n[3][70] = 4.53e-10; + I_off_n[3][80] = 5.87e-10; + I_off_n[3][90] = 7.29e-10; + I_off_n[3][100] = 8.87e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.0; + Lphy[3] = 0.032; + Lelec[3] = 0.0205; // Assume Lelec is 30% lesser than Lphy for DRAM + // access and wordline transistors. + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.032; + curr_I_on_dram_cell = 20e-6; + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.032 * 0.032; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 2.6; + t_ox[3] = 4e-3; + v_th[3] = 1.0; + c_ox[3] = 7.99e-15; + mobility_eff[3] = 380.76 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.129; + c_g_ideal[3] = 2.56e-16; + c_fringe[3] = 0.053e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1024.5e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.69; + n_to_p_eff_curr_drv_ratio[3] = 1.95; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 3.63e-14; + I_off_n[3][10] = 7.18e-14; + I_off_n[3][20] = 1.36e-13; + I_off_n[3][30] = 2.49e-13; + I_off_n[3][40] = 4.41e-13; + I_off_n[3][50] = 7.55e-13; + I_off_n[3][60] = 1.26e-12; + I_off_n[3][70] = 2.03e-12; + I_off_n[3][80] = 3.19e-12; + I_off_n[3][90] = 4.87e-12; + I_off_n[3][100] = 7.16e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7; + curr_core_tx_density = 1.25 / 0.7; + curr_sckt_co_eff = 1.1111; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 22) { + SENSE_AMP_D = .03e-9; // s + SENSE_AMP_P = 2.16e-15; // J + // For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is + // 22 nm technology i.e. FEATURESIZE = 0.022). Using the DG process + // numbers for HP. 22 nm HP + vdd[0] = 0.8; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; // TODO + alpha_power_law[0] = 1.2; // 1.3//1.15; + Lphy[0] = 0.009; // Lphy is the physical gate-length. + Lelec[0] = 0.00468; // Lelec is the electrical gate-length. + t_ox[0] = 0.55e-3; // micron + v_th[0] = 0.1395; // V + c_ox[0] = 3.63e-14; // F/micron2 + mobility_eff[0] = 426.07 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 2.33e-2; // V/micron + c_g_ideal[0] = 3.27e-16; // F/micron + c_fringe[0] = 0.06e-15; // F/micron + c_junc[0] = 0; // F/micron2 + I_on_n[0] = 2626.4e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); // A/micron + // I_on_p[0] = I_on_n[0] / + // 2; // A/micron //This value for I_on_p is not really + // used. + nmos_effective_resistance_multiplier = 1.45; + n_to_p_eff_curr_drv_ratio[0] = + 2; // Wpmos/Wnmos = 2 in 2007 MASTAR. Look in + //"Dynamic" tab of Device workspace. + gmp_to_gmn_multiplier[0] = 1.38; // Just using the 32nm SOI value. + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd_real[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1 / 3.274; + I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2 * + pow(vdd_real[0] / (vdd[0]), + 2); // From 22nm, leakage current are directly from + // ITRS report rather than MASTAR, since MASTAR + // has serious bugs there. + I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + // for 22nm DG HP + I_g_on_n[0][0] = 1.81e-9; // A/micron + I_g_on_n[0][10] = 1.81e-9; + I_g_on_n[0][20] = 1.81e-9; + I_g_on_n[0][30] = 1.81e-9; + I_g_on_n[0][40] = 1.81e-9; + I_g_on_n[0][50] = 1.81e-9; + I_g_on_n[0][60] = 1.81e-9; + I_g_on_n[0][70] = 1.81e-9; + I_g_on_n[0][80] = 1.81e-9; + I_g_on_n[0][90] = 1.81e-9; + I_g_on_n[0][100] = 1.81e-9; + + // 22 nm LSTP DG + vdd[1] = 0.8; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; // TODO + alpha_power_law[1] = 1.23; + Lphy[1] = 0.014; + Lelec[1] = 0.008; // Lelec is the electrical gate-length. + t_ox[1] = 1.1e-3; // micron + v_th[1] = 0.40126; // V + c_ox[1] = 2.30e-14; // F/micron2 + mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[1] = 6.64e-2; // V/micron + c_g_ideal[1] = 3.22e-16; // F/micron + c_fringe[1] = 0.08e-15; + c_junc[1] = 0; // F/micron2 + I_on_n[1] = 727.6e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); // A/micron + // I_on_p[1] = I_on_n[1] / 2; + nmos_effective_resistance_multiplier = 1.99; + n_to_p_eff_curr_drv_ratio[1] = 2; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd_real[1] / + I_on_n[1]; // ohm-micron + Rpchannelon[1] = + n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; // ohm-micron + long_channel_leakage_reduction[1] = 1 / 1.89; + I_off_n[1][0] = 2.43e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][10] = 4.85e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][20] = 9.68e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][30] = 1.94e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][40] = 3.87e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][50] = 7.73e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][60] = 3.55e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][70] = 3.09e-9 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][80] = 6.19e-9 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][90] = 1.24e-8 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][100] = 2.48e-8 * pow(vdd_real[1] / (vdd[1]), 1); + + I_g_on_n[1][0] = 4.51e-10; // A/micron + I_g_on_n[1][10] = 4.51e-10; + I_g_on_n[1][20] = 4.51e-10; + I_g_on_n[1][30] = 4.51e-10; + I_g_on_n[1][40] = 4.51e-10; + I_g_on_n[1][50] = 4.51e-10; + I_g_on_n[1][60] = 4.51e-10; + I_g_on_n[1][70] = 4.51e-10; + I_g_on_n[1][80] = 4.51e-10; + I_g_on_n[1][90] = 4.51e-10; + I_g_on_n[1][100] = 4.51e-10; + + // 22 nm LOP + vdd[2] = 0.6; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; // TODO + alpha_power_law[2] = 1.21; + Lphy[2] = 0.011; + Lelec[2] = 0.00604; // Lelec is the electrical gate-length. + t_ox[2] = 0.8e-3; // micron + v_th[2] = 0.2315; // V + c_ox[2] = 2.87e-14; // F/micron2 + mobility_eff[2] = 698.37 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[2] = 1.81e-2; // V/micron + c_g_ideal[2] = 3.16e-16; // F/micron + c_fringe[2] = 0.08e-15; + c_junc[2] = + 0; // F/micron2 This is Cj0 not Cjunc in MASTAR results->Dynamic Tab + I_on_n[2] = 916.1e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); // A/micron + // I_on_p[2] = I_on_n[2] / 2; + nmos_effective_resistance_multiplier = 1.73; + n_to_p_eff_curr_drv_ratio[2] = 2; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd_real[2] / + I_on_n[2]; // ohm-micron + Rpchannelon[2] = + n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; // ohm-micron + long_channel_leakage_reduction[2] = 1 / 2.38; + + I_off_n[2][0] = 1.31e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 2.60e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 5.14e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 1.02e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 2.02e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 3.99e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 7.91e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.09e-6 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 2.09e-6 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 4.04e-6 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 4.48e-6 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 2.74e-9; // A/micron + I_g_on_n[2][10] = 2.74e-9; + I_g_on_n[2][20] = 2.74e-9; + I_g_on_n[2][30] = 2.74e-9; + I_g_on_n[2][40] = 2.74e-9; + I_g_on_n[2][50] = 2.74e-9; + I_g_on_n[2][60] = 2.74e-9; + I_g_on_n[2][70] = 2.74e-9; + I_g_on_n[2][80] = 2.74e-9; + I_g_on_n[2][90] = 2.74e-9; + I_g_on_n[2][100] = 2.74e-9; + + if (ram_cell_tech_type == 3) { + } + else if (ram_cell_tech_type == 4) { + // 22 nm commodity DRAM cell access transistor technology parameters. + // parameters + curr_vdd_dram_cell = 0.9; // 0.45;//This value has reduced greatly in + // 2007 ITRS for all technology nodes. In + // 2005 ITRS, the value was about twice the value in 2007 ITRS + Lphy[3] = 0.022; // micron + Lelec[3] = 0.0181; // micron. + curr_v_th_dram_access_transistor = 1; // V + width_dram_access_transistor = 0.022; // micron + curr_I_on_dram_cell = + 20e-6; // This is a typical value that I have always + // kept constant. In reality this could perhaps be lower + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; // A + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.022 * 0.022; // micron2. + curr_asp_ratio_cell_dram = 0.667; + curr_c_dram_cell = 30e-15; // This is a typical value that I have + // alwaus + // kept constant. + + // 22 nm commodity DRAM wordline transistor parameters obtained using + // MASTAR. + curr_vpp = 2.3; // vpp. V + t_ox[3] = 3.5e-3; // micron + v_th[3] = 1.0; // V + c_ox[3] = 9.06e-15; // F/micron2 + mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[3] = 0.0972; // V/micron + c_g_ideal[3] = 1.99e-16; // F/micron + c_fringe[3] = 0.053e-15; // F/micron + c_junc[3] = 1e-15; // F/micron2 + I_on_n[3] = 910.5e-6; // A/micron + // I_on_p[3] = I_on_n[3] / 2; // This value for I_on_p is not + // really used. + nmos_effective_resistance_multiplier = + 1.69; // Using the value from 32nm. + // + n_to_p_eff_curr_drv_ratio[3] = 1.95; // Using the value from 32nm + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / + I_on_n[3]; // ohm-micron + Rpchannelon[3] = + n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; // ohm-micron + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.1e-13; // A/micron + I_off_n[3][10] = 2.11e-13; + I_off_n[3][20] = 3.88e-13; + I_off_n[3][30] = 6.9e-13; + I_off_n[3][40] = 1.19e-12; + I_off_n[3][50] = 1.98e-12; + I_off_n[3][60] = 3.22e-12; + I_off_n[3][70] = 5.09e-12; + I_off_n[3][80] = 7.85e-12; + I_off_n[3][90] = 1.18e-11; + I_off_n[3][100] = 1.72e-11; + } + else { + // some error handler + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7; + curr_core_tx_density = 1.25 / 0.7 / 0.7; + curr_sckt_co_eff = 1.1296; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 16) { + // For 2019, MPU/ASIC stagger-contacted M1 half-pitch is 16 nm (so this is + // 16 nm technology i.e. FEATURESIZE = 0.016). Using the DG process + // numbers for HP. 16 nm HP + vdd[0] = 0.7; + Lphy[0] = 0.006; // Lphy is the physical gate-length. + Lelec[0] = 0.00315; // Lelec is the electrical gate-length. + t_ox[0] = 0.5e-3; // micron + v_th[0] = 0.1489; // V + c_ox[0] = 3.83e-14; // F/micron2 Cox_elec in MASTAR + mobility_eff[0] = 476.15 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 1.42e-2; // V/micron calculated in spreadsheet + c_g_ideal[0] = 2.30e-16; // F/micron + c_fringe[0] = 0.06e-15; // F/micron MASTAR inputdynamic/3 + c_junc[0] = 0; // F/micron2 MASTAR result dynamic + I_on_n[0] = 2768.4e-6; // A/micron + // I_on_p[0] = I_on_n[0] / + // 2; // A/micron //This value for I_on_p is not really + // used. + nmos_effective_resistance_multiplier = + 1.48; // nmos_effective_resistance_multiplier is the ratio of Ieff + // to Idsat where Ieff is the effective NMOS current and Idsat + // is the saturation current. + n_to_p_eff_curr_drv_ratio[0] = + 2; // Wpmos/Wnmos = 2 in 2007 MASTAR. Look in + //"Dynamic" tab of Device workspace. + gmp_to_gmn_multiplier[0] = 1.38; // Just using the 32nm SOI value. + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1 / 2.655; + I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2 * 1.07; + I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2 * 1.07; + I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2 * 1.07; + I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2 * 1.07; + // for 16nm DG HP + I_g_on_n[0][0] = 1.07e-9; // A/micron + I_g_on_n[0][10] = 1.07e-9; + I_g_on_n[0][20] = 1.07e-9; + I_g_on_n[0][30] = 1.07e-9; + I_g_on_n[0][40] = 1.07e-9; + I_g_on_n[0][50] = 1.07e-9; + I_g_on_n[0][60] = 1.07e-9; + I_g_on_n[0][70] = 1.07e-9; + I_g_on_n[0][80] = 1.07e-9; + I_g_on_n[0][90] = 1.07e-9; + I_g_on_n[0][100] = 1.07e-9; + + // //16 nm LSTP DG + // vdd[1] = 0.8; + // Lphy[1] = 0.014; + // Lelec[1] = 0.008;//Lelec is the electrical gate-length. + // t_ox[1] = 1.1e-3;//micron + // v_th[1] = 0.40126;//V + // c_ox[1] = 2.30e-14;//F/micron2 + // mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 + // / Vs Vdsat[1] = 6.64e-2; //V/micron c_g_ideal[1] + // = 3.22e-16;//F/micron c_fringe[1] = 0.008e-15; + // c_junc[1] = 0;//F/micron2 + // I_on_n[1] = 727.6e-6;//A/micron + // // I_on_p[1] = I_on_n[1] / 2; + // nmos_effective_resistance_multiplier = 1.99; + // n_to_p_eff_curr_drv_ratio[1] = 2; + // gmp_to_gmn_multiplier[1] = 0.99; + // Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / + // I_on_n[1];//ohm-micron Rpchannelon[1] = + // n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];//ohm-micron + // I_off_n[1][0] = 2.43e-11; + // I_off_n[1][10] = 4.85e-11; + // I_off_n[1][20] = 9.68e-11; + // I_off_n[1][30] = 1.94e-10; + // I_off_n[1][40] = 3.87e-10; + // I_off_n[1][50] = 7.73e-10; + // I_off_n[1][60] = 3.55e-10; + // I_off_n[1][70] = 3.09e-9; + // I_off_n[1][80] = 6.19e-9; + // I_off_n[1][90] = 1.24e-8; + // I_off_n[1][100]= 2.48e-8; + // + // // for 22nm LSTP HP + // I_g_on_n[1][0] = 4.51e-10;//A/micron + // I_g_on_n[1][10] = 4.51e-10; + // I_g_on_n[1][20] = 4.51e-10; + // I_g_on_n[1][30] = 4.51e-10; + // I_g_on_n[1][40] = 4.51e-10; + // I_g_on_n[1][50] = 4.51e-10; + // I_g_on_n[1][60] = 4.51e-10; + // I_g_on_n[1][70] = 4.51e-10; + // I_g_on_n[1][80] = 4.51e-10; + // I_g_on_n[1][90] = 4.51e-10; + // I_g_on_n[1][100] = 4.51e-10; + + if (ram_cell_tech_type == 3) { + } + else if (ram_cell_tech_type == 4) { + // 22 nm commodity DRAM cell access transistor technology parameters. + // parameters + curr_vdd_dram_cell = 0.9; // 0.45;//This value has reduced greatly in + // 2007 ITRS for all technology nodes. In + // 2005 ITRS, the value was about twice the value in 2007 ITRS + Lphy[3] = 0.022; // micron + Lelec[3] = 0.0181; // micron. + curr_v_th_dram_access_transistor = 1; // V + width_dram_access_transistor = 0.022; // micron + curr_I_on_dram_cell = + 20e-6; // This is a typical value that I have always + // kept constant. In reality this could perhaps be lower + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; // A + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.022 * 0.022; // micron2. + curr_asp_ratio_cell_dram = 0.667; + curr_c_dram_cell = 30e-15; // This is a typical value that I have + // alwaus + // kept constant. + + // 22 nm commodity DRAM wordline transistor parameters obtained using + // MASTAR. + curr_vpp = 2.3; // vpp. V + t_ox[3] = 3.5e-3; // micron + v_th[3] = 1.0; // V + c_ox[3] = 9.06e-15; // F/micron2 + mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[3] = 0.0972; // V/micron + c_g_ideal[3] = 1.99e-16; // F/micron + c_fringe[3] = 0.053e-15; // F/micron + c_junc[3] = 1e-15; // F/micron2 + I_on_n[3] = 910.5e-6; // A/micron + // I_on_p[3] = I_on_n[3] / 2; // This value for I_on_p is not + // really used. + nmos_effective_resistance_multiplier = + 1.69; // Using the value from 32nm. + // + n_to_p_eff_curr_drv_ratio[3] = 1.95; // Using the value from 32nm + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / + I_on_n[3]; // ohm-micron + Rpchannelon[3] = + n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; // ohm-micron + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.1e-13; // A/micron + I_off_n[3][10] = 2.11e-13; + I_off_n[3][20] = 3.88e-13; + I_off_n[3][30] = 6.9e-13; + I_off_n[3][40] = 1.19e-12; + I_off_n[3][50] = 1.98e-12; + I_off_n[3][60] = 3.22e-12; + I_off_n[3][70] = 5.09e-12; + I_off_n[3][80] = 7.85e-12; + I_off_n[3][90] = 1.18e-11; + I_off_n[3][100] = 1.72e-11; + } + else { + // some error handler + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7 * 0.7; + curr_core_tx_density = 1.25 / 0.7 / 0.7 / 0.7; + curr_sckt_co_eff = 1.1296; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + /* + * TODO:WL_Vcc does not need to retain data as long as the wordline enable + * signal is not active (of course enable signal will not be active since it + * is idle) So, the WL_Vcc only need to balance the leakage reduction and + * the required waking up restore time (as mentioned in the 4.0Ghz 291 Mb + * SRAM Intel Paper) + */ + g_tp.peri_global.Vdd += + curr_alpha * + vdd_real[peri_global_tech_type]; // real vdd, user defined or itrs + g_tp.peri_global.Vdd_default += + curr_alpha * vdd[peri_global_tech_type]; // itrs vdd this does not have + // to do within line + // interpolation loop, can be + // assigned directly + g_tp.peri_global.Vth += curr_alpha * v_th[peri_global_tech_type]; + g_tp.peri_global.Vcc_min_default += + g_tp.peri_global.Vdd_default * + 0.45; // Use minimal voltage to keep the device + // conducted.//g_tp.peri_global.Vth; + g_tp.peri_global.t_ox += curr_alpha * t_ox[peri_global_tech_type]; + g_tp.peri_global.C_ox += curr_alpha * c_ox[peri_global_tech_type]; + g_tp.peri_global.C_g_ideal += curr_alpha * c_g_ideal[peri_global_tech_type]; + g_tp.peri_global.C_fringe += curr_alpha * c_fringe[peri_global_tech_type]; + g_tp.peri_global.C_junc += curr_alpha * c_junc[peri_global_tech_type]; + g_tp.peri_global.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.peri_global.l_phy += curr_alpha * Lphy[peri_global_tech_type]; + g_tp.peri_global.l_elec += curr_alpha * Lelec[peri_global_tech_type]; + g_tp.peri_global.I_on_n += curr_alpha * I_on_n[peri_global_tech_type]; + g_tp.peri_global.R_nch_on += + curr_alpha * Rnchannelon[peri_global_tech_type]; + g_tp.peri_global.R_pch_on += + curr_alpha * Rpchannelon[peri_global_tech_type]; + g_tp.peri_global.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[peri_global_tech_type]; + g_tp.peri_global.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[peri_global_tech_type]; + g_tp.peri_global.I_off_n += + curr_alpha * + I_off_n + [peri_global_tech_type] + [g_ip->temp - + 300]; //*pow(g_tp.peri_global.Vdd/g_tp.peri_global.Vdd_default,3);//Consider + // the voltage change may affect the current density as + // well. + // TODO: polynomial curve-fitting based on MASTAR may not be + // accurate enough + g_tp.peri_global.I_off_p += + curr_alpha * + I_off_n + [peri_global_tech_type] + [g_ip->temp - + 300]; //*pow(g_tp.peri_global.Vdd/g_tp.peri_global.Vdd_default,3);//To + // mimic the Vdd effect on Ioff (for the same device, dvs + // should not change default Ioff---only changes if device + // is different?? but MASTAR shows different results) + g_tp.peri_global.I_g_on_n += + curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; + g_tp.peri_global.I_g_on_p += + curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; + gmp_to_gmn_multiplier_periph_global += + curr_alpha * gmp_to_gmn_multiplier[peri_global_tech_type]; + g_tp.peri_global.Mobility_n += + curr_alpha * mobility_eff[peri_global_tech_type]; + + // Sleep tx uses LSTP devices + g_tp.sleep_tx.Vdd += curr_alpha * vdd_real[1]; + g_tp.sleep_tx.Vdd_default += curr_alpha * vdd[1]; + g_tp.sleep_tx.Vth += curr_alpha * v_th[1]; + g_tp.sleep_tx.Vcc_min_default += g_tp.sleep_tx.Vdd; + g_tp.sleep_tx.Vcc_min = + g_tp.sleep_tx.Vcc_min_default; // user cannot change this, has to be + // decided by technology + g_tp.sleep_tx.t_ox += curr_alpha * t_ox[1]; + g_tp.sleep_tx.C_ox += curr_alpha * c_ox[1]; + g_tp.sleep_tx.C_g_ideal += curr_alpha * c_g_ideal[1]; + g_tp.sleep_tx.C_fringe += curr_alpha * c_fringe[1]; + g_tp.sleep_tx.C_junc += curr_alpha * c_junc[1]; + g_tp.sleep_tx.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.sleep_tx.l_phy += curr_alpha * Lphy[1]; + g_tp.sleep_tx.l_elec += curr_alpha * Lelec[1]; + g_tp.sleep_tx.I_on_n += curr_alpha * I_on_n[1]; + g_tp.sleep_tx.R_nch_on += curr_alpha * Rnchannelon[1]; + g_tp.sleep_tx.R_pch_on += curr_alpha * Rpchannelon[1]; + g_tp.sleep_tx.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[1]; + g_tp.sleep_tx.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[1]; + g_tp.sleep_tx.I_off_n += + curr_alpha * + I_off_n[1] + [g_ip->temp - + 300]; //**pow(g_tp.sleep_tx.Vdd/g_tp.sleep_tx.Vdd_default,4); + g_tp.sleep_tx.I_off_p += + curr_alpha * + I_off_n[1] + [g_ip->temp - + 300]; //**pow(g_tp.sleep_tx.Vdd/g_tp.sleep_tx.Vdd_default,4); + g_tp.sleep_tx.I_g_on_n += curr_alpha * I_g_on_n[1][g_ip->temp - 300]; + g_tp.sleep_tx.I_g_on_p += curr_alpha * I_g_on_n[1][g_ip->temp - 300]; + g_tp.sleep_tx.Mobility_n += curr_alpha * mobility_eff[1]; + // gmp_to_gmn_multiplier_periph_global += curr_alpha * + // gmp_to_gmn_multiplier[1]; + + g_tp.sram_cell.Vdd += curr_alpha * vdd_real[ram_cell_tech_type]; + g_tp.sram_cell.Vdd_default += curr_alpha * vdd[ram_cell_tech_type]; + g_tp.sram_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; + g_tp.sram_cell.Vcc_min_default += g_tp.sram_cell.Vdd_default * 0.6; + g_tp.sram_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; + g_tp.sram_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; + g_tp.sram_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; + g_tp.sram_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; + g_tp.sram_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; + g_tp.sram_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; + g_tp.sram_cell.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.sram_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; + g_tp.sram_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; + g_tp.sram_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; + g_tp.sram_cell.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; + g_tp.sram_cell.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; + g_tp.sram_cell.I_off_n += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //**pow(g_tp.sram_cell.Vdd/g_tp.sram_cell.Vdd_default,4); + g_tp.sram_cell.I_off_p += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //**pow(g_tp.sram_cell.Vdd/g_tp.sram_cell.Vdd_default,4); + g_tp.sram_cell.I_g_on_n += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + g_tp.sram_cell.I_g_on_p += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + + g_tp.dram_cell_Vdd += curr_alpha * curr_vdd_dram_cell; + g_tp.dram_acc.Vth += curr_alpha * curr_v_th_dram_access_transistor; + g_tp.dram_acc.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; + g_tp.dram_acc.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; + g_tp.dram_acc.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; + g_tp.dram_acc.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; + g_tp.dram_acc.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; + g_tp.dram_acc.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.dram_cell_I_on += curr_alpha * curr_I_on_dram_cell; + g_tp.dram_cell_I_off_worst_case_len_temp += + curr_alpha * curr_I_off_dram_cell_worst_case_length_temp; + g_tp.dram_acc.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; + g_tp.dram_cell_C += curr_alpha * curr_c_dram_cell; + g_tp.vpp += curr_alpha * curr_vpp; + g_tp.dram_wl.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; + g_tp.dram_wl.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; + g_tp.dram_wl.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; + g_tp.dram_wl.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; + g_tp.dram_wl.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; + g_tp.dram_wl.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.dram_wl.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; + g_tp.dram_wl.R_nch_on += curr_alpha * Rnchannelon[dram_cell_tech_flavor]; + g_tp.dram_wl.R_pch_on += curr_alpha * Rpchannelon[dram_cell_tech_flavor]; + g_tp.dram_wl.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[dram_cell_tech_flavor]; + g_tp.dram_wl.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[dram_cell_tech_flavor]; + g_tp.dram_wl.I_off_n += + curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; + g_tp.dram_wl.I_off_p += + curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; + + g_tp.cam_cell.Vdd += curr_alpha * vdd_real[ram_cell_tech_type]; + g_tp.cam_cell.Vdd_default += curr_alpha * vdd[ram_cell_tech_type]; + g_tp.cam_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; + g_tp.cam_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; + g_tp.cam_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; + g_tp.cam_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; + g_tp.cam_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; + g_tp.cam_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; + g_tp.cam_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; + g_tp.cam_cell.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.cam_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; + g_tp.cam_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; + g_tp.cam_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; + g_tp.cam_cell.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; + g_tp.cam_cell.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; + g_tp.cam_cell.I_off_n += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //*pow(g_tp.cam_cell.Vdd/g_tp.cam_cell.Vdd_default,4); + g_tp.cam_cell.I_off_p += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //**pow(g_tp.cam_cell.Vdd/g_tp.cam_cell.Vdd_default,4); + g_tp.cam_cell.I_g_on_n += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + g_tp.cam_cell.I_g_on_p += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + + g_tp.dram.cell_a_w += curr_alpha * curr_Wmemcella_dram; + g_tp.dram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_dram; + g_tp.dram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_dram; + area_cell_dram += curr_alpha * curr_area_cell_dram; + asp_ratio_cell_dram += curr_alpha * curr_asp_ratio_cell_dram; + + g_tp.sram.cell_a_w += curr_alpha * curr_Wmemcella_sram; + g_tp.sram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_sram; + g_tp.sram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_sram; + area_cell_sram += curr_alpha * curr_area_cell_sram; + asp_ratio_cell_sram += curr_alpha * curr_asp_ratio_cell_sram; + + g_tp.cam.cell_a_w += curr_alpha * curr_Wmemcella_cam; // sheng + g_tp.cam.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_cam; + g_tp.cam.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_cam; + area_cell_cam += curr_alpha * curr_area_cell_cam; + asp_ratio_cell_cam += curr_alpha * curr_asp_ratio_cell_cam; + + // Sense amplifier latch Gm calculation + mobility_eff_periph_global += + curr_alpha * mobility_eff[peri_global_tech_type]; + Vdsat_periph_global += curr_alpha * Vdsat[peri_global_tech_type]; + + // Empirical undifferetiated core/FU coefficient + g_tp.scaling_factor.logic_scaling_co_eff += + curr_alpha * curr_logic_scaling_co_eff; + g_tp.scaling_factor.core_tx_density += curr_alpha * curr_core_tx_density; + g_tp.chip_layout_overhead += curr_alpha * curr_chip_layout_overhead; + g_tp.macro_layout_overhead += curr_alpha * curr_macro_layout_overhead; + g_tp.sckt_co_eff += curr_alpha * curr_sckt_co_eff; + } + + // Currently we are not modeling the resistance/capacitance of poly anywhere. + // following data are continuous function (or data have been processed) does + // not need linear interpolation + g_tp.w_comp_inv_p1 = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + g_tp.w_comp_inv_n1 = + 7.5 * g_ip->F_sz_um; // this was 6 micron for the 0.8 micron process + g_tp.w_comp_inv_p2 = + 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron process + g_tp.w_comp_inv_n2 = + 15 * g_ip->F_sz_um; // this was 12 micron for the 0.8 micron process + g_tp.w_comp_inv_p3 = + 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron process + g_tp.w_comp_inv_n3 = + 30 * g_ip->F_sz_um; // this was 24 micron for the 0.8 micron process + g_tp.w_eval_inv_p = + 100 * g_ip->F_sz_um; // this was 80 micron for the 0.8 micron process + g_tp.w_eval_inv_n = + 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron process + g_tp.w_comp_n = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + g_tp.w_comp_p = + 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron process + + g_tp.MIN_GAP_BET_P_AND_N_DIFFS = 5 * g_ip->F_sz_um; + g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS = 1.5 * g_ip->F_sz_um; + g_tp.HPOWERRAIL = 2 * g_ip->F_sz_um; + g_tp.cell_h_def = 50 * g_ip->F_sz_um; + g_tp.w_poly_contact = g_ip->F_sz_um; + g_tp.spacing_poly_to_contact = g_ip->F_sz_um; + g_tp.spacing_poly_to_poly = 1.5 * g_ip->F_sz_um; + g_tp.ram_wl_stitching_overhead_ = 7.5 * g_ip->F_sz_um; + + g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2; + g_tp.max_w_nmos_ = 100 * g_ip->F_sz_um; + g_tp.w_iso = 12.5 * g_ip->F_sz_um; // was 10 micron for the 0.8 micron + // process + g_tp.w_sense_n = 3.75 * g_ip->F_sz_um; // sense amplifier N-trans; was 3 + // micron for the 0.8 micron process + g_tp.w_sense_p = 7.5 * g_ip->F_sz_um; // sense amplifier P-trans; was 6 + // micron for the 0.8 micron process + g_tp.w_sense_en = 5 * g_ip->F_sz_um; // Sense enable transistor of the sense + // amplifier; was 4 micron for the 0.8 + // micron process + g_tp.w_nmos_b_mux = 6 * g_tp.min_w_nmos_; + g_tp.w_nmos_sa_mux = 6 * g_tp.min_w_nmos_; + + if (ram_cell_tech_type == comm_dram) { + g_tp.max_w_nmos_dec = 8 * g_ip->F_sz_um; + g_tp.h_dec = 8; // in the unit of memory cell height + } + else { + g_tp.max_w_nmos_dec = g_tp.max_w_nmos_; + g_tp.h_dec = 4; // in the unit of memory cell height + } + + g_tp.peri_global.C_overlap = 0.2 * g_tp.peri_global.C_g_ideal; + g_tp.sram_cell.C_overlap = 0.2 * g_tp.sram_cell.C_g_ideal; + g_tp.cam_cell.C_overlap = 0.2 * g_tp.cam_cell.C_g_ideal; + + g_tp.dram_acc.C_overlap = 0.2 * g_tp.dram_acc.C_g_ideal; + g_tp.dram_acc.R_nch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_n; + // // g_tp.dram_acc.R_pch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_p; + + g_tp.dram_wl.C_overlap = 0.2 * g_tp.dram_wl.C_g_ideal; + + double gmn_sense_amp_latch = + (mobility_eff_periph_global / 2) * g_tp.peri_global.C_ox * + (g_tp.w_sense_n / g_tp.peri_global.l_elec) * Vdsat_periph_global; + double gmp_sense_amp_latch = + gmp_to_gmn_multiplier_periph_global * gmn_sense_amp_latch; + g_tp.gm_sense_amp_latch = + gmn_sense_amp_latch + + gmp_sense_amp_latch * + pow((g_tp.peri_global.Vdd - g_tp.peri_global.Vth) / + (g_tp.peri_global.Vdd_default - g_tp.peri_global.Vth), + 1.3) / + (g_tp.peri_global.Vdd / g_tp.peri_global.Vdd_default); + + g_tp.dram.b_w = sqrt(area_cell_dram / (asp_ratio_cell_dram)); + g_tp.dram.b_h = asp_ratio_cell_dram * g_tp.dram.b_w; + g_tp.sram.b_w = sqrt(area_cell_sram / (asp_ratio_cell_sram)); + g_tp.sram.b_h = asp_ratio_cell_sram * g_tp.sram.b_w; + g_tp.cam.b_w = sqrt(area_cell_cam / (asp_ratio_cell_cam)); // Sheng + g_tp.cam.b_h = asp_ratio_cell_cam * g_tp.cam.b_w; + + g_tp.dram.Vbitpre = g_tp.dram_cell_Vdd; + g_tp.sram.Vbitpre = g_tp.sram_cell.Vdd; // vdd[ram_cell_tech_type]; + g_tp.cam.Vbitpre = g_tp.cam_cell.Vdd; // vdd[ram_cell_tech_type];//Sheng + pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + g_tp.w_pmos_bl_precharge = 6 * pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; + g_tp.w_pmos_bl_eq = pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; + + // DVS and power-gating voltage finalization + if ((g_tp.sram_cell.Vcc_min_default > g_tp.sram_cell.Vdd || + g_tp.peri_global.Vdd < g_tp.peri_global.Vdd_default * 0.75 || + g_tp.sram_cell.Vdd < g_tp.sram_cell.Vdd_default * 0.75) && + (!g_ip->is_main_mem)) { + cerr << "User defined Vdd is too low.\n\n" << endl; + exit(0); + } + + if (g_ip->specific_vcc_min) { + g_tp.sram_cell.Vcc_min = g_ip->user_defined_vcc_min; + g_tp.peri_global.Vcc_min = g_ip->user_defined_vcc_min; + g_tp.sram.Vbitfloating = + g_tp.sram.Vbitpre * 0.7 * + (g_tp.sram_cell.Vcc_min / g_tp.peri_global.Vcc_min_default); + // if (g_ip->user_defined_vcc_min < g_tp.peri_global.Vcc_min_default) + // { + // g_tp.peri_global.Vcc_min = g_ip->user_defined_vcc_min; + // } + // else { + // + // } + } + else { + g_tp.sram_cell.Vcc_min = g_tp.sram_cell.Vcc_min_default; + g_tp.peri_global.Vcc_min = g_tp.peri_global.Vcc_min_default; + g_tp.sram.Vbitfloating = g_tp.sram.Vbitpre * 0.7; + } + + if (g_tp.sram_cell.Vcc_min < + g_tp.sram_cell.Vcc_min_default) // if want to compute multiple + // power-gating vdd settings in one run, + // should have multiple results copies + // (each copy containing such flag) in + // update_pg () + { + g_ip->user_defined_vcc_underflow = true; + } + else { + g_ip->user_defined_vcc_underflow = false; + } + + if ((g_tp.sram_cell.Vcc_min > g_tp.sram_cell.Vdd || + g_tp.peri_global.Vcc_min > g_tp.peri_global.Vdd) && + (!g_ip->is_main_mem)) { + cerr << "User defined power-saving supply voltage cannot be lower than Vdd " + "(DVS0).\n\n" + << endl; + exit(0); + } + double wire_pitch[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], + wire_r_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + wire_c_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + horiz_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + vert_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + aspect_ratio[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], + miller_value[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], + ild_thickness[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES]; + + for (iter = 0; iter <= 1; ++iter) { + // linear interpolation + if (iter == 0) { + tech = tech_lo; + if (tech_lo == tech_hi) { + curr_alpha = 1; + } + else { + curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); + } + } + else { + tech = tech_hi; + if (tech_lo == tech_hi) { + break; + } + else { + curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); + } + } + + if (tech == 180) { + // Aggressive projections + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // micron + aspect_ratio[0][0] = 2.0; + wire_width = wire_pitch[0][0] / 2; // micron + wire_thickness = aspect_ratio[0][0] * wire_width; // micron + wire_spacing = wire_pitch[0][0] - wire_width; // micron + barrier_thickness = 0.017; // micron + dishing_thickness = 0; // micron + alpha_scatter = 1; + wire_r_per_micron[0][0] = wire_resistance( + CU_RESISTIVITY, wire_width, wire_thickness, barrier_thickness, + dishing_thickness, alpha_scatter); // ohm/micron + ild_thickness[0][0] = 0.75; // micron + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 2.709; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; // F/micron + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], + fringe_cap); // F/micron. + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 2.4; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.75; // micron + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 2.709; + vert_dielectric_constant[0][1] = 3.9; + fringe_cap = 0.115e-15; // F/micron + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 2.2; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 1.5; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 2.709; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.017; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.75; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 3.038; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.75; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 3.038; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 1.98; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 3.038; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.18; + wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.18); + wire_r_per_micron[1][3] = 12 / 0.18; + } + else if (tech == 90) { + // Aggressive projections + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // micron + aspect_ratio[0][0] = 2.4; + wire_width = wire_pitch[0][0] / 2; // micron + wire_thickness = aspect_ratio[0][0] * wire_width; // micron + wire_spacing = wire_pitch[0][0] - wire_width; // micron + barrier_thickness = 0.01; // micron + dishing_thickness = 0; // micron + alpha_scatter = 1; + wire_r_per_micron[0][0] = wire_resistance( + CU_RESISTIVITY, wire_width, wire_thickness, barrier_thickness, + dishing_thickness, alpha_scatter); // ohm/micron + ild_thickness[0][0] = 0.48; // micron + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 2.709; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; // F/micron + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], + fringe_cap); // F/micron. + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 2.4; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.48; // micron + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 2.709; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 2.7; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.96; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 2.709; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.008; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.48; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 3.038; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.48; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 3.038; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 1.1; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 3.038; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.09; + wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.09); + wire_r_per_micron[1][3] = 12 / 0.09; + } + else if (tech == 65) { + // Aggressive projections + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[0][0] = 2.7; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.405; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 2.303; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 2.7; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.405; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 2.303; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 2.8; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.81; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 2.303; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.006; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.405; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.734; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.405; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.734; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.77; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.734; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.065; + wire_c_per_micron[1][3] = 52.5e-15 / (256 * 2 * 0.065); + wire_r_per_micron[1][3] = 12 / 0.065; + } + else if (tech == 45) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.315; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.958; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 3.0; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.315; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.958; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.63; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.958; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.004; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.315; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.46; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.315; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.46; + vert_dielectric_constant[1][1] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.55; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.46; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.045; + wire_c_per_micron[1][3] = 37.5e-15 / (256 * 2 * 0.045); + wire_r_per_micron[1][3] = 12 / 0.045; + } + else if (tech == 32) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.21; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.664; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 3.0; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.21; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.664; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.42; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.664; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.003; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.21; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.214; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + aspect_ratio[1][1] = 2.0; + wire_width = wire_pitch[1][1] / 2; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.21; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.214; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.385; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.214; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.032; // micron + wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.032); // F/micron + wire_r_per_micron[1][3] = 12 / 0.032; // ohm/micron + } + else if (tech == 22) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // local + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.15; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.414; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; // semi-global + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 3.0; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.15; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.414; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; // global + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.3; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.414; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // //************************* + // wire_pitch[0][4] = 16 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][4] - wire_width; + // wire_r_per_micron[0][4] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][5] = 24 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][5] - wire_width; + // wire_r_per_micron[0][5] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][6] = 32 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][6] - wire_width; + // wire_r_per_micron[0][6] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + //************************* + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.003; + dishing_thickness = 0; + alpha_scatter = 1.05; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.15; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.104; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.15; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.104; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.275; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.104; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.022; // micron + wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.022); // F/micron + wire_r_per_micron[1][3] = 12 / 0.022; // ohm/micron + + //****************** + // wire_pitch[1][4] = 16 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][4] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][4] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][5] = 24 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][5] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][5] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][6] = 32 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][6] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][6] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + } + + else if (tech == 16) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // local + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.108; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.202; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; // semi-global + aspect_ratio[0][1] = 3.0; + wire_width = wire_pitch[0][1] / 2; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.108; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.202; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; // global + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.216; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.202; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // //************************* + // wire_pitch[0][4] = 16 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][4] - wire_width; + // wire_r_per_micron[0][4] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][5] = 24 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][5] - wire_width; + // wire_r_per_micron[0][5] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][6] = 32 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][6] - wire_width; + // wire_r_per_micron[0][6] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + //************************* + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.002; + dishing_thickness = 0; + alpha_scatter = 1.05; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.108; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 1.998; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.108; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 1.998; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.198; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 1.998; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.016; // micron + wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.016); // F/micron + wire_r_per_micron[1][3] = 12 / 0.016; // ohm/micron + + //****************** + // wire_pitch[1][4] = 16 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][4] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][4] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][5] = 24 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][5] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][5] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][6] = 32 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][6] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][6] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + } + g_tp.wire_local.pitch += + curr_alpha * wire_pitch[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.R_per_um += + curr_alpha * + wire_r_per_micron[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.C_per_um += + curr_alpha * + wire_c_per_micron[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.aspect_ratio += + curr_alpha * aspect_ratio[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.ild_thickness += + curr_alpha * ild_thickness[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.miller_value += + curr_alpha * miller_value[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.horiz_dielectric_constant += + curr_alpha * + horiz_dielectric_constant[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.vert_dielectric_constant += + curr_alpha * + vert_dielectric_constant[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + + g_tp.wire_inside_mat.pitch += + curr_alpha * wire_pitch[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.R_per_um += + curr_alpha * + wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.C_per_um += + curr_alpha * + wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.aspect_ratio += + curr_alpha * aspect_ratio[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.ild_thickness += + curr_alpha * ild_thickness[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.miller_value += + curr_alpha * miller_value[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.horiz_dielectric_constant += + curr_alpha * + horiz_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.vert_dielectric_constant += + curr_alpha * + vert_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + + g_tp.wire_outside_mat.pitch += + curr_alpha * wire_pitch[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.R_per_um += + curr_alpha * + wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.C_per_um += + curr_alpha * + wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.aspect_ratio += + curr_alpha * aspect_ratio[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.ild_thickness += + curr_alpha * ild_thickness[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.miller_value += + curr_alpha * miller_value[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.horiz_dielectric_constant += + curr_alpha * + horiz_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.vert_dielectric_constant += + curr_alpha * + vert_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + + g_tp.unit_len_wire_del = + g_tp.wire_inside_mat.R_per_um * g_tp.wire_inside_mat.C_per_um / 2; + + g_tp.sense_delay += curr_alpha * SENSE_AMP_D; + g_tp.sense_dy_power += curr_alpha * SENSE_AMP_P; + // g_tp.horiz_dielectric_constant += horiz_dielectric_constant; + // g_tp.vert_dielectric_constant += vert_dielectric_constant; + // g_tp.aspect_ratio += aspect_ratio; + // g_tp.miller_value += miller_value; + // g_tp.ild_thickness += ild_thickness; + } + g_tp.fringe_cap = fringe_cap; + + double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1); + double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(); + double c_load = gate_C(g_tp.min_w_nmos_ * (1 + p_to_n_sizing_r), 0.0); + double tf = rd * c_load; + g_tp.kinv = horowitz(0, tf, 0.5, 0.5, RISE); + double KLOAD = 1; + c_load = KLOAD * (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, + g_tp.cell_h_def) + + gate_C(g_tp.min_w_nmos_ * 4 * (1 + p_to_n_sizing_r), 0.0)); + tf = rd * c_load; + g_tp.FO4 = horowitz(0, tf, 0.5, 0.5, RISE); +} + +} // namespace cacti diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/uca.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/uca.cc new file mode 100644 index 0000000000..b7922b0202 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/uca.cc @@ -0,0 +1,478 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include + +#include "uca.h" +using namespace cacti; + +UCA::UCA(const DynamicParameter &dyn_p) + : dp(dyn_p), bank(dp), nbanks(g_ip->nbanks), refresh_power(0) { + int num_banks_ver_dir = + 1 << ((bank.area.h > bank.area.w) ? _log2(nbanks) / 2 + : (_log2(nbanks) - _log2(nbanks) / 2)); + int num_banks_hor_dir = nbanks / num_banks_ver_dir; + + if (dp.use_inp_params) { + RWP = dp.num_rw_ports; + ERP = dp.num_rd_ports; + EWP = dp.num_wr_ports; + SCHP = dp.num_search_ports; + } + else { + RWP = g_ip->num_rw_ports; + ERP = g_ip->num_rd_ports; + EWP = g_ip->num_wr_ports; + SCHP = g_ip->num_search_ports; + } + + num_addr_b_bank = + (dp.number_addr_bits_mat + dp.number_subbanks_decode) * (RWP + ERP + EWP); + num_di_b_bank = dp.num_di_b_bank_per_port * (RWP + EWP); + num_do_b_bank = dp.num_do_b_bank_per_port * (RWP + ERP); + num_si_b_bank = dp.num_si_b_bank_per_port * SCHP; + num_so_b_bank = dp.num_so_b_bank_per_port * SCHP; + + if (!dp.fully_assoc && !dp.pure_cam) { + if (g_ip->fast_access && dp.is_tag == false) { + num_do_b_bank *= g_ip->data_assoc; + } + + htree_in_add = + new Htree2(g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, + num_di_b_bank, 0, num_do_b_bank, 0, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Add_htree, true); + htree_in_data = + new Htree2(g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, + num_di_b_bank, 0, num_do_b_bank, 0, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_in_htree, true); + htree_out_data = + new Htree2(g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, + num_di_b_bank, 0, num_do_b_bank, 0, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_out_htree, true); + } + + else { + htree_in_add = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Add_htree, true); + htree_in_data = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_in_htree, true); + htree_out_data = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_out_htree, true); + htree_in_search = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_in_htree, true); + htree_out_search = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_out_htree, true); + } + + area.w = htree_in_data->area.w; + area.h = htree_in_data->area.h; + + area_all_dataramcells = + bank.mat.subarray.get_total_cell_area() * dp.num_subarrays * g_ip->nbanks; + // cout<<"area cell"<delay + bank.htree_in_add->delay; + double max_delay_before_row_decoder = + delay_array_to_mat + bank.mat.r_predec->delay; + delay_array_to_sa_mux_lev_1_decoder = delay_array_to_mat + + bank.mat.sa_mux_lev_1_predec->delay + + bank.mat.sa_mux_lev_1_dec->delay; + delay_array_to_sa_mux_lev_2_decoder = delay_array_to_mat + + bank.mat.sa_mux_lev_2_predec->delay + + bank.mat.sa_mux_lev_2_dec->delay; + double delay_inside_mat = + bank.mat.row_dec->delay + bank.mat.delay_bitline + bank.mat.delay_sa; + + delay_before_subarray_output_driver = + MAX(MAX(max_delay_before_row_decoder + delay_inside_mat, // row_path + delay_array_to_mat + bank.mat.b_mux_predec->delay + + bank.mat.bit_mux_dec->delay + bank.mat.delay_sa), // col_path + MAX(delay_array_to_sa_mux_lev_1_decoder, // sa_mux_lev_1_path + delay_array_to_sa_mux_lev_2_decoder)); // sa_mux_lev_2_path + delay_from_subarray_out_drv_to_out = bank.mat.delay_subarray_out_drv_htree + + bank.htree_out_data->delay + + htree_out_data->delay; + access_time = bank.mat.delay_comparator; + + double ram_delay_inside_mat; + if (dp.fully_assoc) { + // delay of FA contains both CAM tag and RAM data + { // delay of CAM + ram_delay_inside_mat = + bank.mat.delay_bitline + bank.mat.delay_matchchline; + access_time = htree_in_add->delay + bank.htree_in_add->delay; + // delay of fully-associative data array + access_time += ram_delay_inside_mat + delay_from_subarray_out_drv_to_out; + } + } + else { + access_time = delay_before_subarray_output_driver + + delay_from_subarray_out_drv_to_out; // data_acc_path + } + + if (dp.is_main_mem) { + double t_rcd = max_delay_before_row_decoder + delay_inside_mat; + double cas_latency = MAX(delay_array_to_sa_mux_lev_1_decoder, + delay_array_to_sa_mux_lev_2_decoder) + + delay_from_subarray_out_drv_to_out; + access_time = t_rcd + cas_latency; + } + + double temp; + + if (!dp.fully_assoc) { + temp = delay_inside_mat + bank.mat.delay_wl_reset + + bank.mat.delay_bl_restore; // TODO: Sheng: revisit + if (dp.is_dram) { + temp += bank.mat.delay_writeback; // temp stores random cycle time + } + + temp = MAX(temp, bank.mat.r_predec->delay); + temp = MAX(temp, bank.mat.b_mux_predec->delay); + temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay); + temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay); + } + else { + ram_delay_inside_mat = bank.mat.delay_bitline + bank.mat.delay_matchchline; + temp = ram_delay_inside_mat + bank.mat.delay_cam_sl_restore + + bank.mat.delay_cam_ml_reset + bank.mat.delay_bl_restore + + bank.mat.delay_hit_miss_reset + bank.mat.delay_wl_reset; + + temp = MAX(temp, bank.mat.b_mux_predec->delay); // TODO: Sheng revisit + // whether distinguish cam + // and ram bitline etc. + temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay); + temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay); + } + + // The following is true only if the input parameter "repeaters_in_htree" is + // set to false --Nav + if (g_ip->rpters_in_htree == false) { + temp = MAX(temp, bank.htree_in_add->max_unpipelined_link_delay); + } + cycle_time = temp; + + double delay_req_network = max_delay_before_row_decoder; + double delay_rep_network = delay_from_subarray_out_drv_to_out; + multisubbank_interleave_cycle_time = + MAX(delay_req_network, delay_rep_network); + + if (dp.is_main_mem) { + multisubbank_interleave_cycle_time = htree_in_add->delay; + precharge_delay = htree_in_add->delay + bank.htree_in_add->delay + + bank.mat.delay_writeback + bank.mat.delay_wl_reset + + bank.mat.delay_bl_restore; + cycle_time = access_time + precharge_delay; + } + else { + precharge_delay = 0; + } + + // double dram_array_availability = 0; + // if (dp.is_dram) { + // dram_array_availability = + // (1 - dp.num_r_subarray * cycle_time / dp.dram_refresh_period) * 100; + // } + + return outrisetime; +} + +// note: currently, power numbers are for a bank of an array +void UCA::compute_power_energy() { + bank.compute_power_energy(); + power = bank.power; + + power_routing_to_bank.readOp.dynamic = + htree_in_add->power.readOp.dynamic + htree_out_data->power.readOp.dynamic; + power_routing_to_bank.writeOp.dynamic = + htree_in_add->power.readOp.dynamic + htree_in_data->power.readOp.dynamic; + if (dp.fully_assoc || dp.pure_cam) { + power_routing_to_bank.searchOp.dynamic = + htree_in_search->power.searchOp.dynamic + + htree_out_search->power.searchOp.dynamic; + } + power_routing_to_bank.readOp.leakage += htree_in_add->power.readOp.leakage + + htree_in_data->power.readOp.leakage + + htree_out_data->power.readOp.leakage; + + power_routing_to_bank.readOp.power_gated_leakage += + htree_in_add->power.readOp.power_gated_leakage + + htree_in_data->power.readOp.power_gated_leakage + + htree_out_data->power.readOp.power_gated_leakage; + + power_routing_to_bank.readOp.gate_leakage += + htree_in_add->power.readOp.gate_leakage + + htree_in_data->power.readOp.gate_leakage + + htree_out_data->power.readOp.gate_leakage; + if (dp.fully_assoc || dp.pure_cam) { + power_routing_to_bank.readOp.leakage += + htree_in_search->power.readOp.leakage + + htree_out_search->power.readOp.leakage; + power_routing_to_bank.readOp.gate_leakage += + htree_in_search->power.readOp.gate_leakage + + htree_out_search->power.readOp.gate_leakage; + } + + power.searchOp.dynamic += power_routing_to_bank.searchOp.dynamic; + power.readOp.dynamic += power_routing_to_bank.readOp.dynamic; + power.readOp.leakage += power_routing_to_bank.readOp.leakage; + power.readOp.power_gated_leakage += + power_routing_to_bank.readOp.power_gated_leakage; + power.readOp.gate_leakage += power_routing_to_bank.readOp.gate_leakage; + + // calculate total write energy per access + power.writeOp.dynamic = + power.readOp.dynamic - + bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir + + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir - + power_routing_to_bank.readOp.dynamic + + power_routing_to_bank.writeOp.dynamic + + bank.htree_in_data->power.readOp.dynamic - + bank.htree_out_data->power.readOp.dynamic; + + if (dp.is_dram == false) { + power.writeOp.dynamic -= + bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; + } + + dyn_read_energy_from_closed_page = power.readOp.dynamic; + dyn_read_energy_from_open_page = + power.readOp.dynamic - + (bank.mat.r_predec->power.readOp.dynamic + + bank.mat.power_row_decoders.readOp.dynamic + + bank.mat.power_bl_precharge_eq_drv.readOp.dynamic + + bank.mat.power_sa.readOp.dynamic + + bank.mat.power_bitline.readOp.dynamic) * + dp.num_act_mats_hor_dir; + + dyn_read_energy_remaining_words_in_burst = + (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1) * + ((bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + + bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + + bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + + bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic + + bank.mat.power_subarray_out_drv.readOp.dynamic) * + dp.num_act_mats_hor_dir + + bank.htree_out_data->power.readOp.dynamic + + power_routing_to_bank.readOp.dynamic); + dyn_read_energy_from_closed_page += dyn_read_energy_remaining_words_in_burst; + dyn_read_energy_from_open_page += dyn_read_energy_remaining_words_in_burst; + + activate_energy = htree_in_add->power.readOp.dynamic + + bank.htree_in_add->power_bit.readOp.dynamic * + bank.num_addr_b_routed_to_mat_for_act + + (bank.mat.r_predec->power.readOp.dynamic + + bank.mat.power_row_decoders.readOp.dynamic + + bank.mat.power_sa.readOp.dynamic) * + dp.num_act_mats_hor_dir; + read_energy = (htree_in_add->power.readOp.dynamic + + bank.htree_in_add->power_bit.readOp.dynamic * + bank.num_addr_b_routed_to_mat_for_rd_or_wr + + (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + + bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + + bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + + bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic + + bank.mat.power_subarray_out_drv.readOp.dynamic) * + dp.num_act_mats_hor_dir + + bank.htree_out_data->power.readOp.dynamic + + htree_in_data->power.readOp.dynamic) * + g_ip->burst_len; + write_energy = (htree_in_add->power.readOp.dynamic + + bank.htree_in_add->power_bit.readOp.dynamic * + bank.num_addr_b_routed_to_mat_for_rd_or_wr + + htree_in_data->power.readOp.dynamic + + bank.htree_in_data->power.readOp.dynamic + + (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + + bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + + bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + + bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic) * + dp.num_act_mats_hor_dir) * + g_ip->burst_len; + precharge_energy = (bank.mat.power_bitline.readOp.dynamic + + bank.mat.power_bl_precharge_eq_drv.readOp.dynamic) * + dp.num_act_mats_hor_dir; + + // The follow 6 parameters are only used in DRAM/eDRAM output for now + leak_power_subbank_closed_page = + (bank.mat.r_predec->power.readOp.leakage + + bank.mat.b_mux_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.leakage + + bank.mat.power_row_decoders.readOp.leakage + + bank.mat.power_bit_mux_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage + + bank.mat.leak_power_sense_amps_closed_page_state) * + dp.num_act_mats_hor_dir; + + leak_power_subbank_closed_page += + (bank.mat.r_predec->power.readOp.gate_leakage + + bank.mat.b_mux_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage + + bank.mat.power_row_decoders.readOp.gate_leakage + + bank.mat.power_bit_mux_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * + dp.num_act_mats_hor_dir; //+ + // bank.mat.leak_power_sense_amps_closed_page_state) * + // dp.num_act_mats_hor_dir; + + leak_power_subbank_open_page = + (bank.mat.r_predec->power.readOp.leakage + + bank.mat.b_mux_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.leakage + + bank.mat.power_row_decoders.readOp.leakage + + bank.mat.power_bit_mux_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage + + bank.mat.leak_power_sense_amps_open_page_state) * + dp.num_act_mats_hor_dir; + + leak_power_subbank_open_page += + (bank.mat.r_predec->power.readOp.gate_leakage + + bank.mat.b_mux_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage + + bank.mat.power_row_decoders.readOp.gate_leakage + + bank.mat.power_bit_mux_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * + dp.num_act_mats_hor_dir; + // bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir; + + leak_power_request_and_reply_networks = + power_routing_to_bank.readOp.leakage + + bank.htree_in_add->power.readOp.leakage + + bank.htree_in_data->power.readOp.leakage + + bank.htree_out_data->power.readOp.leakage; + + leak_power_request_and_reply_networks += + power_routing_to_bank.readOp.gate_leakage + + bank.htree_in_add->power.readOp.gate_leakage + + bank.htree_in_data->power.readOp.gate_leakage + + bank.htree_out_data->power.readOp.gate_leakage; + + if (dp.fully_assoc || dp.pure_cam) { + leak_power_request_and_reply_networks += + htree_in_search->power.readOp.leakage + + htree_out_search->power.readOp.leakage; + leak_power_request_and_reply_networks += + htree_in_search->power.readOp.gate_leakage + + htree_out_search->power.readOp.gate_leakage; + } + + if (dp.is_dram) { // if DRAM, add contribution of power spent in row + // predecoder drivers, blocks and decoders to refresh power + refresh_power = + (bank.mat.r_predec->power.readOp.dynamic * dp.num_act_mats_hor_dir + + bank.mat.row_dec->power.readOp.dynamic) * + dp.num_r_subarray * dp.num_subarrays; + refresh_power += bank.mat.per_bitline_read_energy * dp.num_c_subarray * + dp.num_r_subarray * dp.num_subarrays; + refresh_power += bank.mat.power_bl_precharge_eq_drv.readOp.dynamic * + dp.num_act_mats_hor_dir; + refresh_power += bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; + refresh_power /= dp.dram_refresh_period; + } + // The follow 6 parameters are only used in DRAM/eDRAM output for now + + if (dp.is_tag == false) { + power.readOp.dynamic = dyn_read_energy_from_closed_page; + power.writeOp.dynamic = + dyn_read_energy_from_closed_page - + dyn_read_energy_remaining_words_in_burst - + bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir + + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir + + (power_routing_to_bank.writeOp.dynamic - + power_routing_to_bank.readOp.dynamic - + bank.htree_out_data->power.readOp.dynamic + + bank.htree_in_data->power.readOp.dynamic) * + (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1); // FIXME + + if (dp.is_dram == false) { + power.writeOp.dynamic -= + bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; + } + } + + // if DRAM, add refresh power to total leakage + if (dp.is_dram) { + power.readOp.leakage += refresh_power; + } + + // TODO: below should be avoided. + /*if (dp.is_main_mem) + { + power.readOp.leakage += MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA * 1e-3 * + g_tp.peri_global.Vdd / g_ip->nbanks; + }*/ + + assert(power.readOp.dynamic > 0); + assert(power.writeOp.dynamic > 0); + assert(power.readOp.leakage > 0); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/uca.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/uca.h new file mode 100644 index 0000000000..4201479923 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/uca.h @@ -0,0 +1,97 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __UCA_H__ +#define __UCA_H__ + +#include "area.h" +#include "bank.h" +#include "component.h" +#include "htree2.h" +#include "parameter.h" + +namespace cacti { + +class UCA : public Component { + public: + UCA(const DynamicParameter &dyn_p); + ~UCA(); + double compute_delays(double inrisetime); // returns outrisetime + void compute_power_energy(); + + DynamicParameter dp; + Bank bank; + + Htree2 *htree_in_add; + Htree2 *htree_in_data; + Htree2 *htree_out_data; + Htree2 *htree_in_search; + Htree2 *htree_out_search; + + powerDef power_routing_to_bank; + + uint32_t nbanks; + + int num_addr_b_bank; + int num_di_b_bank; + int num_do_b_bank; + int num_si_b_bank; + int num_so_b_bank; + int RWP, ERP, EWP, SCHP; + double area_all_dataramcells; + + double dyn_read_energy_from_closed_page; + double dyn_read_energy_from_open_page; + double dyn_read_energy_remaining_words_in_burst; + + double refresh_power; // only for DRAM + double activate_energy; + double read_energy; + double write_energy; + double precharge_energy; + double leak_power_subbank_closed_page; + double leak_power_subbank_open_page; + double leak_power_request_and_reply_networks; + + double delay_array_to_sa_mux_lev_1_decoder; + double delay_array_to_sa_mux_lev_2_decoder; + double delay_before_subarray_output_driver; + double delay_from_subarray_out_drv_to_out; + double access_time; + double precharge_delay; + double multisubbank_interleave_cycle_time; + double long_channel_leakage_reduction_periperal; + double long_channel_leakage_reduction_memcell; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/version_cacti.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/version_cacti.h new file mode 100644 index 0000000000..6af534e3c5 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/version_cacti.h @@ -0,0 +1,44 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef VERSION_H_ +#define VERSION_H_ + +#include + +#define VER_MAJOR_CACTI 6 /* CACTI-P and DVS */ +#define VER_MINOR_CACTI 5 +const std::string VER_postfix_CACTI = "-P"; +#define VER_COMMENT_CACTI \ + "CAM and fully associative cache, power gating, and DVS" +#define VER_UPDATE_CACTI "June, 2014" + +#endif /* VERSION_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/wire.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/wire.cc new file mode 100644 index 0000000000..9b58c9aa32 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/wire.cc @@ -0,0 +1,919 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "wire.h" +#include "cmath" +using namespace cacti; +// use this constructor to calculate wire stats +Wire::Wire(enum Wire_type wire_model, double wl, int n, double w_s, double s_s, + enum Wire_placement wp, double resistivity, + TechnologyParameter::DeviceType *dt) + : wt(wire_model), + wire_length(wl * 1e-6), + nsense(n), + w_scale(w_s), + s_scale(s_s), + resistivity(resistivity), + deviceType(dt) { + wire_placement = wp; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + in_rise_time = 0; + out_rise_time = 0; + if (initialized != 1) { + cout << "Wire not initialized. Initializing it with default values\n"; + Wire winit; + } + calculate_wire_stats(); + // change everything back to seconds, microns, and Joules + repeater_spacing *= 1e6; + wire_length *= 1e6; + wire_width *= 1e6; + wire_spacing *= 1e6; + assert(wire_length > 0); + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); +} + +// the following values are for peripheral global technology +// specified in the input config file +Component Wire::global; +Component Wire::global_5; +Component Wire::global_10; +Component Wire::global_20; +Component Wire::global_30; +Component Wire::low_swing; + +int Wire::initialized; +double Wire::wire_width_init; +double Wire::wire_spacing_init; +double Wire::repeater_size_init; // value used in initialization should not be + // reused in final output +double Wire::repeater_spacing_init; + +Wire::Wire(double w_s, double s_s, + /*bool reset_repeater_sizing,*/ enum Wire_placement wp, double resis, + TechnologyParameter::DeviceType *dt) { + w_scale = w_s; + s_scale = s_s; + deviceType = dt; + wire_placement = wp; + resistivity = resis; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + in_rise_time = 0; + out_rise_time = 0; + + switch (wire_placement) { + case outside_mat: + wire_width = g_tp.wire_outside_mat.pitch; + break; + case inside_mat: + wire_width = g_tp.wire_inside_mat.pitch; + break; + default: + wire_width = g_tp.wire_local.pitch; + break; + } + + wire_spacing = wire_width; + + wire_width *= (w_scale * 1e-6 / 2) /* (m) */; + wire_spacing *= (s_scale * 1e-6 / 2) /* (m) */; + + initialized = 1; + init_wire(); + // init_wire(reset_repeater_sizing); + wire_width_init = wire_width; + wire_spacing_init = wire_spacing; + + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); +} + +Wire::~Wire() {} + +void Wire::calculate_wire_stats() { + if (wire_placement == outside_mat) { + wire_width = g_tp.wire_outside_mat.pitch; + } + else if (wire_placement == inside_mat) { + wire_width = g_tp.wire_inside_mat.pitch; + } + else { + wire_width = g_tp.wire_local.pitch; + } + + wire_spacing = wire_width; + + wire_width *= (w_scale * 1e-6 / 2) /* (m) */; + wire_spacing *= (s_scale * 1e-6 / 2) /* (m) */; + + if (wt != Low_swing) { + // delay_optimal_wire(); + + if (wt == Global) { + delay = global.delay * wire_length; + power.readOp.dynamic = global.power.readOp.dynamic * wire_length; + power.readOp.leakage = global.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global.power.readOp.gate_leakage * wire_length; + repeater_spacing = global.area.w; + repeater_size = global.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_5) { + delay = global_5.delay * wire_length; + power.readOp.dynamic = global_5.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_5.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_5.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_5.area.w; + repeater_size = global_5.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_10) { + delay = global_10.delay * wire_length; + power.readOp.dynamic = global_10.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_10.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_10.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_10.area.w; + repeater_size = global_10.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_20) { + delay = global_20.delay * wire_length; + power.readOp.dynamic = global_20.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_20.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_20.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_20.area.w; + repeater_size = global_20.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_30) { + delay = global_30.delay * wire_length; + power.readOp.dynamic = global_30.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_30.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_30.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_30.area.w; + repeater_size = global_30.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + out_rise_time = delay * repeater_spacing / deviceType->Vth; + } + else if (wt == Low_swing) { + low_swing_model(); + repeater_spacing = wire_length; + repeater_size = 1; + } + else { + assert(0); + } + + // if (g_ip->interconect_power_gated)//TODO:actual sleep txs need to be added + // as in the wordline drivers, + // //but since wires have enough space underneath for placement and + // routing of the sleep tx, the area overhead should be very small. + // //performance loss and energy overhead is also very small + // because of the property of sleep tx. + // { + // power.readOp.leakage = + // power.readOp.leakage/deviceType->Vdd*deviceType->Vcc_min; + // } + power.readOp.power_gated_leakage = + power.readOp.leakage / deviceType->Vdd * deviceType->Vcc_min; // TODO: +} + +/* + * The fall time of an input signal to the first stage of a circuit is + * assumed to be same as the fall time of the output signal of two + * inverters connected in series (refer: CACTI 1 Technical report, + * section 6.1.3) + */ +double Wire::signal_fall_time() { + /* rise time of inverter 1's output */ + double rt; + /* fall time of inverter 2's output */ + double ft; + double timeconst; + + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(min_w_pmos, PCH, 1); + rt = horowitz(0, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, FALL) / + (deviceType->Vdd - deviceType->Vth); + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(g_tp.min_w_nmos_, NCH, 1); + ft = horowitz(rt, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE) / + deviceType->Vth; + return ft; +} + +double Wire::signal_rise_time() { + /* rise time of inverter 1's output */ + double ft; + /* fall time of inverter 2's output */ + double rt; + double timeconst; + + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(g_tp.min_w_nmos_, NCH, 1); + rt = horowitz(0, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE) / + deviceType->Vth; + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(min_w_pmos, PCH, 1); + ft = horowitz(rt, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, FALL) / + (deviceType->Vdd - deviceType->Vth); + return ft; // sec +} + +/* Wire resistance and capacitance calculations + * wire width + * + * /__/ + * | | + * | | height = ASPECT_RATIO*wire width (ASPECT_RATIO = 2.2, ref: ITRS) + * |__|/ + * + * spacing between wires in same level = wire width + * spacing between wires in adjacent levels = wire width---this is incorrect, + * according to R.Ho's paper and thesis. ILD != wire width + * + */ + +double Wire::wire_cap(double len /* in m */, bool call_from_outside) { + // TODO: this should be consistent with the wire_res in technology file + double sidewall, adj, tot_cap; + double wire_height; + double epsilon0 = 8.8542e-12; + double aspect_ratio, horiz_dielectric_constant, vert_dielectric_constant, + miller_value, ild_thickness; + + switch (wire_placement) { + case outside_mat: { + aspect_ratio = g_tp.wire_outside_mat.aspect_ratio; + horiz_dielectric_constant = + g_tp.wire_outside_mat.horiz_dielectric_constant; + vert_dielectric_constant = g_tp.wire_outside_mat.vert_dielectric_constant; + miller_value = g_tp.wire_outside_mat.miller_value; + ild_thickness = g_tp.wire_outside_mat.ild_thickness; + break; + } + case inside_mat: { + aspect_ratio = g_tp.wire_inside_mat.aspect_ratio; + horiz_dielectric_constant = + g_tp.wire_inside_mat.horiz_dielectric_constant; + vert_dielectric_constant = g_tp.wire_inside_mat.vert_dielectric_constant; + miller_value = g_tp.wire_inside_mat.miller_value; + ild_thickness = g_tp.wire_inside_mat.ild_thickness; + break; + } + default: { + aspect_ratio = g_tp.wire_local.aspect_ratio; + horiz_dielectric_constant = g_tp.wire_local.horiz_dielectric_constant; + vert_dielectric_constant = g_tp.wire_local.vert_dielectric_constant; + miller_value = g_tp.wire_local.miller_value; + ild_thickness = g_tp.wire_local.ild_thickness; + break; + } + } + + if (call_from_outside) { + wire_width *= 1e-6; + wire_spacing *= 1e-6; + } + wire_height = wire_width / w_scale * aspect_ratio; + /* + * assuming height does not change. wire_width = width_original*w_scale + * So wire_height does not change as wire width increases + */ + + // capacitance between wires in the same level + // sidewall = 2*miller_value * horiz_dielectric_constant * + // (wire_height/wire_spacing) + // * epsilon0; + + sidewall = miller_value * horiz_dielectric_constant * + (wire_height / wire_spacing) * epsilon0; + + // capacitance between wires in adjacent levels + // adj = miller_value * vert_dielectric_constant *w_scale * epsilon0; + // adj = 2*vert_dielectric_constant *wire_width/(ild_thickness*1e-6) * + // epsilon0; + + adj = miller_value * vert_dielectric_constant * wire_width / + (ild_thickness * 1e-6) * epsilon0; + // Change ild_thickness from micron to M + + // tot_cap = (sidewall + adj + (deviceType->C_fringe * 1e6)); //F/m + tot_cap = (sidewall + adj + (g_tp.fringe_cap * 1e6)); // F/m + + if (call_from_outside) { + wire_width *= 1e6; + wire_spacing *= 1e6; + } + return (tot_cap * len); // (F) +} + +double Wire::wire_res(double len /*(in m)*/) { + double aspect_ratio, alpha_scatter = 1.05, dishing_thickness = 0, + barrier_thickness = 0; + // TODO: this should be consistent with the wire_res in technology file + // The whole computation should be consistent with the wire_res in + // technology.cc too! + + switch (wire_placement) { + case outside_mat: { + aspect_ratio = g_tp.wire_outside_mat.aspect_ratio; + break; + } + case inside_mat: { + aspect_ratio = g_tp.wire_inside_mat.aspect_ratio; + break; + } + default: { + aspect_ratio = g_tp.wire_local.aspect_ratio; + break; + } + } + return (alpha_scatter * resistivity * 1e-6 * len / + ((aspect_ratio * wire_width / w_scale - dishing_thickness - + barrier_thickness) * + (wire_width - 2 * barrier_thickness))); +} + +/* + * Calculates the delay, power and area of the transmitter circuit. + * + * The transmitter delay is the sum of nand gate delay, inverter delay + * low swing nmos delay, and the wire delay + * (ref: Technical report 6) + */ +void Wire::low_swing_model() { + double len = wire_length; + double beta = pmos_to_nmos_sz_ratio(); + + double inputrise = (in_rise_time == 0) ? signal_rise_time() : in_rise_time; + + /* Final nmos low swing driver size calculation: + * Try to size the driver such that the delay + * is less than 8FO4. + * If the driver size is greater than + * the max allowable size, assume max size for the driver. + * In either case, recalculate the delay using + * the final driver size assuming slow input with + * finite rise time instead of ideal step input + * + * (ref: Technical report 6) + */ + double cwire = wire_cap(len); /* load capacitance */ + double rwire = wire_res(len); + +#define RES_ADJ (8.6) // Increase in resistance due to low driving vol. + + double driver_res = (-8 * g_tp.FO4 / (log(0.5) * cwire)) / RES_ADJ; + double nsize = R_to_w(driver_res, NCH); + + nsize = MIN(nsize, g_tp.max_w_nmos_); + nsize = MAX(nsize, g_tp.min_w_nmos_); + + if (rwire * cwire > 8 * g_tp.FO4) { + nsize = g_tp.max_w_nmos_; + } + + // size the inverter appropriately to minimize the transmitter delay + // Note - In order to minimize leakage, we are not adding a set of inverters + // to bring down delay. Instead, we are sizing the single gate based on the + // logical effort. + double st_eff = + sqrt((2 + beta / 1 + beta) * gate_C(nsize, 0) / + (gate_C(2 * g_tp.min_w_nmos_, 0) + gate_C(2 * min_w_pmos, 0))); + double req_cin = ((2 + beta / 1 + beta) * gate_C(nsize, 0)) / st_eff; + double inv_size = + req_cin / (gate_C(min_w_pmos, 0) + gate_C(g_tp.min_w_nmos_, 0)); + inv_size = MAX(inv_size, 1); + + /* nand gate delay */ + double res_eq = (2 * tr_R_on(g_tp.min_w_nmos_, NCH, 1)); + double cap_eq = 2 * drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(2 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(inv_size * g_tp.min_w_nmos_, 0) + + gate_C(inv_size * min_w_pmos, 0); + + double timeconst = res_eq * cap_eq; + + delay = horowitz(inputrise, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + double temp_power = cap_eq * deviceType->Vdd * deviceType->Vdd; + + inputrise = + delay / (deviceType->Vdd - deviceType->Vth); /* for the next stage */ + + /* Inverter delay: + * The load capacitance of this inv depends on + * the gate capacitance of the final stage nmos + * transistor which in turn depends on nsize + */ + res_eq = tr_R_on(inv_size * min_w_pmos, PCH, 1); + cap_eq = drain_C_(inv_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(inv_size * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(nsize, 0); + timeconst = res_eq * cap_eq; + + delay += horowitz(inputrise, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, FALL); + temp_power += cap_eq * deviceType->Vdd * deviceType->Vdd; + + transmitter.delay = delay; + transmitter.power.readOp.dynamic = + temp_power * 2; /* since it is a diff. model*/ + transmitter.power.readOp.leakage = + deviceType->Vdd * + (4 * cmos_Isub_leakage(g_tp.min_w_nmos_, min_w_pmos, 2, nand) + + 4 * cmos_Isub_leakage(g_tp.min_w_nmos_, min_w_pmos, 1, inv)); + + transmitter.power.readOp.gate_leakage = + deviceType->Vdd * + (4 * cmos_Ig_leakage(g_tp.min_w_nmos_, min_w_pmos, 2, nand) + + 4 * cmos_Ig_leakage(g_tp.min_w_nmos_, min_w_pmos, 1, inv)); + + inputrise = delay / deviceType->Vth; + + /* nmos delay + wire delay */ + cap_eq = cwire + drain_C_(nsize, NCH, 1, 1, g_tp.cell_h_def) * 2 + + nsense * sense_amp_input_cap(); //+receiver cap + /* + * NOTE: nmos is used as both pull up and pull down transistor + * in the transmitter. This is because for low voltage swing, drive + * resistance of nmos is less than pmos + * (for a detailed graph ref: On-Chip Wires: Scaling and Efficiency) + */ + timeconst = (tr_R_on(nsize, NCH, 1) * RES_ADJ) * + (cwire + drain_C_(nsize, NCH, 1, 1, g_tp.cell_h_def) * 2) + + rwire * cwire / 2 + + (tr_R_on(nsize, NCH, 1) * RES_ADJ + rwire) * nsense * + sense_amp_input_cap(); + + /* + * since we are pre-equalizing and overdriving the low + * swing wires, the net time constant is less + * than the actual value + */ + delay += + horowitz(inputrise, timeconst, deviceType->Vth / deviceType->Vdd, .25, 0); +#define VOL_SWING .1 + temp_power += cap_eq * VOL_SWING * .400; /* .4v is the over drive voltage */ + temp_power *= 2; /* differential wire */ + + l_wire.delay = delay - transmitter.delay; + l_wire.power.readOp.dynamic = temp_power - transmitter.power.readOp.dynamic; + l_wire.power.readOp.leakage = + deviceType->Vdd * (4 * cmos_Isub_leakage(nsize, 0, 1, nmos)); + + l_wire.power.readOp.gate_leakage = + deviceType->Vdd * (4 * cmos_Ig_leakage(nsize, 0, 1, nmos)); + + // double rt = horowitz(inputrise, timeconst, deviceType->Vth/deviceType->Vdd, + // deviceType->Vth/deviceType->Vdd, RISE)/deviceType->Vth; + + delay += g_tp.sense_delay; + + sense_amp.delay = g_tp.sense_delay; + out_rise_time = g_tp.sense_delay / (deviceType->Vth); + sense_amp.power.readOp.dynamic = g_tp.sense_dy_power; + sense_amp.power.readOp.leakage = 0; // FIXME + sense_amp.power.readOp.gate_leakage = 0; + + power.readOp.dynamic = temp_power + sense_amp.power.readOp.dynamic; + power.readOp.leakage = transmitter.power.readOp.leakage + + l_wire.power.readOp.leakage + + sense_amp.power.readOp.leakage; + power.readOp.gate_leakage = transmitter.power.readOp.gate_leakage + + l_wire.power.readOp.gate_leakage + + sense_amp.power.readOp.gate_leakage; +} + +double Wire::sense_amp_input_cap() { + return drain_C_(g_tp.w_iso, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(g_tp.w_sense_en + g_tp.w_sense_n, 0) + + drain_C_(g_tp.w_sense_n, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.w_sense_p, PCH, 1, 1, g_tp.cell_h_def); +} + +void Wire::delay_optimal_wire(/*bool reset_repeater_sizing*/) { + double len = wire_length; + // double min_wire_width = wire_width; //m + double beta = pmos_to_nmos_sz_ratio(); + double switching = 0; // switching energy + double short_ckt = 0; // short-circuit energy + double tc = 0; // time constant + // input cap of min sized driver + double input_cap = gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0); + + // output parasitic capacitance of + // the min. sized driver + double out_cap = drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def); + // drive resistance + double out_res = + (tr_R_on(g_tp.min_w_nmos_, NCH, 1) + tr_R_on(min_w_pmos, PCH, 1)) / 2; + double wr = wire_res(len); // ohm + + // wire cap /m + double wc = wire_cap(len); + + // size the repeater such that the delay of the wire is minimum + double repeater_scaling = + sqrt(out_res * wc / (wr * input_cap)); // len will cancel + + // calc the optimum spacing between the repeaters (m) + + // if (reset_repeater_sizing==true) { + + repeater_spacing_init = + sqrt(2 * out_res * (out_cap + input_cap) / ((wr / len) * (wc / len))); + repeater_size_init = repeater_scaling; + // } + + switching = (repeater_scaling * (input_cap + out_cap) + + repeater_spacing_init * (wc / len)) * + deviceType->Vdd * deviceType->Vdd; + + tc = out_res * (input_cap + out_cap) + + out_res * wc / len * repeater_spacing_init / repeater_scaling + + wr / len * repeater_spacing_init * input_cap * repeater_scaling + + 0.5 * (wr / len) * (wc / len) * repeater_spacing_init * + repeater_spacing_init; + + delay = 0.693 * tc * len / repeater_spacing_init; + +#define Ishort_ckt 65e-6 /* across all tech Ref:Banerjee et al. {IEEE TED} */ + short_ckt = deviceType->Vdd * g_tp.min_w_nmos_ * Ishort_ckt * 1.0986 * + repeater_scaling * tc; + + area.set_area((len / repeater_spacing_init) * + compute_gate_area(INV, 1, min_w_pmos * repeater_scaling, + g_tp.min_w_nmos_ * repeater_scaling, + g_tp.cell_h_def)); + power.readOp.dynamic = + ((len / repeater_spacing_init) * (switching + short_ckt)); + power.readOp.leakage = + ((len / repeater_spacing_init) * deviceType->Vdd * + cmos_Isub_leakage(g_tp.min_w_nmos_ * repeater_scaling, + beta * g_tp.min_w_nmos_ * repeater_scaling, 1, inv)); + power.readOp.gate_leakage = + ((len / repeater_spacing_init) * deviceType->Vdd * + cmos_Ig_leakage(g_tp.min_w_nmos_ * repeater_scaling, + beta * g_tp.min_w_nmos_ * repeater_scaling, 1, inv)); +} + +// calculate power/delay values for wires with suboptimal repeater +// sizing/spacing +void Wire::init_wire(/*bool reset_repeater_sizing*/) { + wire_length = 1; + delay_optimal_wire(/*reset_repeater_sizing*/); + double sp, si; + powerDef pow; + si = repeater_size_init; + sp = repeater_spacing_init; + sp *= 1e6; // in microns + + double i, j, del; + repeated_wire.push_back(Component()); + for (j = sp; j < 4 * sp; j += 100) { + for (i = si; i > 1; i--) { + pow = wire_model(j * 1e-6, i, &del); + if (j == sp && i == si) { + global.delay = del; + global.power = pow; + global.area.h = si; + global.area.w = sp * 1e-6; // m + } + // cout << "Repeater size - "<< i << + // " Repeater spacing - " << j << + // " Delay - " << del << + // " PowerD - " << pow.readOp.dynamic << + // " PowerL - " << pow.readOp.leakage <delay; + low_swing.power = l_wire->power; + delete l_wire; +} + +void Wire::update_fullswing() { + list::iterator citer; + double del[4]; + del[3] = this->global.delay + this->global.delay * .3; + del[2] = global.delay + global.delay * .2; + del[1] = global.delay + global.delay * .1; + del[0] = global.delay + global.delay * .05; + double threshold; + double ncost; + double cost; + int i = 4; + while (i > 0) { + threshold = del[i - 1]; + cost = BIGNUM; + for (citer = repeated_wire.begin(); citer != repeated_wire.end(); citer++) { + if (citer->delay > threshold) { + citer = repeated_wire.erase(citer); + citer--; + } + else { + ncost = citer->power.readOp.dynamic / global.power.readOp.dynamic + + citer->power.readOp.leakage / global.power.readOp.leakage; + if (ncost < cost) { + cost = ncost; + if (i == 4) { + global_30.delay = citer->delay; + global_30.power = citer->power; + global_30.area = citer->area; + } + else if (i == 3) { + global_20.delay = citer->delay; + global_20.power = citer->power; + global_20.area = citer->area; + } + else if (i == 2) { + global_10.delay = citer->delay; + global_10.power = citer->power; + global_10.area = citer->area; + } + else if (i == 1) { + global_5.delay = citer->delay; + global_5.power = citer->power; + global_5.area = citer->area; + } + } + } + } + i--; + } + citer = repeated_wire.begin(); + while (!repeated_wire.empty()) // TODO: code optimize + { + citer = repeated_wire.erase(citer); + } +} + +powerDef Wire::wire_model(double space, double size, double *delay) { + powerDef ptemp; + double len = 1; + // double min_wire_width = wire_width; //m + double beta = pmos_to_nmos_sz_ratio(); + // switching energy + double switching = 0; + // short-circuit energy + double short_ckt = 0; + // time constant + double tc = 0; + // input cap of min sized driver + double input_cap = gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0); + + // output parasitic capacitance of + // the min. sized driver + double out_cap = drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def); + // drive resistance + double out_res = + (tr_R_on(g_tp.min_w_nmos_, NCH, 1) + tr_R_on(min_w_pmos, PCH, 1)) / 2; + double wr = wire_res(len); // ohm + + // wire cap /m + double wc = wire_cap(len); + + repeater_spacing = space; + repeater_size = size; + + switching = + (repeater_size * (input_cap + out_cap) + repeater_spacing * (wc / len)) * + deviceType->Vdd * deviceType->Vdd; + + tc = out_res * (input_cap + out_cap) + + out_res * wc / len * repeater_spacing / repeater_size + + wr / len * repeater_spacing * out_cap * repeater_size + + 0.5 * (wr / len) * (wc / len) * repeater_spacing * repeater_spacing; + + *delay = 0.693 * tc * len / repeater_spacing; + +#define Ishort_ckt 65e-6 /* across all tech Ref:Banerjee et al. {IEEE TED} */ + short_ckt = deviceType->Vdd * g_tp.min_w_nmos_ * Ishort_ckt * 1.0986 * + repeater_size * tc; + + ptemp.readOp.dynamic = ((len / repeater_spacing) * (switching + short_ckt)); + ptemp.readOp.leakage = + ((len / repeater_spacing) * deviceType->Vdd * + cmos_Isub_leakage(g_tp.min_w_nmos_ * repeater_size, + beta * g_tp.min_w_nmos_ * repeater_size, 1, inv)); + + ptemp.readOp.gate_leakage = + ((len / repeater_spacing) * deviceType->Vdd * + cmos_Ig_leakage(g_tp.min_w_nmos_ * repeater_size, + beta * g_tp.min_w_nmos_ * repeater_size, 1, inv)); + + return ptemp; +} + +void Wire::print_wire() { + cout << "\nWire Properties at DVS level 0:\n\n"; + cout << " Delay Optimal\n\tRepeater size - " << global.area.h + << " \n\tRepeater spacing - " << global.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + + cout << " 5% Overhead\n\tRepeater size - " << global_5.area.h + << " \n\tRepeater spacing - " << global_5.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_5.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_5.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_5.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_5.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " 10% Overhead\n\tRepeater size - " << global_10.area.h + << " \n\tRepeater spacing - " << global_10.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_10.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_10.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_10.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_10.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " 20% Overhead\n\tRepeater size - " << global_20.area.h + << " \n\tRepeater spacing - " << global_20.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_20.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_20.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_20.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_20.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " 30% Overhead\n\tRepeater size - " << global_30.area.h + << " \n\tRepeater spacing - " << global_30.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_30.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_30.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_30.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_30.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " Low-swing wire (1 mm) - Note: Unlike repeated wires, \n\tdelay " + "and power " + "values of low-swing wires do not\n\thave a linear relationship with " + "length." + << " \n\tdelay - " << low_swing.delay * 1e9 + << " (ns)" + " \n\tpowerD - " + << low_swing.power.readOp.dynamic * 1e9 + << " (nJ)" + " \n\tPowerL - " + << low_swing.power.readOp.leakage + << " (mW)" + " \n\tPowerLgate - " + << low_swing.power.readOp.gate_leakage << " (mW)\n"; + cout << "\tWire width - " + << wire_width_init * 2 /* differential */ << " microns\n"; + cout << "\tWire spacing - " + << wire_spacing_init * 2 /* differential */ << " microns\n"; + cout << endl; + cout << endl; + + // cout<<"repeater_size_init"<delay; + low_swing.power = l_wire->power; + delete l_wire; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/wire.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/wire.h new file mode 100644 index 0000000000..c652e9f36a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/cacti/wire.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __WIRE_H__ +#define __WIRE_H__ + +#include +#include +#include "assert.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "parameter.h" + +namespace cacti { + +class Wire : public Component { + public: + Wire(enum Wire_type wire_model, double len /* in u*/, + int nsense = 1 /* no. of sense amps connected to the low-swing wire */, + double width_scaling = 1, double spacing_scaling = 1, + enum Wire_placement wire_placement = outside_mat, + double resistivity = CU_RESISTIVITY, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + ~Wire(); + + Wire(double width_scaling = 1, double spacing_scaling = 1, + // bool reset_repeater_sizing = true, + enum Wire_placement wire_placement = outside_mat, + double resistivity = CU_RESISTIVITY, + TechnologyParameter::DeviceType *dt = + &(g_tp.peri_global)); // should be used only once for initializing + // static members + void init_wire(/*bool reset_repeater_sizing = true*/); + + void calculate_wire_stats(); + void delay_optimal_wire(/*bool reset_repeater_sizing = true*/); + double wire_cap(double len, bool call_from_outside = false); + double wire_res(double len); + void low_swing_model(); + double signal_fall_time(); + double signal_rise_time(); + double sense_amp_input_cap(); + + enum Wire_type wt; + double wire_spacing; + double wire_width; + enum Wire_placement wire_placement; + double repeater_size; + double repeater_spacing; + static double repeater_size_init; // value used in initialization should not + // be reused in final output + static double repeater_spacing_init; + double wire_length; + double in_rise_time, out_rise_time; + + void set_in_rise_time(double rt) { in_rise_time = rt; } + static Component global; + static Component global_5; + static Component global_10; + static Component global_20; + static Component global_30; + static Component low_swing; + static double wire_width_init; + static double wire_spacing_init; + static void print_wire(); + void wire_dvs_update(); + + private: + int nsense; // no. of sense amps connected to a low-swing wire if it + // is broadcasting data to multiple destinations + // width and spacing scaling factor can be used + // to model low level wires or special + // fat wires + double w_scale, s_scale; + double resistivity; + powerDef wire_model(double space, double size, double *delay); + list repeated_wire; + void update_fullswing(); + static int initialized; + + // low-swing + Component transmitter; + Component l_wire; + Component sense_amp; + + double min_w_pmos; + + TechnologyParameter::DeviceType *deviceType; +}; + +} // namespace cacti + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/core.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/core.cc new file mode 100644 index 0000000000..79c43e0b61 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/core.cc @@ -0,0 +1,5893 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "core.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +//#include "globalvar.h" + +InstFetchU::InstFetchU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + IB(0), + BTB(0), + ID_inst(0), + ID_operand(0), + ID_misc(0), + exist(exist_) { + if (!exist) + return; + int idx, tag, data, size, line, assoc, banks; + bool debug = false, is_default = true; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + cache_p = (Cache_policy)(int)XML->sys.core[ithCore].icache.icache_config[7]; + // Assuming all L1 caches are virtually idxed physically tagged. + // cache + + size = (int)XML->sys.core[ithCore].icache.icache_config[0]; + line = (int)XML->sys.core[ithCore].icache.icache_config[1]; + assoc = (int)XML->sys.core[ithCore].icache.icache_config[2]; + banks = (int)XML->sys.core[ithCore].icache.icache_config[3]; + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + tag = debug ? 51 + : (int)XML->sys.physical_address_width - idx - + int(ceil(log2(line))) + EXTRA_TAG_BITS; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + debug ? 32768 : (int)XML->sys.core[ithCore].icache.icache_config[0]; + interface_ip.line_sz = + debug ? 64 : (int)XML->sys.core[ithCore].icache.icache_config[1]; + interface_ip.assoc = + debug ? 8 : (int)XML->sys.core[ithCore].icache.icache_config[2]; + interface_ip.nbanks = + debug ? 1 : (int)XML->sys.core[ithCore].icache.icache_config[3]; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = + 0; // debug?0:XML->sys.core[ithCore].icache.icache_config[5]; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 3.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + // interface_ip.obj_func_dyn_energy = 0; + // interface_ip.obj_func_dyn_power = 0; + // interface_ip.obj_func_leak_power = 0; + // interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + icache.caches = new ArrayST(&interface_ip, "icache", Core_device, + coredynp.opt_local, coredynp.core_ty); + scktRatio = g_tp.sckt_co_eff; + chip_PR_overhead = g_tp.chip_layout_overhead; + macro_PR_overhead = g_tp.macro_layout_overhead; + icache.area.set_area(icache.area.get_area() + + icache.caches->local_result.area); + area.set_area(area.get_area() + icache.caches->local_result.area); + // output_data_csv(icache.caches.local_result); + + /* + *iCache controllers + *miss buffer Each MSHR contains enough state + *to handle one or more accesses of any type to a single memory line. + *Due to the generality of the MSHR mechanism, + *the amount of state involved is non-trivial: + *including the address, pointers to the cache entry and destination register, + *written data, and various other pieces of state. + */ + interface_ip.num_search_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = (XML->sys.physical_address_width) + int(ceil(log2(size / line))) + + icache.caches->l_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].icache.buffer_sizes[0] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / + clockRate; // means cycle time + interface_ip.latency = debug + ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / + clockRate; // means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + XML->sys.core[ithCore].number_instruction_fetch_ports; + icache.missb = new ArrayST(&interface_ip, "icacheMissBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + icache.area.set_area(icache.area.get_area() + + icache.missb->local_result.area); + area.set_area(area.get_area() + icache.missb->local_result.area); + // output_data_csv(icache.missb.local_result); + + // fill buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = icache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data * XML->sys.core[ithCore].icache.buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + XML->sys.core[ithCore].number_instruction_fetch_ports; + icache.ifb = new ArrayST(&interface_ip, "icacheFillBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + icache.area.set_area(icache.area.get_area() + icache.ifb->local_result.area); + area.set_area(area.get_area() + icache.ifb->local_result.area); + // output_data_csv(icache.ifb.local_result); + + // prefetch buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; // check with + // previous entries + // to decide wthether + // to merge. + data = icache.caches->l_ip + .line_sz; // separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = + XML->sys.core[ithCore].icache.buffer_sizes[2] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + XML->sys.core[ithCore].number_instruction_fetch_ports; + icache.prefetchb = + new ArrayST(&interface_ip, "icacheprefetchBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + icache.area.set_area(icache.area.get_area() + + icache.prefetchb->local_result.area); + area.set_area(area.get_area() + icache.prefetchb->local_result.area); + // output_data_csv(icache.prefetchb.local_result); + + // Instruction buffer + data = + XML->sys.core[ithCore].instruction_length * + XML->sys.core[ithCore].peak_issue_width; // icache.caches.l_ip.line_sz; + // //multiple threads timing + // sharing the instruction + // buffer. + interface_ip.is_cache = false; + interface_ip.pure_ram = true; + interface_ip.pure_cam = false; + interface_ip.line_sz = int(ceil(data / 8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].number_hardware_threads * + XML->sys.core[ithCore].instruction_buffer_size * + interface_ip.line_sz > + 64 + ? XML->sys.core[ithCore].number_hardware_threads * + XML->sys.core[ithCore].instruction_buffer_size * + interface_ip.line_sz + : 64; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + // NOTE: Assuming IB is time slice shared among threads, every fetch op will + // at least fetch "fetch width" instructions. + interface_ip.num_rw_ports = + debug + ? 1 + : XML->sys.core[ithCore] + .number_instruction_fetch_ports; // XML->sys.core[ithCore].fetch_width; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + IB = new ArrayST(&interface_ip, "InstBuffer", Core_device, coredynp.opt_local, + coredynp.core_ty); + IB->area.set_area(IB->area.get_area() + IB->local_result.area); + area.set_area(area.get_area() + IB->local_result.area); + // output_data_csv(IB.IB.local_result); + + // inst_decoder.opcode_length = XML->sys.core[ithCore].opcode_width; + // inst_decoder.init_decoder(is_default, &interface_ip); + // inst_decoder.full_decoder_power(); + + if (coredynp.predictionW > 0) { + /* + * BTB branch target buffer, accessed during IF stage. Virtually indexed and + * virtually tagged It is only a cache without all the buffers in the cache + * controller since it is more like a look up table than a cache with cache + * controller. When access miss, no load from other places such as main + * memory (not actively fill the misses), it is passively updated under two + * circumstances: 1) when BPT@ID stage finds out current is a taken branch + * while BTB missed 2) When BPT@ID stage predicts differently than BTB 3) + * When ID stage finds out current instruction is not a branch while BTB had + * a hit.(mark as invalid) 4) when EXEU find out wrong target has been + * provided from BTB. + * + */ + size = XML->sys.core[ithCore].BTB.BTB_config[0]; + line = XML->sys.core[ithCore].BTB.BTB_config[1]; + assoc = XML->sys.core[ithCore].BTB.BTB_config[2]; + banks = XML->sys.core[ithCore].BTB.BTB_config[3]; + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + // tag = + // debug?51:XML->sys.virtual_address_width-idx-int(ceil(log2(line))) + + // int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + // +EXTRA_TAG_BITS; + tag = debug ? 51 + : XML->sys.virtual_address_width + + int(ceil(log2( + XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = debug ? 32768 : size; + interface_ip.line_sz = debug ? 64 : line; + interface_ip.assoc = debug ? 8 : assoc; + interface_ip.nbanks = debug ? 1 : banks; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = + 0; // debug?0:XML->sys.core[ithCore].dcache.dcache_config[5]; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].BTB.BTB_config[4] / clockRate; + interface_ip.latency = + debug ? 3.0 / clockRate + : XML->sys.core[ithCore].BTB.BTB_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + BTB = new ArrayST(&interface_ip, "Branch Target Buffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + BTB->area.set_area(BTB->area.get_area() + BTB->local_result.area); + area.set_area(area.get_area() + BTB->local_result.area); + /// cout<<"area="<area.get_area()); + } + + ID_inst = new inst_decoder(is_default, &interface_ip, coredynp.opcode_length, + 1 /*Decoder should not know how many by itself*/, + coredynp.x86, Core_device, coredynp.core_ty); + + ID_operand = + new inst_decoder(is_default, &interface_ip, coredynp.arch_ireg_width, 1, + coredynp.x86, Core_device, coredynp.core_ty); + + ID_misc = new inst_decoder(is_default, &interface_ip, + 8 /* Prefix field etc upto 14B*/, 1, coredynp.x86, + Core_device, coredynp.core_ty); + // TODO: X86 decoder should decode the inst in cyclic mode under the control + // of squencer. So the dynamic power should be multiplied by a few times. + area.set_area(area.get_area() + + (ID_inst->area.get_area() + ID_operand->area.get_area() + + ID_misc->area.get_area()) * + coredynp.decodeW); +} + +BranchPredictor::BranchPredictor(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + globalBPT(0), + localBPT(0), + L1_localBPT(0), + L2_localBPT(0), + chooser(0), + RAS(0), + exist(exist_) { + /* + * Branch Predictor, accessed during ID stage. + * McPAT's branch predictor model is the tournament branch predictor used in + * Alpha 21264, including global predictor, local two level predictor, and + * Chooser. The Branch predictor also includes a RAS (return address stack) + * for function calls Branch predictors are tagged by thread ID and modeled as + * 1-way associative cache. However RAS return address stacks are duplicated + * for each thread. + * TODO:Data Width need to be computed more precisely * + */ + if (!exist) + return; + int tag, data; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + interface_ip.assoc = 1; + interface_ip.pure_cam = false; + if (coredynp.multithreaded) { + tag = int(log2(coredynp.num_hthreads) + EXTRA_TAG_BITS); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + } + else { + interface_ip.is_cache = false; + interface_ip.pure_ram = true; + } + // Global predictor + data = + int(ceil(XML->sys.core[ithCore].predictor.global_predictor_bits / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.global_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + globalBPT = new ArrayST(&interface_ip, "Global Predictor", Core_device, + coredynp.opt_local, coredynp.core_ty); + globalBPT->area.set_area(globalBPT->area.get_area() + + globalBPT->local_result.area); + area.set_area(area.get_area() + globalBPT->local_result.area); + + // Local BPT (Level 1) + data = + int(ceil(XML->sys.core[ithCore].predictor.local_predictor_size[0] / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.local_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + L1_localBPT = new ArrayST(&interface_ip, "L1 local Predictor", Core_device, + coredynp.opt_local, coredynp.core_ty); + L1_localBPT->area.set_area(L1_localBPT->area.get_area() + + L1_localBPT->local_result.area); + area.set_area(area.get_area() + L1_localBPT->local_result.area); + + // Local BPT (Level 2) + data = + int(ceil(XML->sys.core[ithCore].predictor.local_predictor_size[1] / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.local_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + L2_localBPT = new ArrayST(&interface_ip, "L2 local Predictor", Core_device, + coredynp.opt_local, coredynp.core_ty); + L2_localBPT->area.set_area(L2_localBPT->area.get_area() + + L2_localBPT->local_result.area); + area.set_area(area.get_area() + L2_localBPT->local_result.area); + + // Chooser + data = + int(ceil(XML->sys.core[ithCore].predictor.chooser_predictor_bits / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.chooser_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + chooser = new ArrayST(&interface_ip, "Predictor Chooser", Core_device, + coredynp.opt_local, coredynp.core_ty); + chooser->area.set_area(chooser->area.get_area() + chooser->local_result.area); + area.set_area(area.get_area() + chooser->local_result.area); + + // RAS return address stacks are Duplicated for each thread. + interface_ip.is_cache = false; + interface_ip.pure_ram = true; + data = int(ceil(coredynp.pc_width / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].RAS_size; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + RAS = new ArrayST(&interface_ip, "RAS", Core_device, coredynp.opt_local, + coredynp.core_ty); + RAS->area.set_area(RAS->area.get_area() + + RAS->local_result.area * coredynp.num_hthreads); + area.set_area(area.get_area() + + RAS->local_result.area * coredynp.num_hthreads); +} + +SchedulerU::SchedulerU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + int_inst_window(0), + fp_inst_window(0), + ROB(0), + instruction_selection(0), + exist(exist_) { + if (!exist) + return; + int tag, data; + bool is_default = true; + string tmp_name; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + if (coredynp.core_ty == Inorder && coredynp.multithreaded) { + // Instruction issue queue, in-order multi-issue or multithreaded processor + // also has this structure. Unified window for Inorder processors + tag = int(log2(XML->sys.core[ithCore].number_hardware_threads) * + coredynp.perThreadState); // This is the normal thread state bits + // based on Niagara Design + data = XML->sys.core[ithCore].instruction_length; + // NOTE: x86 inst can be very lengthy, up to 15B. Source: Intel® 64 and + // IA-32 Architectures Software Developer’s Manual + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = int(ceil(data / 8.0)); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + XML->sys.core[ithCore].instruction_window_size * interface_ip.line_sz > + 64 + ? XML->sys.core[ithCore].instruction_window_size * + interface_ip.line_sz + : 64; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.peak_issueW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = coredynp.peak_issueW; + int_inst_window = new ArrayST(&interface_ip, "InstFetchQueue", Core_device, + coredynp.opt_local, coredynp.core_ty); + int_inst_window->area.set_area(int_inst_window->area.get_area() + + int_inst_window->local_result.area * + coredynp.num_pipelines); + area.set_area(area.get_area() + + int_inst_window->local_result.area * coredynp.num_pipelines); + // output_data_csv(iRS.RS.local_result); + Iw_height = int_inst_window->local_result.cache_ht; + + /* + * selection logic + * In a single-issue Inorder multithreaded processor like Niagara, issue + * width=1*number_of_threads since the processor does need to pick up + * instructions from multiple ready ones(although these ready ones are from + * different threads).While SMT processors do not distinguish which thread + * belongs to who at the issue stage. + */ + interface_ip.assoc = + 1; // reset to prevent unnecessary warning messages when init_interface + instruction_selection = new selection_logic( + is_default, XML->sys.core[ithCore].instruction_window_size, + coredynp.peak_issueW * XML->sys.core[ithCore].number_hardware_threads, + &interface_ip, Core_device, coredynp.core_ty); + } + + if (coredynp.core_ty == OOO) { + /* + * CAM based instruction window + * For physicalRegFilebased OOO it is the instruction issue queue, where + * only tags of phy regs are stored For RS based OOO it is the Reservation + * station, where both tags and values of phy regs are stored It is written + * once and read twice(two operands) before an instruction can be issued. + * X86 instruction can be very long up to 15B. add instruction length in XML + */ + if (coredynp.scheu_ty == PhysicalRegFile) { + tag = coredynp.phy_ireg_width; + // Each time only half of the tag is compared, but two tag should be + // stored. This underestimate the search power + data = + int((ceil((coredynp.instruction_length + + 2 * (coredynp.phy_ireg_width - coredynp.arch_ireg_width)) / + 2.0) / + 8.0)); + // Data width being divided by 2 means only after both operands available + // the whole data will be read out. This is modeled using two equivalent + // readouts with half of the data width + tmp_name = "InstIssueQueue"; + } + else { + tag = coredynp.phy_ireg_width; + // Each time only half of the tag is compared, but two tag should be + // stored. This underestimate the search power + data = + int(ceil(((coredynp.instruction_length + + 2 * (coredynp.phy_ireg_width - coredynp.arch_ireg_width) + + 2 * coredynp.int_data_width) / + 2.0) / + 8.0)); + // Data width being divided by 2 means only after both operands available + // the whole data will be read out. This is modeled using two equivalent + // readouts with half of the data width + + tmp_name = "IntReservationStation"; + } + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].instruction_window_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 0; + interface_ip.throughput = 2 * 1.0 / clockRate; + interface_ip.latency = 2 * 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.peak_issueW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = coredynp.peak_issueW; + int_inst_window = new ArrayST(&interface_ip, tmp_name, Core_device, + coredynp.opt_local, coredynp.core_ty); + int_inst_window->area.set_area(int_inst_window->area.get_area() + + int_inst_window->local_result.area * + coredynp.num_pipelines); + area.set_area(area.get_area() + + int_inst_window->local_result.area * coredynp.num_pipelines); + Iw_height = int_inst_window->local_result.cache_ht; + // FU inst window + if (coredynp.scheu_ty == PhysicalRegFile) { + tag = 2 * coredynp.phy_freg_width; // TODO: each time only half of the + // tag is compared + data = + int(ceil((coredynp.instruction_length + + 2 * (coredynp.phy_freg_width - coredynp.arch_freg_width)) / + 8.0)); + tmp_name = "FPIssueQueue"; + } + else { + tag = 2 * coredynp.phy_ireg_width; + data = + int(ceil((coredynp.instruction_length + + 2 * (coredynp.phy_freg_width - coredynp.arch_freg_width) + + 2 * coredynp.fp_data_width) / + 8.0)); + tmp_name = "FPReservationStation"; + } + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].fp_instruction_window_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.fp_issueW; + interface_ip.num_wr_ports = coredynp.fp_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = coredynp.fp_issueW; + fp_inst_window = new ArrayST(&interface_ip, tmp_name, Core_device, + coredynp.opt_local, coredynp.core_ty); + fp_inst_window->area.set_area(fp_inst_window->area.get_area() + + fp_inst_window->local_result.area * + coredynp.num_fp_pipelines); + area.set_area(area.get_area() + fp_inst_window->local_result.area * + coredynp.num_fp_pipelines); + fp_Iw_height = fp_inst_window->local_result.cache_ht; + + if (XML->sys.core[ithCore].ROB_size > 0) { + /* + * if ROB_size = 0, then the target processor does not support + *hardware-based speculation, i.e. , the processor allow OOO issue as well + *as OOO completion, which means branch must be resolved before + *instruction issued into instruction window, since there is no change + *to flush miss-predict branch path after instructions are issued in + *this situation. + * + * ROB.ROB size = inflight inst. ROB is unified for int and fp inst. + * One old approach is to combine the RAT and ROB as a huge CAM structure + *as in AMD K7. However, this approach is abandoned due to its high power + *and poor scalability. McPAT uses current implementation of ROB as + *circular buffer. ROB is written once when instruction is issued and + *read once when the instruction is committed. * + */ + + int robExtra = int(ceil(5 + log2(coredynp.num_hthreads))); + data = int(ceil( + (robExtra + coredynp.pc_width + + ((coredynp.rm_ty == RAMbased) + ? (coredynp.phy_ireg_width + coredynp.phy_freg_width) + : fmax(coredynp.phy_ireg_width, coredynp.phy_freg_width)) + + ((coredynp.scheu_ty == PhysicalRegFile) ? 0 + : coredynp.fp_data_width)) / + 8.0)); + /* + * 5 bits are: busy, Issued, Finished, speculative, valid; + * PC is to id the instruction for recover + * exception/mis-prediction. When using RAM-based RAT, ROB needs to + * contain the ARF-PRF mapping to index the correct entry in the RAT, so + * that the correct architecture register (and freelist) can be found and + * the RAT can be appropriately updated; otherwise, the RAM-based RAT + * needs to support search ops to identify the target architecture + * register that needs to be updated, or the physical resigner that needs + * to be recycled; When using CAM-based RAT, ROB only needs to contain + * destination physical register since the CAM-base RAT can search for + * the corresponding ARF-PRF mapping to find the correct entry in the RAT, + * so that the correct architecture register (and freelist/bits) can be + * found and the RAT can be appropriately updated. ROB phy_reg entry + * should use the larger one from phy_ireg and phy_freg; fdata_width is + * always larger. Latest Intel Processors may have different ROB/RS + * designs. + */ + + /* + if(coredynp.scheu_ty==PhysicalRegFile) + { + //PC is to id the instruction for recover + exception. + //inst is used to map the renamed dest. + registers.so that commit stage can know which reg/RRAT to update + // data = + int(ceil((robExtra+coredynp.pc_width + + + // coredynp.instruction_length + + 2*coredynp.phy_ireg_width)/8.0)); + + if (coredynp.rm_ty ==RAMbased) + { + data = int(ceil((robExtra + + coredynp.pc_width + (coredynp.phy_ireg_width, + coredynp.phy_freg_width))/8.0)); + //When using RAM-based RAT, ROB + needs to contain the ARF-PRF mapping to index the correct entry in the + RAT, + //so that the correct architecture + register (and freelist) can be found and the RAT can be appropriately + updated. + } + else if (coredynp.rm_ty ==CAMbased) + { + data = + int(ceil((robExtra+coredynp.pc_width + fmax(coredynp.phy_ireg_width, + coredynp.phy_freg_width))/8.0)); + //When using CAM-based RAT, ROB + needs to contain the ARF-PRF mapping to index the correct entry in the + RAT, + //so that the correct architecture register (and freelist) can be found and the RAT can be appropriately updated. + } + } + else + { + //in RS based OOO, ROB also contains value + of destination reg + // data = + int(ceil((robExtra+coredynp.pc_width + + + // coredynp.instruction_length + + 2*coredynp.phy_ireg_width + + coredynp.fp_data_width)/8.0)); + + //using phy_reg number to search in the + RAT, the correct architecture register can be found and the RAT can be + appropriately updated. + //ROB phy_reg entry should use the larger + one from ireg and freg; fdata_width is always larger; Latest Intel + Processors may have different ROB/RS designs. data = int(ceil((robExtra + + coredynp.pc_width + fmax(coredynp.phy_ireg_width, coredynp.phy_freg_width) + + coredynp.fp_data_width)/8.0)); + } + */ + + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore] + .ROB_size; // The XML ROB size is for all threads + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.peak_commitW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 0; + ROB = new ArrayST(&interface_ip, "ReorderBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + ROB->area.set_area(ROB->area.get_area() + + ROB->local_result.area * coredynp.num_pipelines); + area.set_area(area.get_area() + + ROB->local_result.area * coredynp.num_pipelines); + ROB_height = ROB->local_result.cache_ht; + } + + instruction_selection = new selection_logic( + is_default, XML->sys.core[ithCore].instruction_window_size, + coredynp.peak_issueW, &interface_ip, Core_device, coredynp.core_ty); + } +} + +LoadStoreU::LoadStoreU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + LSQ(0), + LoadQ(0), + exist(exist_) { + if (!exist) + return; + int idx, tag, data, size, line, assoc; + bool debug = false; + int ldst_opcode = XML->sys.core[ithCore].opcode_width; // 16; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + cache_p = (Cache_policy)(int)XML->sys.core[ithCore].dcache.dcache_config[7]; + + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + // Dcache + size = (int)XML->sys.core[ithCore].dcache.dcache_config[0]; + line = (int)XML->sys.core[ithCore].dcache.dcache_config[1]; + assoc = (int)XML->sys.core[ithCore].dcache.dcache_config[2]; + // banks = (int)XML->sys.core[ithCore].dcache.dcache_config[3]; + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + tag = debug ? 51 + : XML->sys.physical_address_width - idx - int(ceil(log2(line))) + + EXTRA_TAG_BITS; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + debug ? 32768 : (int)XML->sys.core[ithCore].dcache.dcache_config[0]; + interface_ip.line_sz = + debug ? 64 : (int)XML->sys.core[ithCore].dcache.dcache_config[1]; + interface_ip.assoc = + debug ? 8 : (int)XML->sys.core[ithCore].dcache.dcache_config[2]; + interface_ip.nbanks = + debug ? 1 : (int)XML->sys.core[ithCore].dcache.dcache_config[3]; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = + 0; // debug?0:XML->sys.core[ithCore].dcache.dcache_config[5]; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 3.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.is_cache = true; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].memory_ports; // usually In-order has + // 1 and OOO has 2 at + // least. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.caches = new ArrayST(&interface_ip, "dcache", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.caches->local_result.area); + area.set_area(area.get_area() + dcache.caches->local_result.area); + // output_data_csv(dcache.caches.local_result); + + // dCache controllers + // miss buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = (XML->sys.physical_address_width) + int(ceil(log2(size / line))) + + dcache.caches->l_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].dcache.buffer_sizes[0] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = debug ? 1 : XML->sys.core[ithCore].memory_ports; + ; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.missb = new ArrayST(&interface_ip, "dcacheMissBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.missb->local_result.area); + area.set_area(area.get_area() + dcache.missb->local_result.area); + // output_data_csv(dcache.missb.local_result); + + // fill buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = dcache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data * XML->sys.core[ithCore].dcache.buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = debug ? 1 : XML->sys.core[ithCore].memory_ports; + ; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.ifb = new ArrayST(&interface_ip, "dcacheFillBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + dcache.ifb->local_result.area); + area.set_area(area.get_area() + dcache.ifb->local_result.area); + // output_data_csv(dcache.ifb.local_result); + + // prefetch buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; // check with + // previous entries + // to decide wthether + // to merge. + data = dcache.caches->l_ip + .line_sz; // separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = + XML->sys.core[ithCore].dcache.buffer_sizes[2] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = debug ? 1 : XML->sys.core[ithCore].memory_ports; + ; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.prefetchb = + new ArrayST(&interface_ip, "dcacheprefetchBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.prefetchb->local_result.area); + area.set_area(area.get_area() + dcache.prefetchb->local_result.area); + // output_data_csv(dcache.prefetchb.local_result); + + // WBB + + if (cache_p == Write_back) { + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = dcache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.core[ithCore].dcache.buffer_sizes[3] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.wbb = new ArrayST(&interface_ip, "dcacheWBB", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.wbb->local_result.area); + area.set_area(area.get_area() + dcache.wbb->local_result.area); + // output_data_csv(dcache.wbb.local_result); + } + + /* + * LSU--in-order processors do not have separate load queue: unified lsq + * partitioned among threads + * it is actually the store queue but for inorder processors it serves as both + * loadQ and StoreQ + */ + tag = ldst_opcode + XML->sys.virtual_address_width + + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + data = XML->sys.machine_bits; + interface_ip.is_cache = true; + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + XML->sys.core[ithCore].store_buffer_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + LSQ = new ArrayST(&interface_ip, "Load(Store)Queue", Core_device, + coredynp.opt_local, coredynp.core_ty); + LSQ->area.set_area(LSQ->area.get_area() + LSQ->local_result.area); + area.set_area(area.get_area() + LSQ->local_result.area); + // output_data_csv(LSQ.LSQ.local_result); + lsq_height = + LSQ->local_result.cache_ht * + sqrt(cdb_overhead); /*XML->sys.core[ithCore].number_hardware_threads*/ + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + XML->sys.core[ithCore].load_buffer_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + LoadQ = new ArrayST(&interface_ip, "LoadQueue", Core_device, + coredynp.opt_local, coredynp.core_ty); + LoadQ->area.set_area(LoadQ->area.get_area() + LoadQ->local_result.area); + area.set_area(area.get_area() + LoadQ->local_result.area); + // output_data_csv(LoadQ.LoadQ.local_result); + lsq_height = + (LSQ->local_result.cache_ht + LoadQ->local_result.cache_ht) * + sqrt(cdb_overhead); /*XML->sys.core[ithCore].number_hardware_threads*/ + } + area.set_area(area.get_area() * cdb_overhead); +} + +MemManU::MemManU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + itlb(0), + dtlb(0), + exist(exist_) { + if (!exist) + return; + int tag, data; + bool debug = false; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.specific_tag = 1; + // Itlb TLBs are partioned among threads according to Nigara and Nehalem + tag = XML->sys.virtual_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))) + + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + data = XML->sys.physical_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))); + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].itlb.number_entries * + interface_ip.line_sz; //*XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + itlb = new ArrayST(&interface_ip, "ITLB", Core_device, coredynp.opt_local, + coredynp.core_ty); + itlb->area.set_area(itlb->area.get_area() + itlb->local_result.area); + area.set_area(area.get_area() + itlb->local_result.area); + // output_data_csv(itlb.tlb.local_result); + + // dtlb + tag = XML->sys.virtual_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))) + + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + data = XML->sys.physical_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].dtlb.number_entries * + interface_ip.line_sz; //*XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + dtlb = new ArrayST(&interface_ip, "DTLB", Core_device, coredynp.opt_local, + coredynp.core_ty); + dtlb->area.set_area(dtlb->area.get_area() + dtlb->local_result.area); + area.set_area(area.get_area() + dtlb->local_result.area); + // output_data_csv(dtlb.tlb.local_result); +} + +RegFU::RegFU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + IRF(0), + FRF(0), + RFWIN(0), + exist(exist_) { + /* + * processors have separate architectural register files for each thread. + * therefore, the bypass buses need to travel across all the register files. + */ + + if (!exist) + return; + int data; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + //**********************************IRF*************************************** + data = coredynp.int_data_width; + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.cache_sz = coredynp.num_IRF_entry * interface_ip.line_sz; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // this is the transfer port for + // saving/restoring states when exceptions + // happen. + interface_ip.num_rd_ports = 2 * coredynp.peak_issueW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + IRF = new ArrayST(&interface_ip, "Integer Register File", Core_device, + coredynp.opt_local, coredynp.core_ty); + IRF->area.set_area(IRF->area.get_area() + + IRF->local_result.area * coredynp.num_pipelines * + cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + area.set_area(area.get_area() + + IRF->local_result.area * coredynp.num_pipelines * cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + // area.set_area(area.get_area()*cdb_overhead); + // output_data_csv(IRF.RF.local_result); + + //**********************************FRF*************************************** + data = coredynp.fp_data_width; + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.cache_sz = coredynp.num_FRF_entry * interface_ip.line_sz; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // this is the transfer port for + // saving/restoring states when exceptions + // happen. + interface_ip.num_rd_ports = 2 * XML->sys.core[ithCore].issue_width; + interface_ip.num_wr_ports = XML->sys.core[ithCore].issue_width; + interface_ip.num_se_rd_ports = 0; + FRF = new ArrayST(&interface_ip, "Floating point Register File", Core_device, + coredynp.opt_local, coredynp.core_ty); + FRF->area.set_area(FRF->area.get_area() + + FRF->local_result.area * coredynp.num_fp_pipelines * + cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + area.set_area(area.get_area() + + FRF->local_result.area * coredynp.num_fp_pipelines * + cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + // area.set_area(area.get_area()*cdb_overhead); + // output_data_csv(FRF.RF.local_result); + int_regfile_height = IRF->local_result.cache_ht * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1) * + sqrt(cdb_overhead); + fp_regfile_height = FRF->local_result.cache_ht * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1) * + sqrt(cdb_overhead); + // since a EXU is associated with each pipeline, the cdb should not have + // longer length. + if (coredynp.regWindowing) { + //*********************************REG_WIN************************************ + data = coredynp.int_data_width; // ECC, and usually 2 regs are transfered + // together during window shifting.Niagara + // Mega cell + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = int(ceil(data / 8.0)); + interface_ip.cache_sz = XML->sys.core[ithCore].register_windows_size * + IRF->l_ip.cache_sz * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 4.0 / clockRate; + interface_ip.latency = 4.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // this is the transfer port for + // saving/restoring states when exceptions + // happen. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + RFWIN = new ArrayST(&interface_ip, "RegWindow", Core_device, + coredynp.opt_local, coredynp.core_ty); + RFWIN->area.set_area(RFWIN->area.get_area() + + RFWIN->local_result.area * coredynp.num_pipelines); + area.set_area(area.get_area() + + RFWIN->local_result.area * coredynp.num_pipelines); + // output_data_csv(RFWIN.RF.local_result); + } +} + +EXECU::EXECU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, double lsq_height_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + lsq_height(lsq_height_), + coredynp(dyn_p_), + rfu(0), + scheu(0), + fp_u(0), + exeu(0), + mul(0), + int_bypass(0), + intTagBypass(0), + int_mul_bypass(0), + intTag_mul_Bypass(0), + fp_bypass(0), + fpTagBypass(0), + exist(exist_) { + // bool exist_flag = true; + if (!exist) + return; + double fu_height = 0.0; + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + rfu = new RegFU(XML, ithCore, &interface_ip, coredynp); + scheu = new SchedulerU(XML, ithCore, &interface_ip, coredynp); + exeu = new FunctionalUnit(XML, ithCore, &interface_ip, coredynp, ALU); + area.set_area(area.get_area() + exeu->area.get_area() + rfu->area.get_area() + + scheu->area.get_area()); + fu_height = exeu->FU_height; + if (coredynp.num_fpus > 0) { + fp_u = new FunctionalUnit(XML, ithCore, &interface_ip, coredynp, FPU); + area.set_area(area.get_area() + fp_u->area.get_area()); + } + if (coredynp.num_muls > 0) { + mul = new FunctionalUnit(XML, ithCore, &interface_ip, coredynp, MUL); + area.set_area(area.get_area() + mul->area.get_area()); + fu_height += mul->FU_height; + } + /* + * broadcast logic, including int-broadcast; int_tag-broadcast; fp-broadcast; + * fp_tag-broadcast integer by pass has two paths and fp has 3 paths. on the + * same bus there are multiple tri-state drivers and muxes that go to + * different components on the same bus + */ + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 0; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = + 2; // start from semi-global since local wires are already used + interface_ip.wire_os_mat_type = 2; + interface_ip.throughput = 10.0 / clockRate; // Do not care + interface_ip.latency = 10.0 / clockRate; + } + + if (coredynp.core_ty == Inorder) { + int_bypass = new interconnect( + "Int Bypass Data", Core_device, 1, 1, + int(ceil(XML->sys.machine_bits / 32.0) * 32), + rfu->int_regfile_height + exeu->FU_height + lsq_height, &interface_ip, + 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + int_bypass->area.get_area()); + intTagBypass = new interconnect( + "Int Bypass tag", Core_device, 1, 1, coredynp.perThreadState, + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + intTagBypass->area.get_area()); + + if (coredynp.num_muls > 0) { + int_mul_bypass = new interconnect( + "Mul Bypass Data", Core_device, 1, 1, + int(ceil(XML->sys.machine_bits / 32.0) * 32 * 1.5), + rfu->fp_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_mul_bypass->area.get_area()); + intTag_mul_Bypass = new interconnect( + "Mul Bypass tag", Core_device, 1, 1, coredynp.perThreadState, + rfu->fp_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + intTag_mul_Bypass->area.get_area()); + } + + if (coredynp.num_fpus > 0) { + fp_bypass = new interconnect( + "FP Bypass Data", Core_device, 1, 1, + int(ceil(XML->sys.machine_bits / 32.0) * 32 * 1.5), + rfu->fp_regfile_height + fp_u->FU_height, &interface_ip, 3, false, + 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + fp_bypass->area.get_area()); + fpTagBypass = new interconnect( + "FP Bypass tag", Core_device, 1, 1, coredynp.perThreadState, + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->Iw_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + fpTagBypass->area.get_area()); + } + } + else { // OOO + if (coredynp.scheu_ty == PhysicalRegFile) { + /* For physical register based OOO, + * data broadcast interconnects cover across functional units, lsq, inst + * windows and register files, while tag broadcast interconnects also + * cover across ROB + */ + int_bypass = new interconnect( + "Int Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + lsq_height, &interface_ip, + 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_bypass->area.get_area()); + intTagBypass = new interconnect( + "Int Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + intTagBypass->area.get_area()); + + if (coredynp.num_muls > 0) { + int_mul_bypass = new interconnect( + "Mul Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + intTag_mul_Bypass = new interconnect( + "Mul Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_mul_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + intTag_mul_Bypass->area.get_area()); + } + + if (coredynp.num_fpus > 0) { + fp_bypass = new interconnect("FP Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.fp_data_width)), + rfu->fp_regfile_height + fp_u->FU_height, + &interface_ip, 3, false, 1.0, + coredynp.opt_local, coredynp.core_ty); + fpTagBypass = new interconnect( + "FP Bypass tag", Core_device, 1, 1, coredynp.phy_freg_width, + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->fp_Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + fp_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + fpTagBypass->area.get_area()); + } + } + else { + /* + * In RS based processor both data and tag are broadcast together, + * covering functional units, lsq, nst windows, register files, and ROBs + */ + int_bypass = new interconnect( + "Int Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + intTagBypass = new interconnect( + "Int Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + intTagBypass->area.get_area()); + if (coredynp.num_muls > 0) { + int_mul_bypass = new interconnect( + "Mul Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + intTag_mul_Bypass = new interconnect( + "Mul Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_mul_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + intTag_mul_Bypass->area.get_area()); + } + + if (coredynp.num_fpus > 0) { + fp_bypass = new interconnect( + "FP Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.fp_data_width)), + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->fp_Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + fpTagBypass = new interconnect( + "FP Bypass tag", Core_device, 1, 1, coredynp.phy_freg_width, + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->fp_Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + fp_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + fpTagBypass->area.get_area()); + } + } + } + area.set_area(area.get_area() + bypass.area.get_area()); +} + +RENAMINGU::RENAMINGU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + iFRAT(0), + fFRAT(0), + iRRAT(0), + fRRAT(0), + ifreeL(0), + ffreeL(0), + idcl(0), + fdcl(0), + RAHT(0), + exist(exist_) { + /* + * Although renaming logic maybe be used in in-order processors, +* McPAT assumes no renaming logic is used since the performance gain is very +limited and +* the only major inorder processor with renaming logic is Itainium +* that is a VLIW processor and different from current McPAT's model. + * physical register base OOO must have Dual-RAT architecture or equivalent +structure.FRAT:FrontRAT, RRAT:RetireRAT; + * i,f prefix mean int and fp + * RAT for all Renaming logic, random accessible checkpointing is used, but +only update when instruction retires. + * FRAT will be read twice and written once per instruction; + * RRAT will be write once per instruction when committing and reads out all +when context switch + * + * RAM scheme has # ARchi Reg entry with each entry hold phy reg tag, + * CAM scheme has # Phy Reg entry with each entry hold ARchi reg tag, + * + * RAM-based RAT is duplicated/partitioned for each different hardware threads + * CAM-based RAT is shared for all hardware threads + * With SMT, RAT is partitioned and tagged. RAM-based RAT needs to have N +(N-way SMT) sets of entries, with each set for a thread. + * The RAT control logic will determine different sets to use for different +threads. But it does not need extra tag bits in the entries. + * However, CAM-based RAT need extra tag bits to distinguish the architecture +register ids for different threads. + + * + * checkpointing of RAT and RRAT are both for architecture state recovery with +events including mis-speculation; + * Checkpointing is easier to implement in CAM than in RAM based RAT, despite +of the inferior scalabilty of the CAM-based RATs. + * McPAT assumes at least 1 checkpoint for CAM-based RATs, and no more than 4 +checkpoints (based on MIPS designs) for RAM based RATs, + * thus CAM-based RAT does not need RRAT + * Although no Dual-RAT is needed in RS-based OOO processors, since archi +RegFile contains the committed register values, + * a RRAT or GC (not both) will speedup the mis-speculation recovery. Thus, +when RAM-RAT does not have any GC, McPAT assumes the existence of a RRAT. + * + * RAM-base RAT does not need to scan/search all contents during instruction +commit, since the ROB for RAM-based RAT contains the ARF-PRF mapping that is +used for index the RAT entry to be updated. + * + * Both RAM and CAM have same DCL + * + + * + */ + if (!exist) + return; + int tag, data, out_w; + // interface_ip.wire_is_mat_type = 0; + // interface_ip.wire_os_mat_type = 0; + // interface_ip.wt = Global_30; + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + if (coredynp.core_ty == OOO) { + // integer pipeline + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { // FRAT with global checkpointing (GCs) + // please see paper tech report for + // detailed explanation. + data = int(ceil(coredynp.phy_ireg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); // 33; + out_w = int(ceil(coredynp.phy_ireg_width / 8.0)); // bytes + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_IRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FRAT floating point + data = int(ceil(coredynp.phy_freg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_FRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + else if (coredynp.rm_ty == CAMbased) { + // FRAT + tag = coredynp.arch_ireg_width + coredynp.hthread_width; + data = int( + ceil((coredynp.arch_ireg_width + 1 * coredynp.globalCheckpoint) / + 8.0)); // each checkpoint in the CAM-based RAT design needs + // only 1 bit, see "a power-aware hybrid ram-cam + // renaming mechanism for fast recovery" + out_w = int(ceil(coredynp.arch_ireg_width / 8.0)); + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_IRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.decodeW; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FRAT for FP + tag = coredynp.arch_freg_width + coredynp.hthread_width; + data = int( + ceil((coredynp.arch_freg_width + 1 * coredynp.globalCheckpoint) / + 8.0)); // each checkpoint in the CAM-based RAT design needs + // only 1 bit, see "a power-aware hybrid ram-cam + // renaming mechanism for fast recovery" + out_w = int(ceil(coredynp.arch_freg_width / 8.0)); + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_FRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.fp_decodeW; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + + // RRAT is always RAM based, does not have GCs, and is used only for + // record latest non-speculative mapping RRAT is not needed for CAM-based + // RAT (McPAT assumes CAM-based RAT to have at least 1 checkpoint), it is + // not needed for RAM-based RAT with checkpoints McPAT assumes renaming + // unit to have RRAT when there is no checkpoints in FRAT, while MIPS + // R1000 has 4 GCs, according to Intel Netburst Archi, combine GC with + // FRAT is very costly, especially for high issue width and high clock + // rate. + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_IRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_wr_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + iRRAT = new ArrayST(&interface_ip, "Int RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iRRAT->area.set_area(iRRAT->area.get_area() + iRRAT->local_result.area); + area.set_area(area.get_area() + iRRAT->area.get_area()); + + // RRAT for FP + data = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_FRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fRRAT = new ArrayST(&interface_ip, "FP RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fRRAT->area.set_area(fRRAT->area.get_area() + fRRAT->local_result.area); + area.set_area(area.get_area() + fRRAT->area.get_area()); + } + // Freelist of renaming unit always RAM based and needed for RAM-based + // RATs. Although it can be implemented within the CAM-based RAT, Current + // McPAT does not have the free bits in the CAM but use the same external + // free list as a close approximation for CAM RAT. Recycle happens at two + // places: 1)when DCL check there are WAW, the Phy-registers/ROB directly + // recycles into freelist + // 2)When instruction commits the Phyregisters/ROB needed to be recycled. + // therefore num_wr port = decode-1(-1 means at least one phy reg will be + // used for the current renaming group) + commit width + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * coredynp.num_ifreelist_entries; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // TODO + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = + coredynp.decodeW - 1 + XML->sys.core[ithCore].commit_width; + // every cycle, (coredynp.decodeW -1) inst may need to send back it dest + // tags, committW insts needs to update freelist buffers + interface_ip.num_se_rd_ports = 0; + ifreeL = new ArrayST(&interface_ip, "Int Free List", Core_device, + coredynp.opt_local, coredynp.core_ty); + ifreeL->area.set_area(ifreeL->area.get_area() + + ifreeL->local_result.area); + area.set_area(area.get_area() + ifreeL->area.get_area()); + + // freelist for FP + data = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * coredynp.num_ffreelist_entries; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = + coredynp.fp_decodeW - 1 + XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + ffreeL = new ArrayST(&interface_ip, "FP Free List", Core_device, + coredynp.opt_local, coredynp.core_ty); + ffreeL->area.set_area(ffreeL->area.get_area() + + ffreeL->local_result.area); + area.set_area(area.get_area() + ffreeL->area.get_area()); + + idcl = new dep_resource_conflict_check( + &interface_ip, coredynp, + coredynp.phy_ireg_width); // TODO:Separate 2 sections See TR + fdcl = new dep_resource_conflict_check(&interface_ip, coredynp, + coredynp.phy_freg_width); + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + data = int(ceil(coredynp.phy_ireg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.phy_ireg_width / + 8.0)); // GC does not need to be readout + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_IRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->local_result.adjust_area(); + // iFRAT->local_result.power.readOp.dynamic *= + // 1+0.2*0.05;//1+mis-speculation% TODO + // iFRAT->local_result.power.writeOp.dynamic + //*=1+0.2*0.05;//compensate for GC + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FP + data = int(ceil(coredynp.phy_freg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_FRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->local_result.adjust_area(); + // fFRAT->local_result.power.readOp.dynamic *= + // 1+0.2*0.05;//1+mis-speculation% TODO + // fFRAT->local_result.power.writeOp.dynamic + //*=1+0.2*0.05;//compensate for GC + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + else if (coredynp.rm_ty == CAMbased) { + // FRAT + tag = coredynp.arch_ireg_width + coredynp.hthread_width; + data = int(ceil( + (coredynp.arch_ireg_width + 1 * coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.arch_ireg_width / + 8.0)); // GC bits does not need to be sent out + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_IRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.decodeW; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FRAT + tag = coredynp.arch_freg_width + coredynp.hthread_width; + data = int( + ceil((coredynp.arch_freg_width + 1 * coredynp.globalCheckpoint) / + 8.0)); // the address of CAM needed to be sent out + out_w = int(ceil(coredynp.arch_freg_width / 8.0)); + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_FRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = + XML->sys.core[ithCore].decode_width; // 0;TODO; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.fp_decodeW; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + // Although no RRAT for RS based OOO is really needed since the archiRF + // always holds the non-speculative data, having the RRAT or GC (not both) + // can help the recovery of mis-speculations. + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_IRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_wr_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + iRRAT = new ArrayST(&interface_ip, "Int RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iRRAT->area.set_area(iRRAT->area.get_area() + iRRAT->local_result.area); + area.set_area(area.get_area() + iRRAT->area.get_area()); + + // RRAT for FP + data = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_FRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fRRAT = new ArrayST(&interface_ip, "FP RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fRRAT->area.set_area(fRRAT->area.get_area() + fRRAT->local_result.area); + area.set_area(area.get_area() + fRRAT->area.get_area()); + } + + // Freelist of renaming unit of RS based OOO is unifed for both int and fp + // renaming unit since the ROB is unified + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * coredynp.num_ifreelist_entries; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // TODO + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = + coredynp.decodeW - 1 + XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + ifreeL = new ArrayST(&interface_ip, "Unified Free List", Core_device, + coredynp.opt_local, coredynp.core_ty); + // ifreeL->area.set_area(ifreeL->area.get_area()+ + // ifreeL->local_result.area*XML->sys.core[ithCore].number_hardware_threads); + area.set_area(area.get_area() + ifreeL->area.get_area()); + + idcl = new dep_resource_conflict_check( + &interface_ip, coredynp, + coredynp.phy_ireg_width); // TODO:Separate 2 sections See TR + fdcl = new dep_resource_conflict_check(&interface_ip, coredynp, + coredynp.phy_freg_width); + } + } + if (coredynp.core_ty == Inorder && coredynp.issueW > 1) { + /* Dependency check logic will only present when decode(issue) width>1. + * Multiple issue in order processor can do without renaming, but dcl is a + * must. + */ + idcl = new dep_resource_conflict_check( + &interface_ip, coredynp, + coredynp.phy_ireg_width); // TODO:Separate 2 sections See TR + fdcl = new dep_resource_conflict_check(&interface_ip, coredynp, + coredynp.phy_freg_width); + } +} + +Core::Core(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + ifu(0), + lsu(0), + mmu(0), + exu(0), + rnu(0), + corepipe(0), + undiffCore(0), + l2cache(0) { + /* + * initialize, compute and optimize individual components. + */ + + bool exit_flag = true; + + double pipeline_area_per_unit; + // interface_ip.wire_is_mat_type = 2; + // interface_ip.wire_os_mat_type = 2; + // interface_ip.wt =Global_30; + set_core_param(); + + if (XML->sys.Private_L2) { + l2cache = new SharedCache(XML, ithCore, &interface_ip); + } + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + ifu = new InstFetchU(XML, ithCore, &interface_ip, coredynp, exit_flag); + lsu = new LoadStoreU(XML, ithCore, &interface_ip, coredynp, exit_flag); + mmu = new MemManU(XML, ithCore, &interface_ip, coredynp, exit_flag); + exu = new EXECU(XML, ithCore, &interface_ip, lsu->lsq_height, coredynp, + exit_flag); + undiffCore = new UndiffCore(XML, ithCore, &interface_ip, coredynp, exit_flag); + if (coredynp.core_ty == OOO) { + rnu = new RENAMINGU(XML, ithCore, &interface_ip, coredynp); + } + corepipe = new Pipeline(&interface_ip, coredynp); + + if (coredynp.core_ty == OOO) { + pipeline_area_per_unit = + (corepipe->area.get_area() * coredynp.num_pipelines) / 5.0; + if (rnu->exist) { + rnu->area.set_area(rnu->area.get_area() + pipeline_area_per_unit); + } + } + else { + pipeline_area_per_unit = + (corepipe->area.get_area() * coredynp.num_pipelines) / 4.0; + } + + // area.set_area(area.get_area()+ corepipe->area.get_area()); + if (ifu->exist) { + ifu->area.set_area(ifu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + ifu->area.get_area()); + } + if (lsu->exist) { + lsu->area.set_area(lsu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + lsu->area.get_area()); + } + if (exu->exist) { + exu->area.set_area(exu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + exu->area.get_area()); + } + if (mmu->exist) { + mmu->area.set_area(mmu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + mmu->area.get_area()); + } + + if (coredynp.core_ty == OOO) { + if (rnu->exist) { + area.set_area(area.get_area() + rnu->area.get_area()); + } + } + + if (undiffCore->exist) { + area.set_area(area.get_area() + undiffCore->area.get_area()); + } + + if (XML->sys.Private_L2) { + area.set_area(area.get_area() + l2cache->area.get_area()); + } + // //clock power + // clockNetwork.init_wire_external(is_default, &interface_ip); + // clockNetwork.clk_area =area*1.1;//10% of placement overhead. + // rule of thumb clockNetwork.end_wiring_level =5;//toplevel metal + // clockNetwork.start_wiring_level =5;//toplevel metal + // clockNetwork.num_regs = corepipe.tot_stage_vector; + // clockNetwork.optimize_wire(); +} + +void BranchPredictor::computeEnergy(bool is_tdp) { + if (!exist) + return; + double r_access; + double w_access; + if (is_tdp) { + r_access = coredynp.predictionW * coredynp.BR_duty_cycle; + w_access = 0 * coredynp.BR_duty_cycle; + globalBPT->stats_t.readAc.access = r_access; + globalBPT->stats_t.writeAc.access = w_access; + globalBPT->tdp_stats = globalBPT->stats_t; + + L1_localBPT->stats_t.readAc.access = r_access; + L1_localBPT->stats_t.writeAc.access = w_access; + L1_localBPT->tdp_stats = L1_localBPT->stats_t; + + L2_localBPT->stats_t.readAc.access = r_access; + L2_localBPT->stats_t.writeAc.access = w_access; + L2_localBPT->tdp_stats = L2_localBPT->stats_t; + + chooser->stats_t.readAc.access = r_access; + chooser->stats_t.writeAc.access = w_access; + chooser->tdp_stats = chooser->stats_t; + + RAS->stats_t.readAc.access = r_access; + RAS->stats_t.writeAc.access = w_access; + RAS->tdp_stats = RAS->stats_t; + } + else { + // The resolution of BPT accesses is coarse, but this is + // because most simulators cannot track finer grained details + r_access = XML->sys.core[ithCore].branch_instructions; + w_access = + XML->sys.core[ithCore].branch_mispredictions + + 0.1 * XML->sys.core[ithCore] + .branch_instructions; // 10% of BR will flip internal bits//0 + globalBPT->stats_t.readAc.access = r_access; + globalBPT->stats_t.writeAc.access = w_access; + globalBPT->rtp_stats = globalBPT->stats_t; + + L1_localBPT->stats_t.readAc.access = r_access; + L1_localBPT->stats_t.writeAc.access = w_access; + L1_localBPT->rtp_stats = L1_localBPT->stats_t; + + L2_localBPT->stats_t.readAc.access = r_access; + L2_localBPT->stats_t.writeAc.access = w_access; + L2_localBPT->rtp_stats = L2_localBPT->stats_t; + + chooser->stats_t.readAc.access = r_access; + chooser->stats_t.writeAc.access = w_access; + chooser->rtp_stats = chooser->stats_t; + + RAS->stats_t.readAc.access = XML->sys.core[ithCore].function_calls; + RAS->stats_t.writeAc.access = XML->sys.core[ithCore].function_calls; + RAS->rtp_stats = RAS->stats_t; + } + + globalBPT->power_t.reset(); + L1_localBPT->power_t.reset(); + L2_localBPT->power_t.reset(); + chooser->power_t.reset(); + RAS->power_t.reset(); + + globalBPT->power_t.readOp.dynamic += + globalBPT->local_result.power.readOp.dynamic * + globalBPT->stats_t.readAc.access + + globalBPT->stats_t.writeAc.access * + globalBPT->local_result.power.writeOp.dynamic; + L1_localBPT->power_t.readOp.dynamic += + L1_localBPT->local_result.power.readOp.dynamic * + L1_localBPT->stats_t.readAc.access + + L1_localBPT->stats_t.writeAc.access * + L1_localBPT->local_result.power.writeOp.dynamic; + + L2_localBPT->power_t.readOp.dynamic += + L2_localBPT->local_result.power.readOp.dynamic * + L2_localBPT->stats_t.readAc.access + + L2_localBPT->stats_t.writeAc.access * + L2_localBPT->local_result.power.writeOp.dynamic; + + chooser->power_t.readOp.dynamic += + chooser->local_result.power.readOp.dynamic * + chooser->stats_t.readAc.access + + chooser->stats_t.writeAc.access * + chooser->local_result.power.writeOp.dynamic; + RAS->power_t.readOp.dynamic += + RAS->local_result.power.readOp.dynamic * RAS->stats_t.readAc.access + + RAS->stats_t.writeAc.access * RAS->local_result.power.writeOp.dynamic; + + if (is_tdp) { + globalBPT->power = + globalBPT->power_t + globalBPT->local_result.power * pppm_lkg; + L1_localBPT->power = + L1_localBPT->power_t + L1_localBPT->local_result.power * pppm_lkg; + L2_localBPT->power = + L2_localBPT->power_t + L2_localBPT->local_result.power * pppm_lkg; + chooser->power = chooser->power_t + chooser->local_result.power * pppm_lkg; + RAS->power = + RAS->power_t + RAS->local_result.power * coredynp.pppm_lkg_multhread; + + power = power + globalBPT->power + L1_localBPT->power + L2_localBPT->power + + chooser->power + RAS->power; + } + else { + globalBPT->rt_power = + globalBPT->power_t + globalBPT->local_result.power * pppm_lkg; + L1_localBPT->rt_power = + L1_localBPT->power_t + L1_localBPT->local_result.power * pppm_lkg; + L2_localBPT->rt_power = + L2_localBPT->power_t + L2_localBPT->local_result.power * pppm_lkg; + chooser->rt_power = + chooser->power_t + chooser->local_result.power * pppm_lkg; + RAS->rt_power = + RAS->power_t + RAS->local_result.power * coredynp.pppm_lkg_multhread; + rt_power = rt_power + globalBPT->rt_power + L1_localBPT->rt_power + + L2_localBPT->rt_power + chooser->rt_power + RAS->rt_power; + } +} + +void BranchPredictor::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + if (is_tdp) { + cout << indent_str << "Global Predictor:" << endl; + cout << indent_str_next << "Area = " << globalBPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << globalBPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? globalBPT->power.readOp.longer_channel_leakage + : globalBPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? globalBPT->power.readOp + .power_gated_with_long_channel_leakage + : globalBPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << globalBPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << globalBPT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "Local Predictor:" << endl; + cout << indent_str << "L1_Local Predictor:" << endl; + cout << indent_str_next << "Area = " << L1_localBPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << L1_localBPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? L1_localBPT->power.readOp.longer_channel_leakage + : L1_localBPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? L1_localBPT->power.readOp + .power_gated_with_long_channel_leakage + : L1_localBPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << L1_localBPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << L1_localBPT->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + cout << indent_str << "L2_Local Predictor:" << endl; + cout << indent_str_next << "Area = " << L2_localBPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << L2_localBPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? L2_localBPT->power.readOp.longer_channel_leakage + : L2_localBPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? L2_localBPT->power.readOp + .power_gated_with_long_channel_leakage + : L2_localBPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << L2_localBPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << L2_localBPT->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + + cout << indent_str << "Chooser:" << endl; + cout << indent_str_next << "Area = " << chooser->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << chooser->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? chooser->power.readOp.longer_channel_leakage + : chooser->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? chooser->power.readOp.power_gated_with_long_channel_leakage + : chooser->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << chooser->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << chooser->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "RAS:" << endl; + cout << indent_str_next << "Area = " << RAS->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << RAS->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? RAS->power.readOp.longer_channel_leakage + : RAS->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? RAS->power.readOp.power_gated_with_long_channel_leakage + : RAS->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << RAS->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << RAS->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + else { + // cout << indent_str_next << "Global Predictor Peak Dynamic = " + //<< globalBPT->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Global Predictor Subthreshold + // Leakage = " << globalBPT->rt_power.readOp.leakage <<" W" << endl; cout + // << + // indent_str_next << "Global Predictor Gate Leakage = " << + // globalBPT->rt_power.readOp.gate_leakage << " W" << endl; + // cout + // << indent_str_next << "Local Predictor Peak Dynamic = " << + // L1_localBPT->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Local Predictor Subthreshold + // Leakage + //= + //" + //<< L1_localBPT->rt_power.readOp.leakage << " W" << endl; + // cout << indent_str_next << "Local Predictor Gate Leakage = " + //<< L1_localBPT->rt_power.readOp.gate_leakage << " W" << endl; + // cout << indent_str_next << "Chooser Peak Dynamic = " << + // chooser->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Chooser Subthreshold Leakage = " + //<< chooser->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Chooser Gate Leakage = " << + // chooser->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "RAS Peak Dynamic = " << + // RAS->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "RAS Subthreshold Leakage = " << + // RAS->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "RAS Gate Leakage = " << + // RAS->rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void InstFetchU::computeEnergy(bool is_tdp) { + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + icache.caches->stats_t.readAc.access = + icache.caches->l_ip.num_rw_ports * coredynp.IFU_duty_cycle; + icache.caches->stats_t.readAc.miss = 0; + icache.caches->stats_t.readAc.hit = icache.caches->stats_t.readAc.access - + icache.caches->stats_t.readAc.miss; + icache.caches->tdp_stats = icache.caches->stats_t; + + icache.missb->stats_t.readAc.access = icache.missb->stats_t.readAc.hit = + icache.missb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.missb->stats_t.writeAc.access = icache.missb->stats_t.writeAc.hit = + icache.missb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.missb->tdp_stats = icache.missb->stats_t; + + icache.ifb->stats_t.readAc.access = icache.ifb->stats_t.readAc.hit = + icache.ifb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.ifb->stats_t.writeAc.access = icache.ifb->stats_t.writeAc.hit = + icache.ifb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.ifb->tdp_stats = icache.ifb->stats_t; + + icache.prefetchb->stats_t.readAc.access = + icache.prefetchb->stats_t.readAc.hit = + icache.prefetchb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.prefetchb->stats_t.writeAc.access = icache.ifb->stats_t.writeAc.hit = + icache.ifb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.prefetchb->tdp_stats = icache.prefetchb->stats_t; + + IB->stats_t.readAc.access = IB->stats_t.writeAc.access = + XML->sys.core[ithCore].peak_issue_width; + IB->tdp_stats = IB->stats_t; + + if (coredynp.predictionW > 0) { + BTB->stats_t.readAc.access = + coredynp.predictionW; // XML->sys.core[ithCore].BTB.read_accesses; + BTB->stats_t.writeAc.access = + 0; // XML->sys.core[ithCore].BTB.write_accesses; + } + + ID_inst->stats_t.readAc.access = coredynp.decodeW; + ID_operand->stats_t.readAc.access = coredynp.decodeW; + ID_misc->stats_t.readAc.access = coredynp.decodeW; + ID_inst->tdp_stats = ID_inst->stats_t; + ID_operand->tdp_stats = ID_operand->stats_t; + ID_misc->tdp_stats = ID_misc->stats_t; + } + else { + // init stats for Runtime Dynamic (RTP) + icache.caches->stats_t.readAc.access = + XML->sys.core[ithCore].icache.read_accesses; + icache.caches->stats_t.readAc.miss = + XML->sys.core[ithCore].icache.read_misses; + icache.caches->stats_t.readAc.hit = icache.caches->stats_t.readAc.access - + icache.caches->stats_t.readAc.miss; + icache.caches->rtp_stats = icache.caches->stats_t; + + icache.missb->stats_t.readAc.access = icache.caches->stats_t.readAc.miss; + icache.missb->stats_t.writeAc.access = icache.caches->stats_t.readAc.miss; + icache.missb->rtp_stats = icache.missb->stats_t; + + icache.ifb->stats_t.readAc.access = icache.caches->stats_t.readAc.miss; + icache.ifb->stats_t.writeAc.access = icache.caches->stats_t.readAc.miss; + icache.ifb->rtp_stats = icache.ifb->stats_t; + + icache.prefetchb->stats_t.readAc.access = + icache.caches->stats_t.readAc.miss; + icache.prefetchb->stats_t.writeAc.access = + icache.caches->stats_t.readAc.miss; + icache.prefetchb->rtp_stats = icache.prefetchb->stats_t; + + IB->stats_t.readAc.access = IB->stats_t.writeAc.access = + XML->sys.core[ithCore].total_instructions; + IB->rtp_stats = IB->stats_t; + + if (coredynp.predictionW > 0) { + BTB->stats_t.readAc.access = + XML->sys.core[ithCore] + .BTB + .read_accesses; // XML->sys.core[ithCore].branch_instructions; + BTB->stats_t.writeAc.access = + XML->sys.core[ithCore] + .BTB + .write_accesses; // XML->sys.core[ithCore].branch_mispredictions; + BTB->rtp_stats = BTB->stats_t; + } + + ID_inst->stats_t.readAc.access = XML->sys.core[ithCore].total_instructions; + ID_operand->stats_t.readAc.access = + XML->sys.core[ithCore].total_instructions; + ID_misc->stats_t.readAc.access = XML->sys.core[ithCore].total_instructions; + ID_inst->rtp_stats = ID_inst->stats_t; + ID_operand->rtp_stats = ID_operand->stats_t; + ID_misc->rtp_stats = ID_misc->stats_t; + } + + icache.power_t.reset(); + IB->power_t.reset(); + // ID_inst->power_t.reset(); + // ID_operand->power_t.reset(); + // ID_misc->power_t.reset(); + if (coredynp.predictionW > 0) { + BTB->power_t.reset(); + } + + icache.power_t.readOp.dynamic += + (icache.caches->stats_t.readAc.hit * + icache.caches->local_result.power.readOp.dynamic + + // icache.caches->stats_t.readAc.miss*icache.caches->local_result.tag_array2->power.readOp.dynamic+ + icache.caches->stats_t.readAc.miss * + icache.caches->local_result.power.readOp + .dynamic + // assume tag data accessed in parallel + icache.caches->stats_t.readAc.miss * + icache.caches->local_result.power.writeOp + .dynamic); // read miss in Icache cause a write to Icache + icache.power_t.readOp.dynamic += + icache.missb->stats_t.readAc.access * + icache.missb->local_result.power.searchOp.dynamic + + icache.missb->stats_t.writeAc.access * + icache.missb->local_result.power.writeOp + .dynamic; // each access to missb involves a CAM and a write + icache.power_t.readOp.dynamic += + icache.ifb->stats_t.readAc.access * + icache.ifb->local_result.power.searchOp.dynamic + + icache.ifb->stats_t.writeAc.access * + icache.ifb->local_result.power.writeOp.dynamic; + icache.power_t.readOp.dynamic += + icache.prefetchb->stats_t.readAc.access * + icache.prefetchb->local_result.power.searchOp.dynamic + + icache.prefetchb->stats_t.writeAc.access * + icache.prefetchb->local_result.power.writeOp.dynamic; + + IB->power_t.readOp.dynamic += + IB->local_result.power.readOp.dynamic * IB->stats_t.readAc.access + + IB->stats_t.writeAc.access * IB->local_result.power.writeOp.dynamic; + + if (coredynp.predictionW > 0) { + BTB->power_t.readOp.dynamic += + BTB->local_result.power.readOp.dynamic * BTB->stats_t.readAc.access + + BTB->stats_t.writeAc.access * BTB->local_result.power.writeOp.dynamic; + + BPT->computeEnergy(is_tdp); + } + + if (is_tdp) { + // icache.power = icache.power_t + + // (icache.caches->local_result.power)*pppm_lkg + + // (icache.missb->local_result.power + + // icache.ifb->local_result.power + + // icache.prefetchb->local_result.power)*pppm_Isub; + icache.power = icache.power_t + (icache.caches->local_result.power + + icache.missb->local_result.power + + icache.ifb->local_result.power + + icache.prefetchb->local_result.power) * + pppm_lkg; + + IB->power = IB->power_t + IB->local_result.power * pppm_lkg; + power = power + icache.power + IB->power; + if (coredynp.predictionW > 0) { + BTB->power = BTB->power_t + BTB->local_result.power * pppm_lkg; + power = power + BTB->power + BPT->power; + } + + ID_inst->power_t.readOp.dynamic = ID_inst->power.readOp.dynamic; + ID_operand->power_t.readOp.dynamic = ID_operand->power.readOp.dynamic; + ID_misc->power_t.readOp.dynamic = ID_misc->power.readOp.dynamic; + + ID_inst->power.readOp.dynamic *= ID_inst->tdp_stats.readAc.access; + ID_operand->power.readOp.dynamic *= ID_operand->tdp_stats.readAc.access; + ID_misc->power.readOp.dynamic *= ID_misc->tdp_stats.readAc.access; + + power = power + (ID_inst->power + ID_operand->power + ID_misc->power); + } + else { + // icache.rt_power = icache.power_t + + // (icache.caches->local_result.power)*pppm_lkg + + // (icache.missb->local_result.power + + // icache.ifb->local_result.power + + // icache.prefetchb->local_result.power)*pppm_Isub; + + icache.rt_power = icache.power_t + (icache.caches->local_result.power + + icache.missb->local_result.power + + icache.ifb->local_result.power + + icache.prefetchb->local_result.power) * + pppm_lkg; + + IB->rt_power = IB->power_t + IB->local_result.power * pppm_lkg; + rt_power = rt_power + icache.rt_power + IB->rt_power; + if (coredynp.predictionW > 0) { + BTB->rt_power = BTB->power_t + BTB->local_result.power * pppm_lkg; + rt_power = rt_power + BTB->rt_power + BPT->rt_power; + } + + ID_inst->rt_power.readOp.dynamic = + ID_inst->power_t.readOp.dynamic * ID_inst->rtp_stats.readAc.access; + ID_operand->rt_power.readOp.dynamic = ID_operand->power_t.readOp.dynamic * + ID_operand->rtp_stats.readAc.access; + ID_misc->rt_power.readOp.dynamic = + ID_misc->power_t.readOp.dynamic * ID_misc->rtp_stats.readAc.access; + + rt_power = rt_power + + (ID_inst->rt_power + ID_operand->rt_power + ID_misc->rt_power); + } +} + +void InstFetchU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Instruction Cache:" << endl; + cout << indent_str_next << "Area = " << icache.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << icache.power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? icache.power.readOp.longer_channel_leakage + : icache.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? icache.power.readOp.power_gated_with_long_channel_leakage + : icache.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << icache.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << icache.rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (coredynp.predictionW > 0) { + cout << indent_str << "Branch Target Buffer:" << endl; + cout << indent_str_next << "Area = " << BTB->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << BTB->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? BTB->power.readOp.longer_channel_leakage + : BTB->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? BTB->power.readOp.power_gated_with_long_channel_leakage + : BTB->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << BTB->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << BTB->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (BPT->exist) { + cout << indent_str << "Branch Predictor:" << endl; + cout << indent_str_next << "Area = " << BPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << BPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? BPT->power.readOp.longer_channel_leakage + : BPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? BPT->power.readOp.power_gated_with_long_channel_leakage + : BPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << BPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << BPT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 3) { + BPT->displayEnergy(indent + 4, plevel, is_tdp); + } + } + } + cout << indent_str << "Instruction Buffer:" << endl; + cout << indent_str_next << "Area = " << IB->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << IB->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? IB->power.readOp.longer_channel_leakage + : IB->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? IB->power.readOp.power_gated_with_long_channel_leakage + : IB->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << IB->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << IB->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + cout << indent_str << "Instruction Decoder:" << endl; + cout << indent_str_next << "Area = " + << (ID_inst->area.get_area() + ID_operand->area.get_area() + + ID_misc->area.get_area()) * + coredynp.decodeW * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << (ID_inst->power.readOp.dynamic + ID_operand->power.readOp.dynamic + + ID_misc->power.readOp.dynamic) * + clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? (ID_inst->power.readOp.longer_channel_leakage + + ID_operand->power.readOp.longer_channel_leakage + + ID_misc->power.readOp.longer_channel_leakage) + : (ID_inst->power.readOp.leakage + + ID_operand->power.readOp.leakage + + ID_misc->power.readOp.leakage)) + << " W" << endl; + + // double tot_leakage = + // (ID_inst->power.readOp.leakage + ID_operand->power.readOp.leakage + + // ID_misc->power.readOp.leakage); + // double tot_leakage_longchannel = + // (ID_inst->power.readOp.longer_channel_leakage + + // ID_operand->power.readOp.longer_channel_leakage + + // ID_misc->power.readOp.longer_channel_leakage); + double tot_leakage_pg = (ID_inst->power.readOp.power_gated_leakage + + ID_operand->power.readOp.power_gated_leakage + + ID_misc->power.readOp.power_gated_leakage); + double tot_leakage_pg_with_long_channel = + (ID_inst->power.readOp.power_gated_with_long_channel_leakage + + ID_operand->power.readOp.power_gated_with_long_channel_leakage + + ID_misc->power.readOp.power_gated_with_long_channel_leakage); + + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? tot_leakage_pg_with_long_channel : tot_leakage_pg) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " + << (ID_inst->power.readOp.gate_leakage + + ID_operand->power.readOp.gate_leakage + + ID_misc->power.readOp.gate_leakage) + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << (ID_inst->rt_power.readOp.dynamic + + ID_operand->rt_power.readOp.dynamic + + ID_misc->rt_power.readOp.dynamic) / + executionTime + << " W" << endl; + cout << endl; + } + else { + // cout << indent_str_next << "Instruction Cache Peak Dynamic = + //" + //<< icache.rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Instruction Cache Subthreshold + // Leakage + //= " << icache.rt_power.readOp.leakage <<" W" << endl; cout << + // indent_str_next << "Instruction Cache Gate Leakage = " << + // icache.rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Instruction Buffer Peak Dynamic = " << + // IB->rt_power.readOp.dynamic*clockRate << " W" << endl; cout << + // indent_str_next << "Instruction Buffer Subthreshold Leakage = " << + // IB->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Instruction Buffer Gate Leakage = " << + // IB->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Branch Target Buffer Peak Dynamic = " << + // BTB->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Branch Target Buffer Subthreshold Leakage = " + // << BTB->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Branch Target Buffer Gate Leakage = " << + // BTB->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Branch Predictor Peak Dynamic = " << + // BPT->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Branch Predictor Subthreshold Leakage = " << + // BPT->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Branch Predictor Gate Leakage = " << + // BPT->rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void RENAMINGU::computeEnergy(bool is_tdp) { + if (!exist) + return; + double pppm_t[4] = {1, 1, 1, 1}; + if (is_tdp) { // init stats for Peak + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_rd_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_rd_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_search_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_search_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = iRRAT->l_ip.num_rd_ports; + iRRAT->stats_t.writeAc.access = iRRAT->l_ip.num_wr_ports; + iRRAT->tdp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = fRRAT->l_ip.num_rd_ports; + fRRAT->stats_t.writeAc.access = fRRAT->l_ip.num_wr_ports; + fRRAT->tdp_stats = fRRAT->stats_t; + } + ifreeL->stats_t.readAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_rd_ports;; + ifreeL->stats_t.writeAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_wr_ports; + ifreeL->tdp_stats = ifreeL->stats_t; + + ffreeL->stats_t.readAc.access = + coredynp.decodeW; // ffreeL->l_ip.num_rd_ports; + ffreeL->stats_t.writeAc.access = + coredynp.decodeW; // ffreeL->l_ip.num_wr_ports; + ffreeL->tdp_stats = ffreeL->stats_t; + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_rd_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_rd_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_search_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_search_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = iRRAT->l_ip.num_rd_ports; + iRRAT->stats_t.writeAc.access = iRRAT->l_ip.num_wr_ports; + iRRAT->tdp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = fRRAT->l_ip.num_rd_ports; + fRRAT->stats_t.writeAc.access = fRRAT->l_ip.num_wr_ports; + fRRAT->tdp_stats = fRRAT->stats_t; + } + // Unified free list for both int and fp + ifreeL->stats_t.readAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_rd_ports; + ifreeL->stats_t.writeAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_wr_ports; + ifreeL->tdp_stats = ifreeL->stats_t; + } + idcl->stats_t.readAc.access = coredynp.decodeW; + fdcl->stats_t.readAc.access = coredynp.decodeW; + idcl->tdp_stats = idcl->stats_t; + fdcl->tdp_stats = fdcl->stats_t; + } + else { + if (coredynp.issueW > 1) { + idcl->stats_t.readAc.access = coredynp.decodeW; + fdcl->stats_t.readAc.access = coredynp.decodeW; + idcl->tdp_stats = idcl->stats_t; + fdcl->tdp_stats = fdcl->stats_t; + } + } + } + else { // init stats for Runtime Dynamic (RTP) + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fFRAT->rtp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fFRAT->rtp_stats = fFRAT->stats_t; + } + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].rename_writes; // Hack, should be (context + // switch + branch + // mispredictions)*16 + iRRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iRRAT->rtp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].fp_rename_writes; // Hack, should be + // (context switch + + // branch + // mispredictions)*16 + fRRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fRRAT->rtp_stats = fRRAT->stats_t; + } + ifreeL->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + ifreeL->stats_t.writeAc.access = + 2 * XML->sys.core[ithCore].rename_writes; + ifreeL->rtp_stats = ifreeL->stats_t; + + ffreeL->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + ffreeL->stats_t.writeAc.access = + 2 * XML->sys.core[ithCore].fp_rename_writes; + ffreeL->rtp_stats = ffreeL->stats_t; + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + // iFRAT->stats_t.searchAc.access = + // XML->sys.core[ithCore].committed_int_instructions;//hack: not all + // committed instructions use regs. + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + // fFRAT->stats_t.searchAc.access = + // XML->sys.core[ithCore].committed_fp_instructions; + fFRAT->rtp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fFRAT->rtp_stats = fFRAT->stats_t; + } + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].rename_writes; // Hack, should be (context + // switch + branch + // mispredictions)*16 + iRRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iRRAT->rtp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].fp_rename_writes; // Hack, should be + // (context switch + + // branch + // mispredictions)*16 + fRRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fRRAT->rtp_stats = fRRAT->stats_t; + } + // Unified free list for both int and fp since the ROB act as physcial + // registers + ifreeL->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads + + XML->sys.core[ithCore].fp_rename_reads; + ifreeL->stats_t.writeAc.access = + 2 * (XML->sys.core[ithCore].rename_writes + + XML->sys.core[ithCore].fp_rename_writes); // HACK: 2-> since + // some of renaming + // in the same group + // are terminated + // early + ifreeL->rtp_stats = ifreeL->stats_t; + } + idcl->stats_t.readAc.access = 3 * coredynp.decodeW * coredynp.decodeW * + XML->sys.core[ithCore].rename_reads; + fdcl->stats_t.readAc.access = 3 * coredynp.fp_issueW * + coredynp.fp_issueW * + XML->sys.core[ithCore].fp_rename_writes; + idcl->rtp_stats = idcl->stats_t; + fdcl->rtp_stats = fdcl->stats_t; + } + else { + if (coredynp.issueW > 1) { + idcl->stats_t.readAc.access = + 2 * XML->sys.core[ithCore].int_instructions; + fdcl->stats_t.readAc.access = XML->sys.core[ithCore].fp_instructions; + idcl->rtp_stats = idcl->stats_t; + fdcl->rtp_stats = fdcl->stats_t; + } + } + } + /* Compute engine */ + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.readOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.readOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.searchOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.searchOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power_t.reset(); + fRRAT->power_t.reset(); + + iRRAT->power_t.readOp.dynamic += + (iRRAT->stats_t.readAc.access * + iRRAT->local_result.power.readOp.dynamic + + iRRAT->stats_t.writeAc.access * + iRRAT->local_result.power.writeOp.dynamic); + fRRAT->power_t.readOp.dynamic += + (fRRAT->stats_t.readAc.access * + fRRAT->local_result.power.readOp.dynamic + + fRRAT->stats_t.writeAc.access * + fRRAT->local_result.power.writeOp.dynamic); + } + + ifreeL->power_t.reset(); + ffreeL->power_t.reset(); + ifreeL->power_t.readOp.dynamic += + (ifreeL->stats_t.readAc.access * + ifreeL->local_result.power.readOp.dynamic + + ifreeL->stats_t.writeAc.access * + ifreeL->local_result.power.writeOp.dynamic); + ffreeL->power_t.readOp.dynamic += + (ffreeL->stats_t.readAc.access * + ffreeL->local_result.power.readOp.dynamic + + ffreeL->stats_t.writeAc.access * + ffreeL->local_result.power.writeOp.dynamic); + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.readOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.readOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.searchOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.searchOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power_t.reset(); + fRRAT->power_t.reset(); + + iRRAT->power_t.readOp.dynamic += + (iRRAT->stats_t.readAc.access * + iRRAT->local_result.power.readOp.dynamic + + iRRAT->stats_t.writeAc.access * + iRRAT->local_result.power.writeOp.dynamic); + fRRAT->power_t.readOp.dynamic += + (fRRAT->stats_t.readAc.access * + fRRAT->local_result.power.readOp.dynamic + + fRRAT->stats_t.writeAc.access * + fRRAT->local_result.power.writeOp.dynamic); + } + + ifreeL->power_t.reset(); + ifreeL->power_t.readOp.dynamic += + (ifreeL->stats_t.readAc.access * + ifreeL->local_result.power.readOp.dynamic + + ifreeL->stats_t.writeAc.access * + ifreeL->local_result.power.writeOp.dynamic); + } + } + else { + if (coredynp.issueW > 1) { + idcl->power_t.reset(); + fdcl->power_t.reset(); + set_pppm(pppm_t, idcl->stats_t.readAc.access, coredynp.num_hthreads, + coredynp.num_hthreads, idcl->stats_t.readAc.access); + idcl->power_t = idcl->power * pppm_t; + set_pppm(pppm_t, fdcl->stats_t.readAc.access, coredynp.num_hthreads, + coredynp.num_hthreads, idcl->stats_t.readAc.access); + fdcl->power_t = fdcl->power * pppm_t; + } + } + + // assign value to tpd and rtp + if (is_tdp) { + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + iFRAT->power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + ifreeL->power = ifreeL->power_t + ifreeL->local_result.power; + ffreeL->power = ffreeL->power_t + ffreeL->local_result.power; + power = power + + (iFRAT->power + fFRAT->power) + //+ (iRRAT->power + fRRAT->power) + + (ifreeL->power + ffreeL->power); + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->power = fRRAT->power_t + fRRAT->local_result.power; + power = power + (iRRAT->power + fRRAT->power); + } + } + else if (coredynp.scheu_ty == ReservationStation) { + iFRAT->power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + ifreeL->power = ifreeL->power_t + ifreeL->local_result.power; + power = power + (iFRAT->power + fFRAT->power) + ifreeL->power; + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->power = fRRAT->power_t + fRRAT->local_result.power; + power = power + (iRRAT->power + fRRAT->power); + } + } + } + else { + power = power + idcl->power_t + fdcl->power_t; + } + } + else { + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + iFRAT->rt_power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->rt_power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + + ifreeL->rt_power = ifreeL->power_t + ifreeL->local_result.power; + ffreeL->rt_power = ffreeL->power_t + ffreeL->local_result.power; + rt_power = rt_power + + (iFRAT->rt_power + fFRAT->rt_power) + // + (iRRAT->rt_power + + // fRRAT->rt_power) + + (ifreeL->rt_power + ffreeL->rt_power); + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->rt_power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->rt_power = fRRAT->power_t + fRRAT->local_result.power; + rt_power = rt_power + (iRRAT->rt_power + fRRAT->rt_power); + } + } + else if (coredynp.scheu_ty == ReservationStation) { + iFRAT->rt_power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->rt_power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + ifreeL->rt_power = ifreeL->power_t + ifreeL->local_result.power; + rt_power = + rt_power + (iFRAT->rt_power + fFRAT->rt_power) + ifreeL->rt_power; + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->rt_power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->rt_power = fRRAT->power_t + fRRAT->local_result.power; + rt_power = rt_power + (iRRAT->rt_power + fRRAT->rt_power); + } + } + } + else { + rt_power = rt_power + idcl->power_t + fdcl->power_t; + } + } +} + +void RENAMINGU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + if (coredynp.core_ty == OOO) { + cout << indent_str << "Int Front End RAT with " + << coredynp.globalCheckpoint << " internal checkpoints:" << endl; + cout << indent_str_next << "Area = " << iFRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << iFRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? iFRAT->power.readOp.longer_channel_leakage + : iFRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? iFRAT->power.readOp.power_gated_with_long_channel_leakage + : iFRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << iFRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << iFRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "FP Front End RAT with " + << coredynp.globalCheckpoint << " internal checkpoints:" << endl; + cout << indent_str_next << "Area = " << fFRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << fFRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? fFRAT->power.readOp.longer_channel_leakage + : fFRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? fFRAT->power.readOp.power_gated_with_long_channel_leakage + : fFRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fFRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fFRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "Free List:" << endl; + cout << indent_str_next << "Area = " << ifreeL->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ifreeL->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ifreeL->power.readOp.longer_channel_leakage + : ifreeL->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout + << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? ifreeL->power.readOp.power_gated_with_long_channel_leakage + : ifreeL->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ifreeL->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ifreeL->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + cout << indent_str << "Int Retire RAT: " << endl; + cout << indent_str_next << "Area = " << iRRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << iRRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? iRRAT->power.readOp.longer_channel_leakage + : iRRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? iRRAT->power.readOp + .power_gated_with_long_channel_leakage + : iRRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << iRRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << iRRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "FP Retire RAT:" << endl; + cout << indent_str_next << "Area = " << fRRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << fRRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? fRRAT->power.readOp.longer_channel_leakage + : fRRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? fRRAT->power.readOp + .power_gated_with_long_channel_leakage + : fRRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fRRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fRRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + if (coredynp.scheu_ty == PhysicalRegFile) { + cout << indent_str << "FP Free List:" << endl; + cout << indent_str_next << "Area = " << ffreeL->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ffreeL->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ffreeL->power.readOp.longer_channel_leakage + : ffreeL->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? ffreeL->power.readOp + .power_gated_with_long_channel_leakage + : ffreeL->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ffreeL->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ffreeL->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << indent_str << "Int DCL:" << endl; + cout << indent_str_next + << "Peak Dynamic = " << idcl->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? idcl->power.readOp.longer_channel_leakage + : idcl->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? idcl->power.readOp.power_gated_with_long_channel_leakage + : idcl->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << idcl->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << idcl->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << indent_str << "FP DCL:" << endl; + cout << indent_str_next + << "Peak Dynamic = " << fdcl->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? fdcl->power.readOp.longer_channel_leakage + : fdcl->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? fdcl->power.readOp.power_gated_with_long_channel_leakage + : fdcl->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fdcl->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fdcl->rt_power.readOp.dynamic / executionTime << " W" << endl; + } + } + else { + if (coredynp.core_ty == OOO) { + cout << indent_str_next << "Int Front End RAT Peak Dynamic = " + << iFRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Int Front End RAT Subthreshold Leakage = " + << iFRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Int Front End RAT Gate Leakage = " + << iFRAT->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "FP Front End RAT Peak Dynamic = " + << fFRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP Front End RAT Subthreshold Leakage = " + << fFRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Front End RAT Gate Leakage = " + << fFRAT->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Free List Peak Dynamic = " + << ifreeL->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Free List Subthreshold Leakage = " + << ifreeL->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Free List Gate Leakage = " + << fFRAT->rt_power.readOp.gate_leakage << " W" << endl; + if (coredynp.scheu_ty == PhysicalRegFile) { + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + cout << indent_str_next << "Int Retire RAT Peak Dynamic = " + << iRRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Int Retire RAT Subthreshold Leakage = " + << iRRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Int Retire RAT Gate Leakage = " + << iRRAT->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "FP Retire RAT Peak Dynamic = " + << fRRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP Retire RAT Subthreshold Leakage = " + << fRRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Retire RAT Gate Leakage = " + << fRRAT->rt_power.readOp.gate_leakage << " W" << endl; + } + cout << indent_str_next << "FP Free List Peak Dynamic = " + << ffreeL->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP Free List Subthreshold Leakage = " + << ffreeL->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Free List Gate Leakage = " + << fFRAT->rt_power.readOp.gate_leakage << " W" << endl; + } + } + else { + cout << indent_str_next << "Int DCL Peak Dynamic = " + << idcl->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Int DCL Subthreshold Leakage = " + << idcl->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "Int DCL Gate Leakage = " << idcl->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "FP DCL Peak Dynamic = " + << fdcl->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP DCL Subthreshold Leakage = " + << fdcl->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "FP DCL Gate Leakage = " << fdcl->rt_power.readOp.gate_leakage + << " W" << endl; + } + } +} + +void SchedulerU::computeEnergy(bool is_tdp) { + if (!exist) + return; + double ROB_duty_cycle; + // ROB_duty_cycle = ((coredynp.ALU_duty_cycle + + // coredynp.num_muls>0?coredynp.MUL_duty_cycle:0 + // + coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0))*1.1<1 + //? (coredynp.ALU_duty_cycle + coredynp.num_muls>0?coredynp.MUL_duty_cycle:0 + // + + // coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0)*1.1:1; + ROB_duty_cycle = 1; + // init stats + if (is_tdp) { + if (coredynp.core_ty == OOO) { + int_inst_window->stats_t.readAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_search_ports; + int_inst_window->stats_t.writeAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_wr_ports; + int_inst_window->stats_t.searchAc.access = + coredynp.issueW * coredynp.num_pipelines; + int_inst_window->tdp_stats = int_inst_window->stats_t; + fp_inst_window->stats_t.readAc.access = + fp_inst_window->l_ip.num_rd_ports * coredynp.num_fp_pipelines; + fp_inst_window->stats_t.writeAc.access = + fp_inst_window->l_ip.num_wr_ports * coredynp.num_fp_pipelines; + fp_inst_window->stats_t.searchAc.access = + fp_inst_window->l_ip.num_search_ports * coredynp.num_fp_pipelines; + fp_inst_window->tdp_stats = fp_inst_window->stats_t; + + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->stats_t.readAc.access = + coredynp.commitW * coredynp.num_pipelines * ROB_duty_cycle; + ROB->stats_t.writeAc.access = + coredynp.issueW * coredynp.num_pipelines * ROB_duty_cycle; + ROB->tdp_stats = ROB->stats_t; + + /* + * When inst commits, ROB must be read. + * Because for Physcial register based cores, physical register tag in + * ROB need to be read out and write into RRAT/CAM based RAT. For RS + * based cores, register content that stored in ROB must be read out and + * stored in architectural registers. + * + * if no-register is involved, the ROB read out operation when + * instruction commits can be ignored. assuming 20% insts. belong this + * type. + * TODO: ROB duty_cycle need to be revisited + */ + } + } + else if (coredynp.multithreaded) { + int_inst_window->stats_t.readAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_search_ports; + int_inst_window->stats_t.writeAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_wr_ports; + int_inst_window->stats_t.searchAc.access = + coredynp.issueW * coredynp.num_pipelines; + int_inst_window->tdp_stats = int_inst_window->stats_t; + } + } + else { // rtp + if (coredynp.core_ty == OOO) { + int_inst_window->stats_t.readAc.access = + XML->sys.core[ithCore].inst_window_reads; + int_inst_window->stats_t.writeAc.access = + XML->sys.core[ithCore].inst_window_writes; + int_inst_window->stats_t.searchAc.access = + XML->sys.core[ithCore].inst_window_wakeup_accesses; + int_inst_window->rtp_stats = int_inst_window->stats_t; + fp_inst_window->stats_t.readAc.access = + XML->sys.core[ithCore].fp_inst_window_reads; + fp_inst_window->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_inst_window_writes; + fp_inst_window->stats_t.searchAc.access = + XML->sys.core[ithCore].fp_inst_window_wakeup_accesses; + fp_inst_window->rtp_stats = fp_inst_window->stats_t; + + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->stats_t.readAc.access = XML->sys.core[ithCore].ROB_reads; + ROB->stats_t.writeAc.access = XML->sys.core[ithCore].ROB_writes; + /* ROB need to be updated in RS based OOO when new values are produced, + * this update may happen before the commit stage when ROB entry is + * released + * 1. ROB write at instruction inserted in + * 2. ROB write as results produced (for RS based OOO only) + * 3. ROB read as instruction committed. For RS based OOO, data values + * are read out and sent to ARF For Physical reg based OOO, no data + * stored in ROB, but register tags need to be read out and used to set + * the RRAT and to recycle the register tag to free list buffer + */ + ROB->rtp_stats = ROB->stats_t; + } + } + else if (coredynp.multithreaded) { + int_inst_window->stats_t.readAc.access = + XML->sys.core[ithCore].int_instructions + + XML->sys.core[ithCore].fp_instructions; + int_inst_window->stats_t.writeAc.access = + XML->sys.core[ithCore].int_instructions + + XML->sys.core[ithCore].fp_instructions; + int_inst_window->stats_t.searchAc.access = + 2 * (XML->sys.core[ithCore].int_instructions + + XML->sys.core[ithCore].fp_instructions); + int_inst_window->rtp_stats = int_inst_window->stats_t; + } + } + + // computation engine + if (coredynp.core_ty == OOO) { + int_inst_window->power_t.reset(); + fp_inst_window->power_t.reset(); + + /* each instruction needs to write to scheduler, read out when all resources + * and source operands are ready two search ops with one for each source + * operand + * + */ + int_inst_window->power_t.readOp.dynamic += + int_inst_window->local_result.power.readOp.dynamic * + int_inst_window->stats_t.readAc.access + + int_inst_window->local_result.power.searchOp.dynamic * + int_inst_window->stats_t.searchAc.access + + int_inst_window->local_result.power.writeOp.dynamic * + int_inst_window->stats_t.writeAc.access + + int_inst_window->stats_t.readAc.access * + instruction_selection->power.readOp.dynamic; + + fp_inst_window->power_t.readOp.dynamic += + fp_inst_window->local_result.power.readOp.dynamic * + fp_inst_window->stats_t.readAc.access + + fp_inst_window->local_result.power.searchOp.dynamic * + fp_inst_window->stats_t.searchAc.access + + fp_inst_window->local_result.power.writeOp.dynamic * + fp_inst_window->stats_t.writeAc.access + + fp_inst_window->stats_t.writeAc.access * + instruction_selection->power.readOp.dynamic; + + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->power_t.reset(); + ROB->power_t.readOp.dynamic += + ROB->local_result.power.readOp.dynamic * ROB->stats_t.readAc.access + + ROB->stats_t.writeAc.access * ROB->local_result.power.writeOp.dynamic; + } + } + else if (coredynp.multithreaded) { + int_inst_window->power_t.reset(); + int_inst_window->power_t.readOp.dynamic += + int_inst_window->local_result.power.readOp.dynamic * + int_inst_window->stats_t.readAc.access + + int_inst_window->local_result.power.searchOp.dynamic * + int_inst_window->stats_t.searchAc.access + + int_inst_window->local_result.power.writeOp.dynamic * + int_inst_window->stats_t.writeAc.access + + int_inst_window->stats_t.writeAc.access * + instruction_selection->power.readOp.dynamic; + } + + // assign values + if (is_tdp) { + if (coredynp.core_ty == OOO) { + int_inst_window->power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + fp_inst_window->power = + fp_inst_window->power_t + + (fp_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + power = power + int_inst_window->power + fp_inst_window->power; + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->power = ROB->power_t + ROB->local_result.power * pppm_lkg; + power = power + ROB->power; + } + } + else if (coredynp.multithreaded) { + // set_pppm(pppm_t, + // XML->sys.core[ithCore].issue_width,1, 1, 1); + int_inst_window->power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + power = power + int_inst_window->power; + } + } + else { // rtp + if (coredynp.core_ty == OOO) { + int_inst_window->rt_power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + fp_inst_window->rt_power = + fp_inst_window->power_t + + (fp_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + rt_power = + rt_power + int_inst_window->rt_power + fp_inst_window->rt_power; + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->rt_power = ROB->power_t + ROB->local_result.power * pppm_lkg; + rt_power = rt_power + ROB->rt_power; + } + } + else if (coredynp.multithreaded) { + // set_pppm(pppm_t, + // XML->sys.core[ithCore].issue_width,1, 1, 1); + int_inst_window->rt_power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + rt_power = rt_power + int_inst_window->rt_power; + } + } + // set_pppm(pppm_t, XML->sys.core[ithCore].issue_width,1, 1, 1); + // cout<<"Scheduler + // power="<power.readOp.dynamic<<"leakage"<power.readOp.leakage<sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + if (coredynp.core_ty == OOO) { + cout << indent_str << "Instruction Window:" << endl; + cout << indent_str_next + << "Area = " << int_inst_window->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << int_inst_window->power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? int_inst_window->power.readOp.longer_channel_leakage + : int_inst_window->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? int_inst_window->power.readOp + .power_gated_with_long_channel_leakage + : int_inst_window->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << int_inst_window->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << int_inst_window->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + cout << indent_str << "FP Instruction Window:" << endl; + cout << indent_str_next + << "Area = " << fp_inst_window->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << fp_inst_window->power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? fp_inst_window->power.readOp.longer_channel_leakage + : fp_inst_window->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? fp_inst_window->power.readOp + .power_gated_with_long_channel_leakage + : fp_inst_window->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fp_inst_window->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fp_inst_window->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + if (XML->sys.core[ithCore].ROB_size > 0) { + cout << indent_str << "ROB:" << endl; + cout << indent_str_next << "Area = " << ROB->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ROB->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ROB->power.readOp.longer_channel_leakage + : ROB->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? ROB->power.readOp.power_gated_with_long_channel_leakage + : ROB->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ROB->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ROB->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else if (coredynp.multithreaded) { + cout << indent_str << "Instruction Window:" << endl; + cout << indent_str_next + << "Area = " << int_inst_window->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << int_inst_window->power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? int_inst_window->power.readOp.longer_channel_leakage + : int_inst_window->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? int_inst_window->power.readOp + .power_gated_with_long_channel_leakage + : int_inst_window->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << int_inst_window->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << int_inst_window->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + } + } + else { + if (coredynp.core_ty == OOO) { + cout << indent_str_next << "Instruction Window Peak Dynamic = " + << int_inst_window->rt_power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Instruction Window Subthreshold Leakage = " + << int_inst_window->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Instruction Window Gate Leakage = " + << int_inst_window->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "FP Instruction Window Peak Dynamic = " + << fp_inst_window->rt_power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next + << "FP Instruction Window Subthreshold Leakage = " + << fp_inst_window->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Instruction Window Gate Leakage = " + << fp_inst_window->rt_power.readOp.gate_leakage << " W" << endl; + if (XML->sys.core[ithCore].ROB_size > 0) { + cout << indent_str_next << "ROB Peak Dynamic = " + << ROB->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "ROB Subthreshold Leakage = " << ROB->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "ROB Gate Leakage = " << ROB->rt_power.readOp.gate_leakage + << " W" << endl; + } + } + else if (coredynp.multithreaded) { + cout << indent_str_next << "Instruction Window Peak Dynamic = " + << int_inst_window->rt_power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Instruction Window Subthreshold Leakage = " + << int_inst_window->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Instruction Window Gate Leakage = " + << int_inst_window->rt_power.readOp.gate_leakage << " W" << endl; + } + } +} + +void LoadStoreU::computeEnergy(bool is_tdp) { + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + dcache.caches->stats_t.readAc.access = + 0.67 * dcache.caches->l_ip.num_rw_ports * coredynp.LSU_duty_cycle; + dcache.caches->stats_t.readAc.miss = 0; + dcache.caches->stats_t.readAc.hit = dcache.caches->stats_t.readAc.access - + dcache.caches->stats_t.readAc.miss; + dcache.caches->stats_t.writeAc.access = + 0.33 * dcache.caches->l_ip.num_rw_ports * coredynp.LSU_duty_cycle; + dcache.caches->stats_t.writeAc.miss = 0; + dcache.caches->stats_t.writeAc.hit = dcache.caches->stats_t.writeAc.access - + dcache.caches->stats_t.writeAc.miss; + dcache.caches->tdp_stats = dcache.caches->stats_t; + + dcache.missb->stats_t.readAc.access = + dcache.missb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.missb->stats_t.writeAc.access = + dcache.missb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.missb->tdp_stats = dcache.missb->stats_t; + + dcache.ifb->stats_t.readAc.access = + dcache.ifb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.ifb->stats_t.writeAc.access = + dcache.ifb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.ifb->tdp_stats = dcache.ifb->stats_t; + + dcache.prefetchb->stats_t.readAc.access = + dcache.prefetchb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.prefetchb->stats_t.writeAc.access = + dcache.ifb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.prefetchb->tdp_stats = dcache.prefetchb->stats_t; + if (cache_p == Write_back) { + dcache.wbb->stats_t.readAc.access = dcache.wbb->l_ip.num_search_ports; + dcache.wbb->stats_t.writeAc.access = dcache.wbb->l_ip.num_search_ports; + dcache.wbb->tdp_stats = dcache.wbb->stats_t; + } + + LSQ->stats_t.readAc.access = LSQ->stats_t.writeAc.access = + LSQ->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + LSQ->tdp_stats = LSQ->stats_t; + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->stats_t.readAc.access = LoadQ->stats_t.writeAc.access = + LoadQ->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + LoadQ->tdp_stats = LoadQ->stats_t; + } + } + else { + // init stats for Runtime Dynamic (RTP) + dcache.caches->stats_t.readAc.access = + XML->sys.core[ithCore].dcache.read_accesses; + dcache.caches->stats_t.readAc.miss = + XML->sys.core[ithCore].dcache.read_misses; + dcache.caches->stats_t.readAc.hit = dcache.caches->stats_t.readAc.access - + dcache.caches->stats_t.readAc.miss; + dcache.caches->stats_t.writeAc.access = + XML->sys.core[ithCore].dcache.write_accesses; + dcache.caches->stats_t.writeAc.miss = + XML->sys.core[ithCore].dcache.write_misses; + dcache.caches->stats_t.writeAc.hit = dcache.caches->stats_t.writeAc.access - + dcache.caches->stats_t.writeAc.miss; + dcache.caches->rtp_stats = dcache.caches->stats_t; + + if (cache_p == Write_back) { + dcache.missb->stats_t.readAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.missb->stats_t.writeAc.access = + dcache.caches->stats_t.writeAc.miss; + dcache.missb->rtp_stats = dcache.missb->stats_t; + + dcache.ifb->stats_t.readAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.ifb->stats_t.writeAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.ifb->rtp_stats = dcache.ifb->stats_t; + + dcache.prefetchb->stats_t.readAc.access = + dcache.caches->stats_t.writeAc.miss; + dcache.prefetchb->stats_t.writeAc.access = + dcache.caches->stats_t.writeAc.miss; + dcache.prefetchb->rtp_stats = dcache.prefetchb->stats_t; + + dcache.wbb->stats_t.readAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.wbb->stats_t.writeAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.wbb->rtp_stats = dcache.wbb->stats_t; + } + else { + dcache.missb->stats_t.readAc.access = dcache.caches->stats_t.readAc.miss; + dcache.missb->stats_t.writeAc.access = dcache.caches->stats_t.readAc.miss; + dcache.missb->rtp_stats = dcache.missb->stats_t; + + dcache.ifb->stats_t.readAc.access = dcache.caches->stats_t.readAc.miss; + dcache.ifb->stats_t.writeAc.access = dcache.caches->stats_t.readAc.miss; + dcache.ifb->rtp_stats = dcache.ifb->stats_t; + + dcache.prefetchb->stats_t.readAc.access = + dcache.caches->stats_t.readAc.miss; + dcache.prefetchb->stats_t.writeAc.access = + dcache.caches->stats_t.readAc.miss; + dcache.prefetchb->rtp_stats = dcache.prefetchb->stats_t; + } + + LSQ->stats_t.readAc.access = (XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions) * + 2; // flush overhead considered + LSQ->stats_t.writeAc.access = (XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions) * + 2; + LSQ->rtp_stats = LSQ->stats_t; + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->stats_t.readAc.access = XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions; + LoadQ->stats_t.writeAc.access = XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions; + LoadQ->rtp_stats = LoadQ->stats_t; + } + } + + dcache.power_t.reset(); + LSQ->power_t.reset(); + dcache.power_t.readOp.dynamic += + (dcache.caches->stats_t.readAc.hit * + dcache.caches->local_result.power.readOp.dynamic + + dcache.caches->stats_t.readAc.miss * + dcache.caches->local_result.power.readOp + .dynamic + // assuming D cache is in the fast model which read + // tag and data together + dcache.caches->stats_t.writeAc.miss * + dcache.caches->local_result.tag_array2->power.readOp.dynamic + + dcache.caches->stats_t.writeAc.access * + dcache.caches->local_result.power.writeOp.dynamic); + + if (cache_p == Write_back) { // write miss will generate a write later + dcache.power_t.readOp.dynamic += + dcache.caches->stats_t.writeAc.miss * + dcache.caches->local_result.power.writeOp.dynamic; + } + + dcache.power_t.readOp.dynamic += + dcache.missb->stats_t.readAc.access * + dcache.missb->local_result.power.searchOp.dynamic + + dcache.missb->stats_t.writeAc.access * + dcache.missb->local_result.power.writeOp + .dynamic; // each access to missb involves a CAM and a write + dcache.power_t.readOp.dynamic += + dcache.ifb->stats_t.readAc.access * + dcache.ifb->local_result.power.searchOp.dynamic + + dcache.ifb->stats_t.writeAc.access * + dcache.ifb->local_result.power.writeOp.dynamic; + dcache.power_t.readOp.dynamic += + dcache.prefetchb->stats_t.readAc.access * + dcache.prefetchb->local_result.power.searchOp.dynamic + + dcache.prefetchb->stats_t.writeAc.access * + dcache.prefetchb->local_result.power.writeOp.dynamic; + if (cache_p == Write_back) { + dcache.power_t.readOp.dynamic += + dcache.wbb->stats_t.readAc.access * + dcache.wbb->local_result.power.searchOp.dynamic + + dcache.wbb->stats_t.writeAc.access * + dcache.wbb->local_result.power.writeOp.dynamic; + } + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->power_t.reset(); + LoadQ->power_t.readOp.dynamic += + LoadQ->stats_t.readAc.access * + (LoadQ->local_result.power.searchOp.dynamic + + LoadQ->local_result.power.readOp.dynamic) + + LoadQ->stats_t.writeAc.access * + LoadQ->local_result.power.writeOp.dynamic; // every memory access + // invloves at least two + // operations on LoadQ + + LSQ->power_t.readOp.dynamic += + LSQ->stats_t.readAc.access * (LSQ->local_result.power.searchOp.dynamic + + LSQ->local_result.power.readOp.dynamic) + + LSQ->stats_t.writeAc.access * + LSQ->local_result.power.writeOp.dynamic; // every memory access + // invloves at least two + // operations on LSQ + } + else { + LSQ->power_t.readOp.dynamic += + LSQ->stats_t.readAc.access * (LSQ->local_result.power.searchOp.dynamic + + LSQ->local_result.power.readOp.dynamic) + + LSQ->stats_t.writeAc.access * + LSQ->local_result.power.writeOp.dynamic; // every memory access + // invloves at least two + // operations on LSQ + } + + if (is_tdp) { + // dcache.power = dcache.power_t + + // (dcache.caches->local_result.power)*pppm_lkg + + // (dcache.missb->local_result.power + + // dcache.ifb->local_result.power + + // dcache.prefetchb->local_result.power + + // dcache.wbb->local_result.power)*pppm_Isub; + dcache.power = dcache.power_t + (dcache.caches->local_result.power + + dcache.missb->local_result.power + + dcache.ifb->local_result.power + + dcache.prefetchb->local_result.power) * + pppm_lkg; + if (cache_p == Write_back) { + dcache.power = dcache.power + dcache.wbb->local_result.power * pppm_lkg; + } + + LSQ->power = LSQ->power_t + LSQ->local_result.power * pppm_lkg; + power = power + dcache.power + LSQ->power; + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->power = LoadQ->power_t + LoadQ->local_result.power * pppm_lkg; + power = power + LoadQ->power; + } + } + else { + // dcache.rt_power = dcache.power_t + + // (dcache.caches->local_result.power + + // dcache.missb->local_result.power + + // dcache.ifb->local_result.power + + // dcache.prefetchb->local_result.power + + // dcache.wbb->local_result.power)*pppm_lkg; + dcache.rt_power = dcache.power_t + (dcache.caches->local_result.power + + dcache.missb->local_result.power + + dcache.ifb->local_result.power + + dcache.prefetchb->local_result.power) * + pppm_lkg; + + if (cache_p == Write_back) { + dcache.rt_power = + dcache.rt_power + dcache.wbb->local_result.power * pppm_lkg; + } + + LSQ->rt_power = LSQ->power_t + LSQ->local_result.power * pppm_lkg; + rt_power = rt_power + dcache.rt_power + LSQ->rt_power; + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->rt_power = LoadQ->power_t + LoadQ->local_result.power * pppm_lkg; + rt_power = rt_power + LoadQ->rt_power; + } + } +} + +void LoadStoreU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Data Cache:" << endl; + cout << indent_str_next << "Area = " << dcache.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << dcache.power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? dcache.power.readOp.longer_channel_leakage + : dcache.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? dcache.power.readOp.power_gated_with_long_channel_leakage + : dcache.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << dcache.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << dcache.rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (coredynp.core_ty == Inorder) { + cout << indent_str << "Load/Store Queue:" << endl; + cout << indent_str_next << "Area = " << LSQ->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << LSQ->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? LSQ->power.readOp.longer_channel_leakage + : LSQ->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? LSQ->power.readOp.power_gated_with_long_channel_leakage + : LSQ->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << LSQ->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << LSQ->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + else + + { + if (XML->sys.core[ithCore].load_buffer_size > 0) { + cout << indent_str << "LoadQ:" << endl; + cout << indent_str_next << "Area = " << LoadQ->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << LoadQ->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? LoadQ->power.readOp.longer_channel_leakage + : LoadQ->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? LoadQ->power.readOp + .power_gated_with_long_channel_leakage + : LoadQ->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << LoadQ->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << LoadQ->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + cout << indent_str << "StoreQ:" << endl; + cout << indent_str_next << "Area = " << LSQ->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << LSQ->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? LSQ->power.readOp.longer_channel_leakage + : LSQ->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? LSQ->power.readOp.power_gated_with_long_channel_leakage + : LSQ->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << LSQ->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << LSQ->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << indent_str_next << "Data Cache Peak Dynamic = " + << dcache.rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Data Cache Subthreshold Leakage = " + << dcache.rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Data Cache Gate Leakage = " + << dcache.rt_power.readOp.gate_leakage << " W" << endl; + if (coredynp.core_ty == Inorder) { + cout << indent_str_next << "Load/Store Queue Peak Dynamic = " + << LSQ->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Load/Store Queue Subthreshold Leakage = " + << LSQ->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Load/Store Queue Gate Leakage = " + << LSQ->rt_power.readOp.gate_leakage << " W" << endl; + } + else { + cout << indent_str_next << "LoadQ Peak Dynamic = " + << LoadQ->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "LoadQ Subthreshold Leakage = " + << LoadQ->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "LoadQ Gate Leakage = " << LoadQ->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "StoreQ Peak Dynamic = " + << LSQ->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "StoreQ Subthreshold Leakage = " << LSQ->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "StoreQ Gate Leakage = " << LSQ->rt_power.readOp.gate_leakage + << " W" << endl; + } + } +} + +void MemManU::computeEnergy(bool is_tdp) { + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + itlb->stats_t.readAc.access = + itlb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + itlb->stats_t.readAc.miss = 0; + itlb->stats_t.readAc.hit = + itlb->stats_t.readAc.access - itlb->stats_t.readAc.miss; + itlb->tdp_stats = itlb->stats_t; + + dtlb->stats_t.readAc.access = + dtlb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dtlb->stats_t.readAc.miss = 0; + dtlb->stats_t.readAc.hit = + dtlb->stats_t.readAc.access - dtlb->stats_t.readAc.miss; + dtlb->tdp_stats = dtlb->stats_t; + } + else { + // init stats for Runtime Dynamic (RTP) + itlb->stats_t.readAc.access = XML->sys.core[ithCore].itlb.total_accesses; + itlb->stats_t.readAc.miss = XML->sys.core[ithCore].itlb.total_misses; + itlb->stats_t.readAc.hit = + itlb->stats_t.readAc.access - itlb->stats_t.readAc.miss; + itlb->rtp_stats = itlb->stats_t; + + dtlb->stats_t.readAc.access = XML->sys.core[ithCore].dtlb.total_accesses; + dtlb->stats_t.readAc.miss = XML->sys.core[ithCore].dtlb.total_misses; + dtlb->stats_t.readAc.hit = + dtlb->stats_t.readAc.access - dtlb->stats_t.readAc.miss; + dtlb->rtp_stats = dtlb->stats_t; + } + + itlb->power_t.reset(); + dtlb->power_t.reset(); + itlb->power_t.readOp.dynamic += + itlb->stats_t.readAc.access * + itlb->local_result.power.searchOp.dynamic // FA spent most power in + // tag, so use total access + // not hits + + itlb->stats_t.readAc.miss * itlb->local_result.power.writeOp.dynamic; + dtlb->power_t.readOp.dynamic += + dtlb->stats_t.readAc.access * + dtlb->local_result.power.searchOp.dynamic // FA spent most power in + // tag, so use total access + // not hits + + dtlb->stats_t.readAc.miss * dtlb->local_result.power.writeOp.dynamic; + + if (is_tdp) { + itlb->power = itlb->power_t + itlb->local_result.power * pppm_lkg; + dtlb->power = dtlb->power_t + dtlb->local_result.power * pppm_lkg; + power = power + itlb->power + dtlb->power; + } + else { + itlb->rt_power = itlb->power_t + itlb->local_result.power * pppm_lkg; + dtlb->rt_power = dtlb->power_t + dtlb->local_result.power * pppm_lkg; + rt_power = rt_power + itlb->rt_power + dtlb->rt_power; + } +} + +void MemManU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Itlb:" << endl; + cout << indent_str_next << "Area = " << itlb->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << itlb->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? itlb->power.readOp.longer_channel_leakage + : itlb->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? itlb->power.readOp.power_gated_with_long_channel_leakage + : itlb->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << itlb->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << itlb->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "Dtlb:" << endl; + cout << indent_str_next << "Area = " << dtlb->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << dtlb->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? dtlb->power.readOp.longer_channel_leakage + : dtlb->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? dtlb->power.readOp.power_gated_with_long_channel_leakage + : dtlb->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << dtlb->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << dtlb->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + else { + cout << indent_str_next << "Itlb Peak Dynamic = " + << itlb->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "Itlb Subthreshold Leakage = " << itlb->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Itlb Gate Leakage = " << itlb->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Dtlb Peak Dynamic = " + << dtlb->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "Dtlb Subthreshold Leakage = " << dtlb->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Dtlb Gate Leakage = " << dtlb->rt_power.readOp.gate_leakage + << " W" << endl; + } +} + +void RegFU::computeEnergy(bool is_tdp) { + /* + * Architecture RF and physical RF cannot be present at the same time. + * Therefore, the RF stats can only refer to either ARF or PRF; + * And the same stats can be used for both. + */ + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + IRF->stats_t.readAc.access = + coredynp.issueW * 2 * + (coredynp.ALU_duty_cycle * 1.1 + + (coredynp.num_muls > 0 ? coredynp.MUL_duty_cycle : 0)) * + coredynp.num_pipelines; + IRF->stats_t.writeAc.access = + coredynp.issueW * + (coredynp.ALU_duty_cycle * 1.1 + + (coredynp.num_muls > 0 ? coredynp.MUL_duty_cycle : 0)) * + coredynp.num_pipelines; + // Rule of Thumb: about 10% RF related instructions do not need to access + // ALUs + IRF->tdp_stats = IRF->stats_t; + + FRF->stats_t.readAc.access = FRF->l_ip.num_rd_ports * + coredynp.FPU_duty_cycle * 1.05 * + coredynp.num_fp_pipelines; + FRF->stats_t.writeAc.access = FRF->l_ip.num_wr_ports * + coredynp.FPU_duty_cycle * 1.05 * + coredynp.num_fp_pipelines; + FRF->tdp_stats = FRF->stats_t; + if (coredynp.regWindowing) { + RFWIN->stats_t.readAc.access = 0; // 0.5*RFWIN->l_ip.num_rw_ports; + RFWIN->stats_t.writeAc.access = 0; // 0.5*RFWIN->l_ip.num_rw_ports; + RFWIN->tdp_stats = RFWIN->stats_t; + } + } + else { + // init stats for Runtime Dynamic (RTP) + IRF->stats_t.readAc.access = + XML->sys.core[ithCore] + .int_regfile_reads; // TODO: no diff on archi and phy + IRF->stats_t.writeAc.access = XML->sys.core[ithCore].int_regfile_writes; + IRF->rtp_stats = IRF->stats_t; + + FRF->stats_t.readAc.access = XML->sys.core[ithCore].float_regfile_reads; + FRF->stats_t.writeAc.access = XML->sys.core[ithCore].float_regfile_writes; + FRF->rtp_stats = FRF->stats_t; + if (coredynp.regWindowing) { + RFWIN->stats_t.readAc.access = XML->sys.core[ithCore].function_calls * 16; + RFWIN->stats_t.writeAc.access = + XML->sys.core[ithCore].function_calls * 16; + RFWIN->rtp_stats = RFWIN->stats_t; + + IRF->stats_t.readAc.access = XML->sys.core[ithCore].int_regfile_reads + + XML->sys.core[ithCore].function_calls * 16; + IRF->stats_t.writeAc.access = XML->sys.core[ithCore].int_regfile_writes + + XML->sys.core[ithCore].function_calls * 16; + IRF->rtp_stats = IRF->stats_t; + + FRF->stats_t.readAc.access = XML->sys.core[ithCore].float_regfile_reads + + XML->sys.core[ithCore].function_calls * 16; + ; + FRF->stats_t.writeAc.access = + XML->sys.core[ithCore].float_regfile_writes + + XML->sys.core[ithCore].function_calls * 16; + ; + FRF->rtp_stats = FRF->stats_t; + } + } + IRF->power_t.reset(); + FRF->power_t.reset(); + IRF->power_t.readOp.dynamic += + (IRF->stats_t.readAc.access * IRF->local_result.power.readOp.dynamic + + IRF->stats_t.writeAc.access * IRF->local_result.power.writeOp.dynamic); + FRF->power_t.readOp.dynamic += + (FRF->stats_t.readAc.access * FRF->local_result.power.readOp.dynamic + + FRF->stats_t.writeAc.access * FRF->local_result.power.writeOp.dynamic); + if (coredynp.regWindowing) { + RFWIN->power_t.reset(); + RFWIN->power_t.readOp.dynamic += + (RFWIN->stats_t.readAc.access * + RFWIN->local_result.power.readOp.dynamic + + RFWIN->stats_t.writeAc.access * + RFWIN->local_result.power.writeOp.dynamic); + } + + if (is_tdp) { + IRF->power = IRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (IRF->local_result.power * coredynp.pppm_lkg_multhread) + : IRF->local_result.power); + FRF->power = FRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (FRF->local_result.power * coredynp.pppm_lkg_multhread) + : FRF->local_result.power); + power = power + (IRF->power + FRF->power); + if (coredynp.regWindowing) { + RFWIN->power = RFWIN->power_t + RFWIN->local_result.power * pppm_lkg; + power = power + RFWIN->power; + } + } + else { + IRF->rt_power = + IRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (IRF->local_result.power * coredynp.pppm_lkg_multhread) + : IRF->local_result.power); + FRF->rt_power = + FRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (FRF->local_result.power * coredynp.pppm_lkg_multhread) + : FRF->local_result.power); + rt_power = rt_power + (IRF->power_t + FRF->power_t); + if (coredynp.regWindowing) { + RFWIN->rt_power = RFWIN->power_t + RFWIN->local_result.power * pppm_lkg; + rt_power = rt_power + RFWIN->rt_power; + } + } +} + +void RegFU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Integer RF:" << endl; + cout << indent_str_next << "Area = " << IRF->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << IRF->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? IRF->power.readOp.longer_channel_leakage + : IRF->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? IRF->power.readOp.power_gated_with_long_channel_leakage + : IRF->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << IRF->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << IRF->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + cout << indent_str << "Floating Point RF:" << endl; + cout << indent_str_next << "Area = " << FRF->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << FRF->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? FRF->power.readOp.longer_channel_leakage + : FRF->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? FRF->power.readOp.power_gated_with_long_channel_leakage + : FRF->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << FRF->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << FRF->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + if (coredynp.regWindowing) { + cout << indent_str << "Register Windows:" << endl; + cout << indent_str_next << "Area = " << RFWIN->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << RFWIN->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? RFWIN->power.readOp.longer_channel_leakage + : RFWIN->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? RFWIN->power.readOp.power_gated_with_long_channel_leakage + : RFWIN->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << RFWIN->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << RFWIN->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << indent_str_next << "Integer RF Peak Dynamic = " + << IRF->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Integer RF Subthreshold Leakage = " + << IRF->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "Integer RF Gate Leakage = " << IRF->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Floating Point RF Peak Dynamic = " + << FRF->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Floating Point RF Subthreshold Leakage = " + << FRF->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Floating Point RF Gate Leakage = " + << FRF->rt_power.readOp.gate_leakage << " W" << endl; + if (coredynp.regWindowing) { + cout << indent_str_next << "Register Windows Peak Dynamic = " + << RFWIN->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Register Windows Subthreshold Leakage = " + << RFWIN->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Register Windows Gate Leakage = " + << RFWIN->rt_power.readOp.gate_leakage << " W" << endl; + } + } +} + +void EXECU::computeEnergy(bool is_tdp) { + if (!exist) + return; + double pppm_t[4] = {1, 1, 1, 1}; + // rfu->power.reset(); + // rfu->rt_power.reset(); + // scheu->power.reset(); + // scheu->rt_power.reset(); + // exeu->power.reset(); + // exeu->rt_power.reset(); + + rfu->computeEnergy(is_tdp); + scheu->computeEnergy(is_tdp); + exeu->computeEnergy(is_tdp); + if (coredynp.num_fpus > 0) { + fp_u->computeEnergy(is_tdp); + } + if (coredynp.num_muls > 0) { + mul->computeEnergy(is_tdp); + } + + if (is_tdp) { + set_pppm(pppm_t, 2 * coredynp.ALU_cdb_duty_cycle, 2, 2, + 2 * coredynp.ALU_cdb_duty_cycle); // 2 means two source operands + // needs to be passed for each + // int instruction. + bypass.power = bypass.power + intTagBypass->power * pppm_t + + int_bypass->power * pppm_t; + if (coredynp.num_muls > 0) { + set_pppm(pppm_t, 2 * coredynp.MUL_cdb_duty_cycle, 2, 2, + 2 * coredynp.MUL_cdb_duty_cycle); // 2 means two source operands + // needs to be passed for each + // int instruction. + bypass.power = bypass.power + intTag_mul_Bypass->power * pppm_t + + int_mul_bypass->power * pppm_t; + power = power + mul->power; + } + if (coredynp.num_fpus > 0) { + set_pppm(pppm_t, 3 * coredynp.FPU_cdb_duty_cycle, 3, 3, + 3 * coredynp.FPU_cdb_duty_cycle); // 3 means three source + // operands needs to be passed + // for each fp instruction. + bypass.power = bypass.power + fp_bypass->power * pppm_t + + fpTagBypass->power * pppm_t; + power = power + fp_u->power; + } + + power = power + rfu->power + exeu->power + bypass.power + scheu->power; + } + else { + set_pppm(pppm_t, XML->sys.core[ithCore].cdb_alu_accesses, 2, 2, + XML->sys.core[ithCore].cdb_alu_accesses); + bypass.rt_power = bypass.rt_power + intTagBypass->power * pppm_t; + bypass.rt_power = bypass.rt_power + int_bypass->power * pppm_t; + + if (coredynp.num_muls > 0) { + set_pppm(pppm_t, XML->sys.core[ithCore].cdb_mul_accesses, 2, 2, + XML->sys.core[ithCore].cdb_mul_accesses); // 2 means two source + // operands needs to + // be passed for each + // int instruction. + bypass.rt_power = bypass.rt_power + intTag_mul_Bypass->power * pppm_t + + int_mul_bypass->power * pppm_t; + rt_power = rt_power + mul->rt_power; + } + + if (coredynp.num_fpus > 0) { + set_pppm(pppm_t, XML->sys.core[ithCore].cdb_fpu_accesses, 3, 3, + XML->sys.core[ithCore].cdb_fpu_accesses); + bypass.rt_power = bypass.rt_power + fp_bypass->power * pppm_t; + bypass.rt_power = bypass.rt_power + fpTagBypass->power * pppm_t; + rt_power = rt_power + fp_u->rt_power; + } + rt_power = rt_power + rfu->rt_power + exeu->rt_power + bypass.rt_power + + scheu->rt_power; + } +} + +void EXECU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + // cout << indent_str_next << "Results Broadcast Bus Area = " << + // bypass->area.get_area() *1e-6 << " mm^2" << endl; + if (is_tdp) { + cout << indent_str << "Register Files:" << endl; + cout << indent_str_next << "Area = " << rfu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << rfu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? rfu->power.readOp.longer_channel_leakage + : rfu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? rfu->power.readOp.power_gated_with_long_channel_leakage + : rfu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << rfu->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rfu->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + if (plevel > 3) { + rfu->displayEnergy(indent + 4, is_tdp); + } + cout << indent_str << "Instruction Scheduler:" << endl; + cout << indent_str_next << "Area = " << scheu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << scheu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? scheu->power.readOp.longer_channel_leakage + : scheu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? scheu->power.readOp.power_gated_with_long_channel_leakage + : scheu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << scheu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << scheu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 3) { + scheu->displayEnergy(indent + 4, is_tdp); + } + exeu->displayEnergy(indent, is_tdp); + if (coredynp.num_fpus > 0) { + fp_u->displayEnergy(indent, is_tdp); + } + if (coredynp.num_muls > 0) { + mul->displayEnergy(indent, is_tdp); + } + cout << indent_str << "Results Broadcast Bus:" << endl; + cout << indent_str_next + << "Area Overhead = " << bypass.area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << bypass.power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? bypass.power.readOp.longer_channel_leakage + : bypass.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? bypass.power.readOp.power_gated_with_long_channel_leakage + : bypass.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << bypass.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << bypass.rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + else { + cout << indent_str_next << "Register Files Peak Dynamic = " + << rfu->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Register Files Subthreshold Leakage = " + << rfu->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Register Files Gate Leakage = " + << rfu->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Instruction Sheduler Peak Dynamic = " + << scheu->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Instruction Sheduler Subthreshold Leakage = " + << scheu->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Instruction Sheduler Gate Leakage = " + << scheu->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Results Broadcast Bus Peak Dynamic = " + << bypass.rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Results Broadcast Bus Subthreshold Leakage = " + << bypass.rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Results Broadcast Bus Gate Leakage = " + << bypass.rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void Core::computeEnergy(bool is_tdp) { + /* + * When computing TDP, power = energy_per_cycle (the value computed in this + * function) * clock_rate (in the display_energy function) When computing + * dyn_power; power = total energy (the value computed in this function) / + * Total execution time (cycle count / clock rate) + */ + // power_point_product_masks + double pppm_t[4] = {1, 1, 1, 1}; + double rtp_pipeline_coe; + double num_units = 4.0; + if (is_tdp) { + ifu->computeEnergy(is_tdp); + lsu->computeEnergy(is_tdp); + mmu->computeEnergy(is_tdp); + exu->computeEnergy(is_tdp); + + if (coredynp.core_ty == OOO) { + num_units = 5.0; + rnu->computeEnergy(is_tdp); + set_pppm( + pppm_t, coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / + num_units); // User need to feed a duty cycle to improve accuracy + if (rnu->exist) { + rnu->power = rnu->power + corepipe->power * pppm_t; + power = power + rnu->power; + } + } + + if (ifu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * coredynp.IFU_duty_cycle, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + // cout << "IFU = " << + // ifu->power.readOp.dynamic*clockRate << " W" << endl; + ifu->power = ifu->power + corepipe->power * pppm_t; + // cout << "IFU = " << + // ifu->power.readOp.dynamic*clockRate << " W" << endl; + // cout << "1/4 pipe = " << + // corepipe->power.readOp.dynamic*clockRate/num_units << " W" << endl; + power = power + ifu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + if (lsu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * coredynp.LSU_duty_cycle, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + lsu->power = lsu->power + corepipe->power * pppm_t; + // cout << "LSU = " << + // lsu->power.readOp.dynamic*clockRate << " W" << endl; + power = power + lsu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + if (exu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * coredynp.ALU_duty_cycle, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + exu->power = exu->power + corepipe->power * pppm_t; + // cout << "EXE = " << + // exu->power.readOp.dynamic*clockRate << " W" << endl; + power = power + exu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + if (mmu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * + (0.5 + 0.5 * coredynp.LSU_duty_cycle), + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + mmu->power = mmu->power + corepipe->power * pppm_t; + // cout << "MMU = " << + // mmu->power.readOp.dynamic*clockRate << " W" << endl; + power = power + mmu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + + power = power + undiffCore->power; + + if (XML->sys.Private_L2) { + l2cache->computeEnergy(is_tdp); + set_pppm(pppm_t, l2cache->cachep.clockRate / clockRate, 1, 1, 1); + // l2cache->power = l2cache->power*pppm_t; + power = power + l2cache->power * pppm_t; + } + } + else { + ifu->computeEnergy(is_tdp); + lsu->computeEnergy(is_tdp); + mmu->computeEnergy(is_tdp); + exu->computeEnergy(is_tdp); + + if (coredynp.core_ty == OOO) { + num_units = 5.0; + rnu->computeEnergy(is_tdp); + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + XML->sys.total_cycles * XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + if (rnu->exist) { + rnu->rt_power = rnu->rt_power + corepipe->power * pppm_t; + + rt_power = rt_power + rnu->rt_power; + } + } + else { + num_units = 4.0; + } + + if (ifu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.IFU_duty_cycle * XML->sys.total_cycles * + XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.IFU_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + ifu->rt_power = ifu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + ifu->rt_power; + } + if (lsu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.LSU_duty_cycle * XML->sys.total_cycles * + XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.LSU_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + + lsu->rt_power = lsu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + lsu->rt_power; + } + if (exu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.ALU_duty_cycle * XML->sys.total_cycles * + XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.ALU_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + exu->rt_power = exu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + exu->rt_power; + } + if (mmu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + (0.5 + 0.5 * coredynp.LSU_duty_cycle) * + XML->sys.total_cycles * XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + (0.5 + 0.5 * coredynp.LSU_duty_cycle) * + coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + mmu->rt_power = mmu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + mmu->rt_power; + } + + rt_power = rt_power + undiffCore->power; + // cout << "EXE = " << exu->power.readOp.dynamic*clockRate << " W" + //<< endl; + if (XML->sys.Private_L2) { + l2cache->computeEnergy(is_tdp); + // set_pppm(pppm_t,1/l2cache->cachep.executionTime, 1,1,1); + // l2cache->rt_power = l2cache->rt_power*pppm_t; + rt_power = rt_power + l2cache->rt_power; + } + } +} + +void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "Core:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + if (ifu->exist) { + cout << indent_str << "Instruction Fetch Unit:" << endl; + cout << indent_str_next << "Area = " << ifu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ifu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ifu->power.readOp.longer_channel_leakage + : ifu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? ifu->power.readOp.power_gated_with_long_channel_leakage + : ifu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ifu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ifu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + ifu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + if (coredynp.core_ty == OOO) { + if (rnu->exist) { + cout << indent_str << "Renaming Unit:" << endl; + cout << indent_str_next << "Area = " << rnu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << rnu->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? rnu->power.readOp.longer_channel_leakage + : rnu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? rnu->power.readOp.power_gated_with_long_channel_leakage + : rnu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << rnu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << rnu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + rnu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + } + if (lsu->exist) { + cout << indent_str << "Load Store Unit:" << endl; + cout << indent_str_next << "Area = " << lsu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << lsu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? lsu->power.readOp.longer_channel_leakage + : lsu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? lsu->power.readOp.power_gated_with_long_channel_leakage + : lsu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << lsu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << lsu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + lsu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + if (mmu->exist) { + cout << indent_str << "Memory Management Unit:" << endl; + cout << indent_str_next << "Area = " << mmu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << mmu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? mmu->power.readOp.longer_channel_leakage + : mmu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? mmu->power.readOp.power_gated_with_long_channel_leakage + : mmu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << mmu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + mmu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + if (exu->exist) { + cout << indent_str << "Execution Unit:" << endl; + cout << indent_str_next << "Area = " << exu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << exu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? exu->power.readOp.longer_channel_leakage + : exu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? exu->power.readOp.power_gated_with_long_channel_leakage + : exu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << exu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + exu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + // if (plevel >2) + // { + // if (undiffCore->exist) + // { + // cout << indent_str << "Undifferentiated Core" << + // endl; cout << indent_str_next << "Area = " << + // undiffCore->area.get_area()*1e-6<< " mm^2" << endl; + // cout << indent_str_next << "Peak Dynamic = " << + // undiffCore->power.readOp.dynamic*clockRate << " W" << endl; + //// cout << indent_str_next << "Subthreshold + /// Leakage + ///= + ///" + ///<< undiffCore->power.readOp.leakage <<" W" << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= + //" + // << + //(long_channel? + // undiffCore->power.readOp.longer_channel_leakage:undiffCore->power.readOp.leakage) + //<< " W" << endl; + // cout << indent_str_next << "Gate Leakage = " << + // undiffCore->power.readOp.gate_leakage << " W" << endl; + // // cout << indent_str_next << + //"Runtime Dynamic + //= + //" + //<< undiffCore->rt_power.readOp.dynamic/executionTime << " W" << endl; + // cout <sys.Private_L2) { + l2cache->displayEnergy(4, is_tdp); + } + } + else { + // cout << indent_str_next << "Instruction Fetch Unit Peak + // Dynamic + //= + //" + //<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Subthreshold + // Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Gate + // Leakage + //= + //" + //<< ifu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Peak Dynamic = " << + // lsu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Load Store Unit Subthreshold Leakage = " << + // lsu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Gate Leakage = " << + // lsu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Peak Dynamic = " << + // mmu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Memory Management Unit Subthreshold Leakage = " + // << mmu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Gate Leakage = " << + // mmu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Peak Dynamic = " << + // exu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Execution Unit Subthreshold Leakage = " << + // exu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Gate Leakage = " << + // exu->rt_power.readOp.gate_leakage << " W" << endl; + } +} +InstFetchU ::~InstFetchU() { + if (!exist) + return; + if (IB) { + delete IB; + IB = 0; + } + if (ID_inst) { + delete ID_inst; + ID_inst = 0; + } + if (ID_operand) { + delete ID_operand; + ID_operand = 0; + } + if (ID_misc) { + delete ID_misc; + ID_misc = 0; + } + if (coredynp.predictionW > 0) { + if (BTB) { + delete BTB; + BTB = 0; + } + if (BPT) { + delete BPT; + BPT = 0; + } + } +} + +BranchPredictor ::~BranchPredictor() { + if (!exist) + return; + if (globalBPT) { + delete globalBPT; + globalBPT = 0; + } + if (localBPT) { + delete localBPT; + localBPT = 0; + } + if (L1_localBPT) { + delete L1_localBPT; + L1_localBPT = 0; + } + if (L2_localBPT) { + delete L2_localBPT; + L2_localBPT = 0; + } + if (chooser) { + delete chooser; + chooser = 0; + } + if (RAS) { + delete RAS; + RAS = 0; + } +} + +RENAMINGU ::~RENAMINGU() { + if (!exist) + return; + if (iFRAT) { + delete iFRAT; + iFRAT = 0; + } + if (iRRAT) { + delete iRRAT; + iRRAT = 0; + } + if (iFRAT) { + delete iFRAT; + iFRAT = 0; + } + if (ifreeL) { + delete ifreeL; + ifreeL = 0; + } + if (idcl) { + delete idcl; + idcl = 0; + } + if (fFRAT) { + delete fFRAT; + fFRAT = 0; + } + if (fRRAT) { + delete fRRAT; + fRRAT = 0; + } + if (fdcl) { + delete fdcl; + fdcl = 0; + } + if (ffreeL) { + delete ffreeL; + ffreeL = 0; + } + if (RAHT) { + delete RAHT; + RAHT = 0; + } +} + +LoadStoreU ::~LoadStoreU() { + if (!exist) + return; + if (LSQ) { + delete LSQ; + LSQ = 0; + } + if (LoadQ) { + delete LoadQ; + LoadQ = 0; + } +} + +MemManU ::~MemManU() { + if (!exist) + return; + if (itlb) { + delete itlb; + itlb = 0; + } + if (dtlb) { + delete dtlb; + dtlb = 0; + } +} + +RegFU ::~RegFU() { + if (!exist) + return; + if (IRF) { + delete IRF; + IRF = 0; + } + if (FRF) { + delete FRF; + FRF = 0; + } + if (RFWIN) { + delete RFWIN; + RFWIN = 0; + } +} + +SchedulerU ::~SchedulerU() { + if (!exist) + return; + if (int_inst_window) { + delete int_inst_window; + int_inst_window = 0; + } + if (fp_inst_window) { + delete fp_inst_window; + fp_inst_window = 0; + } + if (ROB) { + delete ROB; + ROB = 0; + } + if (instruction_selection) { + delete instruction_selection; + instruction_selection = 0; + } +} + +EXECU ::~EXECU() { + if (!exist) + return; + if (int_bypass) { + delete int_bypass; + int_bypass = 0; + } + if (intTagBypass) { + delete intTagBypass; + intTagBypass = 0; + } + if (int_mul_bypass) { + delete int_mul_bypass; + int_mul_bypass = 0; + } + if (intTag_mul_Bypass) { + delete intTag_mul_Bypass; + intTag_mul_Bypass = 0; + } + if (fp_bypass) { + delete fp_bypass; + fp_bypass = 0; + } + if (fpTagBypass) { + delete fpTagBypass; + fpTagBypass = 0; + } + if (fp_u) { + delete fp_u; + fp_u = 0; + } + if (exeu) { + delete exeu; + exeu = 0; + } + if (mul) { + delete mul; + mul = 0; + } + if (rfu) { + delete rfu; + rfu = 0; + } + if (scheu) { + delete scheu; + scheu = 0; + } +} + +Core ::~Core() { + if (ifu) { + delete ifu; + ifu = 0; + } + if (lsu) { + delete lsu; + lsu = 0; + } + if (rnu) { + delete rnu; + rnu = 0; + } + if (mmu) { + delete mmu; + mmu = 0; + } + if (exu) { + delete exu; + exu = 0; + } + if (corepipe) { + delete corepipe; + corepipe = 0; + } + if (undiffCore) { + delete undiffCore; + undiffCore = 0; + } + if (l2cache) { + delete l2cache; + l2cache = 0; + } +} + +void Core::set_core_param() { + coredynp.opt_local = XML->sys.core[ithCore].opt_local; + coredynp.x86 = XML->sys.core[ithCore].x86; + coredynp.Embedded = XML->sys.Embedded; + coredynp.core_ty = (enum Core_type)XML->sys.core[ithCore].machine_type; + coredynp.rm_ty = (enum Renaming_type)XML->sys.core[ithCore].rename_scheme; + coredynp.fetchW = XML->sys.core[ithCore].fetch_width; + coredynp.decodeW = XML->sys.core[ithCore].decode_width; + coredynp.issueW = XML->sys.core[ithCore].issue_width; + coredynp.peak_issueW = XML->sys.core[ithCore].peak_issue_width; + coredynp.commitW = XML->sys.core[ithCore].commit_width; + coredynp.peak_commitW = XML->sys.core[ithCore].peak_issue_width; + coredynp.predictionW = XML->sys.core[ithCore].prediction_width; + coredynp.fp_issueW = XML->sys.core[ithCore].fp_issue_width; + coredynp.fp_decodeW = XML->sys.core[ithCore].fp_issue_width; + coredynp.num_alus = XML->sys.core[ithCore].ALU_per_core; + coredynp.num_fpus = XML->sys.core[ithCore].FPU_per_core; + coredynp.num_muls = XML->sys.core[ithCore].MUL_per_core; + coredynp.vdd = XML->sys.core[ithCore].vdd; + coredynp.power_gating_vcc = XML->sys.core[ithCore].power_gating_vcc; + + coredynp.num_hthreads = XML->sys.core[ithCore].number_hardware_threads; + coredynp.multithreaded = coredynp.num_hthreads > 1 ? true : false; + coredynp.hthread_width = + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))); + coredynp.instruction_length = XML->sys.core[ithCore].instruction_length; + coredynp.pc_width = XML->sys.virtual_address_width; + + coredynp.opcode_length = XML->sys.core[ithCore].opcode_width; + coredynp.micro_opcode_length = XML->sys.core[ithCore].micro_opcode_width; + coredynp.num_pipelines = XML->sys.core[ithCore].pipelines_per_core[0]; + coredynp.pipeline_stages = XML->sys.core[ithCore].pipeline_depth[0]; + coredynp.num_fp_pipelines = XML->sys.core[ithCore].pipelines_per_core[1]; + coredynp.fp_pipeline_stages = XML->sys.core[ithCore].pipeline_depth[1]; + coredynp.int_data_width = int(ceil(XML->sys.machine_bits / 32.0)) * 32; + coredynp.fp_data_width = coredynp.int_data_width; + coredynp.v_address_width = XML->sys.virtual_address_width; + coredynp.p_address_width = XML->sys.physical_address_width; + + coredynp.scheu_ty = + (enum Scheduler_type)XML->sys.core[ithCore].instruction_window_scheme; + coredynp.arch_ireg_width = + int(ceil(log2(XML->sys.core[ithCore].archi_Regs_IRF_size))); + coredynp.arch_freg_width = + int(ceil(log2(XML->sys.core[ithCore].archi_Regs_FRF_size))); + coredynp.num_IRF_entry = XML->sys.core[ithCore].archi_Regs_IRF_size; + coredynp.num_FRF_entry = XML->sys.core[ithCore].archi_Regs_FRF_size; + coredynp.pipeline_duty_cycle = XML->sys.core[ithCore].pipeline_duty_cycle; + coredynp.total_cycles = XML->sys.core[ithCore].total_cycles; + coredynp.busy_cycles = XML->sys.core[ithCore].busy_cycles; + coredynp.idle_cycles = XML->sys.core[ithCore].idle_cycles; + + // Max power duty cycle for peak power estimation + // if (coredynp.core_ty==OOO) + // { + // coredynp.IFU_duty_cycle = 1; + // coredynp.LSU_duty_cycle = 1; + // coredynp.MemManU_I_duty_cycle =1; + // coredynp.MemManU_D_duty_cycle =1; + // coredynp.ALU_duty_cycle =1; + // coredynp.MUL_duty_cycle =1; + // coredynp.FPU_duty_cycle =1; + // coredynp.ALU_cdb_duty_cycle =1; + // coredynp.MUL_cdb_duty_cycle =1; + // coredynp.FPU_cdb_duty_cycle =1; + // } + // else + // { + coredynp.IFU_duty_cycle = XML->sys.core[ithCore].IFU_duty_cycle; + coredynp.BR_duty_cycle = XML->sys.core[ithCore].BR_duty_cycle; + coredynp.LSU_duty_cycle = XML->sys.core[ithCore].LSU_duty_cycle; + coredynp.MemManU_I_duty_cycle = XML->sys.core[ithCore].MemManU_I_duty_cycle; + coredynp.MemManU_D_duty_cycle = XML->sys.core[ithCore].MemManU_D_duty_cycle; + coredynp.ALU_duty_cycle = XML->sys.core[ithCore].ALU_duty_cycle; + coredynp.MUL_duty_cycle = XML->sys.core[ithCore].MUL_duty_cycle; + coredynp.FPU_duty_cycle = XML->sys.core[ithCore].FPU_duty_cycle; + coredynp.ALU_cdb_duty_cycle = XML->sys.core[ithCore].ALU_cdb_duty_cycle; + coredynp.MUL_cdb_duty_cycle = XML->sys.core[ithCore].MUL_cdb_duty_cycle; + coredynp.FPU_cdb_duty_cycle = XML->sys.core[ithCore].FPU_cdb_duty_cycle; + // } + + if (!(coredynp.core_ty == OOO) || (coredynp.core_ty == Inorder)) { + cout << "Invalid Core Type" << endl; + exit(0); + } + // if (coredynp.core_ty==OOO) + // { + // cout<<"OOO processor models are being updated and will be + // available in next release"<sys.core[ithCore].phy_Regs_IRF_size))); + coredynp.phy_freg_width = + int(ceil(log2(XML->sys.core[ithCore].phy_Regs_FRF_size))); + coredynp.num_ifreelist_entries = coredynp.num_IRF_entry = + XML->sys.core[ithCore].phy_Regs_IRF_size; + coredynp.num_ffreelist_entries = coredynp.num_FRF_entry = + XML->sys.core[ithCore].phy_Regs_FRF_size; + } + else if (coredynp.scheu_ty == + ReservationStation) { // ROB serves as Phy RF in RS based OOO + coredynp.phy_ireg_width = + int(ceil(log2(XML->sys.core[ithCore].ROB_size))); + coredynp.phy_freg_width = + int(ceil(log2(XML->sys.core[ithCore].ROB_size))); + coredynp.num_ifreelist_entries = XML->sys.core[ithCore].ROB_size; + coredynp.num_ffreelist_entries = XML->sys.core[ithCore].ROB_size; + } + } + + int GC_count = + XML->sys.core[ithCore].checkpoint_depth; // best check pointing entries + // for a 4~8 issue OOO should be + // 8~48;See TR for reference. + if (coredynp.rm_ty == RAMbased) { + coredynp.globalCheckpoint = + GC_count > 4 ? 4 : GC_count; // RAM-based RAT cannot have more than 4 + // GCs; see "a power-aware hybrid ram-cam + // renaming mechanism for fast recovery" + } + else if (coredynp.rm_ty == CAMbased) { + coredynp.globalCheckpoint = GC_count < 1 ? 1 : GC_count; + } + + coredynp.perThreadState = 8; + coredynp.instruction_length = 32; + coredynp.clockRate = XML->sys.core[ithCore].clock_rate; + coredynp.clockRate *= 1e6; + coredynp.regWindowing = (XML->sys.core[ithCore].register_windows_size > 0 && + coredynp.core_ty == Inorder) + ? true + : false; + coredynp.executionTime = XML->sys.total_cycles / coredynp.clockRate; + set_pppm(coredynp.pppm_lkg_multhread, 0, coredynp.num_hthreads, + coredynp.num_hthreads, 0); + + // does not care device types, since all core device types are set at sys. + // level + if (coredynp.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = coredynp.vdd; + interface_ip.lop_Vdd = coredynp.vdd; + interface_ip.lstp_Vdd = coredynp.vdd; + } + + if (coredynp.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = coredynp.power_gating_vcc; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/core.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/core.h new file mode 100644 index 0000000000..eea0b173fe --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/core.h @@ -0,0 +1,264 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef CORE_H_ +#define CORE_H_ + +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/parameter.h" +#include "interconnect.h" +#include "logic.h" +#include "sharedcache.h" + +using namespace cacti; + +class BranchPredictor : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + ArrayST *globalBPT; + ArrayST *localBPT; + ArrayST *L1_localBPT; + ArrayST *L2_localBPT; + ArrayST *chooser; + ArrayST *RAS; + bool exist; + + BranchPredictor(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exsit = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~BranchPredictor(); +}; + +class InstFetchU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + enum Cache_policy cache_p; + InstCache icache; + ArrayST *IB; + ArrayST *BTB; + BranchPredictor *BPT; + inst_decoder *ID_inst; + inst_decoder *ID_operand; + inst_decoder *ID_misc; + bool exist; + + InstFetchU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exsit = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~InstFetchU(); +}; + +class SchedulerU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double Iw_height, fp_Iw_height, ROB_height; + ArrayST *int_inst_window; + ArrayST *fp_inst_window; + ArrayST *ROB; + selection_logic *instruction_selection; + bool exist; + + SchedulerU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~SchedulerU(); +}; + +class RENAMINGU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + double clockRate, executionTime; + CoreDynParam coredynp; + ArrayST *iFRAT; + ArrayST *fFRAT; + ArrayST *iRRAT; + ArrayST *fRRAT; + ArrayST *ifreeL; + ArrayST *ffreeL; + dep_resource_conflict_check *idcl; + dep_resource_conflict_check *fdcl; + ArrayST *RAHT; // register alias history table Used to store GC + bool exist; + + RENAMINGU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~RENAMINGU(); +}; + +class LoadStoreU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + enum Cache_policy cache_p; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double lsq_height; + DataCache dcache; + ArrayST *LSQ; // it is actually the store queue but for inorder processors it + // serves as both loadQ and StoreQ + ArrayST *LoadQ; + bool exist; + + LoadStoreU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~LoadStoreU(); +}; + +class MemManU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + ArrayST *itlb; + ArrayST *dtlb; + bool exist; + + MemManU(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MemManU(); +}; + +class RegFU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double int_regfile_height, fp_regfile_height; + ArrayST *IRF; + ArrayST *FRF; + ArrayST *RFWIN; + bool exist; + + RegFU(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~RegFU(); +}; + +class EXECU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double lsq_height; + CoreDynParam coredynp; + RegFU *rfu; + SchedulerU *scheu; + FunctionalUnit *fp_u; + FunctionalUnit *exeu; + FunctionalUnit *mul; + interconnect *int_bypass; + interconnect *intTagBypass; + interconnect *int_mul_bypass; + interconnect *intTag_mul_Bypass; + interconnect *fp_bypass; + interconnect *fpTagBypass; + + Component bypass; + bool exist; + + EXECU(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, + double lsq_height_, const CoreDynParam &dyn_p_, bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~EXECU(); +}; + +class Core : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + InstFetchU *ifu; + LoadStoreU *lsu; + MemManU *mmu; + EXECU *exu; + RENAMINGU *rnu; + Pipeline *corepipe; + UndiffCore *undiffCore; + SharedCache *l2cache; + CoreDynParam coredynp; + // full_decoder inst_decoder; + // clock_network clockNetwork; + Core(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_); + void set_core_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~Core(); +}; + +#endif /* CORE_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/globalvar.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/globalvar.h new file mode 100644 index 0000000000..e0b76c2c6e --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/globalvar.h @@ -0,0 +1,43 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef GLOBALVAR_H_ +#define GLOBALVAR_H_ + +#ifdef GLOBALVAR +#define EXTERN +#else +#define EXTERN extern +#endif + +EXTERN bool opt_for_clk; + +#endif /* GLOBALVAR_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/interconnect.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/interconnect.cc new file mode 100644 index 0000000000..82d2a49689 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/interconnect.cc @@ -0,0 +1,209 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "interconnect.h" +#include +#include +#include "cacti/wire.h" +#include "globalvar.h" + +interconnect::interconnect(string name_, enum Device_ty device_ty_, + double base_w, double base_h, int data_w, double len, + const InputParameter *configure_interface, + int start_wiring_level_, bool pipelinable_, + double route_over_perc_, bool opt_local_, + enum Core_type core_ty_, enum Wire_type wire_model, + double width_s, double space_s, + TechnologyParameter::DeviceType *dt) + : name(name_), + device_ty(device_ty_), + in_rise_time(0), + out_rise_time(0), + base_width(base_w), + base_height(base_h), + data_width(data_w), + wt(wire_model), + width_scaling(width_s), + space_scaling(space_s), + start_wiring_level(start_wiring_level_), + length(len), + // interconnect_latency(1e-12), + // interconnect_throughput(1e-12), + opt_local(opt_local_), + core_ty(core_ty_), + pipelinable(pipelinable_), + route_over_perc(route_over_perc_), + deviceType(dt) { + wt = Global; + l_ip = *configure_interface; + local_result = init_interface(&l_ip); + + max_unpipelined_link_delay = 0; // TODO + min_w_nmos = g_tp.min_w_nmos_; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos; + + latency = l_ip.latency; + throughput = l_ip.throughput; + latency_overflow = false; + throughput_overflow = false; + + /* + * TODO: Add wiring option from semi-global to global automatically + * And directly jump to global if semi-global cannot satisfy timing + * Fat wires only available for global wires, thus + * if signal wiring layer starts from semi-global, + * the next layer up will be global, i.e., semi-global does + * not have fat wires. + */ + if (pipelinable == false) + // Non-pipelinable wires, such as bypass logic, care latency + { + compute(); + if (opt_for_clk && opt_local) { + while (delay > latency && width_scaling < 3.0) { + width_scaling *= 2; + space_scaling *= 2; + Wire winit(width_scaling, space_scaling); + compute(); + } + if (delay > latency) { + latency_overflow = true; + } + } + } + else // Pipelinable wires, such as bus, does not care latency but throughput + { + /* + * TODO: Add pipe regs power, area, and timing; + * Pipelinable wires optimize latency first. + */ + compute(); + if (opt_for_clk && opt_local) { + while (delay > throughput && width_scaling < 3.0) { + width_scaling *= 2; + space_scaling *= 2; + Wire winit(width_scaling, space_scaling); + compute(); + } + if (delay > throughput) + // insert pipeline stages + { + num_pipe_stages = (int)ceil(delay / throughput); + assert(num_pipe_stages > 0); + delay = delay / num_pipe_stages + num_pipe_stages * 0.05 * delay; + } + } + } + + power_bit = power; + power.readOp.dynamic *= data_width; + power.readOp.leakage *= data_width; + power.readOp.gate_leakage *= data_width; + area.set_area(area.get_area() * data_width); + no_device_under_wire_area.h *= data_width; + + if (latency_overflow == true) + cout << "Warning: " << name + << " wire structure cannot satisfy latency constraint." << endl; + + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + double pg_reduction = power_gating_leakage_reduction(false); // + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + + if (pipelinable) // Only global wires has the option to choose whether + // routing over or not + area.set_area(area.get_area() * route_over_perc + + no_device_under_wire_area.get_area() * (1 - route_over_perc)); + + // Wire wreset(); +} + +void interconnect::compute() { + Wire *wtemp1 = 0; + wtemp1 = new Wire(wt, length, 1, width_scaling, space_scaling); + delay = wtemp1->delay; + power.readOp.dynamic = wtemp1->power.readOp.dynamic; + power.readOp.leakage = wtemp1->power.readOp.leakage; + power.readOp.gate_leakage = wtemp1->power.readOp.gate_leakage; + + area.set_area(wtemp1->area.get_area()); + no_device_under_wire_area.h = (wtemp1->wire_width + wtemp1->wire_spacing); + no_device_under_wire_area.w = length; + + if (wtemp1) + delete wtemp1; +} + +void interconnect::leakage_feedback( + double temperature) // TODO: add code for processing power gating +{ + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + uca_org_t init_result = init_interface(&l_ip); // init_result is dummy + + compute(); + + power_bit = power; + power.readOp.dynamic *= data_width; + power.readOp.leakage *= data_width; + power.readOp.gate_leakage *= data_width; + + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/interconnect.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/interconnect.h new file mode 100644 index 0000000000..9f3d14f3f7 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/interconnect.h @@ -0,0 +1,101 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __INTERCONNECT_H__ +#define __INTERCONNECT_H__ + +#include "assert.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/cacti_interface.h" +#include "cacti/component.h" +#include "cacti/parameter.h" +#include "cacti/subarray.h" +#include "cacti/wire.h" + +// leakge power includes entire htree in a bank (when uca_tree == false) +// leakge power includes only part to one bank when uca_tree == true +using namespace cacti; + +class interconnect : public Component { + public: + interconnect(string name_, enum Device_ty device_ty_, double base_w, + double base_h, int data_w, double len, + const InputParameter *configure_interface, + int start_wiring_level_, bool pipelinable_ = false, + double route_over_perc_ = 0.5, bool opt_local_ = true, + enum Core_type core_ty_ = Inorder, + enum Wire_type wire_model = Global, double width_s = 1.0, + double space_s = 1.0, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + + ~interconnect(){}; + + void compute(); + string name; + enum Device_ty device_ty; + double in_rise_time, out_rise_time; + InputParameter l_ip; + uca_org_t local_result; + Area no_device_under_wire_area; + void set_in_rise_time(double rt) { in_rise_time = rt; } + + void leakage_feedback(double temperature); + double max_unpipelined_link_delay; + powerDef power_bit; + + double wire_bw; + double init_wire_bw; // bus width at root + double base_width; + double base_height; + int data_width; + enum Wire_type wt; + double width_scaling, space_scaling; + int start_wiring_level; + double length; + double min_w_nmos; + double min_w_pmos; + double latency, throughput; + bool latency_overflow; + bool throughput_overflow; + double interconnect_latency; + double interconnect_throughput; + bool opt_local; + enum Core_type core_ty; + bool pipelinable; + double route_over_perc; + int num_pipe_stages; + + private: + TechnologyParameter::DeviceType *deviceType; +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/iocontrollers.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/iocontrollers.cc new file mode 100644 index 0000000000..e1e98a7d21 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/iocontrollers.cc @@ -0,0 +1,602 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#include "iocontrollers.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +#include "logic.h" + +/* +SUN Niagara 2 I/O power analysis: +total signal bits: 711 +Total FBDIMM bits: (14+10)*2*8= 384 +PCIe bits: (8 + 8)*2 = 32 +10Gb NIC: (4*2+4*2)*2 = 32 +Debug I/Os: 168 +Other I/Os: 711- 32-32 - 384 - 168 = 95 + +According to "Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC +Server on a Chip" 90% of I/Os are SerDers (the calucaltion is +384+64/(711-168)=83% about the same as the 90% reported in the paper) +--> around 80Pins are common I/Os. +Common I/Os consumes 71mW/Gb/s according to Cadence ChipEstimate @65nm +Niagara 2 I/O clock is 1/4 of core clock. --> 87pin (<--((711-168)*17%)) * +71mW/Gb/s *0.25*1.4Ghz = 2.17W + +Total dynamic power of FBDIMM, NIC, PCIe = 84*0.132 + 84*0.049*0.132 = 11.14 +- 2.17 = 8.98 Further, if assuming I/O logic power is about 50% of I/Os then +Total energy of FBDIMM, NIC, PCIe = 11.14 - 2.17*1.5 = 7.89 + */ + +/* + * A bug in Cadence ChipEstimator: After update the clock rate in the clock tab, + * a user need to re-select the IP clock (the same clk) and then click Estimate. + * if not reselect the new clock rate may not be propogate into the IPs. + * + */ + +NIUController::NIUController(ParseXML *XML_interface, + InputParameter *interface_ip_) + : XML(XML_interface), interface_ip(*interface_ip_) { + double frontend_area; + // double phy_area; + double mac_area; + double SerDer_area; + double frontend_dyn; + double mac_dyn; + double SerDer_dyn; + double frontend_gates; + double mac_gates; + // double SerDer_gates = 0.; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing; + double PMOS_sizing; + + set_niu_param(); + local_result = init_interface(&interface_ip); + + if (niup.type == 0) // high performance NIU + { + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate using 65nm. + mac_area = (1.53 + 0.3) / 2 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2, ISSCC "An + // 800mW 10Gb Ethernet Transceiver in 0.13μm CMOS" and"A 1.2-V-Only 900-mW + // 10 Gb Ethernet Transceiver and XAUI Interface With Robust VCO Tuning + // Technique" Frontend is PCS + frontend_area = (9.8 + (6 + 18) * 65 / 130 * 65 / 130) / 3 * + (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate hard IP @65nm. SerDer is very hard to scale + SerDer_area = (1.39 + 0.36) * (interface_ip.F_sz_um / + 0.065); //* (interface_ip.F_sz_um/0.065); + // phy_area = frontend_area + SerDer_area; + // total area + area.set_area((mac_area + frontend_area + SerDer_area) * 1e6); + // Power + // Cadence ChipEstimate using 65nm (mac, front_end are all energy. E=P*T = + // P/F = 1.37/1Ghz = 1.37e-9); + mac_dyn = 2.19e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // //2.19W@1GHz fully active + // according to Cadence + // ChipEstimate @65nm + // Cadence ChipEstimate using 65nm soft IP; + frontend_dyn = 0.27e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // according to "A 100mW 9.6Gb/s Transceiver in 90nm CMOS..." ISSCC 2006 + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 10 * sqrt(interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2; + SerDer_dyn /= + niup.clockRate; // covert to energy per clock cycle of whole NIU + + // Cadence ChipEstimate using 65nm + mac_gates = 111700; + frontend_gates = 320000; + // SerDer_gates = 200000; + NMOS_sizing = 5 * g_tp.min_w_nmos_; + PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + else { // Low power implementations are mostly from Cadence ChipEstimator; + // Ignore the multiple IP effect + // ---When there are multiple IP (same kind or not) selected, Cadence + // ChipEstimator results are not a simple summation of all IPs. Ignore this + // effect + mac_area = + 0.24 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + frontend_area = + 0.1 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); // Frontend is the PCS layer + SerDer_area = + 0.35 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // Compare 130um implementation in "A 1.2-V-Only 900-mW 10 Gb Ethernet + // Transceiver and XAUI Interface With Robust VCO Tuning Technique" and the + // ChipEstimator XAUI PHY hard IP, confirm that even PHY can scale perfectly + // with the technology total area + area.set_area((mac_area + frontend_area + SerDer_area) * 1e6); + // Power + // Cadence ChipEstimate using 65nm (mac, front_end are all energy. E=P*T = + // P/F = 1.37/1Ghz = 1.37e-9); + mac_dyn = 1.257e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // //2.19W@1GHz fully active + // according to Cadence + // ChipEstimate @65nm + // Cadence ChipEstimate using 65nm soft IP; + frontend_dyn = 0.6e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // SerDer_dyn is power not energy, scaling from 216mw/10Gb/s @130nm + SerDer_dyn = 0.0216 * 10 * (interface_ip.F_sz_um / 0.13) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2; + SerDer_dyn /= + niup.clockRate; // covert to energy per clock cycle of whole NIU + + mac_gates = 111700; + frontend_gates = 52000; + // SerDer_gates = 199260; + + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + + power_t.readOp.dynamic = mac_dyn + frontend_dyn + SerDer_dyn; + power_t.readOp.leakage = + (mac_gates + frontend_gates + frontend_gates) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; + + power_t.readOp.gate_leakage = + (mac_gates + frontend_gates + frontend_gates) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W +} + +void NIUController::computeEnergy(bool is_tdp) { + if (is_tdp) { + power = power_t; + power.readOp.dynamic *= niup.duty_cycle; + } + else { + rt_power = power_t; + rt_power.readOp.dynamic *= niup.perc_load; + } +} + +void NIUController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "NIU:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * niup.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic * niup.clockRate + << " W" << endl; + cout << endl; + } + else { + } +} + +void NIUController::set_niu_param() { + niup.clockRate = XML->sys.niu.clockrate; + niup.clockRate *= 1e6; + niup.num_units = XML->sys.niu.number_units; + niup.duty_cycle = XML->sys.niu.duty_cycle; + niup.perc_load = XML->sys.niu.total_load_perc; + niup.type = XML->sys.niu.type; + if (XML->sys.niu.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.niu.vdd; + interface_ip.lop_Vdd = XML->sys.niu.vdd; + interface_ip.lstp_Vdd = XML->sys.niu.vdd; + } + + if (XML->sys.niu.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.niu.power_gating_vcc; + } + // niup.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); +} + +PCIeController::PCIeController(ParseXML *XML_interface, + InputParameter *interface_ip_) + : XML(XML_interface), interface_ip(*interface_ip_) { + // double frontend_area; + // double phy_area; + double ctrl_area; + double SerDer_area; + double ctrl_dyn; + // double frontend_dyn; + double SerDer_dyn; + double ctrl_gates; + // double frontend_gates; + double SerDer_gates = 0.; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing; + double PMOS_sizing; + + /* Assuming PCIe is bit-slice based architecture + * This is the reason for /8 in both area and power calculation + * to get per lane numbers + */ + set_pcie_param(); + local_result = init_interface(&interface_ip); + + if (pciep.type == 0) // high performance NIU + { + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate @ 65nm. + ctrl_area = (5.2 + 0.5) / 2 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2, and Cadence + // ChipEstimate @ 65nm. + // frontend_area = (5.2 + 0.1) / 2 * (interface_ip.F_sz_um / 0.065) * + // (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate hard IP @65nm. SerDer is very hard to scale + SerDer_area = (3.03 + 0.36) * (interface_ip.F_sz_um / + 0.065); //* (interface_ip.F_sz_um/0.065); + // phy_area = frontend_area + SerDer_area; + // total area + // Power + // Cadence ChipEstimate using 65nm the controller includes everything: the + // PHY, the data link and transaction layer + ctrl_dyn = 3.75e-9 / 8 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); + // //Cadence ChipEstimate using 65nm soft IP; + // frontend_dyn = + // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / + 1.2; // PCIe 2.0 max per lane speed is 4Gb/s + SerDer_dyn /= pciep.clockRate; // covert to energy per clock cycle + + // power_t.readOp.dynamic = (ctrl_dyn)*pciep.num_channels; + // Cadence ChipEstimate using 65nm + ctrl_gates = 900000 / 8 * pciep.num_channels; + // frontend_gates = 120000/8; + // SerDer_gates = 200000/8; + NMOS_sizing = 5 * g_tp.min_w_nmos_; + PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + else { + ctrl_area = + 0.412 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2, and Cadence + // ChipEstimate @ 65nm. + SerDer_area = + 0.36 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // total area + // Power + // Cadence ChipEstimate using 65nm the controller includes everything: the + // PHY, the data link and transaction layer + ctrl_dyn = 2.21e-9 / 8 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); + // //Cadence ChipEstimate using 65nm soft IP; + // frontend_dyn = + // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / + 1.2; // PCIe 2.0 max per lane speed is 4Gb/s + SerDer_dyn /= pciep.clockRate; // covert to energy per clock cycle + + // Cadence ChipEstimate using 65nm + ctrl_gates = 200000 / 8 * pciep.num_channels; + // frontend_gates = 120000/8; + SerDer_gates = 200000 / 8 * pciep.num_channels; + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + area.set_area(((ctrl_area + (pciep.withPHY ? SerDer_area : 0)) / 8 * + pciep.num_channels) * + 1e6); + power_t.readOp.dynamic = + (ctrl_dyn + (pciep.withPHY ? SerDer_dyn : 0)) * pciep.num_channels; + power_t.readOp.leakage = + (ctrl_gates + (pciep.withPHY ? SerDer_gates : 0)) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; + power_t.readOp.gate_leakage = + (ctrl_gates + (pciep.withPHY ? SerDer_gates : 0)) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W +} + +void PCIeController::computeEnergy(bool is_tdp) { + if (is_tdp) { + power = power_t; + power.readOp.dynamic *= pciep.duty_cycle; + } + else { + rt_power = power_t; + rt_power.readOp.dynamic *= pciep.perc_load; + } +} + +void PCIeController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "PCIe:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * pciep.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic * pciep.clockRate + << " W" << endl; + cout << endl; + } + else { + } +} + +void PCIeController::set_pcie_param() { + pciep.clockRate = XML->sys.pcie.clockrate; + pciep.clockRate *= 1e6; + pciep.num_units = XML->sys.pcie.number_units; + pciep.num_channels = XML->sys.pcie.num_channels; + pciep.duty_cycle = XML->sys.pcie.duty_cycle; + pciep.perc_load = XML->sys.pcie.total_load_perc; + pciep.type = XML->sys.pcie.type; + pciep.withPHY = XML->sys.pcie.withPHY; + + if (XML->sys.pcie.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.pcie.vdd; + interface_ip.lop_Vdd = XML->sys.pcie.vdd; + interface_ip.lstp_Vdd = XML->sys.pcie.vdd; + } + + if (XML->sys.pcie.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.pcie.power_gating_vcc; + } + // pciep.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); +} + +FlashController::FlashController(ParseXML *XML_interface, + InputParameter *interface_ip_) + : XML(XML_interface), interface_ip(*interface_ip_) { + // double frontend_area; + // double phy_area; + double ctrl_area; + double SerDer_area; + double ctrl_dyn; + // double frontend_dyn; + double SerDer_dyn; + double ctrl_gates; + // double frontend_gates; + double SerDer_gates = 0.; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing; + double PMOS_sizing; + + /* Assuming PCIe is bit-slice based architecture + * This is the reason for /8 in both area and power calculation + * to get per lane numbers + */ + + set_fc_param(); + local_result = init_interface(&interface_ip); + if (fcp.type == 0) // high performance NIU + { + cout << "Current McPAT does not support high performance flash contorller " + "since even low power designs are enough for maintain throughput" + << endl; + exit(0); + NMOS_sizing = 5 * g_tp.min_w_nmos_; + PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + else { + ctrl_area = + 0.243 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // Area estimation based on Cadence ChipEstimate @ 65nm: NANDFLASH-CTRL from + // CAST + SerDer_area = 0.36 / 8 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // based On PCIe PHY TSMC65GP from Cadence ChipEstimate @ 65nm, it support + // 8x lanes with each lane speed up to 250MB/s (PCIe1.1x) This is already + // saturate the 200MB/s of the flash controller core above. + ctrl_gates = 129267; + SerDer_gates = 200000 / 8; + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + + // Power + // Cadence ChipEstimate using 65nm the controller 125mW for every 200MB/s + // This is power not energy! + ctrl_dyn = 0.125 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / 1.1 * + (interface_ip.F_sz_nm / 65.0); + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 1.6 * (interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2; + // max Per controller speed is 1.6Gb/s (200MB/s) + } + double number_channel = 1 + (fcp.num_channels - 1) * 0.2; + area.set_area((ctrl_area + (fcp.withPHY ? SerDer_area : 0)) * 1e6 * + number_channel); + power_t.readOp.dynamic = + (ctrl_dyn + (fcp.withPHY ? SerDer_dyn : 0)) * number_channel; + power_t.readOp.leakage = + ((ctrl_gates + (fcp.withPHY ? SerDer_gates : 0)) * number_channel) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + double pg_reduction = power_gating_leakage_reduction( + false); // array structure all retain state; + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; + power_t.readOp.gate_leakage = + ((ctrl_gates + (fcp.withPHY ? SerDer_gates : 0)) * number_channel) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W +} + +void FlashController::computeEnergy(bool is_tdp) { + if (is_tdp) { + power = power_t; + power.readOp.dynamic *= fcp.duty_cycle; + } + else { + rt_power = power_t; + rt_power.readOp.dynamic *= fcp.perc_load; + } +} + +void FlashController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "Flash Controller:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic << " W" + << endl; // no multiply of clock since this is power already + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic + << " W" << endl; + cout << endl; + } + else { + } +} + +void FlashController::set_fc_param() { + // fcp.clockRate = XML->sys.flashc.mc_clock; + // fcp.clockRate *= 1e6; + fcp.peakDataTransferRate = XML->sys.flashc.peak_transfer_rate; + fcp.num_channels = ceil(fcp.peakDataTransferRate / 200); + fcp.num_mcs = XML->sys.flashc.number_mcs; + fcp.duty_cycle = XML->sys.flashc.duty_cycle; + fcp.perc_load = XML->sys.flashc.total_load_perc; + fcp.type = XML->sys.flashc.type; + fcp.withPHY = XML->sys.flashc.withPHY; + // flashcp.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + if (XML->sys.flashc.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.flashc.vdd; + interface_ip.lop_Vdd = XML->sys.flashc.vdd; + interface_ip.lstp_Vdd = XML->sys.flashc.vdd; + } + if (XML->sys.flashc.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.flashc.power_gating_vcc; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/iocontrollers.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/iocontrollers.h new file mode 100644 index 0000000000..9f80cc48dc --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/iocontrollers.h @@ -0,0 +1,85 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#ifndef IOCONTROLLERS_H_ +#define IOCONTROLLERS_H_ + +#endif /* IOCONTROLLERS_H_ */ + +#include "XML_Parse.h" +#include "cacti/parameter.h" +//#include "io.h" +#include "array.h" +//#include "Undifferentiated_Core_Area.h" +#include +#include "basic_components.h" +using namespace cacti; + +class NIUController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + NIUParam niup; + powerDef power_t; + uca_org_t local_result; + NIUController(ParseXML *XML_interface, InputParameter *interface_ip_); + void set_niu_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~NIUController(){}; +}; + +class PCIeController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + PCIeParam pciep; + powerDef power_t; + uca_org_t local_result; + PCIeController(ParseXML *XML_interface, InputParameter *interface_ip_); + void set_pcie_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~PCIeController(){}; +}; + +class FlashController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + MCParam fcp; + powerDef power_t; + uca_org_t local_result; + FlashController(ParseXML *XML_interface, InputParameter *interface_ip_); + void set_fc_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~FlashController(){}; +}; diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/logic.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/logic.cc new file mode 100644 index 0000000000..e22c4d0d98 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/logic.cc @@ -0,0 +1,1370 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "logic.h" + +// selection_logic +selection_logic::selection_logic(bool _is_default, int win_entries_, + int issue_width_, + const InputParameter *configure_interface, + enum Device_ty device_ty_, + enum Core_type core_ty_) + // const ParseXML *_XML_interface) + : is_default(_is_default), + win_entries(win_entries_), + issue_width(issue_width_), + device_ty(device_ty_), + core_ty(core_ty_) { + // uca_org_t result2; + l_ip = *configure_interface; + local_result = init_interface(&l_ip); + // init_tech_params(l_ip.F_sz_um, false); + // win_entries=numIBEntries;//IQentries; + // issue_width=issueWidth; + selection_power(); + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void selection_logic::selection_power() { // based on cost effective + // superscalar processor TR pp27-31 + double Ctotal, Cor, Cpencode; + int num_arbiter; + double WSelORn, WSelORprequ, WSelPn, WSelPp, WSelEnn, WSelEnp; + + // TODO: the 0.8um process data is used. + WSelORn = + 12.5 * l_ip.F_sz_um; // this was 10 micron for the 0.8 micron process + WSelORprequ = + 50 * l_ip.F_sz_um; // this was 40 micron for the 0.8 micron process + WSelPn = 12.5 * l_ip.F_sz_um; // this was 10mcron for the 0.8 micron process + WSelPp = + 18.75 * l_ip.F_sz_um; // this was 15 micron for the 0.8 micron process + WSelEnn = 6.25 * l_ip.F_sz_um; // this was 5 micron for the 0.8 micron + // process + WSelEnp = + 12.5 * l_ip.F_sz_um; // this was 10 micron for the 0.8 micron process + + Ctotal = 0; + num_arbiter = 1; + while (win_entries > 4) { + win_entries = (int)ceil((double)win_entries / 4.0); + num_arbiter += win_entries; + } + // the 4-input OR logic to generate anyreq + Cor = 4 * drain_C_(WSelORn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelORprequ, PCH, 1, 1, g_tp.cell_h_def); + power.readOp.gate_leakage = + cmos_Ig_leakage(WSelORn, WSelORprequ, 4, nor) * g_tp.peri_global.Vdd; + + // The total capacity of the 4-bit priority encoder + Cpencode = + drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 1, 1, g_tp.cell_h_def) + + 2 * drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 2, 1, g_tp.cell_h_def) + + 3 * drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 3, 1, g_tp.cell_h_def) + + 4 * drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 4, 1, + g_tp.cell_h_def) + // precompute priority logic + 2 * 4 * gate_C(WSelEnn + WSelEnp, 20.0) + + 4 * drain_C_(WSelEnn, NCH, 1, 1, g_tp.cell_h_def) + + 2 * 4 * drain_C_(WSelEnp, PCH, 1, 1, g_tp.cell_h_def) + // enable logic + (2 * 4 + 2 * 3 + 2 * 2 + 2) * + gate_C(WSelPn + WSelPp, 10.0); // requests signal + + Ctotal += issue_width * num_arbiter * (Cor + Cpencode); + + power.readOp.dynamic = + Ctotal * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * + 2; // 2 means the abitration signal need to travel round trip + power.readOp.leakage = + issue_width * num_arbiter * + (cmos_Isub_leakage( + WSelPn, WSelPp, 2, + nor) /*approximate precompute with a nor gate*/ // grant1p + + cmos_Isub_leakage(WSelPn, WSelPp, 3, nor) // grant2p + + cmos_Isub_leakage(WSelPn, WSelPp, 4, nor) // grant3p + + cmos_Isub_leakage(WSelEnn, WSelEnp, 2, nor) * 4 // enable logic + + cmos_Isub_leakage(WSelEnn, WSelEnp, 1, inv) * 2 * + 3 // for each grant there are two inverters, there are 3 grant + // sIsubnals + ) * + g_tp.peri_global.Vdd; + power.readOp.gate_leakage = + issue_width * num_arbiter * + (cmos_Ig_leakage( + WSelPn, WSelPp, 2, + nor) /*approximate precompute with a nor gate*/ // grant1p + + cmos_Ig_leakage(WSelPn, WSelPp, 3, nor) // grant2p + + cmos_Ig_leakage(WSelPn, WSelPp, 4, nor) // grant3p + + cmos_Ig_leakage(WSelEnn, WSelEnp, 2, nor) * 4 // enable logic + + cmos_Ig_leakage(WSelEnn, WSelEnp, 1, inv) * 2 * + 3 // for each grant there are two inverters, there are 3 grant + // signals + ) * + g_tp.peri_global.Vdd; +} + +dep_resource_conflict_check::dep_resource_conflict_check( + const InputParameter *configure_interface, const CoreDynParam &dyn_p_, + int compare_bits_, bool _is_default) + : l_ip(*configure_interface), + coredynp(dyn_p_), + compare_bits(compare_bits_), + is_default(_is_default) { + Wcompn = 25 * l_ip.F_sz_um; // this was 20.0 micron for the 0.8 micron + // process + Wevalinvp = + 25 * l_ip.F_sz_um; // this was 20.0 micron for the 0.8 micron process + Wevalinvn = + 100 * l_ip.F_sz_um; // this was 80.0 mcron for the 0.8 micron process + Wcomppreequ = + 50 * l_ip.F_sz_um; // this was 40.0 micron for the 0.8 micron process + WNORn = 6.75 * l_ip.F_sz_um; // this was 5.4 micron for the 0.8 micron + // process + WNORp = + 38.125 * l_ip.F_sz_um; // this was 30.5 micron for the 0.8 micron process + + local_result = init_interface(&l_ip); + + if (coredynp.core_ty == Inorder) + compare_bits += 16 + 8 + 8; // TODO: opcode bits + log(shared resources) + + // REG TAG BITS-->opcode comparator + else + compare_bits += 16 + 8 + 8; + + conflict_check_power(); + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; +} + +void dep_resource_conflict_check::conflict_check_power() { + double Ctotal; + int num_comparators; + num_comparators = 3 * ((coredynp.decodeW) * (coredynp.decodeW) - + coredynp.decodeW); // 2(N*N-N) is used for source to + // dest comparison, (N*N-N) is used + // for dest to dest comparision. + // When decode-width ==1, no dcl logic + + Ctotal = num_comparators * compare_cap(); + // printf("%i,%s\n",XML_interface->sys.core[0].predictor.predictor_entries,XML_interface->sys.core[0].predictor.prediction_scheme); + + power.readOp.dynamic = + Ctotal * /*CLOCKRATE*/ g_tp.peri_global.Vdd * g_tp.peri_global.Vdd /*AF*/; + power.readOp.leakage = num_comparators * compare_bits * 2 * + simplified_nmos_leakage(Wcompn, false); + + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + power.readOp.gate_leakage = + num_comparators * compare_bits * 2 * cmos_Ig_leakage(Wcompn, 0, 2, nmos); + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +/* estimate comparator power consumption (this comparator is similar + to the tag-match structure in a CAM */ +double dep_resource_conflict_check::compare_cap() { + double c1, c2; + + WNORp = WNORp * compare_bits / + 2.0; // resize the big NOR gate at the DCL according to fan in. + /* bottom part of comparator */ + c2 = (compare_bits) * (drain_C_(Wcompn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(Wcompn, NCH, 2, 1, g_tp.cell_h_def)) + + drain_C_(Wevalinvp, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(Wevalinvn, NCH, 1, 1, g_tp.cell_h_def); + + /* top part of comparator */ + c1 = (compare_bits) * (drain_C_(Wcompn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(Wcompn, NCH, 2, 1, g_tp.cell_h_def) + + drain_C_(Wcomppreequ, NCH, 1, 1, g_tp.cell_h_def)) + + gate_C(WNORn + WNORp, 10.0) + + drain_C_(WNORp, NCH, 2, 1, g_tp.cell_h_def) + + compare_bits * drain_C_(WNORn, NCH, 2, 1, g_tp.cell_h_def); + return (c1 + c2); +} + +void dep_resource_conflict_check::leakage_feedback(double temperature) { + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + uca_org_t init_result = init_interface(&l_ip); // init_result is dummy + + // This is part of conflict_check_power() + int num_comparators = 3 * ((coredynp.decodeW) * (coredynp.decodeW) - + coredynp.decodeW); // 2(N*N-N) is used for source + // to dest comparison, (N*N-N) + // is used for dest to dest + // comparision. + power.readOp.leakage = num_comparators * compare_bits * 2 * + simplified_nmos_leakage(Wcompn, false); + + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + power.readOp.gate_leakage = + num_comparators * compare_bits * 2 * cmos_Ig_leakage(Wcompn, 0, 2, nmos); + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +// TODO: add inverter and transmission gate base DFF. + +DFFCell::DFFCell(bool _is_dram, double _WdecNANDn, double _WdecNANDp, + double _cell_load, const InputParameter *configure_interface) + : is_dram(_is_dram), + cell_load(_cell_load), + WdecNANDn(_WdecNANDn), + WdecNANDp(_WdecNANDp) { // this model is based on the NAND2 based DFF. + l_ip = *configure_interface; + // area.set_area(730*l_ip.F_sz_um*l_ip.F_sz_um); + area.set_area( + 5 * compute_gate_area(NAND, 2, WdecNANDn, WdecNANDp, g_tp.cell_h_def) + + compute_gate_area(NAND, 2, WdecNANDn, WdecNANDn, g_tp.cell_h_def)); +} + +double DFFCell::fpfp_node_cap(unsigned int fan_in, unsigned int fan_out) { + double Ctotal = 0; + // printf("WdecNANDn = %E\n", WdecNANDn); + + /* part 1: drain cap of NAND gate */ + Ctotal += drain_C_(WdecNANDn, NCH, 2, 1, g_tp.cell_h_def, is_dram) + + fan_in * drain_C_(WdecNANDp, PCH, 1, 1, g_tp.cell_h_def, is_dram); + + /* part 2: gate cap of NAND gates */ + Ctotal += fan_out * gate_C(WdecNANDn + WdecNANDp, 0, is_dram); + + return Ctotal; +} + +void DFFCell::compute_DFF_cell() { + double c1, c2, c3, c4, c5, c6; + /* node 5 and node 6 are identical to node 1 in capacitance */ + c1 = c5 = c6 = fpfp_node_cap(2, 1); + c2 = fpfp_node_cap(2, 3); + c3 = fpfp_node_cap(3, 2); + c4 = fpfp_node_cap(2, 2); + + // cap-load of the clock signal in each Dff, actually the clock signal only + // connected to one NAND2 + clock_cap = 2 * gate_C(WdecNANDn + WdecNANDp, 0, is_dram); + e_switch.readOp.dynamic += (c4 + c1 + c2 + c3 + c5 + c6 + 2 * cell_load) * + 0.5 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + ; + + /* no 1/2 for e_keep and e_clock because clock signal switches twice in one + * cycle */ + e_keep_1.readOp.dynamic += c3 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + e_keep_0.readOp.dynamic += c2 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + e_clock.readOp.dynamic += + clock_cap * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + ; + + /* static power */ + e_switch.readOp.leakage += + (cmos_Isub_leakage(WdecNANDn, WdecNANDp, 2, nand) * + 5 // 5 NAND2 and 1 NAND3 in a DFF + + cmos_Isub_leakage(WdecNANDn, WdecNANDn, 3, nand)) * + g_tp.peri_global.Vdd; + e_switch.readOp.gate_leakage += + (cmos_Ig_leakage(WdecNANDn, WdecNANDp, 2, nand) * + 5 // 5 NAND2 and 1 NAND3 in a DFF + + cmos_Ig_leakage(WdecNANDn, WdecNANDn, 3, nand)) * + g_tp.peri_global.Vdd; + // printf("leakage =%E\n",cmos_Ileak(1, is_dram) ); +} + +Pipeline::Pipeline(const InputParameter *configure_interface, + const CoreDynParam &dyn_p_, enum Device_ty device_ty_, + bool _is_core_pipeline, bool _is_default) + : l_ip(*configure_interface), + coredynp(dyn_p_), + device_ty(device_ty_), + is_core_pipeline(_is_core_pipeline), + is_default(_is_default), + num_piperegs(0.0) + +{ + local_result = init_interface(&l_ip); + if (!coredynp.Embedded) + process_ind = true; + else + process_ind = false; + WNANDn = + (process_ind) + ? 25 * l_ip.F_sz_um + : g_tp.min_w_nmos_; // this was 20 micron for the 0.8 micron process + WNANDp = (process_ind) + ? 37.5 * l_ip.F_sz_um + : g_tp.min_w_nmos_ * pmos_to_nmos_sz_ratio(); // this was 30 + // micron for the + // 0.8 micron + // process + load_per_pipeline_stage = 2 * gate_C(WNANDn + WNANDp, 0, false); + compute(); +} + +void Pipeline::compute() { + compute_stage_vector(); + DFFCell pipe_reg(false, WNANDn, WNANDp, load_per_pipeline_stage, &l_ip); + pipe_reg.compute_DFF_cell(); + + double clock_power_pipereg = num_piperegs * pipe_reg.e_clock.readOp.dynamic; + //******************pipeline power: currently, we average all the + // possibilities of the states of DFFs in the pipeline. A better way to do it + // is to consider the harming distance of two consecutive signals, However + // McPAT does not have plan to do this in near future as it focuses on worst + // case power. + double pipe_reg_power = + num_piperegs * + (pipe_reg.e_switch.readOp.dynamic + pipe_reg.e_keep_0.readOp.dynamic + + pipe_reg.e_keep_1.readOp.dynamic) / + 3 + + clock_power_pipereg; + double pipe_reg_leakage = num_piperegs * pipe_reg.e_switch.readOp.leakage; + double pipe_reg_gate_leakage = + num_piperegs * pipe_reg.e_switch.readOp.gate_leakage; + power.readOp.dynamic += pipe_reg_power; + power.readOp.leakage += pipe_reg_leakage; + power.readOp.gate_leakage += pipe_reg_gate_leakage; + area.set_area(num_piperegs * pipe_reg.area.get_area()); + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + double macro_layout_overhead = g_tp.macro_layout_overhead; + if (!coredynp.Embedded) + area.set_area(area.get_area() * macro_layout_overhead); +} + +void Pipeline::compute_stage_vector() { + double num_stages, tot_stage_vector, per_stage_vector; + int opcode_length = + coredynp.x86 ? coredynp.micro_opcode_length : coredynp.opcode_length; + // Hthread = thread_clock_gated? 1:num_thread; + + if (!is_core_pipeline) { + num_piperegs = l_ip.pipeline_stages * + l_ip.per_stage_vector; // The number of pipeline stages are + // calculated based on the achievable + // throughput and required throughput + } + else { + if (coredynp.core_ty == Inorder) { + /* assume 6 pipe stages and try to estimate bits per pipe stage */ + /* pipe stage 0/IF */ + num_piperegs += coredynp.pc_width * 2 * coredynp.num_hthreads; + /* pipe stage IF/ID */ + num_piperegs += coredynp.fetchW * + (coredynp.instruction_length + coredynp.pc_width) * + coredynp.num_hthreads; + /* pipe stage IF/ThreadSEL */ + if (coredynp.multithreaded) + num_piperegs += coredynp.num_hthreads * + coredynp.perThreadState; // 8 bit thread states + /* pipe stage ID/EXE */ + num_piperegs += coredynp.decodeW * + (coredynp.instruction_length + coredynp.pc_width + + pow(2.0, opcode_length) + 2 * coredynp.int_data_width) * + coredynp.num_hthreads; + /* pipe stage EXE/MEM */ + num_piperegs += + coredynp.issueW * + (3 * coredynp.arch_ireg_width + pow(2.0, opcode_length) + + 8 * 2 * coredynp.int_data_width /*+2*powers (2,reg_length)*/); + /* pipe stage MEM/WB the 2^opcode_length means the total decoded signal + * for the opcode*/ + num_piperegs += + coredynp.issueW * + (2 * coredynp.int_data_width + pow(2.0, opcode_length) + + 8 * 2 * coredynp.int_data_width /*+2*powers (2,reg_length)*/); + // /* pipe stage 5/6 */ + // num_piperegs += issueWidth*(data_width + powers + //(2,opcode_length)/*+2*powers (2,reg_length)*/); + // /* pipe stage 6/7 */ + // num_piperegs += issueWidth*(data_width + powers + //(2,opcode_length)/*+2*powers (2,reg_length)*/); + // /* pipe stage 7/8 */ + // num_piperegs += issueWidth*(data_width + powers + //(2,opcode_length)/**2*powers (2,reg_length)*/); + // /* assume 50% extra in control signals (rule of thumb) + //*/ + num_stages = 6; + } + else { + /* assume 12 stage pipe stages and try to estimate bits per pipe stage */ + /*OOO: Fetch, decode, rename, IssueQ, dispatch, regread, EXE, MEM, WB, CM + */ + + /* pipe stage 0/1F*/ + num_piperegs += + coredynp.pc_width * 2 * coredynp.num_hthreads; // PC and Next PC + /* pipe stage IF/ID */ + num_piperegs += + coredynp.fetchW * (coredynp.instruction_length + coredynp.pc_width) * + coredynp.num_hthreads; // PC is used to feed branch predictor in ID + /* pipe stage 1D/Renaming*/ + num_piperegs += + coredynp.decodeW * (coredynp.instruction_length + coredynp.pc_width) * + coredynp.num_hthreads; // PC is for branch exe in later stage. + /* pipe stage Renaming/wire_drive */ + num_piperegs += + coredynp.decodeW * (coredynp.instruction_length + coredynp.pc_width); + /* pipe stage Renaming/IssueQ */ + num_piperegs += coredynp.issueW * + (coredynp.instruction_length + coredynp.pc_width + + 3 * coredynp.phy_ireg_width) * + coredynp.num_hthreads; // 3*coredynp.phy_ireg_width means + // 2 sources and 1 dest + /* pipe stage IssueQ/Dispatch */ + num_piperegs += coredynp.issueW * (coredynp.instruction_length + + 3 * coredynp.phy_ireg_width); + /* pipe stage Dispatch/EXE */ + + num_piperegs += coredynp.issueW * + (3 * coredynp.phy_ireg_width + coredynp.pc_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); + /* 2^opcode_length means the total decoded signal for the opcode*/ + num_piperegs += coredynp.issueW * + (2 * coredynp.int_data_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); + /*2 source operands in EXE; Assume 2EXE stages* since we do not really + * distinguish OP*/ + num_piperegs += coredynp.issueW * + (2 * coredynp.int_data_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); + /* pipe stage EXE/MEM, data need to be read/write, address*/ + num_piperegs += + coredynp.issueW * + (coredynp.int_data_width + coredynp.v_address_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); // memory + // Opcode + // still need + // to be + // passed + /* pipe stage MEM/WB; result data, writeback regs */ + num_piperegs += + coredynp.issueW * (coredynp.int_data_width + coredynp.phy_ireg_width /* powers (2,opcode_length) + (2,opcode_length)+2*powers (2,reg_length)*/); + /* pipe stage WB/CM ; result data, regs need to be updated, address for + * resolve memory ops in ROB's top*/ + num_piperegs += + coredynp.commitW * + (coredynp.int_data_width + coredynp.v_address_width + coredynp.phy_ireg_width /*+ powers (2,opcode_length)*2*powers (2,reg_length)*/) * + coredynp.num_hthreads; + // if (multithreaded) + // { + // + // } + num_stages = 12; + } + + /* assume 50% extra in control registers and interrupt registers (rule of + * thumb) */ + num_piperegs = num_piperegs * 1.5; + tot_stage_vector = num_piperegs; + per_stage_vector = tot_stage_vector / num_stages; + + if (coredynp.core_ty == Inorder) { + if (coredynp.pipeline_stages > 6) + num_piperegs = per_stage_vector * coredynp.pipeline_stages; + } + else // OOO + { + if (coredynp.pipeline_stages > 12) + num_piperegs = per_stage_vector * coredynp.pipeline_stages; + } + } +} + +FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, + enum FU_type fu_type_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + fu_type(fu_type_) { + double area_t; //, leakage, gate_leakage; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + + // XML_interface=_XML_interface; + uca_org_t result2; + result2 = init_interface(&interface_ip); + if (XML->sys.Embedded) { + if (fu_type == FPU) { + num_fu = coredynp.num_fpus; + // area_t = 8.47*1e6*g_tp.scaling_factor.logic_scaling_co_eff;//this is + // um^2 + area_t = 4.47 * 1e6 * + (g_ip->F_sz_nm * g_ip->F_sz_nm / 90.0 / + 90.0); // this is um^2 The base number + // 4.47 contains both VFP and NEON processing unit, VFP is about 40% and + // NEON is about 60% + if (g_ip->F_sz_nm > 90) + area_t = 4.47 * 1e6 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage( + 5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + // energy = 0.3529/10*1e-9;//this is the energy(nJ) for a FP instruction + // in FPU usually it can have up to 20 cycles. + // base_energy = coredynp.core_ty==Inorder? 0: + // 89e-3*3; //W The base energy of ALU average numbers from Intel 4G and + // 773Mhz (Wattch) base_energy + //*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2); + base_energy = 0; + per_access_energy = + 1.15 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); // g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + // //This is per Hz energy(nJ) + // FPU power from Sandia's processor sizing tech report + FU_height = + (18667 * num_fu) * interface_ip.F_sz_um; // FPU from Sun's data + } + else if (fu_type == ALU) { + num_fu = coredynp.num_alus; + area_t = + 280 * 260 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + // base_energy = coredynp.core_ty==Inorder? + // 0:89e-3; //W The base energy of ALU average numbers from Intel 4G and + // 773Mhz (Wattch) base_energy + //*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2); + base_energy = 0; + per_access_energy = + 1.15 / 3 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ) + FU_height = (6222 * num_fu) * interface_ip.F_sz_um; // integer ALU + } + else if (fu_type == MUL) { + num_fu = coredynp.num_muls; + area_t = + 280 * 260 * 3 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + // base_energy = coredynp.core_ty==Inorder? + // 0:89e-3*2; //W The base energy of ALU average numbers from Intel 4G and + // 773Mhz (Wattch) base_energy + //*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2); + base_energy = 0; + per_access_energy = + 1.15 * 2 / 3 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ), coefficient based on Wattch + FU_height = (9334 * num_fu) * + interface_ip.F_sz_um; // divider/mul from Sun's data + } + else { + cout << "Unknown Functional Unit Type" << endl; + exit(0); + } + per_access_energy *= 0.5; // According to ARM data embedded processor has + // much lower per acc energy + } + else { + if (fu_type == FPU) { + num_fu = coredynp.num_fpus; + // area_t = 8.47*1e6*g_tp.scaling_factor.logic_scaling_co_eff;//this is + // um^2 + area_t = 8.47 * 1e6 * + (g_ip->F_sz_nm * g_ip->F_sz_nm / 90.0 / 90.0); // this is um^2 + if (g_ip->F_sz_nm > 90) + area_t = 8.47 * 1e6 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage( + 5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + // energy = 0.3529/10*1e-9;//this is the energy(nJ) for a FP instruction + // in FPU usually it can have up to 20 cycles. + base_energy = + coredynp.core_ty == Inorder ? 0 : 89e-3 * 3; // W The base energy of + // ALU average numbers + // from Intel 4G and + // 773Mhz (Wattch) + base_energy *= (g_tp.peri_global.Vdd * g_tp.peri_global.Vdd / 1.2 / 1.2); + per_access_energy = + 1.15 * 3 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); // g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + // //This is per op energy(nJ) + FU_height = + (38667 * num_fu) * interface_ip.F_sz_um; // FPU from Sun's data + } + else if (fu_type == ALU) { + num_fu = coredynp.num_alus; + area_t = + 280 * 260 * 2 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + base_energy = coredynp.core_ty == Inorder + ? 0 + : 89e-3; // W The base energy of ALU + // average numbers from Intel + // 4G and 773Mhz (Wattch) + base_energy *= (g_tp.peri_global.Vdd * g_tp.peri_global.Vdd / 1.2 / 1.2); + per_access_energy = + 1.15 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ) + FU_height = (6222 * num_fu) * interface_ip.F_sz_um; // integer ALU + } + else if (fu_type == MUL) { + num_fu = coredynp.num_muls; + area_t = + 280 * 260 * 2 * 3 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + base_energy = + coredynp.core_ty == Inorder ? 0 : 89e-3 * 2; // W The base energy of + // ALU average numbers + // from Intel 4G and + // 773Mhz (Wattch) + base_energy *= (g_tp.peri_global.Vdd * g_tp.peri_global.Vdd / 1.2 / 1.2); + per_access_energy = + 1.15 * 2 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ), coefficient based on Wattch + FU_height = (9334 * num_fu) * + interface_ip.F_sz_um; // divider/mul from Sun's data + } + else { + cout << "Unknown Functional Unit Type" << endl; + exit(0); + } + } + // IEXEU, simple ALU and FPU + // double C_ALU, C_EXEU, C_FPU; //Lum Equivalent capacitance of IEXEU and + // FPU. Based on Intel and Sun 90nm process fabracation. + // + // C_ALU = 0.025e-9;//F + // C_EXEU = 0.05e-9; //F + // C_FPU = 0.35e-9;//F + area.set_area(area_t * num_fu); + leakage *= num_fu; + gate_leakage *= num_fu; + double macro_layout_overhead = g_tp.macro_layout_overhead; + // if (!XML->sys.Embedded) + area.set_area(area.get_area() * macro_layout_overhead); +} + +void FunctionalUnit::computeEnergy(bool is_tdp) { + double pppm_t[4] = {1, 1, 1, 1}; + double FU_duty_cycle = 0.; + if (is_tdp) { + set_pppm(pppm_t, 2, 2, 2, 2); // 2 means two source operands needs to be + // passed for each int instruction. + if (fu_type == FPU) { + stats_t.readAc.access = num_fu; + tdp_stats = stats_t; + FU_duty_cycle = coredynp.FPU_duty_cycle; + } + else if (fu_type == ALU) { + stats_t.readAc.access = 1 * num_fu; + tdp_stats = stats_t; + FU_duty_cycle = coredynp.ALU_duty_cycle; + } + else if (fu_type == MUL) { + stats_t.readAc.access = num_fu; + tdp_stats = stats_t; + FU_duty_cycle = coredynp.MUL_duty_cycle; + } + + // power.readOp.dynamic = base_energy/clockRate + + // energy*stats_t.readAc.access; + power.readOp.dynamic = + per_access_energy * stats_t.readAc.access + base_energy / clockRate; + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation * FU_duty_cycle; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + power.readOp.leakage = leakage; + power.readOp.gate_leakage = gate_leakage; + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + } + else { + if (fu_type == FPU) { + stats_t.readAc.access = XML->sys.core[ithCore].fpu_accesses; + rtp_stats = stats_t; + } + else if (fu_type == ALU) { + stats_t.readAc.access = XML->sys.core[ithCore].ialu_accesses; + rtp_stats = stats_t; + } + else if (fu_type == MUL) { + stats_t.readAc.access = XML->sys.core[ithCore].mul_accesses; + rtp_stats = stats_t; + } + + // rt_power.readOp.dynamic = base_energy*executionTime + + // energy*stats_t.readAc.access; + rt_power.readOp.dynamic = + per_access_energy * stats_t.readAc.access + base_energy * executionTime; + double sckRation = g_tp.sckt_co_eff; + rt_power.readOp.dynamic *= sckRation; + rt_power.writeOp.dynamic *= sckRation; + rt_power.searchOp.dynamic *= sckRation; + } +} + +void FunctionalUnit::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + // cout << indent_str_next << "Results Broadcast Bus Area = " << + // bypass->area.get_area() *1e-6 << " mm^2" << endl; + if (is_tdp) { + if (fu_type == FPU) { + cout << indent_str + << "Floating Point Units (FPUs) (Count: " << coredynp.num_fpus + << " ):" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= " << power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + else if (fu_type == ALU) { + cout << indent_str << "Integer ALUs (Count: " << coredynp.num_alus + << " ):" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= " << power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + else if (fu_type == MUL) { + cout << indent_str + << "Complex ALUs (Mul/Div) (Count: " << coredynp.num_muls + << " ):" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= " << power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + } + else { + } +} + +void FunctionalUnit::leakage_feedback(double temperature) { + // Update the temperature and initialize the global interfaces. + interface_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + + uca_org_t init_result = + init_interface(&interface_ip); // init_result is dummy + + // This is part of FunctionalUnit() + double area_t, leakage, gate_leakage; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + + if (fu_type == FPU) { + area_t = 4.47 * 1e6 * + (g_ip->F_sz_nm * g_ip->F_sz_nm / 90.0 / + 90.0); // this is um^2 The base number + if (g_ip->F_sz_nm > 90) + area_t = 4.47 * 1e6 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + } + else if (fu_type == ALU) { + area_t = + 280 * 260 * 2 * num_fu * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; + } + else if (fu_type == MUL) { + area_t = + 280 * 260 * 2 * 3 * num_fu * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; + } + else { + cout << "Unknown Functional Unit Type" << endl; + exit(1); + } + + power.readOp.leakage = leakage * num_fu; + power.readOp.gate_leakage = gate_leakage * num_fu; + power.readOp.longer_channel_leakage = + longer_channel_device_reduction(Core_device, coredynp.core_ty) * + power.readOp.leakage; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; +} + +UndiffCore::UndiffCore(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_, bool embedded_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + core_ty(coredynp.core_ty), + embedded(XML->sys.Embedded), + pipeline_stage(coredynp.pipeline_stages), + num_hthreads(coredynp.num_hthreads), + issue_width(coredynp.issueW), + exist(exist_) +// is_default(_is_default) +{ + if (!exist) + return; + double undifferentiated_core = 0; + double core_tx_density = 0; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double undifferentiated_core_coe; + // XML_interface=_XML_interface; + uca_org_t result2; + result2 = init_interface(&interface_ip); + + // Compute undifferentiated core area at 90nm. + if (embedded == false) { + // Based on the results of polynomial/log curve fitting based on + // undifferentiated core of Niagara, Niagara2, Merom, Penyrn, Prescott, + // Opteron die measurements + if (core_ty == OOO) { + // undifferentiated_core = (0.0764*pipeline_stage*pipeline_stage + // -2.3685*pipeline_stage + 10.405);//OOO + undifferentiated_core = (3.57 * log(pipeline_stage) - 1.2643) > 0 + ? (3.57 * log(pipeline_stage) - 1.2643) + : 0; + } + else if (core_ty == Inorder) { + // undifferentiated_core = (0.1238*pipeline_stage + 7.2572)*0.9;//inorder + undifferentiated_core = (-2.19 * log(pipeline_stage) + 6.55) > 0 + ? (-2.19 * log(pipeline_stage) + 6.55) + : 0; + } + else { + cout << "invalid core type" << endl; + exit(0); + } + undifferentiated_core *= (1 + logtwo(num_hthreads) * 0.0716); + } + else { + // Based on the results in paper "parametrized processor models" Sandia Labs + if (XML->sys.opt_clockrate) + undifferentiated_core_coe = 0.05; + else + undifferentiated_core_coe = 0; + undifferentiated_core = + (0.4109 * pipeline_stage - 0.776) * undifferentiated_core_coe; + undifferentiated_core *= (1 + logtwo(num_hthreads) * 0.0426); + } + + undifferentiated_core *= g_tp.scaling_factor.logic_scaling_co_eff * + 1e6; // change from mm^2 to um^2 + core_tx_density = g_tp.scaling_factor.core_tx_density; + // undifferentiated_core = 3*1e6; + // undifferentiated_core *= + // g_tp.scaling_factor.logic_scaling_co_eff;//(g_ip->F_sz_um*g_ip->F_sz_um/0.09/0.09)*; + power.readOp.leakage = + undifferentiated_core * + (core_tx_density)*cmos_Isub_leakage( + 5 * g_tp.min_w_nmos_, 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd; // unit W + power.readOp.gate_leakage = + undifferentiated_core * + (core_tx_density)*cmos_Ig_leakage( + 5 * g_tp.min_w_nmos_, 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd; + + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + + area.set_area(undifferentiated_core); + + scktRatio = g_tp.sckt_co_eff; + power.readOp.dynamic *= scktRatio; + power.writeOp.dynamic *= scktRatio; + power.searchOp.dynamic *= scktRatio; + macro_PR_overhead = g_tp.macro_layout_overhead; + area.set_area(area.get_area() * macro_PR_overhead); + + // double vt=g_tp.peri_global.Vth; + // double velocity_index=1.1; + // double c_in=gate_C(g_tp.min_w_nmos_, + // g_tp.min_w_nmos_*pmos_to_nmos_sizing_r , 0.0, false); double + // c_out= drain_C_(g_tp.min_w_nmos_, NCH, 2, 1, g_tp.cell_h_def, false) + + // drain_C_(g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, PCH, 1, 1, + // g_tp.cell_h_def, false) + c_in; double w_nmos=g_tp.min_w_nmos_; + // double w_pmos=g_tp.min_w_nmos_*pmos_to_nmos_sizing_r; + // double i_on_n=1.0; + // double i_on_p=1.0; + // double i_on_n_in=1.0; + // double i_on_p_in=1; + // double vdd=g_tp.peri_global.Vdd; + + // power.readOp.sc=shortcircuit_simple(vt, velocity_index, c_in, + // c_out, w_nmos,w_pmos, i_on_n, i_on_p,i_on_n_in, i_on_p_in, vdd); + // power.readOp.dynamic=c_out*vdd*vdd/2; + + // cout<sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "UndiffCore:" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage = " << + // power.readOp.leakage <<" W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + // cout << indent_str_next << "Runtime Dynamic = " << + // rt_power.readOp.dynamic/executionTime << " W" << endl; + cout << endl; + } + else { + cout << indent_str << "UndiffCore:" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " << power.readOp.leakage + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + // cout << indent_str_next << "Runtime Dynamic = " << + // rt_power.readOp.dynamic/executionTime << " W" << endl; + cout << endl; + } +} + +inst_decoder::inst_decoder(bool _is_default, + const InputParameter *configure_interface, + int opcode_length_, int num_decoders_, bool x86_, + enum Device_ty device_ty_, enum Core_type core_ty_) + : is_default(_is_default), + opcode_length(opcode_length_), + num_decoders(num_decoders_), + x86(x86_), + device_ty(device_ty_), + core_ty(core_ty_) { + /* + * Instruction decoder is different from n to 2^n decoders + * that are commonly used in row decoders in memory arrays. + * The RISC instruction decoder is typically a very simple device. + * We can decode an instruction by simply + * separating the machine word into small parts using wire slices + * The RISC instruction decoder can be approximate by the n to 2^n decoders, + * although this approximation usually underestimate power since each decoded + * instruction normally has more than 1 active signal. + * + * However, decoding a CISC instruction word is much more difficult + * than the RISC case. A CISC decoder is typically set up as a state machine. + * The machine reads the opcode field to determine + * what type of instruction it is, + * and where the other data values are. + * The instruction word is read in piece by piece, + * and decisions are made at each stage as to + * how the remainder of the instruction word will be read. + * (sequencer and ROM are usually needed) + * An x86 decoder can be even more complex since + * it involve both decoding instructions into u-ops and + * merge u-ops when doing micro-ops fusion. + */ + bool is_dram = false; + double pmos_to_nmos_sizing_r; + double load_nmos_width, load_pmos_width; + double C_driver_load, R_wire_load; + Area cell; + + l_ip = *configure_interface; + local_result = init_interface(&l_ip); + cell.h = g_tp.cell_h_def; + cell.w = g_tp.cell_h_def; + + num_decoder_segments = (int)ceil(opcode_length / 18.0); + if (opcode_length > 18) + opcode_length = 18; + num_decoded_signals = (int)pow(2.0, opcode_length); + pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + load_nmos_width = g_tp.max_w_nmos_ / 2; + load_pmos_width = g_tp.max_w_nmos_ * pmos_to_nmos_sizing_r; + C_driver_load = + 1024 * gate_C(load_nmos_width + load_pmos_width, 0, + is_dram); // TODO: this number 1024 needs to be revisited + R_wire_load = 3000 * l_ip.F_sz_um * g_tp.wire_outside_mat.R_per_um; + + final_dec = new Decoder(num_decoded_signals, false, C_driver_load, + R_wire_load, false /*is_fa*/, false /*is_dram*/, + false /*wl_tr*/, // to use peri device + cell); + + PredecBlk *predec_blk1 = + new PredecBlk(num_decoded_signals, final_dec, + 0, // Assuming predec and dec are back to back + 0, + 1, // Each Predec only drives one final dec + false /*is_dram*/, true); + PredecBlk *predec_blk2 = + new PredecBlk(num_decoded_signals, final_dec, + 0, // Assuming predec and dec are back to back + 0, + 1, // Each Predec only drives one final dec + false /*is_dram*/, false); + + PredecBlkDrv *predec_blk_drv1 = new PredecBlkDrv(0, predec_blk1, false); + PredecBlkDrv *predec_blk_drv2 = new PredecBlkDrv(0, predec_blk2, false); + + pre_dec = new Predec(predec_blk_drv1, predec_blk_drv2); + + double area_decoder = final_dec->area.get_area() * num_decoded_signals * + num_decoder_segments * num_decoders; + // double w_decoder = area_decoder / area.get_h(); + double area_pre_dec = + (predec_blk_drv1->area.get_area() + predec_blk_drv2->area.get_area() + + predec_blk1->area.get_area() + predec_blk2->area.get_area()) * + num_decoder_segments * num_decoders; + area.set_area(area.get_area() + area_decoder + area_pre_dec); + double macro_layout_overhead = g_tp.macro_layout_overhead; + double chip_PR_overhead = g_tp.chip_layout_overhead; + area.set_area(area.get_area() * macro_layout_overhead * chip_PR_overhead); + + inst_decoder_delay_power(); + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void inst_decoder::inst_decoder_delay_power() { + // double dec_outrisetime; + // double inrisetime = 0, outrisetime; + double pppm_t[4] = {1, 1, 1, 1}; + double squencer_passes = x86 ? 2 : 1; + + // outrisetime = pre_dec->compute_delays(inrisetime); + // dec_outrisetime = final_dec->compute_delays(outrisetime); + set_pppm(pppm_t, squencer_passes * num_decoder_segments, num_decoder_segments, + squencer_passes * num_decoder_segments, num_decoder_segments); + power = power + pre_dec->power * pppm_t; + set_pppm(pppm_t, squencer_passes * num_decoder_segments, + num_decoder_segments * num_decoded_signals, + num_decoder_segments * num_decoded_signals, + squencer_passes * num_decoder_segments); + power = power + final_dec->power * pppm_t; +} +void inst_decoder::leakage_feedback(double temperature) { + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + uca_org_t init_result = init_interface(&l_ip); // init_result is dummy + + final_dec->leakage_feedback(temperature); + pre_dec->leakage_feedback(temperature); + + double pppm_t[4] = {1, 1, 1, 1}; + double squencer_passes = x86 ? 2 : 1; + + set_pppm(pppm_t, squencer_passes * num_decoder_segments, num_decoder_segments, + squencer_passes * num_decoder_segments, num_decoder_segments); + power = pre_dec->power * pppm_t; + + set_pppm(pppm_t, squencer_passes * num_decoder_segments, + num_decoder_segments * num_decoded_signals, + num_decoder_segments * num_decoded_signals, + squencer_passes * num_decoder_segments); + power = power + final_dec->power * pppm_t; + + double sckRation = g_tp.sckt_co_eff; + + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +inst_decoder::~inst_decoder() { + local_result.cleanup(); + + delete final_dec; + + delete pre_dec->blk1; + delete pre_dec->blk2; + delete pre_dec->drv1; + delete pre_dec->drv2; + delete pre_dec; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/logic.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/logic.h new file mode 100644 index 0000000000..10b4f7bc9a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/logic.h @@ -0,0 +1,231 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#ifndef LOGIC_H_ +#define LOGIC_H_ + +#include +#include +#include +#include +#include "XML_Parse.h" +#include "arch_const.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/cacti_interface.h" +#include "cacti/component.h" +#include "cacti/const.h" +#include "cacti/decoder.h" +#include "cacti/parameter.h" + +using namespace std; +using namespace cacti; + +class selection_logic : public Component { + public: + selection_logic( + bool _is_default, int win_entries_, int issue_width_, + const InputParameter *configure_interface, + enum Device_ty device_ty_ = Core_device, + enum Core_type core_ty_ = Inorder); //, const ParseXML *_XML_interface); + bool is_default; + InputParameter l_ip; + uca_org_t local_result; + const ParseXML *XML_interface; + int win_entries; + int issue_width; + int num_threads; + enum Device_ty device_ty; + enum Core_type core_ty; + + void selection_power(); + void leakage_feedback(double temperature); // TODO +}; + +class dep_resource_conflict_check : public Component { + public: + dep_resource_conflict_check(const InputParameter *configure_interface, + const CoreDynParam &dyn_p_, int compare_bits_, + bool _is_default = true); + InputParameter l_ip; + uca_org_t local_result; + double WNORn, WNORp, Wevalinvp, Wevalinvn, Wcompn, Wcompp, Wcomppreequ; + CoreDynParam coredynp; + int compare_bits; + bool is_default; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + + void conflict_check_power(); + double compare_cap(); + ~dep_resource_conflict_check() { local_result.cleanup(); } + + void leakage_feedback(double temperature); +}; + +class inst_decoder : public Component { + public: + inst_decoder(bool _is_default, const InputParameter *configure_interface, + int opcode_length_, int num_decoders_, bool x86_, + enum Device_ty device_ty_ = Core_device, + enum Core_type core_ty_ = Inorder); + inst_decoder(); + bool is_default; + int opcode_length; + int num_decoders; + bool x86; + int num_decoder_segments; + int num_decoded_signals; + InputParameter l_ip; + uca_org_t local_result; + enum Device_ty device_ty; + enum Core_type core_ty; + + cacti::Decoder *final_dec; + Predec *pre_dec; + + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + void inst_decoder_delay_power(); + ~inst_decoder(); + void leakage_feedback(double temperature); +}; + +class DFFCell : public Component { + public: + DFFCell(bool _is_dram, double _WdecNANDn, double _WdecNANDp, + double _cell_load, const InputParameter *configure_interface); + InputParameter l_ip; + bool is_dram; + double cell_load; + double WdecNANDn; + double WdecNANDp; + double clock_cap; + int model; + int n_switch; + int n_keep_1; + int n_keep_0; + int n_clock; + powerDef e_switch; + powerDef e_keep_1; + powerDef e_keep_0; + powerDef e_clock; + + double fpfp_node_cap(unsigned int fan_in, unsigned int fan_out); + void compute_DFF_cell(void); +}; + +class Pipeline : public Component { + public: + Pipeline(const InputParameter *configure_interface, + const CoreDynParam &dyn_p_, enum Device_ty device_ty_ = Core_device, + bool _is_core_pipeline = true, bool _is_default = true); + InputParameter l_ip; + uca_org_t local_result; + CoreDynParam coredynp; + enum Device_ty device_ty; + bool is_core_pipeline, is_default; + double num_piperegs; + // int pipeline_stages; + // int tot_stage_vector, per_stage_vector; + bool process_ind; + double WNANDn; + double WNANDp; + double load_per_pipeline_stage; + // int Hthread, num_thread, fetchWidth, decodeWidth, issueWidth, + // commitWidth, instruction_length; int PC_width, opcode_length, + // num_arch_reg_tag, data_width,num_phsical_reg_tag, address_width; bool + // thread_clock_gated; bool in_order, multithreaded; + void compute_stage_vector(); + void compute(); + ~Pipeline() { local_result.cleanup(); }; +}; + +// class core_pipeline :public pipeline{ +// public: +// int Hthread, num_thread, fetchWidth, decodeWidth, issueWidth, +// commitWidth, instruction_length; int PC_width, opcode_length, +// num_arch_reg_tag, data_width,num_phsical_reg_tag, address_width; bool +// thread_clock_gated; bool in_order, multithreaded; core_pipeline(bool +//_is_default, const InputParameter *configure_interface); virtual void +// compute_stage_vector(); +// +//}; + +class FunctionalUnit : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double FU_height; + double clockRate, executionTime; + double num_fu; + double energy, base_energy, per_access_energy, leakage, gate_leakage; + bool is_default; + enum FU_type fu_type; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + + FunctionalUnit(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + enum FU_type fu_type); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + void leakage_feedback(double temperature); +}; + +class UndiffCore : public Component { + public: + UndiffCore(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true, bool embedded_ = false); + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + enum Core_type core_ty; + bool opt_performance, embedded; + double pipeline_stage, num_hthreads, issue_width; + bool is_default; + + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~UndiffCore(){}; + bool exist; +}; +#endif /* LOGIC_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/mcpat.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/mcpat.cc new file mode 100644 index 0000000000..767065ba7c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/mcpat.cc @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "mcpat.h" + +McPAT::McPAT(ParseXML *c) : setting(c) {} + +McPAT::~McPAT() {} + +void McPAT::getPower(Power &power) { + Processor proc(setting); + + proc.compute(); + proc.getPower(&power); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/mcpat.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/mcpat.h new file mode 100644 index 0000000000..9bf58e4be0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/mcpat.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __LIB_MCPAT__ +#define __LIB_MCPAT__ + +#include "XML_Parse.h" +#include "processor.h" + +class McPAT { + private: + ParseXML *setting; + + public: + McPAT(ParseXML *); + ~McPAT(); + + void getPower(Power &); +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/memoryctrl.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/memoryctrl.cc new file mode 100644 index 0000000000..31e09d4ac1 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/memoryctrl.cc @@ -0,0 +1,1019 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#include "memoryctrl.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +#include "logic.h" + +/* overview of MC models: + * McPAT memory controllers are modeled according to large number of industrial + * data points. The Basic memory controller architecture is base on the Synopsis + * designs (DesignWare DDR2/DDR3-Lite memory controllers and DDR2/DDR3-Lite + * protocol controllers) as in Cadence ChipEstimator Tool + * + * An MC has 3 parts as shown in this design. McPAT models both high performance + * MC based on Niagara processor designs and curving and low power MC based on + * data points in Cadence ChipEstimator Tool. + * + * The frontend is modeled analytically, the backend is modeled empirically + * according to DDR2/DDR3-Lite protocol controllers in Cadence ChipEstimator + * Tool The PHY is modeled based on "A 100mW 9.6Gb/s Transceiver in 90nm CMOS + * for next-generation memory interfaces ," ISSCC 2006, and A 14mW 6.25Gb/s + * Transceiver in 90nm CMOS for Serial Chip-to-Chip Communication," ISSCC 2007 + * + * In Cadence ChipEstimator Tool there are two types of memory controllers: the + * full memory controllers that includes the frontend as the DesignWare + * DDR2/DDR3-Lite memory controllers and the backend only memory controllers as + * the DDR2/DDR3-Lite protocol controllers (except DesignWare DDR2/DDR3-Lite + * memory controllers, all memory controller IP in Cadence ChipEstimator Tool + * are backend memory controllers such as DDRC 1600A and DDRC 800A). Thus,to + * some extend the area and power difference between DesignWare DDR2/DDR3-Lite + * memory controllers and DDR2/DDR3-Lite protocol controllers can be an + * estimation to the frontend power and area, which is very close the + * analitically modeled results of the frontend for Niagara2@65nm + * + */ + +MCBackend::MCBackend(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_) + : l_ip(*interface_ip_), mc_type(mc_type_), mcp(mcp_) { + local_result = init_interface(&l_ip); + compute(); +} + +void MCBackend::compute() { + // double max_row_addr_width = 20.0;//Current address 12~18bits + double C_MCB, mc_power, backend_dyn, + backend_gates; //, refresh_period,refresh_freq;//Equivalent per bit Cap + // for backend, + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing, PMOS_sizing; + + if (mc_type == MC) { + if (mcp.type == 0) { + // area = + // (2.2927*log(peakDataTransferRate)-14.504)*memDataWidth/144.0*(l_ip.F_sz_um/0.09); + area.set_area((2.7927 * log(mcp.peakDataTransferRate * 2) - 19.862) / + 2.0 * mcp.dataBusWidth / 128.0 * (l_ip.F_sz_um / 0.09) * + mcp.num_channels * 1e6); // um^2 + // assuming the approximately same scaling factor as seen in processors. + // C_MCB=0.2/1.3/1.3/266/64/0.09*g_ip.F_sz_um;//based on AMD Geode + // processor which has a very basic mc on chip. C_MCB + // = 1.6/200/1e6/144/1.2/1.2*g_ip.F_sz_um/0.19;//Based on Niagara power + // numbers.The base power (W) is divided by device frequency and vdd and + // scale to target process. mc_power = 0.0291*2;//29.1mW@200MHz @130nm + // From Power Analysis of SystemLevel OnChip Communication Architectures + // by Lahiri et + mc_power = + 4.32 * + 0.1; // 4.32W@1GhzMHz @65nm Cadence ChipEstimator 10% for backend + C_MCB = mc_power / 1e9 / 72 / 1.1 / 1.1 * l_ip.F_sz_um / 0.065; + power_t.readOp.dynamic = + C_MCB * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * + (mcp.dataBusWidth /*+mcp.addressBusWidth*/); // per access energy in + // memory controller + power_t.readOp.leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + } + else { + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + area.set_area(0.15 * mcp.dataBusWidth / 72.0 * (l_ip.F_sz_um / 0.065) * + (l_ip.F_sz_um / 0.065) * mcp.num_channels * 1e6); // um^2 + backend_dyn = 0.9e-9 / 800e6 * mcp.clockRate / 12800 * + mcp.peakDataTransferRate * mcp.dataBusWidth / 72.0 * + g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / 1.1 * + (l_ip.F_sz_nm / 65.0); // Average on DDR2/3 protocol + // controller and DDRC 1600/800A in + // Cadence ChipEstimate + // Scaling to technology and DIMM feature. The base IP support + // DDR3-1600(PC3 12800) + backend_gates = 50000 * mcp.dataBusWidth / + 64.0; // 50000 is from Cadence ChipEstimator + + power_t.readOp.dynamic = backend_dyn; + power_t.readOp.leakage = + (backend_gates)*cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + (backend_gates)*cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + } + } + else { // skip old model + cout << "Unknown memory controllers" << endl; + exit(0); + area.set_area(0.243 * mcp.dataBusWidth / + 8); // area based on Cadence ChipEstimator for 8bit bus + // mc_power = 4.32*0.1;//4.32W@1GhzMHz @65nm Cadence ChipEstimator 10% for + // backend + C_MCB = mc_power / 1e9 / 72 / 1.1 / 1.1 * l_ip.F_sz_um / 0.065; + power_t.readOp.leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.dynamic *= 1.2; + power_t.readOp.leakage *= 1.2; + power_t.readOp.gate_leakage *= 1.2; + // flash controller has about 20% more backend power since BCH ECC in flash + // is complex and power hungry + } + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void MCBackend::computeEnergy(bool is_tdp) { + // backend uses internal data buswidth + if (is_tdp) { + // init stats for Peak + stats_t.readAc.access = 0.5 * mcp.num_channels; + stats_t.writeAc.access = 0.5 * mcp.num_channels; + tdp_stats = stats_t; + } + else { + // init stats for runtime power (RTP) + stats_t.readAc.access = mcp.reads; + stats_t.writeAc.access = mcp.writes; + tdp_stats = stats_t; + } + if (is_tdp) { + power = power_t; + power.readOp.dynamic = (stats_t.readAc.access + stats_t.writeAc.access) * + power_t.readOp.dynamic; + } + else { + rt_power.readOp.dynamic = (stats_t.readAc.access + stats_t.writeAc.access) * + mcp.llcBlockSize * 8.0 / mcp.dataBusWidth * + power_t.readOp.dynamic; + rt_power = rt_power + power_t * pppm_lkg; + rt_power.readOp.dynamic = + rt_power.readOp.dynamic + power.readOp.dynamic * 0.1 * mcp.clockRate * + mcp.num_mcs * mcp.executionTime; + // Assume 10% of peak power is consumed by routine job including memory + // refreshing and scrubbing + } +} + +MCPHY::MCPHY(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_) + : l_ip(*interface_ip_), mc_type(mc_type_), mcp(mcp_) { + local_result = init_interface(&l_ip); + compute(); +} + +void MCPHY::compute() { + // PHY uses internal data buswidth but the actuall off-chip datawidth is + // 64bits + ecc + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + /* + * according to "A 100mW 9.6Gb/s Transceiver in 90nm CMOS for next-generation + * memory interfaces ," ISSCC 2006; From Cadence ChipEstimator for normal I/O + * around 0.4~0.8 mW/Gb/s + */ + double power_per_gb_per_s; + // double phy_dyn; + double phy_gates; + double NMOS_sizing; + double PMOS_sizing; + + if (mc_type == MC) { + if (mcp.type == 0) { + power_per_gb_per_s = mcp.LVDS ? 0.01 : 0.04; + // Based on die photos from Niagara 1 and 2. + // TODO merge this into undifferentiated core.PHY only achieves square + // root of the ideal scaling. area = + // (6.4323*log(peakDataTransferRate)-34.76)*memDataWidth/128.0*(l_ip.F_sz_um/0.09); + area.set_area((6.4323 * log(mcp.peakDataTransferRate * 2) - 48.134) * + mcp.dataBusWidth / 128.0 * (l_ip.F_sz_um / 0.09) * + mcp.num_channels * 1e6 / 2); // TODO:/2 + // This is from curve fitting based on Niagara 1 and 2's PHY die photo. + // This is power not energy, 10mw/Gb/s @90nm for each channel and scaling + // down power.readOp.dynamic = 0.02*memAccesses*llcBlocksize*8;//change + // from Bytes to bits. + power_t.readOp.dynamic = power_per_gb_per_s * sqrt(l_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * + g_tp.peri_global.Vdd / 1.2; + power_t.readOp.leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + } + else { + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + // Designware/synopsis 16bit DDR3 PHY is 1.3mm (WITH IOs) at 40nm for upto + // DDR3 2133 (PC3 17066) + double non_IO_percentage = 0.2; + area.set_area(1.3 * non_IO_percentage / 2133.0e6 * mcp.clockRate / 17066 * + mcp.peakDataTransferRate * mcp.dataBusWidth / 16.0 * + (l_ip.F_sz_um / 0.040) * (l_ip.F_sz_um / 0.040) * + mcp.num_channels * 1e6); // um^2 + phy_gates = 200000 * mcp.dataBusWidth / 64.0; + power_per_gb_per_s = 0.01; + // This is power not energy, 10mw/Gb/s @90nm for each channel and scaling + // down + power_t.readOp.dynamic = power_per_gb_per_s * (l_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * + g_tp.peri_global.Vdd / 1.2; + power_t.readOp.leakage = + (mcp.withPHY ? phy_gates : 0) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + (mcp.withPHY ? phy_gates : 0) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + } + } + else { + area.set_area(0.4e6 / 2 * mcp.dataBusWidth / + 8); // area based on Cadence ChipEstimator for 8bit bus + } + + // double phy_factor = (int)ceil(mcp.dataBusWidth/72.0);//Previous phy power + // numbers are based on 72 bit DIMM interface power_t.readOp.dynamic *= + // phy_factor; power_t.readOp.leakage *= phy_factor; + // power_t.readOp.gate_leakage *= phy_factor; + + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void MCPHY::computeEnergy(bool is_tdp) { + if (is_tdp) { + // init stats for Peak + stats_t.readAc.access = 0.5 * mcp.num_channels; // time share on buses + stats_t.writeAc.access = 0.5 * mcp.num_channels; + tdp_stats = stats_t; + } + else { + // init stats for runtime power (RTP) + stats_t.readAc.access = mcp.reads; + stats_t.writeAc.access = mcp.writes; + tdp_stats = stats_t; + } + + if (is_tdp) { + double data_transfer_unit = (mc_type == MC) ? 72 : 16; /*DIMM data width*/ + power = power_t; + power.readOp.dynamic = + power.readOp.dynamic * + (mcp.peakDataTransferRate * 8 * 1e6 / 1e9 /*change to Gbs*/) * + mcp.dataBusWidth / data_transfer_unit * mcp.num_channels / + mcp.clockRate; + // divide by clock rate is for match the final computation where *clock is + // used + //(stats_t.readAc.access*power_t.readOp.dynamic+ + // stats_t.writeAc.access*power_t.readOp.dynamic); + } + else { + rt_power = power_t; + // rt_power.readOp.dynamic = + // (stats_t.readAc.access*power_t.readOp.dynamic+ + // stats_t.writeAc.access*power_t.readOp.dynamic); + + rt_power.readOp.dynamic = power_t.readOp.dynamic * + (stats_t.readAc.access + stats_t.writeAc.access) * + (mcp.llcBlockSize) * 8 / 1e9 / mcp.executionTime * + (mcp.executionTime); + rt_power.readOp.dynamic = + rt_power.readOp.dynamic + power.readOp.dynamic * 0.1 * mcp.clockRate * + mcp.num_mcs * mcp.executionTime; + } +} + +MCFrontEnd::MCFrontEnd(ParseXML *XML_interface, InputParameter *interface_ip_, + const MCParam &mcp_, enum MemoryCtrl_type mc_type_) + : XML(XML_interface), + interface_ip(*interface_ip_), + mc_type(mc_type_), + mcp(mcp_), + MC_arb(0), + frontendBuffer(0), + readBuffer(0), + writeBuffer(0) { + /* All computations are for a single MC + * + */ + + int tag, data; + bool is_default = true; // indication for default setup + + /* MC frontend engine channels share the same engines but logically + * partitioned For all hardware inside MC. different channels do not share + * resources. + * TODO: add docodeing/mux stage to steer memory requests to different + * channels. + */ + + // memory request reorder buffer + tag = mcp.addressBusWidth + EXTRA_TAG_BITS + mcp.opcodeW; + data = int(ceil((XML->sys.physical_address_width + mcp.opcodeW) / 8.0)); + interface_ip.cache_sz = data * XML->sys.mc.req_window_size_per_channel; + interface_ip.line_sz = data; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / mcp.clockRate; + interface_ip.latency = 1.0 / mcp.clockRate; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.mc.memory_channels_per_mc; + interface_ip.num_wr_ports = interface_ip.num_rd_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.mc.memory_channels_per_mc; + frontendBuffer = + new ArrayST(&interface_ip, "MC ReorderBuffer", Uncore_device); + frontendBuffer->area.set_area(frontendBuffer->area.get_area() + + frontendBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + area.set_area(area.get_area() + frontendBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + + // selection and arbitration logic + interface_ip.assoc = + 1; // reset to prevent unnecessary warning messages when init_interface + MC_arb = + new selection_logic(is_default, XML->sys.mc.req_window_size_per_channel, + 1, &interface_ip, Uncore_device); + + // read buffers. + data = (int)ceil(mcp.dataBusWidth / 8.0); // Support key words first + // operation //8 means converting + // bit to Byte + interface_ip.cache_sz = + data * XML->sys.mc.IO_buffer_size_per_channel; //*llcBlockSize; + interface_ip.line_sz = data; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / mcp.clockRate; + interface_ip.latency = 1.0 / mcp.clockRate; + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + 0; // XML->sys.mc.memory_channels_per_mc*2>2?2:XML->sys.mc.memory_channels_per_mc*2; + interface_ip.num_rd_ports = XML->sys.mc.memory_channels_per_mc; + interface_ip.num_wr_ports = interface_ip.num_rd_ports; + interface_ip.num_se_rd_ports = 0; + readBuffer = new ArrayST(&interface_ip, "MC ReadBuffer", Uncore_device); + readBuffer->area.set_area(readBuffer->area.get_area() + + readBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + area.set_area(area.get_area() + readBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + + // write buffer + data = (int)ceil(mcp.dataBusWidth / 8.0); // Support key words first + // operation //8 means converting + // bit to Byte + interface_ip.cache_sz = + data * XML->sys.mc.IO_buffer_size_per_channel; //*llcBlockSize; + interface_ip.line_sz = data; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / mcp.clockRate; + interface_ip.latency = 1.0 / mcp.clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.mc.memory_channels_per_mc; + interface_ip.num_wr_ports = interface_ip.num_rd_ports; + interface_ip.num_se_rd_ports = 0; + writeBuffer = new ArrayST(&interface_ip, "MC writeBuffer", Uncore_device); + writeBuffer->area.set_area(writeBuffer->area.get_area() + + writeBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + area.set_area(area.get_area() + writeBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); +} + +void MCFrontEnd::computeEnergy(bool is_tdp) { + if (is_tdp) { + // init stats for Peak + frontendBuffer->stats_t.readAc.access = + frontendBuffer->l_ip.num_search_ports; + frontendBuffer->stats_t.writeAc.access = frontendBuffer->l_ip.num_wr_ports; + frontendBuffer->tdp_stats = frontendBuffer->stats_t; + + readBuffer->stats_t.readAc.access = + readBuffer->l_ip.num_rd_ports * mcp.frontend_duty_cycle; + readBuffer->stats_t.writeAc.access = + readBuffer->l_ip.num_wr_ports * mcp.frontend_duty_cycle; + readBuffer->tdp_stats = readBuffer->stats_t; + + writeBuffer->stats_t.readAc.access = + writeBuffer->l_ip.num_rd_ports * mcp.frontend_duty_cycle; + writeBuffer->stats_t.writeAc.access = + writeBuffer->l_ip.num_wr_ports * mcp.frontend_duty_cycle; + writeBuffer->tdp_stats = writeBuffer->stats_t; + } + else { + // init stats for runtime power (RTP) + frontendBuffer->stats_t.readAc.access = + XML->sys.mc.memory_reads * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth * + mcp.dataBusWidth / 72; + // For each channel, each memory word need to check the address data to + // achieve best scheduling results. and this need to be done on all + // physical DIMMs in each logical memory DIMM *mcp.dataBusWidth/72 + frontendBuffer->stats_t.writeAc.access = + XML->sys.mc.memory_writes * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth * + mcp.dataBusWidth / 72; + frontendBuffer->rtp_stats = frontendBuffer->stats_t; + + readBuffer->stats_t.readAc.access = + XML->sys.mc.memory_reads * mcp.llcBlockSize * 8.0 / + mcp.dataBusWidth; // support key word first + readBuffer->stats_t.writeAc.access = + XML->sys.mc.memory_reads * mcp.llcBlockSize * 8.0 / + mcp.dataBusWidth; // support key word first + readBuffer->rtp_stats = readBuffer->stats_t; + + writeBuffer->stats_t.readAc.access = + XML->sys.mc.memory_writes * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth; + writeBuffer->stats_t.writeAc.access = + XML->sys.mc.memory_writes * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth; + writeBuffer->rtp_stats = writeBuffer->stats_t; + } + + frontendBuffer->power_t.reset(); + readBuffer->power_t.reset(); + writeBuffer->power_t.reset(); + + // frontendBuffer->power_t.readOp.dynamic += + //(frontendBuffer->stats_t.readAc.access* + // (frontendBuffer->local_result.power.searchOp.dynamic+frontendBuffer->local_result.power.readOp.dynamic)+ + // frontendBuffer->stats_t.writeAc.access*frontendBuffer->local_result.power.writeOp.dynamic); + + frontendBuffer->power_t.readOp.dynamic += + (frontendBuffer->stats_t.readAc.access + + frontendBuffer->stats_t.writeAc.access) * + frontendBuffer->local_result.power.searchOp.dynamic + + frontendBuffer->stats_t.readAc.access * + frontendBuffer->local_result.power.readOp.dynamic + + frontendBuffer->stats_t.writeAc.access * + frontendBuffer->local_result.power.writeOp.dynamic; + + readBuffer->power_t.readOp.dynamic += + (readBuffer->stats_t.readAc.access * + readBuffer->local_result.power.readOp.dynamic + + readBuffer->stats_t.writeAc.access * + readBuffer->local_result.power.writeOp.dynamic); + writeBuffer->power_t.readOp.dynamic += + (writeBuffer->stats_t.readAc.access * + writeBuffer->local_result.power.readOp.dynamic + + writeBuffer->stats_t.writeAc.access * + writeBuffer->local_result.power.writeOp.dynamic); + + if (is_tdp) { + power = power + frontendBuffer->power_t + readBuffer->power_t + + writeBuffer->power_t + + (frontendBuffer->local_result.power + + readBuffer->local_result.power + writeBuffer->local_result.power) * + pppm_lkg; + } + else { + rt_power = + rt_power + frontendBuffer->power_t + readBuffer->power_t + + writeBuffer->power_t + + (frontendBuffer->local_result.power + readBuffer->local_result.power + + writeBuffer->local_result.power) * + pppm_lkg; + rt_power.readOp.dynamic = + rt_power.readOp.dynamic + power.readOp.dynamic * 0.1 * mcp.clockRate * + mcp.num_mcs * mcp.executionTime; + } +} + +void MCFrontEnd::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Front End ROB:" << endl; + cout << indent_str_next + << "Area = " << frontendBuffer->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << frontendBuffer->power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << frontendBuffer->power.readOp.leakage + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? frontendBuffer->power.readOp + .power_gated_with_long_channel_leakage + : frontendBuffer->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << frontendBuffer->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << frontendBuffer->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + + cout << endl; + cout << indent_str << "Read Buffer:" << endl; + cout << indent_str_next << "Area = " << readBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << readBuffer->power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << readBuffer->power.readOp.leakage + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? readBuffer->power.readOp + .power_gated_with_long_channel_leakage + : readBuffer->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << readBuffer->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << readBuffer->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + cout << indent_str << "Write Buffer:" << endl; + cout << indent_str_next << "Area = " << writeBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << writeBuffer->power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << writeBuffer->power.readOp.leakage + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? writeBuffer->power.readOp + .power_gated_with_long_channel_leakage + : writeBuffer->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << writeBuffer->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << writeBuffer->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + } + else { + cout << indent_str << "Front End ROB:" << endl; + cout << indent_str_next + << "Area = " << frontendBuffer->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << frontendBuffer->rt_power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << frontendBuffer->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << frontendBuffer->rt_power.readOp.gate_leakage + << " W" << endl; + cout << endl; + cout << indent_str << "Read Buffer:" << endl; + cout << indent_str_next << "Area = " << readBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << readBuffer->rt_power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << readBuffer->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << readBuffer->rt_power.readOp.gate_leakage + << " W" << endl; + cout << endl; + cout << indent_str << "Write Buffer:" << endl; + cout << indent_str_next << "Area = " << writeBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << writeBuffer->rt_power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << writeBuffer->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << writeBuffer->rt_power.readOp.gate_leakage + << " W" << endl; + } +} + +MemoryController::MemoryController(ParseXML *XML_interface, + InputParameter *interface_ip_, + enum MemoryCtrl_type mc_type_) + : XML(XML_interface), + interface_ip(*interface_ip_), + mc_type(mc_type_), + frontend(0), + transecEngine(0), + PHY(0), + pipeLogic(0) { + /* All computations are for a single MC + * + */ + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + interface_ip.wt = Global; + set_mc_param(); + frontend = new MCFrontEnd(XML, &interface_ip, mcp, mc_type); + area.set_area(area.get_area() + frontend->area.get_area()); + transecEngine = new MCBackend(&interface_ip, mcp, mc_type); + area.set_area(area.get_area() + transecEngine->area.get_area()); + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + PHY = new MCPHY(&interface_ip, mcp, mc_type); + area.set_area(area.get_area() + PHY->area.get_area()); + } + //+++++++++Transaction engine +++++++++++++++++ ////TODO needs better numbers, + // Run the RTL code from OpenSparc. + // transecEngine.initialize(&interface_ip); + // transecEngine.peakDataTransferRate = XML->sys.mem.peak_transfer_rate; + // transecEngine.memDataWidth = dataBusWidth; + // transecEngine.memRank = XML->sys.mem.number_ranks; + // //transecEngine.memAccesses=XML->sys.mc.memory_accesses; + // //transecEngine.llcBlocksize=llcBlockSize; + // transecEngine.compute(); + // transecEngine.area.set_area(XML->sys.mc.memory_channels_per_mc*transecEngine.area.get_area()) + // ; area.set_area(area.get_area()+ transecEngine.area.get_area()); + // ///cout<<"area="<sys.mem.peak_transfer_rate; + // PHY.memDataWidth = dataBusWidth; + // //PHY.memAccesses=PHY.peakDataTransferRate;//this is the max power + // //PHY.llcBlocksize=llcBlockSize; + // PHY.compute(); + // PHY.area.set_area(XML->sys.mc.memory_channels_per_mc*PHY.area.get_area()) + // ; area.set_area(area.get_area()+ PHY.area.get_area()); + /// cout<<"area="<sys.core[0].opcode_width + dataBusWidth; pipeLogic = new + // pipeline(is_default, &interface_ip); + // //pipeLogic.init_pipeline(is_default, &interface_ip); + // pipeLogic->compute_pipeline(); + // area.set_area(area.get_area()+ pipeLogic->area.get_area()*1e-6); + // area.set_area((area.get_area()+mc_area*1e-6)*1.1);//placement and routing + // overhead + // + // + //// //clock + //// clockNetwork.init_wire_external(is_default, &interface_ip); + //// clockNetwork.clk_area =area*1.1;//10% of placement overhead. + /// rule of thumb / clockNetwork.end_wiring_level =5;//toplevel metal / + /// clockNetwork.start_wiring_level =5;//toplevel metal / + /// clockNetwork.num_regs = pipeLogic.tot_stage_vector; / + /// clockNetwork.optimize_wire(); +} +void MemoryController::computeEnergy(bool is_tdp) { + frontend->computeEnergy(is_tdp); + transecEngine->computeEnergy(is_tdp); + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + PHY->computeEnergy(is_tdp); + } + if (is_tdp) { + power = power + frontend->power + transecEngine->power; + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + power = power + PHY->power; + } + } + else { + rt_power = rt_power + frontend->rt_power + transecEngine->rt_power; + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + rt_power = rt_power + PHY->rt_power; + } + } +} + +void MemoryController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "Memory Controller:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic / mcp.executionTime + << " W" << endl; + cout << endl; + cout << indent_str << "Front End Engine:" << endl; + cout << indent_str_next << "Area = " << frontend->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << frontend->power.readOp.dynamic * mcp.clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? frontend->power.readOp.longer_channel_leakage + : frontend->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout + << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? frontend->power.readOp.power_gated_with_long_channel_leakage + : frontend->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << frontend->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << frontend->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + if (plevel > 2) { + frontend->displayEnergy(indent + 4, is_tdp); + } + cout << indent_str << "Transaction Engine:" << endl; + cout << indent_str_next + << "Area = " << transecEngine->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << transecEngine->power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? transecEngine->power.readOp.longer_channel_leakage + : transecEngine->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? transecEngine->power.readOp + .power_gated_with_long_channel_leakage + : transecEngine->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << transecEngine->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << transecEngine->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + cout << indent_str << "PHY:" << endl; + cout << indent_str_next << "Area = " << PHY->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << PHY->power.readOp.dynamic * mcp.clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? PHY->power.readOp.longer_channel_leakage + : PHY->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? PHY->power.readOp.power_gated_with_long_channel_leakage + : PHY->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << PHY->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << PHY->rt_power.readOp.dynamic / mcp.executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << "Memory Controller:" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " << power.readOp.leakage + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << endl; + } +} + +void MemoryController::set_mc_param() { + if (mc_type == MC) { + mcp.clockRate = XML->sys.mc.mc_clock * 2; // DDR double pumped + mcp.clockRate *= 1e6; + mcp.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + + mcp.llcBlockSize = int(ceil(XML->sys.mc.llc_line_length / 8.0)) + + XML->sys.mc.llc_line_length; // ecc overhead + mcp.dataBusWidth = + int(ceil(XML->sys.mc.databus_width / 8.0)) + XML->sys.mc.databus_width; + mcp.addressBusWidth = int(ceil( + XML->sys.mc.addressbus_width)); // XML->sys.physical_address_width; + mcp.opcodeW = 16; + mcp.num_mcs = XML->sys.mc.number_mcs; + mcp.num_channels = XML->sys.mc.memory_channels_per_mc; + mcp.reads = XML->sys.mc.memory_reads; + mcp.writes = XML->sys.mc.memory_writes; + //+++++++++Transaction engine +++++++++++++++++ ////TODO needs better + // numbers, Run the RTL code from OpenSparc. + mcp.peakDataTransferRate = XML->sys.mc.peak_transfer_rate; + mcp.memRank = XML->sys.mc.number_ranks; + //++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs better numbers + // PHY.memAccesses=PHY.peakDataTransferRate;//this is the max power + // PHY.llcBlocksize=llcBlockSize; + mcp.frontend_duty_cycle = 0.5; // for max power, the actual off-chip links + // is bidirectional but time shared + mcp.LVDS = XML->sys.mc.LVDS; + mcp.type = XML->sys.mc.type; + mcp.withPHY = XML->sys.mc.withPHY; + + if (XML->sys.mc.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.mc.vdd; + interface_ip.lop_Vdd = XML->sys.mc.vdd; + interface_ip.lstp_Vdd = XML->sys.mc.vdd; + } + if (XML->sys.mc.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.mc.power_gating_vcc; + } + } + // else if (mc_type==FLASHC) + // { + // mcp.clockRate =XML->sys.flashc.mc_clock*2;//DDR double + // pumped mcp.clockRate *= 1e6; + // mcp.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + // + // mcp.llcBlockSize + //=int(ceil(XML->sys.flashc.llc_line_length/8.0))+XML->sys.flashc.llc_line_length;//ecc + // overhead mcp.dataBusWidth + //=int(ceil(XML->sys.flashc.databus_width/8.0)) + + // XML->sys.flashc.databus_width; mcp.addressBusWidth + //=int(ceil(XML->sys.flashc.addressbus_width));//XML->sys.physical_address_width; + // mcp.opcodeW =16; + // mcp.num_mcs = XML->sys.flashc.number_mcs; + // mcp.num_channels = XML->sys.flashc.memory_channels_per_mc; + // mcp.reads = XML->sys.flashc.memory_reads; + // mcp.writes = XML->sys.flashc.memory_writes; + // //+++++++++Transaction engine +++++++++++++++++ ////TODO needs + // better numbers, Run the RTL code from OpenSparc. + // mcp.peakDataTransferRate = XML->sys.flashc.peak_transfer_rate; + // mcp.memRank = XML->sys.flashc.number_ranks; + // //++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs + // better numbers + // //PHY.memAccesses=PHY.peakDataTransferRate;//this is the max + // power + // //PHY.llcBlocksize=llcBlockSize; + // mcp.frontend_duty_cycle = 0.5;//for max power, the actual + // off-chip links is bidirectional but time shared mcp.LVDS = + // XML->sys.flashc.LVDS; mcp.type = XML->sys.flashc.type; + // } + else { + cout << "Unknown memory controller type: neither DRAM controller nor Flash " + "controller" + << endl; + exit(0); + } +} + +MCFrontEnd ::~MCFrontEnd() { + if (MC_arb) { + delete MC_arb; + MC_arb = 0; + } + if (frontendBuffer) { + delete frontendBuffer; + frontendBuffer = 0; + } + if (readBuffer) { + delete readBuffer; + readBuffer = 0; + } + if (writeBuffer) { + delete writeBuffer; + writeBuffer = 0; + } +} + +MemoryController ::~MemoryController() { + if (frontend) { + delete frontend; + frontend = 0; + } + if (transecEngine) { + delete transecEngine; + transecEngine = 0; + } + if (PHY) { + delete PHY; + PHY = 0; + } + if (pipeLogic) { + delete pipeLogic; + pipeLogic = 0; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/memoryctrl.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/memoryctrl.h new file mode 100644 index 0000000000..c2fbb922e2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/memoryctrl.h @@ -0,0 +1,118 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef MEMORYCTRL_H_ +#define MEMORYCTRL_H_ + +#include "XML_Parse.h" +#include "cacti/parameter.h" +//#include "io.h" +#include "array.h" +//#include "Undifferentiated_Core_Area.h" +#include +#include "basic_components.h" +#include "logic.h" +using namespace cacti; + +class MCBackend : public Component { + public: + InputParameter l_ip; + uca_org_t local_result; + enum MemoryCtrl_type mc_type; + MCParam mcp; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + MCBackend(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_); + void compute(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MCBackend(){}; +}; + +class MCPHY : public Component { + public: + InputParameter l_ip; + uca_org_t local_result; + enum MemoryCtrl_type mc_type; + MCParam mcp; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + MCPHY(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_); + void compute(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MCPHY(){}; +}; + +class MCFrontEnd : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + enum MemoryCtrl_type mc_type; + MCParam mcp; + selection_logic *MC_arb; + ArrayST *frontendBuffer; + ArrayST *readBuffer; + ArrayST *writeBuffer; + + MCFrontEnd(ParseXML *XML_interface, InputParameter *interface_ip_, + const MCParam &mcp_, enum MemoryCtrl_type mc_type_); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MCFrontEnd(); +}; + +class MemoryController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + enum MemoryCtrl_type mc_type; + MCParam mcp; + MCFrontEnd *frontend; + MCBackend *transecEngine; + MCPHY *PHY; + Pipeline *pipeLogic; + + // clock_network clockNetwork; + MemoryController(ParseXML *XML_interface, InputParameter *interface_ip_, + enum MemoryCtrl_type mc_type_); + void set_mc_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MemoryController(); +}; +#endif /* MEMORYCTRL_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/noc.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/noc.cc new file mode 100644 index 0000000000..f5a8bf2c66 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/noc.cc @@ -0,0 +1,530 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "noc.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" + +NoC::NoC(ParseXML *XML_interface, int ithNoC_, InputParameter *interface_ip_, + double M_traffic_pattern_, double link_len_) + : XML(XML_interface), + ithNoC(ithNoC_), + interface_ip(*interface_ip_), + router(0), + link_bus(0), + link_bus_exist(false), + router_exist(false), + M_traffic_pattern(M_traffic_pattern_) { + /* + * initialize, compute and optimize individual components. + */ + + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 1; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + } + set_noc_param(); + local_result = init_interface(&interface_ip); + scktRatio = g_tp.sckt_co_eff; + + if (nocdynp.type) { /* + * if NOC compute router, router links must be computed + * separately and called from external since total chip + * area must be known first + */ + init_router(); + } + else { + init_link_bus(link_len_); // if bus compute bus + } + + // //clock power + // clockNetwork.init_wire_external(is_default, &interface_ip); + // clockNetwork.clk_area =area*1.1;//10% of placement overhead. + // rule of thumb clockNetwork.end_wiring_level =5;//toplevel metal + // clockNetwork.start_wiring_level =5;//toplevel metal + // clockNetwork.num_regs = corepipe.tot_stage_vector; + // clockNetwork.optimize_wire(); +} + +void NoC::init_router() { + router = new Router( + nocdynp.flit_size, + nocdynp.virtual_channel_per_port * nocdynp.input_buffer_entries_per_vc, + nocdynp.virtual_channel_per_port, &(g_tp.peri_global), + nocdynp.input_ports, nocdynp.output_ports, M_traffic_pattern); + // router->print_router(); + area.set_area(area.get_area() + + router->area.get_area() * nocdynp.total_nodes); + + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + double pg_reduction_retain = power_gating_leakage_reduction( + false); // state retaining array structure; + double pg_reduction_nonretain = power_gating_leakage_reduction( + false); // non-state-retaining array structure; + + router->power.readOp.longer_channel_leakage = + router->power.readOp.leakage * long_channel_device_reduction; + router->buffer.power.readOp.longer_channel_leakage = + router->buffer.power.readOp.leakage * long_channel_device_reduction; + router->crossbar.power.readOp.longer_channel_leakage = + router->crossbar.power.readOp.leakage * long_channel_device_reduction; + router->arbiter.power.readOp.longer_channel_leakage = + router->arbiter.power.readOp.leakage * long_channel_device_reduction; + + router->buffer.power.readOp.power_gated_leakage = + router->buffer.power.readOp.leakage * + pg_reduction_retain; // TODO: this is a simplified version; should use + // the power_gated_leakage generated in buff + router->crossbar.power.readOp.power_gated_leakage = + router->crossbar.power.readOp.leakage * pg_reduction_nonretain; + router->arbiter.power.readOp.power_gated_leakage = + router->arbiter.power.readOp.leakage * pg_reduction_nonretain; + router->power.readOp.power_gated_leakage = + router->buffer.power.readOp.power_gated_leakage + + router->crossbar.power.readOp.power_gated_leakage + + router->arbiter.power.readOp.power_gated_leakage; + + router->buffer.power.readOp.power_gated_with_long_channel_leakage = + router->buffer.power.readOp.power_gated_leakage * + long_channel_device_reduction; // TODO: this is a simplified version; + // should use the power_gated_leakage + // generated in buff + router->crossbar.power.readOp.power_gated_with_long_channel_leakage = + router->crossbar.power.readOp.power_gated_leakage * + long_channel_device_reduction; + router->arbiter.power.readOp.power_gated_with_long_channel_leakage = + router->arbiter.power.readOp.power_gated_leakage * + long_channel_device_reduction; + router->power.readOp.power_gated_with_long_channel_leakage = + router->buffer.power.readOp.power_gated_with_long_channel_leakage + + router->crossbar.power.readOp.power_gated_with_long_channel_leakage + + router->arbiter.power.readOp.power_gated_with_long_channel_leakage; + + router_exist = true; +} + +void NoC ::init_link_bus(double link_len_) { + // if (nocdynp.min_ports==1 ) + if (nocdynp.type) + link_name = "Links"; + else + link_name = "Bus"; + + link_len = link_len_; + assert(link_len > 0); + + interface_ip.throughput = nocdynp.link_throughput / nocdynp.clockRate; + interface_ip.latency = nocdynp.link_latency / nocdynp.clockRate; + + link_len /= (nocdynp.horizontal_nodes + nocdynp.vertical_nodes) / 2; + + if (nocdynp.total_nodes > 1) + link_len /= 2; // All links are shared by neighbors + link_bus = new interconnect(name, Uncore_device, 1, 1, nocdynp.flit_size, + link_len, &interface_ip, 3, true /*pipelinable*/, + nocdynp.route_over_perc); + + link_bus_tot_per_Router.area.set_area( + link_bus_tot_per_Router.area.get_area() + + link_bus->area.get_area() * nocdynp.global_linked_ports); + + area.set_area(area.get_area() + + link_bus_tot_per_Router.area.get_area() * nocdynp.total_nodes); + link_bus_exist = true; +} +void NoC::computeEnergy(bool is_tdp) { + // power_point_product_masks + double pppm_t[4] = {1, 1, 1, 1}; + double M = nocdynp.duty_cycle; + if (is_tdp) { + // init stats for TDP + stats_t.readAc.access = M; + tdp_stats = stats_t; + if (router_exist) { + set_pppm(pppm_t, 1 * M, 1, 1, 1); // reset traffic pattern + router->power = router->power * pppm_t; + set_pppm(pppm_t, nocdynp.total_nodes, nocdynp.total_nodes, + nocdynp.total_nodes, nocdynp.total_nodes); + power = power + router->power * pppm_t; + } + if (link_bus_exist) { + if (nocdynp.type) + set_pppm(pppm_t, 1 * M_traffic_pattern * M * (nocdynp.min_ports - 1), + nocdynp.global_linked_ports, nocdynp.global_linked_ports, + nocdynp.global_linked_ports); + // reset traffic pattern; local port do not have router links + else + set_pppm(pppm_t, 1 * M_traffic_pattern * M * (nocdynp.min_ports), + nocdynp.global_linked_ports, nocdynp.global_linked_ports, + nocdynp.global_linked_ports); // reset traffic pattern + + link_bus_tot_per_Router.power = link_bus->power * pppm_t; + + set_pppm(pppm_t, nocdynp.total_nodes, nocdynp.total_nodes, + nocdynp.total_nodes, nocdynp.total_nodes); + power = power + link_bus_tot_per_Router.power * pppm_t; + } + } + else { + // init stats for runtime power (RTP) + stats_t.readAc.access = XML->sys.NoC[ithNoC].total_accesses; + rtp_stats = stats_t; + set_pppm(pppm_t, 1, 0, 0, 0); + if (router_exist) { + router->buffer.rt_power.readOp.dynamic = + (router->buffer.power.readOp.dynamic + + router->buffer.power.writeOp.dynamic) * + rtp_stats.readAc.access; + router->crossbar.rt_power.readOp.dynamic = + router->crossbar.power.readOp.dynamic * rtp_stats.readAc.access; + router->arbiter.rt_power.readOp.dynamic = + router->arbiter.power.readOp.dynamic * rtp_stats.readAc.access; + + router->rt_power = + router->rt_power + + (router->buffer.rt_power + router->crossbar.rt_power + + router->arbiter.rt_power) * + pppm_t + + router->power * pppm_lkg; // TDP power must be calculated first! + rt_power = rt_power + router->rt_power; + } + if (link_bus_exist) { + set_pppm(pppm_t, rtp_stats.readAc.access, 1, 1, rtp_stats.readAc.access); + link_bus->rt_power = link_bus->power * pppm_t; + rt_power = rt_power + link_bus->rt_power; + } + } +} + +void NoC::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + double M = M_traffic_pattern * nocdynp.duty_cycle; + /*only router as a whole has been applied the M_traffic_pattern(0.6 by + * default) factor in router.cc; When power of crossbars, arbiters, etc need + * to be displayed, the M_traffic_pattern factor need to be applied together + * with McPAT's extra traffic pattern. + * */ + if (is_tdp) { + cout << name << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * nocdynp.clockRate + << " W" << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (power.readOp.power_gated_leakage * + (long_channel + ? power.readOp.longer_channel_leakage / power.readOp.leakage + : 1)) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " + << rt_power.readOp.dynamic / nocdynp.executionTime << " W" << endl; + cout << endl; + + if (router_exist) { + cout << indent_str << "Router: " << endl; + cout << indent_str_next << "Area = " << router->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << router->power.readOp.dynamic * nocdynp.clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? router->power.readOp.longer_channel_leakage + : router->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout + << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->power.readOp.power_gated_with_long_channel_leakage + : router->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << router->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << router->rt_power.readOp.dynamic / nocdynp.executionTime << " W" + << endl; + cout << endl; + if (plevel > 2) { + cout << indent_str << indent_str << "Virtual Channel Buffer:" << endl; + cout << indent_str << indent_str_next << "Area = " + << router->buffer.area.get_area() * 1e-6 * nocdynp.input_ports + << " mm^2" << endl; + cout << indent_str << indent_str_next << "Peak Dynamic = " + << (router->buffer.power.readOp.dynamic + + router->buffer.power.writeOp.dynamic) * + nocdynp.min_ports * M * nocdynp.clockRate + << " W" << endl; + cout << indent_str << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? router->buffer.power.readOp.longer_channel_leakage * + nocdynp.input_ports + : router->buffer.power.readOp.leakage * + nocdynp.input_ports) + << " W" << endl; + if (power_gating) + cout << indent_str << indent_str_next + << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->buffer.power.readOp + .power_gated_with_long_channel_leakage + : router->buffer.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << indent_str_next << "Gate Leakage = " + << router->buffer.power.readOp.gate_leakage * nocdynp.input_ports + << " W" << endl; + cout << indent_str << indent_str_next << "Runtime Dynamic = " + << router->buffer.rt_power.readOp.dynamic / nocdynp.executionTime + << " W" << endl; + cout << endl; + cout << indent_str << indent_str << "Crossbar:" << endl; + cout << indent_str << indent_str_next + << "Area = " << router->crossbar.area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << indent_str_next << "Peak Dynamic = " + << router->crossbar.power.readOp.dynamic * nocdynp.clockRate * + nocdynp.min_ports * M + << " W" << endl; + cout << indent_str << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? router->crossbar.power.readOp.longer_channel_leakage + : router->crossbar.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << indent_str_next + << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->crossbar.power.readOp + .power_gated_with_long_channel_leakage + : router->crossbar.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << indent_str_next + << "Gate Leakage = " << router->crossbar.power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << indent_str_next << "Runtime Dynamic = " + << router->crossbar.rt_power.readOp.dynamic / nocdynp.executionTime + << " W" << endl; + cout << endl; + cout << indent_str << indent_str << "Arbiter:" << endl; + cout << indent_str << indent_str_next << "Peak Dynamic = " + << router->arbiter.power.readOp.dynamic * nocdynp.clockRate * + nocdynp.min_ports * M + << " W" << endl; + cout << indent_str << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? router->arbiter.power.readOp.longer_channel_leakage + : router->arbiter.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << indent_str_next + << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->arbiter.power.readOp + .power_gated_with_long_channel_leakage + : router->arbiter.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << indent_str_next + << "Gate Leakage = " << router->arbiter.power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << indent_str_next << "Runtime Dynamic = " + << router->arbiter.rt_power.readOp.dynamic / nocdynp.executionTime + << " W" << endl; + cout << endl; + } + } + if (link_bus_exist) { + cout << indent_str << (nocdynp.type ? "Per Router " : "") << link_name + << ": " << endl; + cout << indent_str_next + << "Area = " << link_bus_tot_per_Router.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << link_bus_tot_per_Router.power.readOp.dynamic * nocdynp.clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? link_bus_tot_per_Router.power.readOp.longer_channel_leakage + : link_bus_tot_per_Router.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? link_bus_tot_per_Router.power.readOp + .power_gated_with_long_channel_leakage + : link_bus_tot_per_Router.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " + << link_bus_tot_per_Router.power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << link_bus->rt_power.readOp.dynamic / nocdynp.executionTime << " W" + << endl; + cout << endl; + } + } + else { + // cout << indent_str_next << "Instruction Fetch Unit Peak + // Dynamic + //= + //" + //<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Subthreshold + // Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Gate + // Leakage + //= + //" + //<< ifu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Peak Dynamic = " << + // lsu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Load Store Unit Subthreshold Leakage = " << + // lsu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Gate Leakage = " << + // lsu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Peak Dynamic = " << + // mmu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Memory Management Unit Subthreshold Leakage = " + // << mmu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Gate Leakage = " << + // mmu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Peak Dynamic = " << + // exu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Execution Unit Subthreshold Leakage = " << + // exu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Gate Leakage = " << + // exu->rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void NoC::set_noc_param() { + nocdynp.type = XML->sys.NoC[ithNoC].type; + nocdynp.clockRate = XML->sys.NoC[ithNoC].clockrate; + nocdynp.clockRate *= 1e6; + nocdynp.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + + nocdynp.flit_size = XML->sys.NoC[ithNoC].flit_bits; + if (nocdynp.type) { + nocdynp.input_ports = XML->sys.NoC[ithNoC].input_ports; + nocdynp.output_ports = XML->sys.NoC[ithNoC].output_ports; // later minus 1 + nocdynp.min_ports = min(nocdynp.input_ports, nocdynp.output_ports); + nocdynp.global_linked_ports = + (nocdynp.input_ports - 1) + (nocdynp.output_ports - 1); + /* + * Except local i/o ports, all ports needs links( global_linked_ports); + * However only min_ports can be fully active simultaneously + * since the fewer number of ports (input or output ) is the bottleneck. + */ + } + else { + nocdynp.input_ports = 1; + nocdynp.output_ports = 1; + nocdynp.min_ports = min(nocdynp.input_ports, nocdynp.output_ports); + nocdynp.global_linked_ports = 1; + } + + nocdynp.virtual_channel_per_port = + XML->sys.NoC[ithNoC].virtual_channel_per_port; + nocdynp.input_buffer_entries_per_vc = + XML->sys.NoC[ithNoC].input_buffer_entries_per_vc; + + nocdynp.horizontal_nodes = XML->sys.NoC[ithNoC].horizontal_nodes; + nocdynp.vertical_nodes = XML->sys.NoC[ithNoC].vertical_nodes; + nocdynp.total_nodes = nocdynp.horizontal_nodes * nocdynp.vertical_nodes; + nocdynp.duty_cycle = XML->sys.NoC[ithNoC].duty_cycle; + nocdynp.has_global_link = XML->sys.NoC[ithNoC].has_global_link; + nocdynp.link_throughput = XML->sys.NoC[ithNoC].link_throughput; + nocdynp.link_latency = XML->sys.NoC[ithNoC].link_latency; + nocdynp.chip_coverage = XML->sys.NoC[ithNoC].chip_coverage; + nocdynp.route_over_perc = XML->sys.NoC[ithNoC].route_over_perc; + + assert(nocdynp.chip_coverage <= 1); + assert(nocdynp.route_over_perc <= 1); + + if (nocdynp.type) + name = "NOC"; + else + name = "BUSES"; + + if (XML->sys.NoC[ithNoC].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.NoC[ithNoC].vdd; + interface_ip.lop_Vdd = XML->sys.NoC[ithNoC].vdd; + interface_ip.lstp_Vdd = XML->sys.NoC[ithNoC].vdd; + } + + if (XML->sys.NoC[ithNoC].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.NoC[ithNoC].power_gating_vcc; + } +} + +NoC ::~NoC() { + if (router) { + delete router; + router = 0; + } + if (link_bus) { + delete link_bus; + link_bus = 0; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/noc.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/noc.h new file mode 100644 index 0000000000..3cf23e8312 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/noc.h @@ -0,0 +1,77 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef NOC_H_ +#define NOC_H_ +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/parameter.h" +#include "cacti/router.h" +#include "interconnect.h" +#include "logic.h" +using namespace cacti; + +class NoC : public Component { + public: + ParseXML *XML; + int ithNoC; + InputParameter interface_ip; + double link_len; + double executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + Router *router; + interconnect *link_bus; + NoCParam nocdynp; + uca_org_t local_result; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + Component link_bus_tot_per_Router; + bool link_bus_exist; + bool router_exist; + string name, link_name; + double M_traffic_pattern; + NoC(ParseXML *XML_interface, int ithNoC_, InputParameter *interface_ip_, + double M_traffic_pattern_ = 0.6, double link_len_ = 0); + void set_noc_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + void init_link_bus(double link_len_); + void init_router(); + void computeEnergy_link_bus(bool is_tdp = true); + void displayEnergy_link_bus(uint32_t indent = 0, int plevel = 100, + bool is_tdp = true); + ~NoC(); +}; + +#endif /* NOC_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/processor.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/processor.cc new file mode 100644 index 0000000000..1a0310d49e --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/processor.cc @@ -0,0 +1,1188 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#include "processor.h" +#include +#include +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "array.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/parameter.h" +#include "version.h" + +Processor::Processor(ParseXML *XML_interface) + : XML(XML_interface), // TODO: using one global copy may have problems. + mc(0), + niu(0), + pcie(0), + flashcontroller(0) { + /* + * placement and routing overhead is 10%, core scales worse than cache 40% is + * accumulated from 90 to 22nm There is no point to have heterogeneous memory + * controller on chip, thus McPAT only support homogeneous memory + * controllers. + */ + int i; + set_proc_param(); + if (procdynp.homoCore) + numCore = procdynp.numCore == 0 ? 0 : 1; + else + numCore = procdynp.numCore; + + if (procdynp.homoL2) + numL2 = procdynp.numL2 == 0 ? 0 : 1; + else + numL2 = procdynp.numL2; + + if (XML->sys.Private_L2 && numCore != numL2) { + cout << "Number of private L2 does not match number of cores" << endl; + exit(0); + } + + if (procdynp.homoL3) + numL3 = procdynp.numL3 == 0 ? 0 : 1; + else + numL3 = procdynp.numL3; + + if (procdynp.homoNOC) + numNOC = procdynp.numNOC == 0 ? 0 : 1; + else + numNOC = procdynp.numNOC; + + // if (!procdynp.homoNOC) + // { + // cout<<"Current McPAT does not support heterogeneous NOC"<area.get_area() * procdynp.numCore); + area.set_area( + area.get_area() + + core.area.get_area()); // placement and routing overhead is + // 10%, core scales worse than cache + // 40% is accumulated from 90 to 22nm + } + else { + core.area.set_area(core.area.get_area() + cores[i]->area.get_area()); + area.set_area(area.get_area() + + cores[i]->area.get_area()); // placement and routing + // overhead is 10%, core scales + // worse than cache 40% is + // accumulated from 90 to 22nm + } + } + + if (!XML->sys.Private_L2) { + if (numL2 > 0) + for (i = 0; i < numL2; i++) { + l2array.push_back(new SharedCache(XML, i, &interface_ip)); + if (procdynp.homoL2) { + l2.area.set_area(l2.area.get_area() + + l2array[i]->area.get_area() * procdynp.numL2); + area.set_area(area.get_area() + + l2.area.get_area()); // placement and routing overhead + // is 10%, l2 scales worse than + // cache 40% is accumulated from + // 90 to 22nm + } + else { + l2.area.set_area(l2.area.get_area() + l2array[i]->area.get_area()); + area.set_area( + area.get_area() + + l2array[i]->area.get_area()); // placement and routing + // overhead is 10%, l2 + // scales worse than cache + // 40% is accumulated from + // 90 to 22nm + } + } + } + + if (numL3 > 0) + for (i = 0; i < numL3; i++) { + l3array.push_back(new SharedCache(XML, i, &interface_ip, L3)); + if (procdynp.homoL3) { + l3.area.set_area(l3.area.get_area() + + l3array[i]->area.get_area() * procdynp.numL3); + area.set_area( + area.get_area() + + l3.area.get_area()); // placement and routing overhead is + // 10%, l3 scales worse than cache + // 40% is accumulated from 90 to 22nm + } + else { + l3.area.set_area(l3.area.get_area() + l3array[i]->area.get_area()); + area.set_area(area.get_area() + + l3array[i]->area.get_area()); // placement and routing + // overhead is 10%, l3 + // scales worse than cache + // 40% is accumulated from + // 90 to 22nm + } + } + if (numL1Dir > 0) + for (i = 0; i < numL1Dir; i++) { + l1dirarray.push_back(new SharedCache(XML, i, &interface_ip, L1Directory)); + if (procdynp.homoL1Dir) { + l1dir.area.set_area(l1dir.area.get_area() + + l1dirarray[i]->area.get_area() * procdynp.numL1Dir); + area.set_area(area.get_area() + + l1dir.area.get_area()); // placement and routing overhead + // is 10%, l1dir scales worse + // than cache 40% is accumulated + // from 90 to 22nm + power = power + l1dir.power; + rt_power = rt_power + l1dir.rt_power; + } + else { + l1dir.area.set_area(l1dir.area.get_area() + + l1dirarray[i]->area.get_area()); + area.set_area(area.get_area() + l1dirarray[i]->area.get_area()); + } + } + + if (numL2Dir > 0) + for (i = 0; i < numL2Dir; i++) { + l2dirarray.push_back(new SharedCache(XML, i, &interface_ip, L2Directory)); + if (procdynp.homoL2Dir) { + l2dir.area.set_area(l2dir.area.get_area() + + l2dirarray[i]->area.get_area() * procdynp.numL2Dir); + area.set_area(area.get_area() + + l2dir.area.get_area()); // placement and routing overhead + // is 10%, l2dir scales worse + // than cache 40% is accumulated + // from 90 to 22nm + } + else { + l2dir.area.set_area(l2dir.area.get_area() + + l2dirarray[i]->area.get_area()); + area.set_area(area.get_area() + l2dirarray[i]->area.get_area()); + } + } + + if (XML->sys.mc.number_mcs > 0 && XML->sys.mc.memory_channels_per_mc > 0) { + mc = new MemoryController(XML, &interface_ip, MC); + mcs.area.set_area(mcs.area.get_area() + + mc->area.get_area() * XML->sys.mc.number_mcs); + area.set_area(area.get_area() + + mc->area.get_area() * XML->sys.mc.number_mcs); + } + + if (XML->sys.flashc.number_mcs > 0) // flash controller + { + flashcontroller = new FlashController(XML, &interface_ip); + double number_fcs = flashcontroller->fcp.num_mcs; + flashcontrollers.area.set_area(flashcontrollers.area.get_area() + + flashcontroller->area.get_area() * + number_fcs); + area.set_area(area.get_area() + flashcontrollers.area.get_area()); + } + + if (XML->sys.niu.number_units > 0) { + niu = new NIUController(XML, &interface_ip); + nius.area.set_area(nius.area.get_area() + + niu->area.get_area() * XML->sys.niu.number_units); + area.set_area(area.get_area() + + niu->area.get_area() * XML->sys.niu.number_units); + } + + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + pcie = new PCIeController(XML, &interface_ip); + pcies.area.set_area(pcies.area.get_area() + + pcie->area.get_area() * XML->sys.pcie.number_units); + area.set_area(area.get_area() + + pcie->area.get_area() * XML->sys.pcie.number_units); + } + + if (numNOC > 0) { + for (i = 0; i < numNOC; i++) { + if (XML->sys.NoC[i].type) { // First add up area of routers if NoC is + // used + nocs.push_back(new NoC(XML, i, &interface_ip, 1)); + if (procdynp.homoNOC) { + noc.area.set_area(noc.area.get_area() + + nocs[i]->area.get_area() * procdynp.numNOC); + area.set_area(area.get_area() + noc.area.get_area()); + } + else { + noc.area.set_area(noc.area.get_area() + nocs[i]->area.get_area()); + area.set_area(area.get_area() + nocs[i]->area.get_area()); + } + } + else { // Bus based interconnect + nocs.push_back( + new NoC(XML, i, &interface_ip, 1, + sqrt(area.get_area() * XML->sys.NoC[i].chip_coverage))); + if (procdynp.homoNOC) { + noc.area.set_area(noc.area.get_area() + + nocs[i]->area.get_area() * procdynp.numNOC); + area.set_area(area.get_area() + noc.area.get_area()); + } + else { + noc.area.set_area(noc.area.get_area() + nocs[i]->area.get_area()); + area.set_area(area.get_area() + nocs[i]->area.get_area()); + } + } + } + + /* + * Compute global links associated with each NOC, if any. This must be done + * at the end (even after the NOC router part) since the total chip area + * must be obtain to decide the link routing + */ + for (i = 0; i < numNOC; i++) { + if (nocs[i]->nocdynp.has_global_link && XML->sys.NoC[i].type) { + nocs[i]->init_link_bus( + sqrt(area.get_area() * + XML->sys.NoC[i].chip_coverage)); // compute global links + if (procdynp.homoNOC) { + noc.area.set_area(noc.area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes * procdynp.numNOC); + area.set_area(area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes * procdynp.numNOC); + } + else { + noc.area.set_area(noc.area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes); + area.set_area(area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes); + } + } + } + } + + // //clock power + // globalClock.init_wire_external(is_default, &interface_ip); + // globalClock.clk_area =area*1e6; //change it from mm^2 to um^2 + // globalClock.end_wiring_level =5;//toplevel metal + // globalClock.start_wiring_level =5;//toplevel metal + // globalClock.l_ip.with_clock_grid=false;//global clock does not drive local + // final nodes globalClock.optimize_wire(); +} + +void Processor::compute() { + int i; + double pppm_t[4] = {1, 1, 1, 1}; + + for (i = 0; i < numCore; i++) { + cores[i]->computeEnergy(); + cores[i]->computeEnergy(false); + if (procdynp.homoCore) { + set_pppm(pppm_t, cores[i]->clockRate * procdynp.numCore, procdynp.numCore, + procdynp.numCore, procdynp.numCore); + core.power = core.power + cores[i]->power * pppm_t; + set_pppm(pppm_t, 1 / cores[i]->executionTime, procdynp.numCore, + procdynp.numCore, procdynp.numCore); + core.rt_power = core.rt_power + cores[i]->rt_power * pppm_t; + power = power + core.power; + rt_power = rt_power + core.rt_power; + } + else { + set_pppm(pppm_t, cores[i]->clockRate, 1, 1, 1); + core.power = core.power + cores[i]->power * pppm_t; + power = power + cores[i]->power * pppm_t; + + set_pppm(pppm_t, 1 / cores[i]->executionTime, 1, 1, 1); + core.rt_power = core.rt_power + cores[i]->rt_power * pppm_t; + rt_power = rt_power + cores[i]->rt_power * pppm_t; + } + } + + if (!XML->sys.Private_L2) { + if (numL2 > 0) + for (i = 0; i < numL2; i++) { + l2array[i]->computeEnergy(); + l2array[i]->computeEnergy(false); + if (procdynp.homoL2) { + set_pppm(pppm_t, l2array[i]->cachep.clockRate * procdynp.numL2, + procdynp.numL2, procdynp.numL2, procdynp.numL2); + l2.power = l2.power + l2array[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l2array[i]->cachep.executionTime, procdynp.numL2, + procdynp.numL2, procdynp.numL2); + l2.rt_power = l2.rt_power + l2array[i]->rt_power * pppm_t; + power = power + l2.power; + rt_power = rt_power + l2.rt_power; + } + else { + set_pppm(pppm_t, l2array[i]->cachep.clockRate, 1, 1, 1); + l2.power = l2.power + l2array[i]->power * pppm_t; + power = power + l2array[i]->power * pppm_t; + ; + set_pppm(pppm_t, 1 / l2array[i]->cachep.executionTime, 1, 1, 1); + l2.rt_power = l2.rt_power + l2array[i]->rt_power * pppm_t; + rt_power = rt_power + l2array[i]->rt_power * pppm_t; + } + } + } + + if (numL3 > 0) + for (i = 0; i < numL3; i++) { + l3array[i]->computeEnergy(); + l3array[i]->computeEnergy(false); + if (procdynp.homoL3) { + set_pppm(pppm_t, l3array[i]->cachep.clockRate * procdynp.numL3, + procdynp.numL3, procdynp.numL3, procdynp.numL3); + l3.power = l3.power + l3array[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l3array[i]->cachep.executionTime, procdynp.numL3, + procdynp.numL3, procdynp.numL3); + l3.rt_power = l3.rt_power + l3array[i]->rt_power * pppm_t; + power = power + l3.power; + rt_power = rt_power + l3.rt_power; + } + else { + set_pppm(pppm_t, l3array[i]->cachep.clockRate, 1, 1, 1); + l3.power = l3.power + l3array[i]->power * pppm_t; + power = power + l3array[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l3array[i]->cachep.executionTime, 1, 1, 1); + l3.rt_power = l3.rt_power + l3array[i]->rt_power * pppm_t; + rt_power = rt_power + l3array[i]->rt_power * pppm_t; + } + } + if (numL1Dir > 0) + for (i = 0; i < numL1Dir; i++) { + l1dirarray[i]->computeEnergy(); + l1dirarray[i]->computeEnergy(false); + if (procdynp.homoL1Dir) { + set_pppm(pppm_t, l1dirarray[i]->cachep.clockRate * procdynp.numL1Dir, + procdynp.numL1Dir, procdynp.numL1Dir, procdynp.numL1Dir); + l1dir.power = l1dir.power + l1dirarray[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l1dirarray[i]->cachep.executionTime, + procdynp.numL1Dir, procdynp.numL1Dir, procdynp.numL1Dir); + l1dir.rt_power = l1dir.rt_power + l1dirarray[i]->rt_power * pppm_t; + power = power + l1dir.power; + rt_power = rt_power + l1dir.rt_power; + } + else { + set_pppm(pppm_t, l1dirarray[i]->cachep.clockRate, 1, 1, 1); + l1dir.power = l1dir.power + l1dirarray[i]->power * pppm_t; + power = power + l1dirarray[i]->power; + set_pppm(pppm_t, 1 / l1dirarray[i]->cachep.executionTime, 1, 1, 1); + l1dir.rt_power = l1dir.rt_power + l1dirarray[i]->rt_power * pppm_t; + rt_power = rt_power + l1dirarray[i]->rt_power; + } + } + + if (numL2Dir > 0) + for (i = 0; i < numL2Dir; i++) { + l2dirarray[i]->computeEnergy(); + l2dirarray[i]->computeEnergy(false); + if (procdynp.homoL2Dir) { + set_pppm(pppm_t, l2dirarray[i]->cachep.clockRate * procdynp.numL2Dir, + procdynp.numL2Dir, procdynp.numL2Dir, procdynp.numL2Dir); + l2dir.power = l2dir.power + l2dirarray[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l2dirarray[i]->cachep.executionTime, + procdynp.numL2Dir, procdynp.numL2Dir, procdynp.numL2Dir); + l2dir.rt_power = l2dir.rt_power + l2dirarray[i]->rt_power * pppm_t; + power = power + l2dir.power; + rt_power = rt_power + l2dir.rt_power; + } + else { + set_pppm(pppm_t, l2dirarray[i]->cachep.clockRate, 1, 1, 1); + l2dir.power = l2dir.power + l2dirarray[i]->power * pppm_t; + power = power + l2dirarray[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l2dirarray[i]->cachep.executionTime, 1, 1, 1); + l2dir.rt_power = l2dir.rt_power + l2dirarray[i]->rt_power * pppm_t; + rt_power = rt_power + l2dirarray[i]->rt_power * pppm_t; + } + } + + if (XML->sys.mc.number_mcs > 0 && XML->sys.mc.memory_channels_per_mc > 0) { + mc->computeEnergy(); + mc->computeEnergy(false); + set_pppm(pppm_t, XML->sys.mc.number_mcs * mc->mcp.clockRate, + XML->sys.mc.number_mcs, XML->sys.mc.number_mcs, + XML->sys.mc.number_mcs); + mcs.power = mc->power * pppm_t; + power = power + mcs.power; + set_pppm(pppm_t, 1 / mc->mcp.executionTime, XML->sys.mc.number_mcs, + XML->sys.mc.number_mcs, XML->sys.mc.number_mcs); + mcs.rt_power = mc->rt_power * pppm_t; + rt_power = rt_power + mcs.rt_power; + } + + if (XML->sys.flashc.number_mcs > 0) // flash controller + { + flashcontroller->computeEnergy(); + flashcontroller->computeEnergy(false); + double number_fcs = flashcontroller->fcp.num_mcs; + set_pppm(pppm_t, number_fcs, number_fcs, number_fcs, number_fcs); + flashcontrollers.power = flashcontroller->power * pppm_t; + power = power + flashcontrollers.power; + set_pppm(pppm_t, number_fcs, number_fcs, number_fcs, number_fcs); + flashcontrollers.rt_power = flashcontroller->rt_power * pppm_t; + rt_power = rt_power + flashcontrollers.rt_power; + } + + if (XML->sys.niu.number_units > 0) { + niu->computeEnergy(); + niu->computeEnergy(false); + set_pppm(pppm_t, XML->sys.niu.number_units * niu->niup.clockRate, + XML->sys.niu.number_units, XML->sys.niu.number_units, + XML->sys.niu.number_units); + nius.power = niu->power * pppm_t; + power = power + nius.power; + set_pppm(pppm_t, XML->sys.niu.number_units * niu->niup.clockRate, + XML->sys.niu.number_units, XML->sys.niu.number_units, + XML->sys.niu.number_units); + nius.rt_power = niu->rt_power * pppm_t; + rt_power = rt_power + nius.rt_power; + } + + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + pcie->computeEnergy(); + pcie->computeEnergy(false); + set_pppm(pppm_t, XML->sys.pcie.number_units * pcie->pciep.clockRate, + XML->sys.pcie.number_units, XML->sys.pcie.number_units, + XML->sys.pcie.number_units); + pcies.power = pcie->power * pppm_t; + power = power + pcies.power; + set_pppm(pppm_t, XML->sys.pcie.number_units * pcie->pciep.clockRate, + XML->sys.pcie.number_units, XML->sys.pcie.number_units, + XML->sys.pcie.number_units); + pcies.rt_power = pcie->rt_power * pppm_t; + rt_power = rt_power + pcies.rt_power; + } + + if (numNOC > 0) { + // Compute energy of NoC (w or w/o links) or buses + for (i = 0; i < numNOC; i++) { + nocs[i]->computeEnergy(); + nocs[i]->computeEnergy(false); + if (procdynp.homoNOC) { + set_pppm(pppm_t, procdynp.numNOC * nocs[i]->nocdynp.clockRate, + procdynp.numNOC, procdynp.numNOC, procdynp.numNOC); + noc.power = noc.power + nocs[i]->power * pppm_t; + set_pppm(pppm_t, 1 / nocs[i]->nocdynp.executionTime, procdynp.numNOC, + procdynp.numNOC, procdynp.numNOC); + noc.rt_power = noc.rt_power + nocs[i]->rt_power * pppm_t; + power = power + noc.power; + rt_power = rt_power + noc.rt_power; + } + else { + set_pppm(pppm_t, nocs[i]->nocdynp.clockRate, 1, 1, 1); + noc.power = noc.power + nocs[i]->power * pppm_t; + power = power + nocs[i]->power * pppm_t; + set_pppm(pppm_t, 1 / nocs[i]->nocdynp.executionTime, 1, 1, 1); + noc.rt_power = noc.rt_power + nocs[i]->rt_power * pppm_t; + rt_power = rt_power + nocs[i]->rt_power * pppm_t; + } + } + } + + // //clock power + // globalClock.init_wire_external(is_default, &interface_ip); + // globalClock.clk_area =area*1e6; //change it from mm^2 to um^2 + // globalClock.end_wiring_level =5;//toplevel metal + // globalClock.start_wiring_level =5;//toplevel metal + // globalClock.l_ip.with_clock_grid=false;//global clock does not drive local + // final nodes globalClock.optimize_wire(); +} + +void Processor::getPower(Power *value) { + bool long_channel = XML->sys.longer_channel_device; + + if (value) { + value->core.area = core.area.get_area() * 1e-6; + value->core.peakDynamic = core.power.readOp.dynamic; + value->core.subthresholdLeakage = + long_channel ? core.power.readOp.longer_channel_leakage + : core.power.readOp.leakage; + value->core.gateLeakage = core.power.readOp.gate_leakage; + value->core.runtimeDynamic = core.rt_power.readOp.dynamic; + + if (!XML->sys.Private_L2) { + if (numL2 > 0) { + value->level2.area = l2.area.get_area() * 1e-6; + value->level2.peakDynamic = l2.power.readOp.dynamic; + value->level2.subthresholdLeakage = + long_channel ? l2.power.readOp.longer_channel_leakage + : l2.power.readOp.leakage; + value->level2.gateLeakage = l2.power.readOp.gate_leakage; + value->level2.runtimeDynamic = l2.rt_power.readOp.dynamic; + } + } + + if (numL3 > 0) { + value->level3.area = l3.area.get_area() * 1e-6; + value->level3.peakDynamic = l3.power.readOp.dynamic; + value->level3.subthresholdLeakage = + long_channel ? l3.power.readOp.longer_channel_leakage + : l3.power.readOp.leakage; + value->level3.gateLeakage = l3.power.readOp.gate_leakage; + value->level3.runtimeDynamic = l3.rt_power.readOp.dynamic; + } + } +} + +void Processor::displayDeviceType(int device_type_, uint32_t indent) { + string indent_str(indent, ' '); + + switch (device_type_) { + case 0: + cout << indent_str << "Device Type= " + << "ITRS high performance device type" << endl; + break; + case 1: + cout << indent_str << "Device Type= " + << "ITRS low standby power device type" << endl; + break; + case 2: + cout << indent_str << "Device Type= " + << "ITRS low operating power device type" << endl; + break; + case 3: + cout << indent_str << "Device Type= " + << "LP-DRAM device type" << endl; + break; + case 4: + cout << indent_str << "Device Type= " + << "COMM-DRAM device type" << endl; + break; + default: { + cout << indent_str << "Unknown Device Type" << endl; + exit(0); + } + } +} + +void Processor::displayInterconnectType(int interconnect_type_, + uint32_t indent) { + string indent_str(indent, ' '); + + switch (interconnect_type_) { + case 0: + cout << indent_str << "Interconnect metal projection= " + << "aggressive interconnect technology projection" << endl; + break; + case 1: + cout << indent_str << "Interconnect metal projection= " + << "conservative interconnect technology projection" << endl; + break; + default: { + cout << indent_str << "Unknown Interconnect Projection Type" << endl; + exit(0); + } + } +} + +void Processor::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + int i; + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + if (is_tdp) { + if (plevel < 5) { + cout + << "\nMcPAT (version " << VER_MAJOR << "." << VER_MINOR << " of " + << VER_UPDATE << ") results (current print level is " << plevel + << ", please increase print level to see the details in components): " + << endl; + } + else { + cout << "\nMcPAT (version " << VER_MAJOR << "." << VER_MINOR << " of " + << VER_UPDATE << ") results (current print level is 5)" << endl; + } + cout << "******************************************************************" + "***********************" + << endl; + cout << indent_str << "Technology " << XML->sys.core_tech_node << " nm" + << endl; + // cout <sys.interconnect_projection_type<sys.interconnect_projection_type, indent); + cout << indent_str << "Core clock Rate(MHz) " << XML->sys.core[0].clock_rate + << endl; + cout << endl; + cout << "******************************************************************" + "***********************" + << endl; + cout << "Processor: " << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << "Peak Power = " + << power.readOp.dynamic + + (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + + power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << "Total Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + + power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic + << " W" << endl; + cout << endl; + if (numCore > 0) { + cout << indent_str << "Total Cores: " << XML->sys.number_of_cores + << " cores " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << core.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << core.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? core.power.readOp.longer_channel_leakage + : core.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? core.power.readOp.power_gated_with_long_channel_leakage + : core.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << core.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << core.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (!XML->sys.Private_L2) { + if (numL2 > 0) { + cout << indent_str << "Total L2s: " << endl; + displayDeviceType(XML->sys.L2[0].device_type, indent); + cout << indent_str_next << "Area = " << l2.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l2.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l2.power.readOp.longer_channel_leakage + : l2.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l2.power.readOp.power_gated_with_long_channel_leakage + : l2.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l2.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l2.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + } + if (numL3 > 0) { + cout << indent_str << "Total L3s: " << endl; + displayDeviceType(XML->sys.L3[0].device_type, indent); + cout << indent_str_next << "Area = " << l3.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l3.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l3.power.readOp.longer_channel_leakage + : l3.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l3.power.readOp.power_gated_with_long_channel_leakage + : l3.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l3.power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l3.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (numL1Dir > 0) { + cout << indent_str << "Total First Level Directory: " << endl; + displayDeviceType(XML->sys.L1Directory[0].device_type, indent); + cout << indent_str_next << "Area = " << l1dir.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l1dir.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l1dir.power.readOp.longer_channel_leakage + : l1dir.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l1dir.power.readOp.power_gated_with_long_channel_leakage + : l1dir.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l1dir.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l1dir.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (numL2Dir > 0) { + cout << indent_str << "Total Second Level Directory: " << endl; + displayDeviceType(XML->sys.L1Directory[0].device_type, indent); + cout << indent_str_next << "Area = " << l2dir.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l2dir.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l2dir.power.readOp.longer_channel_leakage + : l2dir.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l2dir.power.readOp.power_gated_with_long_channel_leakage + : l2dir.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l2dir.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l2dir.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (numNOC > 0) { + cout << indent_str << "Total NoCs (Network/Bus): " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << noc.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << noc.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? noc.power.readOp.longer_channel_leakage + : noc.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? noc.power.readOp.power_gated_with_long_channel_leakage + : noc.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << noc.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << noc.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (XML->sys.mc.number_mcs > 0 && XML->sys.mc.memory_channels_per_mc > 0) { + cout << indent_str << "Total MCs: " << XML->sys.mc.number_mcs + << " Memory Controllers " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << mcs.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << mcs.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? mcs.power.readOp.longer_channel_leakage + : mcs.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? mcs.power.readOp.power_gated_with_long_channel_leakage + : mcs.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << mcs.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << mcs.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (XML->sys.flashc.number_mcs > 0) { + cout << indent_str + << "Total Flash/SSD Controllers: " << flashcontroller->fcp.num_mcs + << " Flash/SSD Controllers " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next + << "Area = " << flashcontrollers.area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << flashcontrollers.power.readOp.dynamic << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? flashcontrollers.power.readOp.longer_channel_leakage + : flashcontrollers.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? flashcontrollers.power.readOp + .power_gated_with_long_channel_leakage + : flashcontrollers.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << flashcontrollers.power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << flashcontrollers.rt_power.readOp.dynamic + << " W" << endl; + cout << endl; + } + if (XML->sys.niu.number_units > 0) { + cout << indent_str << "Total NIUs: " << niu->niup.num_units + << " Network Interface Units " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << nius.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << nius.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? nius.power.readOp.longer_channel_leakage + : nius.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? nius.power.readOp.power_gated_with_long_channel_leakage + : nius.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << nius.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << nius.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + cout << indent_str << "Total PCIes: " << pcie->pciep.num_units + << " PCIe Controllers " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << pcies.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << pcies.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? pcies.power.readOp.longer_channel_leakage + : pcies.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? pcies.power.readOp.power_gated_with_long_channel_leakage + : pcies.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << pcies.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << pcies.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + cout << "******************************************************************" + "***********************" + << endl; + if (plevel > 1) { + for (i = 0; i < numCore; i++) { + cores[i]->displayEnergy(indent + 4, plevel, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (!XML->sys.Private_L2) { + for (i = 0; i < numL2; i++) { + l2array[i]->displayEnergy(indent + 4, is_tdp); + cout << "************************************************************" + "*****************************" + << endl; + } + } + for (i = 0; i < numL3; i++) { + l3array[i]->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + for (i = 0; i < numL1Dir; i++) { + l1dirarray[i]->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + for (i = 0; i < numL2Dir; i++) { + l2dirarray[i]->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.mc.number_mcs > 0 && + XML->sys.mc.memory_channels_per_mc > 0) { + mc->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.flashc.number_mcs > 0 && + XML->sys.flashc.memory_channels_per_mc > 0) { + flashcontroller->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.niu.number_units > 0) { + niu->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + pcie->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + + for (i = 0; i < numNOC; i++) { + nocs[i]->displayEnergy(indent + 4, plevel, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + } + } + else { + } +} + +void Processor::set_proc_param() { + bool debug = false; + + procdynp.homoCore = bool(debug ? 1 : XML->sys.homogeneous_cores); + procdynp.homoL2 = bool(debug ? 1 : XML->sys.homogeneous_L2s); + procdynp.homoL3 = bool(debug ? 1 : XML->sys.homogeneous_L3s); + procdynp.homoNOC = bool(debug ? 1 : XML->sys.homogeneous_NoCs); + procdynp.homoL1Dir = bool(debug ? 1 : XML->sys.homogeneous_L1Directories); + procdynp.homoL2Dir = bool(debug ? 1 : XML->sys.homogeneous_L2Directories); + + procdynp.numCore = XML->sys.number_of_cores; + procdynp.numL2 = XML->sys.number_of_L2s; + procdynp.numL3 = XML->sys.number_of_L3s; + procdynp.numNOC = XML->sys.number_of_NoCs; + procdynp.numL1Dir = XML->sys.number_of_L1Directories; + procdynp.numL2Dir = XML->sys.number_of_L2Directories; + procdynp.numMC = XML->sys.mc.number_mcs; + procdynp.numMCChannel = XML->sys.mc.memory_channels_per_mc; + + // if (procdynp.numCore<1) + // { + // cout<<" The target processor should at least have one core on + // chip." + //<2) + // { + // cout <<"number of NOCs must be 1 (only global NOCs) or 2 (both global + // and local NOCs)"<sys.device_type; + interface_ip.data_arr_peri_global_tech_type = + debug ? 0 : XML->sys.device_type; + interface_ip.tag_arr_ram_cell_tech_type = debug ? 0 : XML->sys.device_type; + interface_ip.tag_arr_peri_global_tech_type = debug ? 0 : XML->sys.device_type; + + interface_ip.specific_hp_vdd = false; + interface_ip.specific_lop_vdd = false; + interface_ip.specific_lstp_vdd = false; + + interface_ip.specific_vcc_min = false; + + interface_ip.ic_proj_type = debug ? 0 : XML->sys.interconnect_projection_type; + interface_ip.delay_wt = + 100; // Fixed number, make sure timing can be satisfied. + interface_ip.area_wt = 0; // Fixed number, This is used to exhaustive search + // for individual components. + interface_ip.dynamic_power_wt = 100; // Fixed number, This is used to + // exhaustive search for individual + // components. + interface_ip.leakage_power_wt = 0; + interface_ip.cycle_time_wt = 0; + + interface_ip.delay_dev = + 10000; // Fixed number, make sure timing can be satisfied. + interface_ip.area_dev = 10000; // Fixed number, This is used to exhaustive + // search for individual components. + interface_ip.dynamic_power_dev = 10000; // Fixed number, This is used to + // exhaustive search for individual + // components. + interface_ip.leakage_power_dev = 10000; + interface_ip.cycle_time_dev = 10000; + + interface_ip.ed = 2; + interface_ip.burst_len = 1; // parameters are fixed for processor section, + // since memory is processed separately + interface_ip.int_prefetch_w = 1; + interface_ip.page_sz_bits = 0; + interface_ip.temp = debug ? 360 : XML->sys.temperature; + interface_ip.F_sz_nm = + debug ? 90 : XML->sys.core_tech_node; // XML->sys.core_tech_node; + interface_ip.F_sz_um = interface_ip.F_sz_nm / 1000; + + //***********This section of code does not have real meaning, they are just to + // ensure all data will have initial value to prevent errors. They will be + // overridden during each components initialization + interface_ip.cache_sz = 64; + interface_ip.line_sz = 1; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = 64; + interface_ip.access_mode = 2; + + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + + interface_ip.is_main_mem = false; + interface_ip.rpters_in_htree = true; + interface_ip.ver_htree_wires_over_array = 0; + interface_ip.broadcast_addr_din_over_ver_htrees = 0; + + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 1; + interface_ip.nuca = 0; + interface_ip.nuca_bank_count = 0; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.force_cache_config = false; + interface_ip.power_gating = XML->sys.power_gating; + + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 0; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + } + interface_ip.force_wiretype = false; + interface_ip.print_detail = 1; + interface_ip.add_ecc_b_ = true; +} + +Processor::~Processor() { + while (!cores.empty()) { + delete cores.back(); + cores.pop_back(); + } + while (!l2array.empty()) { + delete l2array.back(); + l2array.pop_back(); + } + while (!l3array.empty()) { + delete l3array.back(); + l3array.pop_back(); + } + while (!nocs.empty()) { + delete nocs.back(); + nocs.pop_back(); + } + while (!l1dirarray.empty()) { + delete l1dirarray.back(); + l1dirarray.pop_back(); + } + while (!l2dirarray.empty()) { + delete l2dirarray.back(); + l2dirarray.pop_back(); + } + if (mc) { + delete mc; + mc = 0; + } + if (niu) { + delete niu; + niu = 0; + } + if (pcie) { + delete pcie; + pcie = 0; + } + if (flashcontroller) { + delete flashcontroller; + flashcontroller = 0; + } +}; diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/processor.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/processor.h new file mode 100644 index 0000000000..1ce5b9410d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/processor.h @@ -0,0 +1,102 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#ifndef PROCESSOR_H_ +#define PROCESSOR_H_ + +#include +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/arbiter.h" +#include "cacti/area.h" +#include "cacti/decoder.h" +#include "cacti/parameter.h" +#include "cacti/router.h" +#include "core.h" +#include "iocontrollers.h" +#include "memoryctrl.h" +#include "noc.h" +#include "sharedcache.h" + +struct PowerGroup { + double area; // Unit: mm^2 + double peakDynamic; // Unit: W + double subthresholdLeakage; // Unit: W + double gateLeakage; // Unit: W + double runtimeDynamic; // Unit: W + + PowerGroup() + : area(0.0), + peakDynamic(0.0), + subthresholdLeakage(0.0), + gateLeakage(0.0), + runtimeDynamic(0.0) {} +}; + +struct Power { + PowerGroup core; // Total cores including all per-core elements + PowerGroup level2; + PowerGroup level3; +}; + +using namespace cacti; + +class Processor : public Component { + public: + ParseXML *XML; + vector cores; + vector l2array; + vector l3array; + vector l1dirarray; + vector l2dirarray; + vector nocs; + MemoryController *mc; + NIUController *niu; + PCIeController *pcie; + FlashController *flashcontroller; + InputParameter interface_ip; + ProcParam procdynp; + // wire globalInterconnect; + // clock_network globalClock; + Component core, l2, l3, l1dir, l2dir, noc, mcs, cc, nius, pcies, + flashcontrollers; + int numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir; + Processor(ParseXML *XML_interface); + void compute(); + void set_proc_param(); + void getPower(Power *); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + void displayDeviceType(int device_type_, uint32_t indent = 0); + void displayInterconnectType(int interconnect_type_, uint32_t indent = 0); + ~Processor(); +}; + +#endif /* PROCESSOR_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/sharedcache.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/sharedcache.cc new file mode 100644 index 0000000000..a847a2f33c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/sharedcache.cc @@ -0,0 +1,1454 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "sharedcache.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "array.h" +#include "cacti/arbiter.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +#include "logic.h" + +SharedCache::SharedCache(ParseXML *XML_interface, int ithCache_, + InputParameter *interface_ip_, + enum cache_level cacheL_) + : XML(XML_interface), + ithCache(ithCache_), + interface_ip(*interface_ip_), + cacheL(cacheL_), + dir_overhead(0) { + int idx; + int tag, data; + // bool is_default; + bool debug; + enum Device_ty device_t; + enum Core_type core_t; + double size, line, assoc, banks; + if (cacheL == L2 && XML->sys.Private_L2) { + device_t = Core_device; + core_t = (enum Core_type)XML->sys.core[ithCache].machine_type; + } + else { + device_t = LLC_device; + core_t = Inorder; + } + + debug = false; + // is_default = true; // indication for default setup + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 1; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + } + set_cache_param(); + + // All lower level cache are physically indexed and tagged. + size = cachep.capacity; + line = cachep.blockW; + assoc = cachep.assoc; + banks = cachep.nbanks; + if ((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory)) { + assoc = 0; + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + interface_ip.num_search_ports = 1; + } + else { + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + tag = debug ? 51 + : XML->sys.physical_address_width - idx - + int(ceil(log2(line))) + EXTRA_TAG_BITS; + interface_ip.num_search_ports = 0; + if (cachep.dir_ty == SBT) { + dir_overhead = + ceil(XML->sys.number_of_cores / 8.0) * 8 / (cachep.blockW * 8); + line = cachep.blockW * (1 + dir_overhead); + size = cachep.capacity * (1 + dir_overhead); + } + } + // if (XML->sys.first_level_dir==2) + // tag += int(XML->sys.domain_size + 5); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = (int)size; + interface_ip.line_sz = (int)line; + interface_ip.assoc = (int)assoc; + interface_ip.nbanks = (int)banks; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 1; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // lower level cache usually has one port. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + // interface_ip.force_cache_config =true; + // interface_ip.ndwl = 4; + // interface_ip.ndbl = 8; + // interface_ip.nspd = 1; + // interface_ip.ndcm =1 ; + // interface_ip.ndsam1 =1; + // interface_ip.ndsam2 =1; + unicache.caches = + new ArrayST(&interface_ip, cachep.name + "cache", device_t, true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.caches->local_result.area); + area.set_area(area.get_area() + unicache.caches->local_result.area); + interface_ip.force_cache_config = false; + + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = (XML->sys.physical_address_width) + int(ceil(log2(size / line))) + + unicache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = cachep.missb_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; // means cycle time + interface_ip.latency = cachep.latency; // means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 1; + unicache.missb = new ArrayST(&interface_ip, cachep.name + "MissB", device_t, + true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.missb->local_result.area); + area.set_area(area.get_area() + unicache.missb->local_result.area); + // fill buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = unicache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data * cachep.fu_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + unicache.ifb = new ArrayST(&interface_ip, cachep.name + "FillB", device_t, + true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.ifb->local_result.area); + area.set_area(area.get_area() + unicache.ifb->local_result.area); + // prefetch buffer + tag = XML->sys.physical_address_width + + EXTRA_TAG_BITS; // check with previous entries to decide wthether to + // merge. + data = unicache.caches->l_ip + .line_sz; // separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = cachep.prefetchb_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + unicache.prefetchb = new ArrayST(&interface_ip, cachep.name + "PrefetchB", + device_t, true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.prefetchb->local_result.area); + area.set_area(area.get_area() + unicache.prefetchb->local_result.area); + // WBB + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = unicache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = cachep.wbb_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + unicache.wbb = + new ArrayST(&interface_ip, cachep.name + "WBB", device_t, true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.wbb->local_result.area); + area.set_area(area.get_area() + unicache.wbb->local_result.area); + } + // //pipeline + // interface_ip.pipeline_stages = + // int(ceil(llCache.caches.local_result.access_time/llCache.caches.local_result.cycle_time)); + // interface_ip.per_stage_vector = llCache.caches.l_ip.out_w + + // llCache.caches.l_ip.tag_w ; pipeLogicCache.init_pipeline(is_default, + // &interface_ip); pipeLogicCache.compute_pipeline(); + + /* + if (!((XML->sys.number_of_dir_levels==1 && XML->sys.first_level_dir ==1) + ||(XML->sys.number_of_dir_levels==1 && + XML->sys.first_level_dir ==2)))//not single level IC and DIC + { + //directory Now assuming one directory per bank, TODO:should change it later + size = XML->sys.L2directory.L2Dir_config[0]; + line = XML->sys.L2directory.L2Dir_config[1]; + assoc = XML->sys.L2directory.L2Dir_config[2]; + banks = XML->sys.L2directory.L2Dir_config[3]; + tag = + debug?51:XML->sys.physical_address_width + EXTRA_TAG_BITS;//TODO: a little bit + over estimate interface_ip.specific_tag = 0; interface_ip.tag_w + = tag; interface_ip.cache_sz = + XML->sys.L2directory.L2Dir_config[0]; interface_ip.line_sz = + XML->sys.L2directory.L2Dir_config[1]; interface_ip.assoc = + XML->sys.L2directory.L2Dir_config[2]; interface_ip.nbanks = + XML->sys.L2directory.L2Dir_config[3]; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = + 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5]; + interface_ip.throughput = + XML->sys.L2directory.L2Dir_config[4]/clockRate; interface_ip.latency + = XML->sys.L2directory.L2Dir_config[5]/clockRate; interface_ip.is_cache + = true; interface_ip.obj_func_dyn_energy = 0; interface_ip.obj_func_dyn_power + = 0; interface_ip.obj_func_leak_power = 0; interface_ip.obj_func_cycle_t = + 1; interface_ip.num_rw_ports = 1;//lower level cache usually has one port. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + + strcpy(directory.caches.name,"L2 Directory"); + directory.caches.init_cache(&interface_ip); + directory.caches.optimize_array(); + directory.area += directory.caches.local_result.area; + //output_data_csv(directory.caches.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; + data = + (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + + directory.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[0]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate;//means cycle time + interface_ip.latency = + XML->sys.L2[ithCache].L2_config[5]/clockRate;//means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.missb.name,"directoryMissB"); + directory.missb.init_cache(&interface_ip); + directory.missb.optimize_array(); + directory.area += directory.missb.local_result.area; + //output_data_csv(directory.missb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data*XML->sys.L2[ithCache].buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz*8; + interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.ifb.name,"directoryFillB"); + directory.ifb.init_cache(&interface_ip); + directory.ifb.optimize_array(); + directory.area += directory.ifb.local_result.area; + //output_data_csv(directory.ifb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries + to decide wthether to merge. + data = + directory.caches.l_ip.line_sz;//separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[2]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.prefetchb.name,"directoryPrefetchB"); + directory.prefetchb.init_cache(&interface_ip); + directory.prefetchb.optimize_array(); + directory.area += directory.prefetchb.local_result.area; + //output_data_csv(directory.prefetchb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[3]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[4]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.wbb.name,"directoryWBB"); + directory.wbb.init_cache(&interface_ip); + directory.wbb.optimize_array(); + directory.area += directory.wbb.local_result.area; + } + + if (XML->sys.number_of_dir_levels ==2 && XML->sys.first_level_dir==0) + { + //first level directory + size = + XML->sys.L2directory.L2Dir_config[0]*XML->sys.domain_size/128; line + = int(ceil(XML->sys.domain_size/8.0)); assoc = + XML->sys.L2directory.L2Dir_config[2]; banks = + XML->sys.L2directory.L2Dir_config[3]; tag + = debug?51:XML->sys.physical_address_width + EXTRA_TAG_BITS;//TODO: a little + bit over estimate interface_ip.specific_tag = 1; interface_ip.tag_w + = tag; interface_ip.cache_sz = + XML->sys.L2directory.L2Dir_config[0]; interface_ip.line_sz = + XML->sys.L2directory.L2Dir_config[1]; interface_ip.assoc = + XML->sys.L2directory.L2Dir_config[2]; interface_ip.nbanks = + XML->sys.L2directory.L2Dir_config[3]; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = + 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5]; + interface_ip.throughput = + XML->sys.L2directory.L2Dir_config[4]/clockRate; interface_ip.latency + = XML->sys.L2directory.L2Dir_config[5]/clockRate; interface_ip.is_cache + = true; interface_ip.obj_func_dyn_energy = 0; interface_ip.obj_func_dyn_power + = 0; interface_ip.obj_func_leak_power = 0; interface_ip.obj_func_cycle_t = + 1; interface_ip.num_rw_ports = 1;//lower level cache usually has one port. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + + strcpy(directory1.caches.name,"first level Directory"); + directory1.caches.init_cache(&interface_ip); + directory1.caches.optimize_array(); + directory1.area += directory1.caches.local_result.area; + //output_data_csv(directory.caches.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; + data = + (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + + directory1.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[0]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate;//means cycle time + interface_ip.latency = + XML->sys.L2[ithCache].L2_config[5]/clockRate;//means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.missb.name,"directory1MissB"); + directory1.missb.init_cache(&interface_ip); + directory1.missb.optimize_array(); + directory1.area += directory1.missb.local_result.area; + //output_data_csv(directory.missb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory1.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data*XML->sys.L2[ithCache].buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz*8; + interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.ifb.name,"directory1FillB"); + directory1.ifb.init_cache(&interface_ip); + directory1.ifb.optimize_array(); + directory1.area += directory1.ifb.local_result.area; + //output_data_csv(directory.ifb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries + to decide wthether to merge. + data = + directory1.caches.l_ip.line_sz;//separate queue to prevent from cache + polution. interface_ip.specific_tag = 1; interface_ip.tag_w + = tag; interface_ip.line_sz = + data;//int(pow(2.0,ceil(log2(data)))); interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[2]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.prefetchb.name,"directory1PrefetchB"); + directory1.prefetchb.init_cache(&interface_ip); + directory1.prefetchb.optimize_array(); + directory1.area += directory1.prefetchb.local_result.area; + //output_data_csv(directory.prefetchb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory1.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[3]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.wbb.name,"directoryWBB"); + directory1.wbb.init_cache(&interface_ip); + directory1.wbb.optimize_array(); + directory1.area += directory1.wbb.local_result.area; + } + + if (XML->sys.first_level_dir==1)//IC + { + tag = + XML->sys.physical_address_width + EXTRA_TAG_BITS; data + = int(ceil(XML->sys.domain_size/8.0)); interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.domain_size*data*XML->sys.L2[ithCache].L2_config[0]/XML->sys.L2[ithCache].L2_config[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1024; + interface_ip.out_w = interface_ip.line_sz*8; + interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(inv_dir.caches.name,"inv_dir"); + inv_dir.caches.init_cache(&interface_ip); + inv_dir.caches.optimize_array(); + inv_dir.area = inv_dir.caches.local_result.area; + + } +*/ + // //pipeline + // interface_ip.pipeline_stages = + // int(ceil(directory.caches.local_result.access_time/directory.caches.local_result.cycle_time)); + // interface_ip.per_stage_vector = directory.caches.l_ip.out_w + + // directory.caches.l_ip.tag_w ; pipeLogicDirectory.init_pipeline(is_default, + // &interface_ip); pipeLogicDirectory.compute_pipeline(); + // + // //clock power + // clockNetwork.init_wire_external(is_default, &interface_ip); + // clockNetwork.clk_area =area*1.1;//10% of placement overhead. + // rule of thumb clockNetwork.end_wiring_level =5;//toplevel metal + // clockNetwork.start_wiring_level =5;//toplevel metal + // clockNetwork.num_regs = pipeLogicCache.tot_stage_vector + + // pipeLogicDirectory.tot_stage_vector; clockNetwork.optimize_wire(); +} + +void SharedCache::computeEnergy(bool is_tdp) { + double homenode_data_access = (cachep.dir_ty == SBT) ? 0.9 : 1.0; + if (is_tdp) { + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + // init stats for Peak + unicache.caches->stats_t.readAc.access = + .67 * unicache.caches->l_ip.num_rw_ports * cachep.duty_cycle * + homenode_data_access; + unicache.caches->stats_t.readAc.miss = 0; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + .33 * unicache.caches->l_ip.num_rw_ports * cachep.duty_cycle * + homenode_data_access; + unicache.caches->stats_t.writeAc.miss = 0; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->tdp_stats = unicache.caches->stats_t; + + if (cachep.dir_ty == SBT) { + homenode_stats_t.readAc.access = + .67 * unicache.caches->l_ip.num_rw_ports * cachep.dir_duty_cycle * + (1 - homenode_data_access); + homenode_stats_t.readAc.miss = 0; + homenode_stats_t.readAc.hit = + homenode_stats_t.readAc.access - homenode_stats_t.readAc.miss; + homenode_stats_t.writeAc.access = + .67 * unicache.caches->l_ip.num_rw_ports * cachep.dir_duty_cycle * + (1 - homenode_data_access); + homenode_stats_t.writeAc.miss = 0; + homenode_stats_t.writeAc.hit = + homenode_stats_t.writeAc.access - homenode_stats_t.writeAc.miss; + homenode_tdp_stats = homenode_stats_t; + } + + unicache.missb->stats_t.readAc.access = + unicache.missb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.missb->stats_t.writeAc.access = + unicache.missb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.missb->tdp_stats = unicache.missb->stats_t; + + unicache.ifb->stats_t.readAc.access = + unicache.ifb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.ifb->stats_t.writeAc.access = + unicache.ifb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.ifb->tdp_stats = unicache.ifb->stats_t; + + unicache.prefetchb->stats_t.readAc.access = + unicache.prefetchb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.prefetchb->stats_t.writeAc.access = + unicache.ifb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.prefetchb->tdp_stats = unicache.prefetchb->stats_t; + + unicache.wbb->stats_t.readAc.access = + unicache.wbb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.wbb->stats_t.writeAc.access = + unicache.wbb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.wbb->tdp_stats = unicache.wbb->stats_t; + } + else { + unicache.caches->stats_t.readAc.access = + unicache.caches->l_ip.num_search_ports * cachep.duty_cycle; + unicache.caches->stats_t.readAc.miss = 0; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = 0; + unicache.caches->stats_t.writeAc.miss = 0; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->tdp_stats = unicache.caches->stats_t; + } + } + else { + // init stats for runtime power (RTP) + if (cacheL == L2) { + unicache.caches->stats_t.readAc.access = + XML->sys.L2[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = XML->sys.L2[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L2[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L2[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + + if (cachep.dir_ty == SBT) { + homenode_rtp_stats.readAc.access = + XML->sys.L2[ithCache].homenode_read_accesses; + homenode_rtp_stats.readAc.miss = + XML->sys.L2[ithCache].homenode_read_misses; + homenode_rtp_stats.readAc.hit = + homenode_rtp_stats.readAc.access - homenode_rtp_stats.readAc.miss; + homenode_rtp_stats.writeAc.access = + XML->sys.L2[ithCache].homenode_write_accesses; + homenode_rtp_stats.writeAc.miss = + XML->sys.L2[ithCache].homenode_write_misses; + homenode_rtp_stats.writeAc.hit = + homenode_rtp_stats.writeAc.access - homenode_rtp_stats.writeAc.miss; + } + } + else if (cacheL == L3) { + unicache.caches->stats_t.readAc.access = + XML->sys.L3[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = XML->sys.L3[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L3[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L3[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + + if (cachep.dir_ty == SBT) { + homenode_rtp_stats.readAc.access = + XML->sys.L3[ithCache].homenode_read_accesses; + homenode_rtp_stats.readAc.miss = + XML->sys.L3[ithCache].homenode_read_misses; + homenode_rtp_stats.readAc.hit = + homenode_rtp_stats.readAc.access - homenode_rtp_stats.readAc.miss; + homenode_rtp_stats.writeAc.access = + XML->sys.L3[ithCache].homenode_write_accesses; + homenode_rtp_stats.writeAc.miss = + XML->sys.L3[ithCache].homenode_write_misses; + homenode_rtp_stats.writeAc.hit = + homenode_rtp_stats.writeAc.access - homenode_rtp_stats.writeAc.miss; + } + } + else if (cacheL == L1Directory) { + unicache.caches->stats_t.readAc.access = + XML->sys.L1Directory[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = + XML->sys.L1Directory[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L1Directory[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L1Directory[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + } + else if (cacheL == L2Directory) { + unicache.caches->stats_t.readAc.access = + XML->sys.L2Directory[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = + XML->sys.L2Directory[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L2Directory[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L2Directory[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + } + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && + cacheL == + L2Directory))) { // Assuming write back and write-allocate cache + + unicache.missb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.missb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.missb->rtp_stats = unicache.missb->stats_t; + + unicache.ifb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.ifb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.ifb->rtp_stats = unicache.ifb->stats_t; + + unicache.prefetchb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.prefetchb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.prefetchb->rtp_stats = unicache.prefetchb->stats_t; + + unicache.wbb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.wbb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + if (cachep.dir_ty == SBT) { + unicache.missb->stats_t.readAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->stats_t.writeAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->rtp_stats = unicache.missb->stats_t; + + unicache.missb->stats_t.readAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->stats_t.writeAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->rtp_stats = unicache.missb->stats_t; + + unicache.ifb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss; + unicache.ifb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss; + unicache.ifb->rtp_stats = unicache.ifb->stats_t; + + unicache.prefetchb->stats_t.readAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.prefetchb->stats_t.writeAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.prefetchb->rtp_stats = unicache.prefetchb->stats_t; + + unicache.wbb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss; + unicache.wbb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss; + } + unicache.wbb->rtp_stats = unicache.wbb->stats_t; + } + } + + unicache.power_t.reset(); + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + unicache.power_t.readOp.dynamic += + (unicache.caches->stats_t.readAc.hit * + unicache.caches->local_result.power.readOp.dynamic + + unicache.caches->stats_t.readAc.miss * + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + unicache.caches->stats_t.writeAc.miss * + unicache.caches->local_result.tag_array2->power.writeOp.dynamic + + unicache.caches->stats_t.writeAc.access * + unicache.caches->local_result.power.writeOp + .dynamic); // write miss will also generate a write later + + if (cachep.dir_ty == SBT) { + unicache.power_t.readOp.dynamic += + homenode_stats_t.readAc.hit * + (unicache.caches->local_result.data_array2->power.readOp.dynamic * + dir_overhead + + unicache.caches->local_result.tag_array2->power.readOp.dynamic) + + homenode_stats_t.readAc.miss * + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + homenode_stats_t.writeAc.miss * + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + homenode_stats_t.writeAc.hit * + (unicache.caches->local_result.data_array2->power.writeOp + .dynamic * + dir_overhead + + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + homenode_stats_t.writeAc.miss * + unicache.caches->local_result.power.writeOp + .dynamic); // write miss on dynamic home node will + // generate a replacement write on whole + // cache block + } + + unicache.power_t.readOp.dynamic += + unicache.missb->stats_t.readAc.access * + unicache.missb->local_result.power.searchOp.dynamic + + unicache.missb->stats_t.writeAc.access * + unicache.missb->local_result.power.writeOp + .dynamic; // each access to missb involves a CAM and a write + unicache.power_t.readOp.dynamic += + unicache.ifb->stats_t.readAc.access * + unicache.ifb->local_result.power.searchOp.dynamic + + unicache.ifb->stats_t.writeAc.access * + unicache.ifb->local_result.power.writeOp.dynamic; + unicache.power_t.readOp.dynamic += + unicache.prefetchb->stats_t.readAc.access * + unicache.prefetchb->local_result.power.searchOp.dynamic + + unicache.prefetchb->stats_t.writeAc.access * + unicache.prefetchb->local_result.power.writeOp.dynamic; + unicache.power_t.readOp.dynamic += + unicache.wbb->stats_t.readAc.access * + unicache.wbb->local_result.power.searchOp.dynamic + + unicache.wbb->stats_t.writeAc.access * + unicache.wbb->local_result.power.writeOp.dynamic; + } + else { + unicache.power_t.readOp.dynamic += + (unicache.caches->stats_t.readAc.access * + unicache.caches->local_result.power.searchOp.dynamic + + unicache.caches->stats_t.writeAc.access * + unicache.caches->local_result.power.writeOp.dynamic); + } + + if (is_tdp) { + unicache.power = + unicache.power_t + (unicache.caches->local_result.power) * pppm_lkg; + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + unicache.power = + unicache.power + (unicache.missb->local_result.power + + unicache.ifb->local_result.power + + unicache.prefetchb->local_result.power + + unicache.wbb->local_result.power) * + pppm_lkg; + } + power = power + unicache.power; + // cout<<"unicache.caches->local_result.power.readOp.dynamic"<local_result.power.readOp.dynamic<local_result.power.writeOp.dynamic"<local_result.power.writeOp.dynamic<local_result.power) * pppm_lkg; + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + unicache.rt_power = + unicache.rt_power + (unicache.missb->local_result.power + + unicache.ifb->local_result.power + + unicache.prefetchb->local_result.power + + unicache.wbb->local_result.power) * + pppm_lkg; + } + rt_power = rt_power + unicache.rt_power; + } +} + +void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << (XML->sys.Private_L2 ? indent_str : "") << cachep.name << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * cachep.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " + << rt_power.readOp.dynamic / cachep.executionTime << " W" << endl; + cout << endl; + } + else { + } +} + +// void SharedCache::computeMaxPower() +//{ +// //Compute maximum power and runtime power. +// //When computing runtime power, McPAT gets or reasons out the statistics +// based on XML input. maxPower = 0.0; +// //llCache,itlb +// llCache.maxPower = 0.0; +// llCache.maxPower += +// (llCache.caches.l_ip.num_rw_ports*(0.67*llCache.caches.local_result.power.readOp.dynamic+0.33*llCache.caches.local_result.power.writeOp.dynamic) +// +llCache.caches.l_ip.num_rd_ports*llCache.caches.local_result.power.readOp.dynamic+llCache.caches.l_ip.num_wr_ports*llCache.caches.local_result.power.writeOp.dynamic +// +llCache.caches.l_ip.num_se_rd_ports*llCache.caches.local_result.power.readOp.dynamic)*clockRate; +// ///cout<<"llCache.maxPower=" <sys.first_level_dir==1) +// { +// inv_dir.maxPower = +// inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size; +// cc.power.readOp.dynamic = +// inv_dir.maxPower*scktRatio*64/XML->sys.domain_size; +// cc.power.readOp.leakage = +// inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*64/XML->sys.domain_size; +// +// cc.area.set_area(inv_dir.area*64/XML->sys.domain_size); +// cout<<"CC area="<sys.number_of_dir_levels==2) +// { +// +// directory.maxPower = 0.0; +// directory.maxPower += +//(directory.caches.l_ip.num_rw_ports*(0.67*directory.caches.local_result.power.readOp.dynamic+0.33*directory.caches.local_result.power.writeOp.dynamic) +// +directory.caches.l_ip.num_rd_ports*directory.caches.local_result.power.readOp.dynamic+directory.caches.l_ip.num_wr_ports*directory.caches.local_result.power.writeOp.dynamic +// +directory.caches.l_ip.num_se_rd_ports*directory.caches.local_result.power.readOp.dynamic)*clockRate; +// ///cout<<"directory.maxPower=" +//<sys.L2[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L2[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L2[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L2[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L2[ithCache].device_type; + cachep.capacity = XML->sys.L2[ithCache].L2_config[0]; + cachep.blockW = XML->sys.L2[ithCache].L2_config[1]; + cachep.assoc = XML->sys.L2[ithCache].L2_config[2]; + cachep.nbanks = XML->sys.L2[ithCache].L2_config[3]; + cachep.throughput = XML->sys.L2[ithCache].L2_config[4] / cachep.clockRate; + cachep.latency = XML->sys.L2[ithCache].L2_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L2[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L2[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L2[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L2[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L2[ithCache].duty_cycle; + if (!XML->sys.L2[ithCache].merged_dir) { + cachep.dir_ty = NonDir; + } + else { + cachep.dir_ty = SBT; + cachep.dir_duty_cycle = XML->sys.L2[ithCache].dir_duty_cycle; + } + + if (XML->sys.Private_L2 && XML->sys.core[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.core[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.core[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.core[ithCache].vdd; + } + + if (XML->sys.Private_L2 && XML->sys.core[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.core[ithCache].power_gating_vcc; + } + if (!XML->sys.Private_L2 && XML->sys.L2[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L2[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L2[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L2[ithCache].vdd; + } + if (!XML->sys.Private_L2 && XML->sys.L2[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L2[ithCache].power_gating_vcc; + } + } + else if (cacheL == L3) { + cachep.name = "L3"; + cachep.clockRate = XML->sys.L3[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L3[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L3[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L3[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L3[ithCache].device_type; + cachep.capacity = XML->sys.L3[ithCache].L3_config[0]; + cachep.blockW = XML->sys.L3[ithCache].L3_config[1]; + cachep.assoc = XML->sys.L3[ithCache].L3_config[2]; + cachep.nbanks = XML->sys.L3[ithCache].L3_config[3]; + cachep.throughput = XML->sys.L3[ithCache].L3_config[4] / cachep.clockRate; + cachep.latency = XML->sys.L3[ithCache].L3_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L3[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L3[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L3[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L3[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L3[ithCache].duty_cycle; + if (!XML->sys.L2[ithCache].merged_dir) { + cachep.dir_ty = NonDir; + } + else { + cachep.dir_ty = SBT; + cachep.dir_duty_cycle = XML->sys.L2[ithCache].dir_duty_cycle; + } + if (XML->sys.L3[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L3[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L3[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L3[ithCache].vdd; + } + + if (XML->sys.L3[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L3[ithCache].power_gating_vcc; + } + } + else if (cacheL == L1Directory) { + cachep.name = "First Level Directory"; + cachep.dir_ty = + (enum Dir_type)XML->sys.L1Directory[ithCache].Directory_type; + cachep.clockRate = XML->sys.L1Directory[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L1Directory[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L1Directory[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = + XML->sys.L1Directory[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L1Directory[ithCache].device_type; + cachep.capacity = XML->sys.L1Directory[ithCache].Dir_config[0]; + cachep.blockW = XML->sys.L1Directory[ithCache].Dir_config[1]; + cachep.assoc = XML->sys.L1Directory[ithCache].Dir_config[2]; + cachep.nbanks = XML->sys.L1Directory[ithCache].Dir_config[3]; + cachep.throughput = + XML->sys.L1Directory[ithCache].Dir_config[4] / cachep.clockRate; + cachep.latency = + XML->sys.L1Directory[ithCache].Dir_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L1Directory[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L1Directory[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L1Directory[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L1Directory[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L1Directory[ithCache].duty_cycle; + + if (XML->sys.L1Directory[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L1Directory[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L1Directory[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L1Directory[ithCache].vdd; + } + + if (XML->sys.L1Directory[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L1Directory[ithCache].power_gating_vcc; + } + } + else if (cacheL == L2Directory) { + cachep.name = "Second Level Directory"; + cachep.dir_ty = + (enum Dir_type)XML->sys.L2Directory[ithCache].Directory_type; + cachep.clockRate = XML->sys.L2Directory[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L2Directory[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L2Directory[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = + XML->sys.L2Directory[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L2Directory[ithCache].device_type; + cachep.capacity = XML->sys.L2Directory[ithCache].Dir_config[0]; + cachep.blockW = XML->sys.L2Directory[ithCache].Dir_config[1]; + cachep.assoc = XML->sys.L2Directory[ithCache].Dir_config[2]; + cachep.nbanks = XML->sys.L2Directory[ithCache].Dir_config[3]; + cachep.throughput = + XML->sys.L2Directory[ithCache].Dir_config[4] / cachep.clockRate; + cachep.latency = + XML->sys.L2Directory[ithCache].Dir_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L2Directory[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L2Directory[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L2Directory[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L2Directory[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L2Directory[ithCache].duty_cycle; + + if (XML->sys.L2Directory[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L2Directory[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L2Directory[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L2Directory[ithCache].vdd; + } + + if (XML->sys.L2Directory[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L2Directory[ithCache].power_gating_vcc; + } + } + // cachep.cache_duty_cycle=cachep.dir_duty_cycle = 0.35; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/sharedcache.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/sharedcache.h new file mode 100644 index 0000000000..26aa42c0ca --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/sharedcache.h @@ -0,0 +1,90 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef SHAREDCACHE_H_ +#define SHAREDCACHE_H_ +#include +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/area.h" +#include "cacti/parameter.h" +#include "logic.h" +using namespace cacti; + +class SharedCache : public Component { + public: + ParseXML *XML; + int ithCache; + InputParameter interface_ip; + enum cache_level cacheL; + DataCache unicache; // Shared cache + CacheDynParam cachep; + statsDef homenode_tdp_stats; + statsDef homenode_rtp_stats; + statsDef homenode_stats_t; + double dir_overhead; + // cache_processor llCache,directory, directory1, inv_dir; + + // pipeline pipeLogicCache, pipeLogicDirectory; + // clock_network clockNetwork; + double scktRatio, executionTime; + // Component L2Tot, cc, cc1, ccTot; + + SharedCache(ParseXML *XML_interface, int ithCache_, + InputParameter *interface_ip_, enum cache_level cacheL_ = L2); + void set_cache_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, bool is_tdp = true); + ~SharedCache(){}; +}; + +class CCdir : public Component { + public: + ParseXML *XML; + int ithCache; + InputParameter interface_ip; + DataCache dc; // Shared cache + ArrayST *shadow_dir; + // cache_processor llCache,directory, directory1, inv_dir; + + // pipeline pipeLogicCache, pipeLogicDirectory; + // clock_network clockNetwork; + double scktRatio, clockRate, executionTime; + Component L2Tot, cc, cc1, ccTot; + + CCdir(ParseXML *XML_interface, int ithCache_, InputParameter *interface_ip_); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, bool is_tdp = true); + ~CCdir(); +}; + +#endif /* SHAREDCACHE_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/version.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/version.h new file mode 100644 index 0000000000..ec8e616d04 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/lib/mcpat/version.h @@ -0,0 +1,40 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef VERSION_H_ +#define VERSION_H_ + +#define VER_MAJOR 1 +#define VER_MINOR 3 + +#define VER_UPDATE "Feb, 2015" + +#endif /* VERSION_H_ */ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/abstract_pal.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/abstract_pal.hh new file mode 100644 index 0000000000..86ad5e86c2 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/abstract_pal.hh @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_ABSTRACT_PAL__ +#define __PAL_ABSTRACT_PAL__ + +#include + +#include "pal/pal.hh" + +namespace SimpleSSD { + +namespace PAL { + +class AbstractPAL : public StatObject { + protected: + Parameter ¶m; + ConfigReader &conf; + + public: + AbstractPAL(Parameter &p, ConfigReader &c) : param(p), conf(c) {} + virtual ~AbstractPAL() {} + + virtual void read(Request &, uint64_t &) = 0; + virtual void write(Request &, uint64_t &) = 0; + virtual void erase(Request &, uint64_t &) = 0; +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/config.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/config.cc new file mode 100644 index 0000000000..f9bf83d0d3 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/config.cc @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "pal/config.hh" + +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace PAL { + +const char NAME_CHANNEL[] = "Channel"; +const char NAME_PACKAGE[] = "Package"; +const char NAME_PAGE_ALLOCATION[] = "PageAllocation"; +const char NAME_SUPER_BLOCK[] = "SuperblockSize"; + +/* NAND config TODO: seperate this */ +const char NAME_DIE[] = "Die"; +const char NAME_PLANE[] = "Plane"; +const char NAME_BLOCK[] = "Block"; +const char NAME_PAGE[] = "Page"; +const char NAME_PAGE_SIZE[] = "PageSize"; +const char NAME_USE_MULTI_PLANE_OP[] = "EnableMultiPlaneOperation"; +const char NAME_DMA_SPEED[] = "DMASpeed"; +const char NAME_DMA_WIDTH[] = "DMAWidth"; +const char NAME_FLASH_TYPE[] = "NANDType"; + +/* NAND timing TODO: seperate this */ +const char NAME_NAND_LSB_READ[] = "LSBRead"; +const char NAME_NAND_LSB_WRITE[] = "LSBWrite"; +const char NAME_NAND_CSB_READ[] = "CSBRead"; +const char NAME_NAND_CSB_WRITE[] = "CSBWrite"; +const char NAME_NAND_MSB_READ[] = "MSBRead"; +const char NAME_NAND_MSB_WRITE[] = "MSBWrite"; +const char NAME_NAND_ERASE[] = "Erase"; + +/* NAND power TODO: seperate this */ +const char NAME_NAND_VOLTAGE[] = "Voltage"; +const char NAME_NAND_CURRENT_READ[] = "ReadCurrent"; +const char NAME_NAND_CURRENT_PROGRAM[] = "ProgramCurrent"; +const char NAME_NAND_CURRENT_ERASE[] = "EraseCurrent"; +const char NAME_NAND_CURRENT_IDLE[] = "IdleCurrent"; +const char NAME_NAND_CURRENT_STANDBY[] = "StandbyCurrent"; + +/* Constants for calculating DMA time based on ONFI 3.x spec */ +// READ : <00h> <30h> [tWB] [tR] [tRR] +// WRITE: <80h> [tADL] <10h> [tWB] [tPROG] +// ERASE: <60h> [tWB] [tBERS] +const uint8_t readCycle = 7; +const uint8_t writeCycle = 7; +const uint8_t eraseCycle = 5; + +Config::Config() { + channel = 8; + package = 4; + die = 2; + plane = 1; + block = 512; + page = 512; + pageSize = 16384; + useMultiPlaneOperation = true; + dmaSpeed = 400; + dmaWidth = 8; + nandType = NAND_MLC; + + // Set NAND timing (Default: MLC, csb is not used) + nandTiming.lsb.read = 40000000; // 40us + nandTiming.lsb.write = 500000000; // 500us + nandTiming.csb.read = 0; + nandTiming.csb.write = 0; + nandTiming.msb.read = 65000000; // 65us + nandTiming.msb.write = 1300000000; // 1300us + nandTiming.erase = 3500000000; // 3.5ms + + // Set NAND power (From: Micron's MT29F64*) + nandPower.voltage = 3300; // 3.3V + nandPower.current.read = 25000; // 25mA + nandPower.current.program = 25000; // 25mA + nandPower.current.erase = 25000; // 25mA + nandPower.current.busIdle = 5000; // 5mA + nandPower.current.standby = 10; // 10uA + + superblock = 0; + memset(PageAllocation, 0, 4); +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_CHANNEL)) { + channel = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PACKAGE)) { + package = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DIE)) { + die = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PLANE)) { + plane = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_BLOCK)) { + block = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PAGE)) { + page = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PAGE_SIZE)) { + pageSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_USE_MULTI_PLANE_OP)) { + useMultiPlaneOperation = convertBool(value); + } + else if (MATCH_NAME(NAME_DMA_SPEED)) { + dmaSpeed = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DMA_WIDTH)) { + dmaWidth = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FLASH_TYPE)) { + nandType = (NAND_TYPE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SUPER_BLOCK)) { + _superblock = value; + } + else if (MATCH_NAME(NAME_PAGE_ALLOCATION)) { + _pageAllocation = value; + } + else if (MATCH_NAME(NAME_NAND_LSB_READ)) { + nandTiming.lsb.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_LSB_WRITE)) { + nandTiming.lsb.write = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CSB_READ)) { + nandTiming.csb.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CSB_WRITE)) { + nandTiming.csb.write = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_MSB_READ)) { + nandTiming.msb.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_MSB_WRITE)) { + nandTiming.msb.write = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_ERASE)) { + nandTiming.erase = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_VOLTAGE)) { + nandPower.voltage = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_READ)) { + nandPower.current.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_PROGRAM)) { + nandPower.current.program = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_ERASE)) { + nandPower.current.erase = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_IDLE)) { + nandPower.current.busIdle = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_STANDBY)) { + nandPower.current.standby = strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (dmaWidth & 0x07) { + panic("dmaWidth should be multiple of 8."); + } + + // DMA time calculation + // MT/s MT -> T ms us ns ps + float tCK = 1.f / (dmaSpeed * 1048576) * 1000 * 1000 * 1000 * 1000; + + nandTiming.dma0.read = readCycle * tCK / (dmaWidth / 8); + nandTiming.dma0.write = (writeCycle + pageSize) * tCK / (dmaWidth / 8); + nandTiming.dma0.erase = eraseCycle * tCK / (dmaWidth / 8); + nandTiming.dma1.read = pageSize * tCK / (dmaWidth / 8); + nandTiming.dma1.write = 1 * tCK / (dmaWidth / 8); + nandTiming.dma1.erase = 1 * tCK / (dmaWidth / 8); + + // Parse page allocation setting + int i = 0; + uint8_t check = 0; + bool fail = false; + + for (auto iter : _pageAllocation) { + if ((iter == 'C') | (iter == 'c')) { + if (check & INDEX_CHANNEL) { + fail = true; + } + + PageAllocation[i++] = INDEX_CHANNEL; + check |= INDEX_CHANNEL; + } + else if ((iter == 'W') | (iter == 'w')) { + if (check & INDEX_PACKAGE) { + fail = true; + } + + PageAllocation[i++] = INDEX_PACKAGE; + check |= INDEX_PACKAGE; + } + else if ((iter == 'D') | (iter == 'd')) { + if (check & INDEX_DIE) { + fail = true; + } + + PageAllocation[i++] = INDEX_DIE; + check |= INDEX_DIE; + } + else if ((iter == 'P') | (iter == 'p')) { + if (check & INDEX_PLANE) { + fail = true; + } + + PageAllocation[i++] = INDEX_PLANE; + check |= INDEX_PLANE; + } + + if (i == 4) { + break; + } + } + + if (check != (INDEX_CHANNEL | INDEX_PACKAGE | INDEX_DIE | INDEX_PLANE)) { + fail = true; + } + + if (useMultiPlaneOperation) { + // Move P to front + for (i = 0; i < 4; i++) { + if (PageAllocation[i] == INDEX_PLANE) { + for (int j = i; j > 0; j--) { + PageAllocation[j] = PageAllocation[j - 1]; + } + + PageAllocation[0] = INDEX_PLANE; + + break; + } + } + } + + if (fail) { + panic("Invalid page allocation string"); + } + + // Parse super block size setting + if (_superblock.length() > 0) { + superblock = 0x00; + + for (auto iter : _superblock) { + if ((iter == 'C') | (iter == 'c')) { + superblock |= INDEX_CHANNEL; + } + else if ((iter == 'W') | (iter == 'w')) { + superblock |= INDEX_PACKAGE; + } + else if ((iter == 'D') | (iter == 'd')) { + superblock |= INDEX_DIE; + } + else if ((iter == 'P') | (iter == 'p')) { + superblock |= INDEX_PLANE; + } + } + } + + if (useMultiPlaneOperation) { + superblock |= INDEX_PLANE; + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case NAND_FLASH_TYPE: + ret = nandType; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case PAL_CHANNEL: + ret = channel; + break; + case PAL_PACKAGE: + ret = package; + break; + case NAND_DIE: + ret = die; + break; + case NAND_PLANE: + ret = plane; + break; + case NAND_BLOCK: + ret = block; + break; + case NAND_PAGE: + ret = page; + break; + case NAND_PAGE_SIZE: + ret = pageSize; + break; + case NAND_DMA_SPEED: + ret = dmaSpeed; + break; + case NAND_DMA_WIDTH: + ret = dmaWidth; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case NAND_USE_MULTI_PLANE_OP: + ret = useMultiPlaneOperation; + break; + } + + return ret; +} + +uint8_t Config::getSuperblockConfig() { + return superblock; +} + +uint32_t Config::getPageAllocationConfig() { + return (uint32_t)PageAllocation[0] | ((uint32_t)PageAllocation[1] << 8) | + ((uint32_t)PageAllocation[2] << 16) | + ((uint32_t)PageAllocation[3] << 24); +} + +Config::NANDTiming *Config::getNANDTiming() { + return &nandTiming; +} + +Config::NANDPower *Config::getNANDPower() { + return &nandPower; +} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/config.hh new file mode 100644 index 0000000000..b7e7f79da7 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/config.hh @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_CONFIG__ +#define __PAL_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace PAL { + +typedef enum { + /* PAL config */ + PAL_CHANNEL, + PAL_PACKAGE, + + /* NAND config TODO: seperate this */ + NAND_DIE, + NAND_PLANE, + NAND_BLOCK, + NAND_PAGE, + NAND_PAGE_SIZE, + NAND_USE_MULTI_PLANE_OP, + NAND_DMA_SPEED, + NAND_DMA_WIDTH, + NAND_FLASH_TYPE, +} PAL_CONFIG; + +typedef enum { + NAND_SLC, + NAND_MLC, + NAND_TLC, +} NAND_TYPE; + +typedef enum : uint8_t { + INDEX_CHANNEL = 0x01, + INDEX_PACKAGE = 0x02, + INDEX_DIE = 0x04, + INDEX_PLANE = 0x08, +} ADDR_INDEX; + +class Config : public BaseConfig { + public: + typedef struct { + uint64_t read; + uint64_t write; + } PAGETiming; + + typedef struct { + uint64_t read; + uint64_t write; + uint64_t erase; + } DMATiming; + + typedef struct { + PAGETiming lsb; + PAGETiming csb; + PAGETiming msb; + DMATiming dma0; + DMATiming dma1; + uint64_t erase; + } NANDTiming; + + typedef struct { + uint64_t voltage; //!< Unit: mV + struct { //!< Unit: uA + uint64_t read; + uint64_t program; + uint64_t erase; + uint64_t busIdle; + uint64_t standby; + } current; + } NANDPower; + + private: + uint32_t channel; //!< Default: 8 + uint32_t package; //!< Default: 4 + + uint32_t die; //!< Default: 2 + uint32_t plane; //!< Default: 1 + uint32_t block; //!< Default: 512 + uint32_t page; //!< Default: 512 + uint32_t pageSize; //!< Default: 16384 + bool useMultiPlaneOperation; //!< Default: true + uint32_t dmaSpeed; //!< Default: 400 + uint32_t dmaWidth; //!< Default: 8 + NAND_TYPE nandType; //!< Default: NAND_MLC + uint8_t superblock; //!< Default: All (0x0F) + uint8_t PageAllocation[4]; //!< Default: CWDP (0x01, 0x02, 0x04, 0x08) + + NANDTiming nandTiming; + NANDPower nandPower; + + // Raw variable + std::string _superblock; + std::string _pageAllocation; + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + bool readBoolean(uint32_t) override; + + uint8_t getSuperblockConfig(); + uint32_t getPageAllocationConfig(); + + NANDTiming *getNANDTiming(); + NANDPower *getNANDPower(); +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/Latency.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/Latency.cc new file mode 100644 index 0000000000..0c20ca78a0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/Latency.cc @@ -0,0 +1,58 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "Latency.h" + +/*============================== + Latency +==============================*/ + +/* + Latency class is inherited to: + - TLC + - MLC + - SLC +*/ + +Latency::Latency(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : timing(t), power(p) {} + +Latency::~Latency() {} + +// Unit conversion: mV * uA = nW +uint64_t Latency::GetPower(uint8_t Oper, uint8_t Busy) { + switch (Busy) { + case BUSY_DMA0: + case BUSY_DMA1: + return power.voltage * power.current.busIdle; + case BUSY_MEM: + if (Oper == OPER_READ) { + return power.voltage * power.current.read; + } + else if (Oper == OPER_WRITE) { + return power.voltage * power.current.program; + } + else { + return power.voltage * power.current.erase; + } + + break; + default: + return power.voltage * power.current.standby; + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/Latency.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/Latency.h new file mode 100644 index 0000000000..dbbe80b054 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/Latency.h @@ -0,0 +1,56 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __Latency_h__ +#define __Latency_h__ + +#include "util/old/SimpleSSD_types.h" + +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +#include "pal/config.hh" + +/*============================== + Latency +==============================*/ +class Latency { + protected: + SimpleSSD::PAL::Config::NANDTiming timing; + SimpleSSD::PAL::Config::NANDPower power; + + public: + Latency(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + virtual ~Latency(); + + // Get Latency for PageAddress(L/C/MSBpage), Operation(RWE), + // BusyFor(Ch.DMA/Mem.Work) + virtual uint64_t GetLatency(uint32_t, uint8_t, uint8_t) { return 0; }; + virtual inline uint8_t GetPageType(uint32_t) { return PAGE_NUM; }; + + // Setup DMA speed and pagesize + virtual uint64_t GetPower(uint8_t, uint8_t); +}; + +#endif //__Latency_h__ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyMLC.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyMLC.cc new file mode 100644 index 0000000000..c4382fda5c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyMLC.cc @@ -0,0 +1,84 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "LatencyMLC.h" + +LatencyMLC::LatencyMLC(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : Latency(t, p) {} + +LatencyMLC::~LatencyMLC() {} + +inline uint8_t LatencyMLC::GetPageType(uint32_t AddrPage) { + return AddrPage % 2; +} + +uint64_t LatencyMLC::GetLatency(uint32_t AddrPage, uint8_t Oper, uint8_t Busy) { + SimpleSSD::PAL::Config::PAGETiming *pTiming = nullptr; + + switch (Busy) { + case BUSY_DMA0: + if (Oper == OPER_READ) { + return timing.dma0.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma0.write; + } + else { + return timing.dma0.erase; + } + + break; + case BUSY_DMA1: + if (Oper == OPER_READ) { + return timing.dma1.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma1.write; + } + else { + return timing.dma1.erase; + } + + break; + case BUSY_MEM: { + if (Oper == OPER_ERASE) { + return timing.erase; + } + + if (GetPageType(AddrPage) == PAGE_LSB) { + pTiming = &timing.lsb; + } + else { + pTiming = &timing.msb; + } + + if (Oper == OPER_READ) { + return pTiming->read; + } + else { + return pTiming->write; + } + + break; + } + default: + break; + } + + return 10; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyMLC.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyMLC.h new file mode 100644 index 0000000000..19dbafb088 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyMLC.h @@ -0,0 +1,33 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __LatencyMLC_h__ +#define __LatencyMLC_h__ + +#include "Latency.h" + +class LatencyMLC : public Latency { + public: + LatencyMLC(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + ~LatencyMLC(); + + uint64_t GetLatency(uint32_t, uint8_t, uint8_t) override; + inline uint8_t GetPageType(uint32_t) override; +}; + +#endif //__LatencyMLC_h__ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencySLC.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencySLC.cc new file mode 100644 index 0000000000..a6b6c2a83d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencySLC.cc @@ -0,0 +1,73 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "LatencySLC.h" + +LatencySLC::LatencySLC(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : Latency(t, p) {} + +LatencySLC::~LatencySLC() {} + +inline uint8_t LatencySLC::GetPageType(uint32_t) { + return PAGE_LSB; +} + +uint64_t LatencySLC::GetLatency(uint32_t, uint8_t Oper, uint8_t Busy) { + switch (Busy) { + case BUSY_DMA0: + if (Oper == OPER_READ) { + return timing.dma0.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma0.write; + } + else { + return timing.dma0.erase; + } + + break; + case BUSY_DMA1: + if (Oper == OPER_READ) { + return timing.dma1.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma1.write; + } + else { + return timing.dma1.erase; + } + + break; + case BUSY_MEM: + if (Oper == OPER_READ) { + return timing.lsb.read; + } + else if (Oper == OPER_WRITE) { + return timing.lsb.write; + } + else { + return timing.erase; + } + + break; + default: + break; + } + + return 10; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencySLC.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencySLC.h new file mode 100644 index 0000000000..97da54c931 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencySLC.h @@ -0,0 +1,33 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __LatencySLC_h__ +#define __LatencySLC_h__ + +#include "Latency.h" + +class LatencySLC : public Latency { + public: + LatencySLC(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + ~LatencySLC(); + + uint64_t GetLatency(uint32_t, uint8_t, uint8_t) override; + inline uint8_t GetPageType(uint32_t) override; +}; + +#endif //__LatencyTLC_h__ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyTLC.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyTLC.cc new file mode 100644 index 0000000000..db056acfb9 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyTLC.cc @@ -0,0 +1,90 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "LatencyTLC.h" + +LatencyTLC::LatencyTLC(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : Latency(t, p) {} + +LatencyTLC::~LatencyTLC() {} + +inline uint8_t LatencyTLC::GetPageType(uint32_t AddrPage) { + return (AddrPage <= 5) ? (uint8_t)PAGE_LSB + : ((AddrPage <= 7) ? (uint8_t)PAGE_CSB + : (((AddrPage - 8) >> 1) % 3)); +} + +uint64_t LatencyTLC::GetLatency(uint32_t AddrPage, uint8_t Oper, uint8_t Busy) { + SimpleSSD::PAL::Config::PAGETiming *pTiming = nullptr; + uint8_t pType = GetPageType(AddrPage); + + switch (Busy) { + case BUSY_DMA0: + if (Oper == OPER_READ) { + return timing.dma0.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma0.write; + } + else { + return timing.dma0.erase; + } + + break; + case BUSY_DMA1: + if (Oper == OPER_READ) { + return timing.dma1.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma1.write; + } + else { + return timing.dma1.erase; + } + + break; + case BUSY_MEM: { + if (Oper == OPER_ERASE) { + return timing.erase; + } + + if (pType == PAGE_LSB) { + pTiming = &timing.lsb; + } + else if (pType == PAGE_CSB) { + pTiming = &timing.csb; + } + else { + pTiming = &timing.msb; + } + + if (Oper == OPER_READ) { + return pTiming->read; + } + else { + return pTiming->write; + } + + break; + } + default: + break; + } + + return 10; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyTLC.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyTLC.h new file mode 100644 index 0000000000..fe0d794836 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/LatencyTLC.h @@ -0,0 +1,33 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __LatencyTLC_h__ +#define __LatencyTLC_h__ + +#include "Latency.h" + +class LatencyTLC : public Latency { + public: + LatencyTLC(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + ~LatencyTLC(); + + uint64_t GetLatency(uint32_t, uint8_t, uint8_t) override; + inline uint8_t GetPageType(uint32_t) override; +}; + +#endif //__LatencyTLC_h__ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2.cc new file mode 100644 index 0000000000..1964cb6a36 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2.cc @@ -0,0 +1,963 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#include "PAL2.h" + +#include "util/algorithm.hh" + +PAL2::PAL2(PALStatistics *statistics, SimpleSSD::PAL::Parameter *p, + SimpleSSD::ConfigReader *c, Latency *l) + : pParam(p), lat(l), stats(statistics) { + uint32_t OriginalSizes[7]; + + uint32_t SPDIV = + c->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_DMA_SPEED) / 50; + uint32_t PGDIV = 16384 / c->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE); + + if (SPDIV == 0 || PGDIV == 0) { + SimpleSSD::panic("SPDIV or PGDIV is 0"); + } + + OriginalSizes[ADDR_CHANNEL] = pParam->channel; + OriginalSizes[ADDR_PACKAGE] = pParam->package; + OriginalSizes[ADDR_DIE] = pParam->die; + + if (c->readBoolean(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_USE_MULTI_PLANE_OP)) { + OriginalSizes[ADDR_PLANE] = 1; + } + else { + OriginalSizes[ADDR_PLANE] = pParam->plane; + } + + OriginalSizes[ADDR_BLOCK] = pParam->block; + OriginalSizes[ADDR_PAGE] = pParam->page; + OriginalSizes[6] = 0; // Add remaining bits + + AddrRemap[0] = ADDR_PAGE; + AddrRemap[1] = ADDR_BLOCK; + AddrRemap[2] = ADDR_PLANE; + AddrRemap[3] = ADDR_DIE; + AddrRemap[4] = ADDR_PACKAGE; + AddrRemap[5] = ADDR_CHANNEL; + + RearrangedSizes[6] = OriginalSizes[6]; + for (int i = 0; i < 6; i++) { + RearrangedSizes[i] = OriginalSizes[AddrRemap[i]]; + + // DPRINTF(PAL,"PAL: [%d] ORI(%s): %u --> REARR(%s): %u\n", i, + // ADDR_STRINFO[ i ], OriginalSizes[ i ], ADDR_STRINFO[ gconf->AddrSeq[i] + // ], RearrangedSizes[i]); //Use DPRINTF here + } + + totalDie = pParam->channel * pParam->package * pParam->die; + + ChFreeSlots = + new std::map *>[pParam->channel]; + ChStartPoint = new uint64_t[pParam->channel]; + for (unsigned i = 0; i < pParam->channel; i++) + ChStartPoint[i] = 0; + + DieFreeSlots = + new std::map *>[totalDie]; + DieStartPoint = new uint64_t[totalDie]; + for (unsigned i = 0; i < totalDie; i++) + DieStartPoint[i] = 0; + + // currently, hard code pre-dma, mem-op and post-dma values + for (unsigned i = 0; i < pParam->channel; i++) { + std::map *tmp; + switch ( + c->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_FLASH_TYPE)) { + case SimpleSSD::PAL::NAND_SLC: + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV)] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV) + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][1500000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_MLC: + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV)] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV) + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][1500000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_TLC: + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV)] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV) + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][1500000 / SPDIV] = tmp; + break; + default: + printf("unsupported NAND types!\n"); + std::terminate(); + break; + } + } + + for (unsigned i = 0; i < totalDie; i++) { + std::map *tmp; + switch ( + c->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_FLASH_TYPE)) { + case SimpleSSD::PAL::NAND_SLC: + tmp = new std::map; + DieFreeSlots[i][25000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][300000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][2000000000 + 100000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_MLC: + tmp = new std::map; + DieFreeSlots[i][40000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][90000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][500000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][1300000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][3500000000 + 100000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_TLC: + tmp = new std::map; + DieFreeSlots[i][58000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][78000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][107000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][558000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][2201000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][5001000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][2274000000 + 100000 / SPDIV] = tmp; + break; + default: + printf("unsupported NAND types!\n"); + std::terminate(); + break; + } + } +} + +PAL2::~PAL2() { + FlushTimeSlots(MAX64); + + for (uint i = 0; i < pParam->channel; i++) { + for (auto &iter : ChFreeSlots[i]) { + { + delete iter.second; + iter.second = NULL; + } + } + } + delete[] ChFreeSlots; + + for (uint i = 0; i < totalDie; i++) { + for (auto &iter : DieFreeSlots[i]) { + { + delete iter.second; + iter.second = NULL; + } + } + } + delete[] DieFreeSlots; + + delete[] ChStartPoint; + delete[] DieStartPoint; +} + +void PAL2::TimelineScheduling(Command &req, CPDPBP &reqCPD) { + // ensure we can erase multiple blocks from single request + unsigned erase_block = 1; + /*=========== CONFLICT data gather ============*/ + for (unsigned cur_command = 0; cur_command < erase_block; cur_command++) { +#if GATHER_RESOURCE_CONFLICT + uint8_t confType = CONFLICT_NONE; +#endif + req.ppn = req.ppn - (req.ppn & (erase_block - 1)) + cur_command; + uint32_t reqCh = reqCPD.Channel; + uint32_t reqDieIdx = CPDPBPtoDieIdx(&reqCPD); + TimeSlot tsDMA0, tsMEM, tsDMA1; + uint64_t tickDMA0 = 0, tickMEM = 0, + tickDMA1 = 0; // start tick of the free slot + uint64_t latDMA0, latMEM, latDMA1, totalLat; + uint64_t DMA0tickFrom, MEMtickFrom, DMA1tickFrom; // starting point + uint64_t latANTI; // anticipate time slot + bool conflicts; // check conflict when scheduling + latDMA0 = lat->GetLatency(reqCPD.Page, req.operation, BUSY_DMA0); + latMEM = lat->GetLatency(reqCPD.Page, req.operation, BUSY_MEM); + latDMA1 = lat->GetLatency(reqCPD.Page, req.operation, BUSY_DMA1); + latANTI = lat->GetLatency(reqCPD.Page, OPER_READ, BUSY_DMA0); + // Start Finding available Slot + DMA0tickFrom = req.arrived; // get Current System Time + while (1) // LOOP0 + { + while (1) // LOOP1 + { + // 1a) LOOP1 - Find DMA0 available slot in ChTimeSlots + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA0, DMA0tickFrom, tickDMA0, + conflicts)) { + if (DMA0tickFrom < ChStartPoint[reqCh]) { + DMA0tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA0 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA0tickFrom = tickDMA0; + } + /*=========== CONFLICT check - DMA0 ============*/ +#if GATHER_RESOURCE_CONFLICT + if (conflicts && !(confType & CONFLICT_MEM)) { + confType |= CONFLICT_DMA0; + } +#endif + + // 2b) LOOP1 - Find MEM avaiable slot in DieTimeSlots + MEMtickFrom = DMA0tickFrom; + if (!FindFreeTime(DieFreeSlots[reqDieIdx], (latDMA0 + latMEM), + MEMtickFrom, tickMEM, conflicts)) { + if (MEMtickFrom < DieStartPoint[reqDieIdx]) { + MEMtickFrom = DieStartPoint[reqDieIdx]; + conflicts = true; + } + else { + conflicts = false; + } + tickMEM = DieStartPoint[reqDieIdx]; + } + else { + if (conflicts) + MEMtickFrom = tickMEM; + } + if (tickMEM == tickDMA0) + break; + DMA0tickFrom = MEMtickFrom; + + uint64_t tickDMA0_vrfy; + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA0, DMA0tickFrom, + tickDMA0_vrfy, conflicts)) { + tickDMA0_vrfy = ChStartPoint[reqCh]; + } + if (tickDMA0_vrfy == tickDMA0) + break; + /*=========== CONFLICT check - MEM ============*/ +#if GATHER_RESOURCE_CONFLICT + if (conflicts && !(confType & CONFLICT_DMA0)) { + confType |= CONFLICT_MEM; + } +#endif + + } // LOOP1 + + // 3) Find DMA1 available slot + DMA1tickFrom = DMA0tickFrom + (latDMA0 + latMEM); + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA1 + latANTI, DMA1tickFrom, + tickDMA1, conflicts)) { + if (DMA1tickFrom < ChStartPoint[reqCh]) { + DMA1tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA1 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA1tickFrom = tickDMA1; + } + + // 4) Re-verify MEM slot + // The target die should be free during (DMA0_start ~ DMA1_end) + totalLat = (DMA1tickFrom + latDMA1 + latANTI) - DMA0tickFrom; + uint64_t tickMEM_vrfy; + if (!FindFreeTime(DieFreeSlots[reqDieIdx], totalLat, DMA0tickFrom, + tickMEM_vrfy, conflicts)) { + tickMEM_vrfy = DieStartPoint[reqDieIdx]; + } + if (tickMEM_vrfy == tickMEM) + break; + /*=========== CONFLICT check - DMA1 ============*/ +#if GATHER_RESOURCE_CONFLICT + { confType |= CONFLICT_DMA1; } +#endif + + DMA0tickFrom = tickMEM_vrfy; // or re-search for next available resource! + } // LOOP0 + + // 5) Assign dma0, dma1, mem + { + InsertFreeSlot(ChFreeSlots[reqCh], latDMA0, DMA0tickFrom, tickDMA0, + ChStartPoint[reqCh], 0); + + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA1 + latANTI, DMA1tickFrom, + tickDMA1, conflicts)) { + if (DMA1tickFrom < ChStartPoint[reqCh]) { + DMA1tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA1 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA1tickFrom = tickDMA1; + } + if (DMA1tickFrom > tickDMA1) + InsertFreeSlot(ChFreeSlots[reqCh], latDMA1, DMA1tickFrom + latANTI, + tickDMA1, ChStartPoint[reqCh], 0); + else + InsertFreeSlot(ChFreeSlots[reqCh], latDMA1, tickDMA1 + latANTI, + tickDMA1, ChStartPoint[reqCh], 0); + + // temporarily use previous MergedTimeSlots design + InsertFreeSlot(DieFreeSlots[reqDieIdx], totalLat, DMA0tickFrom, tickMEM, + DieStartPoint[reqDieIdx], 0); + + if (DMA0tickFrom < tickDMA0) + tsDMA0 = TimeSlot(tickDMA0, latDMA0); + else + tsDMA0 = TimeSlot(DMA0tickFrom, latDMA0); + + if (DMA1tickFrom < tickDMA1) + tsDMA1 = TimeSlot(tickDMA1 + latANTI, latDMA1); + else + tsDMA1 = TimeSlot(DMA1tickFrom + latANTI, latDMA1); + + if (DMA0tickFrom < tickMEM) + tsMEM = TimeSlot(tickMEM, totalLat); + else + tsMEM = TimeSlot(DMA0tickFrom, totalLat); + + //******************************************************************// + if (DMA0tickFrom > tickDMA0) + DMA0tickFrom = DMA0tickFrom + latDMA0; + else + DMA0tickFrom = tickDMA0 + latDMA0; + uint64_t tmpTick = DMA0tickFrom; + if (!FindFreeTime(ChFreeSlots[reqCh], latANTI * 2, DMA0tickFrom, tickDMA0, + conflicts)) { + if (DMA0tickFrom < ChStartPoint[reqCh]) { + DMA0tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA0 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA0tickFrom = tickDMA0; + } + if (DMA0tickFrom == tmpTick) + InsertFreeSlot(ChFreeSlots[reqCh], latANTI * 2, DMA0tickFrom, tickDMA0, + ChStartPoint[reqCh], 1); + //******************************************************************// +#if 1 + // Manage MergedTimeSlots + if (MergedTimeSlots.size() == 0) { + MergedTimeSlots.push_back( + TimeSlot(tsMEM.StartTick, tsMEM.EndTick - tsMEM.StartTick + 1)); + } + else { + uint64_t s = tsMEM.StartTick; + uint64_t e = tsMEM.EndTick; + int spnt = 0, epnt = 0; // inside(0), rightside(1) + std::list::iterator cur; + std::list::iterator spos = MergedTimeSlots.end(); + std::list::iterator epos = MergedTimeSlots.end(); + + // find s position + cur = MergedTimeSlots.begin(); + + while (cur != MergedTimeSlots.end()) { + if (cur->StartTick <= s && s <= cur->EndTick) { + spos = cur; + spnt = 0; // inside + break; + } + + auto next = cur; + + next++; + + if ((next == MergedTimeSlots.end()) || + (next != MergedTimeSlots.end() && (s < next->StartTick))) { + spos = cur; + spnt = 1; // rightside + break; + } + + cur = next; + } + + // find e position + cur = MergedTimeSlots.begin(); + + while (cur != MergedTimeSlots.end()) { + if (cur->StartTick <= e && e <= cur->EndTick) { + epos = cur; + epnt = 0; // inside + break; + } + + auto next = cur; + + next++; + + if ((next == MergedTimeSlots.end()) || + (next != MergedTimeSlots.end() && (e < next->StartTick))) { + epos = cur; + epnt = 1; // rightside + break; + } + + cur = next; + } + + // merge + // if both side is in a merged slot, skip + if (!(spos != MergedTimeSlots.end() && epos != MergedTimeSlots.end() && + (spos == epos && spnt == 0 && epnt == 0))) { + if (spos != MergedTimeSlots.end() && + spnt == 1) { // right side of spos + bool update = false; + + if (spos == epos) { + update = true; + } + + // duration will be updated later + // Insert tmp after spos + auto tmp = MergedTimeSlots.insert( + ++spos, + TimeSlot(tsMEM.StartTick, tsMEM.EndTick - tsMEM.StartTick + 1)); + + if (update) { + epos = tmp; + } + + spos = --tmp; // update spos + } + else { + if (epos == MergedTimeSlots.end()) // both new + { + auto tmp = + TimeSlot(tsMEM.StartTick, + tsMEM.EndTick - tsMEM.StartTick + 1); // copy one + + MergedTimeSlots.insert(MergedTimeSlots.begin(), tmp); + } + else { + auto tmp = TimeSlot(tsMEM.StartTick, + 999); // duration will be updated later + spos = MergedTimeSlots.insert(MergedTimeSlots.begin(), tmp); + } + } + + if (epos != MergedTimeSlots.end()) { + if (epnt == 0) { + spos->EndTick = epos->EndTick; + } + else if (epnt == 1) { + spos->EndTick = tsMEM.EndTick; + } + + // remove [ spos->Next ~ epos ] + auto iter = spos; + + for (iter++; iter != epos;) { + iter = MergedTimeSlots.erase(iter); + } + + // We need to erase epos + MergedTimeSlots.erase(epos); + } + } + } +#endif // END MERGE TIMESLOT + } + + // print Log +#if 1 // DBG_PRINT_BUSY + if (1) { +#if DBG_PRINT_REQUEST + // DPRINTF(PAL, + // "PAL: %s PPN 0x%" PRIX64 " ch%02d die%05d : REQTime %" PRIu64 + // "\n", + // OPER_STRINFO[req.operation], req.ppn, reqCPD.Channel, + // reqDieIdx, req.arrived); // Use DPRINTF here + printCPDPBP(&reqCPD); + // DPRINTF(PAL, + // "PAL: %s PPN 0x%" PRIX64 " ch%02d die%05d : DMA0 %" PRIu64 + // " ~ %" PRIu64 " (%" PRIu64 ") , MEM %" PRIu64 " ~ %" PRIu64 + // " (%" PRIu64 ") , DMA1 %" PRIu64 " ~ %" PRIu64 " (%" PRIu64 + // ")\n", OPER_STRINFO[req.operation], req.ppn, reqCPD.Channel, + // reqDieIdx, tsDMA0->StartTick, tsDMA0->EndTick, (tsDMA0->EndTick + // - tsDMA0->StartTick + 1), tsMEM->StartTick, tsMEM->EndTick, + // (tsMEM->EndTick - tsMEM->StartTick + 1) - + // (tsDMA0->EndTick - tsDMA0->StartTick + 1) - + // (tsDMA1->EndTick - tsDMA1->StartTick + 1), + // tsDMA1->StartTick, tsDMA1->EndTick, + // (tsDMA1->EndTick - tsDMA1->StartTick + 1)); // Use DPRINTF + // here + + // DPRINTF(PAL, + // "PAL: %s PPN 0x%" PRIX64 + // " ch%02d die%05d : REQ~DMA0start(%" PRIu64 + // "), DMA0~DMA1end(%" PRIu64 ")\n", + // OPER_STRINFO[req.operation], req.ppn, reqCPD.Channel, + // reqDieIdx, (tsDMA0->StartTick - 1 - req.arrived + 1), + // (tsDMA1->EndTick - tsDMA0->StartTick + 1)); // Use DPRINTF + // here +#endif + } +#endif + + // 6) Write-back latency on RequestLL + req.finished = tsDMA1.EndTick; + + // categorize the time spent for read/write operation + std::map::iterator e; + e = OpTimeStamp[req.operation].find(tsDMA0.StartTick); + if (e != OpTimeStamp[req.operation].end()) { + if (e->second < tsDMA1.EndTick) + e->second = tsDMA1.EndTick; + } + else { + OpTimeStamp[req.operation][tsDMA0.StartTick] = tsDMA1.EndTick; + } + FlushOpTimeStamp(); + + // Update stats +#if 1 + stats->UpdateLastTick(tsDMA1.EndTick); +#if GATHER_RESOURCE_CONFLICT + stats->AddLatency(req, &reqCPD, reqDieIdx, tsDMA0, tsMEM, tsDMA1, confType); +#else + stats->AddLatency(req, &reqCPD, reqDieIdx, tsDMA0, tsMEM, tsDMA1); +#endif +#endif + + if (req.operation == OPER_ERASE || req.mergeSnapshot) { + stats->MergeSnapshot(); + } + } +} + +void PAL2::submit(Command &cmd, CPDPBP &addr) { + TimelineScheduling(cmd, addr); +} + +void PAL2::FlushATimeSlotBusyTime(std::list &tgtTimeSlot, + uint64_t currentTick, uint64_t *TimeSum) { + auto cur = tgtTimeSlot.begin(); + + while (cur != tgtTimeSlot.end()) { + if (cur->EndTick < currentTick) { + *TimeSum += (cur->EndTick - cur->StartTick + 1); + + cur = tgtTimeSlot.erase(cur); + + continue; + } + + break; + } +} + +void PAL2::FlushOpTimeStamp() // currently only used during garbage collection +{ + // flush OpTimeStamp + std::map::iterator e; + for (unsigned Oper = 0; Oper < 3; Oper++) { + uint64_t start_tick = (uint64_t)-1, end_tick = (uint64_t)-1; + for (e = OpTimeStamp[Oper].begin(); e != OpTimeStamp[Oper].end();) { + if (start_tick == (uint64_t)-1 && end_tick == (uint64_t)-1) { + start_tick = e->first; + end_tick = e->second; + } + else if (e->first < end_tick && e->second <= end_tick) { + } + else if (e->first < end_tick && e->second > end_tick) { + end_tick = e->second; + } + else if (e->first >= end_tick) { + stats->OpBusyTime[Oper] += end_tick - start_tick + 1; + start_tick = e->first; + end_tick = e->second; + } + OpTimeStamp[Oper].erase(e); + e = OpTimeStamp[Oper].begin(); + } + stats->OpBusyTime[Oper] += end_tick - start_tick + 1; + } +} + +void PAL2::FlushTimeSlots(uint64_t currentTick) { + FlushATimeSlotBusyTime(MergedTimeSlots, currentTick, &(stats->ExactBusyTime)); + + stats->Access_Capacity.update(); + stats->Ticks_Total.update(); +} + +void PAL2::FlushFreeSlots(uint64_t currentTick) { + for (uint32_t i = 0; i < pParam->channel; i++) { + FlushAFreeSlot(ChFreeSlots[i], currentTick); + } + for (uint32_t i = 0; i < totalDie; i++) { + FlushAFreeSlot(DieFreeSlots[i], currentTick); + } + + FlushATimeSlotBusyTime(MergedTimeSlots, currentTick, &(stats->ExactBusyTime)); + + stats->Access_Capacity.update(); + stats->Ticks_Total.update(); +} + +void PAL2::FlushAFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t currentTick) { + for (std::map *>::iterator e = + tgtFreeSlot.begin(); + e != tgtFreeSlot.end(); e++) { + std::map::iterator f = (e->second)->begin(); + std::map::iterator g = (e->second)->end(); + + for (; f != g;) { + // count++; + if (f->second < currentTick) + (e->second)->erase(f++); + else + break; + } + } +} + +std::list::iterator PAL2::FindFreeTime( + std::list &tgtTimeSlot, uint64_t tickLen, uint64_t fromTick) { + auto cur = tgtTimeSlot.begin(); + auto next = cur; + + while (cur != tgtTimeSlot.end()) { + // printf("FindFreeTime.FIND : cur->ST=%llu, cur->ET=%llu, next=0x%X\n", + // cur->StartTick, cur->EndTick, (unsigned int)next); //DBG + next++; + + if (next == tgtTimeSlot.end()) { + break; + } + + if (cur->EndTick < fromTick && fromTick < next->StartTick) { + if ((next->StartTick - fromTick) >= tickLen) { + // printf("FindFreeTime.RET A: cur->ET=%llu, next->ST=%llu, ft=%llu, + // tickLen=%llu\n", cur->EndTick, next->StartTick, fromTick, tickLen); + // //DBG + break; + } + } + else if (fromTick <= cur->EndTick) { + if ((next->StartTick - (cur->EndTick + 1)) >= tickLen) { + break; + } + } + + cur++; + } + + // v-- this condition looks strange? but [minus of uint64_t values] do not + // work correctly without this! + if ((tgtTimeSlot.begin()->StartTick > fromTick) && + ((tgtTimeSlot.begin()->StartTick - fromTick) >= tickLen)) { + cur = tgtTimeSlot.end(); // if there is an available time slot before first + // cmd, return NULL! + } + + return cur; +} + +bool PAL2::FindFreeTime( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t &startTick, bool &conflicts) { + auto e = tgtFreeSlot.upper_bound(tickLen); + if (e == tgtFreeSlot.end()) { + e--; // Jie: tgtFreeSlot is not empty + auto f = (e->second)->upper_bound(tickFrom); + if (f != (e->second)->begin()) { + f--; + if (f->second >= tickLen + tickFrom - (uint64_t)1) { + startTick = f->first; + conflicts = false; + return true; + } + f++; + } + while (f != (e->second)->end()) { + if (f->second >= tickLen + f->first - 1) { + startTick = f->first; + conflicts = true; + return true; + } + f++; + } + // reach this means no FreeSlot satisfy the requirement; allocate unused + // slots startTick will be updated in upper function + conflicts = false; + return false; + } + if (e != tgtFreeSlot.begin()) + e--; + uint64_t minTick = (uint64_t)-1; + while (e != tgtFreeSlot.end()) { + std::map::iterator f = + (e->second)->upper_bound(tickFrom); + if (f != (e->second)->begin()) { + f--; + if (f->second >= + tickLen + tickFrom - (uint64_t)1) { // this free slot is + // best fit one, skip + // checking others + startTick = f->first; + conflicts = false; + return true; + } + f++; + } + while (f != (e->second)->end()) { + if (f->second >= tickLen + f->first - (uint64_t)1) { + if (minTick == (uint64_t)-1 || minTick > f->first) { + conflicts = true; + minTick = f->first; + } + break; + } + f++; + } + e++; + } + if (minTick == (uint64_t)-1) { + // startTick will be updated in upper function + conflicts = false; + return false; + } + else { + startTick = minTick; + return true; + } +} + +void PAL2::InsertFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t startTick, + uint64_t &startPoint, bool split) { + if (startTick == startPoint) { + if (tickFrom == startTick) { + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, startPoint); + startPoint = startPoint + tickLen; // Jie: just need to shift startPoint + } + else { + assert(tickFrom > startTick); + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, tickFrom); + startPoint = tickFrom + tickLen; + AddFreeSlot(tgtFreeSlot, tickFrom - startTick, startTick); + } + } + else { + std::pair *>::iterator, + std::map *>::iterator> + ePair; + ePair = tgtFreeSlot.equal_range(tickLen); + std::map::iterator f; + std::map *>::iterator e = + tgtFreeSlot.upper_bound(tickLen); + if (e != tgtFreeSlot.begin()) + e--; + while (e != tgtFreeSlot.end()) { + f = e->second->find(startTick); + if (f != e->second->end()) { + uint64_t tmpStartTick = f->first; + uint64_t tmpEndTick = f->second; + e->second->erase(f); + if (tmpStartTick < tickFrom) { + AddFreeSlot(tgtFreeSlot, tickFrom - tmpStartTick, tmpStartTick); + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, tickFrom); + assert(tmpEndTick - tickFrom + 1 >= tickLen); + if (tmpEndTick > tickLen + tickFrom - (uint64_t)1) { + AddFreeSlot(tgtFreeSlot, tmpEndTick - (tickFrom + tickLen - 1), + tickFrom + tickLen); + } + } + else { + assert(tmpStartTick == tickFrom); + assert(tmpEndTick - tickFrom + 1 >= tickLen); + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, tmpStartTick); + if (tmpEndTick > tickLen + tickFrom - (uint64_t)1) { + AddFreeSlot(tgtFreeSlot, tmpEndTick - (tickFrom + tickLen - 1), + tmpStartTick + tickLen); + } + } + break; + } + e++; + } + } +} + +void PAL2::AddFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom) { + std::map *>::iterator e; + e = tgtFreeSlot.upper_bound(tickLen); + if (e != tgtFreeSlot.begin()) { + e--; + (e->second)->insert(std::pair( + tickFrom, tickFrom + tickLen - (uint64_t)1)); + } +} +// PPN number conversion +uint32_t PAL2::CPDPBPtoDieIdx(CPDPBP *pCPDPBP) { + //[Channel][Package][Die]; + uint32_t ret = 0; + ret += pCPDPBP->Die; + ret += pCPDPBP->Package * pParam->die; + ret += pCPDPBP->Channel * pParam->die * pParam->package; + + return ret; +} + +void PAL2::printCPDPBP(CPDPBP *) {} +// void PAL2::printCPDPBP(CPDPBP *pCPDPBP) { +// uint32_t *pCPDPBP_IDX = ((uint32_t *)pCPDPBP); +// +// DPRINTF(PAL, "PAL: %7s | %7s | %7s | %7s | %7s | %7s\n", +// ADDR_STRINFO[gconf->AddrSeq[0]], ADDR_STRINFO[gconf->AddrSeq[1]], +// ADDR_STRINFO[gconf->AddrSeq[2]], ADDR_STRINFO[gconf->AddrSeq[3]], +// ADDR_STRINFO[gconf->AddrSeq[4]], +// ADDR_STRINFO[gconf->AddrSeq[5]]); // Use DPRINTF here +// DPRINTF(PAL, "PAL: %7u | %7u | %7u | %7u | %7u | %7u\n", +// pCPDPBP_IDX[gconf->AddrSeq[0]], pCPDPBP_IDX[gconf->AddrSeq[1]], +// pCPDPBP_IDX[gconf->AddrSeq[2]], pCPDPBP_IDX[gconf->AddrSeq[3]], +// pCPDPBP_IDX[gconf->AddrSeq[4]], +// pCPDPBP_IDX[gconf->AddrSeq[5]]); // Use DPRINTF here +// } + +void PAL2::PPNdisassemble(uint64_t *pPPN, CPDPBP *pCPDPBP) { + uint32_t *pCPDPBP_IDX = ((uint32_t *)pCPDPBP); + uint64_t tmp_MOD = *pPPN; + uint8_t *AS = AddrRemap; + uint32_t *RS = RearrangedSizes; + for (uint32_t i = 0; i < 6; i++) { + pCPDPBP_IDX[i] = 0; + } + if (RS[6] == 0) // there is no misalignment + { + pCPDPBP_IDX[AS[0]] = tmp_MOD / (RS[5] * RS[4] * RS[3] * RS[2] * RS[1]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4] * RS[3] * RS[2] * RS[1]); + + pCPDPBP_IDX[AS[1]] = tmp_MOD / (RS[5] * RS[4] * RS[3] * RS[2]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4] * RS[3] * RS[2]); + + pCPDPBP_IDX[AS[2]] = tmp_MOD / (RS[5] * RS[4] * RS[3]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4] * RS[3]); + + pCPDPBP_IDX[AS[3]] = tmp_MOD / (RS[5] * RS[4]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4]); + + pCPDPBP_IDX[AS[4]] = tmp_MOD / (RS[5]); + tmp_MOD = tmp_MOD % (RS[5]); + + pCPDPBP_IDX[AS[5]] = tmp_MOD; + } + else { + uint32_t tmp_size = RS[6] * RS[5] * RS[4] * RS[3] * RS[2] * RS[1] * RS[0]; + for (int i = 0; i < (4 - AS[6]); i++) { + tmp_size /= RS[i]; + pCPDPBP_IDX[AS[i]] = tmp_MOD / tmp_size; + tmp_MOD = tmp_MOD % tmp_size; + } + tmp_size /= RS[6]; + uint32_t tmp = tmp_MOD / tmp_size; + tmp_MOD = tmp_MOD % tmp_size; + for (int i = (4 - AS[6]); i < 6; i++) { + tmp_size /= RS[i]; + pCPDPBP_IDX[AS[i]] = tmp_MOD / tmp_size; + tmp_MOD = tmp_MOD % tmp_size; + } + pCPDPBP_IDX[AS[5 - AS[6]]] *= tmp; + } + +#if DBG_PRINT_PPN + DPRINTF(PAL, "PAL: 0x%llX (%llu) ==>\n", *pPPN, + *pPPN); // Use DPRINTF here + printCPDPBP(pCPDPBP); +#endif +} + +void PAL2::AssemblePPN(CPDPBP *pCPDPBP, uint64_t *pPPN) { + uint64_t AddrPPN = 0; + + // with re-arrange ... I hate current structure! too dirty even made with + // FOR-LOOP! (less-readability) + uint32_t *pCPDPBP_IDX = ((uint32_t *)pCPDPBP); + uint8_t *AS = AddrRemap; + uint32_t *RS = RearrangedSizes; + AddrPPN += pCPDPBP_IDX[AS[5]]; + AddrPPN += pCPDPBP_IDX[AS[4]] * (RS[5]); + AddrPPN += pCPDPBP_IDX[AS[3]] * (RS[5] * RS[4]); + AddrPPN += pCPDPBP_IDX[AS[2]] * (RS[5] * RS[4] * RS[3]); + AddrPPN += pCPDPBP_IDX[AS[1]] * (RS[5] * RS[4] * RS[3] * RS[2]); + AddrPPN += pCPDPBP_IDX[AS[0]] * (RS[5] * RS[4] * RS[3] * RS[2] * RS[1]); + + *pPPN = AddrPPN; + +#if DBG_PRINT_PPN + printCPDPBP(pCPDPBP); + DPRINTF(PAL, "PAL ==> 0x%llx (%llu)\n", *pPPN, *pPPN); // Use DPRINTF here +#endif +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2.h new file mode 100644 index 0000000000..75b56398f7 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2.h @@ -0,0 +1,105 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#ifndef __PAL2_h__ +#define __PAL2_h__ + +#include "util/old/SimpleSSD_types.h" + +#include "Latency.h" +#include "PALStatistics.h" +#include "pal/pal.hh" + +#include "PAL2_TimeSlot.h" + +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +class PALStatistics; + +class PAL2 // let's not inherit PAL1 +{ + public: + PAL2(PALStatistics *statistics, SimpleSSD::PAL::Parameter *p, + SimpleSSD::ConfigReader *c, Latency *l); + ~PAL2(); + + SimpleSSD::PAL::Parameter *pParam; + Latency *lat; + PALStatistics *stats; // statistics of PAL2, not created by itself + + std::list MergedTimeSlots; // for gathering busy time + + uint64_t totalDie; + + std::map OpTimeStamp[3]; + + std::map *> *ChFreeSlots; + uint64_t *ChStartPoint; // record the start point of rightmost free slot + std::map *> *DieFreeSlots; + uint64_t *DieStartPoint; + + void submit(Command &cmd, CPDPBP &addr); + void TimelineScheduling(Command &req, CPDPBP &reqCPD); + void FlushTimeSlots(uint64_t currentTick); + void FlushOpTimeStamp(); + void FlushATimeSlotBusyTime(std::list &tgtTimeSlot, + uint64_t currentTick, uint64_t *TimeSum); + + // you can insert a tickLen + // TimeSlot after Returned + // TimeSlot. + std::list::iterator FindFreeTime(std::list &tgtTimeSlot, + uint64_t tickLen, + uint64_t tickFrom); + + // Jie: return: FreeSlot is found? + bool FindFreeTime( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t &startTick, + bool &conflicts); + void InsertFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t startTick, + uint64_t &startPoint, bool split); + void AddFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom); + void FlushFreeSlots(uint64_t currentTick); + void FlushAFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t currentTick); + + // PPN Conversion related //ToDo: Shifted-Mode is also required for better + // performance. + uint32_t RearrangedSizes[7]; + uint8_t AddrRemap[6]; + uint32_t CPDPBPtoDieIdx(CPDPBP *pCPDPBP); + void printCPDPBP(CPDPBP *pCPDPBP); + void PPNdisassemble(uint64_t *pPPN, CPDPBP *pCPDPBP); + void AssemblePPN(CPDPBP *pCPDPBP, uint64_t *pPPN); +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2_TimeSlot.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2_TimeSlot.cc new file mode 100644 index 0000000000..bc3ff93756 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2_TimeSlot.cc @@ -0,0 +1,25 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#include "PAL2_TimeSlot.h" + +TimeSlot::TimeSlot(uint64_t startTick, uint64_t duration) { + StartTick = startTick; + EndTick = startTick + duration - 1; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2_TimeSlot.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2_TimeSlot.h new file mode 100644 index 0000000000..4ed6563029 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PAL2_TimeSlot.h @@ -0,0 +1,43 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#ifndef __PAL2_TimeSlot_h__ +#define __PAL2_TimeSlot_h__ + +#include "util/old/SimpleSSD_types.h" + +#include +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +struct TimeSlot { + uint64_t StartTick; + uint64_t EndTick; + + TimeSlot(uint64_t startTick, uint64_t duration); + TimeSlot() : StartTick(0ull), EndTick(0ull){}; +}; + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PALStatistics.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PALStatistics.cc new file mode 100644 index 0000000000..e1ba2ea2c0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PALStatistics.cc @@ -0,0 +1,1111 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#include "PALStatistics.h" +#include "util/algorithm.hh" +#include "util/old/SimpleSSD_types.h" + +char ADDR_STRINFO[ADDR_NUM][10] = {"Channel", "Package", "Die", + "Plane", "Block", "Page"}; +char ADDR_STRINFO2[ADDR_NUM][15] = {"ADDR_CHANNEL", "ADDR_PACKAGE", + "ADDR_DIE", "ADDR_PLANE", + "ADDR_BLOCK", "ADDR_PAGE"}; +char OPER_STRINFO[OPER_NUM][10] = {"R", "W", "E"}; +char OPER_STRINFO2[OPER_NUM][10] = {"Read ", "Write", "Erase"}; +char BUSY_STRINFO[BUSY_NUM][10] = {"IDLE", "DMA0", "MEM", + "DMA1WAIT", "DMA1", "END"}; +char PAGE_STRINFO[PAGE_NUM][10] = {"LSB", "CSB", "MSB"}; +char NAND_STRINFO[NAND_NUM][10] = {"SLC", "MLC", "TLC"}; +#if GATHER_RESOURCE_CONFLICT +char CONFLICT_STRINFO[CONFLICT_NUM][10] = {"NONE", "DMA0", "MEM", "DMA1"}; +#endif + +PALStatistics::Counter::Counter() { + init(); +} + +void PALStatistics::Counter::init() { + cnt = 0; +} + +void PALStatistics::Counter::add() { + cnt++; +} + +PALStatistics::CounterOper::CounterOper() { + init(); +} + +void PALStatistics::CounterOper::init() { + for (int i = 0; i < OPER_ALL; i++) + cnts[i].init(); +} + +void PALStatistics::CounterOper::add(uint32_t oper) { + cnts[oper].add(); + cnts[OPER_NUM].add(); +} + +void PALStatistics::CounterOper::printstat(const char *) {} +// void PALStatistics::CounterOper::printstat(const char *namestr) { +// char OPER_STR[OPER_ALL][8] = {"Read ", "Write", "Erase", "Total"}; +// DPRINTF(PAL, "[ %s ]:\n", namestr); +// DPRINTF(PAL, "OPER, COUNT\n"); +// for (int i = 0; i < OPER_ALL; i++) { +// DPRINTF(PAL, "%s, %" PRIu64 "\n", OPER_STR[i], cnts[i].cnt); +// } +// } + +PALStatistics::Value::Value() { + init(); +} + +void PALStatistics::Value::init() { + sum = 0; + cnt = 0; + sampled_sum = 0; + sampled_cnt = 0; + minval = MAX64; + maxval = 0; + legacy_sum = 0; + legacy_cnt = 0; + legacy_minval = MAX64; + legacy_maxval = 0; +} +void PALStatistics::Value::backup() { + sampled_sum = sum; + sampled_cnt = cnt; +} + +void PALStatistics::Value::update() { + legacy_sum = sum; + legacy_cnt = cnt; + legacy_minval = minval; + legacy_maxval = maxval; +} + +void PALStatistics::Value::add(double val) { + sum += val; + cnt += 1; + minval = MIN(val, minval); + maxval = MAX(val, maxval); +} + +double PALStatistics::Value::avg() { + return SAFEDIV(sum, cnt); +} + +double PALStatistics::Value::legacy_avg() { + return SAFEDIV(legacy_sum, legacy_cnt); +} + +PALStatistics::ValueOper::ValueOper() { + init(); +} +PALStatistics::ValueOper::ValueOper(ValueOper *_ValueOper) { + for (int i = 0; i < OPER_ALL; i++) { + vals[i].sum = _ValueOper->vals[i].sum; + vals[i].cnt = _ValueOper->vals[i].cnt; + vals[i].sampled_sum = _ValueOper->vals[i].sampled_sum; + vals[i].sampled_cnt = _ValueOper->vals[i].sampled_cnt; + vals[i].minval = _ValueOper->vals[i].minval; + vals[i].maxval = _ValueOper->vals[i].maxval; + vals[i].legacy_sum = _ValueOper->vals[i].legacy_sum; + vals[i].legacy_cnt = _ValueOper->vals[i].legacy_cnt; + vals[i].legacy_minval = _ValueOper->vals[i].legacy_minval; + vals[i].legacy_maxval = _ValueOper->vals[i].legacy_maxval; + } +} + +void PALStatistics::ValueOper::init() { + for (int i = 0; i < OPER_ALL; i++) + vals[i].init(); +} + +void PALStatistics::ValueOper::update() { + for (int i = 0; i < OPER_ALL; i++) + vals[i].update(); +} + +void PALStatistics::ValueOper::add(uint32_t oper, double val) { + vals[oper].add(val); + vals[OPER_NUM].add(val); +} + +void PALStatistics::ValueOper::exclusive_add(uint32_t oper, double val) { + vals[oper].add(val); +} + +void PALStatistics::ValueOper::printstat(const char *) {} +// void PALStatistics::ValueOper::printstat( +// const char *namestr) // This is only used by access capacity +// { +// char OPER_STR[OPER_ALL][8] = {"Read ", "Write", "Erase", "Total"}; +// DPRINTF(PAL, "[ %s ]:\n", namestr); +// DPRINTF(PAL, "OPER, AVERAGE, COUNT, TOTAL, MIN, MAX\n"); +// for (int i = 0; i < OPER_ALL; i++) { +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s, ( NO DATA )\n", OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s, %" PRIu64 ", %" PRIu64 ", %" PRIu64 ", %" PRIu64 ", %" +// PRIu64 +// "\n", +// OPER_STR[i], (uint64_t)vals[i].avg(), (uint64_t)vals[i].cnt, +// (uint64_t)vals[i].sum, (uint64_t)vals[i].minval, +// (uint64_t)vals[i].maxval); +// } +// } +// } + +void PALStatistics::getTickStat(OperStats &stat) { + stat.read = Ticks_Total.vals[OPER_READ].avg(); + stat.write = Ticks_Total.vals[OPER_WRITE].avg(); + stat.erase = Ticks_Total.vals[OPER_ERASE].avg(); + stat.total = Ticks_Total.vals[OPER_NUM].avg(); +} + +void PALStatistics::getEnergyStat(OperStats &stat) { + // val = [pJ] / [10^6] = [uJ] + stat.read = Energy_Total.vals[OPER_READ].sum / 1000000; // uJ + stat.write = Energy_Total.vals[OPER_WRITE].sum / 1000000; // uJ + stat.erase = Energy_Total.vals[OPER_ERASE].sum / 1000000; // uJ + stat.total = stat.read + stat.write + stat.erase; +} + +void PALStatistics::ValueOper::printstat_energy(const char *) {} +// void PALStatistics::ValueOper::printstat_energy(const char *namestr) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// printf("[ %s ]:\n", namestr); +// printf("PAL: OPER, AVERAGE(nJ), COUNT, TOTAL(uJ)\n"); +// +// for (int i = 0; i < OPER_ALL; i++) { +// if (vals[i].cnt == 0) { +// printf("PAL: %s, ( NO DATA )\n", OPER_STR[i]); +// } +// else { +// printf("PAL: %s, %llu, %llu, %llu\n", OPER_STR[i], +// (uint64_t)vals[i].avg() / 1000000, (uint64_t)vals[i].cnt, +// (uint64_t)vals[i].sum / 1000000); +// } +// } +// } + +// get average tick spent in each step during read +void PALStatistics::getReadBreakdown(Breakdown &value) { + value.dma0wait = Ticks_DMA0WAIT.vals[OPER_READ].avg(); + value.dma0 = Ticks_DMA0.vals[OPER_READ].avg(); + value.mem = Ticks_MEM.vals[OPER_READ].avg(); + value.dma1wait = Ticks_DMA1WAIT.vals[OPER_READ].avg(); + value.dma1 = Ticks_DMA1.vals[OPER_READ].avg(); +} + +// get average tick spent in each step during write +void PALStatistics::getWriteBreakdown(Breakdown &value) { + value.dma0wait = Ticks_DMA0WAIT.vals[OPER_WRITE].avg(); + value.dma0 = Ticks_DMA0.vals[OPER_WRITE].avg(); + value.mem = Ticks_MEM.vals[OPER_WRITE].avg(); + value.dma1wait = Ticks_DMA1WAIT.vals[OPER_WRITE].avg(); + value.dma1 = Ticks_DMA1.vals[OPER_WRITE].avg(); +} + +void PALStatistics::getEraseBreakdown(Breakdown &value) { + value.dma0wait = Ticks_DMA0WAIT.vals[OPER_ERASE].avg(); + value.dma0 = Ticks_DMA0.vals[OPER_ERASE].avg(); + value.mem = Ticks_MEM.vals[OPER_ERASE].avg(); + value.dma1wait = Ticks_DMA1WAIT.vals[OPER_ERASE].avg(); + value.dma1 = Ticks_DMA1.vals[OPER_ERASE].avg(); +} + +void PALStatistics::getChannelActiveTime(uint32_t c, ActiveTime &stat) { + static uint32_t numOfChannel = + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + + if (c < numOfChannel) { + stat.min = Ticks_Active_ch[c].vals[OPER_NUM].minval; + stat.max = Ticks_Active_ch[c].vals[OPER_NUM].maxval; + stat.average = Ticks_Active_ch[c].vals[OPER_NUM].avg(); + } +} + +void PALStatistics::getDieActiveTime(uint32_t d, ActiveTime &stat) { + if (d < totalDie) { + stat.min = Ticks_Active_die[d].vals[OPER_NUM].minval; + stat.max = Ticks_Active_die[d].vals[OPER_NUM].maxval; + stat.average = Ticks_Active_die[d].vals[OPER_NUM].avg(); + } +} + +void PALStatistics::getChannelActiveTimeAll(ActiveTime &stat) { + static uint32_t numOfChannel = + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + ActiveTime tmp; + + stat.min = (double)std::numeric_limits::max(); + stat.max = 0.; + stat.average = 0.; + + for (uint32_t i = 0; i < numOfChannel; i++) { + getChannelActiveTime(i, tmp); + + if (stat.min > tmp.min) { + stat.min = tmp.min; + } + if (stat.max < tmp.max) { + stat.max = tmp.max; + } + + stat.average += tmp.average; + } + + stat.average /= numOfChannel; +} + +void PALStatistics::getDieActiveTimeAll(ActiveTime &stat) { + ActiveTime tmp; + + stat.min = (double)std::numeric_limits::max(); + stat.max = 0.; + stat.average = 0.; + + for (uint32_t i = 0; i < totalDie; i++) { + getDieActiveTime(i, tmp); + + if (stat.min > tmp.min) { + stat.min = tmp.min; + } + if (stat.max < tmp.max) { + stat.max = tmp.max; + } + + stat.average += tmp.average; + } + + stat.average /= totalDie; +} + +void PALStatistics::PrintDieIdleTicks(uint32_t, uint64_t, uint64_t) {} +// void PALStatistics::PrintDieIdleTicks(uint32_t die_num, uint64_t sim_time_ps, +// uint64_t idle_power_nw) { +// uint64_t active_time_ps = Ticks_Active_die[die_num].vals[OPER_ALL - 1].sum; +// uint64_t idle_time_ps = sim_time_ps - active_time_ps; +// uint64_t idle_energy = idle_power_nw * idle_time_ps; +// +// printf("PAL: Idle(pJ), Die%d, %llu\n", die_num, idle_energy / 1000000000); +// } + +void PALStatistics::ValueOper::printstat_bandwidth(class ValueOper *, uint64_t, + uint64_t) {} +// void PALStatistics::ValueOper::printstat_bandwidth( +// class ValueOper *Access_Capacity, uint64_t ExactBusyTime, +// uint64_t LastExactBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// if (ExactBusyTime > LastExactBusyTime) { +// // +// printf("sum=%f\tsampled_sum=%f\n", Access_Capacity->vals[i].sum, +// Access_Capacity->vals[i].sampled_sum); +// this->exclusive_add( +// i, (Access_Capacity->vals[i].sum - +// Access_Capacity->vals[i].sampled_sum) * +// 1.0 / MBYTE / +// ((ExactBusyTime - LastExactBusyTime) * 1.0 / PSEC)); +// } +// if (vals[i].cnt == 0) { +// DPRINTF( +// PAL, "%s bandwidth excluding idle time (min, max, average): ( NO +// DATA +// )\n ", OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s bandwidth excluding idle time (min, max, average): %.6lf " +// "MB/s, %.6lf MB/s, %.6lf MB/s\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].sum) * 1.0 / MBYTE / +// ((ExactBusyTime)*1.0 / PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_bandwidth_widle(class ValueOper *, + uint64_t, uint64_t) {} +// void PALStatistics::ValueOper::printstat_bandwidth_widle( +// class ValueOper *Access_Capacity, uint64_t ExecutionTime, +// uint64_t LastExecutionTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// assert(ExecutionTime > LastExecutionTime); +// this->exclusive_add( +// i, +// (Access_Capacity->vals[i].sum - Access_Capacity->vals[i].sampled_sum) +// * +// 1.0 / MBYTE / ((ExecutionTime - LastExecutionTime) * 1.0 / +// PSEC)); +// +// if (vals[i].cnt == 0) { +// DPRINTF( +// PAL, "%s bandwidth including idle time (min, max, average): ( NO +// DATA +// )\n ", OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s bandwidth including idle time (min, max, average): %.6lf " +// "MB/s, %.6lf MB/s, %.6lf MB/s\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].sum) * 1.0 / MBYTE / +// ((ExecutionTime)*1.0 / PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_oper_bandwidth(class ValueOper *, + uint64_t *, + uint64_t *) {} +// void PALStatistics::ValueOper::printstat_oper_bandwidth( +// class ValueOper *Access_Capacity, uint64_t *OpBusyTime, +// uint64_t *LastOpBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < 3; i++) // only read/write/erase +// { +// if (OpBusyTime[i] > LastOpBusyTime[i]) +// this->exclusive_add( +// i, (Access_Capacity->vals[i].sum - +// Access_Capacity->vals[i].sampled_sum) * +// 1.0 / MBYTE / +// ((OpBusyTime[i] - LastOpBusyTime[i]) * 1.0 / PSEC)); +// +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s-only bandwidth (min, max, average): ( NO DATA )\n", +// OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s-only bandwidth (min, max, average): %.6lf MB/s, %.6lf MB/s, +// " +// "%.6lf MB/s\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].sum) * 1.0 / MBYTE / +// ((OpBusyTime[i]) * 1.0 / PSEC)); +// } +// } +// } +void PALStatistics::ValueOper::printstat_iops(class ValueOper *, uint64_t, + uint64_t) {} +// void PALStatistics::ValueOper::printstat_iops(class ValueOper +// *Access_Capacity, +// uint64_t ExactBusyTime, +// uint64_t LastExactBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// if (ExactBusyTime > LastExactBusyTime) +// this->exclusive_add( +// i, (Access_Capacity->vals[i].cnt - +// Access_Capacity->vals[i].sampled_cnt) * +// 1.0 / ((ExactBusyTime - LastExactBusyTime) * 1.0 / PSEC)); +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s IOPS excluding idle time (min, max, average): ( NO +// DATA +// )\n ", OPER_STR[i]); +// } +// else { +// DPRINTF( +// PAL, +// "%s IOPS excluding idle time (min, max, average): %.6lf, %.6lf, " +// "%.6lf\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].cnt) * 1.0 / ((ExactBusyTime)*1.0 / +// PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_iops_widle(class ValueOper *, uint64_t, + uint64_t) {} +// void PALStatistics::ValueOper::printstat_iops_widle( +// class ValueOper *Access_Capacity, uint64_t ExecutionTime, +// uint64_t LastExecutionTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// this->exclusive_add( +// i, +// (Access_Capacity->vals[i].cnt - Access_Capacity->vals[i].sampled_cnt) +// * +// 1.0 / ((ExecutionTime - LastExecutionTime) * 1.0 / PSEC)); +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, +// "%s IOPS including idle time (min, max, average): ( NO DATA +// )\n", OPER_STR[i]); +// } +// else { +// DPRINTF( +// PAL, +// "%s IOPS including idle time (min, max, average): %.6lf, %.6lf, " +// "%.6lf\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].cnt) * 1.0 / ((ExecutionTime)*1.0 / +// PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_oper_iops(class ValueOper *, + uint64_t *, uint64_t *) {} +// void PALStatistics::ValueOper::printstat_oper_iops( +// class ValueOper *Access_Capacity, uint64_t *OpBusyTime, +// uint64_t *LastOpBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < 3; i++) // only read/write/erase +// { +// if (OpBusyTime[i] > LastOpBusyTime[i]) +// this->exclusive_add( +// i, (Access_Capacity->vals[i].cnt - +// Access_Capacity->vals[i].sampled_cnt) * +// 1.0 / ((OpBusyTime[i] - LastOpBusyTime[i]) * 1.0 / PSEC)); +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s-only IOPS (min, max, average): ( NO DATA )\n", +// OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, "%s-only IOPS (min, max, average): %.6lf, %.6lf, %.6lf\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].cnt) * 1.0 / +// ((OpBusyTime[i]) * 1.0 / PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_latency(const char *) {} +// void PALStatistics::ValueOper::printstat_latency(const char *namestr) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s latency (min, max, average): ( NO DATA )\n", +// OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s latency (min, max, average): %" PRIu64 " us, %" PRIu64 +// " us, %" PRIu64 " us\n", +// OPER_STR[i], (uint64_t)(vals[i].minval * 1.0 / 1000000), +// (uint64_t)(vals[i].maxval * 1.0 / 1000000), +// (uint64_t)(vals[i].avg() * 1.0 / 1000000)); +// } +// } +// } + +PALStatistics::PALStatistics(SimpleSSD::ConfigReader *c, Latency *l) + : gconf(c), lat(l) { + LastTick = 0; + + InitStats(); + + SampledTick = 0; + skip = true; +} + +PALStatistics::~PALStatistics() { + // PrintStats(curTick()); + ClearStats(); +} + +void PALStatistics::ResetStats() { + ClearStats(); + InitStats(); +} + +void PALStatistics::InitStats() { + sim_start_time_ps = 0; + + ExactBusyTime = 0; + LastExactBusyTime = 0; + LastExecutionTime = 0; + OpBusyTime[0] = OpBusyTime[1] = OpBusyTime[2] = 0; + LastOpBusyTime[0] = LastOpBusyTime[1] = LastOpBusyTime[2] = 0; + + totalDie = + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + totalDie *= + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_PACKAGE); + totalDie *= gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_DIE); + + PPN_requested_ch = new CounterOper[gconf->readUint( + SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL)]; + PPN_requested_die = new CounterOper[totalDie]; + Ticks_Active_ch = new ValueOper[gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::PAL_CHANNEL)]; + Ticks_Active_die = new ValueOper[totalDie]; + + PPN_requested_rwe.init(); + for (int j = 0; j < PAGE_ALL; j++) { + PPN_requested_pagetype[j].init(); + }; + // PPN_requested_ch + // PPN_requested_die + CF_DMA0_dma.init(); + CF_DMA0_mem.init(); + CF_DMA0_none.init(); + CF_DMA1_dma.init(); + CF_DMA1_none.init(); + + Ticks_DMA0WAIT.init(); + Ticks_DMA0.init(); + Ticks_MEM.init(); + Ticks_DMA1WAIT.init(); + Ticks_DMA1.init(); + Ticks_Total.init(); + Ticks_TotalOpti.init(); + // Ticks_Active_ch + Energy_DMA0.init(); + Energy_MEM.init(); + Energy_DMA1.init(); + Energy_Total.init(); + + // Ticks_Active_ch + // Ticks_Active_die + Access_Capacity.init(); + Access_Bandwidth.init(); + Access_Bandwidth_widle.init(); + Access_Oper_Bandwidth.init(); + Access_Iops.init(); + Access_Iops_widle.init(); + Access_Oper_Iops.init(); +} + +void PALStatistics::ClearStats() { + delete[] PPN_requested_ch; + delete[] PPN_requested_die; + delete[] Ticks_Active_ch; + delete[] Ticks_Active_die; + + for (auto &iter : Ticks_Total_snapshot) { + delete iter.second; + } + + for (auto &iter : Access_Capacity_snapshot) { + delete iter.second; + } +} + +void PALStatistics::UpdateLastTick(uint64_t tick) { + if (LastTick < tick) + LastTick = tick; +} + +uint64_t PALStatistics::GetLastTick() { + return LastTick; +} + +void PALStatistics::MergeSnapshot() { + if (Ticks_Total_snapshot.size() != 0) { + std::map::iterator e = Ticks_Total_snapshot.end(); + e--; + for (std::map::iterator f = + Ticks_Total_snapshot.begin(); + f != e;) { + delete f->second; + Ticks_Total_snapshot.erase(f++); + } + } + if (Access_Capacity_snapshot.size() != 0) { + std::map::iterator e = + Access_Capacity_snapshot.end(); + e--; + for (std::map::iterator f = + Access_Capacity_snapshot.begin(); + f != e;) { + delete f->second; + Access_Capacity_snapshot.erase(f++); + } + } +} + +#if GATHER_RESOURCE_CONFLICT +void PALStatistics::AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, + TimeSlot &DMA0, TimeSlot &MEM, TimeSlot &DMA1, + uint8_t confType) +#else +void PALStatistics::AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, + TimeSlot &DMA0, TimeSlot &MEM, TimeSlot &DMA1) +#endif +{ + uint32_t oper = CMD.operation; + uint32_t chIdx = CPD->Channel; + uint64_t time_all[TICK_STAT_NUM]; + uint8_t pageType = lat->GetPageType(CPD->Page); + memset(time_all, 0, sizeof(time_all)); + + /* + TICK_IOREQUESTED, CMD.arrived_time + TICK_DMA0WAIT, let it 0 + TICK_DMA0, DMA0->StartTick + TICK_MEM, MEM->StartTick + TICK_DMA1WAIT, + TICK_DMA1, DMA1->StartTick + TICK_IOEND, DMA1->TickEnd + */ + + time_all[TICK_DMA0WAIT] = + DMA0.StartTick - + CMD.arrived; // FETCH_WAIT --> when DMA0 couldn't start immediatly + time_all[TICK_DMA0] = lat->GetLatency(CPD->Page, CMD.operation, BUSY_DMA0); + time_all[TICK_DMA0_SUSPEND] = 0; // no suspend in new design + time_all[TICK_MEM] = lat->GetLatency(CPD->Page, CMD.operation, BUSY_MEM); + time_all[TICK_DMA1WAIT] = + (MEM.EndTick - MEM.StartTick + 1) - + (lat->GetLatency(CPD->Page, CMD.operation, BUSY_DMA0) + + lat->GetLatency(CPD->Page, CMD.operation, BUSY_MEM) + + lat->GetLatency(CPD->Page, CMD.operation, + BUSY_DMA1)); // --> when DMA1 didn't start immediatly. + time_all[TICK_DMA1] = lat->GetLatency(CPD->Page, CMD.operation, BUSY_DMA1); + time_all[TICK_DMA1_SUSPEND] = 0; // no suspend in new design + time_all[TICK_FULL] = + DMA1.EndTick - CMD.arrived + 1; // D0W+D0+M+D1W+D1 full latency + time_all[TICK_PROC] = time_all[TICK_DMA0] + time_all[TICK_MEM] + + time_all[TICK_DMA1]; // OPTIMUM_TIME + + PPN_requested_rwe.add(oper); + PPN_requested_pagetype[pageType].add(oper); + PPN_requested_ch[chIdx].add(oper); // PPN_requested_ch[ch#] + PPN_requested_die[dieIdx].add(oper); // PPN_requested_die[die#] + + if (confType & CONFLICT_DMA0) + CF_DMA0_dma.add(oper); + if (confType & CONFLICT_MEM) + CF_DMA0_mem.add(oper); + if (!(confType & (CONFLICT_DMA0 | CONFLICT_MEM))) + CF_DMA0_none.add(oper); + + if (confType & CONFLICT_DMA1) + CF_DMA1_dma.add(oper); + if (!(confType & CONFLICT_DMA1)) + CF_DMA1_none.add(oper); + + Ticks_DMA0WAIT.add(oper, time_all[TICK_DMA0WAIT]); + Ticks_DMA0.add(oper, time_all[TICK_DMA0]); + Ticks_MEM.add(oper, time_all[TICK_MEM]); + Ticks_DMA1WAIT.add(oper, time_all[TICK_DMA1WAIT]); + Ticks_DMA1.add(oper, time_all[TICK_DMA1]); + Ticks_Total.add(oper, time_all[TICK_FULL]); + //*********************************************** + // energy = [nW] * [ps] / [10^9] = [pJ] + uint64_t energy_dma0 = lat->GetPower(CMD.operation, BUSY_DMA0) * + time_all[TICK_DMA0] / 1000000000; + uint64_t energy_mem = + lat->GetPower(CMD.operation, BUSY_MEM) * time_all[TICK_MEM] / 1000000000; + uint64_t energy_dma1 = lat->GetPower(CMD.operation, BUSY_DMA1) * + time_all[TICK_DMA1] / 1000000000; + Energy_DMA0.add(oper, energy_dma0); + Energy_MEM.add(oper, energy_mem); + Energy_DMA1.add(oper, energy_dma1); + Energy_Total.add(oper, energy_dma0 + energy_mem + energy_dma1); + // printf("[Energy(fJ) of Oper(%d)] DMA0(%llu) MEM(%llu) DMA1(%llu)\n", oper, + // energy_dma0, energy_mem, energy_dma1); + uint64_t finished_time = CMD.finished; + uint64_t update_point = finished_time / EPOCH_INTERVAL; + std::map::iterator e = + Ticks_Total_snapshot.find(update_point); + if (e != Ticks_Total_snapshot.end()) + e->second->add(oper, time_all[TICK_FULL]); + else { + e = Ticks_Total_snapshot.upper_bound(update_point); + if (e != Ticks_Total_snapshot.end()) { + if (e != Ticks_Total_snapshot.begin()) { + e--; + Ticks_Total_snapshot[update_point] = new ValueOper(e->second); + } + else { + Ticks_Total_snapshot[update_point] = new ValueOper(); + } + } + else { + if (Ticks_Total_snapshot.size() == 0) + Ticks_Total_snapshot[update_point] = new ValueOper(); + else { + e--; + Ticks_Total_snapshot[update_point] = new ValueOper(e->second); + } + } + Ticks_Total_snapshot[update_point]->add(oper, time_all[TICK_FULL]); + } + + e = Ticks_Total_snapshot.upper_bound(update_point); + while (e != Ticks_Total_snapshot.end()) { + e->second->add(oper, time_all[TICK_FULL]); + + e = Ticks_Total_snapshot.upper_bound(e->first); + } + //*********************************************** + Ticks_TotalOpti.add(oper, time_all[TICK_PROC]); + Ticks_Active_ch[chIdx].add(oper, time_all[TICK_DMA0] + time_all[TICK_DMA1]); + Ticks_Active_die[dieIdx].add(oper, + (time_all[TICK_DMA0] + time_all[TICK_MEM] + + time_all[TICK_DMA1WAIT] + time_all[TICK_DMA1])); + if (oper == OPER_ERASE) + Access_Capacity.add( + oper, + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + Access_Capacity.add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + //************************************************ + update_point = finished_time / EPOCH_INTERVAL; + std::map::iterator f = + Access_Capacity_snapshot.find(update_point); + if (f != Access_Capacity_snapshot.end()) { + if (oper == OPER_ERASE) + f->second->add(oper, + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + f->second->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + } + else { + f = Access_Capacity_snapshot.upper_bound(update_point); + if (f != Access_Capacity_snapshot.end()) { + if (f != Access_Capacity_snapshot.begin()) { + f--; + Access_Capacity_snapshot[update_point] = new ValueOper(f->second); + } + else { + Access_Capacity_snapshot[update_point] = new ValueOper(); + } + } + else { + if (Access_Capacity_snapshot.size() == 0) + Access_Capacity_snapshot[update_point] = new ValueOper(); + else { + f--; + Access_Capacity_snapshot[update_point] = new ValueOper(f->second); + } + } + + if (oper == OPER_ERASE) + Access_Capacity_snapshot[update_point]->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + Access_Capacity_snapshot[update_point]->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + } + f = Access_Capacity_snapshot.upper_bound(update_point); + while (f != Access_Capacity_snapshot.end()) { + if (oper == OPER_ERASE) + f->second->add(oper, + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + f->second->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + f = Access_Capacity_snapshot.upper_bound(f->first); + } + //************************************************ +} + +/* +#define fDPRINTF(out_to, fmt, ...) \ + do { \ + char buf[1024]; \ + sprintf(buf, fmt, ##__VA_ARGS__); \ + DPRINTF(out_to, "%s", buf); \ + } while (0); +*/ + +void PALStatistics::PrintFinalStats(uint64_t sim_time_ps) { + // DPRINTF(PAL, "PAL Final Stats Report ]\n"); + // DPRINTF(PAL, "Total execution time (ms), Total SSD active time (ms)\n"); + // DPRINTF(PAL, "%.2f\t\t\t, %.2f\n", sim_time_ps * 1.0 / 1000000000, + // SampledExactBusyTime * 1.0 / 1000000000); + + assert(Access_Capacity_snapshot.size() > 0); + std::map::iterator e = Access_Capacity_snapshot.end(); + e--; + + e->second->printstat("Info of Access Capacity"); + Access_Bandwidth.printstat_bandwidth(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Bandwidth_widle.printstat_bandwidth_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Bandwidth.printstat_oper_bandwidth(e->second, OpBusyTime, + LastOpBusyTime); + + assert(Ticks_Total_snapshot.size() > 0); + std::map::iterator f = Ticks_Total_snapshot.end(); + f--; + + f->second->printstat_latency("Info of Latency"); + Access_Iops.printstat_iops(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Iops_widle.printstat_iops_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Iops.printstat_oper_iops(e->second, OpBusyTime, LastOpBusyTime); + // DPRINTF(PAL, "===================\n"); + PPN_requested_rwe.printstat("Num of PPN IO request"); + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < PAGE_NUM; i++) { + char str[256]; + sprintf(str, "Num of %s page PPN IO request", PAGE_STRINFO[i]); + PPN_requested_pagetype[i].printstat(str); + } + printf("===================\n"); + + for (uint32_t i = 0; + i < gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Num of CH_%u PPN IO request", i); + PPN_requested_ch[i].printstat(str); + } + printf("===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Num of DIE_%u PPN IO request", i); + PPN_requested_die[i].printstat(str); + } + printf("===================\n"); + + CF_DMA0_dma.printstat("Num of conflict DMA0-CH"); + CF_DMA0_mem.printstat("Num of conflict DMA0-MEM"); + CF_DMA0_none.printstat("Num of conflict DMA0-None"); + printf("===================\n"); + + CF_DMA1_dma.printstat("Num of conflict DMA1-CH"); + CF_DMA1_none.printstat("Num of conflict DMA1-None"); + printf("===================\n"); + + Ticks_DMA0WAIT.printstat("Info of DMA0WAIT Tick"); + Ticks_DMA0.printstat("Info of DMA0 Tick"); + Ticks_MEM.printstat("Info of MEM Tick"); + Ticks_DMA1WAIT.printstat("Info of DMA1WAIT Tick"); + Ticks_DMA1.printstat("Info of DMA1 Tick"); + Ticks_Total.printstat("Info of TOTAL(D0W+D0+M+D1W+D1) Tick"); + Ticks_TotalOpti.printstat("Info of OPTIMUM(D0+M+D1) Tick"); + // power + printf("===================\n"); + Energy_DMA0.printstat_energy("Energy consumption of DMA0"); + Energy_MEM.printstat_energy("Energy consumption of MEM"); + Energy_DMA1.printstat_energy("Energy consumption of DAM1"); + Energy_Total.printstat_energy("Total Energy consumption"); + printf("-------------------\n"); + for (uint32_t i = 0; i < totalDie; i++) { + PrintDieIdleTicks(i, sim_time_ps, lat->GetPower(10, 10)); + } + printf("===================\n"); + + for (uint32_t i = 0; + i < gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Info of CH_%u Active Tick", i); + Ticks_Active_ch[i].printstat(str); + } + printf("===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Info of DIE_%u Active Tick", i); + Ticks_Active_die[i].printstat(str); + } + printf("===================\n"); +} + +void PALStatistics::PrintStats(uint64_t sim_time_ps) { + // uint64_t elapsed_time_ps = (sim_time_ps - sim_start_time_ps) + 1; + // if (LastExecutionTime == 0) + // LastExecutionTime = sim_start_time_ps; + // DPRINTF(PAL, "Execution time = %" PRIu64 "\n", sim_time_ps); + // DPRINTF(PAL, "Last Execution time = %" PRIu64 "\n", LastExecutionTime); + // if (sim_start_time_ps >= sim_time_ps) // abnormal case + // { + // elapsed_time_ps = sim_time_ps + 1; + // } + + // DPRINTF(PAL, "[ PAL Stats ]\n"); + +#define SIM_TIME_SEC ((long double)elapsed_time_ps / PSEC) +#define BUSY_TIME_SEC ((long double)ExactBusyTime / PSEC) +#define TRANSFER_TOTAL_MB \ + ((long double)(Access_Capacity.vals[OPER_READ].sum + \ + Access_Capacity.vals[OPER_WRITE].sum) / \ + MBYTE) + + // fDPRINTF(PAL, "Sim.Time : %Lf Sec. , %" PRIu64 " ps\n", SIM_TIME_SEC, + // elapsed_time_ps); + // fDPRINTF(PAL, "Transferred : %Lf MB\n", TRANSFER_TOTAL_MB); + // fDPRINTF(PAL, "Performance: %Lf MB/Sec\n", + // (long double)TRANSFER_TOTAL_MB / SIM_TIME_SEC); + // fDPRINTF(PAL, "Busy Sim.Time: %Lf Sec. , %" PRIu64 " ps\n", BUSY_TIME_SEC, + // ExactBusyTime); + // fDPRINTF(PAL, "Busy Performance: %Lf MB/Sec\n", + // (long double)TRANSFER_TOTAL_MB / BUSY_TIME_SEC); + + std::map::iterator e = + Access_Capacity_snapshot.find(sim_time_ps / EPOCH_INTERVAL - 1); + if (sim_time_ps > 0 && e != Access_Capacity_snapshot.end()) { + PPN_requested_rwe.printstat("Num of PPN IO request"); + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < PAGE_NUM; i++) { + char str[256]; + sprintf(str, "Num of %s page PPN IO request", PAGE_STRINFO[i]); + PPN_requested_pagetype[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Num of CH_%u PPN IO request", i); + PPN_requested_ch[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Num of DIE_%u PPN IO request", i); + PPN_requested_die[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + CF_DMA0_dma.printstat("Num of conflict DMA0-CH"); + CF_DMA0_mem.printstat("Num of conflict DMA0-MEM"); + CF_DMA0_none.printstat("Num of conflict DMA0-None"); + // DPRINTF(PAL, "===================\n"); + + CF_DMA1_dma.printstat("Num of conflict DMA1-CH"); + CF_DMA1_none.printstat("Num of conflict DMA1-None"); + // DPRINTF(PAL, "===================\n"); + + Ticks_DMA0WAIT.printstat("Info of DMA0WAIT Tick"); + Ticks_DMA0.printstat("Info of DMA0 Tick"); + Ticks_MEM.printstat("Info of MEM Tick"); + Ticks_DMA1WAIT.printstat("Info of DMA1WAIT Tick"); + Ticks_DMA1.printstat("Info of DMA1 Tick"); + Ticks_Total.printstat("Info of TOTAL(D0W+D0+M+D1W+D1) Tick"); + Ticks_TotalOpti.printstat("Info of OPTIMUM(D0+M+D1) Tick"); + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Info of CH_%u Active Tick", i); + Ticks_Active_ch[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Info of DIE_%u Active Tick", i); + Ticks_Active_die[i].printstat(str); + } + // DPRINTF(PAL, "===================\n") + + e->second->printstat("Info of Access Capacity"); + // DPRINTF(PAL, "Total execution time (ms)\n"); + // DPRINTF(PAL, "%.2f\n", SampledExactBusyTime * 1.0 / 1000000000); + Access_Bandwidth.printstat_bandwidth(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Bandwidth_widle.printstat_bandwidth_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Bandwidth.printstat_oper_bandwidth(e->second, OpBusyTime, + LastOpBusyTime); + std::map::iterator f = + Ticks_Total_snapshot.find(sim_time_ps / EPOCH_INTERVAL - 1); + f->second->printstat_latency("Info of Latency"); + Access_Iops.printstat_iops(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Iops_widle.printstat_iops_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Iops.printstat_oper_iops(e->second, OpBusyTime, LastOpBusyTime); + LastExactBusyTime = SampledExactBusyTime; + LastExecutionTime = sim_time_ps; + LastOpBusyTime[0] = OpBusyTime[0]; + LastOpBusyTime[1] = OpBusyTime[1]; + LastOpBusyTime[2] = OpBusyTime[2]; + std::map::iterator g = + Access_Capacity_snapshot.upper_bound(sim_time_ps / EPOCH_INTERVAL - 1); + if (g != Access_Capacity_snapshot.end()) { + for (int i = 0; i < OPER_ALL; i++) { + g->second->vals[i].sampled_sum = e->second->vals[i].sum; + g->second->vals[i].sampled_cnt = e->second->vals[i].cnt; + e->second->vals[i].sampled_sum = e->second->vals[i].sum; + e->second->vals[i].sampled_cnt = e->second->vals[i].cnt; + } + } + else { + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL] = new ValueOper( + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL - 1]); + for (int i = 0; i < OPER_ALL; i++) { + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_sum = e->second->vals[i].sum; + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_cnt = e->second->vals[i].cnt; + } + } + std::map::iterator h = + Ticks_Total_snapshot.upper_bound(sim_time_ps / EPOCH_INTERVAL - 1); + if (h != Ticks_Total_snapshot.end()) { + for (int i = 0; i < OPER_ALL; i++) { + h->second->vals[i].sampled_sum = f->second->vals[i].sum; + h->second->vals[i].sampled_cnt = f->second->vals[i].cnt; + f->second->vals[i].sampled_sum = f->second->vals[i].sum; + f->second->vals[i].sampled_cnt = f->second->vals[i].cnt; + } + } + else { + Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL] = + new ValueOper(Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL - 1]); + for (int i = 0; i < OPER_ALL; i++) { + Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_sum = f->second->vals[i].sum; + Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_cnt = f->second->vals[i].cnt; + } + } + Access_Capacity_snapshot.erase(sim_time_ps / EPOCH_INTERVAL - 1); + Ticks_Total_snapshot.erase(sim_time_ps / EPOCH_INTERVAL - 1); + } + + for (int i = 0; i < OPER_ALL; i++) { + Access_Capacity.vals[i].backup(); + } +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PALStatistics.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PALStatistics.h new file mode 100644 index 0000000000..77e504785b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/old/PALStatistics.h @@ -0,0 +1,329 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#ifndef __PALStatistics_h__ +#define __PALStatistics_h__ + +#include "util/old/SimpleSSD_types.h" + +#include "Latency.h" +#include "PAL2_TimeSlot.h" + +#include "sim/config_reader.hh" +#include "sim/simulator.hh" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +#define OPER_ALL (OPER_NUM + 1) +#define PAGE_ALL (PAGE_NUM + 1) + +// From ftl_command.hh +typedef struct _Command { + Tick arrived; + Tick finished; + Addr ppn; + PAL_OPERATION operation; + bool mergeSnapshot; + uint64_t size; + + _Command() + : arrived(0), + finished(0), + ppn(0), + operation(OPER_NUM), + mergeSnapshot(false), + size(0) {} + _Command(Tick t, Addr a, PAL_OPERATION op, uint64_t s) + : arrived(t), + finished(0), + ppn(a), + operation(op), + mergeSnapshot(false), + size(s) {} + + Tick getLatency() { + if (finished > 0) { + return finished - arrived; + } + else { + return 0; + } + } +} Command; + +// From ftl_defs.hh +#define EPOCH_INTERVAL 100000000000 + +class PALStatistics { + public: + enum { + /* + BUSY_DMA0WAIT = 0, + BUSY_DMA0 = 1, + BUSY_MEM = 2, + BUSY_DMA1WAIT = 3, + BUSY_DMA1 = 4, + BUSY_END = 5 + */ + TICK_DMA0_CHANNEL_CONFLICT = TICK_NUM, + TICK_DMA0_PLANE_CONFLICT, + TICK_DMA1_CONFLICT, + TICK_DMA0_SUSPEND, + TICK_DMA1_SUSPEND, + TICK_PROC, + TICK_FULL, + TICK_STAT_NUM + }; + + SimpleSSD::ConfigReader *gconf; + Latency *lat; + uint64_t totalDie; + +#if 0 // ch-die io count (legacy) + class mini_cnt_page + { + public: + mini_cnt_page(); + uint64_t c[OPER_NUM][PAGE_NUM]; + }; + mini_cnt_page* ch_io_cnt; + mini_cnt_page* die_io_cnt; +#endif + +#if GATHER_RESOURCE_CONFLICT && 0 // conflict gather (legacy) + class mini_cnt_conflict { + public: + mini_cnt_conflict(); + uint64_t c[OPER_NUM][CONFLICT_NUM]; + }; + mini_cnt_conflict *ch_conflict_cnt; + mini_cnt_conflict *ch_conflict_length; + mini_cnt_conflict *die_conflict_cnt; + mini_cnt_conflict *die_conflict_length; +#endif + +#if 0 // latency (legacy method) + uint64_t latency_cnt[OPER_NUM][TICK_STAT_NUM]; // RWE count for: (page_size * cnt)/SIM_TIME + uint64_t latency_sum[OPER_NUM][TICK_STAT_NUM]; +#endif + +#if 0 // util time (legacy method) + uint64_t* channel_util_time_sum; + uint64_t* die_util_time_sum_mem; //mem only-mem occupy + uint64_t* die_util_time_sum_optimum; //mem oper occupy optimum (DMA0+MEM+DMA1) + uint64_t* die_util_time_sum_all; //mem oper actual occupy +#endif + +#if 0 // stall + /* StallInfo: + Actually, only use 5 entries --- 1a) TICK_DMA0_CHANNEL_CONFLICT, 1b) TICK_DMA0_PLANE_CONFLICT, + 2) TICK_DMA1WAIT, 3) TICK_DMA0_SUSPEND, 4) TICK_DMA1_SUSPEND */ + uint64_t stall_sum[OPER_NUM][TICK_STAT_NUM]; + uint64_t stall_cnt[OPER_NUM][TICK_STAT_NUM]; + uint8_t LastDMA0Stall; + uint64_t LastDMA0AttemptTick; + + void CountStall(uint8_t oper, uint8_t stall_kind); + void AddStall(uint8_t oper, uint8_t stall_kind, uint64_t lat); +#endif + + PALStatistics(SimpleSSD::ConfigReader *, Latency *); + + ~PALStatistics(); + + /* + void AddLatency(uint32_t lat, uint8_t oper, uint8_t busyfor); + */ + + void AddLatency(Task *task); + + /* + void AddOccupy(uint32_t ch, uint64_t ch_time, uint64_t pl, uint64_t pl_time, + uint64_t pl2_time); + */ + + uint64_t sim_start_time_ps; + uint64_t LastTick; + void UpdateLastTick(uint64_t tick); + uint64_t GetLastTick(); +#if GATHER_RESOURCE_CONFLICT + void AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, TimeSlot &DMA0, + TimeSlot &MEM, TimeSlot &DMA1, uint8_t confType); +#else + void AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, TimeSlot &DMA0, + TimeSlot &MEM, TimeSlot &DMA1); +#endif + void MergeSnapshot(); + uint64_t ExactBusyTime, SampledExactBusyTime; + uint64_t OpBusyTime[3], LastOpBusyTime[3]; // 0: Read, 1: Write, 2: Erase; + uint64_t LastExactBusyTime; + uint64_t LastExecutionTime; + + struct Breakdown { + double dma0wait; + double dma0; + double mem; + double dma1wait; + double dma1; + + Breakdown() : dma0wait(0.), dma0(0.), mem(0.), dma1wait(0.), dma1(0.) {} + }; + + struct OperStats { + double read; + double write; + double erase; + double total; + + OperStats() : read(0.), write(0.), erase(0.), total(0.) {} + }; + + struct ActiveTime { + double min; + double average; + double max; + + ActiveTime() : min(0.), average(0.), max(0.) {} + }; + + void PrintStats(uint64_t sim_time_ps); + void ResetStats(); + void PrintFinalStats(uint64_t sim_time_ps); + + void getTickStat(OperStats &); // Return busy ticks in ps + void getEnergyStat(OperStats &); // Return energy in uJ + void getReadBreakdown(Breakdown &); // Return READ breakdown in ps + void getWriteBreakdown(Breakdown &); // Return WRITE breakdown in ps + void getEraseBreakdown(Breakdown &); // Return ERASE breakdown in ps + void getChannelActiveTime(uint32_t, ActiveTime &); + void getDieActiveTime(uint32_t, ActiveTime &); + void getChannelActiveTimeAll(ActiveTime &); + void getDieActiveTimeAll(ActiveTime &); + + class Counter { + public: + Counter(); + void init(); + void add(); + uint64_t cnt; + }; + + class CounterOper { + public: + CounterOper(); + Counter cnts[OPER_ALL]; + void init(); + void add(uint32_t oper); + void printstat(const char *namestr); + }; + + CounterOper PPN_requested_rwe; + CounterOper PPN_requested_pagetype[PAGE_ALL]; + CounterOper *PPN_requested_ch; // channels + CounterOper *PPN_requested_die; // dies + CounterOper CF_DMA0_dma; + CounterOper CF_DMA0_mem; + CounterOper CF_DMA0_none; + CounterOper CF_DMA1_dma; + CounterOper CF_DMA1_none; + + class Value { + public: + Value(); + void init(); + void add(double val); + void backup(); + void update(); + double avg(); + double legacy_avg(); + double sum, minval, maxval, cnt, sampled_sum, sampled_cnt, legacy_sum, + legacy_cnt, legacy_minval, legacy_maxval; + }; + + class ValueOper { + public: + ValueOper(); + ValueOper(ValueOper *_ValueOper); + Value vals[OPER_ALL]; + void init(); + void update(); + void add(uint32_t oper, double val); + void exclusive_add(uint32_t oper, double val); + void printstat(const char *namestr); + void printstat_bandwidth(class ValueOper *, uint64_t, + uint64_t); // bandwidth excluding idle time + void printstat_bandwidth_widle(class ValueOper *, uint64_t, + uint64_t); // bandwidth including idle time + void printstat_oper_bandwidth( + class ValueOper *, uint64_t *, + uint64_t *); // read/write/erase-only bandwidth + void printstat_latency(const char *namestr); + void printstat_iops(class ValueOper *, uint64_t, uint64_t); + void printstat_iops_widle(class ValueOper *, uint64_t, uint64_t); + void printstat_oper_iops(class ValueOper *, uint64_t *, uint64_t *); + + void printstat_energy(const char *namestr); + }; + + ValueOper Ticks_DMA0WAIT; + ValueOper Ticks_DMA0; + ValueOper Ticks_MEM; + ValueOper Ticks_DMA1WAIT; + ValueOper Ticks_DMA1; + ValueOper Ticks_Total; // Total = D0W+D0+M+D1W+D1 + // power + ValueOper Energy_DMA0; + ValueOper Energy_MEM; + ValueOper Energy_DMA1; + ValueOper Energy_Total; + + std::map Ticks_Total_snapshot; + ValueOper Ticks_TotalOpti; // TotalOpti = D0+M+D1 --- exclude WAIT + ValueOper *Ticks_Active_ch; // channels + ValueOper *Ticks_Active_die; // dies + ValueOper Access_Capacity; + std::map Access_Capacity_snapshot; + ValueOper Access_Bandwidth; + ValueOper Access_Bandwidth_widle; + ValueOper Access_Oper_Bandwidth; + ValueOper Access_Iops; + ValueOper Access_Iops_widle; + ValueOper Access_Oper_Iops; + uint64_t SampledTick; + bool skip; + + void PrintDieIdleTicks(uint32_t die_num, uint64_t sim_time_ps, + uint64_t idle_power_nw); + + private: + void ClearStats(); + void InitStats(); +}; + +#endif //__PALStatistics_h__ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal.cc new file mode 100644 index 0000000000..c14045be97 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal.cc @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "pal/pal.hh" + +#include "pal/pal_old.hh" + +namespace SimpleSSD { + +namespace PAL { + +PAL::PAL(ConfigReader &c) : conf(c) { + static const char name[4][16] = {"Channel", "Way", "Die", "Plane"}; + uint32_t value[4]; + uint8_t superblock = conf.getSuperblockConfig(); + + param.channel = conf.readUint(CONFIG_PAL, PAL_CHANNEL); + param.package = conf.readUint(CONFIG_PAL, PAL_PACKAGE); + + param.die = conf.readUint(CONFIG_PAL, NAND_DIE); + param.plane = conf.readUint(CONFIG_PAL, NAND_PLANE); + param.block = conf.readUint(CONFIG_PAL, NAND_BLOCK); + param.page = conf.readUint(CONFIG_PAL, NAND_PAGE); + param.pageSize = conf.readUint(CONFIG_PAL, NAND_PAGE_SIZE); + param.superBlock = param.block; + param.superPageSize = param.pageSize; + + // Super block includes channel + if (superblock & INDEX_CHANNEL) { + param.superPageSize *= param.channel; + value[0] = param.channel; + } + else { + param.superBlock *= param.channel; + } + + // Super block includes way (package) + if (superblock & INDEX_PACKAGE) { + param.superPageSize *= param.package; + value[1] = param.package; + } + else { + param.superBlock *= param.package; + } + + // Super block includes die + if (superblock & INDEX_DIE) { + param.superPageSize *= param.die; + value[2] = param.die; + } + else { + param.superBlock *= param.die; + } + + // Super block includes plane + if (conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP) || + (superblock & INDEX_PLANE)) { + param.superPageSize *= param.plane; + value[3] = param.plane; + } + else { + param.superBlock *= param.plane; + } + + // Partial I/O tweak + param.pageInSuperPage = param.superPageSize / param.pageSize; + + // TODO: If PAL revised, this code may not needed + if (conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP)) { + param.pageInSuperPage /= param.plane; + } + + // Print super block information + debugprint(LOG_PAL, + "Channel | Way | Die | Plane | Block | Page "); + debugprint(LOG_PAL, "%7u | %7u | %7u | %7u | %7u | %7u", param.channel, + param.package, param.die, param.plane, param.block, param.page); + debugprint(LOG_PAL, "Multi-plane mode %s", + conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP) + ? "enabled" + : "disabled"); + debugprint(LOG_PAL, "Superblock multiplier"); + + for (int i = 0; i < 4; i++) { + if (superblock & (1 << i)) { + debugprint(LOG_PAL, "x%u (%s)", value[i], name[i]); + } + } + + debugprint(LOG_PAL, "Page size %u -> %u", param.pageSize, + param.superPageSize); + debugprint( + LOG_PAL, "Total block count %u -> %u", + param.channel * param.package * param.die * param.plane * param.block, + param.superBlock); + + pPAL = new PALOLD(param, c); +} + +PAL::~PAL() { + delete pPAL; +} + +void PAL::read(Request &req, uint64_t &tick) { + pPAL->read(req, tick); +} + +void PAL::write(Request &req, uint64_t &tick) { + pPAL->write(req, tick); +} + +void PAL::erase(Request &req, uint64_t &tick) { + pPAL->erase(req, tick); +} + +void PAL::copyback(uint32_t, uint32_t, uint32_t, uint64_t &) { + panic("Copyback not implemented"); +} + +Parameter *PAL::getInfo() { + return ¶m; +} + +void PAL::getStatList(std::vector &list, std::string prefix) { + pPAL->getStatList(list, prefix + "pal."); +} + +void PAL::getStatValues(std::vector &values) { + pPAL->getStatValues(values); +} + +void PAL::resetStatValues() { + pPAL->resetStatValues(); +} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal.hh new file mode 100644 index 0000000000..cee31e4622 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal.hh @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_PAL__ +#define __PAL_PAL__ + +#include "util/def.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace PAL { + +class AbstractPAL; + +typedef struct { + uint32_t channel; //!< Total # channels + uint32_t package; //!< # packages / channel + uint32_t die; //!< # dies / package + uint32_t plane; //!< # planes / die + uint32_t block; //!< # blocks / plane + uint32_t page; //!< # pages / block + uint32_t superBlock; //!< Total super blocks + uint32_t pageSize; //!< Size of page in bytes + uint32_t superPageSize; //!< Size of super page in bytes + uint32_t pageInSuperPage; //!< # pages in one superpage +} Parameter; + +class PAL : public StatObject { + private: + Parameter param; + AbstractPAL *pPAL; + + ConfigReader &conf; + + public: + PAL(ConfigReader &); + ~PAL(); + + void read(Request &, uint64_t &); + void write(Request &, uint64_t &); + void erase(Request &, uint64_t &); + void copyback(uint32_t, uint32_t, uint32_t, uint64_t &); + + Parameter *getInfo(); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal_old.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal_old.cc new file mode 100644 index 0000000000..f275008b2c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal_old.cc @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "pal/pal_old.hh" + +#include + +#include "pal/old/Latency.h" +#include "pal/old/LatencyMLC.h" +#include "pal/old/LatencySLC.h" +#include "pal/old/LatencyTLC.h" +#include "pal/old/PAL2.h" +#include "pal/old/PALStatistics.h" +#include "util/algorithm.hh" + +#define FLUSH_PERIOD 100000000000ull // 0.1sec +#define FLUSH_RANGE 10000000000ull // 0.01sec + +namespace SimpleSSD { + +namespace PAL { + +PALOLD::PALOLD(Parameter &p, ConfigReader &c) + : AbstractPAL(p, c), lastResetTick(0) { + Config::NANDTiming *pTiming = c.getNANDTiming(); + Config::NANDPower *pPower = c.getNANDPower(); + + memset(&stat, 0, sizeof(stat)); + + switch (conf.readInt(CONFIG_PAL, NAND_FLASH_TYPE)) { + case NAND_SLC: + lat = new LatencySLC(*pTiming, *pPower); + break; + case NAND_MLC: + lat = new LatencyMLC(*pTiming, *pPower); + break; + case NAND_TLC: + lat = new LatencyTLC(*pTiming, *pPower); + break; + } + + debugprint(LOG_PAL_OLD, "NAND timing:"); + debugprint(LOG_PAL_OLD, "Operation | LSB | CSB | MSB | " + " DMA 0 | DMA "); + debugprint(LOG_PAL_OLD, + " READ | %10" PRIu64 " | %10" PRIu64 " | %10" PRIu64 + " | %10" PRIu64 " | %10" PRIu64, + pTiming->lsb.read, pTiming->csb.read, pTiming->msb.read, + pTiming->dma0.read, pTiming->dma1.read); + debugprint(LOG_PAL_OLD, + " WRITE | %10" PRIu64 " | %10" PRIu64 " | %10" PRIu64 + " | %10" PRIu64 " | %10" PRIu64, + pTiming->lsb.write, pTiming->csb.write, pTiming->msb.write, + pTiming->dma0.write, pTiming->dma1.write); + debugprint(LOG_PAL_OLD, + " ERASE | %10" PRIu64 " | %10" PRIu64 + " | %10" PRIu64, + pTiming->erase, pTiming->dma0.erase, pTiming->dma1.erase); + + stats = new PALStatistics(&conf, lat); + pal = new PAL2(stats, ¶m, &conf, lat); + + // We will periodically flush timeslot for saving memory + flushFunction = [this](uint64_t tick) { + pal->FlushFreeSlots(tick - FLUSH_RANGE); + pal->FlushTimeSlots(tick - FLUSH_RANGE); + + schedule(flushEvent, tick + FLUSH_PERIOD); + }; + flushEvent = allocate(flushFunction); + schedule(flushEvent, getTick() + FLUSH_PERIOD); +} + +PALOLD::~PALOLD() { + delete pal; + delete stats; + delete lat; +} + +void PALOLD::read(Request &req, uint64_t &tick) { + uint64_t finishedAt = tick; + ::Command cmd(tick, 0, OPER_READ, param.superPageSize); + std::vector<::CPDPBP> list; + + printPPN(req, "READ"); + + convertCPDPBP(req, list); + + for (auto &iter : list) { + printCPDPBP(iter, "READ"); + + pal->submit(cmd, iter); + stat.readCount++; + + finishedAt = MAX(finishedAt, cmd.finished); + } + + tick = finishedAt; +} + +void PALOLD::write(Request &req, uint64_t &tick) { + uint64_t finishedAt = tick; + ::Command cmd(tick, 0, OPER_WRITE, param.superPageSize); + std::vector<::CPDPBP> list; + + printPPN(req, "WRITE"); + + convertCPDPBP(req, list); + + for (auto &iter : list) { + printCPDPBP(iter, "WRITE"); + + pal->submit(cmd, iter); + stat.writeCount++; + + finishedAt = MAX(finishedAt, cmd.finished); + } + + tick = finishedAt; +} + +void PALOLD::erase(Request &req, uint64_t &tick) { + uint64_t finishedAt = tick; + ::Command cmd(tick, 0, OPER_ERASE, param.superPageSize * param.page); + std::vector<::CPDPBP> list; + + printPPN(req, "ERASE"); + + convertCPDPBP(req, list); + + for (auto &iter : list) { + printCPDPBP(iter, "ERASE"); + + pal->submit(cmd, iter); + stat.eraseCount++; + + finishedAt = MAX(finishedAt, cmd.finished); + } + + tick = finishedAt; +} + +void PALOLD::convertCPDPBP(Request &req, std::vector<::CPDPBP> &list) { + ::CPDPBP addr; + static uint32_t pageAllocation = conf.getPageAllocationConfig(); + static uint8_t superblock = conf.getSuperblockConfig(); + static bool useMultiplaneOP = + conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP); + static uint32_t pageInSuperPage = param.pageInSuperPage; + static bool bRandomTweak = + conf.readBoolean(CONFIG_FTL, FTL::FTL_USE_RANDOM_IO_TWEAK); + uint32_t value[4]; + uint32_t *ptr[4]; + uint64_t tmp = req.blockIndex; + int count = 0; + + if (bRandomTweak && req.ioFlag.size() != pageInSuperPage) { + panic("Invalid size of I/O flag"); + } + + if (!bRandomTweak && req.ioFlag.size() != pageInSuperPage) { + req.ioFlag = Bitset(pageInSuperPage); + req.ioFlag.set(); + } + + list.clear(); + + addr.Plane = 0; + + for (int i = 0; i < 4; i++) { + uint8_t idx = (pageAllocation >> (i * 8)) & 0xFF; + + switch (idx) { + case INDEX_CHANNEL: + if (superblock & INDEX_CHANNEL) { + value[count] = param.channel; + ptr[count++] = &addr.Channel; + } + else { + addr.Channel = tmp % param.channel; + tmp /= param.channel; + } + + break; + case INDEX_PACKAGE: + if (superblock & INDEX_PACKAGE) { + value[count] = param.package; + ptr[count++] = &addr.Package; + } + else { + addr.Package = tmp % param.package; + tmp /= param.package; + } + + break; + case INDEX_DIE: + if (superblock & INDEX_DIE) { + value[count] = param.die; + ptr[count++] = &addr.Die; + } + else { + addr.Die = tmp % param.die; + tmp /= param.die; + } + + break; + case INDEX_PLANE: + if (!useMultiplaneOP) { + if (superblock & INDEX_PLANE) { + value[count] = param.plane; + ptr[count++] = &addr.Plane; + } + else { + addr.Plane = tmp % param.plane; + tmp /= param.plane; + } + } + + break; + default: + break; + } + } + + addr.Block = tmp; + addr.Page = req.pageIndex; + + // Index of ioFlag + tmp = 0; + + if (count == 4) { + list.reserve(value[0] * value[1] * value[2] * value[3]); + + for (uint32_t i = 0; i < value[3]; i++) { + for (uint32_t j = 0; j < value[2]; j++) { + for (uint32_t k = 0; k < value[1]; k++) { + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + *ptr[1] = k; + *ptr[2] = j; + *ptr[3] = i; + + list.push_back(addr); + } + } + } + } + } + } + else if (count == 3) { + list.reserve(value[0] * value[1] * value[2]); + + for (uint32_t j = 0; j < value[2]; j++) { + for (uint32_t k = 0; k < value[1]; k++) { + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + *ptr[1] = k; + *ptr[2] = j; + + list.push_back(addr); + } + } + } + } + } + else if (count == 2) { + list.reserve(value[0] * value[1]); + + for (uint32_t k = 0; k < value[1]; k++) { + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + *ptr[1] = k; + + list.push_back(addr); + } + } + } + } + else if (count == 1) { + list.reserve(value[0]); + + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + + list.push_back(addr); + } + } + } + else { + if (req.ioFlag.test(tmp++)) { + list.push_back(addr); + } + } + + if (tmp != pageInSuperPage) { + panic("I/O flag size != # pages in super page"); + } +} + +void PALOLD::printCPDPBP(::CPDPBP &addr, const char *prefix) { + debugprint(LOG_PAL_OLD, + "%-5s | C %5u | W %5u | D %5u | P %5u | B %5u | P %5u", prefix, + addr.Channel, addr.Package, addr.Die, addr.Plane, addr.Block, + addr.Page); +} + +void PALOLD::printPPN(Request &req, const char *prefix) { + debugprint(LOG_PAL_OLD, "%-5s | Block %u | Page %u", prefix, req.blockIndex, + req.pageIndex); +} + +void PALOLD::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "energy.read"; + temp.desc = "Consumed energy by NAND read operation (uJ)"; + list.push_back(temp); + + temp.name = prefix + "energy.program"; + temp.desc = "Consumed energy by NAND program operation (uJ)"; + list.push_back(temp); + + temp.name = prefix + "energy.erase"; + temp.desc = "Consumed energy by NAND erase operation (uJ)"; + list.push_back(temp); + + temp.name = prefix + "energy.total"; + temp.desc = "Total consumed energy by NAND (uJ)"; + list.push_back(temp); + + temp.name = prefix + "power"; + temp.desc = "Average power consumed by NAND (uW)"; + list.push_back(temp); + + temp.name = prefix + "read.count"; + temp.desc = "Total read operation count"; + list.push_back(temp); + + temp.name = prefix + "program.count"; + temp.desc = "Total program operation count"; + list.push_back(temp); + + temp.name = prefix + "erase.count"; + temp.desc = "Total erase operation count"; + list.push_back(temp); + + temp.name = prefix + "read.bytes"; + temp.desc = "Total read operation bytes"; + list.push_back(temp); + + temp.name = prefix + "program.bytes"; + temp.desc = "Total program operation bytes"; + list.push_back(temp); + + temp.name = prefix + "erase.bytes"; + temp.desc = "Total erase operation bytes"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma0.wait"; + temp.desc = "Average dma0 wait time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma0"; + temp.desc = "Average dma0 time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.mem"; + temp.desc = "Average memory operation time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma1.wait"; + temp.desc = "Average dma1 wait time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma1"; + temp.desc = "Average dma1 time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.total"; + temp.desc = "Average time of read"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma0.wait"; + temp.desc = "Average dma0 wait time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma0"; + temp.desc = "Average dma0 time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.mem"; + temp.desc = "Average memory operation time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma1.wait"; + temp.desc = "Average dma1 wait time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma1"; + temp.desc = "Average dma1 time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.total"; + temp.desc = "Average time of program"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma0.wait"; + temp.desc = "Average dma0 wait time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma0"; + temp.desc = "Average dma0 time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.mem"; + temp.desc = "Average memory operation time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma1.wait"; + temp.desc = "Average dma1 wait time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma1"; + temp.desc = "Average dma1 time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.total"; + temp.desc = "Average time of erase"; + list.push_back(temp); + + temp.name = prefix + "channel.time.active"; + temp.desc = "Average active time of all channels"; + list.push_back(temp); + + temp.name = prefix + "die.time.active"; + temp.desc = "Average active time of all dies"; + list.push_back(temp); +} + +void PALOLD::getStatValues(std::vector &values) { + PALStatistics::OperStats energy; + PALStatistics::OperStats ticks; + PALStatistics::ActiveTime active; + PALStatistics::Breakdown breakdown; + double elapsedTick = (double)(getTick() - lastResetTick); + + stats->getEnergyStat(energy); + stats->getTickStat(ticks); + + values.push_back(energy.read); + values.push_back(energy.write); + values.push_back(energy.erase); + values.push_back(energy.total); + + // uW = uJ / ps * 1e+12 + energy.total /= elapsedTick / 1e+12; + values.push_back(energy.total); + + values.push_back(stat.readCount); + values.push_back(stat.writeCount); + values.push_back(stat.eraseCount); + + values.push_back(stat.readCount * param.pageSize); + values.push_back(stat.writeCount * param.pageSize); + values.push_back(stat.eraseCount * param.pageSize * param.page); + + stats->getReadBreakdown(breakdown); + values.push_back(breakdown.dma0wait); + values.push_back(breakdown.dma0); + values.push_back(breakdown.mem); + values.push_back(breakdown.dma1wait); + values.push_back(breakdown.dma1); + values.push_back(ticks.read); + + stats->getWriteBreakdown(breakdown); + values.push_back(breakdown.dma0wait); + values.push_back(breakdown.dma0); + values.push_back(breakdown.mem); + values.push_back(breakdown.dma1wait); + values.push_back(breakdown.dma1); + values.push_back(ticks.write); + + stats->getEraseBreakdown(breakdown); + values.push_back(breakdown.dma0wait); + values.push_back(breakdown.dma0); + values.push_back(breakdown.mem); + values.push_back(breakdown.dma1wait); + values.push_back(breakdown.dma1); + values.push_back(ticks.erase); + + stats->getChannelActiveTimeAll(active); + values.push_back(active.average); + + stats->getDieActiveTimeAll(active); + values.push_back(active.average); +} + +void PALOLD::resetStatValues() { + stats->ResetStats(); + lastResetTick = getTick(); + + memset(&stat, 0, sizeof(stat)); +} + +void PALOLD::read(::CPDPBP &addr, uint64_t &tick) { + ::Command cmd(tick, 0, OPER_READ, param.superPageSize); + + printCPDPBP(addr, "READ"); + pal->submit(cmd, addr); + stat.readCount++; + + tick = cmd.finished; +} + +void PALOLD::write(::CPDPBP &addr, uint64_t &tick) { + ::Command cmd(tick, 0, OPER_WRITE, param.superPageSize); + + printCPDPBP(addr, "WRITE"); + pal->submit(cmd, addr); + stat.writeCount++; + + tick = cmd.finished; +} + +void PALOLD::erase(::CPDPBP &addr, uint64_t &tick) { + ::Command cmd(tick, 0, OPER_ERASE, param.superPageSize * param.page); + + printCPDPBP(addr, "ERASE"); + pal->submit(cmd, addr); + stat.eraseCount++; + + tick = cmd.finished; +} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal_old.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal_old.hh new file mode 100644 index 0000000000..29f4a46520 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/pal/pal_old.hh @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_PAL_OLD__ +#define __PAL_PAL_OLD__ + +#include +#include + +#include "pal/abstract_pal.hh" +#include "util/old/SimpleSSD_types.h" + +class PAL2; +class PALStatistics; +class Latency; + +namespace SimpleSSD { + +namespace PAL { + +class PALOLD : public AbstractPAL { + private: + ::PAL2 *pal; + ::PALStatistics *stats; + ::Latency *lat; + + Event flushEvent; + EventFunction flushFunction; + + uint8_t lastResetTick; + + struct { + uint64_t readCount; + uint64_t writeCount; + uint64_t eraseCount; + } stat; + + void convertCPDPBP(Request &, std::vector<::CPDPBP> &); + void printCPDPBP(::CPDPBP &, const char *); + void printPPN(Request &, const char *); + + public: + PALOLD(Parameter &, ConfigReader &); + ~PALOLD(); + + void read(Request &, uint64_t &) override; + void write(Request &, uint64_t &) override; + void erase(Request &, uint64_t &) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; + + // Direct interface for OCSSD + void read(::CPDPBP &, uint64_t &); + void write(::CPDPBP &, uint64_t &); + void erase(::CPDPBP &, uint64_t &); +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/base_config.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/base_config.hh new file mode 100644 index 0000000000..0ca91f9625 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/base_config.hh @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_BASE_CONFIG__ +#define __SIM_BASE_CONFIG__ + +#include +#include +#include + +namespace SimpleSSD { + +#define MATCH_SECTION(str) (strcmp(section, str) == 0) +#define MATCH_NAME(str) (strcmp(name, str) == 0) +#define MATCH_VALUE(str) (strcmp(value, str) == 0) + +class BaseConfig { + protected: + bool convertBool(const char *); + + public: + BaseConfig() {} + virtual ~BaseConfig() {} + + virtual bool setConfig(const char *, const char *) = 0; + virtual void update() {} + + virtual int64_t readInt(uint32_t) { return 0; } + virtual uint64_t readUint(uint32_t) { return 0; } + virtual float readFloat(uint32_t) { return 0.f; } + virtual std::string readString(uint32_t) { return std::string(); } + virtual bool readBoolean(uint32_t) { return false; } +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/config_reader.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/config_reader.cc new file mode 100644 index 0000000000..8117b77c06 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/config_reader.cc @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/config_reader.hh" + +#include "sim/base_config.hh" +#include "sim/trace.hh" + +#ifdef _MSC_VER +#define strcasecmp _stricmp +#else +#include +#endif + +namespace SimpleSSD { + +const char SECTION_CPU[] = "cpu"; +const char SECTION_DRAM[] = "dram"; +const char SECTION_FTL[] = "ftl"; +const char SECTION_NVME[] = "nvme"; +const char SECTION_ICL[] = "icl"; +const char SECTION_PAL[] = "pal"; +const char SECTION_SATA[] = "sata"; +const char SECTION_UFS[] = "ufs"; + +bool BaseConfig::convertBool(const char *value) { + bool ret = false; + + if (strcasecmp(value, "true") == 0 || strtoul(value, nullptr, 10)) { + ret = true; + } + + return ret; +} + +bool ConfigReader::init(std::string file) { + if (ini_parse(file.c_str(), parserHandler, this) < 0) { + return false; + } + + // Update all + cpuConfig.update(); + dramConfig.update(); + ftlConfig.update(); + nvmeConfig.update(); + iclConfig.update(); + palConfig.update(); + sataConfig.update(); + ufsConfig.update(); + + return true; +} + +int64_t ConfigReader::readInt(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readInt(idx); + case CONFIG_DRAM: + return dramConfig.readInt(idx); + case CONFIG_FTL: + return ftlConfig.readInt(idx); + case CONFIG_NVME: + return nvmeConfig.readInt(idx); + case CONFIG_SATA: + return sataConfig.readInt(idx); + case CONFIG_UFS: + return ufsConfig.readInt(idx); + case CONFIG_ICL: + return iclConfig.readInt(idx); + case CONFIG_PAL: + return palConfig.readInt(idx); + default: + return 0; + } +} + +uint64_t ConfigReader::readUint(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readUint(idx); + case CONFIG_DRAM: + return dramConfig.readUint(idx); + case CONFIG_FTL: + return ftlConfig.readUint(idx); + case CONFIG_NVME: + return nvmeConfig.readUint(idx); + case CONFIG_SATA: + return sataConfig.readUint(idx); + case CONFIG_UFS: + return ufsConfig.readUint(idx); + case CONFIG_ICL: + return iclConfig.readUint(idx); + case CONFIG_PAL: + return palConfig.readUint(idx); + default: + return 0; + } +} + +float ConfigReader::readFloat(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readFloat(idx); + case CONFIG_DRAM: + return dramConfig.readFloat(idx); + case CONFIG_FTL: + return ftlConfig.readFloat(idx); + case CONFIG_NVME: + return nvmeConfig.readFloat(idx); + case CONFIG_SATA: + return sataConfig.readFloat(idx); + case CONFIG_UFS: + return ufsConfig.readFloat(idx); + case CONFIG_ICL: + return iclConfig.readFloat(idx); + case CONFIG_PAL: + return palConfig.readFloat(idx); + default: + return 0.f; + } +} + +std::string ConfigReader::readString(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readString(idx); + case CONFIG_DRAM: + return dramConfig.readString(idx); + case CONFIG_FTL: + return ftlConfig.readString(idx); + case CONFIG_NVME: + return nvmeConfig.readString(idx); + case CONFIG_SATA: + return sataConfig.readString(idx); + case CONFIG_UFS: + return ufsConfig.readString(idx); + case CONFIG_ICL: + return iclConfig.readString(idx); + case CONFIG_PAL: + return palConfig.readString(idx); + default: + return std::string(); + } +} + +bool ConfigReader::readBoolean(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readBoolean(idx); + case CONFIG_DRAM: + return dramConfig.readBoolean(idx); + case CONFIG_FTL: + return ftlConfig.readBoolean(idx); + case CONFIG_NVME: + return nvmeConfig.readBoolean(idx); + case CONFIG_SATA: + return sataConfig.readBoolean(idx); + case CONFIG_UFS: + return ufsConfig.readBoolean(idx); + case CONFIG_ICL: + return iclConfig.readBoolean(idx); + case CONFIG_PAL: + return palConfig.readBoolean(idx); + default: + return false; + } +} + +int ConfigReader::parserHandler(void *context, const char *section, + const char *name, const char *value) { + ConfigReader *pThis = (ConfigReader *)context; + bool handled = false; + + if (MATCH_SECTION(SECTION_CPU)) { + handled = pThis->cpuConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_DRAM)) { + handled = pThis->dramConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_FTL)) { + handled = pThis->ftlConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_NVME)) { + handled = pThis->nvmeConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_SATA)) { + handled = pThis->sataConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_UFS)) { + handled = pThis->ufsConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_ICL)) { + handled = pThis->iclConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_PAL)) { + handled = pThis->palConfig.setConfig(name, value); + } + + if (!handled) { + warn("Config [%s] %s = %s not handled", section, name, value); + } + + return 1; +} + +DRAM::Config::DRAMStructure *ConfigReader::getDRAMStructure() { + return dramConfig.getDRAMStructure(); +} + +DRAM::Config::DRAMTiming *ConfigReader::getDRAMTiming() { + return dramConfig.getDRAMTiming(); +} + +DRAM::Config::DRAMPower *ConfigReader::getDRAMPower() { + return dramConfig.getDRAMPower(); +} + +uint8_t ConfigReader::getSuperblockConfig() { + return palConfig.getSuperblockConfig(); +} + +uint32_t ConfigReader::getPageAllocationConfig() { + return palConfig.getPageAllocationConfig(); +} + +PAL::Config::NANDTiming *ConfigReader::getNANDTiming() { + return palConfig.getNANDTiming(); +} + +PAL::Config::NANDPower *ConfigReader::getNANDPower() { + return palConfig.getNANDPower(); +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/config_reader.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/config_reader.hh new file mode 100644 index 0000000000..e831329c66 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/config_reader.hh @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_CONFIG_READER__ +#define __SIM_CONFIG_READER__ + +#include +#include + +#include "cpu/config.hh" +#include "dram/config.hh" +#include "ftl/config.hh" +#include "hil/nvme/config.hh" +#include "hil/sata/config.hh" +#include "hil/ufs/config.hh" +#include "icl/config.hh" +#include "lib/inih/ini.h" +#include "pal/config.hh" + +namespace SimpleSSD { + +typedef enum { + CONFIG_CPU, + CONFIG_DRAM, + CONFIG_FTL, + CONFIG_NVME, + CONFIG_SATA, + CONFIG_UFS, + CONFIG_ICL, + CONFIG_PAL, +} CONFIG_SECTION; + +class ConfigReader { + private: + CPU::Config cpuConfig; + DRAM::Config dramConfig; + FTL::Config ftlConfig; + HIL::NVMe::Config nvmeConfig; + HIL::SATA::Config sataConfig; + HIL::UFS::Config ufsConfig; + ICL::Config iclConfig; + PAL::Config palConfig; + + static int parserHandler(void *, const char *, const char *, const char *); + + public: + bool init(std::string); + + int64_t readInt(CONFIG_SECTION, uint32_t); + uint64_t readUint(CONFIG_SECTION, uint32_t); + float readFloat(CONFIG_SECTION, uint32_t); + std::string readString(CONFIG_SECTION, uint32_t); + bool readBoolean(CONFIG_SECTION, uint32_t); + + // DRAM::Config + DRAM::Config::DRAMStructure *getDRAMStructure(); + DRAM::Config::DRAMTiming *getDRAMTiming(); + DRAM::Config::DRAMPower *getDRAMPower(); + + // PAL::Config + uint8_t getSuperblockConfig(); + uint32_t getPageAllocationConfig(); + + PAL::Config::NANDTiming *getNANDTiming(); + PAL::Config::NANDPower *getNANDPower(); +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/cpu.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/cpu.cc new file mode 100644 index 0000000000..ac01439b89 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/cpu.cc @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/cpu.hh" + +namespace SimpleSSD { + +// Defined in sim/cpu.hh +CPU::CPU *cpu = nullptr; +DMAFunction cpuHandler = commonCPUHandler; + +CPUContext::_CPUContext(DMAFunction &f, void *c) : func(f), context(c) {} + +CPUContext::_CPUContext(DMAFunction &f, void *c, CPU::NAMESPACE n, + CPU::FUNCTION fc) + : func(f), context(c), ns(n), fct(fc), delay(0) {} + +CPUContext::_CPUContext(DMAFunction &f, void *c, CPU::NAMESPACE n, + CPU::FUNCTION fc, uint64_t d) + : func(f), context(c), ns(n), fct(fc), delay(d) {} + +void initCPU(ConfigReader &conf) { + if (cpu) { + delete cpu; + } + + cpu = new CPU::CPU(conf); +} + +void deInitCPU() { + delete cpu; + cpu = nullptr; +} + +void getCPUStatList(std::vector &list, std::string prefix) { + if (cpu) { + cpu->getStatList(list, prefix); + } +} + +void getCPUStatValues(std::vector &values) { + if (cpu) { + cpu->getStatValues(values); + } +} + +void resetCPUStatValues() { + if (cpu) { + cpu->resetStatValues(); + } +} + +void printCPULastStat() { + if (cpu) { + cpu->printLastStat(); + } +} + +void execute(CPU::NAMESPACE ns, CPU::FUNCTION fct, DMAFunction &func, + void *context, uint64_t delay) { + if (cpu) { + cpu->execute(ns, fct, func, context, delay); + } +} + +void commonCPUHandler(uint64_t, void *context) { + CPUContext *pContext = (CPUContext *)context; + + execute(pContext->ns, pContext->fct, pContext->func, pContext->context, + pContext->delay); + + delete pContext; +} + +uint64_t applyLatency(CPU::NAMESPACE ns, CPU::FUNCTION fct) { + if (cpu) { + return cpu->applyLatency(ns, fct); + } + + return 0; +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/cpu.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/cpu.hh new file mode 100644 index 0000000000..4d49048d7a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/cpu.hh @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_CPU__ +#define __SIM_CPU__ + +#include +#include + +#include "cpu/cpu.hh" + +namespace SimpleSSD { + +typedef struct _CPUContext { + DMAFunction func; + void *context; + + CPU::NAMESPACE ns; + CPU::FUNCTION fct; + uint64_t delay; + + _CPUContext(DMAFunction &, void *); + _CPUContext(DMAFunction &, void *, CPU::NAMESPACE, CPU::FUNCTION); + _CPUContext(DMAFunction &, void *, CPU::NAMESPACE, CPU::FUNCTION, uint64_t); +} CPUContext; + +void initCPU(ConfigReader &); +void deInitCPU(); +void getCPUStatList(std::vector &, std::string); +void getCPUStatValues(std::vector &); +void resetCPUStatValues(); +void printCPULastStat(); + +void execute(CPU::NAMESPACE, CPU::FUNCTION, DMAFunction &, void * = nullptr, + uint64_t = 0); +uint64_t applyLatency(CPU::NAMESPACE, CPU::FUNCTION); + +void commonCPUHandler(uint64_t, void *); + +// Defined at sim/cpu.cc +extern DMAFunction cpuHandler; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/dma_interface.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/dma_interface.hh new file mode 100644 index 0000000000..40af0d1b1a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/dma_interface.hh @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_DMA_INTERFACE__ +#define __SIM_DMA_INTERFACE__ + +#include +#include + +namespace SimpleSSD { + +typedef std::function DMAFunction; + +typedef struct _DMAContext { + int counter; + DMAFunction function; + void *context; + + _DMAContext(DMAFunction &f) : counter(0), function(f), context(nullptr) {} + _DMAContext(DMAFunction &f, void *c) : counter(0), function(f), context(c) {} +} DMAContext; + +class DMAInterface { + public: + DMAInterface() {} + virtual ~DMAInterface() {} + + virtual void dmaRead(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; + virtual void dmaWrite(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/log.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/log.cc new file mode 100644 index 0000000000..31335f0368 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/log.cc @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/log.hh" +#include "sim/trace.hh" + +#include +#include +#include +#include +#include + +#include "util/simplessd.hh" + +namespace SimpleSSD { + +struct Logger { + std::ostream *outfile; + std::ostream *errfile; + + Logger(std::ostream *o, std::ostream *e) : outfile(o), errfile(e) {} +}; + +Logger *logger = nullptr; + +void panic(const char *format, ...) { + if (logger) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + if (logger->errfile) { + *(logger->errfile) << getTick() << ": panic: " << str.data() << std::endl; + } + else { + std::cerr << getTick() << ": panic: " << str.data() << std::endl; + } + } + + std::terminate(); +} + +void warn(const char *format, ...) { + if (logger && logger->errfile) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + *(logger->errfile) << getTick() << ": warn: " << str.data() << std::endl; + } +} + +void info(const char *format, ...) { + if (logger && logger->errfile) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + *(logger->errfile) << getTick() << ": info: " << str.data() << std::endl; + } +} + +const std::string logName[LOG_NUM] = { + "global", //!< LOG_COMMON + "CPU", //!< LOG_CPU + "HIL", //!< LOG_HIL + "HIL::NVMe", //!< LOG_HIL_NVME + "HIL::SATA", //!< LOG_HIL_SATA + "HIL::UFS", //!< LOG_HIL_UFS + "ICL", //!< LOG_ICL + "ICL::GenericCache", //!< LOG_ICL_GENERIC_CACHE + "FTL", //!< LOG_FTL + "FTL::PageMapping", //!< LOG_FTL_PAGE_MAPPING + "PAL", //!< LOG_PAL + "PAL::PALOLD", //!< LOG_PAL_OLD +}; + +void debugprint(LOG_ID id, const char *format, ...) { + if (logger && logger->outfile && id < LOG_NUM) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + *(logger->outfile) << getTick() << ": " << logName[id] << ": " << str.data() + << std::endl; + } +} + +void debugprint(LOG_ID id, const uint8_t *buffer, uint64_t size) { + if (logger && logger->outfile && id < LOG_NUM) { + uint32_t temp; + + temp = id; + logger->outfile->write((char *)&temp, 4); + logger->outfile->write((char *)&size, 8); + logger->outfile->write((const char *)buffer, size); + } +} + +void initLogSystem(std::ostream *out, std::ostream *err) { + destroyLogSystem(); + + logger = new Logger(out, err); +} + +void destroyLogSystem() { + delete logger; +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/log.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/log.hh new file mode 100644 index 0000000000..23df8293fd --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/log.hh @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_LOG__ +#define __SIM_LOG__ + +#include + +namespace SimpleSSD { + +void initLogSystem(std::ostream *, std::ostream *); +void destroyLogSystem(); + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/simulator.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/simulator.cc new file mode 100644 index 0000000000..8e3c2d1682 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/simulator.cc @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/simulator.hh" + +namespace SimpleSSD { + +// Defined in sim/simulator.hh +Simulator *sim = nullptr; + +void setSimulator(Simulator *p) { + sim = p; +} + +uint64_t getTick() { + if (sim) { + return sim->getCurrentTick(); + } + + return 0; +} + +Event allocate(EventFunction f) { + if (sim) { + return sim->allocateEvent(f); + } + + return 0; +} + +void schedule(Event e, uint64_t t) { + if (sim) { + sim->scheduleEvent(e, t); + } +} + +void deschedule(Event e) { + if (sim) { + sim->descheduleEvent(e); + } +} + +bool scheduled(Event e, uint64_t *p) { + if (sim) { + return sim->isScheduled(e, p); + } + + return false; +} + +void deallocate(Event e) { + if (sim) { + sim->deallocateEvent(e); + } +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/simulator.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/simulator.hh new file mode 100644 index 0000000000..9a1d27e5b6 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/simulator.hh @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_SIMULATOR__ +#define __SIM_SIMULATOR__ + +#include +#include + +#include "sim/config_reader.hh" + +namespace SimpleSSD { + +typedef uint64_t Event; +typedef std::function EventFunction; + +class Simulator { + public: + Simulator() {} + virtual ~Simulator() {} + + virtual uint64_t getCurrentTick() = 0; + + virtual Event allocateEvent(EventFunction) = 0; + virtual void scheduleEvent(Event, uint64_t) = 0; + virtual void descheduleEvent(Event) = 0; + virtual bool isScheduled(Event, uint64_t * = nullptr) = 0; + virtual void deallocateEvent(Event) = 0; +}; + +void setSimulator(Simulator *p); +uint64_t getTick(); +Event allocate(EventFunction f); +void schedule(Event e, uint64_t t); +void deschedule(Event e); +bool scheduled(Event e, uint64_t *p = nullptr); +void deallocate(Event e); + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/state.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/state.cc new file mode 100644 index 0000000000..728b0446a9 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/state.cc @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/state.hh" + +#include + +#include "sim/trace.hh" + +namespace SimpleSSD { + +template +void StateObject::pushValue(std::vector &data, T value) { + uint32_t valueSize = sizeof(value); + uint8_t *src = (uint8_t *)&value; + uint8_t *dst = nullptr; + + data.resize(data.size() + valueSize); + + dst = data.data() + data.size() - valueSize; + memcpy(dst, src, valueSize); +} + +template +void StateObject::popValue(std::vector &data, T value) { + uint32_t valueSize = sizeof(value); + uint8_t *dst = (uint8_t *)&value; + uint8_t *src = nullptr; + + if (data.size() < valueSize) { + panic("Invalid data stream size"); + } + + src = data.data() + data.size() - valueSize; + memcpy(dst, src, valueSize); + + data.erase(data.begin() + data.size() - valueSize, data.end()); +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/state.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/state.hh new file mode 100644 index 0000000000..b74789dbc0 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/state.hh @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_STATE__ +#define __SIM_STATE__ + +#include +#include + +namespace SimpleSSD { + +class StateObject { + protected: + template + static void pushValue(std::vector &, T); + template + static void popValue(std::vector &, T); + + public: + StateObject() {} + virtual ~StateObject() {} + + virtual void saveState(std::vector &) {} + virtual void loadState(std::vector &) {} +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/statistics.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/statistics.hh new file mode 100644 index 0000000000..7ee6f9eb5c --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/statistics.hh @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_STATISTICS__ +#define __SIM_STATISTICS__ + +#include +#include +#include + +namespace SimpleSSD { + +typedef struct { + std::string name; + std::string desc; +} Stats; + +class StatObject { + public: + StatObject() {} + virtual ~StatObject() {} + + virtual void getStatList(std::vector &, std::string) {} + virtual void getStatValues(std::vector &) {} + virtual void resetStatValues() {} +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/trace.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/trace.hh new file mode 100644 index 0000000000..2bdd0c423d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/sim/trace.hh @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_TRACE__ +#define __SIM_TRACE__ + +#include + +namespace SimpleSSD { + +typedef enum { + LOG_COMMON, + LOG_CPU, + LOG_HIL, + LOG_HIL_NVME, + LOG_HIL_SATA, + LOG_HIL_UFS, + LOG_ICL, + LOG_ICL_GENERIC_CACHE, + LOG_FTL, + LOG_FTL_PAGE_MAPPING, + LOG_PAL, + LOG_PAL_OLD, + LOG_NUM +} LOG_ID; + +void debugprint(LOG_ID, const char *, ...); +void debugprint(LOG_ID, const uint8_t *, uint64_t); + +void panic(const char *, ...); +void warn(const char *, ...); +void info(const char *, ...); + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/algorithm.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/algorithm.hh new file mode 100644 index 0000000000..03ee065859 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/algorithm.hh @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_ALGORITHM__ +#define __UTIL_ALGORITHM__ + +#include +#include +#include + +#ifdef _MSC_VER + +#include + +#include + +#define __builtin_bswap16 _byteswap_ushort +#define __builtin_bswap32 _byteswap_ulong +#define __builtin_bswap64 _byteswap_uint64 + +inline uint32_t __builtin_clzl(uint32_t val) { + unsigned long leadingZero = 0; + + if (_BitScanReverse(&leadingZero, val)) { + return 31 - leadingZero; + } + + return 32; +} + +inline uint32_t __builtin_ffsl(uint32_t val) { + unsigned long trailingZero = 0; + + if (_BitScanForward(&trailingZero, val)) { + return trailingZero + 1; + } + + return 0; +} + +#endif + +#ifndef MIN +#define MIN(x, y) ((x) > (y) ? (y) : (x)) +#endif + +#ifndef MAX +#define MAX(x, y) ((x) > (y) ? (x) : (y)) +#endif + +#define DIVCEIL(x, y) (((x)-1) / (y) + 1) + +namespace SimpleSSD { + +template +uint8_t popcount(T v) { + v = v - ((v >> 1) & (T) ~(T)0 / 3); + v = (v & (T) ~(T)0 / 15 * 3) + ((v >> 2) & (T) ~(T)0 / 15 * 3); + v = (v + (v >> 4)) & (T) ~(T)0 / 255 * 15; + v = (T)(v * ((T) ~(T)0 / 255)) >> (sizeof(T) - 1) * CHAR_BIT; + + return (uint8_t)v; +} + +inline uint64_t generateMask(uint32_t val, uint32_t &count) { + uint64_t mask = (uint64_t)-1; + uint32_t tmp = 0; + + if (val > 0) { + int shift = __builtin_clzl(val); + + if (shift + __builtin_ffsl(val) == 64) { + shift++; + } + + tmp = 64 - shift; + mask = (mask << tmp); + } + + mask = (~mask) << count; + count += tmp; + + return mask; +} + +inline uint16_t bswap16(uint16_t val) { + return __builtin_bswap16(val); +} + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/bitset.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/bitset.cc new file mode 100644 index 0000000000..559fd478af --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/bitset.cc @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/bitset.hh" + +#include +#include + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +Bitset::Bitset() : data(nullptr), dataSize(0), allocSize(0) {} + +Bitset::Bitset(uint32_t size) : Bitset() { + if (size > 0) { + dataSize = size; + allocSize = DIVCEIL(dataSize, 8); + data = (uint8_t *)calloc(allocSize, 1); + } +} + +Bitset::Bitset(const Bitset &rhs) : Bitset(rhs.dataSize) { + if (rhs.data) { + memcpy(data, rhs.data, allocSize); + } +} + +Bitset::Bitset(Bitset &&rhs) noexcept { + dataSize = std::move(rhs.dataSize); + allocSize = std::move(rhs.allocSize); + data = std::move(rhs.data); + + rhs.dataSize = 0; + rhs.allocSize = 0; + rhs.data = nullptr; +} + +Bitset::~Bitset() { + free(data); + + data = nullptr; + dataSize = 0; + allocSize = 0; +} + +bool Bitset::test(uint32_t idx) noexcept { + return data[idx / 8] & (0x01 << (idx % 8)); +} + +bool Bitset::all() noexcept { + uint8_t ret = 0xFF; + uint8_t mask = 0xFF << (dataSize + 8 - allocSize * 8); + + for (uint32_t i = 0; i < allocSize - 1; i++) { + ret &= data[i]; + } + + ret &= data[allocSize - 1] | mask; + + return ret == 0xFF; +} + +bool Bitset::any() noexcept { + return !none(); +} + +bool Bitset::none() noexcept { + uint8_t ret = 0x00; + + for (uint32_t i = 0; i < allocSize; i++) { + ret |= data[i]; + } + + return ret == 0x00; +} + +uint32_t Bitset::count() noexcept { + uint32_t count = 0; + + for (uint32_t i = 0; i < allocSize; i++) { + count += popcount(data[i]); + } + + return count; +} + +uint32_t Bitset::size() noexcept { + return dataSize; +} + +void Bitset::set() noexcept { + uint8_t mask = 0xFF >> (allocSize * 8 - dataSize); + + for (uint32_t i = 0; i < allocSize - 1; i++) { + data[i] = 0xFF; + } + + data[allocSize - 1] = mask; +} + +void Bitset::set(uint32_t idx, bool value) noexcept { + data[idx / 8] &= ~(0x01 << (idx % 8)); + + if (value) { + data[idx / 8] = data[idx / 8] | (0x01 << (idx % 8)); + } +} + +void Bitset::reset() noexcept { + for (uint32_t i = 0; i < allocSize; i++) { + data[i] = 0x00; + } +} + +void Bitset::reset(uint32_t idx) noexcept { + data[idx / 8] &= ~(0x01 << (idx % 8)); +} + +void Bitset::flip() noexcept { + uint8_t mask = 0xFF >> (allocSize * 8 - dataSize); + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] = ~data[i]; + } + + data[allocSize - 1] &= mask; +} + +void Bitset::flip(uint32_t idx) noexcept { + data[idx / 8] = (~data[idx / 8] & (0x01 << (idx % 8))) | + (data[idx / 8] & ~(0x01 << (idx % 8))); +} + +bool Bitset::operator[](uint32_t idx) noexcept { + return test(idx); +} + +Bitset &Bitset::operator&=(const Bitset &rhs) { + if (dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] &= rhs.data[i]; + } + + return *this; +} + +Bitset &Bitset::operator|=(const Bitset &rhs) { + if (dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] |= rhs.data[i]; + } + + return *this; +} + +Bitset &Bitset::operator^=(const Bitset &rhs) { + if (dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] ^= rhs.data[i]; + } + + return *this; +} + +Bitset &Bitset::operator=(const Bitset &rhs) { + if (this != &rhs) { + free(data); + data = nullptr; + + *this = Bitset(rhs); + } + + return *this; +} + +Bitset &Bitset::operator=(Bitset &&rhs) noexcept { + if (this != &rhs) { + free(data); + + dataSize = std::move(rhs.dataSize); + allocSize = std::move(rhs.allocSize); + data = std::move(rhs.data); + + rhs.dataSize = 0; + rhs.allocSize = 0; + rhs.data = nullptr; + } + + return *this; +} + +Bitset Bitset::operator~() const { + Bitset ret(*this); + + ret.flip(); + + return ret; +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/bitset.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/bitset.hh new file mode 100644 index 0000000000..5469cb9a86 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/bitset.hh @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_BITSET__ +#define __UTIL_BITSET__ + +#include +#include + +#include "sim/trace.hh" + +namespace SimpleSSD { + +// TODO: use SIMD operation if possible +class Bitset { + private: + uint8_t *data; + uint32_t dataSize; + uint32_t allocSize; + + public: + Bitset(); + Bitset(uint32_t); + Bitset(const Bitset &); + Bitset(Bitset &&) noexcept; + ~Bitset(); + + bool test(uint32_t) noexcept; + bool all() noexcept; + bool any() noexcept; + bool none() noexcept; + uint32_t count() noexcept; + uint32_t size() noexcept; + void set() noexcept; + void set(uint32_t, bool = true) noexcept; + void reset() noexcept; + void reset(uint32_t) noexcept; + void flip() noexcept; + void flip(uint32_t) noexcept; + + bool operator[](uint32_t) noexcept; + Bitset &operator&=(const Bitset &); + Bitset &operator|=(const Bitset &); + Bitset &operator^=(const Bitset &); + Bitset &operator=(const Bitset &); + Bitset &operator=(Bitset &&) noexcept; + Bitset operator~() const; + + friend Bitset operator&(Bitset lhs, const Bitset &rhs) { lhs &= rhs; return lhs; } + friend Bitset operator|(Bitset lhs, const Bitset &rhs) { lhs |= rhs; return lhs; } + friend Bitset operator^(Bitset lhs, const Bitset &rhs) { lhs ^= rhs; return lhs; } + friend bool operator==(const Bitset &lhs, const Bitset &rhs) { + bool ret = true; + + if (lhs.dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < lhs.allocSize; i++) { + if (lhs.data[i] != rhs.data[i]) { + ret = false; + + break; + } + } + + return ret; + } + + friend bool operator!=(const Bitset &lhs, const Bitset &rhs) { + return !operator==(lhs, rhs); + } +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/def.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/def.cc new file mode 100644 index 0000000000..16a300aa59 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/def.cc @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/def.hh" + +#include +#include + +namespace SimpleSSD { + +LPNRange::_LPNRange() : slpn(0), nlp(0) {} + +LPNRange::_LPNRange(uint64_t s, uint64_t n) : slpn(s), nlp(n) {} + +namespace HIL { + +Request::_Request() + : reqID(0), + reqSubID(0), + offset(0), + length(0), + finishedAt(0), + context(nullptr) {} + +Request::_Request(DMAFunction &f, void *c) + : reqID(0), + reqSubID(0), + offset(0), + length(0), + finishedAt(0), + function(f), + context(c) {} + +bool Request::operator()(const Request &a, const Request &b) { + return a.finishedAt > b.finishedAt; +} + +} // namespace HIL + +namespace ICL { + +Request::_Request() : reqID(0), reqSubID(0), offset(0), length(0) {} + +Request::_Request(HIL::Request &r) + : reqID(r.reqID), + reqSubID(r.reqSubID), + offset(r.offset), + length(r.length), + range(r.range) {} + +} // namespace ICL + +namespace FTL { + +Request::_Request(uint32_t iocount) + : reqID(0), reqSubID(0), lpn(0), ioFlag(iocount) {} + +Request::_Request(uint32_t iocount, ICL::Request &r) + : reqID(r.reqID), + reqSubID(r.reqSubID), + lpn(r.range.slpn / iocount), + ioFlag(iocount) { + ioFlag.set(r.range.slpn % iocount); +} + +} // namespace FTL + +namespace PAL { + +Request::_Request(uint32_t iocount) + : reqID(0), reqSubID(0), blockIndex(0), pageIndex(0), ioFlag(iocount) {} + +Request::_Request(FTL::Request &r) + : reqID(r.reqID), + reqSubID(r.reqSubID), + blockIndex(0), + pageIndex(0), + ioFlag(r.ioFlag) {} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/def.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/def.hh new file mode 100644 index 0000000000..b61cda3ceb --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/def.hh @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_DEF__ +#define __UTIL_DEF__ + +#include + +#include "sim/dma_interface.hh" +#include "util/bitset.hh" + +namespace SimpleSSD { + +typedef struct _LPNRange { + uint64_t slpn; + uint64_t nlp; + + _LPNRange(); + _LPNRange(uint64_t, uint64_t); +} LPNRange; + +namespace HIL { + +typedef struct _Request { + uint64_t reqID; + uint64_t reqSubID; + uint64_t offset; + uint64_t length; + LPNRange range; + + uint64_t finishedAt; + DMAFunction function; + void *context; + + _Request(); + _Request(DMAFunction &, void *); + + bool operator()(const _Request &a, const _Request &b); +} Request; + +} // namespace HIL + +namespace ICL { + +typedef struct _Request { + uint64_t reqID; + uint64_t reqSubID; + uint64_t offset; + uint64_t length; + LPNRange range; + + _Request(); + _Request(HIL::Request &); +} Request; + +} // namespace ICL + +namespace FTL { + +typedef struct _Request { + uint64_t reqID; // ID of ICL::Request + uint64_t reqSubID; + uint64_t lpn; + Bitset ioFlag; + + _Request(uint32_t); + _Request(uint32_t, ICL::Request &); +} Request; + +} // namespace FTL + +namespace PAL { + +typedef struct _Request { + uint64_t reqID; // ID of ICL::Request + uint64_t reqSubID; + uint32_t blockIndex; + uint32_t pageIndex; + Bitset ioFlag; + + _Request(uint32_t); + _Request(FTL::Request &); +} Request; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/disk.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/disk.cc new file mode 100644 index 0000000000..1987d7b0a6 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/disk.cc @@ -0,0 +1,314 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/disk.hh" + +#include + +#ifdef _MSC_VER +#include +#else +#include +#include +#endif + +namespace SimpleSSD { + +Disk::Disk() : diskSize(0), sectorSize(0) {} + +Disk::~Disk() { + close(); +} + +uint64_t Disk::open(std::string path, uint64_t desiredSize, uint32_t lbaSize) { + filename = path; + sectorSize = lbaSize; + + // Validate size +#ifdef _MSC_VER + LARGE_INTEGER size; + HANDLE hFile = CreateFileA(path.c_str(), GENERIC_READ | GENERIC_WRITE, NULL, + NULL, OPEN_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); + + if (GetLastError() == ERROR_ALREADY_EXISTS) { + if (GetFileSizeEx(hFile, &size)) { + diskSize = size.QuadPart; + } + else { + // panic("Get file size failed!"); + } + } + else { + size.QuadPart = desiredSize; + + if (SetFilePointerEx(hFile, size, nullptr, FILE_BEGIN)) { + if (SetEndOfFile(hFile)) { + diskSize = desiredSize; + } + else { + // panic("SetEndOfFile failed"); + } + } + else { + // panic("SetFilePointerEx failed"); + } + } + + CloseHandle(hFile); +#else + struct stat s; + + if (stat(filename.c_str(), &s) == 0) { + // File exists + if (S_ISREG(s.st_mode)) { + diskSize = s.st_size; + } + else { + // panic("nvme_disk: Specified file %s is not regular file.\n", + // filename.c_str()); + } + } + else { + // Create zero-sized file + disk.open(filename, std::ios::out | std::ios::binary); + disk.close(); + + // Set file size + if (truncate(filename.c_str(), desiredSize) == 0) { + diskSize = desiredSize; + } + else { + // panic("nvme_disk: Failed to set disk size %" PRIu64 " errno=%d\n", + // diskSize, errno); + } + } +#endif + + // Open file + disk.open(filename, std::ios::in | std::ios::out | std::ios::binary); + + if (!disk.is_open()) { + // panic("failed to open file"); + } + + return diskSize; +} + +void Disk::close() { + if (disk.is_open()) { + disk.close(); + } +} + +uint16_t Disk::read(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t ret = 0; + + if (disk.is_open()) { + uint64_t avail; + + slba *= sectorSize; + avail = nlblk * sectorSize; + + if (slba + avail > diskSize) { + if (slba >= diskSize) { + avail = 0; + } + else { + avail = diskSize - slba; + } + } + + if (avail > 0) { + disk.seekg(slba, std::ios::beg); + if (!disk.good()) { + // panic("nvme_disk: Fail to seek to %" PRIu64 "\n", slba); + } + + disk.read((char *)buffer, avail); + } + + memset(buffer + avail, 0, nlblk * sectorSize - avail); + + // DPRINTF(NVMeDisk, "DISK | READ | BYTE %016" PRIX64 " + %X\n", + // slba, nlblk * sectorSize); + + ret = nlblk; + } + + return ret; +} + +uint16_t Disk::write(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t ret = 0; + + if (disk.is_open()) { + slba *= sectorSize; + + disk.seekp(slba, std::ios::beg); + if (!disk.good()) { + // panic("nvme_disk: Fail to seek to %" PRIu64 "\n", slba); + } + + uint64_t offset = disk.tellp(); + disk.write((char *)buffer, sectorSize * nlblk); + offset = (uint64_t)disk.tellp() - offset; + + // DPRINTF(NVMeDisk, "DISK | WRITE | BYTE %016" PRIX64 " + %X\n", slba, + // offset); + + ret = offset / sectorSize; + } + + return ret; +} + +uint16_t Disk::erase(uint64_t, uint16_t nlblk) { + return nlblk; +} + +CoWDisk::CoWDisk() {} + +CoWDisk::~CoWDisk() { + close(); +} + +void CoWDisk::close() { + table.clear(); + + Disk::close(); +} + +uint16_t CoWDisk::read(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t read = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(buffer + i * sectorSize, block->second.data(), sectorSize); + read++; + } + else { + read += Disk::read(slba + i, 1, buffer + i * sectorSize); + } + } + + return read; +} + +uint16_t CoWDisk::write(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t write = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(block->second.data(), buffer + i * sectorSize, sectorSize); + } + else { + std::vector data; + + data.resize(sectorSize); + memcpy(data.data(), buffer + i * sectorSize, sectorSize); + + table.insert({slba + i, data}); + } + + write++; + } + + return write; +} + +uint64_t MemDisk::open(std::string, uint64_t size, uint32_t lbaSize) { + diskSize = size; + sectorSize = lbaSize; + + return size; +} + +void MemDisk::close() { + table.clear(); +} + +MemDisk::MemDisk() {} + +MemDisk::~MemDisk() { + close(); +} + +uint16_t MemDisk::read(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t read = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(buffer + i * sectorSize, block->second.data(), sectorSize); + } + else { + memset(buffer + i * sectorSize, 0, sectorSize); + } + + read++; + } + + return read; +} + +uint16_t MemDisk::write(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t write = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(block->second.data(), buffer + i * sectorSize, sectorSize); + } + else { + std::vector data; + + data.resize(sectorSize); + memcpy(data.data(), buffer + i * sectorSize, sectorSize); + + table.insert({slba + i, data}); + } + + write++; + } + + return write; +} +uint16_t MemDisk::erase(uint64_t slba, uint16_t nlblk) { + uint16_t erase = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + table.erase(block); + } + + erase++; + } + + return erase; +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/disk.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/disk.hh new file mode 100644 index 0000000000..77342c2d7a --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/disk.hh @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_DISK__ +#define __UTIL_DISK__ + +#include +#include +#include +#include +#include + +namespace SimpleSSD { + +class Disk { + protected: + std::string filename; + uint64_t diskSize; + uint32_t sectorSize; + + std::fstream disk; + + public: + Disk(); + Disk(const Disk &) = delete; + virtual ~Disk(); + + virtual uint64_t open(std::string, uint64_t, uint32_t); + virtual void close(); + + virtual uint16_t read(uint64_t, uint16_t, uint8_t *); + virtual uint16_t write(uint64_t, uint16_t, uint8_t *); + virtual uint16_t erase(uint64_t, uint16_t); +}; + +class CoWDisk : public Disk { + private: + std::unordered_map> table; + + public: + CoWDisk(); + CoWDisk(const CoWDisk &) = delete; + ~CoWDisk(); + + void close() override; + + uint16_t read(uint64_t, uint16_t, uint8_t *) override; + uint16_t write(uint64_t, uint16_t, uint8_t *) override; +}; + +class MemDisk : public Disk { + private: + std::unordered_map> table; + + public: + MemDisk(); + MemDisk(const MemDisk &) = delete; + ~MemDisk(); + + uint64_t open(std::string, uint64_t, uint32_t) override; + void close() override; + + uint16_t read(uint64_t, uint16_t, uint8_t *) override; + uint16_t write(uint64_t, uint16_t, uint8_t *) override; + uint16_t erase(uint64_t, uint16_t) override; +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/fifo.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/fifo.cc new file mode 100644 index 0000000000..50a7cdc8dc --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/fifo.cc @@ -0,0 +1,421 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/fifo.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +FIFOEntry::FIFOEntry() + : last(true), + id(0), + addr(0), + size(0), + buffer(nullptr), + arrivedAt(0), + insertBeginAt(0), + insertEndAt(0), + context(nullptr) {} + +FIFOEntry::FIFOEntry(uint64_t a, uint64_t s, uint8_t *b, DMAFunction &f, + void *c) + : last(true), + id(0), + addr(a), + size(s), + buffer(b), + arrivedAt(getTick()), + insertBeginAt(0), + insertEndAt(0), + func(f), + context(c) {} + +ReadEntry::ReadEntry() : id(0), insertEndAt(0), dmaEndAt(0), latency(0) {} + +ReadEntry::ReadEntry(uint64_t a, uint64_t i, uint64_t d, uint64_t l) + : id(a), insertEndAt(i), dmaEndAt(d), latency(l) {} + +FIFO::Queue::Queue(uint64_t c) + : capacity(c), usage(0), insertPending(false), transferPending(false) {} + +FIFO::FIFO(DMAInterface *up, FIFOParam &p) + : upstream(up), + param(p), + readQueue(p.rqSize), + writeQueue(p.wqSize), + counter(0) { + // Sanity check + if (param.transferUnit > param.rqSize || param.transferUnit > param.wqSize) { + panic("Invalid transferUnit size"); + } + + // Set Transfer Unit Latency + unitLatency = param.latency(param.transferUnit); + + // Allocate events and functions for each queue + writeQueue.insertDone = allocate([this](uint64_t) { insertWriteDone(); }); + writeQueue.beginTransfer = allocate([this](uint64_t) { transferWrite(); }); + writeQueue.submitCompletion = + allocate([this](uint64_t) { transferWriteDoneNext(); }); + writeQueue.transferDone = [this](uint64_t, void *) { transferWriteDone(); }; + readQueue.insertDone = allocate([this](uint64_t) { insertReadDone(); }); + readQueue.beginTransfer = allocate([this](uint64_t) { insertRead(); }); + readQueue.submitCompletion = + allocate([this](uint64_t) { insertReadDoneNext(); }); + readQueue.transferDone = [this](uint64_t, void *) { transferReadDone(); }; +} + +FIFO::~FIFO() {} + +std::list::iterator FIFO::find(uint64_t id) { + auto iter = readCompletion.begin(); + + for (; iter != readCompletion.end(); iter++) { + if (iter->id == id) { + break; + } + } + + return iter; +} + +uint64_t FIFO::calcSize(uint64_t size, bool &b) { + if (size < param.transferUnit) { + b = true; + + return size; + } + + return DIVCEIL(size, param.transferUnit) * param.transferUnit; +} + +void FIFO::insertWrite() { + auto iter = writeQueue.waitQueue.begin(); + bool smallerThanUnit = false; + uint64_t now = getTick(); + uint64_t size = calcSize(iter->size, smallerThanUnit); + + if ((writeQueue.insertPending || + writeQueue.usage + size > writeQueue.capacity) && + size <= param.wqSize) { + return; + } + + // We need to split large request + if (size > param.wqSize) { + FIFOEntry copy = *iter; + + // copy is next one + copy.last = true; + copy.addr = iter->addr + param.transferUnit; + copy.size = iter->size - param.transferUnit; + copy.buffer = iter->buffer ? iter->buffer + param.transferUnit : nullptr; + + // iter is current one + iter->last = false; + iter->size = param.transferUnit; + + // Insert copy after iter + writeQueue.waitQueue.insert(++iter, copy); + + // iter should first one + iter = writeQueue.waitQueue.begin(); + size = calcSize(iter->size, smallerThanUnit); + } + + writeQueue.insertPending = true; + + // Current item will be written to FIFO + writeQueue.usage += size; + iter->insertBeginAt = now; + iter->insertEndAt = now + param.latency(size); + + // When insertion done, call handler + schedule(writeQueue.insertDone, iter->insertEndAt); + + // Current item will be transferred after one transferUnit written to FIFO + // If we alwritey scheduled, current item will be transffered after last one + if (!scheduled(writeQueue.beginTransfer)) { + schedule(writeQueue.beginTransfer, + now + (smallerThanUnit ? param.latency(size) : unitLatency)); + } + + // Push current item to transferQueue + writeQueue.transferQueue.push(*iter); +} + +void FIFO::insertWriteDone() { + // Pop last item + writeQueue.waitQueue.pop_front(); + writeQueue.insertPending = false; + + // Insert next waiting item + if (writeQueue.waitQueue.size() > 0) { + insertWrite(); + } +} + +void FIFO::transferWrite() { + auto &iter = writeQueue.transferQueue.front(); + + if (writeQueue.transferPending) { + return; + } + + writeQueue.transferPending = true; + + // Begin transfer + upstream->dmaWrite(iter.addr, iter.size, iter.buffer, + writeQueue.transferDone); +} + +void FIFO::transferWriteDone() { + auto &iter = writeQueue.transferQueue.front(); + uint64_t now = getTick(); + uint64_t latency = + (iter.size < param.transferUnit) ? param.latency(iter.size) : unitLatency; + + if (now >= iter.insertEndAt + latency) { // Upstream <= downstream + // Finish immediately + transferWriteDoneNext(); + } + else { // upstream is faster than downstream + // Should finish at insertedEndAt + upstreamLatency(transferUnit) + // TODO: Applying unitLatency is not correct (more slower result) + schedule(writeQueue.submitCompletion, iter.insertEndAt + latency); + } +} + +void FIFO::transferWriteDoneNext() { + auto &iter = writeQueue.transferQueue.front(); + bool unused; + uint64_t now = getTick(); + + // Call handler + if (iter.last) { + iter.func(now, iter.context); + } + + // Transfer done + writeQueue.usage -= calcSize(iter.size, unused); + writeQueue.transferPending = false; + writeQueue.transferQueue.pop(); + + // Do next transfer if we have + if (writeQueue.transferQueue.size() > 0) { + if (!scheduled(writeQueue.beginTransfer)) { + transferWrite(); + } + } + + // Do next insertion if we have + if (writeQueue.waitQueue.size() > 0) { + insertWrite(); + } +} + +void FIFO::transferRead() { + auto iter = readQueue.waitQueue.begin(); + bool smallerThanUnit = false; + uint64_t size = calcSize(iter->size, smallerThanUnit); + + if ((readQueue.transferPending || + readQueue.usage + size > readQueue.capacity) && + size <= param.rqSize) { + return; + } + + // We need to split large request + if (size > param.rqSize) { + FIFOEntry copy = *iter; + + // copy is next one + copy.last = true; + copy.addr = iter->addr + param.transferUnit; + copy.size = iter->size - param.transferUnit; + copy.buffer = iter->buffer ? iter->buffer + param.transferUnit : nullptr; + + // iter is current one + iter->last = false; + iter->size = param.transferUnit; + + // Insert copy after iter + readQueue.waitQueue.insert(++iter, copy); + + // iter should first one + iter = readQueue.waitQueue.begin(); + size = calcSize(iter->size, smallerThanUnit); + } + + readQueue.transferPending = true; + + // Set ID + iter->id = counter++; + + // Current item will be requested to be read + readQueue.usage += size; + + // When all data is read to FIFO, call handler + upstream->dmaRead(iter->addr, iter->size, iter->buffer, + readQueue.transferDone); + + if (!scheduled(readQueue.beginTransfer)) { + schedule(readQueue.beginTransfer, + getTick() + (smallerThanUnit ? param.latency(size) : unitLatency)); + } + + // Push current item to transferQueue + readQueue.transferQueue.push(*iter); +} + +void FIFO::transferReadDone() { + auto &iter = readQueue.waitQueue.front(); + uint64_t latency = + (iter.size < param.transferUnit) ? param.latency(iter.size) : unitLatency; + + // Save DMA end time + auto comp = find(iter.id); + + if (comp == readCompletion.end()) { + readCompletion.push_back(ReadEntry(iter.id, 0, getTick(), latency)); + } + else { + comp->dmaEndAt = getTick(); + + insertReadDoneMerge(comp); + } + + // Pop last item + readQueue.waitQueue.pop_front(); + readQueue.transferPending = false; + + // Transfer next waiting item + if (readQueue.waitQueue.size() > 0) { + transferRead(); + } +} + +void FIFO::insertRead() { + auto &iter = readQueue.transferQueue.front(); + bool unused; + uint64_t now = getTick(); + + if (readQueue.insertPending) { + return; + } + + readQueue.insertPending = true; + + // Begin insertion + iter.insertBeginAt = now; + iter.insertEndAt = now + param.latency(calcSize(iter.size, unused)); + + // When insertion done, call handler + if (!scheduled(readQueue.insertDone)) { + schedule(readQueue.insertDone, iter.insertEndAt); + } +} + +void FIFO::insertReadDone() { + auto &iter = readQueue.transferQueue.front(); + uint64_t latency = + (iter.size < param.transferUnit) ? param.latency(iter.size) : unitLatency; + + auto comp = find(iter.id); + + if (comp == readCompletion.end()) { + readCompletion.push_back(ReadEntry(iter.id, getTick(), 0, latency)); + } + else { + insertReadDoneMerge(comp); + } +} + +void FIFO::insertReadDoneMerge(std::list::iterator comp) { + uint64_t now = getTick(); + + if (now >= comp->dmaEndAt + comp->latency) { // Upstream <= downstream + // Finish immediately + insertReadDoneNext(); + } + else { // upstream is faster than downstream + // Should finish at insertedEndAt + upstreamLatency(transferUnit) + // TODO: Applying unitLatency is not correct (more slower result) + schedule(readQueue.submitCompletion, comp->dmaEndAt + comp->latency); + } + + readCompletion.erase(comp); +} + +void FIFO::insertReadDoneNext() { + auto &iter = readQueue.transferQueue.front(); + bool unused; + uint64_t now = getTick(); + + // Call handler + if (iter.last) { + iter.func(now, iter.context); + } + + // Insert done + readQueue.usage -= calcSize(iter.size, unused); + readQueue.insertPending = false; + readQueue.transferQueue.pop(); + + // Do next insert if we have + if (readQueue.transferQueue.size() > 0) { + if (!scheduled(readQueue.beginTransfer)) { + insertRead(); + } + } + + // Do next transfer if we have + if (readQueue.waitQueue.size() > 0) { + transferRead(); + } +} + +void FIFO::dmaRead(uint64_t addr, uint64_t size, uint8_t *buffer, + DMAFunction &func, void *context) { + if (size == 0) { + warn("FIFO: zero-size DMA read request. Ignore."); + + return; + } + + readQueue.waitQueue.push_back(FIFOEntry(addr, size, buffer, func, context)); + + transferRead(); +} + +void FIFO::dmaWrite(uint64_t addr, uint64_t size, uint8_t *buffer, + DMAFunction &func, void *context) { + if (size == 0) { + warn("FIFO: zero-size DMA write request. Ignore."); + + return; + } + + writeQueue.waitQueue.push_back(FIFOEntry(addr, size, buffer, func, context)); + + insertWrite(); +} + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/fifo.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/fifo.hh new file mode 100644 index 0000000000..213b6c72fe --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/fifo.hh @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_FIFO__ +#define __UTIL_FIFO__ + +#include +#include + +#include "sim/dma_interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +typedef std::function LatencyFunction; + +struct FIFOParam { + uint64_t rqSize; //!< Read Queue size + uint64_t wqSize; //!< Write Queue size + uint64_t transferUnit; //!< Transfer unit used to interleave DMA + LatencyFunction latency; //!< Downstream latency function +}; + +struct FIFOEntry { + bool last; //!< This is last entry of splitted request + uint64_t id; + + uint64_t addr; + uint64_t size; + uint8_t *buffer; + + uint64_t arrivedAt; //!< Request arrived to FIFO + uint64_t insertBeginAt; //!< Request is now begin to written on FIFO + uint64_t insertEndAt; //!< Request is fully written on FIFO + + DMAFunction func; + void *context; + + FIFOEntry(); + FIFOEntry(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); +}; + +struct ReadEntry { + uint64_t id; + uint64_t insertEndAt; + uint64_t dmaEndAt; + uint64_t latency; + + ReadEntry(); + ReadEntry(uint64_t, uint64_t, uint64_t, uint64_t); +}; + +class FIFO : public DMAInterface { + protected: + class Queue { + public: + uint64_t capacity; + uint64_t usage; + + std::list waitQueue; + std::queue transferQueue; + + Event insertDone; + Event beginTransfer; + Event submitCompletion; + DMAFunction transferDone; + + bool insertPending; + bool transferPending; + + Queue(uint64_t); + }; + + DMAInterface *upstream; + FIFOParam param; + uint64_t unitLatency; + + Queue readQueue; + Queue writeQueue; + + uint64_t counter; + std::list readCompletion; + + std::list::iterator find(uint64_t); + + uint64_t calcSize(uint64_t, bool &); + + // Write + void insertWrite(); + void insertWriteDone(); + void transferWrite(); + void transferWriteDone(); + void transferWriteDoneNext(); + + // Read + void transferRead(); + void transferReadDone(); + void insertRead(); + void insertReadDone(); + void insertReadDoneMerge(std::list::iterator); + void insertReadDoneNext(); + + public: + FIFO() = delete; + FIFO(DMAInterface *, FIFOParam &); + FIFO(const FIFO &) = delete; + ~FIFO(); + + void dmaRead(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; + void dmaWrite(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; +}; + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/interface.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/interface.cc new file mode 100644 index 0000000000..89f35bca53 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/interface.cc @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/interface.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace PCIExpress { + +static const uint32_t maxPayloadSize = 4096; // Bytes +static const uint32_t packetOverhead = 36; // Bytes +static const uint32_t internalDelay[PCIE_NUM] = {19, 70, 115}; // Symbol +static const float encoding[PCIE_NUM] = {1.25f, 1.25f, 1.015625f}; // Ratio +static const uint32_t delay[PCIE_NUM] = {3200, 1600, 1000}; // pico-second + +uint64_t calculateDelay(PCIE_GEN gen, uint8_t lane, uint64_t bytesize) { + uint64_t nTLP = MAX(DIVCEIL(bytesize, maxPayloadSize), 1); + uint64_t nSymbol; + + nSymbol = bytesize + nTLP * (packetOverhead); + nSymbol = DIVCEIL(nSymbol, lane) + 1 + nTLP * internalDelay[gen]; + + return (uint64_t)(delay[gen] * encoding[gen] * nSymbol + 0.5f); +} + +} // namespace PCIExpress + +namespace SATA { + +// Each primitive is 1 DWORD (4bytes) +// One Fram contains SOF/EOF/CRC and HOLD/A primitives +// Just assume no HOLD/HOLDA + +static const uint32_t packetOverhead = 3; // Primitive +static const uint32_t internalDelay = 12; // DWORD +static const float encoding = 1.25f; // Ratio +static const uint32_t delay[SATA_NUM] = {5336, 2667, 1333}; // pico-second + +uint64_t calculateDelay(SATA_GEN gen, uint64_t bytesize) { + uint64_t dwords = DIVCEIL(bytesize, 4) + internalDelay + packetOverhead; + + dwords = dwords * 4; + + return (uint64_t)(delay[gen] * encoding * dwords + 0.5f); +} + +} // namespace SATA + +namespace MIPI { + +namespace M_PHY { + +// See M-PHY spec v4.0 section 4.7.2 BURST, Figure 14 and 15 +static const uint32_t tLine = 7000; // pico-second +static const uint32_t nPrepare = 15; // Bytes +static const uint32_t nSync = 15; // Bytes +static const uint32_t nStall = 7; // Bytes +static const float encoding = 1.25f; // Ratio +static const uint32_t delay[HS_NUM] = {6410, 3205, 1603, 801}; // pico-second + +uint64_t calculateDelay(M_PHY_MODE mode, uint8_t lane, uint64_t symbol) { + uint64_t nSymbol = nPrepare + nSync + 1 + symbol * 2 + nStall; + + nSymbol = (nSymbol - 1) / lane + 2; + + return (uint64_t)(delay[mode] * encoding * nSymbol + 0.5f + tLine); +} + +} // namespace M_PHY + +namespace UniPro { + +static const uint32_t maxPayloadSize = 254; // Bytes +static const uint32_t packetOverhead = 7; // Symbol + +uint64_t calculateDelay(M_PHY::M_PHY_MODE mode, uint8_t lane, + uint64_t bytesize) { + uint64_t nPacket = MAX((bytesize - 1) / maxPayloadSize + 1, 1); + uint64_t nSymbol = (bytesize + 1) / 2; + + nSymbol += nPacket * packetOverhead; + + return M_PHY::calculateDelay(mode, lane, nSymbol); +} + +} // namespace UniPro + +} // namespace MIPI + +namespace ARM { + +namespace AXI { + +// Two cycles per one data beat +// Two cycles for address, one cycle for write response +// One burst request should contain 1, 2, 4, 8 .. of beats + +static const uint32_t maxPayloadSize = 4096; // Bytes + +uint64_t calculateDelay(uint64_t clock, BUS_WIDTH width, uint64_t bytesize) { + uint32_t nBeats = MAX(DIVCEIL(bytesize, width), 1); + uint32_t nBursts = popcount(nBeats) + (bytesize - 1) / maxPayloadSize; + uint32_t nClocks = nBeats * 2 + nBursts * 3; + uint64_t period = (uint64_t)(1000000000000.0 / clock + 0.5); + + return nClocks * period; +} + +namespace Stream { + +// Unlimited bursts +// If master and slave can handle data sufficiently fast, +// one cycle per one data beat +// No address and responses + +uint64_t calculateDelay(uint64_t clock, BUS_WIDTH width, uint64_t bytesize) { + uint64_t period = (uint64_t)(1000000000000.0 / clock + 0.5); + + return bytesize / width * period; +} + +} // namespace Stream + +} // namespace AXI + +} // namespace ARM + +} // namespace SimpleSSD diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/interface.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/interface.hh new file mode 100644 index 0000000000..012b851c9f --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/interface.hh @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_INTERFACE__ +#define __UTIL_INTERFACE__ + +#include + +namespace SimpleSSD { + +namespace PCIExpress { + +typedef enum { + PCIE_1_X, // PCI Express Gen. 1.x + PCIE_2_X, // PCI Express Gen. 2.x + PCIE_3_X, // PCI Express Gen. 3.x + PCIE_NUM +} PCIE_GEN; + +uint64_t calculateDelay(PCIE_GEN, uint8_t, uint64_t); + +} // namespace PCIExpress + +namespace SATA { + +typedef enum { + SATA_1_0, // SATA 1.0 (1.5Gbps) + SATA_2_0, // SATA 2.0 (3Gbps) + SATA_3_0, // SATA 3.0/3.1 (6Gbps) + SATA_NUM +} SATA_GEN; + +uint64_t calculateDelay(SATA_GEN, uint64_t); + +} // namespace SATA + +namespace MIPI { + +namespace M_PHY { + +typedef enum { + HS_G1, // High Speed Gear 1 + HS_G2, // High Speed Gear 2 + HS_G3, // High Speed Gear 3 + HS_G4, // High Speed Gear 4 + HS_NUM +} M_PHY_MODE; + +uint64_t calculateDelay(M_PHY_MODE, uint8_t, uint64_t); + +} // namespace M_PHY + +namespace UniPro { + +uint64_t calculateDelay(M_PHY::M_PHY_MODE, uint8_t, uint64_t); + +} // namespace UniPro + +} // namespace MIPI + +namespace ARM { + +namespace AXI { + +typedef enum { + BUS_32BIT = 4, + BUS_64BIT = 8, + BUS_128BIT = 16, + BUS_256BIT = 32, + BUS_512BIT = 64, + BUS_1024BIT = 128, +} BUS_WIDTH; + +uint64_t calculateDelay(uint64_t, BUS_WIDTH, uint64_t); + +namespace Stream { + +uint64_t calculateDelay(uint64_t, BUS_WIDTH, uint64_t); + +} // namespace Stream + +} // namespace AXI + +} // namespace ARM + +} // namespace SimpleSSD + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/old/SimpleSSD_types.h b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/old/SimpleSSD_types.h new file mode 100644 index 0000000000..75872b3725 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/old/SimpleSSD_types.h @@ -0,0 +1,273 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + * Donghyun Gouk + */ + +#ifndef __ssdsim_types_h__ +#define __ssdsim_types_h__ + +#include + +/*============================== +Switches +==============================*/ + +// Option Switch +#define DMA_PREEMPTION 1 // For distingushing before-implementation. On/off is available at config file. +#define ENABLE_FTL 1 //FTL integration + + +// DBG Print Switch +#define DBG_PRINT 1 +#if DBG_PRINT +#define DBG_PRINT_PPN 0 +#define DBG_PRINT_TICK 0 +#define DBG_PRINT_CHANNEL 0 +#define DBG_PRINT_BUSY 0 +#define DBG_PRINT_REQSTART 1 +#define DBG_PRINT_REQDONE 1 +#define DBG_PRINT_CONFLICT 0 +#define DBG_PRINT_CONFIGPARSER 0 +#define DBG_PRINT_REQUEST 1 +#endif + +#define LOG_PRINT_ABSOLUTE_TIME 0 +#define LOG_PRINT_CONSUMED_TIME 0 + +#define LOG_PRINT_OCCUPY_EACH 0 + +#define GATHER_TIME_SERIES 0 +#define GATHER_RESOURCE_CONFLICT 1 +#define FULL_VERIFY_TIMELINE 0 // don't flush timeline for verification at the end +#define HARD_VERIFY_TIMELINE 0 // Verify PAL Timeline on every update! ... CAUCTION: takes VERY LONG time + + +/*============================== +Strings +==============================*/ +extern char ADDR_STRINFO[][10]; +extern char ADDR_STRINFO2[][15]; +extern char OPER_STRINFO[][10]; +extern char OPER_STRINFO2[][10]; +extern char BUSY_STRINFO[][10]; +extern char PAGE_STRINFO[][10]; +extern char NAND_STRINFO[][10]; +#if GATHER_RESOURCE_CONFLICT +extern char CONFLICT_STRINFO[][10]; +#endif + +typedef uint64_t Tick; +typedef uint64_t Addr; + +/*============================== +Macros +==============================*/ +//#define GET_ACCESSOR(propName, propType) propType get##propName() const { return m_##propName; } +//#define SET_ACCESSOR(propName, propType) void set##propName(const propType &newVal) { m_##propName = newVal; } + +#define CREATE_ACCESSOR(propType, propName) \ +private: \ +propType propName; \ +public: \ +void set##propName(const propType newVal) { propName = newVal; }; \ +propType get##propName() const { return propName; }; + +#ifdef _MSC_VER +#define printa(fmt, ...) do { printf(fmt, __VA_ARGS__); if (outfp) fprintf(outfp, fmt, __VA_ARGS__); } while(0); +#define printo(fmt, ...) do { if (!outfp) printf(fmt, __VA_ARGS__); if(outfp) fprintf(outfp, fmt, __VA_ARGS__); } while(0); +#define printft(fmt, ...) do { printf(" "); printf(fmt, __VA_ARGS__); } while(0); +#else +#define printa(fmt...) do { printf(fmt); if (outfp) fprintf(outfp, fmt); } while(0); +#define printo(fmt...) do { if (!outfp) printf(fmt); if(outfp) fprintf(outfp, fmt); } while(0); +#define printft(fmt...) do { printf(" "); printf(fmt); } while(0); +#endif + +//#define ERR_EXIT(fmt...) {printf(fmt); std::terminate();} +#define SAFEDIV(left,right) ((right)==0?0:(left)/(right)) + + +/*============================== +Type & Struct +==============================*/ +#define MAX64 0xFFFFFFFFFFFFFFFF +#define MAX32 0xFFFFFFFF + +#define BYTE (1) +#define KBYTE (1024) +#define MBYTE (1024*KBYTE) +#define GBYTE (1024*MBYTE) +#define TBYTE (1024*GBYTE) + +#define SEC (1) +#define MSEC (1000) // 1 000 +#define USEC (1000*MSEC) // 1 000 000 +#define NSEC ((uint64_t)1000*USEC) // 1 000 000 000 +#define PSEC ((uint64_t)1000*NSEC) // 1 000 000 000 000 + +//===== Address Sequence ===== +enum { + ADDR_CHANNEL = 0, + ADDR_PACKAGE = 1, + ADDR_DIE = 2, + ADDR_PLANE = 3, + ADDR_BLOCK = 4, + ADDR_PAGE = 5, + ADDR_NUM +}; + +enum { + FTL_PAGE_MAPPING, + FTL_BLOCK_MAPPING, + FTL_HYBRID_MAPPING +}; + +enum { + CACHE_EVICT_SUPER_PAGE, + CACHE_EVICT_SUPER_BLOCK +}; + +//===== Operation Types ===== +typedef enum _PAL_OPERATION { + OPER_READ = 0, + OPER_WRITE = 1, + OPER_ERASE = 2, + OPER_NUM +} PAL_OPERATION; + +//===== Busy Types ===== +enum { + BUSY_DMA0WAIT, + BUSY_DMA0, + BUSY_MEM, + BUSY_DMA1WAIT, + BUSY_DMA1, + BUSY_END, + BUSY_NUM +}; + + +//===== Log-purpose: Tick types ===== +enum { + TICK_DMA0WAIT = 0, // == TICK_IOREQUESTED + TICK_DMA0, + TICK_MEM, + TICK_DMA1WAIT, + TICK_DMA1, + TICK_IOEND, + TICK_NUM +}; + +//===== NAND Flash - Page address kind ===== +enum { + PAGE_LSB = 0, + PAGE_CSB = 1, + PAGE_MSB = 2, + PAGE_NUM +}; + +//===== NAND Flash type ===== +enum { + NAND_SLC, + NAND_MLC, + NAND_TLC, + NAND_NUM +}; + +//===== Request2 Status type ===== +enum +{ + REQSTAT_NEW, + REQSTAT_PROC, + REQSTAT_END +}; + + +#if GATHER_RESOURCE_CONFLICT +enum +{ + CONFLICT_NONE = 0, + CONFLICT_DMA0 = 1<<0, //DMA0 couldn't start due to CH BUSY --- exclusive to CONFLICT_MEM + CONFLICT_MEM = 1<<1, //DMA0 couldn't start due to MEM BUSY --- exclusive to CONFLICT_DMA0 + CONFLICT_DMA1 = 1<<2, //DMA1 couldn't start due to CH BUSY + CONFLICT_NUM = 4 //0~3 = 4 +}; +#endif + +/* +Todo: Make those structs to class?, to check address limitation & warn. +*/ + +//===== Divided Address ===== +typedef struct _CPDPBP +{ + uint32_t Channel; + uint32_t Package; + uint32_t Die; + uint32_t Plane; + uint32_t Block; + uint32_t Page; +}CPDPBP; + +//===== PPN Request Info (would be in the queue) ===== +class RequestFTL +{ +public: + uint64_t PPN; + uint8_t Oper; + uint64_t TickRequested; +}; + +//===== Task which can be assign to Channel or Memory ===== +class Task +{ +public: + uint64_t PPN; + CPDPBP CPD; + uint32_t PlaneIdx; + uint8_t Oper; + uint8_t Busy; + #if DMA_PREEMPTION + uint64_t DMASuspend; // 0 = no suspend, true = suspended & left time + #endif + uint64_t TickStart[TICK_NUM]; // End Time of each BUSY status, [BUSY_NUM] = END_TIME, actually not needed for simulation itself. + uint64_t TickNext; +}; + +//===== PPN Request Info (would be in the queue) ===== +class RequestLL +{ +public: + uint64_t PPN; + uint8_t Oper; + uint64_t TickRequested; + uint64_t TickFinished; + + CPDPBP CPD; + uint8_t status; // 0-New, 1-Fetched, 2-Finished + RequestLL* LLprev; //Dual-Linked-List + RequestLL* LLnext; //Dual-Linked-List +}; + +//===== Task which can be assign to Channel or Memory ===== +class TaskLL : Task +{ +public: + RequestLL* SrcRequest; //Dual-Linked-List +}; + +#endif //__ssdsim_types_h__ diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/simplessd.cc b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/simplessd.cc new file mode 100644 index 0000000000..6dd6df6ef8 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/simplessd.cc @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/simplessd.hh" + +#include "sim/log.hh" + +using namespace SimpleSSD; + +ConfigReader initSimpleSSDEngine(Simulator *sim, std::ostream *info, + std::ostream *err, std::string config) { + ConfigReader conf; + + setSimulator(sim); + initLogSystem(info, err); + + if (!conf.init(config)) { + panic("Failed to open configuration file %s", config.c_str()); + } + + initCPU(conf); + + return conf; +} + +void releaseSimpleSSDEngine() { + printCPULastStat(); + + deInitCPU(); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/simplessd.hh b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/simplessd.hh new file mode 100644 index 0000000000..90bb27e26e --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/simplessd/util/simplessd.hh @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_SIMPLESSD__ +#define __UTIL_SIMPLESSD__ + +#include "sim/config_reader.hh" +#include "sim/cpu.hh" +#include "sim/simulator.hh" +#include "sim/statistics.hh" +#include "sim/trace.hh" + +SimpleSSD::ConfigReader initSimpleSSDEngine(SimpleSSD::Simulator *, + std::ostream *, std::ostream *, + std::string); +void releaseSimpleSSDEngine(); + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/util/convert.cc b/SSD-WAF-Analysis-Capstone-2025-main/util/convert.cc new file mode 100644 index 0000000000..4e1f40b6a5 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/util/convert.cc @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/convert.hh" + +#include + +#include "simplessd/sim/trace.hh" + +const std::regex regexInteger("(\\d+)([kKmMgGtTpP]?)", + std::regex_constants::ECMAScript); +const std::regex regexTime("(\\d+)([munp]?s?)", + std::regex_constants::ECMAScript | + std::regex_constants::icase); + +bool convertBoolean(const char *value) { + uint64_t number = convertInteger(value); + + if (number > 0) { + return true; + } + + if (strlen(value) == 1) { + if (value[0] == 't' || value[0] == 'T' || value[0] == 'y' || + value[0] == 'Y') { + return true; + } + } + + if (strcasecmp(value, "true") == 0 || strcasecmp(value, "yes") == 0) { + return true; + } + + return false; +} + +uint64_t convertInteger(const char *value, bool *valid) { + uint64_t ret = 0; + std::cmatch match; + + if (valid) { + *valid = false; + } + + if (std::regex_match(value, match, regexInteger)) { + if (valid) { + *valid = true; + } + + ret = strtoul(match[1].str().c_str(), nullptr, 10); + + if (match[2].length() > 0) { + switch (match[2].str().at(0)) { + case 'k': + ret *= 1000ul; + break; + case 'K': + ret *= 1024ul; + break; + case 'm': + ret *= 1000000ul; + break; + case 'M': + ret *= 1048576ul; + break; + case 'g': + ret *= 1000000000ul; + break; + case 'G': + ret *= 1073741824ul; + break; + case 't': + ret *= 1000000000000ul; + break; + case 'T': + ret *= 1099511627776ul; + break; + default: + SimpleSSD::warn("Invalid suffix detected"); + break; + } + } + } + + return ret; +} + +uint64_t convertTime(const char *value, bool *valid) { + uint64_t ret = 0; + std::cmatch match; + + if (valid) { + *valid = false; + } + + if (std::regex_match(value, match, regexTime)) { + if (valid) { + *valid = true; + } + + ret = strtoul(match[1].str().c_str(), nullptr, 10); + + if (match[2].length() > 0) { + switch (match[2].str().at(0)) { + case 's': + ret *= 1000000000000ul; + break; + case 'm': + ret *= 1000000000ul; + break; + case 'u': + ret *= 1000000ul; + break; + case 'n': + ret *= 1000ul; + break; + case 'p': + // Do Nothing + break; + default: + SimpleSSD::warn("Invalid suffix detected"); + break; + } + } + } + + return ret; +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/util/convert.hh b/SSD-WAF-Analysis-Capstone-2025-main/util/convert.hh new file mode 100644 index 0000000000..a93753f355 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/util/convert.hh @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_CONVERT__ +#define __UTIL_CONVERT__ + +#include + +#ifdef _MSC_VER +#define strcasecmp _stricmp +#endif + +bool convertBoolean(const char *); +uint64_t convertInteger(const char *, bool * = nullptr); +uint64_t convertTime(const char *, bool * = nullptr); + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/util/print.cc b/SSD-WAF-Analysis-Capstone-2025-main/util/print.cc new file mode 100644 index 0000000000..342ef55e98 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/util/print.cc @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/print.hh" + +void print(std::ostream &out, std::string str, uint32_t width) { + if (str.length() >= width) { + out << str; + } + else { + width -= (uint32_t)str.length(); + + str.append(width, ' '); + + out << str; + } +} + +void print(std::ostream &out, double val, uint32_t width) { + print(out, std::to_string(val), width); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/util/print.hh b/SSD-WAF-Analysis-Capstone-2025-main/util/print.hh new file mode 100644 index 0000000000..c361d6ef5b --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/util/print.hh @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_PRINT__ +#define __UTIL_PRINT__ + +#include +#include +#include + +void print(std::ostream &, std::string, uint32_t); +void print(std::ostream &, double, uint32_t); + +#endif diff --git a/SSD-WAF-Analysis-Capstone-2025-main/util/stopwatch.cc b/SSD-WAF-Analysis-Capstone-2025-main/util/stopwatch.cc new file mode 100644 index 0000000000..20e7b99a0d --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/util/stopwatch.cc @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/stopwatch.hh" + +Stopwatch::Stopwatch() {} + +Stopwatch::~Stopwatch() {} + +double Stopwatch::getTime() { + return std::chrono::duration_cast>( + std::chrono::high_resolution_clock::now().time_since_epoch()) + .count(); +} + +void Stopwatch::start() { + begin = std::chrono::high_resolution_clock::now(); +} + +void Stopwatch::stop() { + end = std::chrono::high_resolution_clock::now(); +} + +double Stopwatch::getDuration() { + return std::chrono::duration_cast>(end - begin) + .count(); +} diff --git a/SSD-WAF-Analysis-Capstone-2025-main/util/stopwatch.hh b/SSD-WAF-Analysis-Capstone-2025-main/util/stopwatch.hh new file mode 100644 index 0000000000..fb94b0e3f5 --- /dev/null +++ b/SSD-WAF-Analysis-Capstone-2025-main/util/stopwatch.hh @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __UTIL_STOPWATCH__ +#define __UTIL_STOPWATCH__ + +#include + +class Stopwatch { + private: + std::chrono::high_resolution_clock::time_point begin; + std::chrono::high_resolution_clock::time_point end; + + public: + Stopwatch(); + ~Stopwatch(); + + // Get timepoint + double getTime(); + + // Stopwatch + void start(); + void stop(); + double getDuration(); +}; + +#endif diff --git "a/docs/01.\353\263\264\352\263\240\354\204\234/01.\341\204\216\341\205\241\341\206\250\341\204\211\341\205\256\341\204\207\341\205\251\341\204\200\341\205\251\341\204\211\341\205\245.pdf" "b/docs/01.\353\263\264\352\263\240\354\204\234/01.\341\204\216\341\205\241\341\206\250\341\204\211\341\205\256\341\204\207\341\205\251\341\204\200\341\205\251\341\204\211\341\205\245.pdf" new file mode 100644 index 0000000000..cb21d840bf Binary files /dev/null and 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a/hotness/SimpleSSD-Standalone/.clang-format b/hotness/SimpleSSD-Standalone/.clang-format new file mode 100644 index 0000000000..38a9d1af6b --- /dev/null +++ b/hotness/SimpleSSD-Standalone/.clang-format @@ -0,0 +1,27 @@ +# Generated by clang-format v5.0.0 +--- +Language: Cpp +BasedOnStyle: Google +AllowShortFunctionsOnASingleLine: Inline +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakBeforeMultilineStrings: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + BeforeCatch: true + BeforeElse: true + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBraces: Custom +DerivePointerAlignment: false +PointerAlignment: Right +... diff --git a/hotness/SimpleSSD-Standalone/.github/ISSUE_TEMPLATE/bug_report.md b/hotness/SimpleSSD-Standalone/.github/ISSUE_TEMPLATE/bug_report.md new file mode 100644 index 0000000000..90db8e42c4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/.github/ISSUE_TEMPLATE/bug_report.md @@ -0,0 +1,30 @@ +--- +name: Bug report +about: Create a report to help us improve +title: '' +labels: '' +assignees: '' + +--- + +### Describe the bug +A clear and concise description of what the bug is. + +### To Reproduce +Steps to reproduce the behavior: +1. Go to '...' +2. Click on '....' +3. Scroll down to '....' +4. See error + +### Expected behavior +A clear and concise description of what you expected to happen. + +### Screenshots +If applicable, add screenshots to help explain your problem. + +### Running Environment (please complete the following information): + - Host OS and Kernel version: [e.g. Ubuntu 16.04 with Linux 4.14] + - Compiler version used to build SimpleSSD-Standalone: [e.g. GCC 5.3.1] + - SimpleSSD-Standalone version: [e.g. v2.0-rc4 - or commit hash] + - SimpleSSD version: [e.g. v2.0.6 - or commit hash] diff --git a/hotness/SimpleSSD-Standalone/.github/ISSUE_TEMPLATE/question.md b/hotness/SimpleSSD-Standalone/.github/ISSUE_TEMPLATE/question.md new file mode 100644 index 0000000000..0c86926b28 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/.github/ISSUE_TEMPLATE/question.md @@ -0,0 +1,21 @@ +--- +name: Question +about: Use this format for asking question +title: '' +labels: '' +assignees: '' + +--- + +### Running Environment (please complete the following information): + - Host OS and Kernel version: [e.g. Ubuntu 16.04 with Linux 4.14] + - Compiler version used to build SimpleSSD-Standalone: [e.g. GCC 5.3.1] + - SimpleSSD-Standalone version: [e.g. v2.0-rc4 - or commit hash] + - SimpleSSD version: [e.g. v2.0.6 - or commit hash] + +### Execution information +- Standalone configuration file: +[e.g. TimingMode = 1 ...] + +### Explain what you want to ask here: +A clear explanation of your question. diff --git a/hotness/SimpleSSD-Standalone/.gitignore b/hotness/SimpleSSD-Standalone/.gitignore new file mode 100644 index 0000000000..296a544bc3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/.gitignore @@ -0,0 +1,38 @@ +# CMake Temporary Files +CMakeFiles/ +*.cmake +CMakeCache.txt + +# SimpleSSD output +libsimplessd.a +libmcpat.a +simplessd-standalone + +# Visual Studio Specific +.vs/ +Debug/ +Release/ +Win32/ +MinSizeRel/ +RelWithDebInfo/ +SimpleSSD-Standalone.dir +*.sdf +*.db +*.opendb +*.filters +*.vcxproj +*.vcproj +*.sln + +# Make Specific +Makefile +*.o +*.s + +# Atom Specific +.clang_complete +compile_flags.txt + +# VSCode Specific +.vscode/ +*.code-workspace diff --git a/hotness/SimpleSSD-Standalone/.gitmodules b/hotness/SimpleSSD-Standalone/.gitmodules new file mode 100644 index 0000000000..ae04c7116a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/.gitmodules @@ -0,0 +1,3 @@ +[submodule "simplessd"] + path = simplessd + url = https://github.com/SimpleSSD/SimpleSSD.git diff --git a/hotness/SimpleSSD-Standalone/CMakeLists.txt b/hotness/SimpleSSD-Standalone/CMakeLists.txt new file mode 100644 index 0000000000..9c3209f93c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/CMakeLists.txt @@ -0,0 +1,166 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +if (CMAKE_CXX_COMPILER_ID STREQUAL "Clang") + add_compile_options(-Wno-unused-command-line-argument) +endif() + +# Set version and project name +cmake_minimum_required(VERSION 3.10) +project(simplessd-standalone C CXX) + +# include_directories(${CMAKE_SOURCE_DIR}/third_party/rapidjson/include) + +if (CMAKE_CXX_COMPILER_ID STREQUAL "Clang") + add_compile_options( + -Wno-unused-command-line-argument + -Wno-error=unused-command-line-argument + ) +endif() + +# Add options for debug build +option(DEBUG_BUILD "Build SimpleSSD-Standalone in debug mode." OFF) + + + +# Set DRAMPower path +set(DRAMPOWER_SOURCE_DIR + "${PROJECT_SOURCE_DIR}/lib/drampower/src" + CACHE PATH + "" + FORCE +) + +# Check SimpleSSD is valid +if (NOT EXISTS "${PROJECT_SOURCE_DIR}/simplessd/CMakeLists.txt") + message(FATAL_ERROR "Failed to find SimpleSSD. \ +Check you initialized submodules.") +endif () + +# Add subproject +add_subdirectory(${PROJECT_SOURCE_DIR}/simplessd + ${CMAKE_BINARY_DIR}/simplessd +) + +# Set include directories +include_directories( + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/bil + ${PROJECT_SOURCE_DIR}/igl + ${PROJECT_SOURCE_DIR}/simplessd + ${DRAMPOWER_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/third_party/json +) + +# Platform specific settings +if (MSVC) + add_definitions(-D_CRT_SECURE_NO_WARNINGS) + add_compile_options(/wd4819) # Surpress unicode warning + add_compile_options(/wd4305) # Surpress truncation warning +else () + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS + "-O0 -g -pthread -Wall -Wextra ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS + "-O2 -pthread -Wall -Wextra ${CMAKE_CXX_FLAGS}") + endif () + + if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS "4.9") + message(FATAL_ERROR "GNU g++ < 4.9 does not support .\ +Please update your compiler.") + endif () + endif () +endif () + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Specify source files +set(SRC_BIL + bil/entry.cc + bil/noop_scheduler.cc +) +set(SRC_IGL_REQUEST + igl/request/request_config.cc + igl/request/request_generator.cc +) +set(SRC_IGL_TRACE + igl/trace/trace_config.cc + igl/trace/trace_replayer.cc +) +set(SRC_LIB_DRAMPOWER + lib/drampower/src/CAHelpers.cc + lib/drampower/src/CmdHandlers.cc + lib/drampower/src/CmdScheduler.cc + lib/drampower/src/CommandAnalysis.cc + lib/drampower/src/MemArchitectureSpec.cc + lib/drampower/src/MemBankWiseParams.cc + lib/drampower/src/MemCommand.cc + lib/drampower/src/MemoryPowerModel.cc + lib/drampower/src/MemorySpecification.cc + lib/drampower/src/MemPowerSpec.cc + lib/drampower/src/MemTimingSpec.cc + lib/drampower/src/Parameter.cc + lib/drampower/src/Parametrisable.cc + lib/drampower/src/TraceParser.cc + lib/drampower/src/libdrampower/LibDRAMPower.cc +) +set(SRC_SIL_NONE + sil/none/none.cc +) +set(SRC_SIL_NVME + sil/nvme/nvme.cc + sil/nvme/prp.cc + sil/nvme/queue.cc +) +set(SRC_SIM + sim/cfg_reader.cc + sim/engine.cc + sim/global_config.cc + sim/main.cc + sim/signal.cc +) +set(SRC_UTIL + util/convert.cc + util/print.cc + util/stopwatch.cc +) + +# Source group for MSVC +SOURCE_GROUP("Source Files\\bil" FILES ${SRC_BIL}) +SOURCE_GROUP("Source Files\\igl\\request" FILES ${SRC_IGL_REQUEST}) +SOURCE_GROUP("Source Files\\igl\\trace" FILES ${SRC_IGL_TRACE}) +SOURCE_GROUP("Source Files\\lib\\drampower" FILES ${SRC_LIB_DRAMPOWER}) +SOURCE_GROUP("Source Files\\sil\\none" FILES ${SRC_SIL_NONE}) +SOURCE_GROUP("Source Files\\sil\\nvme" FILES ${SRC_SIL_NVME}) +SOURCE_GROUP("Source Files\\sim" FILES ${SRC_SIM}) +SOURCE_GROUP("Source Files\\util" FILES ${SRC_UTIL}) + +# Define executable +add_executable(simplessd-standalone + ${SRC_BIL} + ${SRC_IGL_REQUEST} + ${SRC_IGL_TRACE} + ${SRC_LIB_DRAMPOWER} + ${SRC_SIL_NONE} + ${SRC_SIL_NVME} + ${SRC_SIM} + ${SRC_UTIL} +) +target_link_libraries(simplessd-standalone simplessd) diff --git a/hotness/SimpleSSD-Standalone/LICENSE b/hotness/SimpleSSD-Standalone/LICENSE new file mode 100644 index 0000000000..782c854d45 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the GPL requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. + + Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the manufacturer +can do so. This is fundamentally incompatible with the aim of +protecting users' freedom to change the software. The systematic +pattern of such abuse occurs in the area of products for individuals to +use, which is precisely where it is most unacceptable. Therefore, we +have designed this version of the GPL to prohibit the practice for those +products. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + SimpleSSD-Standalone Copyright (C) 2017 SimpleSSD + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/hotness/SimpleSSD-Standalone/README.md b/hotness/SimpleSSD-Standalone/README.md new file mode 100644 index 0000000000..cf8683b79d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/README.md @@ -0,0 +1,38 @@ +# 출처 및 라이선스 +## SimpleSSD version 2.0 +Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations + +This project is managed by [CAMELab](http://camelab.org). +For more information, please visit [SimpleSSD homepage](http://simplessd.org). +SimpleSSD is released under the GPLv3 license. See `LICENSE` file for details. + +- 클론(원본 출처): `git clone git@github.com:simplessd/simplessd-standalone` +- 문서 기준 버전: SimpleSSD 문서 v2.0.12 +- 원 라이선스: GNU GPLv3 +- 라이선스 적용: 본 프로젝트는 SimpleSSD 문서(v2.0.12)에 명시된 대로 **GPLv3 라이선스**를 그대로 차용하며, 원저작권/라이선스 고지를 유지합니다. + +# 목적 (Purpose) +It uses the method of first-touching the block by naming the Hotness label included in the write request as a variable called temperature. The tagged block will only accept data at the same temperature until full, and will be closed when full. After that, when a block is erased from the Garbage Collection (GC), the tag will be removed and returned to the free block, and a page_mapping_hotness file will be added for reuse in any temperature pool. + +쓰기 요청에 포함된 Hotness 레이블을 temperature라는 변수로 명명하여 블록을 첫 태깅(first-touch) 하는 방식을 사용합니다. 태깅된 블록은 가득 찰 때까지 동일 온도의 데이터만 수용하며, 가득 차면 닫힘(closed) 상태가 됩니다. 이후 가비지 컬렉션(GC)에서 블록이 소거(erase) 되면 태그가 제거되어 free 블록으로 환원되고, 어떤 온도 풀에서든 재사용될 수 있도록 하기 위해서 page_mapping_hotness 파일을 추가하게 되었습니다. + +# 변경 사실 +This repository contains the following changes to the source. +- Trace Replayer: Parsing and Injecting Labels +Safely parses the Hotness field in one line of trace. +- None Driver (sil/none): Forward BIO→HIL +Copy the BIO to req.temperature= bio.temperature without loss when converting it to HIL::Request. +- ICL Correction: Preserving labels with cache sidecar and re-injecting Flush +To prevent the label from being lost during ICL's write buffering, merging, and eviction process, introduce cache-line sidecar metadata and re-inject it into FTL requests during flushing. +- FTL modification for Hotness page mapping: label normalization, pool selection, consistent GC/WAF calculation +Receive and normalize req.temperature at FTL inlet (0-3) and select free block in label pool for physical separation recording. Label statistics and WAF are also aggregated and exposed in this module. + +본 저장소에는 원본 대비 다음 변경이 포함됩니다. +- Trace Replayer: 레이블 파싱·주입 +트레이스 한 줄에서 Hotness 필드를 안전하게 정수 파싱합니다. +- None 드라이버(sil/none): BIO→HIL 전달 +BIO를 HIL::Request로 변환할 때 req.temperature = bio.temperature로 손실 없이 복사합니다. +- ICL 수정: 캐시 사이드카로 레이블 보존·Flush 재주입 +ICL의 쓰기 버퍼링·병합·에빅션 과정에서 레이블이 소실되지 않도록, 캐시라인 단위 사이드카 메타데이터를 도입하고 flush 시 FTL 요청에 재주입합니다. +- Hotness page mapping을 위한 FTL 수정 : 레이블 정규화·풀 선택·일관 GC·WAF 산출 +FTL 입구에서 req.temperature를 수신·정규화하고(0~3), 레이블별 풀(Pool)에서 free 블록을 선택해 물리적 분리 기록을 수행합니다. 레이블별 통계와 WAF도 본 모듈에서 집계·노출합니다. diff --git a/hotness/SimpleSSD-Standalone/bandwidth.txt b/hotness/SimpleSSD-Standalone/bandwidth.txt new file mode 100644 index 0000000000..ca1f6722e6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bandwidth.txt @@ -0,0 +1 @@ +I/O (bytes): 8589934592 (256644291.674797 B/s) diff --git a/hotness/SimpleSSD-Standalone/bil/entry.cc b/hotness/SimpleSSD-Standalone/bil/entry.cc new file mode 100644 index 0000000000..45816f1282 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bil/entry.cc @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "bil/entry.hh" + +#include + +#include "bil/interface.hh" +#include "bil/noop_scheduler.hh" +#include "simplessd/sim/trace.hh" + +namespace BIL { + +BlockIOEntry::BlockIOEntry(ConfigReader &c, Engine &e, DriverInterface *i, + std::ostream *o) + : conf(c), + engine(e), + pLatencyFile(o), + pScheduler(nullptr), + pDriver(i), + lastProgress(0), + io_progress(0), + io_count(0), + minLatency(std::numeric_limits::max()), + maxLatency(0), + sumLatency(0), + squareSumLatency(0), + callback([this](uint64_t id) { completion(id); }) { + switch (c.readUint(CONFIG_GLOBAL, GLOBAL_SCHEDULER)) { + case SCHEDULER_NOOP: + pScheduler = new NoopScheduler(e, i); + + break; + default: + SimpleSSD::panic("Invalid I/O scheduler specified"); + + break; + } + + pScheduler->init(); +} + +BlockIOEntry::~BlockIOEntry() { + delete pScheduler; +} + +void BlockIOEntry::submitIO(BIO &bio) { + BIO copy(bio); + + io_count++; + bio.submittedAt = engine.getCurrentTick(); + + ioQueue.push_back(bio); + copy.callback = callback; + + pScheduler->submitIO(copy); +} + +void BlockIOEntry::completion(uint64_t id) { + uint64_t tick = engine.getCurrentTick(); + + for (auto iter = ioQueue.begin(); iter != ioQueue.end(); iter++) { + if (iter->id == id) { + tick = tick - iter->submittedAt; + + { + std::lock_guard guard(m); + + io_progress++; + + progress.latency += tick; + progress.iops++; + progress.bandwidth += iter->length; + } + + if (pLatencyFile) { + *pLatencyFile << std::to_string(iter->id) << ", " + << std::to_string(iter->offset) << ", " + << std::to_string(iter->length) << ", " + << std::to_string(tick) << std::endl; + } + + iter->callback(id); + + ioQueue.erase(iter); + + break; + } + } + + if (minLatency > tick) { + minLatency = tick; + } + if (maxLatency < tick) { + maxLatency = tick; + } + + sumLatency += tick; + squareSumLatency += tick * tick; +} + +void BlockIOEntry::printStats(std::ostream &out) { + double avgLatency = (double)sumLatency / io_count; + double stdevLatency = sqrt((double)squareSumLatency / io_count - avgLatency); + double digit = log10(avgLatency); + + out << "*** Statistics of Block I/O Entry ***" << std::endl; + + if (digit < 6.0) { + out << "Latency (ps): min=" << std::to_string(minLatency) + << ", max=" << std::to_string(maxLatency) + << ", avg=" << std::to_string(avgLatency) + << ", stdev=" << std::to_string(stdevLatency) << std::endl; + } + else if (digit < 9.0) { + out << "Latency (ns): min=" << std::to_string(minLatency / 1000.0) + << ", max=" << std::to_string(maxLatency / 1000.0) + << ", avg=" << std::to_string(avgLatency / 1000.0) + << ", stdev=" << std::to_string(stdevLatency / 31.62277660168) + << std::endl; + } + else if (digit < 12.0) { + out << "Latency (us): min=" << std::to_string(minLatency / 1000000.0) + << ", max=" << std::to_string(maxLatency / 1000000.0) + << ", avg=" << std::to_string(avgLatency / 1000000.0) + << ", stdev=" << std::to_string(stdevLatency / 1000.0) << std::endl; + } + else { + out << "Latency (ms): min=" << std::to_string(minLatency / 1000000000.0) + << ", max=" << std::to_string(maxLatency / 1000000000.0) + << ", avg=" << std::to_string(avgLatency / 1000000000.0) + << ", stdev=" << std::to_string(stdevLatency / 31622.77660168379) + << std::endl; + } + + out << "*** End of statistics ***" << std::endl; +} + +void BlockIOEntry::getProgress(Progress &data) { + uint64_t tick = engine.getCurrentTick(); + uint64_t diff = tick - lastProgress; + + if (diff == 0) { + data.iops = 0; + data.bandwidth = 0; + data.latency = 0; + + return; + } + + double ratio = 1000000000000.0 / diff; + + { + std::lock_guard guard(m); + + data.iops = progress.iops * ratio; + data.bandwidth = progress.bandwidth * ratio; + + if (io_progress == 0) { + data.latency = 0; + } + else { + data.latency = progress.latency / io_progress; + } + + io_progress = 0; + progress.iops = 0; + progress.bandwidth = 0; + progress.latency = 0; + } + + lastProgress = tick; +} + +} // namespace BIL diff --git a/hotness/SimpleSSD-Standalone/bil/entry.hh b/hotness/SimpleSSD-Standalone/bil/entry.hh new file mode 100644 index 0000000000..919c85c57a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bil/entry.hh @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_ENTRY__ +#define __BIL_ENTRY__ + +#include +#include +#include +#include + +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace BIL { + +class Scheduler; +class DriverInterface; + +enum BIO_TYPE : uint8_t { + BIO_READ, + BIO_WRITE, + BIO_FLUSH, + BIO_TRIM, + BIO_NUM, +}; + +typedef struct _BIO { + uint64_t id; + + // I/O definition + BIO_TYPE type; + uint64_t offset; + uint64_t length; + // I/O completion + std::function callback; + + // Statistics + uint64_t submittedAt; + int temperature; + _BIO() : id(0), type(BIO_READ), offset(0), length(0), submittedAt(0),temperature(1) {} +} BIO; + +typedef struct _Progress { + uint64_t iops; + uint64_t bandwidth; + uint64_t latency; +} Progress; + +class BlockIOEntry { + private: + ConfigReader &conf; + Engine &engine; + std::list ioQueue; + + std::ostream *pLatencyFile; + + Scheduler *pScheduler; + DriverInterface *pDriver; + + std::mutex m; + uint64_t lastProgress; + uint64_t io_progress; + Progress progress; + + // Statistics + uint64_t io_count; + uint64_t minLatency; + uint64_t maxLatency; + uint64_t sumLatency; + uint64_t squareSumLatency; + + std::function callback; + void completion(uint64_t); + + public: + BlockIOEntry(ConfigReader &, Engine &, DriverInterface *, std::ostream *); + ~BlockIOEntry(); + + void submitIO(BIO &); + + void printStats(std::ostream &); + void getProgress(Progress &); +}; + +} // namespace BIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/bil/interface.hh b/hotness/SimpleSSD-Standalone/bil/interface.hh new file mode 100644 index 0000000000..0db8d86a98 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bil/interface.hh @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_DRIVER_INTERFACE__ +#define __BIL_DRIVER_INTERFACE__ + +#include + +#include "bil/entry.hh" +#include "simplessd/sim/statistics.hh" + +namespace BIL { + +class DriverInterface { + protected: + Engine &engine; + + std::function beginFunction; + + public: + DriverInterface(Engine &e) : engine(e) {} + virtual ~DriverInterface() {} + + virtual void init(std::function &) = 0; + virtual void getInfo(uint64_t &, uint32_t &) = 0; + virtual void submitIO(BIO &) = 0; + + virtual void initStats(std::vector &) = 0; + virtual void getStats(std::vector &) = 0; +}; + +} // namespace BIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/bil/noop_scheduler.cc b/hotness/SimpleSSD-Standalone/bil/noop_scheduler.cc new file mode 100644 index 0000000000..1f45bb488f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bil/noop_scheduler.cc @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "bil/noop_scheduler.hh" + +namespace BIL { + +NoopScheduler::NoopScheduler(Engine &e, DriverInterface *i) : Scheduler(e, i) {} + +NoopScheduler::~NoopScheduler() {} + +void NoopScheduler::init() {} + +void NoopScheduler::submitIO(BIO &bio) { + pInterface->submitIO(bio); +} + +} // namespace BIL diff --git a/hotness/SimpleSSD-Standalone/bil/noop_scheduler.hh b/hotness/SimpleSSD-Standalone/bil/noop_scheduler.hh new file mode 100644 index 0000000000..814e385d8c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bil/noop_scheduler.hh @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_NOOP_SCHEDULER__ +#define __BIL_NOOP_SCHEDULER__ + +#include "bil/scheduler.hh" + +namespace BIL { + +class NoopScheduler : public Scheduler { + public: + NoopScheduler(Engine &, DriverInterface *); + ~NoopScheduler(); + + void init(); + void submitIO(BIO &); +}; + +} // namespace BIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/bil/scheduler.hh b/hotness/SimpleSSD-Standalone/bil/scheduler.hh new file mode 100644 index 0000000000..292b039a66 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/bil/scheduler.hh @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __BIL_SCHEDULER__ +#define __BIL_SCHEDULER__ + +#include "bil/interface.hh" + +namespace BIL { + +class Scheduler { + protected: + Engine &engine; + DriverInterface *pInterface; + + public: + Scheduler(Engine &e, DriverInterface *i) : engine(e), pInterface(i) {} + virtual ~Scheduler() {} + + virtual void init() = 0; + virtual void submitIO(BIO &) = 0; +}; + +} // namespace BIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/config/.DS_Store b/hotness/SimpleSSD-Standalone/config/.DS_Store new file mode 100644 index 0000000000..9f6a9077c9 Binary files /dev/null and b/hotness/SimpleSSD-Standalone/config/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/config/sample.cfg b/hotness/SimpleSSD-Standalone/config/sample.cfg new file mode 100644 index 0000000000..1099e75227 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/config/sample.cfg @@ -0,0 +1,246 @@ +# +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . +# + +# +# Sample SimpleSSD-Standalone Configuration File +# +# Section: +# global: Global options +# generator: Request generator configuration +# trace: Trace replayer configuration +# + +# Global Configuration +[global] + +## Select mode +# Possible values: +# 0: Request generator mode (all configs in [trace] will be ignored) +# 1: Trace replayer mode (all configs in [generator] will be ignored) +Mode = 1 + +## Statistic log period +# Print statistic log periodically +# 0 means no log printout +# Unit: ms (millisecond) in simulation time (not real time) +LogPeriod = 10 + +## Log file +# Set output path of statistic log and debug log +# means no log printout +# Possible keywords: +# STDOUT: Standard Output +# STDERR: Standard Error +LogFile = STDOUT +DebugLogFile = +#STDERR + +## I/O Log file +# Set output path of latency log +# means no log printout +LatencyLogFile = latency.log + +## Progress printout +# If both logs are printed to file (not screen) +# Event engine speed and simulation progress will be shown to STDOUT +# This option set the period of progress printout +# 0 means no log printout +# Unit: s (second) in host time (real time) +ProgressPeriod = 0 + +## Interface +# Set host interface to use +# Possible values: +# 0: No interface - directly send request to HIL layer +# 1: NVMe - Use Non-Volatile Memory Express +# 2: SATA - Use Serial AT Attachment +# 3: UFS - Use Universal Flash Storage +Interface = 0 + +## Scheduler +# Set scheduler to use in Block I/O Layer +# Possible values: +# 0: Noop - No scheduling +Scheduler = 0 + +## System latency +# Mimics I/O stack of real OSes by adding latency of software execution +SubmissionLatency = 0us +CompletionLatency = 0us + +# Request generator configuration +[generator] + +## This request generator will work similar to Flexible I/O tester +# Definition of Types: +# str: String, a sequence of alphanumeric characters +# int: SI integer, a sequence of numeric characters +# Possible suffix (case sensitive): +# 10^3 base: k, m, g, t +# 2^10 base: K, M, G, T +# float: Floating point number, a sequence of numeric characters +# with one (or none) of decimal point +# bool: Boolean, a true or false value. +# Possible value (case insensitive): +# True: Non-zero number, T, True, Y, Yes +# False: Otherwise +# time: SI integer, a sequenced of numeric characters +# If no suffix provided, value will treated as pico-second. +# Possible suffix (case sensitive): +# s, ms, us, ns, ps + +## Total size to I/O = int +# Only valid when time_based = false +io_size = 16M # 16 * 2^20 bytes + +## Type of I/O = str +# Possible values: +# read: Sequential read +# write: Sequential write +# randread: Random read +# randwrite: Random write +# readwrite: Mixed sequential I/O +# randrw: Mixed random I/O +readwrite = write +# 혼합 워크로드 , 수정 +rwmixread = 0.5 + +## Percentage of mixed I/O = float +# If readwrite is not readwrite nor randrw, this value will ignored +# 0 <= value <= 1 + +## Block size = int +blocksize = 4K + +## Block align = int +# Default is blocksize +blockalign = + +## I/O mode = str +# Possible values: +# sync: Synchronous I/O +# async: Asynchronous I/O +iomode = async + +## I/O depth = int +# iodepth = 1 when = sync +iodepth = 32 + +## Offset = int +offset = 0 + +## Size = int +# Default is [SSD size] - +size = + +## Thinktime = time +thinktime = 0 + +## Random seed = int +randseed = 13245 + +## Time based = bool +time_based = 0 + +## Runtime = time +# Only valid when time_based = true +runtime = 10s + +# Trace replayer configuration +[trace] +TraceFormat = Regex +#TokenSequence = Timestamp,BlockAddress,NumSectors,Operation +UseHexadecimal = false +File = ~/SimpleSSD-Standalone/traces/sa00_50M.csv + +## Timing option +# Possible values: +# 0: No timing constraint (Sync) +# I/O will issued synchronously with BreakSyncIO wait time +# 1: No timing constraint (Async) +# I/O will issued asynchronously with BreakAsyncIO wait time +# 2: Strict timing +# I/O will issued asynchronously at exact time of trace +TimingMode = 1 + +## Queue depth +# Maximum asynchronous I/O depth when using TimingMode = 1 +QueueDepth = 64 + +## Limit the number of I/O +# Set zero or leave empty to issue all I/O in the trace file +IOLimit = 0 + +## Trace file regular expression +# See C++11 Regular Expression Library +# Always use ECMAScript regular expression grammar +# Unmatched line will be ignored +# This example is for blkparse result + +Regex = "^\s*\d+,\d+\s+\d+\s+\d+\s+(\d+)\.(\d+)\s+\d+\s+[A-Z]\s+([A-Z]+)\s+(\d+)\s+\+\s+(\d+)\s+(-?\d+)\s*$" + + +## Trace file regular expression group ID +# Mapping field and group ID of parsed trace file +# = +# Field may empty +# All time field will be added up +# Group ID 0 is matched string (Do not use) +# All field (except operation) must contain integer (not floating point number) +# For operation, only first character of string will be used +# R for read, W for write, F for flush and T/D for trim +# Case-insensitive +# Example: RA (Read, Read-ahead in blkparse) +# Handled as read operation (R) +# Example: trim (Trim in fio iolog version 2) +# Handled as trim operation (T) +# Example: D (Trim in blkparse - Discard) +# Handled as trim operation (D) +# Example: FWFS (Flush, Write, FUA, SYNC in blkparse) +# Handled as flush operation (F) +Operation = 3 +ByteOffset = +ByteLength = +LBAOffset = 4 +LBALength = 5 +Second = 1 +Millisecond = +Microsecond = +Nanosecond = 2 +Picosecond = +Temperature = 6 + +## LBA size +# Set LBA size if LBA offset/length used +LBASize = 512 + +## Treat field (except time) as hexadecimal +# Double check that the regular expression captures hexadecimal number +UseHexadecimal = 0 + +#아래는 다 수정한 값 +[Statistics] +enable_block_io_stats = false +enable_block_erase_count_stats = true + + + +#enable_channel_io_stats = false +#enable_die_io_stats = false +#enable_plane_io_stats = false \ No newline at end of file diff --git a/hotness/SimpleSSD-Standalone/igl/.DS_Store b/hotness/SimpleSSD-Standalone/igl/.DS_Store new file mode 100644 index 0000000000..072b58b677 Binary files /dev/null and b/hotness/SimpleSSD-Standalone/igl/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/igl/io_gen.hh b/hotness/SimpleSSD-Standalone/igl/io_gen.hh new file mode 100644 index 0000000000..c9b6d63f0f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/io_gen.hh @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_IO_GEN__ +#define __IGL_IO_GEN__ + +#include "bil/entry.hh" +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace IGL { + +class IOGenerator { + protected: + Engine &engine; + BIL::BlockIOEntry &bioEntry; + std::function &endCallback; + + public: + IOGenerator(Engine &e, BIL::BlockIOEntry &b, std::function &c) + : engine(e), bioEntry(b), endCallback(c) {} + virtual ~IOGenerator() {} + + virtual void init(uint64_t, uint32_t) = 0; + virtual void begin() = 0; + virtual void printStats(std::ostream &) = 0; + virtual void getProgress(float &) = 0; +}; + +} // namespace IGL + +#endif diff --git a/hotness/SimpleSSD-Standalone/igl/request/request_config.cc b/hotness/SimpleSSD-Standalone/igl/request/request_config.cc new file mode 100644 index 0000000000..e544c7af73 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/request/request_config.cc @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/request/request_config.hh" + +#include "simplessd/sim/trace.hh" +#include "util/convert.hh" + +namespace IGL { + +const char NAME_IO_SIZE[] = "io_size"; +const char NAME_IO_TYPE[] = "readwrite"; +const char NAME_IO_MIX_RATIO[] = "rwmixread"; +const char NAME_BLOCK_SIZE[] = "blocksize"; +const char NAME_BLOCK_ALIGN[] = "blockalign"; +const char NAME_IO_MODE[] = "iomode"; +const char NAME_IO_DEPTH[] = "iodepth"; +const char NAME_OFFSET[] = "offset"; +const char NAME_SIZE[] = "size"; +const char NAME_THINKTIME[] = "thinktime"; +const char NAME_RANDOM_SEED[] = "randseed"; +const char NAME_TIME_BASED[] = "time_based"; +const char NAME_RUN_TIME[] = "runtime"; + +RequestConfig::RequestConfig() { + io_size = 0; + type = IO_READ; + rwmixread = 0; + blocksize = 0; + blockalign = 0; + mode = IO_SYNC; + iodepth = 0; + offset = 0; + size = 0; + thinktime = 0; + randseed = 0; + time_based = false; + runtime = 0; +} + +bool RequestConfig::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_IO_SIZE)) { + io_size = convertInteger(value); + } + else if (MATCH_NAME(NAME_IO_TYPE)) { + if (strcasecmp(value, "read") == 0) { + type = IO_READ; + } + else if (strcasecmp(value, "write") == 0) { + type = IO_WRITE; + } + else if (strcasecmp(value, "randread") == 0) { + type = IO_RANDREAD; + } + else if (strcasecmp(value, "randwrite") == 0) { + type = IO_RANDWRITE; + } + else if (strcasecmp(value, "readwrite") == 0) { + type = IO_READWRITE; + } + else if (strcasecmp(value, "randrw") == 0) { + type = IO_RANDRW; + } + else { + type = IO_TYPE_NUM; + } + } + else if (MATCH_NAME(NAME_IO_MIX_RATIO)) { + rwmixread = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_BLOCK_SIZE)) { + blocksize = convertInteger(value); + } + else if (MATCH_NAME(NAME_BLOCK_ALIGN)) { + blockalign = convertInteger(value); + } + else if (MATCH_NAME(NAME_IO_MODE)) { + if (strcasecmp(value, "sync") == 0) { + mode = IO_SYNC; + } + else if (strcasecmp(value, "async") == 0) { + mode = IO_ASYNC; + } + else { + mode = IO_MODE_NUM; + } + } + else if (MATCH_NAME(NAME_IO_DEPTH)) { + iodepth = convertInteger(value); + } + else if (MATCH_NAME(NAME_OFFSET)) { + offset = convertInteger(value); + } + else if (MATCH_NAME(NAME_SIZE)) { + size = convertInteger(value); + } + else if (MATCH_NAME(NAME_THINKTIME)) { + thinktime = convertInteger(value); + } + else if (MATCH_NAME(NAME_RANDOM_SEED)) { + randseed = convertInteger(value); + } + else if (MATCH_NAME(NAME_TIME_BASED)) { + time_based = convertBoolean(value); + } + else if (MATCH_NAME(NAME_RUN_TIME)) { + runtime = convertTime(value); + } + else { + ret = false; + } + + return ret; +} + +void RequestConfig::update() { + if (type == IO_TYPE_NUM) { + SimpleSSD::panic("Invalid value of readwrite"); + } + if (mode == IO_MODE_NUM) { + SimpleSSD::panic("Invalid value of iomode"); + } + if (rwmixread < 0 || rwmixread > 1) { + SimpleSSD::panic("Invalid value of rwmixread"); + } +} + +uint64_t RequestConfig::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case REQUEST_IO_SIZE: + ret = io_size; + break; + case REQUEST_IO_TYPE: + ret = type; + break; + case REQUEST_BLOCK_SIZE: + ret = blocksize; + break; + case REQUEST_BLOCK_ALIGN: + ret = blockalign; + break; + case REQUEST_IO_MODE: + ret = mode; + break; + case REQUEST_IO_DEPTH: + ret = iodepth; + break; + case REQUEST_OFFSET: + ret = offset; + break; + case REQUEST_SIZE: + ret = size; + break; + case REQUEST_THINKTIME: + ret = thinktime; + break; + case REQUEST_RANDOM_SEED: + ret = randseed; + break; + case REQUEST_RUN_TIME: + ret = runtime; + break; + } + + return ret; +} + +float RequestConfig::readFloat(uint32_t idx) { + float ret = 0.f; + + switch (idx) { + case REQUEST_IO_MIX_RATIO: + ret = rwmixread; + break; + } + + return ret; +} + +bool RequestConfig::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case REQUEST_TIME_BASED: + ret = time_based; + break; + } + + return ret; +} + +} // namespace IGL diff --git a/hotness/SimpleSSD-Standalone/igl/request/request_config.hh b/hotness/SimpleSSD-Standalone/igl/request/request_config.hh new file mode 100644 index 0000000000..bd9571f721 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/request/request_config.hh @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_REQUEST_CONFIG__ +#define __IGL_REQUEST_CONFIG__ + +#include "simplessd/sim/base_config.hh" + +namespace IGL { + +typedef enum { + REQUEST_IO_SIZE, + REQUEST_IO_TYPE, + REQUEST_IO_MIX_RATIO, + REQUEST_BLOCK_SIZE, + REQUEST_BLOCK_ALIGN, + REQUEST_IO_MODE, + REQUEST_IO_DEPTH, + REQUEST_OFFSET, + REQUEST_SIZE, + REQUEST_THINKTIME, + REQUEST_RANDOM_SEED, + REQUEST_TIME_BASED, + REQUEST_RUN_TIME, +} REQUEST_CONFIG; + +typedef enum { + IO_READ, + IO_WRITE, + IO_RANDREAD, + IO_RANDWRITE, + IO_READWRITE, + IO_RANDRW, + IO_TYPE_NUM, +} IO_TYPE; + +typedef enum { + IO_SYNC, + IO_ASYNC, + IO_MODE_NUM, +} IO_MODE; + +class RequestConfig : public SimpleSSD::BaseConfig { + private: + uint64_t io_size; + IO_TYPE type; + float rwmixread; + uint64_t blocksize; + uint64_t blockalign; + IO_MODE mode; + uint64_t iodepth; + uint64_t offset; + uint64_t size; + uint64_t thinktime; + uint64_t randseed; + bool time_based; + uint64_t runtime; + + public: + RequestConfig(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; + float readFloat(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace IGL + +#endif diff --git a/hotness/SimpleSSD-Standalone/igl/request/request_generator.cc b/hotness/SimpleSSD-Standalone/igl/request/request_generator.cc new file mode 100644 index 0000000000..0724cda972 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/request/request_generator.cc @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/request/request_generator.hh" + +#include + +#include "simplessd/sim/trace.hh" +#include "simplessd/util/algorithm.hh" + +namespace IGL { + +RequestGenerator::RequestGenerator(Engine &e, BIL::BlockIOEntry &b, + std::function &f, ConfigReader &c) + : IOGenerator(e, b, f), + io_submitted(0), + io_count(0), + read_count(0), + io_depth(0), + reserveTermination(false) { + // Read config + io_size = c.readUint(CONFIG_REQ_GEN, REQUEST_IO_SIZE); + type = (IO_TYPE)c.readUint(CONFIG_REQ_GEN, REQUEST_IO_TYPE); + mode = (IO_MODE)c.readUint(CONFIG_REQ_GEN, REQUEST_IO_MODE); + iodepth = c.readUint(CONFIG_REQ_GEN, REQUEST_IO_DEPTH); + rwmixread = c.readFloat(CONFIG_REQ_GEN, REQUEST_IO_MIX_RATIO); + offset = c.readUint(CONFIG_REQ_GEN, REQUEST_OFFSET); + size = c.readUint(CONFIG_REQ_GEN, REQUEST_SIZE); + thinktime = c.readUint(CONFIG_REQ_GEN, REQUEST_THINKTIME); + blocksize = c.readUint(CONFIG_REQ_GEN, REQUEST_BLOCK_SIZE); + blockalign = c.readUint(CONFIG_REQ_GEN, REQUEST_BLOCK_ALIGN); + randseed = c.readUint(CONFIG_REQ_GEN, REQUEST_RANDOM_SEED); + time_based = c.readBoolean(CONFIG_REQ_GEN, REQUEST_TIME_BASED); + runtime = c.readUint(CONFIG_REQ_GEN, REQUEST_RUN_TIME); + + if (blockalign == 0) { + blockalign = blocksize; + } + + if (mode == IO_SYNC) { + iodepth = 1; + mode = IO_ASYNC; + } + + submissionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_SUBMISSION_LATENCY); + completionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_COMPLETION_LATENCY); + + // Set random engine + randengine.seed(randseed); + + submitIO = [this](uint64_t tick) { _submitIO(tick); }; + iocallback = [this](uint64_t id) { _iocallback(id); }; + + submitEvent = engine.allocateEvent(submitIO); +} + +RequestGenerator::~RequestGenerator() {} + +void RequestGenerator::init(uint64_t bytesize, uint32_t bs) { + if (offset > bytesize) { + SimpleSSD::panic("offset is larger than SSD size"); + } + if (blocksize < bs) { + SimpleSSD::panic("blocksize is smaller than SSD's logical block"); + } + if (blockalign < bs) { + SimpleSSD::panic("blockalign is smaller than SSD's logical block"); + } + if (blocksize % bs != 0) { + SimpleSSD::warn("blocksize is not aligned to SSD's logical block"); + + blocksize /= bs; + blocksize *= bs; + } + if (blockalign % bs != 0) { + SimpleSSD::warn("blockalign is not aligned to SSD's logical block"); + + blockalign /= bs; + blockalign *= bs; + } + if (offset % blockalign != 0) { + SimpleSSD::warn("offset is not aligned to blockalign"); + + offset /= blockalign; + offset *= blockalign; + } + if (size == 0 || offset + size > bytesize) { + size = bytesize - offset; + } + if (size == 0) { + SimpleSSD::panic("Invalid offset and size provided"); + } + + randgen = std::uniform_int_distribution(offset, offset + size); +} + +void RequestGenerator::begin() { + initTime = engine.getCurrentTick(); + + _submitIO(initTime); +} + +void RequestGenerator::printStats(std::ostream &out) { + uint64_t tick = engine.getCurrentTick(); + + out << "*** Statistics of Request Generator ***" << std::endl; + out << "Tick: " << tick << std::endl; + out << "Time (ps): " << initTime << " - " << tick << " (" << tick - initTime + << ")" << std::endl; + out << "I/O (bytes): " << io_submitted << " (" + << std::to_string((double)io_submitted / (tick - initTime) * + 1000000000000.) + << " B/s)" << std::endl; + out << "I/O (counts): " << io_count << " (Read: " << read_count + << ", Write: " << io_count - read_count << ")" << std::endl; + out << "*** End of statistics ***" << std::endl; + + bioEntry.printStats(out); +} + +void RequestGenerator::getProgress(float &val) { + bool zero = false; + + { + std::lock_guard guard(m); + + if (io_submitted == 0) { + zero = true; + } + } + + if (zero) { + val = 0.f; + + return; + } + + if (time_based) { // Read-only variable after init + uint64_t tick = engine.getCurrentTick(); // Thread-safe + + // initTime is read-only after begin() called + val = (float)(tick - initTime) / runtime; + } + else { + std::lock_guard guard(m); + + val = (float)io_submitted / io_size; + } +} + +void RequestGenerator::generateAddress(uint64_t &off, uint64_t &len) { + // This function generates address to access + // based on I/O type, blocksize/align and offset/size + if (type == IO_RANDREAD || type == IO_RANDWRITE || type == IO_RANDRW) { + off = randgen(randengine); // randgen range: [offset, offset + size) + off -= off % blockalign; + len = blocksize; + } + else { + off = io_count * blockalign; + len = blocksize; + + // Limit range of address to [offset, offset + size) + while (off + len > size) { + if (off >= size) { + off -= size; + } + else { + // TODO: is this correct? + off -= len; + } + } + + off += offset; + } +} + +bool RequestGenerator::nextIOIsRead() { + // This function determine next I/O is read or write + // based on rwmixread + // io_count should not zero + if (type == IO_READWRITE || type == IO_RANDRW) { + if (rwmixread > (float)read_count / io_count) { + return true; + } + } + else if (type == IO_READ || type == IO_RANDREAD) { + return true; + } + + return false; +} + +void RequestGenerator::_submitIO(uint64_t) { + BIL::BIO bio; + + // This function uses io_count (=0 at very beginning) + generateAddress(bio.offset, bio.length); + + bio.id = io_count++; + + // This function also uses io_count (=1 at very beginning) + if (nextIOIsRead()) { + bio.type = BIL::BIO_READ; + read_count++; + } + else { + bio.type = BIL::BIO_WRITE; + } + + io_submitted += bio.length; + + bio.callback = iocallback; + + // push to queue + io_depth++; + + // Submit to Block I/O entry + bioEntry.submitIO(bio); + + // Check on-the-fly I/O depth + rescheduleSubmit(submissionLatency); +} + +void RequestGenerator::_iocallback(uint64_t) { + io_depth--; + + if (reserveTermination) { + // No I/O will be generated anymore + // If no pending I/O call endCallback + if (io_depth == 0) { + endCallback(); + } + } + else { + // Check on-the-fly I/O depth + rescheduleSubmit(submissionLatency + completionLatency); + } +} + +void RequestGenerator::rescheduleSubmit(uint64_t breakTime) { + uint64_t tick = engine.getCurrentTick(); + + // We are done + if ((!time_based && io_submitted >= io_size) || + (time_based && runtime <= (tick - initTime))) { + reserveTermination = true; + + // We need to double-check this for following case: + // _iocallback (all I/O completed) -> rescheduleSubmit + if (io_depth == 0) { + endCallback(); + } + + return; + } + + if (io_depth < iodepth) { + uint64_t scheduledTick; + bool doSchedule = true; + + // Check conflict + if (engine.isScheduled(submitEvent, &scheduledTick)) { + if (scheduledTick >= tick + breakTime) { + doSchedule = false; + } + } + + // We can schedule it + if (doSchedule) { + engine.scheduleEvent(submitEvent, tick + breakTime); + } + } +} + +} // namespace IGL diff --git a/hotness/SimpleSSD-Standalone/igl/request/request_generator.hh b/hotness/SimpleSSD-Standalone/igl/request/request_generator.hh new file mode 100644 index 0000000000..bebf3bec6c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/request/request_generator.hh @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_REQUEST_GENERATOR__ +#define __IGL_REQUEST_GENERATOR__ + +#include +#include +#include +#include + +#include "bil/entry.hh" +#include "igl/io_gen.hh" +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace IGL { + +class RequestGenerator : public IOGenerator { + private: + std::mutex m; + + uint64_t io_size; + uint64_t io_submitted; + + IO_TYPE type; + + IO_MODE mode; + uint64_t iodepth; + + uint64_t io_count; + uint64_t read_count; + float rwmixread; + + uint64_t offset; + uint64_t size; + + uint64_t thinktime; + + uint64_t blocksize; + uint64_t blockalign; + + uint64_t randseed; + std::mt19937_64 randengine; + std::uniform_int_distribution randgen; + + bool time_based; + uint64_t runtime; + + uint64_t submissionLatency; + uint64_t completionLatency; + + uint64_t io_depth; + + uint64_t initTime; + bool reserveTermination; + + void generateAddress(uint64_t &, uint64_t &); + bool nextIOIsRead(); + void rescheduleSubmit(uint64_t); + + SimpleSSD::Event submitEvent; + SimpleSSD::EventFunction submitIO; + SimpleSSD::EventFunction iocallback; + + void _submitIO(uint64_t); + void _iocallback(uint64_t); + + public: + RequestGenerator(Engine &, BIL::BlockIOEntry &, std::function &, + ConfigReader &); + ~RequestGenerator(); + + void init(uint64_t, uint32_t) override; + void begin() override; + void printStats(std::ostream &) override; + void getProgress(float &) override; +}; + +} // namespace IGL + +#endif diff --git a/hotness/SimpleSSD-Standalone/igl/trace/trace_config.cc b/hotness/SimpleSSD-Standalone/igl/trace/trace_config.cc new file mode 100644 index 0000000000..ef479d91e3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/trace/trace_config.cc @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/trace/trace_config.hh" + +#include "simplessd/sim/trace.hh" + +namespace IGL { + +const char NAME_FILE[] = "File"; +const char NAME_TIMING_MODE[] = "TimingMode"; +const char NAME_QUEUE_DEPTH[] = "QueueDepth"; +const char NAME_IO_LIMIT[] = "IOLimit"; +const char NAME_LINE_REGEX[] = "Regex"; +const char NAME_GROUP_OPERATION[] = "Operation"; +const char NAME_GROUP_BYTE_OFFSET[] = "ByteOffset"; +const char NAME_GROUP_BYTE_LENGTH[] = "ByteLength"; +const char NAME_GROUP_LBA_OFFSET[] = "LBAOffset"; +const char NAME_GROUP_LBA_LENGTH[] = "LBALength"; +const char NAME_GROUP_SEC[] = "Second"; +const char NAME_GROUP_MILI_SEC[] = "Millisecond"; +const char NAME_GROUP_MICRO_SEC[] = "Microsecond"; +const char NAME_GROUP_NANO_SEC[] = "Nanosecond"; +const char NAME_GROUP_PICO_SEC[] = "Picosecond"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_USE_HEX[] = "UseHexadecimal"; + +TraceConfig::TraceConfig() { + mode = MODE_SYNC; + queueDepth = 1; + iolimit = 0; + groupOperation = 0; + groupByteOffset = 0; + groupByteLength = 0; + groupLBAOffset = 0; + groupLBALength = 0; + groupSecond = 0; + groupMiliSecond = 0; + groupMicroSecond = 0; + groupNanoSecond = 0; + groupPicoSecond = 0; + lbaSize = 512; + useHexadecimal = false; +} + +bool TraceConfig::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_FILE)) { + file = value; + } + else if (MATCH_NAME(NAME_TIMING_MODE)) { + mode = (TIMING_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_QUEUE_DEPTH)) { + queueDepth = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_IO_LIMIT)) { + iolimit = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LINE_REGEX)) { + regex = value; + } + else if (MATCH_NAME(NAME_GROUP_OPERATION)) { + groupOperation = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_BYTE_OFFSET)) { + groupByteOffset = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_BYTE_LENGTH)) { + groupByteLength = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_LBA_OFFSET)) { + groupLBAOffset = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_LBA_LENGTH)) { + groupLBALength = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_SEC)) { + groupSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_MILI_SEC)) { + groupMiliSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_MICRO_SEC)) { + groupMicroSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_NANO_SEC)) { + groupNanoSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GROUP_PICO_SEC)) { + groupPicoSecond = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_USE_HEX)) { + useHexadecimal = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void TraceConfig::update() { + uint64_t idx = 0; + + // Remove leading spaces + for (auto c : regex) { + if (c != ' ') { + break; + } + + idx++; + } + + // Check double quotes + if (regex[0] == '"') { + regex = regex.substr(idx + 1); + } + else { + regex = regex.substr(idx); + } + + // Remove trailing spaces + while (regex.back() == ' ') { + regex.pop_back(); + } + + if (regex.back() == '"') { + regex.pop_back(); + } + + if (mode >= MODE_NUM) { + SimpleSSD::panic("Invalid timing mode specified"); + } +} + +uint64_t TraceConfig::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case TRACE_TIMING_MODE: + ret = mode; + break; + case TRACE_QUEUE_DEPTH: + ret = queueDepth; + break; + case TRACE_IO_LIMIT: + ret = iolimit; + break; + case TRACE_GROUP_OPERATION: + ret = groupOperation; + break; + case TRACE_GROUP_BYTE_OFFSET: + ret = groupByteOffset; + break; + case TRACE_GROUP_BYTE_LENGTH: + ret = groupByteLength; + break; + case TRACE_GROUP_LBA_OFFSET: + ret = groupLBAOffset; + break; + case TRACE_GROUP_LBA_LENGTH: + ret = groupLBALength; + break; + case TRACE_GROUP_SEC: + ret = groupSecond; + break; + case TRACE_GROUP_MILI_SEC: + ret = groupMiliSecond; + break; + case TRACE_GROUP_MICRO_SEC: + ret = groupMicroSecond; + break; + case TRACE_GROUP_NANO_SEC: + ret = groupNanoSecond; + break; + case TRACE_GROUP_PICO_SEC: + ret = groupPicoSecond; + break; + case TRACE_LBA_SIZE: + ret = lbaSize; + break; + } + + return ret; +} + +std::string TraceConfig::readString(uint32_t idx) { + std::string ret = ""; + + switch (idx) { + case TRACE_FILE: + ret = file; + break; + case TRACE_LINE_REGEX: + ret = regex; + break; + } + + return ret; +} + +bool TraceConfig::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case TRACE_USE_HEX: + ret = useHexadecimal; + break; + } + + return ret; +} + +} // namespace IGL diff --git a/hotness/SimpleSSD-Standalone/igl/trace/trace_config.hh b/hotness/SimpleSSD-Standalone/igl/trace/trace_config.hh new file mode 100644 index 0000000000..a8159b2fd6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/trace/trace_config.hh @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_TRACE_CONFIG__ +#define __IGL_TRACE_CONFIG__ + +#include "simplessd/sim/base_config.hh" + +namespace IGL { + +typedef enum { + TRACE_FILE, + TRACE_TIMING_MODE, + TRACE_QUEUE_DEPTH, + TRACE_IO_LIMIT, + TRACE_LINE_REGEX, + TRACE_GROUP_OPERATION, + TRACE_GROUP_BYTE_OFFSET, + TRACE_GROUP_BYTE_LENGTH, + TRACE_GROUP_LBA_OFFSET, + TRACE_GROUP_LBA_LENGTH, + TRACE_GROUP_SEC, + TRACE_GROUP_MILI_SEC, + TRACE_GROUP_MICRO_SEC, + TRACE_GROUP_NANO_SEC, + TRACE_GROUP_PICO_SEC, + TRACE_LBA_SIZE, + TRACE_USE_HEX, + TRACE_GROUP_TEMPERATURE +} TRACE_CONFIG; + +typedef enum { + MODE_SYNC, + MODE_ASYNC, + MODE_STRICT, + MODE_NUM, +} TIMING_MODE; + +class TraceConfig : public SimpleSSD::BaseConfig { + private: + std::string file; + TIMING_MODE mode; + uint32_t queueDepth; + uint64_t iolimit; + std::string regex; + uint32_t groupOperation; + uint32_t groupByteOffset; + uint32_t groupByteLength; + uint32_t groupLBAOffset; + uint32_t groupLBALength; + uint32_t groupSecond; + uint32_t groupMiliSecond; + uint32_t groupMicroSecond; + uint32_t groupNanoSecond; + uint32_t groupPicoSecond; + uint32_t lbaSize; + bool useHexadecimal; + + public: + TraceConfig(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace IGL + +#endif diff --git a/hotness/SimpleSSD-Standalone/igl/trace/trace_replayer.cc b/hotness/SimpleSSD-Standalone/igl/trace/trace_replayer.cc new file mode 100644 index 0000000000..f83f7a787d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/trace/trace_replayer.cc @@ -0,0 +1,443 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "igl/trace/trace_replayer.hh" +#include +#include + +#include "simplessd/sim/trace.hh" +#include "simplessd/util/algorithm.hh" + +namespace IGL { + +TraceReplayer::TraceReplayer(Engine &e, BIL::BlockIOEntry &b, + std::function &f, ConfigReader &c) + : IOGenerator(e, b, f), + useLBAOffset(false), + useLBALength(false), + nextIOIsSync(false), + reserveTermination(false), + io_submitted(0), + io_count(0), + read_count(0), + write_count(0), + io_depth(0) { + // Check file + auto filename = c.readString(CONFIG_TRACE, TRACE_FILE); + file.open(filename); + + if (!file.is_open()) { + SimpleSSD::panic("Failed to open trace file %s!", filename.c_str()); + } + + file.seekg(0, std::ios::end); + fileSize = file.tellg(); + file.seekg(0, std::ios::beg); + + // Create regex + try { + regex = std::regex(c.readString(CONFIG_TRACE, TRACE_LINE_REGEX)); + } + catch (std::regex_error &e) { + SimpleSSD::panic("Invalid regular expression!"); + } + + // Fill flags + mode = (TIMING_MODE)c.readUint(CONFIG_TRACE, TRACE_TIMING_MODE); + submissionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_SUBMISSION_LATENCY); + completionLatency = c.readUint(CONFIG_GLOBAL, GLOBAL_COMPLETION_LATENCY); + maxQueueDepth = c.readUint(CONFIG_TRACE, TRACE_QUEUE_DEPTH); + max_io = c.readUint(CONFIG_TRACE, TRACE_IO_LIMIT); + groupID[ID_OPERATION] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_OPERATION); + groupID[ID_BYTE_OFFSET] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_BYTE_OFFSET); + groupID[ID_BYTE_LENGTH] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_BYTE_LENGTH); + groupID[ID_LBA_OFFSET] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_LBA_OFFSET); + groupID[ID_LBA_LENGTH] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_LBA_LENGTH); + groupID[ID_TIME_SEC] = (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_SEC); + groupID[ID_TIME_MS] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_MILI_SEC); + groupID[ID_TIME_US] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_MICRO_SEC); + groupID[ID_TIME_NS] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_NANO_SEC); + groupID[ID_TIME_PS] = + (uint32_t)c.readUint(CONFIG_TRACE, TRACE_GROUP_PICO_SEC); + groupID[ID_TEMPERATURE] = 6; + useHex = c.readBoolean(CONFIG_TRACE, TRACE_USE_HEX); + if (groupID[ID_OPERATION] == 0) { + SimpleSSD::panic("Operation group ID cannot be 0"); + } + + if (groupID[ID_LBA_OFFSET] > 0) { + useLBAOffset = true; + } + if (groupID[ID_LBA_LENGTH] > 0) { + useLBALength = true; + } + + if (useLBALength || useLBAOffset) { + lbaSize = (uint32_t)c.readUint(CONFIG_TRACE, TRACE_LBA_SIZE); + + if (SimpleSSD::popcount(lbaSize) != 1) { + SimpleSSD::panic("LBA size should be power of 2"); + } + } + + if (!useLBAOffset && groupID[ID_BYTE_OFFSET] == 0) { + SimpleSSD::panic("Both LBA Offset and Byte Offset group ID cannot be 0"); + } + if (!useLBALength && groupID[ID_BYTE_LENGTH] == 0) { + SimpleSSD::panic("Both LBA Length and Byte Length group ID cannot be 0"); + } + + timeValids[0] = groupID[ID_TIME_SEC] > 0 ? true : false; + timeValids[1] = groupID[ID_TIME_MS] > 0 ? true : false; + timeValids[2] = groupID[ID_TIME_US] > 0 ? true : false; + timeValids[3] = groupID[ID_TIME_NS] > 0 ? true : false; + timeValids[4] = groupID[ID_TIME_PS] > 0 ? true : false; + + if (!(timeValids[0] || timeValids[1] || timeValids[2] || timeValids[3] || + timeValids[4])) { + if (mode == MODE_STRICT) { + SimpleSSD::panic("No valid time field specified"); + } + } + + firstTick = std::numeric_limits::max(); + + completionEvent = [this](uint64_t id) { iocallback(id); }; + + submitEvent = engine.allocateEvent([this](uint64_t) { submitIO(); }); +} + +TraceReplayer::~TraceReplayer() { + file.close(); +} + +void TraceReplayer::init(uint64_t bytesize, uint32_t bs) { + ssdSize = bytesize; + blocksize = bs; + + if ((useLBALength || useLBAOffset) && lbaSize < bs) { + SimpleSSD::warn("LBA size of trace file is smaller than SSD's LBA size"); + } +} + +void TraceReplayer::begin() { + initTime = engine.getCurrentTick(); + + parseLine(); + + if (mode == MODE_STRICT) { + firstTick = linedata.tick; + } + else { + firstTick = initTime; + } + + if (reserveTermination) { + SimpleSSD::warn("No I/O submitted. Check regular expression."); + + endCallback(); + } + else { + submitIO(); + } +} + +void TraceReplayer::printStats(std::ostream &out) { + uint64_t tick = engine.getCurrentTick(); + + out << "*** Statistics of Trace Replayer ***" << std::endl; + out << "Tick: " << tick << std::endl; + out << "Time (ps): " << firstTick - initTime << " - " << tick << " (" + << tick + firstTick - initTime << ")" << std::endl; + out << "I/O (bytes): " << io_submitted << " (" + << std::to_string((double)io_submitted / tick * 1000000000000.) << " B/s)" + << std::endl; + out << "I/O (counts): " << io_count << " (Read: " << read_count + << ", Write: " << write_count << ")" << std::endl; + out << "*** End of statistics ***" << std::endl; + + bioEntry.printStats(out); +} + +void TraceReplayer::getProgress(float &val) { + if (max_io == 0) { + // If I/O count is unlimited, use file pointer for fast progress calculation + uint64_t ptr; + + { + std::lock_guard guard(m); + ptr = file.tellg(); + } + + val = (float)ptr / fileSize; + } + else { + // Use submitted I/O count in progress calculation + // If trace file contains I/O requests smaller than max_io, progress value + // cannot reach 1.0 (100%) + val = (float)io_count / max_io; + } +} + +uint64_t TraceReplayer::mergeTime(std::smatch &match) { + uint64_t tick = 0; + bool valid = true; + + if (timeValids[0] && match.size() > groupID[ID_TIME_SEC]) { + tick += strtoul(match[groupID[ID_TIME_SEC]].str().c_str(), nullptr, 10) * + 1000000000000ULL; + } + else if (timeValids[0]) { + valid = false; + } + + if (timeValids[1] && match.size() > groupID[ID_TIME_MS]) { + tick += strtoul(match[groupID[ID_TIME_MS]].str().c_str(), nullptr, 10) * + 1000000000ULL; + } + else if (timeValids[1]) { + valid = false; + } + + if (timeValids[2] && match.size() > groupID[ID_TIME_US]) { + tick += strtoul(match[groupID[ID_TIME_US]].str().c_str(), nullptr, 10) * + 1000000ULL; + } + else if (timeValids[2]) { + valid = false; + } + + if (timeValids[3] && match.size() > groupID[ID_TIME_NS]) { + tick += strtoul(match[groupID[ID_TIME_NS]].str().c_str(), nullptr, 10) * + 1000ULL; + } + else if (timeValids[3]) { + valid = false; + } + + if (timeValids[4] && match.size() > groupID[ID_TIME_PS]) { + tick += strtoul(match[groupID[ID_TIME_PS]].str().c_str(), nullptr, 10); + } + else if (timeValids[4]) { + valid = false; + } + + if (!valid) { + SimpleSSD::panic("Time parse failed"); + } + + return tick; +} + +BIL::BIO_TYPE TraceReplayer::getType(std::string type) { + io_count++; + + switch (type[0]) { + case 'r': + case 'R': + read_count++; + + return BIL::BIO_READ; + case 'w': + case 'W': + write_count++; + + return BIL::BIO_WRITE; + case 'f': + case 'F': + return BIL::BIO_FLUSH; + case 't': + case 'T': + case 'd': + case 'D': + return BIL::BIO_TRIM; + } + + return BIL::BIO_NUM; +} + +void TraceReplayer::parseLine() { + std::string line; + std::smatch match; + + // Read line + while (true) { + bool eof = false; + + { + std::lock_guard guard(m); + + eof = file.eof(); + std::getline(file, line); + } + + if (eof) { + reserveTermination = true; + + if (io_depth == 0) { + // No on-the-fly I/O + endCallback(); + } + + return; + } + if (std::regex_match(line, match, regex)) { + break; + } + } + + // Get time + linedata.tick = mergeTime(match); + + // Fill BIO + if (useLBAOffset) { + linedata.offset = strtoul(match[groupID[ID_LBA_OFFSET]].str().c_str(), + nullptr, useHex ? 16 : 10) * + lbaSize; + } + else { + linedata.offset = strtoul(match[groupID[ID_BYTE_OFFSET]].str().c_str(), + nullptr, useHex ? 16 : 10); + } + + if (useLBALength) { + linedata.length = strtoul(match[groupID[ID_LBA_LENGTH]].str().c_str(), + nullptr, useHex ? 16 : 10) * + lbaSize; + } + else { + linedata.length = strtoul(match[groupID[ID_BYTE_LENGTH]].str().c_str(), + nullptr, useHex ? 16 : 10); + } + + // This function increases I/O count + linedata.type = getType(match[groupID[ID_OPERATION]].str()); + +/* if (groupID[ID_TEMPERATURE] > 0 && match.size() > groupID[ID_TEMPERATURE]) { + linedata.temperature = std::stoi(match[groupID[ID_TEMPERATURE]]); + } else { + linedata.temperature = 1; // 기본값: medium + } */ + +int temp_raw = 1; // 기본값 +if (groupID[ID_TEMPERATURE] > 0 && match.size() > groupID[ID_TEMPERATURE]) { + const std::string s = match[groupID[ID_TEMPERATURE]].str(); + char* end = nullptr; + long v = std::strtol(s.c_str(), &end, 10); + if (end != s.c_str() && *end == '\0') { + temp_raw = static_cast(v); + } else { + // 헤더("Hotness_Label") 등 비숫자면 기본값 유지(원하면 경고 로그) + } +} +// 온도 대입 직후 + linedata.temperature = temp_raw; +// after: linedata.temperature = temp_raw; + +} + +void TraceReplayer::submitIO() { + BIL::BIO bio; + + if (linedata.type == BIL::BIO_NUM) { + SimpleSSD::panic("Unexpected request type."); + } + + bio.callback = completionEvent; + bio.id = io_count; + bio.type = linedata.type; + bio.offset = linedata.offset; + bio.length = linedata.length; + bio.temperature = linedata.temperature; + + bioEntry.submitIO(bio); + //추가 + io_submitted += bio.length; + + io_depth++; + + if ((max_io != 0 && io_count >= max_io)) { + reserveTermination = true; + + return; + } + + parseLine(); + + if (reserveTermination) { + return; + } + + switch (mode) { + case MODE_STRICT: + engine.scheduleEvent(submitEvent, linedata.tick - firstTick + initTime); + break; + case MODE_ASYNC: + rescheduleSubmit(submissionLatency); + break; + default: + break; + } + + +} + +void TraceReplayer::iocallback(uint64_t) { + io_depth--; + + if (reserveTermination) { + // Everything is done + if (io_depth == 0) { + endCallback(); + } + } + + if (mode == MODE_SYNC || nextIOIsSync) { + // MODE_ASYNC submission blocked by I/O depth limitation + // Let's submit here + nextIOIsSync = false; + + rescheduleSubmit(submissionLatency + completionLatency); + } +} + +void TraceReplayer::rescheduleSubmit(uint64_t breakTime) { + if (mode == MODE_ASYNC) { + if (io_depth >= maxQueueDepth) { + nextIOIsSync = true; + + return; + } + } + else if (mode == MODE_STRICT) { + return; + } + + engine.scheduleEvent(submitEvent, engine.getCurrentTick() + breakTime); +} + +} // namespace IGL diff --git a/hotness/SimpleSSD-Standalone/igl/trace/trace_replayer.hh b/hotness/SimpleSSD-Standalone/igl/trace/trace_replayer.hh new file mode 100644 index 0000000000..8b669ac4d4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/igl/trace/trace_replayer.hh @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __IGL_TRACE_REPLAYER__ +#define __IGL_TRACE_REPLAYER__ + +#include +#include +#include +#include +#include + +#include "bil/entry.hh" +#include "igl/io_gen.hh" +#include "sim/cfg_reader.hh" +#include "sim/engine.hh" + +namespace IGL { + +class TraceReplayer : public IOGenerator { + private: + enum { + ID_OPERATION, + ID_BYTE_OFFSET, + ID_BYTE_LENGTH, + ID_LBA_OFFSET, + ID_LBA_LENGTH, + ID_TIME_SEC, + ID_TIME_MS, + ID_TIME_US, + ID_TIME_NS, + ID_TIME_PS, + ID_TEMPERATURE, + ID_NUM + }; + + std::mutex m; + + std::ifstream file; + std::regex regex; + + uint64_t fileSize; + + TIMING_MODE mode; + uint64_t submissionLatency; + uint64_t completionLatency; + uint32_t maxQueueDepth; // Only used in MODE_ASYNC + uint32_t groupID[ID_NUM]; + + //add + bool useHex = false; + bool useLBAOffset = false; + bool useLBALength = false; + uint32_t lbaSize = 512; + bool timeValids[5] = {false, false, false, false, false}; + + //add끝 + uint64_t ssdSize; + uint32_t blocksize; + + uint64_t initTime; // Only used in MODE_STRICT + uint64_t firstTick; // Only used in MODE_STRICT + bool nextIOIsSync; // Only used in MODE_ASYNC + + bool reserveTermination; + + uint64_t max_io; + uint64_t io_submitted; // Submitted I/O in bytes + uint64_t io_count; // I/O count created and submitted + uint64_t read_count; + uint64_t write_count; + + uint64_t io_depth; + + uint64_t mergeTime(std::smatch &); + BIL::BIO_TYPE getType(std::string); + void parseLine(); + void rescheduleSubmit(uint64_t); + + struct TraceLine { + uint64_t tick; + uint64_t offset; + uint64_t length; + BIL::BIO_TYPE type; + int temperature; + + TraceLine() : tick(0), offset(0), length(0), type(BIL::BIO_NUM),temperature(1) {} + } linedata; + + SimpleSSD::Event submitEvent; + SimpleSSD::EventFunction completionEvent; + + void submitIO(); + void iocallback(uint64_t); + + public: + TraceReplayer(Engine &, BIL::BlockIOEntry &, std::function &, + ConfigReader &); + ~TraceReplayer(); + + void init(uint64_t, uint32_t) override; + void begin() override; + void printStats(std::ostream &) override; + void getProgress(float &) override; +}; + +} // namespace IGL + +#endif diff --git a/hotness/SimpleSSD-Standalone/lib/.DS_Store b/hotness/SimpleSSD-Standalone/lib/.DS_Store new file mode 100644 index 0000000000..d5ac74062b Binary files /dev/null and b/hotness/SimpleSSD-Standalone/lib/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/.DS_Store b/hotness/SimpleSSD-Standalone/lib/drampower/.DS_Store new file mode 100644 index 0000000000..1673112898 Binary files /dev/null and b/hotness/SimpleSSD-Standalone/lib/drampower/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/ChangeLog b/hotness/SimpleSSD-Standalone/lib/drampower/ChangeLog new file mode 100644 index 0000000000..e05228e48c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/ChangeLog @@ -0,0 +1,121 @@ +Change Log: + +DRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a user + to access the tool through an API and log commands and their + corresponding time stamps, removing the need to store large + command traces on disk. In addition, cycle counting variables + have been changed to int64 to support longer simulations. + The library can be compiled without Xerces to remove an optional + dependency and reduce the size of the binary. + * Improved robustness. The latest build is automatically checked + out on a test server, compiled, and tested to verify that the + output matches an expected reference. The code is also compiled + with a large number of warning flags enabled and treats all + warnings as errors. + * Bug fix: Fixed bug in io/termination energy calculation. + * Bug fix: Fixed bug in calculation of auto precharge cycle. + +DRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM Power + Calculator, for all supported DRAM generations. In the case of + Wide IO DRAMs, these measures are already included in the provided + current specifications. This feature enables support for multi-rank + DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies + (equivalent to ranks). To indicate use of multi-rank DRAMs or + multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in + the memory specification XMLs can be employed. Note: The DRAM + command scheduler does not support multi-rank/multi-die DRAMs yet. + Only the power estimation component of DRAMPower has been updated + to support them. The current measures for dual-rank DRAMs only + reflect those for the active rank and not the idle rank. The + default state of the idle rank is assumed to be the same as the + current memory state, for background power estimation. Hence, + rank information in the command trace is not required. + * Added warning messages: New warning messages are provided, to + identify if the memory or bank state is inconsistent in the + user-defined traces. Towards this, a state check is performed on + every memory command issued. + * Improved run-time options: Users can now point directly to the + memory specification XML, instead of just the memory ID. Also, + users can optionally include IO and termination power estimates + (for both single and dual rank DRAMs) using '-r' flag in the + command line options. + * Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was + kept ON in the Self-Refresh mode, when it can be turned OFF. This + bug has now been fixed. (2) Precharge All (PREA) always considered + precharging of all banks. It has now been modified to consider + precharging of the open/active banks alone. + +DRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the already + supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM memories. + * Added DRAM Command Scheduler: To support users of DRAMPower + without access to DRAM controllers, we have added a simple DRAM + command scheduler that dynamically schedules DRAM commands as if + it were a memory controller. The scheduler assumes closed-page + policy, employs ASAP scheduling for DRAM commands (i.e. schedules + commands as soon as timing constraints are met), performs FCFS + scheduling on DRAM transactions and supports all the different + DRAM generations supported by the power model. The generated DRAM + command schedule is also analyzable for real-time applications. + Users can also select speculative usage of power-down or + self-refresh modes (if needed) for idle periods between + transactions. It should be noted that using this command scheduler + is optional and it can be (de-)selected during run-time and users + can switch back to the previously used DRAM command interface as + in the earlier versions. + * Improved run-time options: Users can specify the memory and the + trace file to be used by DRAMPower using command line options. + Additionally, if the DRAM command scheduler is being used, the + users can specify the degree of bank interleaving required, the + request size and power-down or self-refresh options. Also, for + DDR4 memories the bank group interleaving can be specified using + command line options. + * Bug fixes: (1) For command traces ending with a RD/WR/RDA/WRA + command, the tool did not consider completion of operations when + estimating the total trace energy. The missing cycles are now + taken into account. + (2) The IDD5 (REF current) specification for WIDE IO SDR memory + specifications only included 2 banks for refreshes instead of all + four. We would like to thank David Roberts from AMD for spotting + the issue in our DATE'13 article. These measures have been updated. + (3) When estimating precharge cycle for commands with + auto-precharge, (RDA/WRA), the command analysis tool employed the + last activation cycle in the entire DRAM instead of the particular + DRAM bank. This bug has been fixed in this release. + +DRAMPower v2.1 - * Added support for variation-aware power estimation, for a + selection of DDR3 memories manufactured using 50nm process + technology, based on the Monte-Carlo analysis presented in our + DAC'13 article. + +DRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories, besides + the already supported DDR2/DDR3 memories. + * Faster analysis: The trace analysis component in DRAMPower v2.0 + triggers the evaluation only during memory state transitions + (between active, precharged, active and precharged power-down, + refresh, self-refresh and power-up states) and not on every clock + cycle, as was the case till the last version. This optimization + speeds up the power simulations using DRAMPower by several times + over cycle-accurate analysis, resulting in fast power analysis, + without affecting the accuracy of the trace analysis or the + reported power and energy estimates. + * Verification effort: Our power model was verified by the + Microelectronic System Design group at TU Kaiserslautern using + circuit-level SPICE simulations of a DRAM cross-section. As a + result of this verification effort, a couple of power equations + have been modified for Refresh and Self-refresh operations. The + difference between the power and energy estimates reported by our + updated model and the equivalent circuit-level simulations is + < 2% for all memory operations of any granularity for all memories + supported by DRAMPower. + +DRAMPower v1.2 - * Supports different power-down and self-refresh modes in DDR2 and + DDR3 DRAM memories. + * Bug fix: Refresh power consumption equation in DRAMPower v1, + incorrectly subtracted IDD2n (precharge background current) + instead of IDD3n (active background current) from IDD5 (total + refresh current). This error has been rectified in this version. + +DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and estimates + power and energy consumption numbers for the trace. + * It supports the basic memory operations like read, write, refresh, + activate and (auto) precharge in DDR2 and DDR3 memories. diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/README.md b/hotness/SimpleSSD-Standalone/lib/drampower/README.md new file mode 100644 index 0000000000..b5843b0197 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/README.md @@ -0,0 +1,263 @@ +# DRAM Power Model (DRAMPower) +[![Build Status](https://travis-ci.org/ravenrd/DRAMPower.svg?branch=master)](https://travis-ci.org/ravenrd/DRAMPower) +[![Coverage Status](https://coveralls.io/repos/ravenrd/DRAMPower/badge.png?branch=master)](https://coveralls.io/r/ravenrd/DRAMPower?branch=master) +## 0. Releases + +The last official release can be found here: +https://github.com/ravenrd/DRAMPower/releases/tag/4.0 + +The master branch of the repository should be regarded as the bleeding-edge version, which has all the latest features, but also all the latest bugs. Use at your own discretion. + +## 1. Installation + +Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. [drampower.cc](src/cli/drampower.cc) file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: +```bash +make -j4 +``` +This command will download a set of trace files from https://github.com/Sv3n/DRAMPowerTraces which can be used as test input for the tool. + +## 2. Required Packages + +The tool was verified on Ubuntu 14.04 using: + + * xerces-c (libxerces-c-dev) - v3.1 with Xerces development package + * gcc - v4.4.3 + +## 3. Directory Structure + * src/: contains the source code of the DRAMPower tool that covers the power model, the command scheduler and the trace analysis tool. + * memspecs/ : contains the memory specification XMLs, which give the architectural, timing and current/voltage details for different DRAM memories. + * traces/ : contains 4 sample DRAM transaction traces and 1 sample command trace (after the installation / compilation) + * test/ : contains test script and reference output + +## 4. Trace Specification +### Command Traces +If the command-level interface is being used, a command trace can be logged in a file. +An example is given in ```traces/commands.trace``` + +The format it uses is: ```,,```. +For example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is +mentioned in [MemCommand.h](src/MemCommand.h) and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be +specified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder. + +### Transaction Traces +If the transaction-level interface is being used, a transaction trace can be logged. + +The format it uses is: ```,,
```. +For example, "35,READ,0x80028", where READ/WRITE can be the transaction type and the logical address (32-bits long and byte addressable) less than the maximum supported DRAM capacity of 4GB (32Gb). + +The tool uses a flexible and efficient memory map as follows: specified in HEX (0x). Timestamp is in clock cycles (cc) and maximum {row}-{bank}-{column}-{BI}-{BC}-{BGI}-{BL} +Here, BI gives the degree of bank interleaving, BC gives the burst size (count), BGI gives the degree of bank group interleaving (for DDR4) and BL gives the burst length used by the device. +Dual-Rank addressing is not yet supported. The BC and BL address bits are derived from the column address bits, whereas the BI and BGI bits are derived from the bank address bits. + +Four sample MediaBench application transaction traces have been provided. The MediaBench applications include: (1) EPIC Encoder, (2) JPEG Encoder, (3) H263 Encoder and (4) MPEG2 Encoder. These applications were independently executed on the SimpleScalar simulator with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and logged them as transaction traces. These can be used with our command scheduler to generate equivalent command traces for any DRAM memory specified. + +## 5. Usage + +[drampower.cc](src/cli/drampower.cc) is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. + +To use DRAMPower at the command-level (command trace), after make, use the following: +```bash +./drampower -m -c +``` +To use DRAMPower at the transaction-level (command scheduler), after make, use the +following: +```bash +./drampower -m -t +``` +Additional options when using transactions trace [-t] include: + * [-i] `````` + * [-s] `````` + * [-g] `````` + * [-p] ```<0 - No Power-Down, 1 - Power-Down, 2 - Self-Refresh>``` + +Also, when using either the commands trace or the transactions trace, the user can +optionally include IO and Termination power estimates (obtained from Micron's DRAM +Power Calculator). To enable the same, the '-r' flag can be employed in command line. + +If these options are not used, the default values assumed are: +* interleaving = 1 +* request size = burst length * I/O width / 8 (in bytes) (from memory XMLs) +* power saving = No power-down +* bank group interleaving = 1 +* IO and termination = OFF (0) +* Burst size (count) of 1 + +## 6. Memory Specifications + +36 sample memory specifications are given in the XMLs targeting DDR2/DDR3/DDR4, LPDDR/LPDDR2/LPDDR3 and WIDE IO DRAM devices. The memory specifications are based on 1Gb DDR2, 1Gb & 2Gb DDR3, 2Gb LPDDR/LPDDR2 and 4Gb DDR4/LPDDR3 Micron datasheets and the 256Mb Wide IO SDR specifications are based on JEDEC timing specifications and circuit-level IDD measurements by TU Kaiserslautern, inplace of the as yet unavailable vendor datasheets. 4 of the memory specifications target dual-rank DDR3 DIMMs. + +Note: The timing specifications in the XMLs are in clock cycles (cc). The current specifications for Reading and Writing do not include the I/O consumption. They are computed and included seperately based on Micron Power Calculator. The IDD measures associated with different power supply sources of equal measure (VDD2, VDDCA and VDDQ) for LPDDR2, LPDDR3, DDR4 and WIDE IO memories have been added up together for simplicity, since it does not impact power computation accuracy. The current measures for dual-rank DIMMs reflect only the measures for the active rank. The default state of the idle rank is assumed to be the same as the complete memory state, for background power estimation. Accordingly, in all dual-rank memory specifications, IDD2P0 has been subtracted from the active currents and all background currents have been halved. They are also accounted for seperately by the power model. Stacking multiple Wide IO DRAM dies can also be captured by the nbrOfRanks parameter. + +## 7. Variation-aware Power And Energy Estimation + +15 of the included datasheets reflect the impact of process-variations on DRAM currents for a selection of DDR3 memories manufactured at 50nm process technology. These memories include: +(1) MICRON_128MB_DDR3-1066_8bit - revision G +(2) MICRON_128MB_DDR3-1066_16bit - revision G +(3) MICRON_128MB_DDR3-1600_8bit - revision G +(4) MICRON_256MB_DDR3-1066_8bit - revision D +(5) MICRON_256MB_DDR3-1600_16bit - revision D + +The original vendor-provided datasheet current specifications are given in XMLs +without suffixes such as _mu, _2s and _3s. XMLs including suffixes indicate that the +current measures are either: (1) typical (mu), or (2) include +2 sigma variation (2s), +or (3) include +3 sigma variation (3s). These measures are derived based on the +Monte-Carlo analysis performed on our SPICE-based DRAM cross-section. + +To include these XMLs in your simulations, simply use them as the target memory. + +## 8. Example Usage + +An example of using this tool is provided below. To compile the example, +use the Makefile and make sure the gcc and Xerces-c are installed. Then, run: +``` +make -j4 +``` +After this, run with the command trace or the transaction trace, as described before: +``` +./drampower -m memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml -t traces/mediabench-epic.trace -r +``` +The output should be something like this: + +``` +* Parsing memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml +* Analysis start time: Thu Aug 4 15:43:52 2016 +* Analyzing the input trace +* Trace Details: + +#ACT commands: 96984 +#RD + #RDA commands: 67179 +#WR + #WRA commands: 29805 +#PRE (+ PREA) commands: 96984 +#REF commands: 13168 +#Active Cycles: 2519793 + #Active Idle Cycles: 196851 + #Active Power-Up Cycles: 0 + #Auto-Refresh Active cycles during Self-Refresh Power-Up: 0 +#Precharged Cycles: 52261474 + #Precharged Idle Cycles: 51649629 + #Precharged Power-Up Cycles: 0 + #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: 0 + #Self-Refresh Power-Up Cycles: 0 +Total Idle Cycles (Active + Precharged): 51846480 +#Power-Downs: 0 + #Active Fast-exit Power-Downs: 0 + #Active Slow-exit Power-Downs: 0 + #Precharged Fast-exit Power-Downs: 0 + #Precharged Slow-exit Power-Downs: 0 +#Power-Down Cycles: 0 + #Active Fast-exit Power-Down Cycles: 0 + #Active Slow-exit Power-Down Cycles: 0 + #Auto-Refresh Active cycles during Self-Refresh: 0 + #Precharged Fast-exit Power-Down Cycles: 0 + #Precharged Slow-exit Power-Down Cycles: 0 + #Auto-Refresh Precharged cycles during Self-Refresh: 0 +#Auto-Refresh Cycles: 776912 +#Self-Refreshes: 0 +#Self-Refresh Cycles: 0 +---------------------------------------- +Total Trace Length (clock cycles): 54781267 +---------------------------------------- + +* Trace Power and Energy Estimates: + +ACT Cmd Energy: 109175234.52 pJ +PRE Cmd Energy: 47764165.10 pJ +RD Cmd Energy: 49155365.85 pJ +WR Cmd Energy: 23486116.32 pJRD I/O Energy: 20872124.58 pJ +WR Termination Energy: 47419587.24 pJ +ACT Stdby Energy: 283653996.25 pJ + Active Idle Energy: 22159587.24 pJ + Active Power-Up Energy: 0.00 pJ + Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ +PRE Stdby Energy: 5147706163.23 pJ + Precharge Idle Energy: 5087440004.69 pJ + Precharged Power-Up Energy: 0.00 pJ + Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ + Self-Refresh Power-Up Energy: 0.00 pJ +Total Idle Energy (Active + Precharged): 5109599591.93 pJ +Total Power-Down Energy: 0.00 pJ + Fast-Exit Active Power-Down Energy: 0.00 pJ + Slow-Exit Active Power-Down Energy: 0.00 pJ + Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ + Fast-Exit Precharged Power-Down Energy: 0.00 pJ + Slow-Exit Precharged Power-Down Energy: 0.00 pJ + Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ +Auto-Refresh Energy: 262371782.36 pJ +Self-Refresh Energy: 0.00 pJ +---------------------------------------- +Total Trace Energy: 5991604535.46 pJ +Average Power: 58.30 mW +---------------------------------------- +* Power Computation End time: Thu Aug 4 15:43:59 2016 +* Total Simulation time: 7 seconds +* +``` + +As can be noticed, the tool performs DRAM command scheduling and reports the number +of activates, precharges, reads, writes, refreshes, power-downs and self-refreshes +besides the number of clock cycles spent in the active and precharged states, in the +power-down (fast/slow-exit) and self-refresh states and in the idle mode. It also +reports the energy consumption of these components, besides the IO and Termination +components in pJ (pico Joules) and the average power consumption of the trace in mW. +It also reports the simulation start/end times and the total simulation time in seconds. + +## 9. DRAMPower Library + +The DRAMPower tool has an additional feature and can be used as a library. +In order to use the library run "make lib", include [LibDRAMPower.h](src/libdrampower/LibDRAMPower.h) in your project and +link the file src/libdrampower.a with your project. +Examples for the usage of the library are [lib_test.cc](test/libdrampowertest/lib_test.cc) and [window_example.cc](test/libdrampowertest/window_example.cc). + +## 10. Authors & Acknowledgment + +The tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven +and verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations. This tool has been developed by +Karthik Chandrasekar with Yonghui Li under the supervision of Dr. Benny Akesson and Prof. Kees Goossens. The IO and Termination Power measures have been employed +from Micron's DRAM Power Calculator. If you decide to use DRAMPower in your research, please cite one of the following references: + +**To cite the DRAMPower Tool:** +``` +[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool +Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens +URL: http://www.drampower.info +``` + +**To cite the DRAM power model:** +``` +[2] "Improved Power Modeling of DDR SDRAMs" +Karthik Chandrasekar, Benny Akesson, and Kees Goossens +In Proc. 14th Euromicro Conference on Digital System Design (DSD), 2011 +``` + +**To cite the 3D-DRAM power model:** +``` +[3] "System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs" +Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens +In Proc. Design, Automation and Test in Europe (DATE), 2013 +``` + +**To cite variation-aware DRAM power estimation:** +``` +[4] "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach" +Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens +In Proc. Design Automation Conference (DAC), 2013 +``` + +## 11. Contact Information + +Further questions about the tool and the power model can be directed to: + +Benny Akesson (k.b.akesson@tue.nl) + +Feel free to ask for updates to the tool's features and please do report any bugs +and errors you encounter. This will encourage us to continuously improve the tool. + +## Disclaimer + +The tool does not check the timing accuracy of the user's memory command trace +and the use of commands and memory modes. It is expected that the user employs +a valid trace generated using a DRAM memory controller or simulator, which +satisfies all memory timing constraints and other requirements. The user DOES +NOT get ANY WARRANTIES when using this tool. This software is released under the +BSD 3-Clause License. By using this software, the user implicitly agrees to the +licensing terms. diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/CAHelpers.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/CAHelpers.cc new file mode 100644 index 0000000000..e7df883187 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/CAHelpers.cc @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +#include // std::count +#include + +#include "CommandAnalysis.h" + +using std::cerr; +using std::endl; +using std::string; + +using namespace Data; + + +// To get the time of completion of the issued command +// Derived based on JEDEC specifications + +int64_t CommandAnalysis::timeToCompletion(MemCommand::cmds type) +{ + int64_t offset = 0; + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + + if (type == MemCommand::RD) { + offset = memTimingSpec.RL + + memTimingSpec.DQSCK + 1 + (memArchSpec.burstLength / + memArchSpec.dataRate); + } else if (type == MemCommand::WR) { + offset = memTimingSpec.WL + + (memArchSpec.burstLength / memArchSpec.dataRate) + + memTimingSpec.WR; + } else if (type == MemCommand::ACT) { + offset = memTimingSpec.RCD; + } else if ((type == MemCommand::PRE) || (type == MemCommand::PREA)) { + offset = memTimingSpec.RP; + } + return offset; +} // CommandAnalysis::timeToCompletion + + +// Returns the number of active banks based on the bank_state vector. +unsigned CommandAnalysis::get_num_active_banks(void) +{ + return (unsigned)std::count(bank_state.begin(), bank_state.end(), BANK_ACTIVE); +} + +// Naming-standard compliant wrapper +unsigned CommandAnalysis::nActiveBanks(void) +{ + return CommandAnalysis::get_num_active_banks(); +} + +bool CommandAnalysis::isPrecharged(unsigned bank) +{ + return bank_state[bank] == BANK_PRECHARGED; +} + +void CommandAnalysis::printWarningIfActive(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + if (get_num_active_banks() != 0) { + printWarning(warning, type, timestamp, bank); + } +} + +void CommandAnalysis::printWarningIfNotActive(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + if (get_num_active_banks() == 0) { + printWarning(warning, type, timestamp, bank); + } +} + +void CommandAnalysis::printWarningIfPoweredDown(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + if (mem_state != 0) { + printWarning(warning, type, timestamp, bank); + } +} + +void CommandAnalysis::printWarning(const string& warning, int type, int64_t timestamp, unsigned bank) +{ + cerr << "WARNING: " << warning << endl; + cerr << "Command: " << type << ", Timestamp: " << timestamp << + ", Bank: " << bank << endl; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdHandlers.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdHandlers.cc new file mode 100644 index 0000000000..ac05d22f44 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdHandlers.cc @@ -0,0 +1,627 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#include "CommandAnalysis.h" + +using std::cerr; +using std::endl; +using std::max; + +using namespace Data; + + +int64_t zero_guard(int64_t cycles_in, const char* warning) +{ + // Calculate max(0, cycles_in) + int64_t zero = 0; + if (warning != nullptr && cycles_in < 0) { + // This line is commented out for now, we will attempt to remove the situations where + // these warnings trigger later. + // cerr << "WARNING: " << warning << endl; + } + return max(zero, cycles_in); +} + +void CommandAnalysis::handleAct(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::ACT, timestamp, bank); + // If command is ACT - update number of acts, bank state of the + // target bank, first and latest activation cycle and the memory + // state. Update the number of precharged/idle-precharged cycles. + // If the bank is already active ignore the command and generate a + // warning. + if (isPrecharged(bank)) { + numberofactsBanks[bank]++; + + if (nActiveBanks() == 0) { + // Here a memory state transition to ACT is happening. Save the + // number of cycles in precharge state (increment the counter). + first_act_cycle = timestamp; + precycles += zero_guard(timestamp - last_pre_cycle, "1 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + } + + bank_state[bank] = BANK_ACTIVE; + latest_act_cycle = timestamp; + } else { + printWarning("Bank is already active!", MemCommand::ACT, timestamp, bank); + } +} + +void CommandAnalysis::handleRd(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::RD, timestamp, bank); + // If command is RD - update number of reads and read cycle. Check + // for active idle cycles (if any). + if (isPrecharged(bank)) { + printWarning("Bank is not active!", MemCommand::RD, timestamp, bank); + } + numberofreadsBanks[bank]++; + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + latest_read_cycle = timestamp; +} + +void CommandAnalysis::handleWr(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::WR, timestamp, bank); + // If command is WR - update number of writes and write cycle. Check + // for active idle cycles (if any). + if (isPrecharged(bank)) { + printWarning("Bank is not active!", MemCommand::WR, timestamp, bank); + } + numberofwritesBanks[bank]++; + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + latest_write_cycle = timestamp; +} + +void CommandAnalysis::handleRef(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::REF, timestamp, bank); + // If command is REF - update number of refreshes, set bank state of + // all banks to ACT, set the last PRE cycles at RFC-RP cycles from + // timestamp, set the number of active cycles to RFC-RP and check + // for active and precharged cycles and idle active and idle + // precharged cycles before refresh. Change memory state to 0. + printWarningIfActive("One or more banks are active! REF requires all banks to be precharged.", MemCommand::REF, timestamp, bank); + numberofrefs++; + idle_pre_update(timestamp, latest_pre_cycle); + first_act_cycle = timestamp; + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); + precycles += zero_guard(timestamp - last_pre_cycle, "2 last_pre_cycle is in the future."); + last_pre_cycle = timestamp + memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + latest_pre_cycle = last_pre_cycle; + actcycles += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + for (auto &e : actcyclesBanks) { + e += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + } + for (auto& bs : bank_state) { + bs = BANK_PRECHARGED; + } +} + +void CommandAnalysis::handleRefB(unsigned bank, int64_t timestamp) +{ + // A REFB command requires a previous PRE command. + if (isPrecharged(bank)) { + // This previous PRE command handler is also responsible for keeping the + // memory state updated. + // Here we consider that the memory state is not changed in order to keep + // things simple, since the transition from PRE to ACT state takes time. + numberofrefbBanks[bank]++; + // Length of the refresh: here we have an approximation, we consider tRP + // also as act cycles because the bank will be precharged (stable) after + // tRP. + actcyclesBanks[bank] += memSpec.memTimingSpec.RAS + memSpec.memTimingSpec.RP; + } else { + printWarning("Bank must be precharged for REFB!", MemCommand::REFB, timestamp, bank); + } +} + +void CommandAnalysis::handlePre(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::PRE, timestamp, bank); + // If command is explicit PRE - update number of precharges, bank + // state of the target bank and last and latest precharge cycle. + // Calculate the number of active cycles if the memory was in the + // active state before, but there is a state transition to PRE now + // (i.e., this is the last active bank). + // If the bank is already precharged ignore the command and generate a + // warning. + + // Precharge only if the target bank is active + if (bank_state[bank] == BANK_ACTIVE) { + numberofpresBanks[bank]++; + actcyclesBanks[bank] += zero_guard(timestamp - first_act_cycle_banks[bank], "first_act_cycle is in the future (bank)."); + // Since we got here, at least one bank is active + assert(nActiveBanks() != 0); + + if (nActiveBanks() == 1) { + // This is the last active bank. Therefore, here a memory state + // transition to PRE is happening. Let's increment the active cycle + // counter. + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + last_pre_cycle = timestamp; + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + } + + bank_state[bank] = BANK_PRECHARGED; + latest_pre_cycle = timestamp; + } else { + printWarning("Bank is already precharged!", MemCommand::PRE, timestamp, bank); + } +} + +void CommandAnalysis::handlePreA(unsigned bank, int64_t timestamp) +{ + printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::PREA, timestamp, bank); + // If command is explicit PREA (precharge all banks) - update + // number of precharges by the number of active banks, update the bank + // state of all banks to PRE and set the precharge cycle (the cycle in + // which the memory state changes from ACT to PRE, aka last_pre_cycle). + // Calculate the number of active cycles if the memory was in the + // active state before, but there is a state transition to PRE now. + + if (nActiveBanks() > 0) { + // Active banks are being precharged + // At least one bank was active, therefore the current memory state is + // ACT. Since all banks are being precharged a memory state transition + // to PRE is happening. Add to the counter the amount of cycles the + // memory remained in the ACT state. + + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + last_pre_cycle = timestamp; + + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + // Active banks are being precharged + numberofpresBanks[b] += 1; + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)."); + } + } + + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + + latest_pre_cycle = timestamp; + // Reset the state for all banks to precharged. + for (auto& bs : bank_state) { + bs = BANK_PRECHARGED; + } + } else { + printWarning("All banks are already precharged!", MemCommand::PREA, timestamp, bank); + } +} + +void CommandAnalysis::handlePdnFAct(unsigned bank, int64_t timestamp) +{ + // If command is fast-exit active power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // fast-exit active power-down. Save states of all the banks from + // the cycle before entering active power-down, to be returned to + // after powering-up. Update active and active idle cycles. + printWarningIfNotActive("All banks are precharged! Incorrect use of Active Power-Down.", MemCommand::PDN_F_ACT, timestamp, bank); + f_act_pdns++; + last_bank_state = bank_state; + pdn_cycle = timestamp; + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)."); + } + } + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + mem_state = CommandAnalysis::MS_PDN_F_ACT; +} + +void CommandAnalysis::handlePdnSAct(unsigned bank, int64_t timestamp) +{ + // If command is slow-exit active power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // slow-exit active power-down. Save states of all the banks from + // the cycle before entering active power-down, to be returned to + // after powering-up. Update active and active idle cycles. + printWarningIfNotActive("All banks are precharged! Incorrect use of Active Power-Down.", MemCommand::PDN_S_ACT, timestamp, bank); + s_act_pdns++; + last_bank_state = bank_state; + pdn_cycle = timestamp; + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future."); + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)."); + } + } + idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); + mem_state = CommandAnalysis::MS_PDN_S_ACT; +} + +void CommandAnalysis::handlePdnFPre(unsigned bank, int64_t timestamp) +{ + // If command is fast-exit precharged power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // fast-exit precahrged power-down. Update precharged and precharged + // idle cycles. + printWarningIfActive("One or more banks are active! Incorrect use of Precharged Power-Down.", MemCommand::PDN_F_PRE, timestamp, bank); + f_pre_pdns++; + pdn_cycle = timestamp; + precycles += zero_guard(timestamp - last_pre_cycle, "3 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + mem_state = CommandAnalysis::MS_PDN_F_PRE; +} + +void CommandAnalysis::handlePdnSPre(unsigned bank, int64_t timestamp) +{ + // If command is slow-exit precharged power-down - update number of + // power-downs, set the power-down cycle and the memory mode to + // slow-exit precahrged power-down. Update precharged and precharged + // idle cycles. + printWarningIfActive("One or more banks are active! Incorrect use of Precharged Power-Down.", MemCommand::PDN_S_PRE, timestamp, bank); + s_pre_pdns++; + pdn_cycle = timestamp; + precycles += zero_guard(timestamp - last_pre_cycle, "4 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + mem_state = CommandAnalysis::MS_PDN_S_PRE; +} + +void CommandAnalysis::handlePupAct(int64_t timestamp) +{ + // If command is power-up in the active mode - check the power-down + // exit-mode employed (fast or slow), update the number of power-down + // and power-up cycles and the latest and first act cycle. Also, reset + // all the individual bank states to the respective saved states + // before entering power-down. + const MemTimingSpec& t = memSpec.memTimingSpec; + + if (mem_state == CommandAnalysis::MS_PDN_F_ACT) { + f_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + pup_act_cycles += t.XP; + latest_act_cycle = timestamp; + } else if (mem_state == CommandAnalysis::MS_PDN_S_ACT) { + s_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + if (memSpec.memArchSpec.dll == false) { + pup_act_cycles += t.XP; + latest_act_cycle = timestamp; + } else { + pup_act_cycles += t.XPDLL - t.RCD; + latest_act_cycle = timestamp + zero_guard(t.XPDLL - (2 * t.RCD), "t.XPDLL - (2 * t.RCD) < 0"); + } + } else { + cerr << "Incorrect use of Active Power-Up!" << endl; + } + mem_state = MS_NOT_IN_PD; + bank_state = last_bank_state; + first_act_cycle = timestamp; + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); +} + +void CommandAnalysis::handlePupPre(int64_t timestamp) +{ + // If command is power-up in the precharged mode - check the power-down + // exit-mode employed (fast or slow), update the number of power-down + // and power-up cycles and the latest and last pre cycle. + const MemTimingSpec& t = memSpec.memTimingSpec; + if (mem_state == CommandAnalysis::MS_PDN_F_PRE) { + f_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + pup_pre_cycles += t.XP; + latest_pre_cycle = timestamp; + } else if (mem_state == CommandAnalysis::MS_PDN_S_PRE) { + s_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future."); + if (memSpec.memArchSpec.dll == false) { + pup_pre_cycles += t.XP; + latest_pre_cycle = timestamp; + } else { + pup_pre_cycles += t.XPDLL - t.RCD; + latest_pre_cycle = timestamp + zero_guard(t.XPDLL - t.RCD - t.RP, "t.XPDLL - t.RCD - t.RP"); + } + } else { + cerr << "Incorrect use of Precharged Power-Up!" << endl; + } + mem_state = MS_NOT_IN_PD; + last_pre_cycle = timestamp; +} + +void CommandAnalysis::handleSREn(unsigned bank, int64_t timestamp) +{ + // If command is self-refresh - update number of self-refreshes, + // set memory state to SREF, update precharge and idle precharge + // cycles and set the self-refresh cycle. + printWarningIfActive("One or more banks are active! SREF requires all banks to be precharged.", MemCommand::SREN, timestamp, bank); + numberofsrefs++; + sref_cycle = timestamp; + sref_cycle_window = timestamp; + sref_ref_pre_cycles_window = 0; + sref_ref_act_cycles_window = 0; + precycles += zero_guard(timestamp - last_pre_cycle, "5 last_pre_cycle is in the future."); + idle_pre_update(timestamp, latest_pre_cycle); + mem_state = CommandAnalysis::MS_SREF; +} + +void CommandAnalysis::handleSREx(unsigned bank, int64_t timestamp) +{ + // If command is self-refresh exit - update the number of self-refresh + // clock cycles, number of active and precharged auto-refresh clock + // cycles during self-refresh and self-refresh exit based on the number + // of cycles in the self-refresh mode and auto-refresh duration (RFC). + // Set the last and latest precharge cycle accordingly and set the + // memory state to 0. + const MemTimingSpec& t = memSpec.memTimingSpec; + if (mem_state != CommandAnalysis::MS_SREF) { + cerr << "Incorrect use of Self-Refresh Power-Up!" << endl; + } + // The total duration of self-refresh is given by the difference between + // the current clock cycle and the clock cycle of entering self-refresh. + int64_t sref_duration = timestamp - sref_cycle; + + // Negative or zero duration should never happen. + if (sref_duration <= 0) { + printWarning("Invalid Self-Refresh duration!", MemCommand::SREX, timestamp, bank); + sref_duration = 0; + } + + // The minimum time that the DRAM must remain in Self-Refresh is CKESR. + if (sref_duration < t.CKESR) { + printWarning("Self-Refresh duration < CKESR!", MemCommand::SREX, timestamp, bank); + } + + if (sref_duration >= t.RFC) { + /* + * Self-refresh Exit Context 1 (tSREF >= tRFC): + * The memory remained in self-refresh for a certain number of clock + * cycles greater than a refresh cycle time (RFC). Consequently, the + * initial auto-refresh accomplished. + * + * + * SREN # SREX + * | # ^ + * | # | + * |<------------------------- tSREF ----------...----->| + * | # | + * | Initial Auto-Refresh # | + * v # | + * ------------------------------------#-------...-----------------> t + * # + * <------------- tRFC --------------># + * <---- (tRFC - tRP) ----><-- tRP --># + * | | + * v v + * sref_ref_act_cycles sref_ref_pre_cycles + * + * + * Summary: + * sref_cycles += tSREF – tRFC + * sref_ref_act_cycles += tRFC - tRP + * sref_ref_pre_cycles += tRP + * spup_ref_act_cycles += 0 + * spup_ref_pre_cycles += 0 + * + */ + + // The initial auto-refresh consumes (IDD5 − IDD3N) over one refresh + // period (RFC) from the start of the self-refresh. + sref_ref_act_cycles += t.RFC - + t.RP - sref_ref_act_cycles_window; + sref_ref_pre_cycles += t.RP - sref_ref_pre_cycles_window; + last_pre_cycle = timestamp; + + // The IDD6 current is consumed for the time period spent in the + // self-refresh mode, which excludes the time spent in finishing the + // initial auto-refresh. + if (sref_cycle_window > sref_cycle + t.RFC) { + sref_cycles += zero_guard(timestamp - sref_cycle_window, "sref_cycle_window is in the future."); + } else { + sref_cycles += zero_guard(timestamp - sref_cycle - t.RFC, "sref_cycle - t.RFC < 0"); + } + + // IDD2N current is consumed when exiting the self-refresh state. + if (memSpec.memArchSpec.dll == false) { + spup_cycles += t.XS; + latest_pre_cycle = timestamp + zero_guard(t.XS - t.RP, "t.XS - t.RP < 0"); + } else { + spup_cycles += t.XSDLL - t.RCD; + latest_pre_cycle = timestamp + zero_guard(t.XSDLL - t.RCD - t.RP, "t.XSDLL - t.RCD - t.RP < 0"); + } + + } else { + // Self-refresh Exit Context 2 (tSREF < tRFC): + // Exit self-refresh before the completion of the initial + // auto-refresh. + + // Number of active cycles needed by an auto-refresh. + int64_t ref_act_cycles = t.RFC - t.RP; + + if (sref_duration >= ref_act_cycles) { + /* + * Self-refresh Exit Context 2A (tSREF < tRFC && tSREF >= tRFC - tRP): + * The duration of self-refresh is equal or greater than the number + * of active cycles needed by the initial auto-refresh. + * + * + * SREN SREX + * | ^ # + * | | # + * |<------------------ tSREF --------------------->| # + * | | # + * | Initial Auto-Refresh # + * v | # + * -----------------------------------------------------------#--> t + * # + * <------------------------ tRFC --------------------------># + * <------------- (tRFC - tRP)--------------><----- tRP ----># + * | <-----><-------> + * v | | + * sref_ref_act_cycles v v + * sref_ref_pre_cycles spup_ref_pre_cycles + * + * + * Summary: + * sref_cycles += 0 + * sref_ref_act_cycles += tRFC - tRP + * sref_ref_pre_cycles += tSREF – (tRFC – tRP) + * spup_ref_act_cycles += 0 + * spup_ref_pre_cycles += tRP – sref_ref_pre_cycles + * + */ + + // Number of precharged cycles (zero <= pre_cycles < RP) + int64_t pre_cycles = sref_duration - ref_act_cycles - sref_ref_pre_cycles_window; + + sref_ref_act_cycles += ref_act_cycles - sref_ref_act_cycles_window; + sref_ref_pre_cycles += pre_cycles; + + // Number of precharged cycles during the self-refresh power-up. It + // is at maximum tRP (if pre_cycles is zero). + int64_t spup_pre = t.RP - pre_cycles; + + spup_ref_pre_cycles += spup_pre; + + last_pre_cycle = timestamp + spup_pre; + + if (memSpec.memArchSpec.dll == false) { + spup_cycles += t.XS - spup_pre; + latest_pre_cycle = timestamp + zero_guard(t.XS - spup_pre - t.RP, "t.XS - spup_pre - t.RP < 0"); + } else { + spup_cycles += t.XSDLL - t.RCD - spup_pre; + latest_pre_cycle = timestamp + zero_guard(t.XSDLL - t.RCD - spup_pre - t.RP, "t.XSDLL - t.RCD - spup_pre - t.RP"); + } + } else { + /* + * Self-refresh Exit Context 2B (tSREF < tRFC - tRP): + * self-refresh duration is shorter than the number of active cycles + * needed by the initial auto-refresh. + * + * + * SREN SREX + * | ^ # + * | | # + * |<-------------- tSREF ----------->| # + * | | # + * | Initial Auto-Refresh # + * v | # + * ------------------------------------------------------------#--> t + * # + * <------------------------ tRFC ---------------------------># + * <-------------- (tRFC - tRP)-------------><------ tRP ----># + * <--------------------------------><------><---------------> + * | | | + * v v v + * sref_ref_act_cycles spup_ref_act_cycles spup_ref_pre_cycles + * + * + * Summary: + * sref_cycles += 0 + * sref_ref_act_cycles += tSREF + * sref_ref_pre_cycles += 0 + * spup_ref_act_cycles += (tRFC – tRP) - tSREF + * spup_ref_pre_cycles += tRP + * + */ + + sref_ref_act_cycles += sref_duration - sref_ref_act_cycles_window; + + int64_t spup_act = (t.RFC - t.RP) - sref_duration; + + spup_ref_act_cycles += spup_act; + spup_ref_pre_cycles += t.RP; + + last_pre_cycle = timestamp + spup_act + t.RP; + if (memSpec.memArchSpec.dll == false) { + spup_cycles += t.XS - spup_act - t.RP; + latest_pre_cycle = timestamp + zero_guard(t.XS - spup_act - (2 * t.RP), "t.XS - spup_act - (2 * t.RP) < 0"); + } else { + spup_cycles += t.XSDLL - t.RCD - spup_act - t.RP; + latest_pre_cycle = timestamp + zero_guard(t.XSDLL - t.RCD - spup_act - (2 * t.RP), "t.XSDLL - t.RCD - spup_act - (2 * t.RP) < 0"); + } + } + } + mem_state = MS_NOT_IN_PD; +} + + +void CommandAnalysis::handleNopEnd(int64_t timestamp) +{ + // May be optionally used at the end of memory trace for better accuracy + // Update all counters based on completion of operations. + const MemTimingSpec& t = memSpec.memTimingSpec; + for (unsigned b = 0; b < num_banks; b++) { + if (bank_state[b] == BANK_ACTIVE) { + actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)"); + } + } + + if (nActiveBanks() > 0 && mem_state == MS_NOT_IN_PD) { + actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future"); + idle_act_update(latest_read_cycle, latest_write_cycle, + latest_act_cycle, timestamp); + } else if (nActiveBanks() == 0 && mem_state == MS_NOT_IN_PD) { + precycles += zero_guard(timestamp - last_pre_cycle, "6 last_pre_cycle is in the future"); + idle_pre_update(timestamp, latest_pre_cycle); + } else if (mem_state == CommandAnalysis::MS_PDN_F_ACT) { + f_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_PDN_S_ACT) { + s_act_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_PDN_F_PRE) { + f_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_PDN_S_PRE) { + s_pre_pdcycles += zero_guard(timestamp - pdn_cycle, "pdn_cycle is in the future"); + } else if (mem_state == CommandAnalysis::MS_SREF) { + auto rfc_minus_rp = (t.RFC - t.RP); + + if (timestamp > sref_cycle + t.RFC) { + if (sref_cycle_window <= sref_cycle + rfc_minus_rp) { + sref_ref_act_cycles += rfc_minus_rp - sref_ref_act_cycles_window; + sref_ref_act_cycles_window = rfc_minus_rp; + sref_cycle_window = sref_cycle + rfc_minus_rp; + } + if (sref_cycle_window <= sref_cycle + t.RFC) { + sref_ref_pre_cycles += t.RP - sref_ref_pre_cycles_window; + sref_ref_pre_cycles_window = t.RP; + sref_cycle_window = sref_cycle + t.RFC; + } + sref_cycles += zero_guard(timestamp - sref_cycle_window, "sref_cycle_window is in the future"); + } else if (timestamp > sref_cycle + rfc_minus_rp) { + + if (sref_cycle_window <= sref_cycle + rfc_minus_rp) { + sref_ref_act_cycles += rfc_minus_rp - sref_ref_act_cycles_window; + sref_ref_act_cycles_window = rfc_minus_rp; + sref_cycle_window = sref_cycle + rfc_minus_rp; + } + sref_ref_pre_cycles_window += timestamp - sref_cycle_window; + sref_ref_pre_cycles += timestamp - sref_cycle_window; + } else { + sref_ref_act_cycles_window += timestamp - sref_cycle_window; + sref_ref_act_cycles += timestamp - sref_cycle_window; + } + } +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdScheduler.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdScheduler.cc new file mode 100644 index 0000000000..a4619b94ec --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdScheduler.cc @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, Yonghui Li, Sven Goossens + * + */ +#include "CmdScheduler.h" + +#include +#include // For log2 + +#include // For max + + +#define MILLION 1000000 + + +using namespace std; +using namespace Data; + +// Read the traces and get the transaction. Each transaction is executed by +// scheduling a number of commands to the memory. Hence, the transactions are +// translated into a sequence of commands which will be used for power analysis. +void cmdScheduler::transTranslation(const MemorySpecification& memSpec, + ifstream& trans_trace, int grouping, int interleaving, int burst, int powerdown) +{ + commands.open("commands.trace", ifstream::out); + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + nBanks = memArchSpec.nbrOfBanks; + nColumns = memArchSpec.nbrOfColumns; + burstLength = memArchSpec.burstLength; + nbrOfBankGroups = memArchSpec.nbrOfBankGroups; + + BGI = grouping; + BI = interleaving; + BC = burst; + power_down = powerdown; + + schedulingInitialization(memSpec); + getTrans(trans_trace, memSpec); + + trans_trace.close(); + commands.close(); + ACT.erase(ACT.begin(), ACT.end()); + PRE.erase(PRE.begin(), PRE.end()); + RDWR.erase(RDWR.begin(), RDWR.end()); + cmdScheduling.erase(cmdScheduling.begin(), cmdScheduling.end()); + cmdList.erase(cmdList.begin(), cmdList.end()); + transTrace.erase(transTrace.begin(), transTrace.end()); +} // cmdScheduler::transTranslation + +// initialize the variables and vectors for starting command scheduling. +void cmdScheduler::schedulingInitialization(const MemorySpecification& memSpec) +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + + const size_t numBanks = static_cast(memSpec.memArchSpec.nbrOfBanks); + ACT.resize(2 * numBanks); + RDWR.resize(2 * numBanks); + PRE.resize(numBanks); + bankaccess = memSpec.memArchSpec.nbrOfBanks; + if (!ACT.empty()) { + ACT.erase(ACT.begin(), ACT.end()); + } + if (!PRE.empty()) { + PRE.erase(PRE.begin(), PRE.end()); + } + if (!RDWR.empty()) { + RDWR.erase(RDWR.begin(), RDWR.end()); + } + + ///////////////initialization////////////// + for (int64_t i = 0; i < memSpec.memArchSpec.nbrOfBanks; i++) { + cmd.Type = PRECHARGE; + cmd.bank = static_cast(i); + cmd.name = "PRE"; + if (memSpec.id == "WIDEIO_SDR") { + cmd.time = 1 - memSpec.memTimingSpec.TAW; + } else { + cmd.time = 1 - memSpec.memTimingSpec.FAW; + } + + PRE.push_back(cmd); + + cmd.Type = ACTIVATE; + cmd.name = "ACT"; + ACT.push_back(cmd); + + cmd.Type = WRITE; + cmd.name = "WRITE"; + cmd.time = -1; + RDWR[static_cast(i)].push_back(cmd); + } + tREF = memTimingSpec.REFI; + transFinish.time = 0; + transFinish.bank = 0; + + PreRDWR.bank = -1; + PreRDWR.Type = READ; + PreRDWR.name = "RD"; + PreRDWR.time = -1; + startTime = 0; +} // cmdScheduler::schedulingInitialization + +// transactions are generated according to the information read from the traces. +// Then the command scheduling function is triggered to generate commands and +// schedule them to the memory according to the timing constraints. +void cmdScheduler::getTrans(std::ifstream& trans_trace, const MemorySpecification& memSpec) +{ + std::string line; + + transTime = 0; + uint64_t newtranstime; + uint64_t transAddr; + int64_t transType = 1; + trans TransItem; + + if (!transTrace.empty()) { + transTrace.erase(transTrace.begin(), transTrace.end()); + } + + while (getline(trans_trace, line)) { + istringstream linestream(line); + string item; + uint64_t itemnum = 0; + while (getline(linestream, item, ',')) { + if (itemnum == 0) { + stringstream timestamp(item); + timestamp >> newtranstime; + transTime = transTime + static_cast(newtranstime); + } else if (itemnum == 1) { + if (item == "write" || item == "WRITE") { + transType = WRITE; + } else { + transType = READ; + } + } else if (itemnum == 2) { + stringstream timestamp(item); + timestamp >> std::hex >> transAddr; + } + itemnum++; + } + // generate a transaction + TransItem.timeStamp = transTime; + TransItem.logicalAddress = transAddr; + TransItem.type = transType; + + transTrace.push_back(TransItem); + + if (transTrace.size() == MILLION) { + // The scheduling is implemented for every MILLION transactions. + // It is used to reduce the used memory during the running of this tool. + analyticalScheduling(memSpec); + transTrace.erase(transTrace.begin(), transTrace.end()); + } + } + + if ((transTrace.size() < MILLION) && (!transTrace.empty())) { + analyticalScheduling(memSpec); + transTrace.erase(transTrace.begin(), transTrace.end()); + } +} // cmdScheduler::getTrans + +// Transactions are executed individually and the command scheduling is +// independent between transactions. The commands for a new transaction cannot +// be scheduled until all the commands for the current one are scheduled. +// After the scheduling, a sequence of commands are obtained and they are written +// into commands.txt which will be used for power analysis. +void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec) +{ + int64_t transType = -1; + int64_t timer = 0; + uint64_t bankGroupPointer = 0; + uint64_t bankGroupAddr = 0; + bool collisionFound; + physicalAddr PhysicalAddress; + bool bankGroupSwitch = false; + std::vector bankPointer(static_cast(nbrOfBankGroups), 0); + std::vector bankAccessNum(static_cast(nBanks), -1); + std::vector ACTSchedule(static_cast(nBanks), false); + uint64_t bankAddr = 0; + int64_t endTime = 0; + int64_t tComing_REF = 0; + + Inselfrefresh = 0; + + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + + for (uint64_t t = 0; t < transTrace.size(); t++) { + cmdScheduling.erase(cmdScheduling.begin(), cmdScheduling.end()); + + for (auto a : ACTSchedule) { + a = false; + } + + for (auto& b : bankAccessNum) { + b = -1; + } + + timingsGet = false; + timer = transTrace[t].timeStamp; + + PhysicalAddress = memoryMap(transTrace[t], memSpec); + + for (auto& b : bankPointer) { + b = PhysicalAddress.bankAddr; // the bank pointer per group. + } + bankGroupPointer = PhysicalAddress.bankGroupAddr; + + endTime = max(transFinish.time, PRE[static_cast(transFinish.bank)].time + + static_cast(memTimingSpec.RP)); + + // Before starting the scheduling for the next transaction, it has to + // check whether it is necessary for implementing power down. + if (power_down == SELF_REFRESH) + pdScheduling(endTime, timer, memSpec); + else if (power_down == POWER_DOWN) + pdScheduling(endTime, min(timer, tREF), memSpec); + + tComing_REF = tREF; + + ///////////////Scheduling Refresh//////////////////////// + if (((transFinish.time >= tREF) || (timer >= tREF))) { + for (int64_t i = 0; i <= ((timer - tComing_REF) > 0 ? (timer - tComing_REF) / + memTimingSpec.REFI : 0); i++) { + cmd.bank = 0; + cmd.name = "REF"; + cmd.time = max(max(max(transFinish.time, PRE[static_cast(transFinish.bank)].time + memTimingSpec.RP), tREF), startTime); + if ((power_down == SELF_REFRESH && !Inselfrefresh) || power_down != SELF_REFRESH) { + cmdScheduling.push_back(cmd); + startTime = cmd.time + memTimingSpec.RFC; + } + tREF = tREF + memTimingSpec.REFI; + // during the refreshing, power down should be taken into account. + if (!Inselfrefresh) + pdScheduling(endTime, min(timer, tREF), memSpec); + } + } + ///////////////Execution Transactions/////////////////// + uint64_t Bs = PhysicalAddress.bankAddr; + transType = transTrace[t].type; + + tRWTP = getRWTP(transType, memSpec); + + for (int i = 0; i < BI; i++) { + for (int k = 0; k < BC; k++) { + if (memSpec.memoryType == MemoryType::DDR4) { + bankGroupPointer = PhysicalAddress.bankGroupAddr; + } + + for (int j = 0; j < BGI; j++) { + bankGroupSwitch = false; + if (memSpec.memoryType == MemoryType::DDR4) { + if (bankGroupPointer != bankGroupAddr) { + bankGroupSwitch = true; + } + // update to the current bank group address. + bankGroupAddr = PhysicalAddress.bankGroupAddr + static_cast(j); + bankAddr = bankGroupAddr * static_cast(nBanks) / nbrOfBankGroups + bankPointer[bankGroupAddr]; + } else { + bankAddr = Bs + i; + } + + if (!timingsGet) { + getTimingConstraints(bankGroupSwitch, memSpec, + PreRDWR.Type, transType); + } + + ////////////////ACT Scheduling/////////////////// + if (!ACTSchedule[bankAddr]) { + cmd.bank = bankAddr; + cmd.PhysicalAddr.bankAddr = cmd.bank; + cmd.PhysicalAddr.rowAddr = PhysicalAddress.rowAddr; + cmd.Type = ACTIVATE; + cmd.name = "ACT"; + Inselfrefresh = 0; + cmd.time = max(max(ACT[bankaccess - 1].time + tRRD_init, + PRE[cmd.bank].time + static_cast(memTimingSpec.RP)), + ACT[bankaccess - 4].time + + static_cast(memTimingSpec.FAW)); + + if (memSpec.memoryType == MemoryType::WIDEIO_SDR) { + cmd.time = max(max(ACT[bankaccess - 1].time + tRRD_init, + PRE[cmd.bank].time + static_cast(memTimingSpec.RP)), + ACT[bankaccess - 2].time + + static_cast(memTimingSpec.TAW)); + } + + if (i == 0 && j == 0) { + cmd.time = max(cmd.time, PreRDWR.time + 1); + cmd.time = max(cmd.time, timer); + cmd.time = max(startTime, cmd.time); + } + + //////////collision detection//////////////////// + for (int n = 1; n <= i * BGI + j; n++) { + collisionFound = false; + for (unsigned m = 0; m < RDWR[bankaccess - n].size(); m++) { + if (RDWR[bankaccess - n][m].time == cmd.time) { + cmd.time += 1; // ACT is shifted + collisionFound = true; + break; + } + } + if (collisionFound) { + break; + } + } + + ACT.push_back(cmd); + cmdScheduling.push_back(cmd); + + ACTSchedule[bankAddr] = true; + bankAccessNum[bankAddr] = bankaccess; + bankaccess++; + } + + /////RDWR Scheduling////// + cmd.bank = bankAddr; + cmd.PhysicalAddr.bankAddr = cmd.bank; + cmd.PhysicalAddr.rowAddr = PhysicalAddress.rowAddr; + cmd.PhysicalAddr.colAddr = PhysicalAddress.colAddr + k * burstLength; + cmd.Type = transType; + switch (transType) { + case READ: + cmd.name = "RD"; + break; + + case WRITE: + cmd.name = "WR"; + break; + } + for (int ACTBank = static_cast(ACT.size() - 1); + ACTBank >= 0; ACTBank--) { + if (ACT[ACTBank].bank == static_cast(bankAddr)) { + cmd.time = max(PreRDWR.time + tSwitch_init, ACT.back().time + + static_cast(memTimingSpec.RCD)); + break; + } + } + + if ((i == BI - 1) && (k == BC - 1) && (j == BGI - 1)) { + transFinish.time = cmd.time + 1; + transFinish.bank = bankAddr; + } + if (k == BC - 1) { + switch (transType) { + case READ: + cmd.name = "RDA"; + break; + + case WRITE: + cmd.name = "WRA"; + break; + } + } + PreRDWR = cmd; + + RDWR[bankAccessNum[bankAddr]].push_back(cmd); + cmdScheduling.push_back(cmd); + + ////////////////PRE Scheduling//////////////////// + if (k == BC - 1) { + PRE[bankAddr].bank = bankAddr; + PRE[bankAddr].Type = PRECHARGE; + PRE[bankAddr].name = "PRE"; + for (int ACTBank = static_cast(ACT.size() - 1); + ACTBank >= 0; ACTBank--) { + if (ACT[ACTBank].bank == static_cast(bankAddr)) { + PRE[bankAddr].time = max(ACT.back().time + + static_cast(memTimingSpec.RAS), + PreRDWR.time + tRWTP); + break; + } + } + bankPointer[bankGroupAddr] = bankPointer[bankGroupAddr] + 1; + } + + bankGroupPointer++; + } + } + } + + // make sure the scheduled commands are stored with an ascending scheduling time + sort(cmdScheduling.begin(), cmdScheduling.end(), + commandItem::commandItemSorter()); + + // write the scheduled commands into commands.txt. + for (unsigned i = 0; i < cmdScheduling.size(); i++) { + cmdList.push_back(cmdScheduling[i]); + } + + /////////////Update Vector Length///////////////// + // the vector length is reduced so that less memory is used for running + // this tool. + if (ACT.size() >= static_cast(memSpec.memArchSpec.nbrOfBanks)) { + for (int m = 0; m < BI * BGI; m++) { + ACT.erase(ACT.begin()); + RDWR[0].erase(RDWR[0].begin(), RDWR[0].end()); + for (int h = 0; h < bankaccess - 1 - m; h++) { + RDWR[h].insert(RDWR[h].begin(), RDWR[h + 1].begin(), RDWR[h + 1].end()); + RDWR[h + 1].resize(0); + } + } + bankaccess = bankaccess - (BI * BGI); + } + } + + for (unsigned j = 0; j < cmdList.size(); j++) { + commands.precision(0); + commands << fixed << cmdList[j].time << "," << cmdList[j].name << "," << + cmdList[j].bank << endl; + } + cmdList.erase(cmdList.begin(), cmdList.end()); +} // cmdScheduler::analyticalScheduling + +// to add the power down/up during the command scheduling for transactions. +// It is called when the command scheduling for a transaction is finished, and it +// is also called if there is a refresh. +void cmdScheduler::pdScheduling(int64_t endTime, int64_t timer, + const MemorySpecification& memSpec) +{ + int64_t ZERO = 0; + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + + endTime = max(endTime, startTime); + int64_t pdTime = max(ZERO, timer - endTime); + + if ((timer > (endTime + memTimingSpec.CKE)) && (power_down == POWER_DOWN)) { + cmd.bank = 0; + cmd.name = "PDN_S_PRE"; + cmd.time = endTime; + cmdScheduling.push_back(cmd); + cmd.name = "PUP_PRE"; + + if (pdTime > memTimingSpec.REFI) + cmd.time = cmd.time + memTimingSpec.REFI; + else + cmd.time = cmd.time + pdTime; + + if (memSpec.memoryType.isLPDDRFamily()) + startTime = cmd.time + memTimingSpec.XP; + else + startTime = cmd.time + memTimingSpec.XPDLL - memTimingSpec.RCD; + + cmdScheduling.push_back(cmd); + } else if ((timer > (endTime + memTimingSpec.CKESR)) && (power_down == SELF_REFRESH)) { + cmd.bank = 0; + cmd.name = "SREN"; + cmd.time = endTime; + cmdScheduling.push_back(cmd); + Inselfrefresh = 1; + cmd.name = "SREX"; + cmd.time = cmd.time + pdTime; + + if (memSpec.memoryType.isLPDDRFamily()) + startTime = cmd.time + memTimingSpec.XS; + else + startTime = cmd.time + memTimingSpec.XSDLL - memTimingSpec.RCD; + + cmdScheduling.push_back(cmd); + } +} // cmdScheduler::pdScheduling + +// get the time when a precharge occurs after a read/write command is scheduled. +// In addition, it copes with different kind of memories. +int64_t cmdScheduler::getRWTP(int64_t transType, const MemorySpecification& memSpec) +{ + int64_t tRWTP_init = 0; + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + + if (transType == READ) { + switch (memSpec.memoryType) { + case MemoryType::LPDDR: + case MemoryType::WIDEIO_SDR: + tRWTP_init = memArchSpec.burstLength / memArchSpec.dataRate; + break; + + case MemoryType::LPDDR2: + case MemoryType::LPDDR3: + tRWTP_init = memArchSpec.burstLength / memArchSpec.dataRate + + max(int64_t(0), memTimingSpec.RTP - 2); + break; + + case MemoryType::DDR2: + tRWTP_init = memTimingSpec.AL + memArchSpec.burstLength / + memArchSpec.dataRate + + max(memTimingSpec.RTP, int64_t(2)) - 2; + break; + + case MemoryType::DDR3: + case MemoryType::DDR4: + tRWTP_init = memTimingSpec.RTP; + break; + default: + assert("Unknown memory type" && false); + } // switch + } else if (transType == WRITE) { + if (memSpec.memoryType == MemoryType::WIDEIO_SDR) { + tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate - 1 + memTimingSpec.WR; + } else { + tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate + memTimingSpec.WR; + } + if ((memSpec.memoryType == MemoryType::LPDDR2) || + (memSpec.memoryType == MemoryType::LPDDR3)) { + tRWTP_init = tRWTP_init + 1; + } + } + + return tRWTP_init; +} // cmdScheduler::getRWTP + +// get the timings for command scheduling according to different memories. +// In particular, tSwitch_init is generally used to provide the timings for +// scheduling a read/write command after a read/write command which have been +// scheduled to any possible banks within any possible bank groups (DDR4). +void cmdScheduler::getTimingConstraints(bool BGSwitch, const MemorySpecification& memSpec, + int64_t PreType, int64_t CurrentType) +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + + if (memSpec.memoryType != MemoryType::DDR4) { + tRRD_init = memTimingSpec.RRD; + if (PreType == CurrentType) { + tSwitch_init = memTimingSpec.CCD; + timingsGet = true; + } + + if ((PreType == WRITE) && (CurrentType == READ)) { + if (memSpec.memoryType == MemoryType::WIDEIO_SDR) { + tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate - 1 + memTimingSpec.WTR; + } else { + tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate + memTimingSpec.WTR; + } + + if ((memSpec.memoryType == MemoryType::LPDDR2) || + (memSpec.memoryType == MemoryType::LPDDR3)) { + tSwitch_init = tSwitch_init + 1; + } + } + } + + if (memSpec.memoryType == MemoryType::DDR4) { + if (BGSwitch) { + tCCD_init = memTimingSpec.CCD_S; + tRRD_init = memTimingSpec.RRD_S; + tWTR_init = memTimingSpec.WTR_S; + } else { + tCCD_init = memTimingSpec.CCD_L; + tRRD_init = memTimingSpec.RRD_L; + tWTR_init = memTimingSpec.WTR_L; + } + + if (PreType == CurrentType) { + tSwitch_init = tCCD_init; + timingsGet = true; + } else if (PreType == WRITE && CurrentType == READ) { + tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength / + memArchSpec.dataRate + tWTR_init; + } + } + + if ((PreType == READ) && (CurrentType == WRITE)) { + tSwitch_init = memTimingSpec.RL + memArchSpec.burstLength / + memArchSpec.dataRate + 2 - memTimingSpec.WL; + } +} // cmdScheduler::getTimingConstraints + +// The logical address of each transaction is translated into a physical address +// which consists of bank group (for DDR4), bank, row and column addresses. +cmdScheduler::physicalAddr cmdScheduler::memoryMap(trans Trans, + const MemorySpecification& memSpec) +{ + int64_t DecLogic; + physicalAddr PhysicalAddr; + + DecLogic = Trans.logicalAddress; + + // row-bank-column-BI-BC-BGI-BL + if (BGI > 1 && memSpec.memoryType == MemoryType::DDR4) { + uint64_t colBits = uintLog2(nColumns); + uint64_t bankShift = colBits + ((BI > 1) ? uintLog2(BI) : 0) + ((BGI > 1) ? uintLog2(BGI) : 0); + uint64_t bankMask = (nBanks / (BI * nbrOfBankGroups) - 1) << bankShift; + uint64_t bankAddr = (DecLogic & bankMask) >> (colBits + ((BGI > 1) ? uintLog2(BGI) : 0)); + PhysicalAddr.bankAddr = bankAddr; + + uint64_t bankGroupShift = uintLog2(burstLength); + uint64_t bankGroupMask = (nbrOfBankGroups / BGI - 1) << bankGroupShift; + uint64_t bankGroupAddr = (DecLogic & bankGroupMask) >> bankGroupShift; + PhysicalAddr.bankGroupAddr = bankGroupAddr; + + uint64_t colShift = uintLog2(BC * burstLength) + + ((BI > 1) ? uintLog2(BI) : 0) + ((BGI > 1) ? uintLog2(BGI) : 0); + uint64_t colMask = (nColumns / (BC * burstLength) - 1) << colShift; + uint64_t colAddr = (DecLogic & colMask) >> (colShift - uintLog2(static_cast(BC) * burstLength)); + PhysicalAddr.colAddr = colAddr; + } else { + uint64_t colBits = uintLog2(nColumns); + uint64_t bankShift = colBits + ((BI > 1) ? uintLog2(BI) : 0); + uint64_t bankMask = (nBanks / BI - 1) << bankShift; + uint64_t bankAddr = (DecLogic & bankMask) >> colBits; + PhysicalAddr.bankAddr = bankAddr; + + uint64_t colShift = (uintLog2(BC * burstLength) + ((BI > 1) ? uintLog2(BI) : 0)); + uint64_t colMask = (nColumns / (BC * burstLength) - 1) << colShift; + uint64_t colAddr = (DecLogic & colMask) >> (colShift - uintLog2(BC * burstLength)); + PhysicalAddr.colAddr = colAddr; + + PhysicalAddr.bankGroupAddr = 0; + } + + uint64_t rowShift = uintLog2(nColumns * nBanks); + uint64_t rowMask = (memSpec.memArchSpec.nbrOfRows - 1) << rowShift; + uint64_t rowAddr = (DecLogic & rowMask) >> rowShift; + PhysicalAddr.rowAddr = rowAddr; + + return PhysicalAddr; +} // cmdScheduler::memoryMap + +uint64_t cmdScheduler::uintLog2(uint64_t in) +{ + return static_cast(log2(in)); +} \ No newline at end of file diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdScheduler.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdScheduler.h new file mode 100644 index 0000000000..58efd279b1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/CmdScheduler.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#ifndef CMDSCHEDULER_H +#define CMDSCHEDULER_H + +#include +#include +#include // for binary_function<> +#include + +#include "MemorySpecification.h" +#include "Utils.h" + +namespace Data { +class cmdScheduler { + public: + #define READ 0 + #define WRITE 1 + #define ACTIVATE 2 + #define PRECHARGE 3 + #define POWER_DOWN 1 + #define SELF_REFRESH 2 + + // the format of a transaction. + class trans { + public: + int64_t type; + int64_t timeStamp; + uint64_t logicalAddress; + }; + + std::vector transTrace; // to store the transactions. + + // the format of physical address. + class physicalAddr { + public: + uint64_t rowAddr; + uint64_t bankAddr; + uint64_t bankGroupAddr; + uint64_t colAddr; + }; + + // the format of a command. + class commandItem { + public: + int64_t Type; + int64_t bank; + int64_t time; + std::string name; + physicalAddr PhysicalAddr; + // sorting the commands according to their scheduling time. + struct commandItemSorter : public std::binary_function{ + bool operator()(const commandItem& lhs, + const commandItem& rhs) const + { + return lhs.time < rhs.time; + } + }; + }; + + commandItem cmd; + commandItem transFinish; // the last scheduled command for a transaction. + commandItem PreRDWR; // the latest scheduled READ or WRITE command. + // the scheduled ACTIVATE commands are stored in ACT. + std::vector ACT; + // PRE is sued to keep recording the time when a precharge occurs. + std::vector PRE; + // the scheduled READ or WRITE commands are stored in RDWR. + std::vector > RDWR; + // all the scheduled commands for a transaction is stored by cmdScheduling. + std::vector cmdScheduling; + std::vector cmdList; + unsigned elements; + int64_t BI, BC, BGI; + + // the function used to translate a transaction into a sequence of + // commands which are scheduled to the memory. + void transTranslation(const MemorySpecification& memSpec, + std::ifstream& trans_trace, + int grouping, + int interleaving, + int burst, + int powerdown); + // get the transactions by reading the traces. + void getTrans(std::ifstream& pwr_trace, + const MemorySpecification& memSpec); + // the initialization function for scheduling. + void schedulingInitialization(const MemorySpecification& memSpec); + // the function used to schedule commands according to the timing constraints. + void analyticalScheduling(const MemorySpecification& memSpec); + // translate the logical address into physical address. + physicalAddr memoryMap(trans Trans, + const MemorySpecification& memSpec); + // the power down and power up are scheduled by pdScheduling + void pdScheduling(int64_t endTime, + int64_t timer, + const MemorySpecification& memSpec); + // get the timings for scheduling a precharge since a read or write command + // is scheduled. + int64_t getRWTP(int64_t transType, + const MemorySpecification& memSpec); + // get different kind of timing constraints according to the used memory. + void getTimingConstraints(bool BGSwitch, + const MemorySpecification& memSpec, + int64_t PreType, + int64_t CurrentType); + + uint64_t uintLog2(uint64_t in); + + int64_t transTime; + // the flag for power down. + int64_t power_down; + int64_t Inselfrefresh; + int64_t tRRD_init; + int64_t tCCD_init; + int64_t tWTR_init; + int64_t tREF; + int64_t tSwitch_init; + int64_t tRWTP; + int64_t bankaccess; + int64_t nBanks; + int64_t nColumns; + int64_t burstLength; + int64_t nbrOfBankGroups; + bool timingsGet; + int64_t startTime; + + // the scheduling results for all the transactions are written into + // commands which will be used by the power analysis part. + std::ofstream commands; +}; +} + +#endif // ifndef CMDSCHEDULER_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/CommandAnalysis.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/CommandAnalysis.cc new file mode 100644 index 0000000000..b840ab53c3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/CommandAnalysis.cc @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, + * Matthias Jung, + * Omar Naji, + * Sven Goossens, + * Éder F. Zulian + * Subash Kannoth + * Felipe S. Prado + * + */ + +#include +#include +#include + +#include "CommandAnalysis.h" +#include "CmdScheduler.h" + +using namespace Data; +using namespace std; + +bool commandSorter(const MemCommand& i, const MemCommand& j) +{ + if (i.getTimeInt64() == j.getTimeInt64()) { + return i.getType() == MemCommand::PRE && j.getType() != MemCommand::PRE; + } else { + return i.getTimeInt64() < j.getTimeInt64(); + } +} + +CommandAnalysis::CommandAnalysis(const Data::MemorySpecification& memSpec) : + memSpec(memSpec) + +{ + auto &nBanks = memSpec.memArchSpec.nbrOfBanks; + // Initializing all counters and variables + numberofactsBanks.assign(static_cast(nBanks), 0); + numberofpresBanks.assign(static_cast(nBanks), 0); + numberofreadsBanks.assign(static_cast(nBanks), 0); + numberofwritesBanks.assign(static_cast(nBanks), 0); + actcyclesBanks.assign(static_cast(nBanks), 0); + numberofrefbBanks.assign(static_cast(nBanks), 0); + + first_act_cycle_banks.resize(static_cast(nBanks), 0); + + clearStats(0); + zero = 0; + + bank_state.resize(static_cast(nBanks), BANK_PRECHARGED); + last_bank_state.resize(static_cast(nBanks), BANK_PRECHARGED); + mem_state = MS_NOT_IN_PD; + + cmd_list.clear(); + cached_cmd.clear(); + activation_cycle.resize(static_cast(nBanks), 0); + num_banks = nBanks; +} + +// function to clear counters +void CommandAnalysis::clearStats(const int64_t timestamp) +{ + std::fill(numberofactsBanks.begin(), numberofactsBanks.end(), 0); + std::fill(numberofpresBanks.begin(), numberofpresBanks.end(), 0); + std::fill(numberofreadsBanks.begin(), numberofreadsBanks.end(), 0); + std::fill(numberofwritesBanks.begin(), numberofwritesBanks.end(), 0); + std::fill(actcyclesBanks.begin(), actcyclesBanks.end(), 0); + + numberofrefs = 0; + f_act_pdns = 0; + s_act_pdns = 0; + f_pre_pdns = 0; + s_pre_pdns = 0; + numberofsrefs = 0; + + actcycles = 0; + precycles = 0; + f_act_pdcycles = 0; + s_act_pdcycles = 0; + f_pre_pdcycles = 0; + s_pre_pdcycles = 0; + pup_act_cycles = 0; + pup_pre_cycles = 0; + sref_cycles = 0; + spup_cycles = 0; + sref_ref_act_cycles = 0; + sref_ref_pre_cycles = 0; + spup_ref_act_cycles = 0; + spup_ref_pre_cycles = 0; + idlecycles_act = 0; + idlecycles_pre = 0; + + // reset count references to timestamp so that they are moved + // to start of next stats generation + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); + first_act_cycle = timestamp; + + pdn_cycle = timestamp; + sref_cycle_window = timestamp; + + end_act_op = timestamp; + end_read_op = timestamp; + end_write_op = timestamp; + + latest_read_cycle = -1; + latest_write_cycle = -1; + + if (timestamp == 0) { + latest_pre_cycle = -1; + latest_act_cycle = -1; + sref_cycle = 0; + last_pre_cycle = 0; + sref_ref_act_cycles_window = 0; + sref_ref_pre_cycles_window = 0; + } else { + last_pre_cycle = max(timestamp,last_pre_cycle); + + latest_pre_cycle = max(timestamp, latest_pre_cycle); + + if (latest_act_cycle < timestamp) + latest_act_cycle = -1; + } +} + +// function to clear all arrays +void CommandAnalysis::clear() +{ + cached_cmd.clear(); + cmd_list.clear(); + last_bank_state.clear(); + bank_state.clear(); +} + +// Reads through the trace file, identifies the timestamp, command and bank +// If the issued command includes an auto-precharge, adds an explicit +// precharge to a cached command list and computes the precharge offset from the +// issued command timestamp, when the auto-precharge would kick in + +void CommandAnalysis::getCommands(std::vector& list, bool lastupdate, int64_t timestamp) +{ + if (!next_window_cmd_list.empty()) { + list.insert(list.begin(), next_window_cmd_list.begin(), next_window_cmd_list.end()); + next_window_cmd_list.clear(); + } + for (size_t i = 0; i < list.size(); ++i) { + MemCommand& cmd = list[i]; + MemCommand::cmds cmdType = cmd.getType(); + if (cmdType == MemCommand::ACT) { + activation_cycle[cmd.getBank()] = cmd.getTimeInt64(); + } else if (cmdType == MemCommand::RDA || cmdType == MemCommand::WRA) { + // Remove auto-precharge flag from command + cmd.setType(cmd.typeWithoutAutoPrechargeFlag()); + + // Add the auto precharge to the list of cached_cmds + int64_t preTime = max(cmd.getTimeInt64() + cmd.getPrechargeOffset(memSpec, cmdType), + activation_cycle[cmd.getBank()] + memSpec.memTimingSpec.RAS); + list.push_back(MemCommand(MemCommand::PRE, cmd.getBank(), preTime)); + } + + if (!lastupdate && timestamp > 0) { + if(cmd.getTimeInt64() > timestamp) + { + MemCommand nextWindowCmd = list[i]; + next_window_cmd_list.push_back(nextWindowCmd); + list.erase(find(list.begin(), list.end(), cmd)); + } + } + } + sort(list.begin(), list.end(), commandSorter); + + if (lastupdate && list.empty() == false) { + // Add cycles at the end of the list + int64_t t = timeToCompletion(list.back().getType()) + list.back().getTimeInt64() - 1; + list.push_back(MemCommand(MemCommand::NOP, 0, t)); + } + + evaluateCommands(list); +} // CommandAnalysis::getCommands + + +// Used to analyse a given list of commands and identify command timings +// and memory state transitions +void CommandAnalysis::evaluateCommands(vector& cmd_list) +{ + // for each command identify timestamp, type and bank + for (auto cmd : cmd_list) { + // For command type + int type = cmd.getType(); + // For command bank + unsigned bank = cmd.getBank(); + // Command Issue timestamp in clock cycles (cc) + int64_t timestamp = cmd.getTimeInt64(); + + if (type == MemCommand::ACT) { + handleAct(bank, timestamp); + } else if (type == MemCommand::RD) { + handleRd(bank, timestamp); + } else if (type == MemCommand::WR) { + handleWr(bank, timestamp); + } else if (type == MemCommand::REF) { + handleRef(bank, timestamp); + } else if (type == MemCommand::REFB) { + handleRefB(bank, timestamp); + } else if (type == MemCommand::PRE) { + handlePre(bank, timestamp); + } else if (type == MemCommand::PREA) { + handlePreA(bank, timestamp); + } else if (type == MemCommand::PDN_F_ACT) { + handlePdnFAct(bank, timestamp); + } else if (type == MemCommand::PDN_S_ACT) { + handlePdnSAct(bank, timestamp); + } else if (type == MemCommand::PDN_F_PRE) { + handlePdnFPre(bank, timestamp); + } else if (type == MemCommand::PDN_S_PRE) { + handlePdnSPre(bank, timestamp); + } else if (type == MemCommand::PUP_ACT) { + handlePupAct(timestamp); + } else if (type == MemCommand::PUP_PRE) { + handlePupPre(timestamp); + } else if (type == MemCommand::SREN) { + handleSREn(bank, timestamp); + } else if (type == MemCommand::SREX) { + handleSREx(bank, timestamp); + } else if (type == MemCommand::END || type == MemCommand::NOP) { + handleNopEnd(timestamp); + } else { + printWarning("Unknown command given, exiting.", type, timestamp, bank); + exit(-1); + } + } +} // CommandAnalysis::evaluateCommands + +// To update idle period information whenever active cycles may be idle +void CommandAnalysis::idle_act_update(int64_t latest_read_cycle, int64_t latest_write_cycle, + int64_t latest_act_cycle, int64_t timestamp) +{ + if (latest_read_cycle >= 0) { + end_read_op = latest_read_cycle + timeToCompletion(MemCommand::RD) - 1; + } + + if (latest_write_cycle >= 0) { + end_write_op = latest_write_cycle + timeToCompletion(MemCommand::WR) - 1; + } + + if (latest_act_cycle >= 0) { + end_act_op = latest_act_cycle + timeToCompletion(MemCommand::ACT) - 1; + } + + idlecycles_act += max(zero, timestamp - max(max(end_read_op, end_write_op), + end_act_op)); +} // CommandAnalysis::idle_act_update + +// To update idle period information whenever precharged cycles may be idle +void CommandAnalysis::idle_pre_update(int64_t timestamp, int64_t latest_pre_cycle) +{ + if (latest_pre_cycle > 0) { + idlecycles_pre += max(zero, timestamp - latest_pre_cycle - + memSpec.memTimingSpec.RP); + } else if (latest_pre_cycle == 0) { + idlecycles_pre += max(zero, timestamp - latest_pre_cycle); + } +} + diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/CommandAnalysis.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/CommandAnalysis.h new file mode 100644 index 0000000000..6161e687b1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/CommandAnalysis.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#ifndef COMMAND_TIMINGS_H +#define COMMAND_TIMINGS_H + +#include + +#include +#include +#include +#include + +#include "MemCommand.h" +#include "MemorySpecification.h" +#include "Utils.h" + +namespace Data { +class CommandAnalysis { + public: + // Power-Down and Self-refresh related memory states + enum memstate { + MS_NOT_IN_PD = 0, MS_PDN_F_ACT = 10, MS_PDN_S_ACT = 11, MS_PDN_F_PRE = 12, + MS_PDN_S_PRE = 13, MS_SREF = 14 + }; + + // Returns number of reads, writes, acts, pres and refs in the trace + CommandAnalysis(const MemorySpecification& memSpec); + + // Number of activate commands per bank + std::vector numberofactsBanks; + // Number of precharge commands per bank + std::vector numberofpresBanks; + // Number of reads commands per bank + std::vector numberofreadsBanks; + // Number of writes commands per bank + std::vector numberofwritesBanks; + // Number of refresh commands + int64_t numberofrefs; + // Number of bankwise refresh commands + std::vector numberofrefbBanks; + // Number of precharge cycles + int64_t precycles; + // Number of active cycles + int64_t actcycles; + std::vector actcyclesBanks; + // Number of Idle cycles in the active state + int64_t idlecycles_act; + // Number of Idle cycles in the precharge state + int64_t idlecycles_pre; + // Number of fast-exit activate power-downs + int64_t f_act_pdns; + // Number of slow-exit activate power-downs + int64_t s_act_pdns; + // Number of fast-exit precharged power-downs + int64_t f_pre_pdns; + // Number of slow-exit activate power-downs + int64_t s_pre_pdns; + // Number of self-refresh commands + int64_t numberofsrefs; + // Number of clock cycles in fast-exit activate power-down mode + int64_t f_act_pdcycles; + // Number of clock cycles in slow-exit activate power-down mode + int64_t s_act_pdcycles; + // Number of clock cycles in fast-exit precharged power-down mode + int64_t f_pre_pdcycles; + // Number of clock cycles in slow-exit precharged power-down mode + int64_t s_pre_pdcycles; + // Number of clock cycles in self-refresh mode (excludes the initial + // auto-refresh). During this time the current drawn is IDD6. + int64_t sref_cycles; + // Number of clock cycles in activate power-up mode + int64_t pup_act_cycles; + // Number of clock cycles in precharged power-up mode + int64_t pup_pre_cycles; + // Number of clock cycles in self-refresh power-up mode + int64_t spup_cycles; + + // Number of active cycles for the initial auto-refresh when entering + // self-refresh mode. + int64_t sref_ref_act_cycles; + // Number of active auto-refresh cycles in self-refresh mode already used to calculate the energy of the previous windows + int64_t sref_ref_act_cycles_window; + // Number of precharged auto-refresh cycles in self-refresh mode + int64_t sref_ref_pre_cycles; + // Number of precharged auto-refresh cycles in self-refresh mode already used to calculate the energy of the previous window + int64_t sref_ref_pre_cycles_window; + // Number of active auto-refresh cycles during self-refresh exit + int64_t spup_ref_act_cycles; + // Number of precharged auto-refresh cycles during self-refresh exit + int64_t spup_ref_pre_cycles; + + // function for clearing counters + void clearStats(const int64_t timestamp); + + // function for clearing arrays + void clear(); + + // To identify auto-precharges + void getCommands(std::vector& list, + bool lastupdate, + int64_t timestamp = 0); + + private: + MemorySpecification memSpec; + + // Possible bank states are precharged or active + enum BankState { + BANK_PRECHARGED = 0, + BANK_ACTIVE + }; + + int64_t zero; + // Cached last read command from the file + std::vector cached_cmd; + + // Stores the memory commands for analysis + std::vector cmd_list; + + //Stores the memory commands for the next window + std::vector next_window_cmd_list; + + // To save states of the different banks, before entering active + // power-down mode (slow/fast-exit). + std::vector last_bank_state; + // Bank state vector + std::vector bank_state; + + std::vector activation_cycle; + // To keep track of the last ACT cycle + int64_t latest_act_cycle; + // To keep track of the last PRE cycle + int64_t latest_pre_cycle; + // To keep track of the last READ cycle + int64_t latest_read_cycle; + // To keep track of the last WRITE cycle + int64_t latest_write_cycle; + + // To calculate end of READ operation + int64_t end_read_op; + // To calculate end of WRITE operation + int64_t end_write_op; + // To calculate end of ACT operation + int64_t end_act_op; + + // Clock cycle when self-refresh was issued + int64_t sref_cycle; + + // Latest Self-Refresh clock cycle used to calculate the energy of the previous window + int64_t sref_cycle_window; + + // Clock cycle when the latest power-down was issued + int64_t pdn_cycle; + + // Memory State + unsigned mem_state; + + int64_t num_banks; + + // Clock cycle of first activate command when memory state changes to ACT + int64_t first_act_cycle; + std::vector first_act_cycle_banks; + + // Clock cycle of last precharge command when memory state changes to PRE + int64_t last_pre_cycle; + + // To perform timing analysis of a given set of commands and update command counters + void evaluateCommands(std::vector& cmd_list); + + // Handlers for commands that are getting processed + void handleAct( unsigned bank, int64_t timestamp); + void handleRd( unsigned bank, int64_t timestamp); + void handleWr( unsigned bank, int64_t timestamp); + void handleRef( unsigned bank, int64_t timestamp); + void handleRefB(unsigned bank, int64_t timestamp); + void handlePre( unsigned bank, int64_t timestamp); + void handlePreA( unsigned bank, int64_t timestamp); + void handlePdnFAct(unsigned bank, int64_t timestamp); + void handlePdnSAct(unsigned bank, int64_t timestamp); + void handlePdnFPre(unsigned bank, int64_t timestamp); + void handlePdnSPre(unsigned bank, int64_t timestamp); + void handlePupAct( int64_t timestamp); + void handlePupPre( int64_t timestamp); + void handleSREn( unsigned bank, int64_t timestamp); + void handleSREx( unsigned bank, int64_t timestamp); + void handleNopEnd( int64_t timestamp); + + // To calculate time of completion of any issued command + int64_t timeToCompletion(MemCommand::cmds type); + + // To update idle period information whenever active cycles may be idle + void idle_act_update(int64_t latest_read_cycle, + int64_t latest_write_cycle, + int64_t latest_act_cycle, + int64_t timestamp); + + // To update idle period information whenever precharged cycles may be idle + void idle_pre_update(int64_t timestamp, + int64_t latest_pre_cycle); + + // Returns the number of active banks according to the bank_state vector. + unsigned get_num_active_banks(void); + unsigned nActiveBanks(void); + + bool isPrecharged(unsigned bank); + + void printWarningIfActive(const std::string& warning, int type, int64_t timestamp, unsigned bank); + void printWarningIfNotActive(const std::string& warning, int type, int64_t timestamp, unsigned bank); + void printWarningIfPoweredDown(const std::string& warning, int type, int64_t timestamp, unsigned bank); + void printWarning(const std::string& warning, int type, int64_t timestamp, unsigned bank); +}; +} +#endif // ifndef COMMAND_TIMINGS_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemArchitectureSpec.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemArchitectureSpec.cc new file mode 100644 index 0000000000..f3155853d7 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemArchitectureSpec.cc @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemArchitectureSpec.h" + +#include + +using namespace Data; + +MemArchitectureSpec::MemArchitectureSpec() : + burstLength(0), + nbrOfBanks(0), + nbrOfRanks(0), + dataRate(0), + nbrOfColumns(0), + nbrOfRows(0), + width(0), + nbrOfBankGroups(0), + dll(false), + twoVoltageDomains(false), + termination(false) +{ +} + +void MemArchitectureSpec::processParameters() +{ + // Load all parameters in our member variables + nbrOfBanks = getParamValWithDefault("nbrOfBanks", 1); + nbrOfRanks = getParamValWithDefault("nbrOfRanks", 1); + nbrOfBankGroups = getParamValWithDefault("nbrOfBankGroups", 1); + dataRate = getParamValWithDefault("dataRate", 1); + burstLength = getParamValWithDefault("burstLength", 1); + nbrOfColumns = getParamValWithDefault("nbrOfColumns", 1); + nbrOfRows = getParamValWithDefault("nbrOfRows", 1); + width = getParamValWithDefault("width", 1); + assert("memory width should be a multiple of 8" && (width % 8) == 0); + dll = getParamValWithDefault("dll", false); + twoVoltageDomains = getParamValWithDefault("twoVoltageDomains", false); + termination = getParamValWithDefault("termination", false); +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemArchitectureSpec.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemArchitectureSpec.h new file mode 100644 index 0000000000..49eddc8ac1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemArchitectureSpec.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, Sven Goossens + * + */ + +#ifndef TOOLS_MEM_ARCHITECTURE_SPEC_H +#define TOOLS_MEM_ARCHITECTURE_SPEC_H + +#include + +#include "Parametrisable.h" + +namespace Data { +class MemArchitectureSpec : public virtual Parametrisable { + public: + MemArchitectureSpec(); + void processParameters(); + + int64_t burstLength; + int64_t nbrOfBanks; + int64_t nbrOfRanks; + int64_t dataRate; + int64_t nbrOfColumns; + int64_t nbrOfRows; + int64_t width; + int64_t nbrOfBankGroups; + bool dll; + bool twoVoltageDomains; + bool termination; +}; +} +#endif // ifndef TOOLS_MEM_ARCHITECTURE_SPEC_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemBankWiseParams.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemBankWiseParams.cc new file mode 100644 index 0000000000..c13281688c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemBankWiseParams.cc @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2016, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Subash Kannoth, Matthias Jung, Éder F. Zulian + * + */ + +#include "MemBankWiseParams.h" + +using namespace Data; +/** + * Sets the default bankwise configurations. + */ +MemBankWiseParams::MemBankWiseParams(): + bwPowerFactRho(100), + bwPowerFactSigma(100), + bwMode(false), + flgPASR(false) +{ +} +/** + * Sets all the bankwise parameters required in bankwise mode + */ +MemBankWiseParams::MemBankWiseParams(int64_t factRho, int64_t factSigma, + bool hasPASR, int64_t pasrMode, + bool opMode, unsigned nbrofBanks) +{ + + bwPowerFactRho = factRho; + bwPowerFactSigma = factSigma; + bwMode = opMode; + flgPASR = hasPASR; + /////////////////////////////////////////////////////////// + // Activate banks for self refresh based on the PASR mode + // ACTIVE - X + // NOT ACTIVE - 0 + /////////////////////////////////////////////////////////// + switch(pasrMode){ + + case(PASR_0):{ + // PASR MODE 0 + // FULL ARRAY + // |X X X X | + // |X X X X | + activeBanks.resize(nbrofBanks); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_1):{ + // PASR MODE 1 + // (1/2) ARRAY + // |X X X X | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 4); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_2):{ + // PASR MODE 2 + // (1/4) ARRAY + // |X X 0 0 | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 6); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_3):{ + // PASR MODE 3 + // (1/8) ARRAY + // |X 0 0 0 | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 7); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_4):{ + // PASR MODE 4 + // (3/4) ARRAY + // |0 0 X X | + // |X X X X | + activeBanks.resize(nbrofBanks - 2); + std::iota(activeBanks.begin(), activeBanks.end(), 2); + break; + } + case(PASR_5):{ + // PASR MODE 5 + // (1/2) ARRAY + // |0 0 0 0 | + // |X X X X | + activeBanks.resize(nbrofBanks - 4); + std::iota(activeBanks.begin(), activeBanks.end(), 4); + break; + } + case(PASR_6):{ + // PASR MODE 6 + // (1/4) ARRAY + // |0 0 0 0 | + // |0 0 X X | + activeBanks.resize(nbrofBanks - 6); + std::iota(activeBanks.begin(), activeBanks.end(), 6); + break; + } + case(PASR_7):{ + // PASR MODE 7 + // (1/8) ARRAY + // |0 0 0 0 | + // |0 0 0 X | + activeBanks.resize(nbrofBanks - 7); + std::iota(activeBanks.begin(), activeBanks.end(), 7); + break; + } + default:{ + // PASR MODE 0 + // FULL ARRAY + // |X X X X | + // |X X X X | + activeBanks.resize(nbrofBanks); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + } +} + +/** + * Returns true if the given bank is active under the current PASR mode. + */ +bool MemBankWiseParams::isBankActiveInPasr(const unsigned bankIdx) const +{ + return (std::find(activeBanks.begin(), activeBanks.end(), bankIdx) + != activeBanks.end()); +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemBankWiseParams.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemBankWiseParams.h new file mode 100644 index 0000000000..0cc98fb46f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemBankWiseParams.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2016, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Subash Kannoth, Matthias Jung, Eder Zulian + * + */ +#ifndef MEMBANKWISEPARAMS_H +#define MEMBANKWISEPARAMS_H + +#include +#include +#include +#include + +namespace Data { + class MemBankWiseParams { + public: + // Set of possible PASR modes + enum pasrModes{ + PASR_0, + PASR_1, + PASR_2, + PASR_3, + PASR_4, + PASR_5, + PASR_6, + PASR_7 + }; + // List of active banks under the specified PASR mode + std::vector activeBanks; + // ACT Standby power factor + int64_t bwPowerFactRho; + // Self-Refresh power factor( true : Bankwise mode) + int64_t bwPowerFactSigma; + // Bankwise or Normal mode + bool bwMode; + // Wherther PASR is enabled ( true : enabled ) + bool flgPASR; + //Default constructor + MemBankWiseParams(); + MemBankWiseParams(int64_t factRho, int64_t factSigma, + bool hasPASR, int64_t pasrMode, + bool opMode, unsigned nbrofBanks); + + bool isBankActiveInPasr(const unsigned bankIdx) const; + }; +} + +#endif // MEMBANKWISEPARAMS_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemCommand.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemCommand.cc new file mode 100644 index 0000000000..5e1115e050 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemCommand.cc @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemCommand.h" + +#include // for max + +#include "MemorySpecification.h" + +using namespace Data; +using namespace std; + + +MemCommand::MemCommand(MemCommand::cmds type, + unsigned bank, int64_t timestamp) : + type(type), + bank(bank), + timestamp(timestamp) +{ +} + +void MemCommand::setType(MemCommand::cmds _type) +{ + type = _type; +} + +MemCommand::cmds MemCommand::getType() const +{ + return type; +} + +void MemCommand::setBank(unsigned _bank) +{ + bank = _bank; +} + +unsigned MemCommand::getBank() const +{ + return bank; +} + +// For auto-precharge with read or write - to calculate cycle of precharge +int64_t MemCommand::getPrechargeOffset(const MemorySpecification& memSpec, + MemCommand::cmds type) const +{ + int64_t precharge_offset = 0; + + int64_t BL = memSpec.memArchSpec.burstLength; + int64_t RTP = memSpec.memTimingSpec.RTP; + int64_t dataRate = memSpec.memArchSpec.dataRate; + int64_t AL = memSpec.memTimingSpec.AL; + int64_t WL = memSpec.memTimingSpec.WL; + int64_t WR = memSpec.memTimingSpec.WR; + int64_t B = BL/dataRate; + + const MemoryType::MemoryType_t& memType = memSpec.memoryType; + + // Read with auto-precharge + if (type == MemCommand::RDA) { + if (memType == MemoryType::DDR2) { + precharge_offset = B + AL - 2 + max(RTP, int64_t(2)); + } else if (memType == MemoryType::DDR3) { + precharge_offset = AL + max(RTP, int64_t(4)); + } else if (memType == MemoryType::DDR4) { + precharge_offset = AL + RTP; + } else if (memType == MemoryType::LPDDR) { + precharge_offset = B; + } else if (memType == MemoryType::LPDDR2) { + precharge_offset = B + max(int64_t(0), RTP - 2); + } else if (memType == MemoryType::LPDDR3) { + precharge_offset = B + max(int64_t(0), RTP - 4); + } else if (memType == MemoryType::WIDEIO_SDR) { + precharge_offset = B; + } + } else if (type == MemCommand::WRA) { // Write with auto-precharge + if (memType == MemoryType::DDR2) { + precharge_offset = B + WL + WR; + } else if (memType == MemoryType::DDR3) { + precharge_offset = B + WL + WR; + } else if (memType == MemoryType::DDR4) { + precharge_offset = B + WL + WR; + } else if (memType == MemoryType::LPDDR) { + precharge_offset = B + WR; // + DQSS actually, but we don't have that parameter. + } else if (memType == MemoryType::LPDDR2) { + precharge_offset = B + WL + WR + 1; + } else if (memType == MemoryType::LPDDR3) { + precharge_offset = B + WL + WR + 1; + } else if (memType == MemoryType::WIDEIO_SDR) { + precharge_offset = B + WL + WR - 1; + } + } + + return precharge_offset; +} // MemCommand::getPrechargeOffset + +void MemCommand::setTime(int64_t _timestamp) +{ + timestamp = _timestamp; +} + +int64_t MemCommand::getTimeInt64() const +{ + return timestamp; +} + +MemCommand::cmds MemCommand::typeWithoutAutoPrechargeFlag() const +{ + if (type == MemCommand::RDA) { + return MemCommand::RD; + } else if (type == MemCommand::WRA) { + return MemCommand::WR; + } + return type; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemCommand.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemCommand.h new file mode 100644 index 0000000000..3d7b70b5fe --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemCommand.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#ifndef MEMCOMMAND_H +#define MEMCOMMAND_H + +#include +#include +#include + +#include "MemorySpecification.h" + +namespace Data { +class MemCommand { + public: + /* + * 1. ACT - Activate + * 2. RD - Read + * 3. WR - Write + * 4. PRE - Explicit Precharge per bank + * 5. REF - Refresh all banks + * 6 REFB- Refresh a particular bank + * 7. END - To indicate end of trace + * 8. RDA - Read with auto-precharge + * 9. WRA - Write with auto-precharge + * 10. PREA - Precharge all banks + * 11. PDN_F_PRE - Precharge Power-down Entry command (Fast-Exit) + * 12. PDN_S_PRE - Precharge Power-down Entry command (Slow-Exit) + * 13. PDN_F_ACT - Active Power-down Entry command (Fast-Exit) + * 14. PDN_S_ACT - Active Power-down Entry command (Slow-Exit) + * 15. PUP_PRE - Precharge Power-down Exit + * 16. PUP_ACT - Active Power-down Exit + * 17. SREN - Self-Refresh Entry command + * 18. SREX - Self-refresh Exit + * 19. NOP - To indicate end of trace + */ + + enum cmds { + ACT = 0, + RD = 1, + WR = 2, + PRE = 3, + REF = 4, + REFB = 5, + END = 6, + RDA = 7, + WRA = 8, + PREA = 9, + PDN_F_PRE = 10, + PDN_S_PRE = 11, + PDN_F_ACT = 12, + PDN_S_ACT = 13, + PUP_PRE = 14, + PUP_ACT = 15, + SREN = 16, + SREX = 17, + NOP = 18, + UNINITIALIZED = 19 + }; + +// MemCommand(); + MemCommand( + // Command Type + MemCommand::cmds type = UNINITIALIZED, + // Target Bank + unsigned bank = 0, + // Command Issue Timestamp (in cc) + int64_t timestamp = 0L); + + // Get command type + cmds getType() const; + + // Set command type + void setType(MemCommand::cmds type); + + // Set target Bank + void setBank(unsigned bank); + + // Get target Bank + unsigned getBank() const; + + // Set timestamp + void setTime(int64_t _timestamp); + + // Get timestamp + int64_t getTimeInt64() const; + + cmds typeWithoutAutoPrechargeFlag() const; + + // To calculate precharge offset after read or write with auto-precharge + int64_t getPrechargeOffset(const MemorySpecification& memSpec, + MemCommand::cmds type) const; + + // To check for equivalence + + bool operator==(const MemCommand& other) const + { + if ((getType() == other.getType()) && + (getBank() == other.getBank()) + ) { + return true; + } else { + return false; + } + } + + static const unsigned int nCommands = 20; + + static std::string* getCommandTypeStrings() + { + static std::string type_map[nCommands] = { "ACT", + "RD", + "WR", + "PRE", + "REF", + "REFB", + "END", + "RDA", + "WRA", + "PREA", + "PDN_F_PRE", + "PDN_S_PRE", + "PDN_F_ACT", + "PDN_S_ACT", + "PUP_PRE", + "PUP_ACT", + "SREN", + "SREX", + "NOP", + "UNINITIALIZED" }; + + return type_map; + } + + // To identify command type from name + static cmds getTypeFromName(const std::string& name) + { + std::string* typeStrings = getCommandTypeStrings(); + + for (size_t typeId = 0; typeId < nCommands; typeId++) { + if (typeStrings[typeId] == name) { + cmds commandType = static_cast(typeId); + return commandType; + } + } + assert(false); // Unknown name. + return NOP; // For clang compilation + } + + private: + MemCommand::cmds type; + unsigned bank; + int64_t timestamp; +}; +} +#endif // ifndef MEMCOMMAND_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemPowerSpec.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemPowerSpec.cc new file mode 100644 index 0000000000..2f7011c0e2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemPowerSpec.cc @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemPowerSpec.h" + +using namespace Data; + +MemPowerSpec::MemPowerSpec() : + idd0(0.0), + idd02(0.0), + idd2p0(0.0), + idd2p02(0.0), + idd2p1(0.0), + idd2p12(0.0), + idd2n(0.0), + idd2n2(0.0), + idd3p0(0.0), + idd3p02(0.0), + idd3p1(0.0), + idd3p12(0.0), + idd3n(0.0), + idd3n2(0.0), + idd4r(0.0), + idd4r2(0.0), + idd4w(0.0), + idd4w2(0.0), + idd5(0.0), + idd52(0.0), + idd5B(0.0), + idd6(0.0), + idd62(0.0), + vdd(0.0), + vdd2(0.0), + capacitance(0.0), + ioPower(0.0), + wrOdtPower(0.0), + termRdPower(0.0), + termWrPower(0.0) +{ +} + +void MemPowerSpec::processParameters() +{ + idd0 = getParamValWithDefault("idd0", 0.0); + idd02 = getParamValWithDefault("idd02", 0.0); + idd2p0 = getParamValWithDefault("idd2p0", 0.0); + idd2p02 = getParamValWithDefault("idd2p02", 0.0); + idd2p1 = getParamValWithDefault("idd2p1", 0.0); + idd2p12 = getParamValWithDefault("idd2p12", 0.0); + idd2n = getParamValWithDefault("idd2n", 0.0); + idd2n2 = getParamValWithDefault("idd2n2", 0.0); + idd3p0 = getParamValWithDefault("idd3p0", 0.0); + idd3p02 = getParamValWithDefault("idd3p02", 0.0); + idd3p1 = getParamValWithDefault("idd3p1", 0.0); + idd3p12 = getParamValWithDefault("idd3p12", 0.0); + idd3n = getParamValWithDefault("idd3n", 0.0); + idd3n2 = getParamValWithDefault("idd3n2", 0.0); + idd4r = getParamValWithDefault("idd4r", 0.0); + idd4r2 = getParamValWithDefault("idd4r2", 0.0); + idd4w = getParamValWithDefault("idd4w", 0.0); + idd4w2 = getParamValWithDefault("idd4w2", 0.0); + idd5 = getParamValWithDefault("idd5", 0.0); + idd52 = getParamValWithDefault("idd52", 0.0); + idd5B = getParamValWithDefault("idd5B", 0.0); + idd6 = getParamValWithDefault("idd6", 0.0); + idd62 = getParamValWithDefault("idd62", 0.0); + vdd = getParamValWithDefault("vdd", 0.0); + vdd2 = getParamValWithDefault("vdd2", 0.0); + + capacitance = getParamValWithDefault("capacitance", 0.0); + ioPower = getParamValWithDefault("ioPower", 0.0); + wrOdtPower = getParamValWithDefault("wrOdtPower", 0.0); + termRdPower = getParamValWithDefault("termRdPower", 0.0); + termWrPower = getParamValWithDefault("termWrPower", 0.0); +} // MemPowerSpec::processParameters diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemPowerSpec.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemPowerSpec.h new file mode 100644 index 0000000000..c5243dcdf5 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemPowerSpec.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "Parametrisable.h" + +namespace Data { +class MemPowerSpec : public virtual Parametrisable { + public: + MemPowerSpec(); + void processParameters(); + + double idd0; + double idd02; + double idd2p0; + double idd2p02; + double idd2p1; + double idd2p12; + double idd2n; + double idd2n2; + double idd3p0; + double idd3p02; + double idd3p1; + double idd3p12; + double idd3n; + double idd3n2; + double idd4r; + double idd4r2; + double idd4w; + double idd4w2; + double idd5; + double idd52; + double idd5B; + double idd6; + double idd62; + double vdd; + double vdd2; + + double capacitance; + double ioPower; + double wrOdtPower; + double termRdPower; + double termWrPower; +}; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemTimingSpec.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemTimingSpec.cc new file mode 100644 index 0000000000..54b07e3bc3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemTimingSpec.cc @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemTimingSpec.h" + +using namespace Data; + +MemTimingSpec::MemTimingSpec() : + clkMhz(0.0), + RC(0), + RCD(0), + CCD(0), + CCD_S(0), + CCD_L(0), + RRD(0), + RRD_S(0), + RRD_L(0), + FAW(0), + TAW(0), + WTR(0), + WTR_S(0), + WTR_L(0), + REFI(0), + RL(0), + RP(0), + RFC(0), + REFB(0), + RAS(0), + WL(0), + AL(0), + DQSCK(0), + RTP(0), + WR(0), + XP(0), + XPDLL(0), + XS(0), + XSDLL(0), + CKE(0), + CKESR(0), + clkPeriod(0.0) +{ +} + +void MemTimingSpec::processParameters() +{ + clkMhz = getParamValWithDefault("clkMhz", 0.0); + RC = getParamValWithDefault("RC", 0); + RCD = getParamValWithDefault("RCD", 0); + CCD = getParamValWithDefault("CCD", 0); + RRD = getParamValWithDefault("RRD", 0); + WTR = getParamValWithDefault("WTR", 0); + CCD_S = getParamValWithDefault("CCD_S", 0); + CCD_L = getParamValWithDefault("CCD_L", 0); + RRD_S = getParamValWithDefault("RRD_S", 0); + RRD_L = getParamValWithDefault("RRD_L", 0); + WTR_S = getParamValWithDefault("WTR_S", 0); + WTR_L = getParamValWithDefault("WTR_L", 0); + TAW = getParamValWithDefault("TAW", 0); + FAW = getParamValWithDefault("FAW", 0); + REFI = getParamValWithDefault("REFI", 0); + RL = getParamValWithDefault("RL", 0); + RP = getParamValWithDefault("RP", 0); + RFC = getParamValWithDefault("RFC", 0); + REFB = getParamValWithDefault("REFB", 0); + RAS = getParamValWithDefault("RAS", 0); + WL = getParamValWithDefault("WL", 0); + AL = getParamValWithDefault("AL", 0); + DQSCK = getParamValWithDefault("DQSCK", 0); + RTP = getParamValWithDefault("RTP", 0); + WR = getParamValWithDefault("WR", 0); + XP = getParamValWithDefault("XP", 0); + XPDLL = getParamValWithDefault("XPDLL", 0); + XS = getParamValWithDefault("XS", 0); + XSDLL = getParamValWithDefault("XSDLL", 0); + CKE = getParamValWithDefault("CKE", 0); + CKESR = getParamValWithDefault("CKESR", 0); + clkPeriod = 1000.0 / clkMhz; +} // MemTimingSpec::processParameters diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemTimingSpec.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemTimingSpec.h new file mode 100644 index 0000000000..2413177b0f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemTimingSpec.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar, Sven Goossens + * + */ + +#include + +#include "Parametrisable.h" + +namespace Data { +class MemTimingSpec : public virtual Parametrisable { + public: + MemTimingSpec(); + void processParameters(); + + double clkMhz; + int64_t RC; + int64_t RCD; + int64_t CCD; + int64_t CCD_S; + int64_t CCD_L; + int64_t RRD; + int64_t RRD_S; + int64_t RRD_L; + int64_t FAW; + int64_t TAW; + int64_t WTR; + int64_t WTR_S; + int64_t WTR_L; + int64_t REFI; + int64_t RL; + int64_t RP; + int64_t RFC; + int64_t REFB; + int64_t RAS; + int64_t WL; + int64_t AL; + int64_t DQSCK; + int64_t RTP; + int64_t WR; + int64_t XP; + int64_t XPDLL; + int64_t XS; + int64_t XSDLL; + int64_t CKE; + int64_t CKESR; + double clkPeriod; +}; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemoryPowerModel.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemoryPowerModel.cc new file mode 100644 index 0000000000..5c3549c00a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemoryPowerModel.cc @@ -0,0 +1,610 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#include "MemoryPowerModel.h" + +#include + +#include // For pow +#include // fmtflags +#include + +using namespace std; +using namespace Data; + +MemoryPowerModel::MemoryPowerModel() +{ + total_cycles = 0; + energy.total_energy = 0; +} + +// Calculate energy and average power consumption for the given command trace + +void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, + const CommandAnalysis& c, + int term, + const MemBankWiseParams& bwPowerParams) +{ + const MemTimingSpec& t = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + const MemPowerSpec& mps = memSpec.memPowerSpec; + const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks; + + energy.act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.read_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.write_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.refb_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.act_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pre_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.idle_energy_act_banks.assign(static_cast(nbrofBanks), 0.0); + energy.idle_energy_pre_banks.assign(static_cast(nbrofBanks), 0.0); + energy.f_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.f_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.s_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.s_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pup_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pup_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.total_energy_banks.assign(static_cast(nbrofBanks), 0.0); + + energy.act_energy = 0.0; + energy.pre_energy = 0.0; + energy.read_energy = 0.0; + energy.write_energy = 0.0; + energy.ref_energy = 0.0; + energy.act_stdby_energy = 0.0; + energy.pre_stdby_energy = 0.0; + energy.idle_energy_act = 0.0; + energy.idle_energy_pre = 0.0; + energy.window_energy = 0.0; + energy.f_act_pd_energy = 0.0; + energy.f_pre_pd_energy = 0.0; + energy.s_act_pd_energy = 0.0; + energy.s_pre_pd_energy = 0.0; + energy.sref_energy = 0.0; + energy.sref_ref_energy = 0.0; + energy.sref_ref_act_energy = 0.0; + energy.sref_ref_pre_energy = 0.0; + energy.spup_energy = 0.0; + energy.spup_ref_energy = 0.0; + energy.spup_ref_act_energy = 0.0; + energy.spup_ref_pre_energy = 0.0; + energy.pup_act_energy = 0.0; + energy.pup_pre_energy = 0.0; + power.IO_power = 0.0; + power.WR_ODT_power = 0.0; + power.TermRD_power = 0.0; + power.TermWR_power = 0.0; + energy.read_io_energy = 0.0; + energy.write_term_energy = 0.0; + energy.read_oterm_energy = 0.0; + energy.write_oterm_energy = 0.0; + energy.io_term_energy = 0.0; + + // How long a single burst takes, measured in command-clock cycles. + int64_t burstCc = memArchSpec.burstLength / memArchSpec.dataRate; + + // IO and Termination Power measures are included, if required. + if (term) { + io_term_power(memSpec); + + // memArchSpec.width represents the number of data (dq) pins. + // 1 DQS pin is associated with every data byte + int64_t dqPlusDqsBits = memArchSpec.width + memArchSpec.width / 8; + // 1 DQS and 1 DM pin is associated with every data byte + int64_t dqPlusDqsPlusMaskBits = memArchSpec.width + memArchSpec.width / 8 + memArchSpec.width / 8; + // Size of one clock period for the data bus. + double ddrPeriod = t.clkPeriod / static_cast(memArchSpec.dataRate); + + // Read IO power is consumed by each DQ (data) and DQS (data strobe) pin + energy.read_io_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength, + ddrPeriod, + power.IO_power, + dqPlusDqsBits); + + // Write ODT power is consumed by each DQ (data), DQS (data strobe) and DM + energy.write_term_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength, + ddrPeriod, + power.WR_ODT_power, + dqPlusDqsPlusMaskBits); + + if (memArchSpec.nbrOfRanks > 1) { + // Termination power consumed in the idle rank during reads on the active + // rank by each DQ (data) and DQS (data strobe) pin. + energy.read_oterm_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength, + ddrPeriod, + power.TermRD_power, + dqPlusDqsBits); + + // Termination power consumed in the idle rank during writes on the active + // rank by each DQ (data), DQS (data strobe) and DM (data mask) pin. + energy.write_oterm_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength, + ddrPeriod, + power.TermWR_power, + dqPlusDqsPlusMaskBits); + } + + // Sum of all IO and termination energy + energy.io_term_energy = energy.read_io_energy + energy.write_term_energy + + energy.read_oterm_energy + energy.write_oterm_energy; + } + + window_cycles = c.actcycles + c.precycles + + c.f_act_pdcycles + c.f_pre_pdcycles + + c.s_act_pdcycles + c.s_pre_pdcycles + c.sref_cycles + + c.sref_ref_act_cycles + c.sref_ref_pre_cycles + + c.spup_ref_act_cycles + c.spup_ref_pre_cycles; + + EnergyDomain vdd0Domain(mps.vdd, t.clkPeriod); + + energy.act_energy = vdd0Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd0 - mps.idd3n); + energy.pre_energy = vdd0Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd0 - mps.idd2n); + energy.read_energy = vdd0Domain.calcTivEnergy(sum(c.numberofreadsBanks) * burstCc , mps.idd4r - mps.idd3n); + energy.write_energy = vdd0Domain.calcTivEnergy(sum(c.numberofwritesBanks) * burstCc , mps.idd4w - mps.idd3n); + energy.ref_energy = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd5 - mps.idd3n); + energy.pre_stdby_energy = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n); + energy.act_stdby_energy = vdd0Domain.calcTivEnergy(c.actcycles, mps.idd3n); + + // Using the number of cycles that at least one bank is active here + // But the current iddrho is less than idd3n + double iddrho = (static_cast(bwPowerParams.bwPowerFactRho) / 100.0) * (mps.idd3n - mps.idd2n) + mps.idd2n; + double esharedActStdby = vdd0Domain.calcTivEnergy(c.actcycles, iddrho); + // Fixed componenent for PASR + double iddsigma = (static_cast(bwPowerParams.bwPowerFactSigma) / 100.0) * mps.idd6; + double esharedPASR = vdd0Domain.calcTivEnergy(c.sref_cycles, iddsigma); + // ione is Active background current for a single bank. When a single bank is Active + //,all the other remainig (B-1) banks will consume a current of iddrho (based on factor Rho) + // So to derrive ione we add (B-1)*iddrho to the idd3n and distribute it to each banks. + double ione = (mps.idd3n + (iddrho * (static_cast(nbrofBanks - 1)))) / (static_cast(nbrofBanks)); + // If memory specification does not provide bank wise refresh current, + // approximate it to single bank background current removed from + // single bank active current + double idd5Blocal = (mps.idd5B == 0.0) ? (mps.idd0 - ione) :(mps.idd5B); + // if memory specification does not provide the REFB timing approximate it + // to time of ACT + PRE + int64_t tRefBlocal = (t.REFB == 0) ? (t.RAS + t.RP) : (t.REFB); + + //Distribution of energy componets to each banks + for (unsigned i = 0; i < nbrofBanks; i++) { + energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - ione); + energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RP), mps.idd0 - ione); + energy.read_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofreadsBanks[i] * burstCc, mps.idd4r - mps.idd3n); + energy.write_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofwritesBanks[i] * burstCc, mps.idd4w - mps.idd3n); + energy.ref_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC, mps.idd5 - mps.idd3n) / static_cast(nbrofBanks); + energy.refb_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefbBanks[i] * tRefBlocal, idd5Blocal); + energy.pre_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n) / static_cast(nbrofBanks); + energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho) / static_cast(nbrofBanks)) + + esharedActStdby / static_cast(nbrofBanks); + energy.idle_energy_act_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n) / static_cast(nbrofBanks); + energy.idle_energy_pre_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n) / static_cast(nbrofBanks); + energy.f_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p1) / static_cast(nbrofBanks); + energy.f_pre_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p1) / static_cast(nbrofBanks); + energy.s_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p0) / static_cast(nbrofBanks); + energy.s_pre_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p0) / static_cast(nbrofBanks); + + energy.sref_energy_banks[i] = engy_sref_banks(mps.idd6, mps.idd3n, + mps.idd5, mps.vdd, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod,esharedPASR,bwPowerParams,i,nbrofBanks + ); + energy.sref_ref_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p0) / static_cast(nbrofBanks); + energy.sref_ref_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p0) / static_cast(nbrofBanks); + energy.sref_ref_energy_banks[i] = energy.sref_ref_act_energy_banks[i] + energy.sref_ref_pre_energy_banks[i] ;// + + energy.spup_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_cycles, mps.idd2n) / static_cast(nbrofBanks); + energy.spup_ref_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n) / static_cast(nbrofBanks);// + energy.spup_ref_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n) / static_cast(nbrofBanks); + energy.spup_ref_energy_banks[i] = ( energy.spup_ref_act_energy + energy.spup_ref_pre_energy ) / static_cast(nbrofBanks); + energy.pup_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n) / static_cast(nbrofBanks); + energy.pup_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n) / static_cast(nbrofBanks); + } + + // Idle energy in the active standby clock cycles + energy.idle_energy_act = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n); + // Idle energy in the precharge standby clock cycles + energy.idle_energy_pre = vdd0Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n); + // fast-exit active power-down cycles energy + energy.f_act_pd_energy = vdd0Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p1); + // fast-exit precharged power-down cycles energy + energy.f_pre_pd_energy = vdd0Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p1); + // slow-exit active power-down cycles energy + energy.s_act_pd_energy = vdd0Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p0); + // slow-exit precharged power-down cycles energy + energy.s_pre_pd_energy = vdd0Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p0); + + // self-refresh cycles energy including a refresh per self-refresh entry + energy.sref_energy = engy_sref(mps.idd6, mps.idd3n, + mps.idd5, mps.vdd, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod); + + // background energy during active auto-refresh cycles in self-refresh + energy.sref_ref_act_energy = vdd0Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p0); + // background energy during precharged auto-refresh cycles in self-refresh + energy.sref_ref_pre_energy = vdd0Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p0); + // background energy during active auto-refresh cycles in self-refresh exit + energy.spup_ref_act_energy = vdd0Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n); + // background energy during precharged auto-refresh cycles in self-refresh exit + energy.spup_ref_pre_energy = vdd0Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n); + // self-refresh power-up cycles energy -- included + energy.spup_energy = vdd0Domain.calcTivEnergy(c.spup_cycles, mps.idd2n); + // active power-up cycles energy - same as active standby -- included + energy.pup_act_energy = vdd0Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n); + // precharged power-up cycles energy - same as precharged standby -- included + energy.pup_pre_energy = vdd0Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n); + + // similar equations as before to support multiple voltage domains in LPDDR2 + // and WIDEIO memories + if (memArchSpec.twoVoltageDomains) { + EnergyDomain vdd2Domain(mps.vdd2, t.clkPeriod); + + energy.act_energy += vdd2Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd02 - mps.idd3n2); + energy.pre_energy += vdd2Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd02 - mps.idd2n2); + energy.read_energy += vdd2Domain.calcTivEnergy(sum(c.numberofreadsBanks) * burstCc , mps.idd4r2 - mps.idd3n2); + energy.write_energy += vdd2Domain.calcTivEnergy(sum(c.numberofwritesBanks) * burstCc , mps.idd4w2 - mps.idd3n2); + energy.ref_energy += vdd2Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd52 - mps.idd3n2); + energy.pre_stdby_energy += vdd2Domain.calcTivEnergy(c.precycles, mps.idd2n2); + energy.act_stdby_energy += vdd2Domain.calcTivEnergy(c.actcycles, mps.idd3n2); + + // Idle energy in the active standby clock cycles + energy.idle_energy_act += vdd2Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n2); + // Idle energy in the precharge standby clock cycles + energy.idle_energy_pre += vdd2Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n2); + // fast-exit active power-down cycles energy + energy.f_act_pd_energy += vdd2Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p12); + // fast-exit precharged power-down cycles energy + energy.f_pre_pd_energy += vdd2Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p12); + // slow-exit active power-down cycles energy + energy.s_act_pd_energy += vdd2Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p02); + // slow-exit precharged power-down cycles energy + energy.s_pre_pd_energy += vdd2Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p02); + + energy.sref_energy += engy_sref(mps.idd62, mps.idd3n2, + mps.idd52, mps.vdd2, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod); + + // background energy during active auto-refresh cycles in self-refresh + energy.sref_ref_act_energy += vdd2Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p02); + // background energy during precharged auto-refresh cycles in self-refresh + energy.sref_ref_pre_energy += vdd2Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p02); + // background energy during active auto-refresh cycles in self-refresh exit + energy.spup_ref_act_energy += vdd2Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n2); + // background energy during precharged auto-refresh cycles in self-refresh exit + energy.spup_ref_pre_energy += vdd2Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n2); + // self-refresh power-up cycles energy -- included + energy.spup_energy += vdd2Domain.calcTivEnergy(c.spup_cycles, mps.idd2n2); + // active power-up cycles energy - same as active standby -- included + energy.pup_act_energy += vdd2Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n2); + // precharged power-up cycles energy - same as precharged standby -- included + energy.pup_pre_energy += vdd2Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n2); + } + + // auto-refresh energy during self-refresh cycles + energy.sref_ref_energy = energy.sref_ref_act_energy + energy.sref_ref_pre_energy; + + // auto-refresh energy during self-refresh exit cycles + energy.spup_ref_energy = energy.spup_ref_act_energy + energy.spup_ref_pre_energy; + + // adding all energy components for the active rank and all background and idle + // energy components for both ranks (in a dual-rank system) + + if (bwPowerParams.bwMode) { + // Calculate total energy per bank. + for (unsigned i = 0; i < nbrofBanks; i++) { + energy.total_energy_banks[i] = energy.act_energy_banks[i] + energy.pre_energy_banks[i] + energy.read_energy_banks[i] + + energy.ref_energy_banks[i] + energy.write_energy_banks[i] + energy.refb_energy_banks[i] + + static_cast(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i] + + energy.pre_stdby_energy_banks[i] + energy.f_pre_pd_energy_banks[i] + energy.s_act_pd_energy_banks[i] + + energy.s_pre_pd_energy_banks[i]+ energy.sref_ref_energy_banks[i] + energy.spup_ref_energy_banks[i]; + } + // Calculate total energy for all banks. + energy.window_energy = sum(energy.total_energy_banks) + energy.io_term_energy; + + } else { + energy.window_energy = energy.act_energy + energy.pre_energy + energy.read_energy + energy.write_energy + + energy.ref_energy + energy.io_term_energy + sum(energy.refb_energy_banks) + + static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + + energy.pre_stdby_energy + energy.sref_energy + energy.f_act_pd_energy + + energy.f_pre_pd_energy + energy.s_act_pd_energy + energy.s_pre_pd_energy + + energy.sref_ref_energy + energy.spup_ref_energy); + } + + power.window_average_power = energy.window_energy / (static_cast(window_cycles) * t.clkPeriod); + + total_cycles += window_cycles; + + energy.total_energy += energy.window_energy; + + // Calculate the average power consumption + power.average_power = energy.total_energy / (static_cast(total_cycles) * t.clkPeriod); +} // MemoryPowerModel::power_calc + +void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, const CommandAnalysis& c, bool bankwiseMode) const +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + const uint64_t nRanks = static_cast(memArchSpec.nbrOfRanks); + const char eUnit[] = " pJ"; + const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks; + double nRanksDouble = static_cast(nRanks); + + ios_base::fmtflags flags = cout.flags(); + streamsize precision = cout.precision(); + cout.precision(0); + + if (bankwiseMode) { + cout << endl << "* Bankwise Details:"; + for (unsigned i = 0; i < nbrofBanks; i++) { + cout << endl << "## @ Bank " << i << fixed + << endl << " #ACT commands: " << c.numberofactsBanks[i] + << endl << " #RD + #RDA commands: " << c.numberofreadsBanks[i] + << endl << " #WR + #WRA commands: " << c.numberofwritesBanks[i] + << endl << " #PRE (+ PREA) commands: " << c.numberofpresBanks[i]; + } + cout << endl; + } + + cout << endl << "* Trace Details:" << fixed << endl + << endl << "#ACT commands: " << sum(c.numberofactsBanks) + << endl << "#RD + #RDA commands: " << sum(c.numberofreadsBanks) + << endl << "#WR + #WRA commands: " << sum(c.numberofwritesBanks) + /* #PRE commands (precharge all counts a number of #PRE commands equal to the number of active banks) */ + << endl << "#PRE (+ PREA) commands: " << sum(c.numberofpresBanks) + << endl << "#REF commands: " << c.numberofrefs + << endl << "#REFB commands: " << sum(c.numberofrefbBanks) + << endl << "#Active Cycles: " << c.actcycles + << endl << " #Active Idle Cycles: " << c.idlecycles_act + << endl << " #Active Power-Up Cycles: " << c.pup_act_cycles + << endl << " #Auto-Refresh Active cycles during Self-Refresh Power-Up: " << c.spup_ref_act_cycles + << endl << "#Precharged Cycles: " << c.precycles + << endl << " #Precharged Idle Cycles: " << c.idlecycles_pre + << endl << " #Precharged Power-Up Cycles: " << c.pup_pre_cycles + << endl << " #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: " << c.spup_ref_pre_cycles + << endl << " #Self-Refresh Power-Up Cycles: " << c.spup_cycles + << endl << "Total Idle Cycles (Active + Precharged): " << c.idlecycles_act + c.idlecycles_pre + << endl << "#Power-Downs: " << c.f_act_pdns + c.s_act_pdns + c.f_pre_pdns + c.s_pre_pdns + << endl << " #Active Fast-exit Power-Downs: " << c.f_act_pdns + << endl << " #Active Slow-exit Power-Downs: " << c.s_act_pdns + << endl << " #Precharged Fast-exit Power-Downs: " << c.f_pre_pdns + << endl << " #Precharged Slow-exit Power-Downs: " << c.s_pre_pdns + << endl << "#Power-Down Cycles: " << c.f_act_pdcycles + c.s_act_pdcycles + c.f_pre_pdcycles + c.s_pre_pdcycles + << endl << " #Active Fast-exit Power-Down Cycles: " << c.f_act_pdcycles + << endl << " #Active Slow-exit Power-Down Cycles: " << c.s_act_pdcycles + << endl << " #Auto-Refresh Active cycles during Self-Refresh: " << c.sref_ref_act_cycles + << endl << " #Precharged Fast-exit Power-Down Cycles: " << c.f_pre_pdcycles + << endl << " #Precharged Slow-exit Power-Down Cycles: " << c.s_pre_pdcycles + << endl << " #Auto-Refresh Precharged cycles during Self-Refresh: " << c.sref_ref_pre_cycles + << endl << "#Auto-Refresh Cycles: " << c.numberofrefs * memTimingSpec.RFC + << endl << "#Self-Refreshes: " << c.numberofsrefs + << endl << "#Self-Refresh Cycles: " << c.sref_cycles + << endl << "----------------------------------------" + << endl << "Total Trace Length (clock cycles): " << total_cycles + << endl << "----------------------------------------" << endl; + + if (bankwiseMode) { + cout << endl << "* Bankwise Details:"; + for (unsigned i = 0; i < nbrofBanks; i++) { + cout << endl << "## @ Bank " << i << fixed + << endl << " ACT Cmd Energy: " << energy.act_energy_banks[i] << eUnit + << endl << " PRE Cmd Energy: " << energy.pre_energy_banks[i] << eUnit + << endl << " RD Cmd Energy: " << energy.read_energy_banks[i] << eUnit + << endl << " WR Cmd Energy: " << energy.write_energy_banks[i] << eUnit + << endl << " Auto-Refresh Energy: " << energy.ref_energy_banks[i] << eUnit + << endl << " Bankwise-Refresh Energy: " << energy.refb_energy_banks[i] << eUnit + << endl << " ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy_banks[i] << eUnit + << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit + << endl << " Active Idle Energy: "<< nRanksDouble * energy.idle_energy_act_banks[i] << eUnit + << endl << " Precharge Idle Energy: "<< nRanksDouble * energy.idle_energy_pre_banks[i] << eUnit + << endl << " Fast-Exit Active Power-Down Energy: "<< nRanksDouble * energy.f_act_pd_energy_banks[i] << eUnit + << endl << " Fast-Exit Precharged Power-Down Energy: "<< nRanksDouble * energy.f_pre_pd_energy_banks[i] << eUnit + << endl << " Slow-Exit Active Power-Down Energy: "<< nRanksDouble * energy.s_act_pd_energy_banks[i] << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy: "<< nRanksDouble * energy.s_pre_pd_energy_banks[i] << eUnit + << endl << " Self-Refresh Energy: "<< nRanksDouble * energy.sref_energy_banks[i] << eUnit + << endl << " Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: "<< nRanksDouble * energy.sref_ref_act_energy_banks[i] << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy_banks[i] << eUnit + << endl << " Self-Refresh Power-Up Energy: "<< nRanksDouble * energy.spup_energy_banks[i] << eUnit + << endl << " Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_act_energy_banks[i] << eUnit + << endl << " Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_pre_energy_banks[i] << eUnit + << endl << " Active Power-Up Energy: "<< nRanksDouble * energy.pup_act_energy_banks[i] << eUnit + << endl << " Precharged Power-Up Energy: "<< nRanksDouble * energy.pup_pre_energy_banks[i] << eUnit + << endl << " Total Energy: "<< energy.total_energy_banks[i] << eUnit + << endl; + } + cout << endl; + } + + cout.precision(2); + cout << endl << "* Trace Power and Energy Estimates:" << endl + << endl << "ACT Cmd Energy: " << energy.act_energy << eUnit + << endl << "PRE Cmd Energy: " << energy.pre_energy << eUnit + << endl << "RD Cmd Energy: " << energy.read_energy << eUnit + << endl << "WR Cmd Energy: " << energy.write_energy << eUnit; + + if (term) { + cout << endl << "RD I/O Energy: " << energy.read_io_energy << eUnit << endl; + // No Termination for LPDDR/2/3 and DDR memories + if (memSpec.memArchSpec.termination) { + cout << "WR Termination Energy: " << energy.write_term_energy << eUnit << endl; + } + + if (nRanks > 1 && memSpec.memArchSpec.termination) { + cout << "RD Termination Energy (Idle rank): " << energy.read_oterm_energy << eUnit + << endl << "WR Termination Energy (Idle rank): " << energy.write_oterm_energy << eUnit << endl; + } + } + + cout << "ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy << eUnit + << endl << " Active Idle Energy: " << nRanksDouble * energy.idle_energy_act << eUnit + << endl << " Active Power-Up Energy: " << nRanksDouble * energy.pup_act_energy << eUnit + << endl << " Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: " << nRanksDouble * energy.spup_ref_act_energy << eUnit + << endl << "PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy << eUnit + << endl << " Precharge Idle Energy: " << nRanksDouble * energy.idle_energy_pre << eUnit + << endl << " Precharged Power-Up Energy: " << nRanksDouble * energy.pup_pre_energy << eUnit + << endl << " Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: " << nRanksDouble * energy.spup_ref_pre_energy << eUnit + << endl << " Self-Refresh Power-Up Energy: " << nRanksDouble * energy.spup_energy << eUnit + << endl << "Total Idle Energy (Active + Precharged): " << nRanksDouble * (energy.idle_energy_act + energy.idle_energy_pre) << eUnit + << endl << "Total Power-Down Energy: " << nRanksDouble * (energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy + energy.s_pre_pd_energy) << eUnit + << endl << " Fast-Exit Active Power-Down Energy: " << nRanksDouble * energy.f_act_pd_energy << eUnit + << endl << " Slow-Exit Active Power-Down Energy: " << nRanksDouble * energy.s_act_pd_energy << eUnit + << endl << " Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_act_energy << eUnit + << endl << " Fast-Exit Precharged Power-Down Energy: " << nRanksDouble * energy.f_pre_pd_energy << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy: " << nRanksDouble * energy.s_pre_pd_energy << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy << eUnit + << endl << "Auto-Refresh Energy: " << energy.ref_energy << eUnit + << endl << "Bankwise-Refresh Energy: " << sum(energy.refb_energy_banks) << eUnit + << endl << "Self-Refresh Energy: " << nRanksDouble * energy.sref_energy << eUnit + << endl << "----------------------------------------" + << endl << "Total Trace Energy: " << energy.total_energy << eUnit + << endl << "Average Power: " << power.average_power << " mW" + << endl << "----------------------------------------" << endl; + + cout.flags(flags); + cout.precision(precision); +} // MemoryPowerModel::power_print + +// Self-refresh active energy estimation (not including background energy) +double MemoryPowerModel::engy_sref(double idd6, double idd3n, double idd5, + double vdd, double sref_cycles, double sref_ref_act_cycles, + double sref_ref_pre_cycles, double spup_ref_act_cycles, + double spup_ref_pre_cycles, double clk) +{ + double sref_energy; + + sref_energy = ((idd6 * sref_cycles) + ((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles))) + * vdd * clk; + return sref_energy; +} + +// Self-refresh active energy estimation per banks +double MemoryPowerModel::engy_sref_banks(double idd6, double idd3n, double idd5, + double vdd, double sref_cycles, double sref_ref_act_cycles, + double sref_ref_pre_cycles, double spup_ref_act_cycles, + double spup_ref_pre_cycles, double clk, + double esharedPASR, const MemBankWiseParams& bwPowerParams, + unsigned bnkIdx, int64_t nbrofBanks) +{ + // Bankwise Self-refresh energy + double sref_energy_banks; + // Dynamic componenents for PASR energy varying based on PASR mode + double iddsigmaDynBanks; + double pasr_energy_dyn; + // This component is distributed among all banks + double sref_energy_shared; + //Is PASR Active + if (bwPowerParams.flgPASR){ + sref_energy_shared = (((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles)) * vdd * clk) + / static_cast(nbrofBanks); + //if the bank is active under current PASR mode + if (bwPowerParams.isBankActiveInPasr(bnkIdx)){ + // Distribute the sref energy to the active banks + iddsigmaDynBanks = (static_cast(100 - bwPowerParams.bwPowerFactSigma) / (100.0 * static_cast(nbrofBanks))) * idd6; + pasr_energy_dyn = vdd * iddsigmaDynBanks * sref_cycles; + // Add the static components + sref_energy_banks = sref_energy_shared + pasr_energy_dyn + (esharedPASR /static_cast(nbrofBanks)); + + }else{ + sref_energy_banks = (esharedPASR /static_cast(nbrofBanks)); + } + } + //When PASR is not active total all the banks are in Self-Refresh. Thus total Self-Refresh energy is distributed across all banks + else{ + + + sref_energy_banks = (((idd6 * sref_cycles) + ((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles))) + * vdd * clk) + / static_cast(nbrofBanks); + } + return sref_energy_banks; +} + + +// IO and Termination power calculation based on Micron Power Calculators +// Absolute power measures are obtained from Micron Power Calculator (mentioned in mW) +void MemoryPowerModel::io_term_power(const MemorySpecification& memSpec) +{ + const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; + const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + const MemPowerSpec& memPowerSpec = memSpec.memPowerSpec; + + power.IO_power = memPowerSpec.ioPower; // in mW + power.WR_ODT_power = memPowerSpec.wrOdtPower; // in mW + + if (memArchSpec.nbrOfRanks > 1) { + power.TermRD_power = memPowerSpec.termRdPower; // in mW + power.TermWR_power = memPowerSpec.termWrPower; // in mW + } + + if (memPowerSpec.capacitance != 0.0) { + // If capacity is given, then IO Power depends on DRAM clock frequency. + power.IO_power = memPowerSpec.capacitance * 0.5 * pow(memPowerSpec.vdd2, 2.0) * memTimingSpec.clkMhz * 1000000; + } +} // MemoryPowerModel::io_term_power + + +double MemoryPowerModel::calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const +{ + return static_cast(cycles) * period * power * static_cast(numBits); +} + +// time (t) * current (I) * voltage (V) energy calculation +double EnergyDomain::calcTivEnergy(int64_t cycles, double current) const +{ + return static_cast(cycles) * clkPeriod * current * voltage; +} + diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemoryPowerModel.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemoryPowerModel.h new file mode 100644 index 0000000000..916d540a83 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemoryPowerModel.h @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#ifndef MEMORY_POWER_MODEL_H +#define MEMORY_POWER_MODEL_H + +#include +#include "MemorySpecification.h" +#include "MemBankWiseParams.h" +#include "CommandAnalysis.h" + +namespace Data { +class MemoryPowerModel { + public: + + MemoryPowerModel(); + + // Calculate energy and average power consumption for the given memory + // command trace + void power_calc(const MemorySpecification& memSpec, + const CommandAnalysis& c, + int term, + const MemBankWiseParams& bwPowerParams); + + // Used to calculate self-refresh active energy + static double engy_sref(double idd6, + double idd3n, + double idd5, + double vdd, + double sref_cycles_idd6, + double sref_ref_act_cycles, + double sref_ref_pre_cycles, + double spup_ref_act_cycles, + double spup_ref_pre_cycles, + double clk); + static double engy_sref_banks(double idd6, + double idd3n, + double idd5, + double vdd, + double sref_cycles, + double sref_ref_act_cycles, + double sref_ref_pre_cycles, + double spup_ref_act_cycles, + double spup_ref_pre_cycles, + double clk, + double esharedPASR, + const MemBankWiseParams& bwPowerParams, + unsigned bnkIdx, + int64_t nbrofBanks); + + int64_t total_cycles; + + int64_t window_cycles; + + struct Energy { + // Total energy of all activates + double act_energy; + std::vector act_energy_banks; + + // Total energy of all precharges + double pre_energy; + std::vector pre_energy_banks; + + // Total energy of all reads + double read_energy; + std::vector read_energy_banks; + + // Total energy of all writes + double write_energy; + std::vector write_energy_banks; + + // Total energy of all refreshes + double ref_energy; + std::vector ref_energy_banks; + + // Bankwise refresh energy + std::vector refb_energy_banks; + + // Total background energy of all active standby cycles + double act_stdby_energy; + std::vector act_stdby_energy_banks; + + // Total background energy of all precharge standby cycles + double pre_stdby_energy; + std::vector pre_stdby_energy_banks; + + // Total energy of idle cycles in the active mode + double idle_energy_act; + std::vector idle_energy_act_banks; + + // Total energy of idle cycles in the precharge mode + double idle_energy_pre; + std::vector idle_energy_pre_banks; + + // Total trace/pattern energy + double total_energy; + std::vector total_energy_banks; + + // Window energy + double window_energy; + + // Average Power + double average_power; + + // Energy consumed in active/precharged fast/slow-exit modes + double f_act_pd_energy; + std::vector f_act_pd_energy_banks; + + double f_pre_pd_energy; + std::vector f_pre_pd_energy_banks; + + double s_act_pd_energy; + std::vector s_act_pd_energy_banks; + + double s_pre_pd_energy; + std::vector s_pre_pd_energy_banks; + + // Energy consumed in self-refresh mode + double sref_energy; + std::vector sref_energy_banks; + + // Energy consumed in auto-refresh during self-refresh mode + double sref_ref_energy; + std::vector sref_ref_energy_banks; + + double sref_ref_act_energy; + std::vector sref_ref_act_energy_banks; + + double sref_ref_pre_energy; + std::vector sref_ref_pre_energy_banks; + + // Energy consumed in powering-up from self-refresh mode + double spup_energy; + std::vector spup_energy_banks; + + // Energy consumed in auto-refresh during self-refresh power-up + double spup_ref_energy; + std::vector spup_ref_energy_banks; + + double spup_ref_act_energy; + std::vector spup_ref_act_energy_banks; + + double spup_ref_pre_energy; + std::vector spup_ref_pre_energy_banks; + + // Energy consumed in powering-up from active/precharged power-down modes + double pup_act_energy; + std::vector pup_act_energy_banks; + + double pup_pre_energy; + std::vector pup_pre_energy_banks; + + // Energy consumed by IO and Termination + double read_io_energy; // Read IO Energy + double write_term_energy; // Write Termination Energy + double read_oterm_energy; // Read Termination Energy from idle rank + double write_oterm_energy; // Write Termination Energy from idle rank + // Total IO and Termination Energy + double io_term_energy; + }; + + struct Power { + // Power measures corresponding to IO and Termination + double IO_power; // Read IO Power + double WR_ODT_power; // Write ODT Power + double TermRD_power; // Read Termination in idle rank (in dual-rank systems) + double TermWR_power; // Write Termination in idle rank (in dual-rank systems) + + // Average Power + double average_power; + + // Window Average Power + double window_average_power; + }; + + // Print the power and energy + void power_print(const MemorySpecification& memSpec, + int term, + const CommandAnalysis& c, + bool bankwiseMode) const; + + // To derive IO and Termination Power measures using DRAM specification + void io_term_power(const MemorySpecification& memSpec); + + Energy energy; + Power power; + + private: + double calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const; + // Sum quantities (e.g., operations, energy, cycles) that are stored in a per bank basis returning the total amount. + template T sum(const std::vector vec) const { return std::accumulate(vec.begin(), vec.end(), static_cast(0)); } +}; + +class EnergyDomain { + public: + EnergyDomain(double voltage, double clkPeriod) : + voltage(voltage), + clkPeriod(clkPeriod) + {} + + double calcTivEnergy(int64_t cycles, double current) const; + double getVoltage() const{ return voltage; }; + private: + const double voltage; + const double clkPeriod; +}; + +} +#endif // ifndef MEMORY_POWER_MODEL_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemorySpecification.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemorySpecification.cc new file mode 100644 index 0000000000..3f9f188112 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemorySpecification.cc @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#include "MemorySpecification.h" + +using namespace std; +using namespace Data; + +// Set variable values from XML +void MemorySpecification::processParameters() +{ + setVarFromParam(&id,"memoryId"); + memoryType = getParamValWithDefault("memoryType", string("DDR3")); + + if (hasParameter("memoryType")) { + memArchSpec.twoVoltageDomains = memoryType.hasTwoVoltageDomains(); + memArchSpec.dll = memoryType.hasDll(); + memArchSpec.termination = memoryType.hasTermination(); + + memPowerSpec.capacitance = memoryType.getCapacitance(); + memPowerSpec.ioPower = memoryType.getIoPower(); + memPowerSpec.wrOdtPower = memoryType.getWrOdtPower(); + memPowerSpec.termRdPower = memoryType.getTermRdPower(); + memPowerSpec.termWrPower = memoryType.getTermWrPower(); + } +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/MemorySpecification.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemorySpecification.h new file mode 100644 index 0000000000..16d77ef868 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/MemorySpecification.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Karthik Chandrasekar + * + */ + +#ifndef TOOLS_MEMORY_SPECIFICATION_H +#define TOOLS_MEMORY_SPECIFICATION_H + +#include +#include + +#include "MemArchitectureSpec.h" +#include "MemTimingSpec.h" +#include "MemPowerSpec.h" +#include "Parametrisable.h" + + +namespace Data { +// Supported memory types +class MemoryType { + public: + enum MemoryType_t { + DDR2 = 0, + DDR3, + DDR4, + LPDDR, + LPDDR2, + LPDDR3, + WIDEIO_SDR, + MEMORY_TYPE_INVALID + }; + + MemoryType(MemoryType_t _val) : + val(_val) + { + } + + MemoryType() : + val(MEMORY_TYPE_INVALID) + { + } + + MemoryType(const std::string& _val) : + val(MEMORY_TYPE_INVALID) + { + if (_val == "DDR2") { + val = DDR2; + } else if (_val == "DDR3") { + val = DDR3; + } else if (_val == "DDR4") { + val = DDR4; + } else if (_val == "LPDDR") { + val = LPDDR; + } else if (_val == "LPDDR2") { + val = LPDDR2; + } else if (_val == "LPDDR3") { + val = LPDDR3; + } else if (_val == "WIDEIO_SDR") { + val = WIDEIO_SDR; + } + assert("Unknown memory type." && val != MEMORY_TYPE_INVALID); + } + + bool isLPDDRFamily() const + { + return val == LPDDR || + val == LPDDR2 || + val == LPDDR3 || + val == WIDEIO_SDR; + } + + bool hasTwoVoltageDomains() const + { + return val == LPDDR || + val == LPDDR2 || + val == LPDDR3 || + val == WIDEIO_SDR || + val == DDR4; + } + + bool isDDRFamily() const + { + return val == DDR2 || + val == DDR3 || + val == DDR4; + } + + bool hasDll() const + { + return val == DDR2 || + val == DDR3 || + val == DDR4; + } + + bool hasTermination() const + { + return val == DDR2 || + val == DDR3 || + val == DDR4; + } + + double getCapacitance() const + { + // LPDDR1/2 memories only have IO Power (no ODT) + // LPDDR3 has optional ODT, but it is typically not used (reflections are elimitated by other means (layout)) + // The capacitance values are conservative and based on Micron Mobile LPDDR2 Power Calculator + + // LPDDR/2/3 IO Capacitance in mF + if (val == LPDDR) { + return 0.0000000045; + } else if (val == LPDDR2) { + return 0.0000000025; + } else if (val == LPDDR3) { + return 0.0000000018; + } else { + return 0.0; + } + } + + double getIoPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 1.5; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 4.6; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 3.7; // in mW + } else { + return 0.0; + } + } + + double getWrOdtPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 8.2; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 21.2; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 17.0; // in mW + } else { + return 0.0; + } + } + + double getTermRdPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 13.1; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 15.5; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 12.4; // in mW + } else { + return 0.0; + } + } + + double getTermWrPower() const + { + if (val == DDR2) { + // Conservative estimates based on Micron DDR2 Power Calculator + return 14.6; // in mW + } else if (val == DDR3) { + // Conservative estimates based on Micron DDR3 Power Calculator + return 15.4; // in mW + } else if (val == DDR4) { + // Conservative estimates based on Micron DDR3 Power Calculator + // using available termination resistance values from Micron DDR4 Datasheets + return 12.3; // in mW + } else { + return 0.0; + } + } + + operator MemoryType_t() const { + return val; + } + + private: + MemoryType_t val; +}; + +class MemorySpecification : public virtual Parametrisable { + public: + std::string id; + MemoryType memoryType; + + MemArchitectureSpec memArchSpec; + MemTimingSpec memTimingSpec; + MemPowerSpec memPowerSpec; + + void processParameters(); + + static MemorySpecification getMemSpecFromXML(const std::string& id); +}; +} // namespace Data +#endif // ifndef TOOLS_MEMORY_SPECIFICATION_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/Parameter.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parameter.cc new file mode 100644 index 0000000000..9767e1c94c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parameter.cc @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#include "Parameter.h" + +#include +#include "Utils.h" + +using namespace Data; +using namespace std; + +Parameter::Parameter(const string& id, const string& type, + const string& value) : id(id), type(type), value(value) +{ +} + +string Parameter::getId() const +{ + return id; +} + +string Parameter::getType() const +{ + return type; +} + +int Parameter::getIntValue() const +{ + return fromString(value); +} + +unsigned int Parameter::getUIntValue() const +{ + bool isHex = value.size() > 1 && value[0] == '0' && value[1] == 'x'; + + return fromString(value, isHex ? std::hex : std::dec); +} + +#ifdef _LP64 + +size_t Parameter::getSizeTValue() const +{ + bool isHex = value.size() > 1 && value[0] == '0' && value[1] == 'x'; + + return fromString(value, isHex ? std::hex : std::dec); +} + +#endif + +double Parameter::getDoubleValue() const +{ + return fromString(value); +} + +bool Parameter::getBoolValue() const +{ + return fromString(value); +} + +string Parameter::getValue() const +{ + return value; +} + +Parameter Data::HexParameter(const string& id, int value) +{ + std::ostringstream ss; + + ss << "0x" << hex << setw(8) << setfill('0') << value; + + return Parameter(id, "int", ss.str()); +} + +Parameter Data::StringParameter(const string& id, const string& value) +{ + return Parameter(id, "string", value); +} + +ostream& Data::operator<<(ostream& os, const Parameter& parameter) +{ + os << ""; + + return os; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/Parameter.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parameter.h new file mode 100644 index 0000000000..2c9623eeb1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parameter.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#ifndef DATA_PARAMETER_H +#define DATA_PARAMETER_H + +#include +#include + +namespace Data { +class Parameter { + public: + Parameter(const std::string& id, const std::string& type, + const std::string& value); + + std::string getId() const; + std::string getType() const; + std::string getValue() const; + + int getIntValue() const; + unsigned int getUIntValue() const; + size_t getSizeTValue() const; + double getDoubleValue() const; + bool getBoolValue() const; + + operator int() const { + return getIntValue(); + } + + operator unsigned int() const { + return getUIntValue(); + } + +#ifdef _LP64 + + operator size_t() const { + return getSizeTValue(); + } +#endif + + operator double() const { + return getDoubleValue(); + } + + operator bool() const { + return getBoolValue(); + } + + operator std::string() const { + return getValue(); + } + + private: + std::string id; + std::string type; + std::string value; +}; + +Parameter HexParameter(const std::string& id, + int value); + +Parameter StringParameter(const std::string& id, + const std::string& value); + +std::ostream& operator<<(std::ostream& os, + const Parameter& parameter); +} +#endif // ifndef DATA_PARAMETER_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/Parametrisable.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parametrisable.cc new file mode 100644 index 0000000000..a348fd86e1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parametrisable.cc @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#include "Parametrisable.h" + +#include +#include + +using namespace Data; +using namespace std; + +void Parametrisable::pushParameter(const Parameter& parameter) +{ + parameters.push_back(parameter); +} + +void Parametrisable::setParameter(const Parameter& parameter, + unsigned int index) +{ + unsigned int count = 0; + + vector::iterator p = parameters.begin(); + + while (p != parameters.end() && !(p->getId() == parameter.getId() && + index == count)) { + if (p->getId() == parameter.getId()) + ++count; + ++p; + } + + if (p == parameters.end()) { + parameters.push_back(parameter); + } else { + p = parameters.erase(p); + parameters.insert(p, parameter); + } +} // Parametrisable::setParameter + +bool Parametrisable::removeParameter(const string& id, unsigned int index) +{ + unsigned int count = 0; + + for (vector::iterator p = parameters.begin(); + p != parameters.end(); ++p) { + if ((p->getId() == id) && (index == count++)) { + parameters.erase(p); + return true; + } + } + + return false; +} + +/** + * Get a parameter with a specific id. Should there be a multiplicity, + * then the index is used to determine which instance is returned, in + * order traversal. + */ +Parameter Parametrisable::getParameter(const string& id, + unsigned int index) const +{ + unsigned int count = 0; + + for (vector::const_iterator p = parameters.begin(); + p != parameters.end(); ++p) { + if ((p->getId() == id) && (index == count++)) { + return *p; + } + } + + cerr << "Could not find parameter '" << id << "' (" << index << ")" << endl; + cerr << "Stored parameters are: " << endl; + for (vector::const_iterator p = parameters.begin(); + p != parameters.end(); ++p) { + cerr << " " << p->getId() << ": " << p->getValue() << endl; + } + exit(1); + + return Parameter("", "", ""); +} // Parametrisable::getParameter + +vector Parametrisable::getParameters() const +{ + return parameters; +} + +bool Parametrisable::hasParameter(const string& id, unsigned int index) const +{ + unsigned int count = 0; + + for (vector::const_iterator p = parameters.begin(); + p != parameters.end(); ++p) { + if ((p->getId() == id) && (index == count++)) { + return true; + } + } + + return false; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/Parametrisable.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parametrisable.h new file mode 100644 index 0000000000..31a69190fa --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/Parametrisable.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#ifndef DATA_PARAMETRISABLE_H +#define DATA_PARAMETRISABLE_H + +#include +#include + +#include "Parameter.h" + +namespace Data { +/** + * Convenience class for the architectural components that are + * parametrisable. The interface is shared and implemented only in + * this class. + */ +class Parametrisable { + public: + Parametrisable() + { + } + + virtual ~Parametrisable() + { + } + + /** + * Push a new parameter into the in-order vector without checking + * for duplicates. + */ + virtual void pushParameter(const Parameter& parameter); + + /** + * Set a parameter with a given index (default 0). This could for + * example be a queue size for a given channel id. + */ + void setParameter(const Parameter& parameter, + unsigned int index = 0); + + /** + * Get a parameter of a given name and of a certain index. Calling + * this method on an object that has no parameter of that name + * will result in application exit. + */ + Parameter getParameter(const std::string& id, + unsigned int index = 0) const; + + /** + * Remove a parameter with a specific name and index. If a parameter + * is removed this method returns true, otherwise false. + */ + bool removeParameter(const std::string& id, + unsigned int index = 0); + + /** + * Simply get all the parameters. + */ + std::vector getParameters() const; + + /** + * Check if a parameter of a certain name exists in the object. + */ + bool hasParameter(const std::string& id, + unsigned int index = 0) const; + + /** + * Convenience function to set a variable to the value stored in a parameter + * with built in error detection/assertion. Returns true if the value was + * successfully set. + * @param m + * @param paramName + * @param assertOnFail + * @return + */ + template + bool setVarFromParam(T* m, const char* paramName) + { + if (hasParameter(paramName)) { + *m = static_cast(getParameter(paramName)); + return true; + } else { + *m = static_cast(0); + return false; + } + } + + template + T getParamValWithDefault(const char* paramName, T defaultVal) const + { + if (hasParameter(paramName)) { + return static_cast(getParameter(paramName)); + } else { + return defaultVal; + } + } + + protected: + std::vector parameters; +}; +} +#endif // ifndef DATA_PARAMETRISABLE_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/TraceParser.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/TraceParser.cc new file mode 100644 index 0000000000..88f31c21fd --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/TraceParser.cc @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Omar Naji + * + */ +#include "TraceParser.h" + +#include "CommandAnalysis.h" +#include "CmdScheduler.h" + +using namespace Data; +using namespace std; + +TraceParser::TraceParser(const MemorySpecification& memSpec) : + counters(memSpec) +{ +} + + +Data::MemCommand TraceParser::parseLine(std::string line) +{ + MemCommand memcmd(MemCommand::UNINITIALIZED, 0, 0); + istringstream linestream(line); + string item; + int64_t item_val; + unsigned itemnum = 0; + + while (getline(linestream, item, ',')) { + if (itemnum == 0) { + stringstream timestamp(item); + timestamp >> item_val; + memcmd.setTime(item_val); + } else if (itemnum == 1) { + item_val = MemCommand::getTypeFromName(item); + memcmd.setType(static_cast(item_val)); + } else if (itemnum == 2) { + stringstream bank(item); + bank >> item_val; + memcmd.setBank(static_cast(item_val)); + } + itemnum++; + } + return memcmd; +} // TraceParser::parseLine + +void TraceParser::parseFile(MemorySpecification memSpec, std::ifstream& trace, + int window, int grouping, int interleaving, int burst, + int powerdown, int trans) +{ + ifstream pwr_trace; + + counters = CommandAnalysis(memSpec); + int nCommands = 0; + bool lastupdate = false; + if (trans) { + cmdScheduler cmdsched; + cmdsched.transTranslation(memSpec, trace, grouping, interleaving, burst, powerdown); + pwr_trace.open("commands.trace", ifstream::in); + std::string line; + while (getline(pwr_trace, line)) { + MemCommand cmdline = parseLine(line); + cmd_list.push_back(cmdline); + nCommands++; + if (nCommands == window) { + counters.getCommands(cmd_list, lastupdate); + nCommands = 0; + cmd_list.clear(); + } + } + lastupdate = true; + counters.getCommands(cmd_list, lastupdate); + cmd_list.clear(); + pwr_trace.close(); + } else { + std::string line; + while (getline(trace, line)) { + MemCommand cmdline = parseLine(line); + cmd_list.push_back(cmdline); + nCommands++; + if (nCommands == window) { + counters.getCommands(cmd_list, lastupdate); + nCommands = 0; + cmd_list.clear(); + } + } + lastupdate = true; + counters.getCommands(cmd_list, lastupdate); + cmd_list.clear(); + } + counters.clear(); + trace.close(); +} // TraceParser::parseFile diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/TraceParser.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/TraceParser.h new file mode 100644 index 0000000000..3f68ea6ef2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/TraceParser.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Omar Naji + * + */ + +#ifndef TRACE_PARSER_H +#define TRACE_PARSER_H + +#include +#include + +#include "MemCommand.h" +#include "MemorySpecification.h" +#include "CommandAnalysis.h" + + +class TraceParser { + public: + TraceParser(const Data::MemorySpecification& memSpec); + // list of parsed commands + std::vector cmd_list; + + // function for parsing one line of the trace + Data::MemCommand parseLine(std::string line); + + Data::CommandAnalysis counters; + // function for parsing the whole file. + // use this function for small traces ( no out-of-memory issue ) + void parseFile(Data::MemorySpecification memSpec, + std::ifstream& trace, + int window, + int grouping, + int interleaving, + int burst, + int powerdown, + int trans); +}; + +#endif // ifndef TRACE_PARSER_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/Utils.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/Utils.h new file mode 100644 index 0000000000..7c165a3034 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/Utils.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + * + */ + +#ifndef UTILS_H +#define UTILS_H + +#include +#include +#include + + +template +T fromString(const std::string& s, + std::ios_base& (*f)(std::ios_base &) = std::dec) +{ + std::istringstream is(s); + T t; + + if (!(is >> f >> t)) { + throw std::runtime_error("Cannot convert string"); + } + + return t; +} + +#endif /* UTILS_H */ diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/libdrampower/LibDRAMPower.cc b/hotness/SimpleSSD-Standalone/lib/drampower/src/libdrampower/LibDRAMPower.cc new file mode 100644 index 0000000000..65eedacb5d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/libdrampower/LibDRAMPower.cc @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#include "LibDRAMPower.h" + +using namespace Data; + +libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination) : + memSpec(memSpec), + counters(memSpec), + includeIoAndTermination(includeIoAndTermination), + mpm(MemoryPowerModel()) +{ + MemBankWiseParams p (100,100,false,0,false,static_cast(memSpec.memArchSpec.nbrOfBanks)); + libDRAMPower DRAMPower = libDRAMPower(memSpec, 0, p); +} + +libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination, const Data::MemBankWiseParams& bwPowerParams) : + memSpec(memSpec), + counters(CommandAnalysis(memSpec)), + includeIoAndTermination(includeIoAndTermination), + bwPowerParams(bwPowerParams) +{ +} + +libDRAMPower::~libDRAMPower() +{ +} + +void libDRAMPower::doCommand(MemCommand::cmds type, int bank, int64_t timestamp) +{ + MemCommand cmd(type, static_cast(bank), timestamp); + cmdList.push_back(cmd); +} + +void libDRAMPower::updateCounters(bool lastUpdate, int64_t timestamp) +{ + counters.getCommands(cmdList, lastUpdate, timestamp); + cmdList.clear(); +} + +void libDRAMPower::calcEnergy() +{ + updateCounters(true); + mpm.power_calc(memSpec, counters, includeIoAndTermination, bwPowerParams); +} + +void libDRAMPower::calcWindowEnergy(int64_t timestamp) +{ + doCommand(MemCommand::NOP, 0, timestamp); + updateCounters(false, timestamp); + mpm.power_calc(memSpec, counters, includeIoAndTermination, bwPowerParams); + clearCounters(timestamp); +} + + +void libDRAMPower::clearState() +{ + counters.clear(); +} + +void libDRAMPower::clearCounters(int64_t timestamp) +{ + counters.clearStats(timestamp); +} + +const Data::MemoryPowerModel::Energy& libDRAMPower::getEnergy() const +{ + return mpm.energy; +} + +const Data::MemoryPowerModel::Power& libDRAMPower::getPower() const +{ + return mpm.power; +} diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/libdrampower/LibDRAMPower.h b/hotness/SimpleSSD-Standalone/lib/drampower/src/libdrampower/LibDRAMPower.h new file mode 100644 index 0000000000..a9117659b9 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/libdrampower/LibDRAMPower.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2014, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung + * Omar Naji + * Subash Kannoth + * Éder F. Zulian + * Felipe S. Prado + * + */ + +#ifndef LIB_DRAM_POWER_H +#define LIB_DRAM_POWER_H + +#include +#include + +#include "CommandAnalysis.h" +#include "MemoryPowerModel.h" +#include "MemCommand.h" +#include "MemBankWiseParams.h" + + +class libDRAMPower { + public: + libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination); + libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination,const Data::MemBankWiseParams& bwPowerParams); + ~libDRAMPower(); + + void doCommand(Data::MemCommand::cmds type, + int bank, + int64_t timestamp); + + void calcEnergy(); + + void calcWindowEnergy(int64_t timestamp); + + const Data::MemoryPowerModel::Energy& getEnergy() const; + const Data::MemoryPowerModel::Power& getPower() const; + + // list of all commands + std::vector cmdList; + private: + void updateCounters(bool lastUpdate, int64_t timestamp = 0); + + void clearCounters(int64_t timestamp); + + void clearState(); + + Data::MemorySpecification memSpec; + public: + Data::CommandAnalysis counters; + private: + bool includeIoAndTermination; + [[maybe_unused]] bool bankwiseMode; + Data:: MemBankWiseParams bwPowerParams; + // Object of MemoryPowerModel which contains the results + // Energies(pJ) stored in energy, Powers(mW) stored in power. Number of + // each command stored in timings. + Data::MemoryPowerModel mpm; +}; + +#endif // ifndef LIB_DRAM_POWER_H diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/src/uncrustify.cfg b/hotness/SimpleSSD-Standalone/lib/drampower/src/uncrustify.cfg new file mode 100644 index 0000000000..ffe0e5f9c2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/src/uncrustify.cfg @@ -0,0 +1,280 @@ +tok_split_gte=false +utf8_byte=false +utf8_force=false +indent_cmt_with_tabs=false +indent_align_string=true +indent_braces=false +indent_braces_no_func=false +indent_braces_no_class=false +indent_braces_no_struct=false +indent_brace_parent=false +indent_namespace=false +indent_extern=false +indent_class=true +indent_class_colon=true +indent_else_if=false +indent_var_def_cont=false +indent_func_call_param=false +indent_func_def_param=false +indent_func_proto_param=false +indent_func_class_param=false +indent_func_ctor_var_param=false +indent_template_param=false +indent_func_param_double=false +indent_relative_single_line_comments=false +indent_col1_comment=true +indent_access_spec_body=false +indent_paren_nl=false +indent_comma_paren=false +indent_bool_paren=false +indent_first_bool_expr=false +indent_square_nl=false +indent_preserve_sql=false +indent_align_assign=true +sp_balance_nested_parens=false +align_keep_tabs=false +align_with_tabs=false +align_on_tabstop=false +align_number_left=true +align_func_params=true +align_same_func_call_params=true +align_var_def_colon=true +align_var_def_attribute=true +align_var_def_inline=true +align_right_cmt_mix=false +align_on_operator=true +align_mix_var_proto=false +align_single_line_func=true +align_single_line_brace=true +align_nl_cont=true +align_left_shift=true +align_oc_decl_colon=false +nl_collapse_empty_body=false +nl_assign_leave_one_liners=false +nl_class_leave_one_liners=false +nl_enum_leave_one_liners=false +nl_getset_leave_one_liners=false +nl_func_leave_one_liners=false +nl_if_leave_one_liners=false +nl_multi_line_cond=false +nl_multi_line_define=false +nl_before_case=true +nl_after_case=false +nl_after_return=true +nl_after_semicolon=true +nl_after_brace_open=false +nl_after_brace_open_cmt=false +nl_after_vbrace_open=false +nl_after_vbrace_open_empty=false +nl_after_brace_close=false +nl_after_vbrace_close=false +nl_define_macro=true +nl_squeeze_ifdef=false +nl_ds_struct_enum_cmt=true +nl_ds_struct_enum_close_brace=true +nl_create_if_one_liner=false +nl_create_for_one_liner=false +nl_create_while_one_liner=false +ls_for_split_full=false +ls_func_split_full=false +nl_after_multiline_comment=true +eat_blanks_after_open_brace=true +eat_blanks_before_close_brace=true +mod_full_brace_if_chain=true +mod_pawn_semicolon=false +mod_full_paren_if_bool=true +mod_remove_extra_semicolon=true +mod_sort_import=false +mod_sort_using=false +mod_sort_include=false +mod_move_case_break=true +mod_remove_empty_return=true +cmt_indent_multi=true +cmt_c_group=false +cmt_c_nl_start=false +cmt_c_nl_end=false +cmt_cpp_group=false +cmt_cpp_nl_start=false +cmt_cpp_nl_end=false +cmt_cpp_to_c=false +cmt_star_cont=false +cmt_multi_check_last=true +cmt_insert_before_preproc=false +pp_indent_at_level=false +pp_region_indent_code=false +pp_if_indent_code=false +pp_define_at_level=false +output_tab_size=2 +indent_columns=2 +indent_namespace_level=0 +indent_namespace_limit=0 +indent_access_spec=-1 +align_var_def_span=2 +align_var_def_star_style=0 +align_var_def_amp_style=0 +align_var_def_thresh=2 +align_var_def_gap=1 +align_assign_span=3 +align_assign_thresh=12 +align_enum_equ_span=1 +align_var_struct_span=1 +align_struct_init_span=1 +align_typedef_span=1 +align_typedef_star_style=2 +align_typedef_amp_style=2 +align_right_cmt_span=4 +align_right_cmt_at_col=1 +align_func_proto_span=1 +nl_end_of_file_min=1 +nl_func_var_def_blk=1 +nl_max=2 +nl_after_func_proto=0 +nl_after_func_body=2 +nl_after_func_body_class=2 +nl_after_func_body_one_liner=2 +nl_before_access_spec=2 +nl_after_access_spec=1 +nl_comment_func_def=1 +nl_after_try_catch_finally=1 +mod_full_brace_nl=1 +mod_add_long_function_closebrace_comment=16 +mod_add_long_switch_closebrace_comment=16 +mod_add_long_ifdef_endif_comment=16 +mod_add_long_ifdef_else_comment=16 +newlines=auto +indent_with_tabs=0 +sp_arith=add +sp_assign=add +sp_enum_assign=add +sp_pp_concat=add +sp_pp_stringify=add +sp_bool=add +sp_compare=add +sp_inside_paren=remove +sp_paren_paren=remove +sp_paren_brace=add +sp_before_ptr_star=remove +sp_before_unnamed_ptr_star=remove +sp_between_ptr_star=remove +sp_after_ptr_star=force +sp_after_ptr_star_func=force +sp_before_ptr_star_func=remove +sp_before_byref=remove +sp_before_unnamed_byref=remove +sp_after_byref=add +sp_after_byref_func=add +sp_before_byref_func=remove +sp_after_type=add +sp_before_angle=remove +sp_inside_angle=remove +sp_after_angle=remove +sp_angle_paren=remove +sp_angle_word=force +sp_before_sparen=force +sp_inside_sparen=remove +sp_after_sparen=remove +sp_sparen_brace=add +sp_special_semi=remove +sp_before_semi=remove +sp_before_semi_for=remove +sp_before_semi_for_empty=remove +sp_after_semi_for_empty=remove +sp_before_square=remove +sp_before_squares=remove +sp_inside_square=remove +sp_after_comma=add +sp_before_comma=remove +sp_after_class_colon=add +sp_before_class_colon=add +sp_before_case_colon=remove +sp_after_operator=remove +sp_after_operator_sym=remove +sp_after_cast=remove +sp_inside_paren_cast=remove +sp_cpp_cast_paren=remove +sp_sizeof_paren=remove +sp_inside_braces_enum=add +sp_inside_braces_struct=add +sp_inside_braces=add +sp_inside_braces_empty=remove +sp_type_func=add +sp_func_proto_paren=remove +sp_func_def_paren=remove +sp_inside_fparens=remove +sp_inside_fparen=remove +sp_square_fparen=remove +sp_fparen_brace=add +sp_func_call_paren=remove +sp_func_call_user_paren=remove +sp_func_class_paren=remove +sp_return_paren=add +sp_attribute_paren=remove +sp_defined_paren=remove +sp_throw_paren=remove +sp_macro=add +sp_macro_func=remove +sp_else_brace=add +sp_brace_else=add +sp_brace_typedef=add +sp_catch_brace=add +sp_brace_catch=add +sp_finally_brace=add +sp_brace_finally=add +sp_try_brace=add +sp_getset_brace=add +sp_before_dc=remove +sp_after_dc=remove +sp_not=remove +sp_inv=remove +sp_addr=remove +sp_member=remove +sp_deref=remove +sp_sign=remove +sp_incdec=remove +sp_before_nl_cont=remove +sp_after_oc_scope=remove +sp_after_oc_colon=remove +sp_before_oc_colon=remove +sp_after_send_oc_colon=add +sp_before_send_oc_colon=remove +sp_after_oc_type=remove +sp_cond_colon=add +sp_cond_question=add +sp_cmt_cpp_start=add +nl_start_of_file=remove +nl_end_of_file=force +nl_fcall_brace=force +nl_if_brace=remove +nl_brace_else=remove +nl_elseif_brace=remove +nl_else_brace=remove +nl_else_if=remove +nl_for_brace=remove +nl_while_brace=remove +nl_do_brace=remove +nl_switch_brace=remove +nl_namespace_brace=remove +nl_class_brace=remove +nl_class_init_args=add +nl_func_def_paren=remove +nl_func_decl_start=remove +nl_func_decl_args=add +nl_fdef_brace=force +nl_before_if=ignore +nl_after_if=ignore +nl_before_for=ignore +nl_after_for=ignore +nl_before_while=ignore +nl_after_while=ignore +nl_before_switch=ignore +nl_after_switch=ignore +nl_before_do=ignore +nl_after_do=ignore +mod_full_brace_do=force +mod_full_brace_for=force +mod_full_brace_function=force +mod_full_brace_if=force +mod_full_brace_while=force +mod_full_brace_using=remove +mod_paren_on_return=remove +pp_space=force diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/test/.DS_Store b/hotness/SimpleSSD-Standalone/lib/drampower/test/.DS_Store new file mode 100644 index 0000000000..2fdc097c13 Binary files /dev/null and b/hotness/SimpleSSD-Standalone/lib/drampower/test/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/test/libdrampowertest/commands.trace b/hotness/SimpleSSD-Standalone/lib/drampower/test/libdrampowertest/commands.trace new file mode 100644 index 0000000000..75e34a21d5 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/test/libdrampowertest/commands.trace @@ -0,0 +1,19 @@ +35,ACT,0 +50,RDA,0 +51,ACT,4 +66,RDA,4 +86,ACT,0 +101,RDA,0 +102,ACT,2 +117,RDA,2 +119,ACT,5 +134,RDA,5 +137,ACT,0 +152,RDA,0 +159,ACT,3 +174,RDA,3 +195,ACT,0 +210,RDA,0 +232,ACT,4 +247,WRA,4 +265,PDN_F_PRE,3 diff --git a/hotness/SimpleSSD-Standalone/lib/drampower/test/libdrampowertest/lib_test.cc b/hotness/SimpleSSD-Standalone/lib/drampower/test/libdrampowertest/lib_test.cc new file mode 100644 index 0000000000..a79839eef8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/lib/drampower/test/libdrampowertest/lib_test.cc @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2014, TU Delft, TU Eindhoven and TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung, Omar Naji, Felipe S. Prado + * + */ + +#include +#include +#include "libdrampower/LibDRAMPower.h" + +#if USE_XERCES +#include "xmlparser/MemSpecParser.h" +#endif + +using namespace std; +using namespace Data; + +int main(int argc, char* argv[]) +{ + assert(argc == 2); + //Setup of DRAMPower for your simulation + string filename; + //type path to memspec file + filename = argv[1]; + //Parsing the Memspec specification of found in memspec folder +#if USE_XERCES + MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(filename)); +#else + MemorySpecification memSpec; +#endif + libDRAMPower test = libDRAMPower(memSpec, 0); + + ios_base::fmtflags flags = cout.flags(); + streamsize precision = cout.precision(); + cout.precision(2); + cout << fixed << endl; + + // During the simulation you can report activity + // to DRAMPower with the doCommand(...) function: + test.doCommand(MemCommand::ACT,0,35); + test.doCommand(MemCommand::RDA,0,50); + test.doCommand(MemCommand::ACT,4,51); + test.doCommand(MemCommand::RDA,4,66); + test.doCommand(MemCommand::ACT,0,86); + test.doCommand(MemCommand::RDA,0,101); + test.doCommand(MemCommand::ACT,2,102); + test.doCommand(MemCommand::RDA,2,117); + test.doCommand(MemCommand::ACT,5,119); + test.doCommand(MemCommand::RDA,5,134); + test.doCommand(MemCommand::ACT,0,137); + test.doCommand(MemCommand::RDA,0,152); + test.doCommand(MemCommand::ACT,3,159); + test.doCommand(MemCommand::RDA,3,174); + test.doCommand(MemCommand::ACT,0,195); + test.doCommand(MemCommand::RDA,0,210); + test.doCommand(MemCommand::ACT,4,232); + test.doCommand(MemCommand::WRA,4,247); + // Need at least tWRAPDEN = AL + CWL + BL/2 + WR + 1 cycles between WR and PDN_F_PRE + test.doCommand(MemCommand::PDN_F_PRE,3,265); + // Exit from Precharge Power-down + test.doCommand(MemCommand::PUP_PRE,3,300); + // Activate bank 0 + test.doCommand(MemCommand::ACT,0,350); + // Precharge all banks with bank 0 active + test.doCommand(MemCommand::PREA,0,400); + // Precharge all banks again + // XXX: For testing purpose only! Double precharge all should never + // happen. Warnings are generated. + test.doCommand(MemCommand::PREA,0,450); + // Activate bank 0 twice + // XXX: For testing purpose only! Double activate should never happen. + // Warnings are generated. + test.doCommand(MemCommand::ACT,0,500); + test.doCommand(MemCommand::ACT,0,550); + // Precharge bank 0 twice + // XXX: For testing purpose only! Double precharge for the same bank + // should never happen. Warnings are generated. + test.doCommand(MemCommand::PRE,0,600); + test.doCommand(MemCommand::PRE,0,650); + + // At the end of your simulation call the getEnergy(...) + // function to print the power report + test.calcEnergy(); + + // Accesing the results: + + // Number of issued Commands + std::cout << "Number of ACTs: " << std::accumulate(test.counters.numberofactsBanks.begin(), + test.counters.numberofactsBanks.end() + ,0)<< endl; + std::cout << "Number of RDs: " << std::accumulate(test.counters.numberofreadsBanks.begin(), + test.counters.numberofreadsBanks.end() + ,0)<< endl; + std::cout << "Number of PREs: " << std::accumulate(test.counters.numberofpresBanks.begin(), + test.counters.numberofpresBanks.end() + ,0)<< endl; + // many other timing parameters in test.mpm.timings + + //ENERGIES per Rank + std::cout << "ACT Cmd Energy: " << test.getEnergy().act_energy << " pJ" << endl; + std::cout << "PRE Cmd Energy: " << test.getEnergy().pre_energy << " pJ" << endl; + std::cout << "RD Cmd Energy: " << test.getEnergy().read_energy << " pJ" << endl; + std::cout << "WR Cmd Energy: " << test.getEnergy().write_energy << " pJ" << endl << endl; + //Standby Energy for 1 rank + //In total energy calculated for both ranks= test.memSpec.memArchSpec * + //test.getEnergy().act_stdby_energy + std::cout << "ACT Stdby Energy: " << test.getEnergy().act_stdby_energy << " pJ" << endl; + //total active standby energy for both ranks + std::cout << "ACT Stdby Energy total ranks: " << static_cast(memSpec.memArchSpec.nbrOfRanks) * + test.getEnergy().act_stdby_energy << " pJ" << endl ; + std::cout << "PRE Stdby Energy: " << test.getEnergy().pre_stdby_energy << " pJ" << endl << endl; + std::cout << "Total Trace Energy: " << test.getEnergy().total_energy << " pJ" << endl; + //many other energies in test.mpm.energy + + //Powers per Rank + std::cout << "Average Power: " << test.getPower().average_power << " mW" << endl; + //many other powers in test.getPower() + + cout.flags(flags); + cout.precision(precision); + + return 0; +} diff --git a/hotness/SimpleSSD-Standalone/sil/.DS_Store b/hotness/SimpleSSD-Standalone/sil/.DS_Store new file mode 100644 index 0000000000..47e71297eb Binary files /dev/null and b/hotness/SimpleSSD-Standalone/sil/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/sil/none/none.cc b/hotness/SimpleSSD-Standalone/sil/none/none.cc new file mode 100644 index 0000000000..a034970226 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/none/none.cc @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/none/none.hh" + +#include "simplessd/util/algorithm.hh" + +namespace SIL { + +namespace None { + +Driver::Driver(Engine &e, SimpleSSD::ConfigReader &conf) + : BIL::DriverInterface(e), totalLogicalPages(0), logicalPageSize(0) { + pHIL = new SimpleSSD::HIL::HIL(conf); +} + +Driver::~Driver() { + delete pHIL; +} + +void Driver::init(std::function &func) { + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + // No initialization process is needed for NoneDriver + beginFunction = func; + + auto eid = engine.allocateEvent([this](uint64_t) { beginFunction(); }); + engine.scheduleEvent(eid, 0); + + SimpleSSD::info("SIL::None::Driver: Total SSD capacity: %" PRIu64 " bytes", + totalLogicalPages * logicalPageSize); + SimpleSSD::info("SIL::None::Driver: Logical Page Size: %" PRIu32 " bytes", + logicalPageSize); +} + +void Driver::getInfo(uint64_t &bytesize, uint32_t &minbs) { + bytesize = totalLogicalPages * logicalPageSize; + minbs = 512; +} + +void Driver::submitIO(BIL::BIO &bio) { + SimpleSSD::HIL::Request req; + auto *pFunc = new std::function(bio.callback); + + // Convert to request + req.reqID = bio.id; + req.range.slpn = bio.offset / logicalPageSize; + req.range.nlp = DIVCEIL(bio.length, logicalPageSize); + req.offset = bio.offset % logicalPageSize; + req.length = bio.length; + req.temperature = bio.temperature; + req.context = (void *)bio.id; + req.function = [pFunc](uint64_t, void *context) { + pFunc->operator()((uint64_t)context); + delete pFunc; + }; + + // Submit + switch (bio.type) { + case BIL::BIO_READ: + pHIL->read(req); + break; + case BIL::BIO_WRITE: + pHIL->write(req); + break; + case BIL::BIO_FLUSH: + pHIL->flush(req); + break; + case BIL::BIO_TRIM: + pHIL->trim(req); + break; + default: + break; + } +} + +void Driver::initStats(std::vector &list) { + pHIL->getStatList(list, ""); + SimpleSSD::getCPUStatList(list, "cpu"); +} + +void Driver::getStats(std::vector &values) { + pHIL->getStatValues(values); + SimpleSSD::getCPUStatValues(values); +} + +} // namespace None + +} // namespace SIL diff --git a/hotness/SimpleSSD-Standalone/sil/none/none.hh b/hotness/SimpleSSD-Standalone/sil/none/none.hh new file mode 100644 index 0000000000..e02c6621cf --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/none/none.hh @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NONE__ +#define __DRIVERS_NONE__ + +#include "bil/interface.hh" +#include "simplessd/hil/hil.hh" + +namespace SIL { + +namespace None { + +class Driver : public BIL::DriverInterface { + private: + SimpleSSD::HIL::HIL *pHIL; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + + public: + Driver(Engine &, SimpleSSD::ConfigReader &); + ~Driver(); + + void init(std::function &) override; + void getInfo(uint64_t &, uint32_t &) override; + void submitIO(BIL::BIO &) override; + + void initStats(std::vector &) override; + void getStats(std::vector &) override; +}; + +} // namespace None + +} // namespace SIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/sil/nvme/nvme.cc b/hotness/SimpleSSD-Standalone/sil/nvme/nvme.cc new file mode 100644 index 0000000000..3352bb222c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/nvme/nvme.cc @@ -0,0 +1,623 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/nvme/nvme.hh" + +#include "simplessd/hil/nvme/controller.hh" +#include "simplessd/hil/nvme/def.hh" +#include "simplessd/util/algorithm.hh" + +namespace SIL { + +namespace NVMe { + +Driver::Driver(Engine &e, SimpleSSD::ConfigReader &conf) + : BIL::DriverInterface(e), + dmaReadPending(false), + dmaWritePending(false), + phase(true), + adminSQ(nullptr), + adminCQ(nullptr), + ioSQ(nullptr), + ioCQ(nullptr) { + pcieGen = (SimpleSSD::PCIExpress::PCIE_GEN)conf.readInt( + SimpleSSD::CONFIG_NVME, SimpleSSD::HIL::NVMe::NVME_PCIE_GEN); + pcieLane = (uint8_t)conf.readUint(SimpleSSD::CONFIG_NVME, + SimpleSSD::HIL::NVMe::NVME_PCIE_LANE); + + pController = new SimpleSSD::HIL::NVMe::Controller(this, conf); + + dmaReadEvent = engine.allocateEvent([this](uint64_t) { dmaReadDone(); }); + dmaWriteEvent = engine.allocateEvent([this](uint64_t) { dmaWriteDone(); }); +} + +Driver::~Driver() { + delete pController; + delete adminSQ; + delete adminCQ; + delete ioSQ; + delete ioCQ; +} + +void Driver::init(std::function &func) { + beginFunction = func; + + // NVMe Initialization process (Register) + // See Section 7.6.1. Initialization of NVMe 1.3c + union { + uint64_t value; + uint8_t buffer[8]; + } temp; + uint64_t tick = 0; + + // Step 1. Read CAP + pController->readRegister(SimpleSSD::HIL::NVMe::REG_CONTROLLER_CAPABILITY, 8, + temp.buffer, tick); + + // MPSMAX/MIN is setted to 4KB + // DSTRD is setted to 0 (4bytes) + // Check MQES + maxQueueEntries = (temp.value & 0xFFFF) + 1; + + // Step 2. Wait for CSTS.RDY = 0 + // Step 3. Configure admin queue + // Step 3-1. Set admin queue entry size + uint16_t entries = QUEUE_ENTRY_ADMIN; + + if (entries > maxQueueEntries) { + entries = maxQueueEntries; + } + + temp.value = entries - 1; + temp.value |= (entries - 1) << 16; + + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_ADMIN_QUEUE_ATTRIBUTE, 4, + temp.buffer, tick); + + adminSQ = new Queue(entries, 64); + adminCQ = new Queue(entries, 16); + + // Step 3-2. Write base addresses + adminSQ->getBaseAddress(temp.value); + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_ADMIN_SQUEUE_BASE_ADDR, + 8, temp.buffer, tick); + adminCQ->getBaseAddress(temp.value); + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_ADMIN_CQUEUE_BASE_ADDR, + 8, temp.buffer, tick); + + // Step 4. Configure controller + // Step 5. Enable controller + temp.value = 1; // Round Robin, 4K page, NVM command set, Enable + temp.value |= 0x00460000; // 64B SQEntry, 16B CQEntry + pController->writeRegister(SimpleSSD::HIL::NVMe::REG_CONTROLLER_CONFIG, 4, + temp.buffer, tick); + + // Step 6. Wait for CSTS.RDY = 1 + // Step 7. Send Identify + // Step 7-1. Submit Identify Controller + uint32_t cmd[16]; + PRP *prp = new PRP(4096); + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init0(status, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_IDENTIFY; // CID, FUSE, OPC + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + cmd[10] = SimpleSSD::HIL::NVMe::CNS_IDENTIFY_CONTROLLER; // CNS + + submitCommand(0, (uint8_t *)cmd, callback, prp); +} + +void Driver::_init0(uint16_t, void *context) { + PRP *prp = (PRP *)context; + + // Step 7-2. Send Identify Active Namespace List + // Reuse PRP here + uint32_t cmd[16]; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init1(status, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_IDENTIFY; // CID, FUSE, OPC + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + cmd[10] = SimpleSSD::HIL::NVMe::CNS_ACTIVE_NAMESPACE_LIST; // CNS + + submitCommand(0, (uint8_t *)cmd, callback, prp); +} + +void Driver::_init1(uint16_t, void *context) { + PRP *prp = (PRP *)context; + + // Step 7-3. Check active Namespace + // We will perform I/O on first Namespace + uint32_t count = 0; + uint32_t nsid = 0; + + for (count = 0; count < 1024; count++) { + prp->readData(count * 4, 4, (uint8_t *)&nsid); + + if (nsid == 0) { + break; + } + + if (count == 0) { + namespaceID = nsid; + } + } + + if (count == 0) { + SimpleSSD::panic("This NVMe SSD does not have any namespaces."); + } + else if (count > 1) { + SimpleSSD::warn("This NVMe SSD has %u namespaces.", count); + SimpleSSD::warn("All I/O will performed on namespace ID %u.", namespaceID); + } + + // Step 7-4. Send Identify Namespace + // Reuse PRP here + uint32_t cmd[16]; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init2(status, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_IDENTIFY; // CID, FUSE, OPC + cmd[1] = namespaceID; // NSID + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + cmd[10] = SimpleSSD::HIL::NVMe::CNS_IDENTIFY_NAMESPACE; // CNS + + submitCommand(0, (uint8_t *)cmd, callback, prp); +} + +void Driver::_init2(uint16_t, void *context) { + union { + uint64_t value; + uint8_t buffer[8]; + } temp; + PRP *prp = (PRP *)context; + uint8_t nFormat, currentFormat; + uint32_t formatData; + + // Step 7-4. Check structures + prp->readData(0, 8, temp.buffer); + capacity = temp.value; + + prp->readData(25, 1, &nFormat); + nFormat++; + + prp->readData(26, 1, ¤tFormat); + prp->readData(128 + currentFormat * 4ull, 4, (uint8_t *)&formatData); + + LBAsize = (uint32_t)powf(2.f, (float)((formatData >> 16) & 0xFF)); + capacity *= LBAsize; + + delete prp; + + SimpleSSD::info("SIL::NVMe::Driver: Total SSD capacity: %" PRIu64 " bytes", + capacity); + SimpleSSD::info("SIL::NVMe::Driver: Logical Block Size: %" PRIu32 " bytes", + LBAsize); + + // Step 8. Determine I/O queue count + // Step 8-1. Send Set Feature + uint32_t cmd[16]; + ResponseHandler callback = [this](uint16_t status, uint32_t dw0, + void *context) { + _init3(status, dw0, context); + }; + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_SET_FEATURES; // CID, FUSE, OPC + cmd[10] = SimpleSSD::HIL::NVMe::FEATURE_NUMBER_OF_QUEUES; // FID + cmd[11] = 0x00000000; // One I/O SQ, One I/O CQ + + submitCommand(0, (uint8_t *)cmd, callback, nullptr); +} + +void Driver::_init3(uint16_t, uint32_t dw0, void *) { + // Step 8-2. Check response + if (dw0 != 0x00000000) { + SimpleSSD::warn("NVMe SSD responsed too many I/O queue"); + } + + // Step 9. Allocate I/O Completion Queue + // Step 9-1. Send Create I/O Completion Queue + uint32_t cmd[16]; + uint16_t entries = QUEUE_ENTRY_IO; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init4(status, context); + }; + + if (entries > maxQueueEntries) { + entries = maxQueueEntries; + } + + ioCQ = new Queue(entries, 16); + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_CREATE_IO_CQUEUE; // CID, FUSE, OPC + ioCQ->getBaseAddress(*(uint64_t *)(cmd + 6)); // DPTR.PRP1 + cmd[10] = ((uint32_t)(entries - 1) << 16) | 0x0001; // QSIZE, QID + cmd[11] = 0x00010003; // IV, IEN, PC + + submitCommand(0, (uint8_t *)cmd, callback, nullptr); +} + +void Driver::_init4(uint16_t status, void *) { + // Step 9-2. Check result + if (status != 0) { + SimpleSSD::panic("Failed to create I/O Completion Queue"); + } + + // Step 10. Allocate I/O Submission Queue + // Step 10-1. Send Create I/O Submission Queue + uint32_t cmd[16]; + uint16_t entries = QUEUE_ENTRY_IO; + ResponseHandler callback = [this](uint16_t status, uint32_t, void *context) { + _init5(status, context); + }; + + if (entries > maxQueueEntries) { + entries = maxQueueEntries; + } + + ioSQ = new Queue(entries, 64); + + memset(cmd, 0, 64); + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_CREATE_IO_SQUEUE; // CID, FUSE, OPC + ioSQ->getBaseAddress(*(uint64_t *)(cmd + 6)); // DPTR.PRP1 + cmd[10] = ((uint32_t)(entries - 1) << 16) | 0x0001; // QSIZE, QID + cmd[11] = 0x00010001; // CQID, QPRIO, PC + + submitCommand(0, (uint8_t *)cmd, callback, nullptr); +} + +void Driver::_init5(uint16_t status, void *) { + // Step 10-2. Check result + if (status != 0) { + SimpleSSD::panic("Failed to create I/O Submission Queue"); + } + + SimpleSSD::info("SIL::NVMe::Driver: Initialization finished"); + + // Now we initialized NVMe SSD + beginFunction(); +} + +void Driver::submitCommand(uint16_t iv, uint8_t *cmd, ResponseHandler &func, + void *context) { + uint16_t cid = 0; + uint16_t opcode = cmd[0]; + uint16_t tail = 0; + uint64_t tick = engine.getCurrentTick(); + Queue *queue = nullptr; + + // Push to queue + if (iv == 0) { + increaseCommandID(adminCommandID); + cid = adminCommandID; + queue = adminSQ; + } + else if (iv == 1 && ioSQ) { + increaseCommandID(ioCommandID); + cid = ioCommandID; + queue = ioSQ; + } + else { + SimpleSSD::panic("I/O Submission Queue is not initialized"); + } + + memcpy(cmd + 2, &cid, 2); + queue->setData(cmd, 64); + tail = queue->getTail(); + + // Push to pending cmd list + pendingCommandList.push_back(CommandEntry(iv, opcode, cid, context, func)); + + // Ring doorbell + pController->ringSQTailDoorbell(iv, tail, tick); + queue->incrHead(); +} + +void Driver::increaseCommandID(uint16_t &id) { + static const uint16_t maxID = 32767; + + id++; + + if (id > maxID) { + id = 1; + } +} + +void Driver::getInfo(uint64_t &bytesize, uint32_t &minbs) { + bytesize = capacity; + minbs = LBAsize; +} + +void Driver::submitIO(BIL::BIO &bio) { + uint32_t cmd[16]; + PRP *prp = nullptr; + static ResponseHandler callback = [this](uint16_t status, uint32_t, + void *context) { + _io(status, context); + }; + + memset(cmd, 0, 64); + + uint64_t slba = bio.offset / LBAsize; + uint32_t nlb = (uint32_t)DIVCEIL(bio.length, LBAsize); + + cmd[1] = namespaceID; // NSID + + if (bio.type == BIL::BIO_READ) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_READ; // CID, FUSE, OPC + cmd[10] = (uint32_t)slba; + cmd[11] = slba >> 32; + cmd[12] = nlb - 1; // LR, FUA, PRINFO, NLB + + prp = new PRP(bio.length); + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + } + else if (bio.type == BIL::BIO_WRITE) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_WRITE; // CID, FUSE, OPC + cmd[10] = (uint32_t)slba; + cmd[11] = slba >> 32; + cmd[12] = nlb - 1; // LR, FUA, PRINFO, DTYPE, NLB + + prp = new PRP(bio.length); + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + } + else if (bio.type == BIL::BIO_FLUSH) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_FLUSH; // CID, FUSE, OPC + } + else if (bio.type == BIL::BIO_TRIM) { + cmd[0] = SimpleSSD::HIL::NVMe::OPCODE_DATASET_MANAGEMEMT; // CID, FUSE, OPC + cmd[10] = 0; // NR + cmd[11] = 0x04; // AD + + prp = new PRP(16); + prp->getPointer(*(uint64_t *)(cmd + 6), *(uint64_t *)(cmd + 8)); // DPTR + + // Fill range definition + uint8_t data[16]; + + memset(data, 0, 16); + memcpy(data + 4, &nlb, 4); + memcpy(data + 8, &slba, 8); + + prp->writeData(0, 16, data); + } + + submitCommand(1, (uint8_t *)cmd, callback, + new IOWrapper(bio.id, prp, bio.callback)); +} + +void Driver::_io(uint16_t status, void *context) { + IOWrapper *wrapper = (IOWrapper *)context; + PRP *prp = wrapper->prp; + + if (status != 0) { + SimpleSSD::warn("I/O error: %04X", status); + } + + wrapper->bioCallback(wrapper->id); + + delete prp; + delete wrapper; +} + +void Driver::initStats(std::vector &list) { + pController->getStatList(list, ""); + SimpleSSD::getCPUStatList(list, "cpu"); +} + +void Driver::getStats(std::vector &values) { + pController->getStatValues(values); + SimpleSSD::getCPUStatValues(values); +} + +void Driver::dmaRead(uint64_t addr, uint64_t size, uint8_t *buffer, + SimpleSSD::DMAFunction &func, void *context) { + if (size == 0) { + SimpleSSD::warn("nvme_interface: zero-size DMA read request. Ignore."); + + return; + } + + dmaReadQueue.push(DMAEntry(func)); + + auto &iter = dmaReadQueue.back(); + iter.addr = addr; + iter.size = size; + iter.buffer = buffer; + iter.context = context; + + if (!dmaReadPending) { + submitDMARead(); + } +} + +void Driver::dmaReadDone() { + auto &iter = dmaReadQueue.front(); + uint64_t tick = engine.getCurrentTick(); + + if (tick < iter.finishedAt) { + engine.scheduleEvent(dmaReadEvent, iter.finishedAt); + + return; + } + + iter.func(tick, iter.context); + dmaReadQueue.pop(); + dmaReadPending = false; + + if (dmaReadQueue.size() > 0) { + submitDMARead(); + } +} + +void Driver::submitDMARead() { + auto &iter = dmaReadQueue.front(); + + dmaReadPending = true; + + iter.beginAt = engine.getCurrentTick(); + iter.finishedAt = iter.beginAt + SimpleSSD::PCIExpress::calculateDelay( + pcieGen, pcieLane, iter.size); + + if (iter.buffer) { + memcpy(iter.buffer, (uint8_t *)iter.addr, iter.size); + } + + engine.scheduleEvent(dmaReadEvent, iter.finishedAt); +} + +void Driver::dmaWrite(uint64_t addr, uint64_t size, uint8_t *buffer, + SimpleSSD::DMAFunction &func, void *context) { + if (size == 0) { + SimpleSSD::warn("nvme_interface: zero-size DMA write request. Ignore."); + + return; + } + + dmaWriteQueue.push(DMAEntry(func)); + + auto &iter = dmaWriteQueue.back(); + iter.addr = addr; + iter.size = size; + iter.buffer = buffer; + iter.context = context; + + if (!dmaWritePending) { + submitDMAWrite(); + } +} + +void Driver::dmaWriteDone() { + auto &iter = dmaWriteQueue.front(); + uint64_t tick = engine.getCurrentTick(); + + if (tick < iter.finishedAt) { + engine.scheduleEvent(dmaWriteEvent, iter.finishedAt); + + return; + } + + iter.func(tick, iter.context); + dmaWriteQueue.pop(); + dmaWritePending = false; + + if (dmaWriteQueue.size() > 0) { + submitDMAWrite(); + } +} + +void Driver::submitDMAWrite() { + auto &iter = dmaWriteQueue.front(); + + dmaWritePending = true; + + iter.beginAt = engine.getCurrentTick(); + iter.finishedAt = iter.beginAt + SimpleSSD::PCIExpress::calculateDelay( + pcieGen, pcieLane, iter.size); + + if (iter.buffer) { + memcpy((uint8_t *)iter.addr, iter.buffer, iter.size); + } + + engine.scheduleEvent(dmaWriteEvent, iter.finishedAt); +} + +void Driver::updateInterrupt(uint16_t iv, bool post) { + uint32_t cqdata[4]; + + if (post) { + uint64_t tick = engine.getCurrentTick(); + uint16_t count = 0; + Queue *queue = nullptr; + + if (iv == 0) { + queue = adminCQ; + } + else if (iv == 1 && ioCQ) { + queue = ioCQ; + } + else { + SimpleSSD::panic("I/O Completion Queue is not initialized"); + } + + // Peek queue for count how many requests are finished + while (true) { + queue->peekData((uint8_t *)cqdata, 16); + + // Check phase tag + if (((cqdata[3] >> 16) & 0x01) == phase) { + bool found = false; + + queue->incrTail(); + count++; + + // Search pending command list + for (auto iter = pendingCommandList.begin(); + iter != pendingCommandList.end(); iter++) { + if (iter->iv == iv && iter->cid == (cqdata[3] & 0xFFFF)) { + iter->callback((uint16_t)(cqdata[3] >> 17), cqdata[0], + iter->context); + + pendingCommandList.erase(iter); + found = true; + + break; + } + } + + if (found) { + queue->incrHead(); + + if (queue->getHead() == 0) { + // Inverted + phase = !phase; + } + } + else { + SimpleSSD::panic("Invalid interrupt"); + } + } + else { + if (count > 0) { + pController->ringCQHeadDoorbell(iv, queue->getHead(), tick); + } + + break; + } + } + } +} + +void Driver::getVendorID(uint16_t &vid, uint16_t &ssvid) { + // Copied from SimpleSSD-FullSystem + vid = 0x144D; + ssvid = 0x8086; +} + +} // namespace NVMe + +} // namespace SIL diff --git a/hotness/SimpleSSD-Standalone/sil/nvme/nvme.hh b/hotness/SimpleSSD-Standalone/sil/nvme/nvme.hh new file mode 100644 index 0000000000..4b8189156e --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/nvme/nvme.hh @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NVME__ +#define __DRIVERS_NVME__ + +#include +#include + +#include "bil/interface.hh" +#include "sil/nvme/prp.hh" +#include "sil/nvme/queue.hh" +#include "simplessd/hil/nvme/interface.hh" +#include "simplessd/util/interface.hh" + +#define QUEUE_ENTRY_ADMIN 256 +#define QUEUE_ENTRY_IO 1024 + +namespace SIL { + +namespace NVMe { + +// Copied from SimpleSSD-FullSystem +typedef struct _DMAEntry { + uint64_t beginAt; + uint64_t finishedAt; + uint64_t addr; + uint64_t size; + uint8_t *buffer; + void *context; + SimpleSSD::DMAFunction func; + + _DMAEntry(SimpleSSD::DMAFunction &f) + : beginAt(0), + finishedAt(0), + addr(0), + size(0), + buffer(nullptr), + context(nullptr), + func(f) {} +} DMAEntry; + +typedef std::function ResponseHandler; + +typedef struct _CommandEntry { + uint16_t iv; // Same as Queue ID + uint16_t opcode; + uint16_t cid; + void *context; + + ResponseHandler callback; + + _CommandEntry(uint16_t i, uint16_t o, uint16_t c, void *p, ResponseHandler &f) + : iv(i), opcode(o), cid(c), context(p), callback(f) {} +} CommandEntry; + +typedef struct _IOWrapper { + uint64_t id; + PRP *prp; + std::function bioCallback; + + _IOWrapper(uint64_t i, PRP *p, std::function &f) + : id(i), prp(p), bioCallback(f) {} +} IOWrapper; + +class Driver : public BIL::DriverInterface, SimpleSSD::HIL::NVMe::Interface { + private: + // PCI Express (for DMA throttling) + SimpleSSD::PCIExpress::PCIE_GEN pcieGen; + uint8_t pcieLane; + + // DMA scheduling + SimpleSSD::Event dmaReadEvent; + SimpleSSD::Event dmaWriteEvent; + std::queue dmaReadQueue; + std::queue dmaWriteQueue; + bool dmaReadPending; + bool dmaWritePending; + + // NVMe Identify + uint64_t capacity; + uint32_t LBAsize; + uint32_t namespaceID; + + // Queue + uint16_t maxQueueEntries; + uint16_t adminCommandID; + uint16_t ioCommandID; + bool phase; + Queue *adminSQ; + Queue *adminCQ; + Queue *ioSQ; + Queue *ioCQ; + std::list pendingCommandList; + + void dmaReadDone(); + void submitDMARead(); + void dmaWriteDone(); + void submitDMAWrite(); + + void increaseCommandID(uint16_t &); + + void _init0(uint16_t, void *); + void _init1(uint16_t, void *); + void _init2(uint16_t, void *); + void _init3(uint16_t, uint32_t, void *); + void _init4(uint16_t, void *); + void _init5(uint16_t, void *); + + void _io(uint16_t, void *); + + void submitCommand(uint16_t, uint8_t *, ResponseHandler &, void *); + + public: + Driver(Engine &, SimpleSSD::ConfigReader &); + ~Driver(); + + // BIL::DriverInterface + void init(std::function &) override; + void getInfo(uint64_t &, uint32_t &) override; + void submitIO(BIL::BIO &) override; + + void initStats(std::vector &) override; + void getStats(std::vector &) override; + + // SimpleSSD::DMAInterface + void dmaRead(uint64_t, uint64_t, uint8_t *, SimpleSSD::DMAFunction &, + void * = nullptr) override; + void dmaWrite(uint64_t, uint64_t, uint8_t *, SimpleSSD::DMAFunction &, + void * = nullptr) override; + + // SimpleSSD::HIL::NVMe::Interface + void updateInterrupt(uint16_t, bool) override; + void getVendorID(uint16_t &, uint16_t &) override; +}; + +} // namespace NVMe + +} // namespace SIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/sil/nvme/prp.cc b/hotness/SimpleSSD-Standalone/sil/nvme/prp.cc new file mode 100644 index 0000000000..317ea8e3b4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/nvme/prp.cc @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/nvme/prp.hh" + +#include +#include + +#include "simplessd/sim/trace.hh" +#include "simplessd/util/algorithm.hh" + +namespace SIL { + +namespace NVMe { + +PRP::PRP(uint64_t size) : memory(nullptr), capacity(0), ptr1(0), ptr2(0) { + uint8_t mode = 0; + uint32_t listCount = 1; + uint32_t lastEntryCount = 0; + const uint32_t maxEntryCount = PAGE_SIZE / 8; + + // Calculate size to allocate + if (size <= PAGE_SIZE) { + // PRP1 is PRP pointer, PRP2 is not used + capacity = PAGE_SIZE; + mode = 1; + } + else if (size <= PAGE_SIZE * 2) { + // Both are PRP pointer + capacity = PAGE_SIZE * 2; + mode = 2; + } + else { + // We need to create PRPList + // PRP1 is PRP pointer (always) + mode = 3; + size -= PAGE_SIZE; + capacity = PAGE_SIZE * 2; + + while (true) { + if (size > PAGE_SIZE * maxEntryCount) { + listCount++; + + // Last entry is pointing next PRP list + size -= PAGE_SIZE * (maxEntryCount - 1); + capacity += PAGE_SIZE * maxEntryCount; + } + else { + lastEntryCount = (uint32_t)DIVCEIL(size, PAGE_SIZE); + capacity += PAGE_SIZE * lastEntryCount; + + break; + } + } + } + +#ifdef _MSC_VER + memory = (uint8_t *)_aligned_malloc(capacity, PAGE_SIZE); +#else + memory = (uint8_t *)aligned_alloc(PAGE_SIZE, capacity); +#endif + + if (memory == nullptr) { + SimpleSSD::panic("Failed to allocate memory for PRP region"); + } + + memset(memory, 0, capacity); + + if (mode == 1) { + ptr1 = (uint64_t)memory; + ptrList.push_back(ptr1); + } + else { + ptr1 = (uint64_t)memory; + ptr2 = (uint64_t)(memory + PAGE_SIZE); + ptrList.push_back(ptr1); + ptrList.push_back(ptr2); + + if (mode == 3) { + uint64_t *listPtr = (uint64_t *)ptr2; + uint8_t *page = memory + PAGE_SIZE * 2; + uint32_t entry = 0; + + while (true) { + *(listPtr + entry++) = (uint64_t)page; + ptrList.push_back((uint64_t)page); + page += PAGE_SIZE; + + if (listCount == 1 && entry == lastEntryCount) { + *(listPtr + entry) = 0; + + break; + } + else if (listCount > 1 && entry == maxEntryCount - 1) { + *(listPtr + entry) = (uint64_t)page; + listPtr = (uint64_t *)page; + page += PAGE_SIZE; + listCount--; + entry = 0; + } + } + } + } +} + +PRP::~PRP() { +#ifdef _MSC_VER + _aligned_free(memory); +#else + free(memory); +#endif +} + +void PRP::getPointer(uint64_t &prp1, uint64_t &prp2) { + prp1 = ptr1; + prp2 = ptr2; +} + +void PRP::readData(uint64_t offset, uint64_t size, uint8_t *buffer) { + uint64_t begin = offset / PAGE_SIZE; + uint64_t end = DIVCEIL(offset + size, PAGE_SIZE); + uint64_t copied = 0; + + for (uint64_t i = begin; i < end; i++) { + uint64_t ptr = ptrList[i] + (offset - i * PAGE_SIZE); + uint64_t len = MIN((i + 1) * PAGE_SIZE - offset, size - copied); + + memcpy(buffer, (uint8_t *)ptr, len); + + copied += len; + } +} + +void PRP::writeData(uint64_t offset, uint64_t size, uint8_t *buffer) { + uint64_t begin = offset / PAGE_SIZE; + uint64_t end = DIVCEIL(offset + size, PAGE_SIZE); + uint64_t copied = 0; + + for (uint64_t i = begin; i < end; i++) { + uint64_t ptr = ptrList[i] + (offset - i * PAGE_SIZE); + uint64_t len = MIN((i + 1) * PAGE_SIZE - offset, size - copied); + + memcpy((uint8_t *)ptr, buffer, len); + + copied += len; + } +} + +} // namespace NVMe + +} // namespace SIL diff --git a/hotness/SimpleSSD-Standalone/sil/nvme/prp.hh b/hotness/SimpleSSD-Standalone/sil/nvme/prp.hh new file mode 100644 index 0000000000..ed117e9752 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/nvme/prp.hh @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NVME_PRP__ +#define __DRIVERS_NVME_PRP__ + +#include +#include + +#define PAGE_SIZE 4096 + +namespace SIL { + +namespace NVMe { + +class PRP { + private: + uint8_t *memory; + uint64_t capacity; + + uint64_t ptr1; + uint64_t ptr2; + + std::vector ptrList; // For faster access + + public: + PRP(uint64_t); + ~PRP(); + + void getPointer(uint64_t &, uint64_t &); + void readData(uint64_t, uint64_t, uint8_t *); + void writeData(uint64_t, uint64_t, uint8_t *); +}; + +} // namespace NVMe + +} // namespace SIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/sil/nvme/queue.cc b/hotness/SimpleSSD-Standalone/sil/nvme/queue.cc new file mode 100644 index 0000000000..9ac3f6e75c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/nvme/queue.cc @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sil/nvme/queue.hh" + +#include +#include + +#include "sil/nvme/prp.hh" +#include "simplessd/sim/trace.hh" + +namespace SIL { + +namespace NVMe { + +Queue::Queue(uint16_t e, uint16_t s) + : memory(nullptr), stride(s), entries(e), head(0), tail(0) { + capacity = stride * entries; + +#ifdef _MSC_VER + memory = (uint8_t *)_aligned_malloc(capacity, PAGE_SIZE); +#else + memory = (uint8_t *)aligned_alloc(PAGE_SIZE, capacity); +#endif + + if (memory == nullptr) { + SimpleSSD::panic("Failed to allocate memory for PRP region"); + } + + memset(memory, 0, capacity); +} + +Queue::~Queue() { +#ifdef _MSC_VER + _aligned_free(memory); +#else + free(memory); +#endif +} + +void Queue::getBaseAddress(uint64_t &ptr) { + ptr = (uint64_t)memory; +} + +void Queue::peekData(uint8_t *buffer, uint16_t length) { + memcpy(buffer, memory + head * stride, length); +} + +void Queue::getData(uint8_t *buffer, uint16_t length) { + peekData(buffer, length); + + incrHead(); +} + +void Queue::setData(uint8_t *buffer, uint16_t length) { + memcpy(memory + tail * stride, buffer, length); + + incrTail(); +} + +uint16_t Queue::getHead() { + return head; +} + +uint16_t Queue::getTail() { + return tail; +} + +void Queue::incrHead() { + head++; + + if (head == entries) { + head = 0; + } +} + +void Queue::incrTail() { + tail++; + + if (tail == entries) { + tail = 0; + } +} + +} // namespace NVMe + +} // namespace SIL diff --git a/hotness/SimpleSSD-Standalone/sil/nvme/queue.hh b/hotness/SimpleSSD-Standalone/sil/nvme/queue.hh new file mode 100644 index 0000000000..65019b7ecd --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sil/nvme/queue.hh @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __DRIVERS_NVME_QUEUE__ +#define __DRIVERS_NVME_QUEUE__ + +#include + +namespace SIL { + +namespace NVMe { + +class Queue { + private: + uint8_t *memory; + uint64_t capacity; + + uint16_t stride; + uint16_t entries; + uint16_t head; + uint16_t tail; + + public: + Queue(uint16_t, uint16_t); + ~Queue(); + + void getBaseAddress(uint64_t &); + void getData(uint8_t *, uint16_t); // Increase head + void setData(uint8_t *, uint16_t); // Increase tail + uint16_t getHead(); + uint16_t getTail(); + void incrHead(); + void incrTail(); + void peekData(uint8_t *, uint16_t); // Get data without increasing head +}; + +} // namespace NVMe + +} // namespace SIL + +#endif diff --git a/hotness/SimpleSSD-Standalone/sim/cfg_reader.cc b/hotness/SimpleSSD-Standalone/sim/cfg_reader.cc new file mode 100644 index 0000000000..fb5989edfc --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/cfg_reader.cc @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/cfg_reader.hh" + +#include "simplessd/sim/base_config.hh" +#include "simplessd/sim/trace.hh" + +#ifdef _MSC_VER +#define strcasecmp _stricmp +#else +#include +#endif + +const char SECTION_GLOBAL[] = "global"; +const char SECTION_TRACE[] = "trace"; +const char SECTION_REQ_GEN[] = "generator"; + +bool ConfigReader::init(std::string file) { + if (ini_parse(file.c_str(), parserHandler, this) < 0) { + return false; + } + + // Update all + globalConfig.update(); + traceConfig.update(); + requestConfig.update(); + + return true; +} + +int64_t ConfigReader::readInt(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readInt(idx); + case CONFIG_TRACE: + return traceConfig.readInt(idx); + case CONFIG_REQ_GEN: + return requestConfig.readInt(idx); + default: + return 0; + } +} + +uint64_t ConfigReader::readUint(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readUint(idx); + case CONFIG_TRACE: + return traceConfig.readUint(idx); + case CONFIG_REQ_GEN: + return requestConfig.readUint(idx); + default: + return 0; + } +} + +float ConfigReader::readFloat(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readFloat(idx); + case CONFIG_TRACE: + return traceConfig.readFloat(idx); + case CONFIG_REQ_GEN: + return requestConfig.readFloat(idx); + default: + return 0.f; + } +} + +std::string ConfigReader::readString(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readString(idx); + case CONFIG_TRACE: + return traceConfig.readString(idx); + case CONFIG_REQ_GEN: + return requestConfig.readString(idx); + default: + return std::string(); + } +} + +bool ConfigReader::readBoolean(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_GLOBAL: + return globalConfig.readBoolean(idx); + case CONFIG_TRACE: + return traceConfig.readBoolean(idx); + case CONFIG_REQ_GEN: + return requestConfig.readBoolean(idx); + default: + return false; + } +} + +int ConfigReader::parserHandler(void *context, const char *section, + const char *name, const char *value) { + ConfigReader *pThis = (ConfigReader *)context; + bool handled = false; + + if (MATCH_SECTION(SECTION_GLOBAL)) { + handled = pThis->globalConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_TRACE)) { + handled = pThis->traceConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_REQ_GEN)) { + handled = pThis->requestConfig.setConfig(name, value); + } + + if (!handled) { + SimpleSSD::warn("Config [%s] %s = %s not handled", section, name, value); + } + + return 1; +} diff --git a/hotness/SimpleSSD-Standalone/sim/cfg_reader.hh b/hotness/SimpleSSD-Standalone/sim/cfg_reader.hh new file mode 100644 index 0000000000..800da9d6a1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/cfg_reader.hh @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_CONFIG_READER_2__ +#define __SIM_CONFIG_READER_2__ + +#include +#include + +#include "igl/request/request_config.hh" +#include "igl/trace/trace_config.hh" +#include "sim/global_config.hh" +#include "simplessd/lib/inih/ini.h" + +typedef enum { + CONFIG_GLOBAL, + CONFIG_TRACE, + CONFIG_REQ_GEN, +} CONFIG_SECTION; + +class ConfigReader { + private: + Config globalConfig; + IGL::TraceConfig traceConfig; + IGL::RequestConfig requestConfig; + + static int parserHandler(void *, const char *, const char *, const char *); + + public: + bool init(std::string); + + int64_t readInt(CONFIG_SECTION, uint32_t); + uint64_t readUint(CONFIG_SECTION, uint32_t); + float readFloat(CONFIG_SECTION, uint32_t); + std::string readString(CONFIG_SECTION, uint32_t); + bool readBoolean(CONFIG_SECTION, uint32_t); +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/sim/engine.cc b/hotness/SimpleSSD-Standalone/sim/engine.cc new file mode 100644 index 0000000000..81eeb1b6bb --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/engine.cc @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/engine.hh" + +#include "simplessd/sim/trace.hh" + +Engine::Engine() + : SimpleSSD::Simulator(), + simTick(0), + counter(0), + forceStop(false), + eventHandled(0) { + watch.start(); +} + +Engine::~Engine() {} + +bool Engine::insertEvent(SimpleSSD::Event eid, uint64_t tick, + uint64_t *pOldTick) { + bool found = false; + bool flag = false; + auto old = eventQueue.begin(); + auto insert = eventQueue.end(); + + for (auto iter = eventQueue.begin(); iter != eventQueue.end(); iter++) { + if (iter->first == eid) { + found = true; + old = iter; + + if (pOldTick) { + *pOldTick = iter->second; + } + } + + if (iter->second > tick && !flag) { + insert = iter; + flag = true; + } + } + + if (found && pOldTick) { + if (*pOldTick == tick) { + // Rescheduling to same tick. Ignore. + return false; + } + } + + // Iterator will not invalidated on insert + // Do insert first + eventQueue.insert(insert, {eid, tick}); + + if (found) { + eventQueue.erase(old); + } + + return found; +} + +bool Engine::removeEvent(SimpleSSD::Event eid) { + bool found = false; + + for (auto iter = eventQueue.begin(); iter != eventQueue.end(); iter++) { + if (iter->first == eid) { + eventQueue.erase(iter); + found = true; + + break; + } + } + + return found; +} + +bool Engine::isEventExist(SimpleSSD::Event eid, uint64_t *pTick) { + for (auto &iter : eventQueue) { + if (iter.first == eid) { + if (pTick) { + *pTick = iter.second; + } + + return true; + } + } + + return false; +} + +uint64_t Engine::getCurrentTick() { + std::lock_guard guard(mTick); + + return simTick; +} + +SimpleSSD::Event Engine::allocateEvent(SimpleSSD::EventFunction func) { + auto iter = eventList.insert({++counter, func}); + + if (!iter.second) { + SimpleSSD::panic("Fail to allocate event"); + } + + return counter; +} + +void Engine::scheduleEvent(SimpleSSD::Event eid, uint64_t tick) { + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + uint64_t tickCopy; + + { + std::lock_guard guard(mTick); + tickCopy = simTick; + } + + if (tick < tickCopy) { + SimpleSSD::warn("Tried to schedule %" PRIu64 + " < simTick to event %" PRIu64 ". Set tick as simTick.", + tick, eid); + + tick = tickCopy; + } + + uint64_t oldTick; + + if (insertEvent(eid, tick, &oldTick)) { + SimpleSSD::warn("Event %" PRIu64 " rescheduled from %" PRIu64 + " to %" PRIu64, + eid, oldTick, tick); + } + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } +} + +void Engine::descheduleEvent(SimpleSSD::Event eid) { + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + removeEvent(eid); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } +} + +bool Engine::isScheduled(SimpleSSD::Event eid, uint64_t *pTick) { + bool ret = false; + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + ret = isEventExist(eid, pTick); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } + + return ret; +} + +void Engine::deallocateEvent(SimpleSSD::Event eid) { + auto iter = eventList.find(eid); + + if (iter != eventList.end()) { + removeEvent(eid); + eventList.erase(iter); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", eid); + } +} + +bool Engine::doNextEvent() { + uint64_t tickCopy; + + if (forceStop) { + return false; + } + + if (eventQueue.size() > 0) { + auto &now = eventQueue.front(); + + { + std::lock_guard guard(mTick); + + simTick = now.second; + tickCopy = simTick; + } + + auto iter = eventList.find(now.first); + + eventQueue.pop_front(); + + if (iter != eventList.end()) { + iter->second(tickCopy); + } + else { + SimpleSSD::panic("Event %" PRIu64 " does not exists", now.first); + } + + { + std::lock_guard guard(m); + eventHandled++; + } + + return true; + } + + return false; +} + +void Engine::stopEngine() { + forceStop = true; +} + +void Engine::printStats(std::ostream &out) { + watch.stop(); + + double duration = watch.getDuration(); + + out << "*** Statistics of Event Engine ***" << std::endl; + { + std::lock_guard guard(mTick); + + out << "Simulation Tick (ps): " << simTick << std::endl; + } + out << "Host time duration (sec): " << std::to_string(duration) << std::endl; + out << "Event handled: " << eventHandled << " (" + << std::to_string(eventHandled / duration) << " ops)" << std::endl; + out << "*** End of statistics ***" << std::endl; +} + +void Engine::getStat(uint64_t &val) { + std::lock_guard guard(m); + val = eventHandled; +} diff --git a/hotness/SimpleSSD-Standalone/sim/engine.hh b/hotness/SimpleSSD-Standalone/sim/engine.hh new file mode 100644 index 0000000000..2b292f962d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/engine.hh @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_ENGINE__ +#define __SIM_ENGINE__ + +#include +#include +#include +#include +#include + +#include "simplessd/sim/simulator.hh" +#include "util/stopwatch.hh" + +class Engine : public SimpleSSD::Simulator { + private: + std::mutex mTick; + uint64_t simTick; + SimpleSSD::Event counter; + bool forceStop; + std::unordered_map eventList; + std::list> eventQueue; + + Stopwatch watch; + + std::mutex m; + uint64_t eventHandled; + + bool insertEvent(SimpleSSD::Event, uint64_t, uint64_t * = nullptr); + bool removeEvent(SimpleSSD::Event); + bool isEventExist(SimpleSSD::Event, uint64_t * = nullptr); + + public: + Engine(); + ~Engine(); + + uint64_t getCurrentTick() override; + + SimpleSSD::Event allocateEvent(SimpleSSD::EventFunction) override; + void scheduleEvent(SimpleSSD::Event, uint64_t) override; + void descheduleEvent(SimpleSSD::Event) override; + bool isScheduled(SimpleSSD::Event, uint64_t * = nullptr) override; + void deallocateEvent(SimpleSSD::Event) override; + + bool doNextEvent(); + void stopEngine(); + void printStats(std::ostream &); + void getStat(uint64_t &); +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/sim/global_config.cc b/hotness/SimpleSSD-Standalone/sim/global_config.cc new file mode 100644 index 0000000000..af3ac5143b --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/global_config.cc @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/global_config.hh" + +#include "simplessd/sim/trace.hh" +#include "util/convert.hh" + +const char NAME_MODE[] = "Mode"; +const char NAME_LOG_PERIOD[] = "LogPeriod"; +const char NAME_LOG_FILE[] = "LogFile"; +const char NAME_DEBUG_LOG_FILE[] = "DebugLogFile"; +const char NAME_LATENCY_LOG_FILE[] = "LatencyLogFile"; +const char NAME_PROGRESS_PERIOD[] = "ProgressPeriod"; +const char NAME_INTERFACE[] = "Interface"; +const char NAME_SCHEDULER[] = "Scheduler"; +const char NAME_SUBMISSION_LATENCY[] = "SubmissionLatency"; +const char NAME_COMPLETION_LATENCY[] = "CompletionLatency"; + +Config::Config() { + mode = MODE_REQUEST_GENERATOR; + logPeriod = 0; + progressPeriod = 0; + interface = INTERFACE_NVME; + scheduler = SCHEDULER_NOOP; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_MODE)) { + mode = (SIM_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LOG_PERIOD)) { + logPeriod = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LOG_FILE)) { + logFile = value; + } + else if (MATCH_NAME(NAME_DEBUG_LOG_FILE)) { + logDebugFile = value; + } + else if (MATCH_NAME(NAME_LATENCY_LOG_FILE)) { + latencyFile = value; + } + else if (MATCH_NAME(NAME_PROGRESS_PERIOD)) { + progressPeriod = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_INTERFACE)) { + interface = (INTERFACE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SCHEDULER)) { + scheduler = (SCHEDULER)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SUBMISSION_LATENCY)) { + submissionLatency = convertTime(value); + } + else if (MATCH_NAME(NAME_COMPLETION_LATENCY)) { + completionLatency = convertTime(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (mode >= MODE_NUM) { + SimpleSSD::panic("Invalid simulation mode"); + } + if (interface >= INTERFACE_NUM) { + SimpleSSD::panic("Invalid interface"); + } +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case GLOBAL_SIM_MODE: + ret = mode; + break; + case GLOBAL_LOG_PERIOD: + ret = logPeriod; + break; + case GLOBAL_PROGRESS_PERIOD: + ret = progressPeriod; + break; + case GLOBAL_INTERFACE: + ret = interface; + break; + case GLOBAL_SCHEDULER: + ret = scheduler; + break; + case GLOBAL_SUBMISSION_LATENCY: + ret = submissionLatency; + break; + case GLOBAL_COMPLETION_LATENCY: + ret = completionLatency; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret = ""; + + switch (idx) { + case GLOBAL_LOG_FILE: + ret = logFile; + break; + case GLOBAL_DEBUG_LOG_FILE: + ret = logDebugFile; + break; + case GLOBAL_LATENCY_LOG_FILE: + ret = latencyFile; + break; + } + + return ret; +} diff --git a/hotness/SimpleSSD-Standalone/sim/global_config.hh b/hotness/SimpleSSD-Standalone/sim/global_config.hh new file mode 100644 index 0000000000..8ed433cab6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/global_config.hh @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_GLOBAL_CONFIG__ +#define __SIM_GLOBAL_CONFIG__ + +#include "simplessd/sim/base_config.hh" + +typedef enum { + GLOBAL_SIM_MODE, + GLOBAL_LOG_PERIOD, + GLOBAL_LOG_FILE, + GLOBAL_DEBUG_LOG_FILE, + GLOBAL_LATENCY_LOG_FILE, + GLOBAL_PROGRESS_PERIOD, + GLOBAL_INTERFACE, + GLOBAL_SCHEDULER, + GLOBAL_SUBMISSION_LATENCY, + GLOBAL_COMPLETION_LATENCY, +} GLOBAL_CONFIG; + +typedef enum { + MODE_REQUEST_GENERATOR, + MODE_TRACE_REPLAYER, + MODE_NUM, +} SIM_MODE; + +typedef enum { + INTERFACE_NONE, + INTERFACE_NVME, + INTERFACE_SATA, + INTERFACE_UFS, + INTERFACE_NUM, +} INTERFACE; + +typedef enum { + SCHEDULER_NOOP, + SCHEDULER_NUM, +} SCHEDULER; + +class Config : public SimpleSSD::BaseConfig { + private: + SIM_MODE mode; + uint64_t logPeriod; + std::string logFile; + std::string logDebugFile; + std::string latencyFile; + uint64_t progressPeriod; + INTERFACE interface; + SCHEDULER scheduler; + uint64_t submissionLatency; + uint64_t completionLatency; + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/sim/main.cc b/hotness/SimpleSSD-Standalone/sim/main.cc new file mode 100644 index 0000000000..01156fee43 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/main.cc @@ -0,0 +1,384 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include +#include +#include + +#include "icl/generic_cache.hh" +#include "bil/entry.hh" +#include "igl/request/request_generator.hh" +#include "igl/trace/trace_replayer.hh" +#include "sil/none/none.hh" +#include "sil/nvme/nvme.hh" +#include "sim/engine.hh" +#include "sim/signal.hh" +#include "simplessd/util/simplessd.hh" +#include "util/print.hh" + +// Global objects +Engine engine; +ConfigReader simConfig; +BIL::DriverInterface *pInterface = nullptr; +BIL::BlockIOEntry *pBIOEntry = nullptr; +IGL::IOGenerator *pIOGen = nullptr; +std::ostream *pLog = nullptr; +std::ostream *pDebugLog = nullptr; +std::ostream *pLatencyFile = nullptr; +std::thread *pThread = nullptr; +std::mutex killLock; +SimpleSSD::Event statEvent; +std::vector statList; +std::ofstream logOut; +std::ofstream debugLogOut; +std::ofstream latencyFile; + + +// Declaration +void cleanup(int); +void statistics(uint64_t); +void threadFunc(int); + +void joinPath(std::string &lhs, std::string &rhs) { + if (rhs.front() == '/') { + // Assume absolute path + lhs = rhs; + } + else if (lhs.back() == '/') { + lhs += rhs; + } + else { + lhs += '/'; + lhs += rhs; + } +} + +int main(int argc, char *argv[]) { + std::cout << "SimpleSSD Standalone v2.0" << std::endl; + + // Check argument + if (argc != 4) { + std::cerr << " Invalid number of argument!" << std::endl; + std::cerr << " Usage: simplessd-standalone " + << std::endl; + + return 1; + } + + // sim/main.cc, main() 함수 안에서 engine/simConfig/statEvent 정의된 '아래' 위치에 둬야 합니다. + std::function endCallback = []() { + // 주기 통계 이벤트가 켜져 있으면 해제 + if (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) > 0) { + engine.descheduleEvent(statEvent); + } + + // 1) 캐시 엔드-플러시 + uint64_t t = engine.getCurrentTick(); + if (auto* gcache = SimpleSSD::ICL::getLastGenericCache()) { + gcache->flushAll(t); + } + + // 2) stop을 미래 tick에 '이벤트'로 예약 (콜백 내에서 drain/re-enter 금지) + SimpleSSD::Event stopEv = engine.allocateEvent([](uint64_t) { + engine.stopEngine(); + }); + engine.scheduleEvent(stopEv, t + 1000000000ULL); // +1s (ps 단위면 1e12로) + }; + + + // Install signal handler + installSignalHandler(cleanup); + + // Read simulation config file + if (!simConfig.init(argv[1])) { + std::cerr << " Failed to open simulation configuration file!" << std::endl; + + return 2; + } + + // Log setting + bool noLogPrintOnScreen = true; + + std::string logPath = simConfig.readString(CONFIG_GLOBAL, GLOBAL_LOG_FILE); + std::string debugLogPath = + simConfig.readString(CONFIG_GLOBAL, GLOBAL_DEBUG_LOG_FILE); + std::string latencyLogPath = + simConfig.readString(CONFIG_GLOBAL, GLOBAL_LATENCY_LOG_FILE); + + if (logPath.compare("STDOUT") == 0) { + noLogPrintOnScreen = false; + pLog = &std::cout; + } + else if (logPath.compare("STDERR") == 0) { + noLogPrintOnScreen = false; + pLog = &std::cerr; + } + else if (logPath.length() != 0) { + std::string full(argv[3]); + + joinPath(full, logPath); + logOut.open(full); + + if (!logOut.is_open()) { + std::cerr << " Failed to open log file: " << full << std::endl; + + return 3; + } + + pLog = &logOut; + } + + if (debugLogPath.compare("STDOUT") == 0) { + noLogPrintOnScreen = false; + pDebugLog = &std::cout; + } + else if (debugLogPath.compare("STDERR") == 0) { + noLogPrintOnScreen = false; + pDebugLog = &std::cerr; + } + else if (debugLogPath.length() != 0) { + std::string full(argv[3]); + + joinPath(full, debugLogPath); + debugLogOut.open(full); + + if (!debugLogOut.is_open()) { + std::cerr << " Failed to open log file: " << full << std::endl; + + return 3; + } + + pDebugLog = &debugLogOut; + } + + if (latencyLogPath.length() != 0) { + std::string full(argv[3]); + + joinPath(full, latencyLogPath); + latencyFile.open(full); + + if (!latencyFile.is_open()) { + std::cerr << " Failed to open log file: " << full << std::endl; + + return 3; + } + + pLatencyFile = &latencyFile; + } + + // Initialize SimpleSSD + auto ssdConfig = initSimpleSSDEngine(&engine, pDebugLog, pDebugLog, argv[2]); + + // Create Driver + switch (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_INTERFACE)) { + case INTERFACE_NONE: + pInterface = new SIL::None::Driver(engine, ssdConfig); + + break; + case INTERFACE_NVME: + pInterface = new SIL::NVMe::Driver(engine, ssdConfig); + + break; + default: + std::cerr << " Undefined interface specified." << std::endl; + + return 4; + } + + // Create Block I/O Layer + pBIOEntry = + new BIL::BlockIOEntry(simConfig, engine, pInterface, pLatencyFile); + + // Create I/O generator + switch (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_SIM_MODE)) { + case MODE_REQUEST_GENERATOR: + pIOGen = + new IGL::RequestGenerator(engine, *pBIOEntry, endCallback, simConfig); + + break; + case MODE_TRACE_REPLAYER: + pIOGen = + new IGL::TraceReplayer(engine, *pBIOEntry, endCallback, simConfig); + + break; + default: + std::cerr << " Undefined simulation mode specified." << std::endl; + + cleanup(0); + + return 5; + } + + std::function beginCallback = []() { + uint64_t bytesize; + uint32_t bs; + + pInterface->getInfo(bytesize, bs); + pIOGen->init(bytesize, bs); + pIOGen->begin(); + }; + + // Insert stat event + pInterface->initStats(statList); + + if (simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) > 0) { + statEvent = engine.allocateEvent([](uint64_t tick) { + statistics(tick); + + engine.scheduleEvent( + statEvent, + tick + simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) * + 1000000000ULL); + }); + engine.scheduleEvent( + statEvent, + simConfig.readUint(CONFIG_GLOBAL, GLOBAL_LOG_PERIOD) * 1000000000ULL); + } + + // Do Simulation + std::cout << "********** Begin of simulation **********" << std::endl; + + pInterface->init(beginCallback); + + if (noLogPrintOnScreen) { + int period = (int)simConfig.readUint(CONFIG_GLOBAL, GLOBAL_PROGRESS_PERIOD); + + if (period > 0) { + pThread = new std::thread(threadFunc, period); + } + } + + while (engine.doNextEvent()) + ; + + cleanup(0); + + return 0; +} + +void cleanup(int) { + uint64_t tick; + + killLock.lock(); + + tick = engine.getCurrentTick(); + + if (tick == 0) { + // Exit program + exit(0); + } + + // Print last statistics + statistics(tick); + + // Erase progress + printf("\33[2K \r"); + + releaseSimpleSSDEngine(); + + pIOGen->printStats(std::cout); + engine.printStats(std::cout); + + // Cleanup all here + delete pInterface; + delete pIOGen; + + if (pThread) { + pThread->join(); + + delete pThread; + } + + delete pBIOEntry; // Used by progress thread + + if (logOut.is_open()) { + logOut.close(); + } + if (debugLogOut.is_open()) { + debugLogOut.close(); + } + + std::cout << "End of simulation @ tick " << tick << std::endl; + + // Exit program + exit(0); +} + +void statistics(uint64_t tick) { + if (pLog == nullptr) { + return; + } + + std::ostream &out = *pLog; + std::vector stat; + uint64_t count = 0; + + pInterface->getStats(stat); + + count = statList.size(); + + if (count != stat.size()) { + std::cerr << " Stat list length mismatch" << std::endl; + + std::terminate(); + } + + out << "Periodic log printout @ tick " << tick << std::endl; + + for (uint64_t i = 0; i < count; i++) { + print(out, statList[i].name, 40); + out << "\t"; + print(out, stat[i], 20); + out << "\t" << statList[i].desc << std::endl; + } + + out << "End of log @ tick " << tick << std::endl; +} + +void threadFunc(int tick) { + uint64_t current; + uint64_t old = 0; + float progress; + auto duration = std::chrono::seconds(tick); + BIL::Progress data; + + while (true) { + std::this_thread::sleep_for(duration); + + if (killLock.try_lock()) { + killLock.unlock(); + } + else { + break; + } + + engine.getStat(current); + pIOGen->getProgress(progress); + pBIOEntry->getProgress(data); + + printf("\33[2K*** Progress: %.2f%% (%lf ops) IOPS: %" PRIu64 " BW: %" PRIu64 + " B/s Avg. Lat: %" PRIu64 " ps\r", + progress * 100.f, (double)(current - old) / tick, data.iops, + data.bandwidth, data.latency); + fflush(stdout); + + old = current; + } +} diff --git a/hotness/SimpleSSD-Standalone/sim/signal.cc b/hotness/SimpleSSD-Standalone/sim/signal.cc new file mode 100644 index 0000000000..4c3542e2e8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/signal.cc @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +/* + * This file contains some codes from original gem5 project. + * See src/sim/backtrace_glib.cc and src/sim/init_signals.cc of gem5. + * Followings are copyright from gem5. + */ + +/* + * Copyright (c) 2015 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2000-2005 The Regents of The University of Michigan + * Copyright (c) 2008 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg, Nathan Binkert + */ + +#include "sim/signal.hh" + +#include +#include +#include +#include + +#include + +#ifdef _MSC_VER + +#pragma comment(lib, "dbghelp.lib") + +#include +// Windows.h should be included before DbgHelp.h +#include + +#ifndef _M_X64 +#error "Only x86_64 (AMD64) is supported." +#endif + +void (*closeHandler)(int) = nullptr; + +void print_backtrace(); + +BOOL consoleHandler(DWORD type) { + if (closeHandler) { + closeHandler(0); + } + + return TRUE; +} + +LONG WINAPI exceptionHandler(LPEXCEPTION_POINTERS pExceptionInfo) { + switch (pExceptionInfo->ExceptionRecord->ExceptionCode) { + case EXCEPTION_ACCESS_VIOLATION: + case EXCEPTION_IN_PAGE_ERROR: + std::cerr << "Program has encountered a segmentation fault." << std::endl; + break; + case EXCEPTION_INT_OVERFLOW: + case EXCEPTION_INT_DIVIDE_BY_ZERO: + std::cerr << "Program has encountered a floating point exception." + << std::endl; + break; + default: + std::cerr << "Program aborted." << std::endl; + } + + print_backtrace(); + + return EXCEPTION_EXECUTE_HANDLER; +} + +#else + +#include +#include + +#define FRAMECOUNT 32 + +static uint8_t stack[SIGSTKSZ * 2]; + +void print_backtrace(); + +static bool setupStack() { + stack_t st; + + st.ss_sp = stack; + st.ss_size = sizeof(stack); + st.ss_flags = 0; + + return sigaltstack(&st, nullptr) == 0; +} + +static void raiseSignal(int sig) { + pthread_kill(pthread_self(), sig); + + exit(0); +} + +static void installHandler(int sig, void (*handler)(int), + int flags = SA_RESTART) { + struct sigaction sa; + + memset(&sa, 0, sizeof(sa)); + sigemptyset(&sa.sa_mask); + sa.sa_handler = handler; + sa.sa_flags = flags; + + sigaction(sig, &sa, nullptr); +} + +void abortHandler(int sig) { + std::cerr << "Program aborted." << std::endl; + + print_backtrace(); + raiseSignal(sig); +} + +void segfaultHandler(int sig) { + std::cerr << "Program has encountered a segmentation fault." << std::endl; + + print_backtrace(); + raiseSignal(sig); +} + +void fpeHandler(int sig) { + std::cerr << "Program has encountered a floating point exception." + << std::endl; + + print_backtrace(); + raiseSignal(sig); +} + +#endif + +void print_backtrace() { + std::cerr << "--- BEGIN LIBC BACKTRACE ---" << std::endl; + +#ifdef _MSC_VER + CONTEXT context; + STACKFRAME64 frame; + DWORD type; + HANDLE hProcess = GetCurrentProcess(); + HANDLE hThread = GetCurrentThread(); + char buffer[sizeof(SYMBOL_INFO) + MAX_SYM_NAME * sizeof(char)]; + PSYMBOL_INFO symInfo = (PSYMBOL_INFO)buffer; + IMAGEHLP_MODULE modInfo; + DWORD64 displacement; + + RtlCaptureContext(&context); + + memset(&frame, 0, sizeof(STACKFRAME64)); + type = IMAGE_FILE_MACHINE_AMD64; + frame.AddrPC.Offset = context.Rip; + frame.AddrPC.Mode = AddrModeFlat; + frame.AddrFrame.Offset = context.Rsp; + frame.AddrFrame.Mode = AddrModeFlat; + frame.AddrStack.Offset = context.Rsp; + frame.AddrStack.Mode = AddrModeFlat; + + symInfo->SizeOfStruct = sizeof(SYMBOL_INFO); + symInfo->MaxNameLen = MAX_SYM_NAME; + modInfo.SizeOfStruct = sizeof(IMAGEHLP_MODULE); + + if (!SymInitialize(hProcess, nullptr, true)) { + std::cerr << "Failed to initialize symbol table." << std::endl; + std::cerr << "--- END LIBC BACKTRACE ---" << std::endl; + + return; + } + + while (true) { + if (!StackWalk64(type, hProcess, hThread, &frame, &context, nullptr, + SymFunctionTableAccess64, SymGetModuleBase64, nullptr)) { + break; + } + + if (frame.AddrPC.Offset != 0) { + // Get Module Name + if (SymGetModuleInfo(hProcess, frame.AddrPC.Offset, &modInfo)) { + std::cerr << modInfo.ModuleName; + } + else { + std::cerr << ""; + } + + // Get Symbole Name + if (SymFromAddr(hProcess, frame.AddrPC.Offset, &displacement, symInfo)) { + std::cerr << "(" << symInfo->Name << "+0x" << std::hex << displacement + << ")"; + } + + std::cerr << "[0x" << std::hex << frame.AddrPC.Offset << "]" << std::endl; + } + else { + break; + } + } + + SymCleanup(hProcess); + CloseHandle(hThread); + CloseHandle(hProcess); +#else + void *buffer[FRAMECOUNT]; + int size; + + size = backtrace(buffer, sizeof(buffer) / sizeof(*buffer)); + + backtrace_symbols_fd(buffer, size, STDERR_FILENO); + + if (size == sizeof(buffer)) + std::cerr << "Warning: Backtrace may have been truncated." << std::endl; +#endif + + std::cerr << "--- END LIBC BACKTRACE ---" << std::endl; +} + +void installSignalHandler(void (*handler)(int)) { +#ifdef _MSC_VER + closeHandler = handler; + SetConsoleCtrlHandler((PHANDLER_ROUTINE)consoleHandler, TRUE); + SetUnhandledExceptionFilter(exceptionHandler); +#else + installHandler(SIGINT, handler); + installHandler(SIGABRT, abortHandler, SA_RESETHAND | SA_NODEFER); + + setupStack(); + + installHandler(SIGSEGV, segfaultHandler, + SA_RESETHAND | SA_NODEFER | SA_ONSTACK); + installHandler(SIGFPE, fpeHandler, SA_RESETHAND | SA_NODEFER | SA_ONSTACK); +#endif +} diff --git a/hotness/SimpleSSD-Standalone/sim/signal.hh b/hotness/SimpleSSD-Standalone/sim/signal.hh new file mode 100644 index 0000000000..edbbc464f9 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/sim/signal.hh @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_SIGNAL__ +#define __SIM_SIGNAL__ + +void installSignalHandler(void (*)(int)); + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/.clang-format b/hotness/SimpleSSD-Standalone/simplessd/.clang-format new file mode 100644 index 0000000000..f47274946a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/.clang-format @@ -0,0 +1,29 @@ +# Generated by clang-format v6.0.0 +--- +Language: Cpp +BasedOnStyle: Google +AlignEscapedNewlines: Right +AllowShortFunctionsOnASingleLine: Inline +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakBeforeMultilineStrings: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: true + BeforeElse: true + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBraces: Custom +DerivePointerAlignment: false +PointerAlignment: Right +... diff --git a/hotness/SimpleSSD-Standalone/simplessd/.gitignore b/hotness/SimpleSSD-Standalone/simplessd/.gitignore new file mode 100644 index 0000000000..f3fa772012 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/.gitignore @@ -0,0 +1,11 @@ +.DS_Store +*/.DS_Store +build/ +CMakeFiles/ +CMakeCache.txt +cmake_install.cmake +Makefile +*.o +*.a +*.so +*.dylib diff --git a/hotness/SimpleSSD-Standalone/simplessd/.gitmodules b/hotness/SimpleSSD-Standalone/simplessd/.gitmodules new file mode 100644 index 0000000000..eeab98a564 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/.gitmodules @@ -0,0 +1,3 @@ +[submodule "lib/mcpat"] + path = lib/mcpat + url = https://github.com/SimpleSSD/mcpat.git diff --git a/hotness/SimpleSSD-Standalone/simplessd/CMakeLists.txt b/hotness/SimpleSSD-Standalone/simplessd/CMakeLists.txt new file mode 100644 index 0000000000..66ecd892af --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/CMakeLists.txt @@ -0,0 +1,199 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# Set version and project name +cmake_minimum_required(VERSION 3.10) +project(simplessd) + +# Add options for debug build +option(DEBUG_BUILD "Build SimpleSSD in debug mode." OFF) + +# Set output directory +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) + +# Set cache entry for external library include path +set(DRAMPOWER_SOURCE_DIR "." CACHE PATH "Source directory to DRAMPower library") + +# Check DRAMPOWER_SOURCE_DIR is valid +if (NOT EXISTS "${DRAMPOWER_SOURCE_DIR}/libdrampower/LibDRAMPower.h") + message(FATAL_ERROR "Failed to find DRAMPower library. \ +Check you specified DRAMPower path by -DDRAMPOWER_SOURCE_DIR.") +endif () + +# Check mcpat is valid +if (NOT EXISTS "${PROJECT_SOURCE_DIR}/lib/mcpat/mcpat.h") + message(FATAL_ERROR "Failed to find McPAT library. \ +Check you initialized submodules.") +endif () + +# Add subproject +add_subdirectory(${PROJECT_SOURCE_DIR}/lib/mcpat) + +# Set include directories +include_directories( + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/lib/mcpat + ${PROJECT_SOURCE_DIR}/lib/mcpat/cacti + ${PROJECT_SOURCE_DIR}/lib/inih + ${DRAMPOWER_SOURCE_DIR} +) + +# Platform specific settings +if (MSVC) + add_definitions(-D_CRT_SECURE_NO_WARNINGS) + add_compile_options(/wd4819) # Surpress unicode warning + add_compile_options(/wd4244) # Surpress conversion warning + add_compile_options(/wd4267) # Surpress conversion warning + add_compile_options(/wd4305) # Surpress truncation warning + add_compile_options(/wd4800) # Surpress int -> boolean waring +else () + set(CMAKE_CXX_FLAGS "-g -Wall -Wextra -Werror ${CMAKE_CXX_FLAGS}") + + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS "-O0 ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS "-O2 ${CMAKE_CXX_FLAGS}") + endif () + + if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS "6.0") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-strict-aliasing") + endif () + endif () +endif () + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Specify source files +set(SRC_CPU + cpu/config.cc + cpu/cpu.cc +) +set(SRC_DRAM + dram/abstract_dram.cc + dram/config.cc + dram/simple.cc +) +set(SRC_FTL_COMMON + ftl/common/block.cc +) +set(SRC_FTL + ftl/config.cc + ftl/ftl.cc + ftl/page_mapping.cc + ftl/page_mapping_hotness.cc +) +set(SRC_HIL_NVME + hil/nvme/abstract_subsystem.cc + hil/nvme/config.cc + hil/nvme/controller.cc + hil/nvme/dma.cc + hil/nvme/namespace.cc + hil/nvme/ocssd.cc + hil/nvme/queue.cc + hil/nvme/subsystem.cc +) +set(SRC_HIL_SATA + hil/sata/config.cc + hil/sata/device.cc + hil/sata/hba.cc +) +set(SRC_HIL_UFS + hil/ufs/config.cc + hil/ufs/def.cc + hil/ufs/device.cc + hil/ufs/host.cc +) +set(SRC_HIL + hil/hil.cc +) +set(SRC_ICL + icl/abstract_cache.cc + icl/config.cc + icl/generic_cache.cc + icl/icl.cc +) +set(SRC_LIB_INIH + lib/inih/ini.c +) +set(SRC_PAL_OLD + pal/old/Latency.cc + pal/old/LatencyMLC.cc + pal/old/LatencySLC.cc + pal/old/LatencyTLC.cc + pal/old/PAL2.cc + pal/old/PAL2_TimeSlot.cc + pal/old/PALStatistics.cc +) +set(SRC_PAL + pal/config.cc + pal/pal.cc + pal/pal_old.cc +) +set(SRC_SIM + sim/config_reader.cc + sim/cpu.cc + sim/log.cc + sim/simulator.cc + sim/state.cc +) +set(SRC_UTIL + util/bitset.cc + util/def.cc + util/disk.cc + util/fifo.cc + util/interface.cc + util/simplessd.cc +) + +# Source group for MSVC +SOURCE_GROUP("Source Files\\cpu" FILES ${SRC_CPU}) +SOURCE_GROUP("Source Files\\dram" FILES ${SRC_DRAM}) +SOURCE_GROUP("Source Files\\ftl" FILES ${SRC_FTL}) +SOURCE_GROUP("Source Files\\ftl\\common" FILES ${SRC_FTL_COMMON}) +SOURCE_GROUP("Source Files\\hil" FILES ${SRC_HIL}) +SOURCE_GROUP("Source Files\\hil\\nvme" FILES ${SRC_HIL_NVME}) +SOURCE_GROUP("Source Files\\hil\\sata" FILES ${SRC_HIL_SATA}) +SOURCE_GROUP("Source Files\\hil\\ufs" FILES ${SRC_HIL_UFS}) +SOURCE_GROUP("Source Files\\icl" FILES ${SRC_ICL}) +SOURCE_GROUP("Source Files\\lib\\inih" FILES ${SRC_LIB_INIH}) +SOURCE_GROUP("Source Files\\pal" FILES ${SRC_PAL}) +SOURCE_GROUP("Source Files\\pal\\old" FILES ${SRC_PAL_OLD}) +SOURCE_GROUP("Source Files\\sim" FILES ${SRC_SIM}) +SOURCE_GROUP("Source Files\\util" FILES ${SRC_UTIL}) + +# Define library +add_library(simplessd STATIC + ${SRC_CPU} + ${SRC_DRAM} + ${SRC_FTL} + ${SRC_FTL_COMMON} + ${SRC_HIL} + ${SRC_HIL_NVME} + ${SRC_HIL_SATA} + ${SRC_HIL_UFS} + ${SRC_ICL} + ${SRC_LIB_INIH} + ${SRC_PAL} + ${SRC_PAL_OLD} + ${SRC_SIM} + ${SRC_UTIL} +) +target_link_libraries(simplessd mcpat) diff --git a/hotness/SimpleSSD-Standalone/simplessd/CODINGSTYLE.md b/hotness/SimpleSSD-Standalone/simplessd/CODINGSTYLE.md new file mode 100644 index 0000000000..f1f85d0418 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/CODINGSTYLE.md @@ -0,0 +1,17 @@ +# Coding Style +## File +### File Extension +- C++: Use `*.cc` for source files and `*.hh` for header files. +- C: Use `*.c` for source files and `*.h` for header files. + +### File name +Use `snake_case` for filenames. Use only lower-case characters. + +## Language +### C/C++ +User defined type uses `CamelCase`. Typename should begin with upper-case characters. +Variable/function name uses `camelCase`. Variable/function name should begin with lower-case characters. + +### Formatting using `clang-format` +Use C/C++ code formatter `clang-format` version >= 6.0. +See .clang-format file for style definition. diff --git a/hotness/SimpleSSD-Standalone/simplessd/LICENSE b/hotness/SimpleSSD-Standalone/simplessd/LICENSE new file mode 100644 index 0000000000..8ca04e5e57 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. 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Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + SimpleSSD + Copyright (C) 2017 SimpleSSD + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + SimpleSSD Copyright (C) 2017 SimpleSSD + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/hotness/SimpleSSD-Standalone/simplessd/README.md b/hotness/SimpleSSD-Standalone/simplessd/README.md new file mode 100644 index 0000000000..e92d0cfd59 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/README.md @@ -0,0 +1,15 @@ +# SimpleSSD version 2.0 +Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations + +This project is managed by [CAMELab](http://camelab.org). +For more information, please visit [SimpleSSD homepage](http://simplessd.org). + +## Licenses +SimpleSSD is released under the GPLv3 license. See `LICENSE` file for details. +SimpleSSD uses open-source libraries. + + - [inih](https://github.com/benhoyt/inih) located at `/lib/inih` +INI parser library released under the New BSD license. + - [McPAT](https://github.com/HewlettPackard/mcpat) located at `/lib/mcpat` +Multicore Power Area and Timing calculator. +We modified source code to separate initialize phase and calculation phase. diff --git a/hotness/SimpleSSD-Standalone/simplessd/config/sample.cfg b/hotness/SimpleSSD-Standalone/simplessd/config/sample.cfg new file mode 100644 index 0000000000..4f52b49adf --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/config/sample.cfg @@ -0,0 +1,493 @@ +# +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . +# + +# +# Sample SimpleSSD Configuration File +# +# Section: +# cpu: SSD Controller CPU configuration +# nvme: Non-Volatile Memory Express configuration +# ufs: Universal Flash Storage configuration +# sata: Serial ATA configuration +# pal: Parallelism Abstraction Layer configuration +# ftl: Flash Translation Layer configuration +# icl: Internal Cache Layer configuration +# dram: DRAM configuration +# + +# SSD Controller CPU configuration +[cpu] +## Set clock speed in Hz +ClockSpeed = 400000000 + +## Set dedicated core count +HILCoreCount = 1 +ICLCoreCount = 1 +FTLCoreCount = 1 + +# NVMe interface Configuration +[nvme] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NVMe Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## Hardware FIFO Transfer unit +# Smaller value introduce smaller latency +FIFOTransferUnit = 2048 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## Set maximum number of I/O queue that controller supports +# You should check BAR0 size to fit all doorbell +# Doorbell stride is always 0 (4bytes align) +MaxIOCQueue = 16 +MaxIOSQueue = 16 + +## Set parameters of Weighted Round robin +# Set how many commands should be inserted to internal FIFO +# before switch to next low priority +WRRHigh = 2 # Medium-priority command will inserted after two high-priority commands inserted +WRRMedium = 2 # Low-priority command will inserted after two medium-priority command inserted + +## Default Namespace +# Specify number of namespaces to create +# Each namespace has same capacity +DefaultNamespace = 1 + +## LBA Size +# Set logical block size of default namespace +# If DefaultNamespace is false, this value will ignored +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk size check +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 + +## List of disk image path for each namespace +# e.g. Setting disk image for namespace 2 -> DiskImageFile2 = +DiskImageFile1 = nvme.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Universal Flash Storage Configuration +[ufs] + +## AMBA System Bus <-> UFS Host Controller +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 1 +AXIClock = 250000000 # 64bit @ 250MHz -> 2GB/s + +## UFS Host Controller <-> UFS Device +# Set MIPI M-PHY mode and lane count +# Possible values: +# 0: HS-G1 +# 1: HS-G2 +# 2: HS-G3 +# 3: HS-G4 +MPHYMode = 2 +MPHYLane = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = ufs.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Serial ATA Configuration +[sata] + +## PCI Express Interface +# Set PCIe generation and lane count +# Possible values: +# 0: PCI Express 1.x (2.5GT/s/lane) +# 1: PCI Express 2.x (5GT/s/lane) +# 2: PCI Express 3.x (8GT/s/lane) +PCIEGeneration = 2 +PCIELane = 4 + +## PCI Express Endpoint <-> NSATA AHCI HBA +# Set bus width and clock speed of AXI-Stream interface +# Possible values: +# 0: 32Bit +# 1: 64Bit +# 2: 128Bit +# 3: 256Bit +# 4: 512Bit +# 5: 1024Bit +AXIBusWidth = 2 +AXIClock = 250000000 # 128bit @ 250MHz -> 4GB/s + +## SATA AHCI HBA <-> SATA Device +# Set SATA generation +# Possible values: +# 0: SATA 1.0 (1.5Gbps) +# 1: SATA 2.0 (3Gbps) +# 2: SATA 3.0 (6Gbps) +SATAMode = 2 + +## Set interval for controller main loop +WorkInterval = 1000000 # 1us + +## Maximum # of I/O request handling on one loop +MaxRequestCount = 8 + +## LBA Size +# Set logical block size of default namespace +LBASize = 512 + +## Enable Disk Image +# 1 for enable I/O to disk image +# 0 for disable disk image +EnableDiskImage = 0 + +## Disk Image Filename +# If EnableDiskImage is 1, and no file exists, file with size of SSD will created +# If StrictSizeCheck is 1, disk file exists, and size of disk image is not equal to SSD size, it makes error +StrictSizeCheck = 0 +DiskImageFile = sata.img + +## Copy-on-Write Disk +# 0 for use normal disk +# 1 for use Copy-on-write disk (Write to disk will not affect disk image file) +UseCopyOnWriteDisk = 0 + +# Parallelism Abstraction Layer Configuration +[pal] + +## Set SSD structure +# Channel: # of channels in SSD +# Package: # of packages in one channel +Channel = 8 +Package = 4 + +## Set NAND package structure +# Die: # of die in one package +# Plane: # of plane in one die +# Block: # of block in one plane +# Page: # of page in one block +# PageSize: Size of one page in byte +Die = 2 +Plane = 2 +Block = 512 +Page = 512 +PageSize = 8192 + +## Multi-plane operation +# 1 for enable multi-plane operation +EnableMultiPlaneOperation = 1 + +## Set type of NAND flash +# Possible values: +# 0: Single Level Cell +# 1: Multi Level Cell +# 2: Triple Level Cell +# Please check NAND timing has valid values +# SLC: LSB timing should valid +# MLC: LSB and MSB timing should valid +# TLC: LSB, CSB and MSB timing should valid +NANDType = 1 + +## Set NAND timing +LSBRead = 40000000 +LSBWrite = 500000000 +CSBRead = 0 +CSBWrite = 0 +MSBRead = 65000000 +MSBWrite = 1300000000 +Erase = 3500000000 + +## Set speed and width of DMA in channel in MT/s +# Width should be 8 or 16 +# Typical values from ONFi: +# ONFi 1.x 2.x 3.x~4.x 4.x +# Timing Mode SDR NV-DDR NV-DDR2 NV-DDR3 +# 0 10 40 67 67 +# 1 20 67 80 80 +# 2 29 100 133 133 +# 3 33 133 167 167 +# 4 40 167 200 200 +# 5 50 200 267 267 +# 6 - - 333 333 +# 7 - - 400 400 +# 8 - - 533 533 +# 9 - - - 667 +# 10 - - - 800 +DMASpeed = 400 +DMAWidth = 8 + +## Set superblock/page size +# Superblock/page size will multiplied by each values +# Leave empty will disable superblock feature +# Possible values: +# C: # Channel +# W: # Package/Way +# D: # Die +# P: # Plane (If multi-plane mode is enabled, P will always applied) +SuperblockSize = C + +## Set page allocation order +# This order will used when disassembling logical address to physical address +# Possible values: +# C: Channel +# W: Package/Way +# D: Die +# P: Plane +PageAllocation = CWDP + +# Flash Translation Layer Configuration +[ftl] + +## Set mapping method +# Possible values: +# 0: Page level mapping +MappingMode = 0 + +## Set FTL over-provisioning ratio +OverProvisioningRatio = 0.70 + +## Set FTL erase threshold to mark as bad block +EraseThreshold = 100000 + +## Filling options +# Filling Mode +# Possible values: +# 0: Sequential filling + Sequential invalidation +# 1: Sequential filling + Random invalidation +# 2: Random filling + Random invalidation +FillingMode = 0 +# FillRatio +# Fill (warm-up) pages before simulation +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +FillRatio = 0.0 +# InvalidPageRatio +# Create invalid pages by overwrite filled pages +# Set # pages to write (Ratio to total logical pages) +# 0.0 <= val <= 1.0 +InvalidPageRatio = 0.0 + +## Set victim selection algorithm +# Possible values: +# 0: Greedy: Choose least utilized block to clean +# 1: Cost-Benefit: Choose a block that lowest (Utilization / ((1 - Utilization) * Age)) +# 2: Random: Choose random block +# 3: D-CHOICE: Choose least utilized block in randomly sampled blocks +EvictPolicy = 0 + +## DChoice parameter +# When sampling blocks, total blocks to erase * DChoiceParam will be selected +DChoiceParam = 3 + +## Set garbage collection threshold (ratio of free blocks left) +GCThreshold = 0.64 + +## Garbage collection mode +# Possible values: +# 0: Reclaim n blocks +# 1: Reclaim blocks until threshold +GCMode = 0 + +## Specify n (Only in GCMode = 0) +# n > 0 +GCReclaimBlocks = 1 + +## Specify threshold (Only in GCMode = 1) +# t > GCThreshold +GCReclaimThreshold = 0.12 + +## Random I/O tweak +# Enable random I/O tweak when using superpage based mapping +EnableRandomIOTweak = 1 + +# Internal Cache Layer Configuration +[icl] + +## Set Cache size +# Cacheline size = physical page size * (multi-plane mode ? plane count : 1) +# Directed-map cache: Set way as 1 +# Fully-associative cache: Set way value as 0 +CacheSize = 536870912 # 512MiB +CacheWaySize = 8 + +## Set read caching (1 for enable) +EnableReadCache = 1 + +## Set read prefetching (1 for enable) +EnableReadPrefetch = 1 + +## Set prefetch granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +ReadPrefetchMode = 1 + +## Set # of I/O to determine sequential access +# Value < 1 is invalid +# 1 means if 2 contiguous I/O is sequential, prefetch will be enabled +ReadPrefetchCount = 3 + +## Set size of sequential I/O to determine as sequential access +# At least (Super page size * ratio) should be accessed as sequential +# 0 < ratio +ReadPrefetchRatio = 0.25 + +## Set write caching (1 for enable) +EnableWriteCache = 1 + +## Set cache evict policy +# Possible values: +# 0: RANDOM: Evict entry in random fashion +# 1: FIFO: Evict most oldest entry in selected set +# 2: LRU: Evict least recently used entry in selected set +EvictPolicy = 2 + +## Set cache evict granularity +# Possible values: +# 0: One super page +# 1: One page from all NAND flashes +EvictMode = 1 + +## Set cache metadata latency +# Byte / ps +CacheLatency = 10 + +# DRAM configuration +[dram] + +## Select DRAM model to use +# Possible values: +# 0: Simple DRAM model based on atomic dram controller of gem5 +Model = 0 + +## DRAM structure parameters +Channel = 1 +Rank = 1 +Bank = 8 +Chip = 1 +BusWidth = 32 +BurstLength = 8 +ChipSize = 1073741824 +PageSize = 4096 + +## DRAM timing parameters (Unit: ps) +# tCK = 1250 +# tRCD = 13750 +# tCL = 13750 +# tRP = 13750 +# tRAS = 35000 +# tWR = 15000 +# tRTP = 7500 +# tBURST +# tCCD_L = +# tRFC = 160000 # 160ns ~ 70200ns +# tREFI = 7800000 +# tWTR = 7500 +# tRTW = +# tCS = +# tRRD = 6000 +# tRRD_L = +# tXAW = +# tXP = 6000 +# tXPDLL = 24000 +# tXS = 170000 # tRFC + 10ns +# tXSDLL = 640000 + +## DRAM power parameters (Unit: mA or V) +# IDD0_0 = 40 +# IDD0_1 = 0 +# IDD2P0_0 = 12 +# IDD2P0_1 = 0 +# IDD2P1_0 = 14 +# IDD2P1_1 = 0 +# IDD2N_0 = 21 +# IDD2N_1 = 0 +# IDD3P0_0 = 21 +# IDD3P0_1 = 0 +# IDD3P1_0 = 21 +# IDD3P1_1 = 0 +# IDD3N_0 = 34 +# IDD3N_1 = 0 +# IDD4R_0 = 100 +# IDD4R_1 = 0 +# IDD4W_0 = 105 +# IDD4W_1 = 0 +# IDD5_0 = 182 +# IDD5_1 = 0 +# IDD6_0 = 12 +# IDD6_1 = 0 +# VDD_0 = 1.35 +# VDD_1 = 0 diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/config.cc b/hotness/SimpleSSD-Standalone/simplessd/cpu/config.cc new file mode 100644 index 0000000000..f010e48741 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/config.cc @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "cpu/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace CPU { + +const char NAME_CLOCK[] = "ClockSpeed"; +const char NAME_CORE_HIL[] = "HILCoreCount"; +const char NAME_CORE_ICL[] = "ICLCoreCount"; +const char NAME_CORE_FTL[] = "FTLCoreCount"; + +Config::Config() { + clock = 400000000; + hilCore = 1; + iclCore = 1; + ftlCore = 1; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_CLOCK)) { + clock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CORE_HIL)) { + hilCore = (uint32_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CORE_ICL)) { + iclCore = (uint32_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CORE_FTL)) { + ftlCore = (uint32_t)strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (clock == 0) { + panic("Invalid ClockSpeed"); + } +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case CPU_CLOCK: + ret = clock; + break; + case CPU_CORE_HIL: + ret = hilCore; + break; + case CPU_CORE_ICL: + ret = iclCore; + break; + case CPU_CORE_FTL: + ret = ftlCore; + break; + } + + return ret; +} + +} // namespace CPU + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/config.hh b/hotness/SimpleSSD-Standalone/simplessd/cpu/config.hh new file mode 100644 index 0000000000..24b93cf8a1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/config.hh @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __CPU_CONFIG__ +#define __CPU_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace CPU { + +typedef enum { + CPU_CLOCK, + CPU_CORE_HIL, + CPU_CORE_ICL, + CPU_CORE_FTL, +} CPU_CONFIG; + +class Config : public BaseConfig { + private: + uint64_t clock; //!< Default: 400MHz + uint32_t hilCore; //!< Default: 1 + uint32_t iclCore; //!< Default: 1 + uint32_t ftlCore; //!< Default: 1 + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + uint64_t readUint(uint32_t) override; +}; + +} // namespace CPU + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/cpu.cc b/hotness/SimpleSSD-Standalone/simplessd/cpu/cpu.cc new file mode 100644 index 0000000000..36823c13d8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/cpu.cc @@ -0,0 +1,1005 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "cpu/cpu.hh" + +#include + +#include "sim/trace.hh" + +namespace SimpleSSD { + +namespace CPU { + +InstStat::_InstStat() + : branch(0), + load(0), + store(0), + arithmetic(0), + floatingPoint(0), + otherInsts(0), + latency(0) {} + +InstStat::_InstStat(uint64_t b, uint64_t l, uint64_t s, uint64_t a, uint64_t f, + uint64_t o, uint64_t c) + : branch(b), + load(l), + store(s), + arithmetic(a), + floatingPoint(f), + otherInsts(o) { + latency = sum(); + latency *= c; +} + +InstStat &InstStat::operator+=(const InstStat &rhs) { + this->branch += rhs.branch; + this->load += rhs.load; + this->store += rhs.store; + this->arithmetic += rhs.arithmetic; + this->floatingPoint += rhs.floatingPoint; + this->otherInsts += rhs.otherInsts; + // Do not add up totalcycles + + return *this; +} + +uint64_t InstStat::sum() { + return branch + load + store + arithmetic + floatingPoint + otherInsts; +} + +JobEntry::_JobEntry(DMAFunction &f, void *c, InstStat *i) + : func(f), context(c), inst(i) {} + +CPU::CoreStat::CoreStat() : busy(0) {} + +CPU::Core::Core() : busy(false) { + jobEvent = allocate([this](uint64_t) { jobDone(); }); +} + +CPU::Core::~Core() {} + +bool CPU::CPU::Core::isBusy() { + return busy; +} + +uint64_t CPU::CPU::Core::getJobListSize() { + return jobs.size(); +} + +CPU::CoreStat &CPU::Core::getStat() { + return stat; +} + +void CPU::Core::submitJob(JobEntry job, uint64_t delay) { + job.delay = delay; + job.submitAt = getTick(); + jobs.push(job); + + if (!busy) { + handleJob(); + } +} + +void CPU::Core::handleJob() { + auto &iter = jobs.front(); + uint64_t now = getTick(); + uint64_t diff = now - iter.submitAt; + uint64_t finishedAt; + + if (diff >= iter.delay) { + finishedAt = now + iter.inst->latency; + } + else { + finishedAt = now + iter.inst->latency + iter.delay - diff; + } + + busy = true; + + schedule(jobEvent, finishedAt); +} + +void CPU::Core::jobDone() { + auto &iter = jobs.front(); + + iter.func(getTick(), iter.context); + stat.busy += iter.inst->latency; + stat.instStat += *iter.inst; + + jobs.pop(); + busy = false; + + if (jobs.size() > 0) { + handleJob(); + } +} + +void CPU::Core::addStat(InstStat &inst) { + stat.busy += inst.latency; + stat.instStat += inst; +} + +CPU::CPU(ConfigReader &c) : conf(c), lastResetStat(0) { + clockSpeed = conf.readUint(CONFIG_CPU, CPU_CLOCK); + clockPeriod = 1000000000000. / clockSpeed; // in pico-seconds + + hilCore.resize(conf.readUint(CONFIG_CPU, CPU_CORE_HIL)); + iclCore.resize(conf.readUint(CONFIG_CPU, CPU_CORE_ICL)); + ftlCore.resize(conf.readUint(CONFIG_CPU, CPU_CORE_FTL)); + + // Initialize CPU table + cpi.insert({FTL, std::unordered_map()}); + cpi.insert({FTL__PAGE_MAPPING, std::unordered_map()}); + cpi.insert({ICL, std::unordered_map()}); + cpi.insert({ICL__GENERIC_CACHE, std::unordered_map()}); + cpi.insert({HIL, std::unordered_map()}); + cpi.insert({NVME__CONTROLLER, std::unordered_map()}); + cpi.insert({NVME__PRPLIST, std::unordered_map()}); + cpi.insert({NVME__SGL, std::unordered_map()}); + cpi.insert({NVME__SUBSYSTEM, std::unordered_map()}); + cpi.insert({NVME__NAMESPACE, std::unordered_map()}); + cpi.insert({NVME__OCSSD, std::unordered_map()}); + cpi.insert({UFS__DEVICE, std::unordered_map()}); + cpi.insert({SATA__DEVICE, std::unordered_map()}); + + // Insert item (Use cpu/generator/generate.py to generate this code) + cpi.find(0)->second.insert({0, InstStat(5, 32, 6, 13, 0, 1, clockPeriod)}); + cpi.find(0)->second.insert({1, InstStat(5, 32, 6, 13, 0, 1, clockPeriod)}); + cpi.find(0)->second.insert({3, InstStat(5, 32, 6, 13, 0, 1, clockPeriod)}); + cpi.find(0)->second.insert({4, InstStat(4, 24, 4, 6, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert({0, InstStat(8, 28, 7, 18, 0, 1, clockPeriod)}); + cpi.find(1)->second.insert({1, InstStat(8, 28, 7, 19, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert({3, InstStat(4, 28, 6, 11, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert( + {4, InstStat(63, 180, 21, 147, 0, 2, clockPeriod)}); + cpi.find(1)->second.insert( + {9, InstStat(177, 504, 113, 415, 118, 19, clockPeriod)}); + cpi.find(1)->second.insert( + {10, InstStat(157, 616, 102, 338, 0, 2, clockPeriod)}); + cpi.find(1)->second.insert( + {5, InstStat(45, 180, 15, 155, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert( + {6, InstStat(133, 452, 54, 377, 91, 1, clockPeriod)}); + cpi.find(1)->second.insert( + {8, InstStat(34, 140, 10, 146, 0, 0, clockPeriod)}); + cpi.find(1)->second.insert( + {7, InstStat(120, 236, 86, 260, 0, 1, clockPeriod)}); + cpi.find(2)->second.insert({0, InstStat(8, 88, 17, 27, 0, 1, clockPeriod)}); + cpi.find(2)->second.insert({1, InstStat(8, 88, 17, 27, 0, 1, clockPeriod)}); + cpi.find(2)->second.insert({2, InstStat(5, 40, 6, 12, 0, 0, clockPeriod)}); + cpi.find(2)->second.insert({3, InstStat(5, 40, 6, 12, 0, 0, clockPeriod)}); + cpi.find(2)->second.insert({4, InstStat(5, 40, 6, 12, 0, 0, clockPeriod)}); + cpi.find(3)->second.insert( + {0, InstStat(90, 532, 64, 284, 0, 1, clockPeriod)}); + cpi.find(3)->second.insert( + {1, InstStat(82, 496, 53, 312, 0, 5, clockPeriod)}); + cpi.find(3)->second.insert({2, InstStat(22, 120, 20, 59, 0, 2, clockPeriod)}); + cpi.find(3)->second.insert({3, InstStat(22, 120, 20, 61, 0, 2, clockPeriod)}); + cpi.find(3)->second.insert({4, InstStat(9, 72, 12, 86, 0, 1, clockPeriod)}); + cpi.find(4)->second.insert( + {0, InstStat(61, 312, 102, 120, 0, 2, clockPeriod)}); + cpi.find(4)->second.insert( + {1, InstStat(61, 312, 102, 120, 0, 2, clockPeriod)}); + cpi.find(4)->second.insert({2, InstStat(27, 100, 27, 49, 0, 1, clockPeriod)}); + cpi.find(5)->second.insert( + {14, InstStat(44, 164, 32, 68, 0, 2, clockPeriod)}); + cpi.find(5)->second.insert({13, InstStat(0, 0, 0, 0, 0, 0, clockPeriod)}); + cpi.find(5)->second.insert( + {16, InstStat(136, 360, 65, 230, 0, 3, clockPeriod)}); + cpi.find(5)->second.insert( + {15, InstStat(54, 140, 36, 91, 0, 8, clockPeriod)}); + cpi.find(5)->second.insert({11, InstStat(0, 0, 0, 0, 0, 0, clockPeriod)}); + cpi.find(5)->second.insert({12, InstStat(0, 0, 0, 0, 0, 0, clockPeriod)}); + cpi.find(6)->second.insert( + {17, InstStat(41, 168, 42, 75, 0, 1, clockPeriod)}); + cpi.find(6)->second.insert( + {0, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(6)->second.insert( + {1, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(7)->second.insert( + {18, InstStat(44, 152, 35, 78, 0, 2, clockPeriod)}); + cpi.find(7)->second.insert( + {0, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(7)->second.insert( + {1, InstStat(99, 456, 94, 177, 0, 6, clockPeriod)}); + cpi.find(8)->second.insert( + {19, InstStat(119, 220, 45, 160, 0, 6, clockPeriod)}); + cpi.find(8)->second.insert({20, InstStat(4, 40, 14, 110, 0, 1, clockPeriod)}); + cpi.find(8)->second.insert( + {21, InstStat(70, 200, 42, 161, 0, 1, clockPeriod)}); + cpi.find(9)->second.insert({19, InstStat(27, 44, 5, 37, 0, 0, clockPeriod)}); + cpi.find(9)->second.insert( + {0, InstStat(82, 292, 42, 128, 0, 4, clockPeriod)}); + cpi.find(9)->second.insert( + {1, InstStat(86, 304, 47, 141, 0, 3, clockPeriod)}); + cpi.find(9)->second.insert({2, InstStat(51, 124, 28, 78, 0, 3, clockPeriod)}); + cpi.find(9)->second.insert( + {22, InstStat(131, 364, 71, 200, 0, 7, clockPeriod)}); + cpi.find(10)->second.insert( + {19, InstStat(155, 100, 12, 208, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {0, InstStat(93, 284, 60, 146, 0, 5, clockPeriod)}); + cpi.find(10)->second.insert( + {1, InstStat(95, 276, 60, 150, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {22, InstStat(119, 328, 76, 186, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {5, InstStat(54, 172, 69, 89, 0, 1, clockPeriod)}); + cpi.find(10)->second.insert( + {6, InstStat(72, 236, 77, 141, 0, 3, clockPeriod)}); + cpi.find(10)->second.insert( + {7, InstStat(68, 204, 77, 116, 0, 1, clockPeriod)}); + cpi.find(10)->second.insert( + {20, InstStat(65, 388, 63, 303, 0, 1, clockPeriod)}); + cpi.find(10)->second.insert( + {23, InstStat(128, 368, 76, 204, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {24, InstStat(128, 384, 81, 209, 0, 6, clockPeriod)}); + cpi.find(10)->second.insert( + {25, InstStat(69, 184, 43, 112, 0, 4, clockPeriod)}); + cpi.find(10)->second.insert( + {26, InstStat(206, 692, 157, 315, 0, 5, clockPeriod)}); + cpi.find(10)->second.insert( + {27, InstStat(183, 620, 154, 284, 0, 6, clockPeriod)}); + cpi.find(10)->second.insert( + {28, InstStat(162, 460, 78, 227, 0, 4, clockPeriod)}); + cpi.find(11)->second.insert( + {29, InstStat(51, 132, 40, 97, 0, 0, clockPeriod)}); + cpi.find(11)->second.insert( + {30, InstStat(212, 460, 117, 491, 0, 9, clockPeriod)}); + cpi.find(11)->second.insert( + {31, InstStat(42, 172, 43, 74, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert( + {32, InstStat(42, 172, 43, 74, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert({0, InstStat(29, 76, 17, 51, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert({1, InstStat(29, 76, 17, 51, 0, 2, clockPeriod)}); + cpi.find(11)->second.insert({2, InstStat(25, 64, 18, 44, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {19, InstStat(157, 352, 69, 178, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {31, InstStat(42, 172, 43, 73, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {32, InstStat(42, 172, 43, 73, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {0, InstStat(28, 84, 23, 119, 0, 0, clockPeriod)}); + cpi.find(12)->second.insert( + {1, InstStat(28, 84, 23, 120, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert({2, InstStat(25, 64, 18, 44, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {33, InstStat(57, 212, 36, 128, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {34, InstStat(34, 116, 29, 72, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert({35, InstStat(16, 64, 9, 38, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {36, InstStat(28, 72, 15, 48, 0, 2, clockPeriod)}); + cpi.find(12)->second.insert( + {37, InstStat(57, 212, 36, 127, 0, 3, clockPeriod)}); + cpi.find(12)->second.insert( + {38, InstStat(34, 128, 31, 68, 0, 2, clockPeriod)}); + cpi.find(12)->second.insert( + {39, InstStat(18, 56, 10, 37, 0, 1, clockPeriod)}); + cpi.find(12)->second.insert( + {40, InstStat(33, 100, 17, 61, 0, 3, clockPeriod)}); +} + +CPU::~CPU() {} + +void CPU::calculatePower(Power &power) { + // Print stats before die + ParseXML param; + uint64_t simCycle = (getTick() - lastResetStat) / clockPeriod; + uint32_t totalCore = hilCore.size() + iclCore.size() + ftlCore.size(); + uint32_t coreIdx = 0; + + param.initialize(); + + // system + { + param.sys.number_of_L1Directories = 0; + param.sys.number_of_L2Directories = 0; + param.sys.number_of_L2s = 1; + param.sys.Private_L2 = 0; + param.sys.number_of_L3s = 0; + param.sys.number_of_NoCs = 0; + param.sys.homogeneous_cores = 0; + param.sys.homogeneous_L2s = 1; + param.sys.homogeneous_L1Directories = 1; + param.sys.homogeneous_L2Directories = 1; + param.sys.homogeneous_L3s = 1; + param.sys.homogeneous_ccs = 1; + param.sys.homogeneous_NoCs = 1; + param.sys.core_tech_node = 40; + param.sys.target_core_clockrate = clockSpeed / 1000000; + param.sys.temperature = 340; + param.sys.number_cache_levels = 2; + param.sys.interconnect_projection_type = 1; + param.sys.device_type = 0; + param.sys.longer_channel_device = 1; + param.sys.Embedded = 1; + param.sys.opt_clockrate = 1; + param.sys.machine_bits = 64; + param.sys.virtual_address_width = 48; + param.sys.physical_address_width = 48; + param.sys.virtual_memory_page_size = 4096; + param.sys.total_cycles = simCycle; + param.sys.number_of_cores = totalCore; + } + + // Now, we are using heterogeneous cores + for (coreIdx = 0; coreIdx < totalCore; coreIdx++) { + // system.core + { + param.sys.core[coreIdx].clock_rate = param.sys.target_core_clockrate; + param.sys.core[coreIdx].opt_local = 0; + param.sys.core[coreIdx].instruction_length = 32; + param.sys.core[coreIdx].opcode_width = 7; + param.sys.core[coreIdx].x86 = 0; + param.sys.core[coreIdx].micro_opcode_width = 8; + param.sys.core[coreIdx].machine_type = 0; + param.sys.core[coreIdx].number_hardware_threads = 1; + param.sys.core[coreIdx].fetch_width = 2; + param.sys.core[coreIdx].number_instruction_fetch_ports = 1; + param.sys.core[coreIdx].decode_width = 2; + param.sys.core[coreIdx].issue_width = 4; + param.sys.core[coreIdx].peak_issue_width = 7; + param.sys.core[coreIdx].commit_width = 4; + param.sys.core[coreIdx].fp_issue_width = 1; + param.sys.core[coreIdx].prediction_width = 0; + param.sys.core[coreIdx].pipelines_per_core[0] = 1; + param.sys.core[coreIdx].pipelines_per_core[1] = 1; + param.sys.core[coreIdx].pipeline_depth[0] = 8; + param.sys.core[coreIdx].pipeline_depth[1] = 8; + param.sys.core[coreIdx].ALU_per_core = 3; + param.sys.core[coreIdx].MUL_per_core = 1; + param.sys.core[coreIdx].FPU_per_core = 1; + param.sys.core[coreIdx].instruction_buffer_size = 32; + param.sys.core[coreIdx].decoded_stream_buffer_size = 16; + param.sys.core[coreIdx].instruction_window_scheme = 0; + param.sys.core[coreIdx].instruction_window_size = 20; + param.sys.core[coreIdx].fp_instruction_window_size = 15; + param.sys.core[coreIdx].ROB_size = 0; + param.sys.core[coreIdx].archi_Regs_IRF_size = 32; + param.sys.core[coreIdx].archi_Regs_FRF_size = 32; + param.sys.core[coreIdx].phy_Regs_IRF_size = 64; + param.sys.core[coreIdx].phy_Regs_FRF_size = 64; + param.sys.core[coreIdx].rename_scheme = 0; + param.sys.core[coreIdx].checkpoint_depth = 1; + param.sys.core[coreIdx].register_windows_size = 0; + strcpy(param.sys.core[coreIdx].LSU_order, "inorder"); + param.sys.core[coreIdx].store_buffer_size = 4; + param.sys.core[coreIdx].load_buffer_size = 0; + param.sys.core[coreIdx].memory_ports = 1; + param.sys.core[coreIdx].RAS_size = 0; + param.sys.core[coreIdx].number_of_BPT = 2; + param.sys.core[coreIdx].number_of_BTB = 2; + } + + // system.core.itlb + param.sys.core[coreIdx].itlb.number_entries = 64; + + // system.core.icache + { + param.sys.core[coreIdx].icache.icache_config[0] = 32768; + param.sys.core[coreIdx].icache.icache_config[1] = 8; + param.sys.core[coreIdx].icache.icache_config[2] = 4; + param.sys.core[coreIdx].icache.icache_config[3] = 1; + param.sys.core[coreIdx].icache.icache_config[4] = 10; + param.sys.core[coreIdx].icache.icache_config[5] = 10; + param.sys.core[coreIdx].icache.icache_config[6] = 32; + param.sys.core[coreIdx].icache.icache_config[7] = 0; + param.sys.core[coreIdx].icache.buffer_sizes[0] = 4; + param.sys.core[coreIdx].icache.buffer_sizes[1] = 4; + param.sys.core[coreIdx].icache.buffer_sizes[2] = 4; + param.sys.core[coreIdx].icache.buffer_sizes[3] = 0; + } + + // system.core dtlb + param.sys.core[coreIdx].dtlb.number_entries = 64; + + // system.core.dcache + { + param.sys.core[coreIdx].dcache.dcache_config[0] = 32768; + param.sys.core[coreIdx].dcache.dcache_config[1] = 8; + param.sys.core[coreIdx].dcache.dcache_config[2] = 4; + param.sys.core[coreIdx].dcache.dcache_config[3] = 1; + param.sys.core[coreIdx].dcache.dcache_config[4] = 10; + param.sys.core[coreIdx].dcache.dcache_config[5] = 10; + param.sys.core[coreIdx].dcache.dcache_config[6] = 32; + param.sys.core[coreIdx].dcache.dcache_config[7] = 0; + param.sys.core[coreIdx].dcache.buffer_sizes[0] = 4; + param.sys.core[coreIdx].dcache.buffer_sizes[1] = 4; + param.sys.core[coreIdx].dcache.buffer_sizes[2] = 4; + param.sys.core[coreIdx].dcache.buffer_sizes[3] = 4; + } + + // system.core.BTB + param.sys.core[coreIdx].BTB.BTB_config[0] = 4096; + param.sys.core[coreIdx].BTB.BTB_config[1] = 4; + param.sys.core[coreIdx].BTB.BTB_config[2] = 2; + param.sys.core[coreIdx].BTB.BTB_config[3] = 2; + param.sys.core[coreIdx].BTB.BTB_config[4] = 1; + param.sys.core[coreIdx].BTB.BTB_config[5] = 1; + } + + // system.L2 + { + param.sys.L2[0].L2_config[0] = 1048576; + param.sys.L2[0].L2_config[1] = 32; + param.sys.L2[0].L2_config[2] = 8; + param.sys.L2[0].L2_config[3] = 8; + param.sys.L2[0].L2_config[4] = 8; + param.sys.L2[0].L2_config[5] = 23; + param.sys.L2[0].L2_config[6] = 32; + param.sys.L2[0].L2_config[7] = 1; + param.sys.L2[0].buffer_sizes[0] = 16; + param.sys.L2[0].buffer_sizes[1] = 16; + param.sys.L2[0].buffer_sizes[2] = 16; + param.sys.L2[0].buffer_sizes[3] = 16; + param.sys.L2[0].clockrate = param.sys.target_core_clockrate; + param.sys.L2[0].ports[0] = 1; + param.sys.L2[0].ports[1] = 1; + param.sys.L2[0].ports[2] = 1; + param.sys.L2[0].device_type = 0; + } + + // Etcetera + param.sys.mc.req_window_size_per_channel = 32; + + // Apply stat values + + // Core stat + coreIdx = 0; + + for (auto &core : hilCore) { + CoreStat &stat = core.getStat(); + + param.sys.core[coreIdx].total_instructions = stat.instStat.sum(); + param.sys.core[coreIdx].int_instructions = stat.instStat.arithmetic; + param.sys.core[coreIdx].fp_instructions = stat.instStat.floatingPoint; + param.sys.core[coreIdx].branch_instructions = stat.instStat.branch; + param.sys.core[coreIdx].load_instructions = stat.instStat.load; + param.sys.core[coreIdx].store_instructions = stat.instStat.store; + param.sys.core[coreIdx].busy_cycles = stat.busy / clockPeriod; + + coreIdx++; + } + + for (auto &core : iclCore) { + CoreStat &stat = core.getStat(); + + param.sys.core[coreIdx].total_instructions = stat.instStat.sum(); + param.sys.core[coreIdx].int_instructions = stat.instStat.arithmetic; + param.sys.core[coreIdx].fp_instructions = stat.instStat.floatingPoint; + param.sys.core[coreIdx].branch_instructions = stat.instStat.branch; + param.sys.core[coreIdx].load_instructions = stat.instStat.load; + param.sys.core[coreIdx].store_instructions = stat.instStat.store; + param.sys.core[coreIdx].busy_cycles = stat.busy / clockPeriod; + + coreIdx++; + } + + for (auto &core : ftlCore) { + CoreStat &stat = core.getStat(); + + param.sys.core[coreIdx].total_instructions = stat.instStat.sum(); + param.sys.core[coreIdx].int_instructions = stat.instStat.arithmetic; + param.sys.core[coreIdx].fp_instructions = stat.instStat.floatingPoint; + param.sys.core[coreIdx].branch_instructions = stat.instStat.branch; + param.sys.core[coreIdx].load_instructions = stat.instStat.load; + param.sys.core[coreIdx].store_instructions = stat.instStat.store; + param.sys.core[coreIdx].busy_cycles = stat.busy / clockPeriod; + + coreIdx++; + }; + + for (coreIdx = 0; coreIdx < totalCore; coreIdx++) { + param.sys.core[coreIdx].total_cycles = simCycle; + param.sys.core[coreIdx].idle_cycles = + simCycle - param.sys.core[coreIdx].busy_cycles; + param.sys.core[coreIdx].committed_instructions = + param.sys.core[coreIdx].total_instructions; + param.sys.core[coreIdx].committed_int_instructions = + param.sys.core[coreIdx].int_instructions; + param.sys.core[coreIdx].committed_fp_instructions = + param.sys.core[coreIdx].fp_instructions; + param.sys.core[coreIdx].pipeline_duty_cycle = 1; + param.sys.core[coreIdx].IFU_duty_cycle = 0.9; + param.sys.core[coreIdx].BR_duty_cycle = 0.72; + param.sys.core[coreIdx].LSU_duty_cycle = 0.71; + param.sys.core[coreIdx].MemManU_I_duty_cycle = 0.9; + param.sys.core[coreIdx].MemManU_D_duty_cycle = 0.71; + param.sys.core[coreIdx].ALU_duty_cycle = 0.76; + param.sys.core[coreIdx].MUL_duty_cycle = 0.82; + param.sys.core[coreIdx].FPU_duty_cycle = 0.0; + param.sys.core[coreIdx].ALU_cdb_duty_cycle = 0.76; + param.sys.core[coreIdx].MUL_cdb_duty_cycle = 0.82; + param.sys.core[coreIdx].FPU_cdb_duty_cycle = 0.0; + param.sys.core[coreIdx].ialu_accesses = param.sys.core[0].int_instructions; + param.sys.core[coreIdx].fpu_accesses = param.sys.core[0].fp_instructions; + param.sys.core[coreIdx].mul_accesses = + param.sys.core[0].int_instructions * .5; + param.sys.core[coreIdx].int_regfile_reads = + param.sys.core[0].load_instructions; + param.sys.core[coreIdx].float_regfile_reads = + param.sys.core[coreIdx].fp_instructions * .4; + param.sys.core[coreIdx].int_regfile_writes = + param.sys.core[0].store_instructions; + param.sys.core[coreIdx].float_regfile_writes = + param.sys.core[coreIdx].fp_instructions * .4; + + // L1i and L1d + { + auto &core = param.sys.core[coreIdx]; + + core.icache.total_accesses = core.load_instructions * .3; + core.icache.total_hits = core.icache.total_accesses * .7; + core.icache.total_misses = core.icache.total_accesses * .3; + core.icache.read_accesses = core.icache.total_accesses; + core.icache.read_hits = core.icache.total_hits; + core.icache.read_misses = core.icache.total_misses; + core.itlb.total_accesses = core.load_instructions * .2; + core.itlb.total_hits = core.itlb.total_accesses * .8; + core.itlb.total_misses = core.itlb.total_accesses * .2; + + core.dcache.total_accesses = core.load_instructions * .4; + core.dcache.total_hits = core.dcache.total_accesses * .4; + core.dcache.total_misses = core.dcache.total_accesses * .6; + core.dcache.read_accesses = core.dcache.total_accesses * .6; + core.dcache.read_hits = core.dcache.total_hits * .6; + core.dcache.read_misses = core.dcache.total_misses * .6; + core.dcache.write_accesses = core.dcache.total_accesses * .4; + core.dcache.write_hits = core.dcache.total_hits * .4; + core.dcache.write_misses = core.dcache.total_misses * .4; + core.dcache.write_backs = core.dcache.total_misses * .4; + core.dtlb.total_accesses = core.load_instructions * .2; + core.dtlb.total_hits = core.itlb.total_accesses * .8; + core.dtlb.total_misses = core.itlb.total_accesses * .2; + } + } + + // L2 + param.sys.L2[0].duty_cycle = 1.; + + if (param.sys.number_of_L2s > 0) { + auto &L2 = param.sys.L2[0]; + + L2.total_accesses = param.sys.core[0].dcache.write_backs; + L2.total_hits = L2.total_accesses * .4; + L2.total_misses = L2.total_accesses * .6; + L2.read_accesses = L2.total_accesses * .5; + L2.read_hits = L2.total_hits * .5; + L2.read_misses = L2.total_misses * .5; + L2.write_accesses = L2.total_accesses * .5; + L2.write_hits = L2.total_hits * .5; + L2.write_misses = L2.total_misses * .5; + L2.write_backs = L2.total_misses * .4; + } + else { + param.sys.L2[0].total_accesses = 0; + param.sys.L2[0].total_hits = 0; + param.sys.L2[0].total_misses = 0; + param.sys.L2[0].read_accesses = 0; + param.sys.L2[0].read_hits = 0; + param.sys.L2[0].read_misses = 0; + param.sys.L2[0].write_accesses = 0; + param.sys.L2[0].write_hits = 0; + param.sys.L2[0].write_misses = 0; + param.sys.L2[0].write_backs = 0; + } + + // L3 + param.sys.L3[0].duty_cycle = 1.; + + if (param.sys.number_of_L3s > 0) { + auto &L3 = param.sys.L3[0]; + + L3.total_accesses = param.sys.L2[0].write_backs; + L3.total_hits = L3.total_accesses * .4; + L3.total_misses = L3.total_accesses * .6; + L3.read_accesses = L3.total_accesses * .5; + L3.read_hits = L3.total_hits * .5; + L3.read_misses = L3.total_misses * .5; + L3.write_accesses = L3.total_accesses * .5; + L3.write_hits = L3.total_hits * .5; + L3.write_misses = L3.total_misses * .5; + L3.write_backs = L3.total_misses * .4; + } + else { + param.sys.L3[0].total_accesses = 0; + param.sys.L3[0].total_hits = 0; + param.sys.L3[0].total_misses = 0; + param.sys.L3[0].read_accesses = 0; + param.sys.L3[0].read_hits = 0; + param.sys.L3[0].read_misses = 0; + param.sys.L3[0].write_accesses = 0; + param.sys.L3[0].write_hits = 0; + param.sys.L3[0].write_misses = 0; + param.sys.L3[0].write_backs = 0; + } + + McPAT mcpat(¶m); + + mcpat.getPower(power); +} + +uint32_t CPU::leastBusyCPU(std::vector &list) { + uint32_t idx = list.size(); + uint64_t busymin = std::numeric_limits::max(); + + for (uint32_t i = 0; i < list.size(); i++) { + auto &core = list.at(i); + auto busy = core.getStat().busy; + + if (!core.isBusy() && busy < busymin) { + busymin = busy; + idx = i; + } + } + + if (idx == list.size()) { + uint64_t jobmin = std::numeric_limits::max(); + + for (uint32_t i = 0; i < list.size(); i++) { + auto jobs = list.at(i).getJobListSize(); + + if (jobs <= jobmin) { + jobmin = jobs; + idx = i; + } + } + } + + return idx; +} + +void CPU::execute(NAMESPACE ns, FUNCTION fct, DMAFunction &func, void *context, + uint64_t delay) { + Core *pCore = nullptr; + + // Find dedicated core + switch (ns) { + case FTL: + case FTL__PAGE_MAPPING: + if (ftlCore.size() > 0) { + pCore = &ftlCore.at(leastBusyCPU(ftlCore)); + } + + break; + case ICL: + case ICL__GENERIC_CACHE: + if (iclCore.size() > 0) { + pCore = &iclCore.at(leastBusyCPU(iclCore)); + } + + break; + case HIL: + case NVME__CONTROLLER: + case NVME__PRPLIST: + case NVME__SGL: + case NVME__SUBSYSTEM: + case NVME__NAMESPACE: + case NVME__OCSSD: + case UFS__DEVICE: + case SATA__DEVICE: + if (hilCore.size() > 0) { + pCore = &hilCore.at(leastBusyCPU(hilCore)); + } + + break; + default: + panic("Undefined function namespace %u", ns); + + break; + } + + if (pCore) { + // Get CPI table + auto table = cpi.find(ns); + + if (table == cpi.end()) { + panic("Namespace %u not defined in CPI table", ns); + } + + // Get CPI + auto inst = table->second.find(fct); + + if (inst == table->second.end()) { + panic("Namespace %u does not have function %u", ns, fct); + } + + pCore->submitJob(JobEntry(func, context, &inst->second), delay); + } + else { + func(getTick(), context); + } +} + +uint64_t CPU::applyLatency(NAMESPACE ns, FUNCTION fct) { + Core *pCore = nullptr; + + // Find dedicated core + switch (ns) { + case FTL: + case FTL__PAGE_MAPPING: + if (ftlCore.size() > 0) { + pCore = &ftlCore.at(leastBusyCPU(ftlCore)); + } + + break; + case ICL: + case ICL__GENERIC_CACHE: + if (iclCore.size() > 0) { + pCore = &iclCore.at(leastBusyCPU(iclCore)); + } + + break; + case HIL: + case NVME__CONTROLLER: + case NVME__PRPLIST: + case NVME__SGL: + case NVME__SUBSYSTEM: + case NVME__NAMESPACE: + case NVME__OCSSD: + case UFS__DEVICE: + case SATA__DEVICE: + if (hilCore.size() > 0) { + pCore = &hilCore.at(leastBusyCPU(hilCore)); + } + + break; + default: + panic("Undefined function namespace %u", ns); + + break; + } + + if (pCore) { + // Get CPI table + auto table = cpi.find(ns); + + if (table == cpi.end()) { + panic("Namespace %u not defined in CPI table", ns); + } + + // Get CPI + auto inst = table->second.find(fct); + + if (inst == table->second.end()) { + panic("Namespace %u does not have function %u", ns, fct); + } + + pCore->addStat(inst->second); + + return inst->second.latency; + } + + return 0; +} + +void CPU::getStatList(std::vector &list, std::string prefix) { + Stats temp; + std::string number; + + for (uint32_t i = 0; i < hilCore.size(); i++) { + number = std::to_string(i); + + temp.name = prefix + ".hil" + number + ".busy"; + temp.desc = "CPU for HIL core " + number + " busy ticks"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.branch"; + temp.desc = "CPU for HIL core " + number + " executed branch instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.load"; + temp.desc = "CPU for HIL core " + number + " executed load instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.store"; + temp.desc = "CPU for HIL core " + number + " executed store instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.arithmetic"; + temp.desc = + "CPU for HIL core " + number + " executed arithmetic instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.fp"; + temp.desc = + "CPU for HIL core " + number + " executed floating point instructions"; + list.push_back(temp); + + temp.name = prefix + ".hil" + number + ".insts.others"; + temp.desc = "CPU for HIL core " + number + " executed other instructions"; + list.push_back(temp); + } + + for (uint32_t i = 0; i < iclCore.size(); i++) { + number = std::to_string(i); + + temp.name = prefix + ".icl" + number + ".busy"; + temp.desc = "CPU for ICL core " + number + " busy ticks"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.branch"; + temp.desc = "CPU for ICL core " + number + " executed branch instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.load"; + temp.desc = "CPU for ICL core " + number + " executed load instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.store"; + temp.desc = "CPU for ICL core " + number + " executed store instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.arithmetic"; + temp.desc = + "CPU for ICL core " + number + " executed arithmetic instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.fp"; + temp.desc = + "CPU for ICL core " + number + " executed floating point instructions"; + list.push_back(temp); + + temp.name = prefix + ".icl" + number + ".insts.others"; + temp.desc = "CPU for ICL core " + number + " executed other instructions"; + list.push_back(temp); + } + + for (uint32_t i = 0; i < ftlCore.size(); i++) { + number = std::to_string(i); + + temp.name = prefix + ".ftl" + number + ".busy"; + temp.desc = "CPU for FTL core " + number + " busy ticks"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.branch"; + temp.desc = "CPU for FTL core " + number + " executed branch instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.load"; + temp.desc = "CPU for FTL core " + number + " executed store instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.store"; + temp.desc = "CPU for FTL core " + number + " executed load instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.arithmetic"; + temp.desc = + "CPU for FTL core " + number + " executed arithmetic instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.fp"; + temp.desc = + "CPU for FTL core " + number + " executed floating point instructions"; + list.push_back(temp); + + temp.name = prefix + ".ftl" + number + ".insts.others"; + temp.desc = "CPU for FTL core " + number + " executed other instructions"; + list.push_back(temp); + } +} + +void CPU::getStatValues(std::vector &values) { + for (auto &core : hilCore) { + auto &stat = core.getStat(); + + values.push_back(stat.busy); + values.push_back(stat.instStat.branch); + values.push_back(stat.instStat.load); + values.push_back(stat.instStat.store); + values.push_back(stat.instStat.arithmetic); + values.push_back(stat.instStat.floatingPoint); + values.push_back(stat.instStat.otherInsts); + } + + for (auto &core : iclCore) { + auto &stat = core.getStat(); + + values.push_back(stat.busy); + values.push_back(stat.instStat.branch); + values.push_back(stat.instStat.load); + values.push_back(stat.instStat.store); + values.push_back(stat.instStat.arithmetic); + values.push_back(stat.instStat.floatingPoint); + values.push_back(stat.instStat.otherInsts); + } + + for (auto &core : ftlCore) { + auto &stat = core.getStat(); + + values.push_back(stat.busy); + values.push_back(stat.instStat.branch); + values.push_back(stat.instStat.load); + values.push_back(stat.instStat.store); + values.push_back(stat.instStat.arithmetic); + values.push_back(stat.instStat.floatingPoint); + values.push_back(stat.instStat.otherInsts); + } +} + +void CPU::resetStatValues() { + lastResetStat = getTick(); + + for (auto &core : hilCore) { + auto &stat = core.getStat(); + + stat.busy = 0; + stat.instStat = InstStat(); + } + + for (auto &core : iclCore) { + auto &stat = core.getStat(); + + stat.busy = 0; + stat.instStat = InstStat(); + } + + for (auto &core : ftlCore) { + auto &stat = core.getStat(); + + stat.busy = 0; + stat.instStat = InstStat(); + } +} + +void CPU::printLastStat() { + Power power; + + debugprint(LOG_CPU, "Begin CPU power calculation"); + + calculatePower(power); + + debugprint(LOG_CPU, "Core:"); + debugprint(LOG_CPU, " Area: %lf mm^2", power.core.area); + debugprint(LOG_CPU, " Peak Dynamic: %lf W", power.core.peakDynamic); + debugprint(LOG_CPU, " Subthreshold Leakage: %lf W", + power.core.subthresholdLeakage); + debugprint(LOG_CPU, " Gate Leakage: %lf W", power.core.gateLeakage); + debugprint(LOG_CPU, " Runtime Dynamic: %lf W", power.core.runtimeDynamic); + + if (power.level2.area > 0.0) { + debugprint(LOG_CPU, "L2:"); + debugprint(LOG_CPU, " Area: %lf mm^2", power.level2.area); + debugprint(LOG_CPU, " Peak Dynamic: %lf W", power.level2.peakDynamic); + debugprint(LOG_CPU, " Subthreshold Leakage: %lf W", + power.level2.subthresholdLeakage); + debugprint(LOG_CPU, " Gate Leakage: %lf W", power.level2.gateLeakage); + debugprint(LOG_CPU, " Runtime Dynamic: %lf W", + power.level2.runtimeDynamic); + } + + if (power.level3.area > 0.0) { + debugprint(LOG_CPU, "L3:"); + debugprint(LOG_CPU, " Area: %lf mm^2", power.level3.area); + debugprint(LOG_CPU, " Peak Dynamic: %lf W", power.level3.peakDynamic); + debugprint(LOG_CPU, " Subthreshold Leakage: %lf W", + power.level3.subthresholdLeakage); + debugprint(LOG_CPU, " Gate Leakage: %lf W", power.level3.gateLeakage); + debugprint(LOG_CPU, " Runtime Dynamic: %lf W", + power.level3.runtimeDynamic); + } +} + +} // namespace CPU + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/cpu.hh b/hotness/SimpleSSD-Standalone/simplessd/cpu/cpu.hh new file mode 100644 index 0000000000..c1f7c2ebf6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/cpu.hh @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __CPU_CPU__ +#define __CPU_CPU__ + +#include +#include +#include +#include + +#include "cpu/def.hh" +#include "lib/mcpat/mcpat.h" +#include "sim/config_reader.hh" +#include "sim/dma_interface.hh" +#include "sim/simulator.hh" +#include "sim/statistics.hh" + +namespace SimpleSSD { + +namespace CPU { + +typedef struct _InstStat { + // Instruction count + uint64_t branch; + uint64_t load; + uint64_t store; + uint64_t arithmetic; + uint64_t floatingPoint; + uint64_t otherInsts; + + // Total times in ps to execute this insturcion group + uint64_t latency; + + _InstStat(); + _InstStat(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, + uint64_t); + _InstStat &operator+=(const _InstStat &); + uint64_t sum(); +} InstStat; + +typedef struct _JobEntry { + DMAFunction func; + void *context; + InstStat *inst; + uint64_t submitAt; + uint64_t delay; + + _JobEntry(DMAFunction &, void *, InstStat *); +} JobEntry; + +class CPU : public StatObject { + private: + struct CoreStat { + InstStat instStat; + uint64_t busy; + + CoreStat(); + }; + + class Core { + private: + bool busy; + + Event jobEvent; + std::queue jobs; + + CoreStat stat; + + void handleJob(); + void jobDone(); + + public: + Core(); + ~Core(); + + void submitJob(JobEntry, uint64_t = 0); + + void addStat(InstStat &); + + bool isBusy(); + uint64_t getJobListSize(); + CoreStat &getStat(); + }; + + ConfigReader &conf; + uint64_t lastResetStat; + + uint64_t clockSpeed; + uint64_t clockPeriod; + + // Cores + std::vector hilCore; + std::vector iclCore; + std::vector ftlCore; + + // CPIs + std::unordered_map> cpi; + + uint32_t leastBusyCPU(std::vector &); + void calculatePower(Power &); + + public: + CPU(ConfigReader &); + ~CPU(); + + void execute(NAMESPACE, FUNCTION, DMAFunction &, void * = nullptr, + uint64_t = 0); + uint64_t applyLatency(NAMESPACE, FUNCTION); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; + + void printLastStat(); +}; + +} // namespace CPU + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/def.hh b/hotness/SimpleSSD-Standalone/simplessd/cpu/def.hh new file mode 100644 index 0000000000..ad552cf16d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/def.hh @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __CPU_DEF__ +#define __CPU_DEF__ + +#include + +namespace SimpleSSD { + +namespace CPU { + +typedef enum : uint16_t { + FTL, + FTL__PAGE_MAPPING, + ICL, + ICL__GENERIC_CACHE, + HIL, + NVME__CONTROLLER, + NVME__PRPLIST, + NVME__SGL, + NVME__SUBSYSTEM, + NVME__NAMESPACE, + NVME__OCSSD, + UFS__DEVICE, + SATA__DEVICE, +} NAMESPACE; + +typedef enum : uint16_t { + // Common + READ, + WRITE, + FLUSH, + TRIM, + FORMAT, + + // FTL__PAGE_MAPPING + READ_INTERNAL, + WRITE_INTERNAL, + ERASE_INTERNAL, + TRIM_INTERNAL, + SELECT_VICTIM_BLOCK, + DO_GARBAGE_COLLECTION, + + // NVME__CONTROLLER / NVME__SUBSYSTEM + CREATE_CQ, + CREATE_SQ, + + // NVME__CONTROLLER + COLLECT_SQ, + HANDLE_REQUEST, + WORK, + COMPLETION, + + // NVME__PRPLIST + GET_PRPLIST_FROM_PRP, + + // NVME__SGL + PARSE_SGL_SEGMENT, + + // NVME__SUBSYSTEM / NVME__NAMESPACE + SUBMIT_COMMAND, + + // NVME__SUBSYSTEM + CONVERT_UNIT, + FORMAT_NVM, + + // NVME__NAMESPACE + DATASET_MANAGEMENT, + + // NVME__OCSSD + VECTOR_CHUNK_READ, + VECTOR_CHUNK_WRITE, + VECTOR_CHUNK_RESET, + PHYSICAL_PAGE_READ, + PHYSICAL_PAGE_WRITE, + PHYSICAL_BLOCK_ERASE, + + // UFS__DEVICE + PROCESS_QUERY_COMMAND, + PROCESS_COMMAND, + PRDT_READ, + PRDT_WRITE, + + // SATA__DEVICE + READ_DMA, + READ_NCQ, + READ_DMA_SETUP, + READ_DMA_DONE, + WRITE_DMA, + WRITE_NCQ, + WRITE_DMA_SETUP, + WRITE_DMA_DONE, +} FUNCTION; + +} // namespace CPU + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/analyse.py b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/analyse.py new file mode 100644 index 0000000000..571d14483f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/analyse.py @@ -0,0 +1,86 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +import re +from insts import aarch64 + +asmregex = re.compile('[0-9a-f ]+:\t[0-9a-f ]+\t([\w\.]+)') +endregex = re.compile('[0-9a-f]{16} <') + + +def decode(line): + match = asmregex.match(line) + + if match: + return match.group(1) + + return '' + + +def categorize(opstring): + for list in aarch64: + regex = re.compile(list[0], re.IGNORECASE) + match = regex.match(opstring) + + if match: + if match.group(0) == opstring: + return [True, list[1], list[2]] + + return [False, 1, 0] + + +def matchFunction(line, funcstr): + match = endregex.match(line) + + if match: + if line.find(funcstr) >= 0: + return 1 + else: + return 2 + else: + return 0 + + +def analyse(asmfile, funcname): + category = [0, 0, 0, 0, 0, 0] + funcstr = str(len(funcname)) + funcname + + with open(asmfile, 'r') as f: + collect = False + + for line in f: + if collect: + match = matchFunction(line, funcstr) + + if match > 0: + if match == 2: + collect = False + else: + op = decode(line) + + if len(op) > 0: + ret = categorize(op) + + if not ret[0]: + print('Unknown assembly ' + op + ' found') + + category[ret[2]] += ret[1] + else: + if matchFunction(line, funcstr) == 1: + collect = True + + return category diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/compile.py b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/compile.py new file mode 100644 index 0000000000..810608d680 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/compile.py @@ -0,0 +1,61 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +import subprocess +import os + + +def compile(cxx, src, dst, rootpath): + command = [cxx, + '-std=c++11', + '-O2', + '-g', + '-I' + rootpath, + '-I' + os.path.join(rootpath, '../../../../ext/drampower/src'), + '-I' + os.path.join(rootpath, '../lib/drampower/src'), + '-c', + src, + '-o', + dst] + + proc = subprocess.Popen( + command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + + output = proc.communicate()[0] + + if proc.returncode: + print output + + return proc.returncode + + +def disassemble(objdump, src, dst): + command = [objdump, + '-S', + '-d', + src] + + proc = subprocess.Popen( + command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + + output = proc.communicate()[0] + + if proc.returncode == 0: + with open(dst, 'w') as f: + f.write(output) + + return proc.returncode diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/functions.py b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/functions.py new file mode 100644 index 0000000000..37fdc788a3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/functions.py @@ -0,0 +1,158 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# [ Filename, Regex of function name, NS code, FCT code ] +# NAMESPACE code +# 0: FTL +# 1: FTL::PageMapping +# 2: ICL +# 3: ICL::GenericCache +# 4: HIL +# 5: HIL::NVMe::Controller +# 6: HIL::NVMe::PRPList +# 7: HIL::NVMe::SGL +# 8: HIL::NVMe::Subsystem +# 9: HIL::NVMe::Namespace +# 10: HIL::NVMe::OpenChannelSSD +# 11: HIL::UFS::Device +# 12: HIL::SATA::Device +# FUNCTION code +# 0: read +# 1: write +# 2: flush +# 3: trim +# 4: format +# 5: readInternal +# 6: writeInternal +# 7: eraseInternal +# 8: trimInternal +# 9: selectVictimBlock +# 10: doGarbageCollection +# 11: createCQ +# 12: createSQ +# 13: collectSQ +# 14: handleRequest +# 15: work +# 16: completion +# 17: getPRPListFromPRP +# 18: parseSGLSegment +# 19: submitCommand +# 20: convertUnit +# 21: formatNVM +# 22: datasetManagement +# 23: vectorChunkRead +# 24: vectorChunkWrite +# 25: vectorChunkReset +# 26: physicalPageRead +# 27: physicalPageWrite +# 28: physicalBlockErase +# 29: processQueryCommand +# 30: processCommand +# 31: prdtRead +# 32: prdtWrite +# 33: readDMA +# 34: readNCQ +# 35: readDMASetup +# 36: readDMADone +# 37: writeDMA +# 38: writeNCQ +# 39: writeDMASetup +# 40: writeDMADone +function = [ + ["ftl/ftl.cc", "read", 0, 0], + ["ftl/ftl.cc", "write", 0, 1], + ["ftl/ftl.cc", "trim", 0, 3], + ["ftl/ftl.cc", "format", 0, 4], + ["ftl/page_mapping.cc", "read", 1, 0], + ["ftl/page_mapping.cc", "write", 1, 1], + ["ftl/page_mapping.cc", "trim", 1, 3], + ["ftl/page_mapping.cc", "format", 1, 4], + ["ftl/page_mapping.cc", "selectVictimBlock", 1, 9], + ["ftl/page_mapping.cc", "doGarbageCollection", 1, 10], + ["ftl/page_mapping.cc", "readInternal", 1, 5], + ["ftl/page_mapping.cc", "writeInternal", 1, 6], + ["ftl/page_mapping.cc", "trimInternal", 1, 8], + ["ftl/page_mapping.cc", "eraseInternal", 1, 7], + ["icl/icl.cc", "read", 2, 0], + ["icl/icl.cc", "write", 2, 1], + ["icl/icl.cc", "flush", 2, 2], + ["icl/icl.cc", "trim", 2, 3], + ["icl/icl.cc", "format", 2, 4], + ["icl/generic_cache.cc", "read", 3, 0], + ["icl/generic_cache.cc", "write", 3, 1], + ["icl/generic_cache.cc", "flush", 3, 2], + ["icl/generic_cache.cc", "trim", 3, 3], + ["icl/generic_cache.cc", "format", 3, 4], + ["hil/hil.cc", "read", 4, 0], + ["hil/hil.cc", "write", 4, 1], + ["hil/hil.cc", "flush", 4, 2], + ["hil/nvme/controller.cc", "handleRequest", 5, 14], + ["hil/nvme/controller.cc", "collectSQ", 5, 13], + ["hil/nvme/controller.cc", "completion", 5, 16], + ["hil/nvme/controller.cc", "work", 5, 15], + ["hil/nvme/controller.cc", "createCQ", 5, 11], + ["hil/nvme/controller.cc", "createSQ", 5, 12], + ["hil/nvme/dma.cc", "getPRPListFromPRP", 6, 17], + ["hil/nvme/dma.cc", "read", 6, 0], + ["hil/nvme/dma.cc", "write", 6, 1], + ["hil/nvme/dma.cc", "parseSGLSegment", 7, 18], + ["hil/nvme/dma.cc", "read", 7, 0], + ["hil/nvme/dma.cc", "write", 7, 1], + ["hil/nvme/subsystem.cc", "submitCommand", 8, 19], + ["hil/nvme/subsystem.cc", "convertUnit", 8, 20], + ["hil/nvme/subsystem.cc", "formatNVM", 8, 21], + ["hil/nvme/namespace.cc", "submitCommand", 9, 19], + ["hil/nvme/namespace.cc", "read", 9, 0], + ["hil/nvme/namespace.cc", "write", 9, 1], + ["hil/nvme/namespace.cc", "flush", 9, 2], + ["hil/nvme/namespace.cc", "datasetManagement", 9, 22], + ["hil/nvme/ocssd.cc", "submitCommand", 10, 19], + ["hil/nvme/ocssd.cc", "read", 10, 0], + ["hil/nvme/ocssd.cc", "write", 10, 1], + ["hil/nvme/ocssd.cc", "datasetManagement", 10, 22], + ["hil/nvme/ocssd.cc", "readInternal", 10, 5], + ["hil/nvme/ocssd.cc", "writeInternal", 10, 6], + ["hil/nvme/ocssd.cc", "eraseInternal", 10, 7], + ["hil/nvme/ocssd.cc", "convertUnit", 10, 20], + ["hil/nvme/ocssd.cc", "vectorChunkRead", 10, 23], + ["hil/nvme/ocssd.cc", "vectorChunkWrite", 10, 24], + ["hil/nvme/ocssd.cc", "vectorChunkReset", 10, 25], + ["hil/nvme/ocssd.cc", "physicalPageRead", 10, 26], + ["hil/nvme/ocssd.cc", "physicalPageWrite", 10, 27], + ["hil/nvme/ocssd.cc", "physicalBlockErase", 10, 28], + ["hil/ufs/device.cc", "processQueryCommand", 11, 29], + ["hil/ufs/device.cc", "processCommand", 11, 30], + ["hil/ufs/device.cc", "prdtRead", 11, 31], + ["hil/ufs/device.cc", "prdtWrite", 11, 32], + ["hil/ufs/device.cc", "read", 11, 0], + ["hil/ufs/device.cc", "write", 11, 1], + ["hil/ufs/device.cc", "flush", 11, 2], + ["hil/sata/device.cc", "submitCommand", 12, 19], + ["hil/sata/device.cc", "prdtRead", 12, 31], + ["hil/sata/device.cc", "prdtWrite", 12, 32], + ["hil/sata/device.cc", "read", 12, 0], + ["hil/sata/device.cc", "write", 12, 1], + ["hil/sata/device.cc", "flush", 12, 2], + ["hil/sata/device.cc", "readDMA", 12, 33], + ["hil/sata/device.cc", "readNCQ", 12, 34], + ["hil/sata/device.cc", "_readDMASetup", 12, 35], + ["hil/sata/device.cc", "_readDMADone", 12, 36], + ["hil/sata/device.cc", "writeDMA", 12, 37], + ["hil/sata/device.cc", "writeNCQ", 12, 38], + ["hil/sata/device.cc", "_writeDMASetup", 12, 39], + ["hil/sata/device.cc", "_writeDMADone", 12, 40], +] diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/generate.py b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/generate.py new file mode 100644 index 0000000000..dd6e776895 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/generate.py @@ -0,0 +1,125 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +import os +import shutil +from functions import function as funcList +from compile import compile, disassemble +from analyse import analyse + +# Begin of main +print('SimpleSSD Instruction Counter\n') + +# Find root directory of SimpleSSD +pwd = os.getcwd() +rootdir = '' + +while True: + if pwd == '/': + print('Failed to find SimpleSSD root directory') + exit(-1) + + if os.path.isdir(os.path.join(pwd, 'cpu')) and os.path.isdir(os.path.join(pwd, 'hil')): + rootdir = os.path.abspath(pwd) + break + + pwd = os.path.join(pwd, '..') + +print('SimpleSSD found on ' + rootdir) + +# Create temp directory +tempdir = os.path.join(rootdir, 'temp_build') + +if os.path.exists(tempdir): + shutil.rmtree(tempdir) + +os.mkdir(tempdir) + +if not os.path.isdir(tempdir): + print('Failed to create temp directory') + exit(-1) + +print('Temporary directory ' + tempdir + ' created') + +# Load files to compile & disassemble +result = [] +files = set() + +for func in funcList: + files.add(func[0]) + +files = list(files) + +# Compile all +print('Begin compile') + +for file in files: + path = os.path.join(rootdir, file) + filename = os.path.splitext(file.replace('/', '_'))[0] + '.o' + outfile = os.path.join(tempdir, filename) + + if os.path.exists(path): + ret = compile('aarch64-linux-gnu-g++', path, outfile, rootdir) + + if ret: + print(' file ' + file + ' failed to compile') + else: + print(' file ' + file + ' not exists') + +# Disassemble all +print('Begin disassemble') + +for file in files: + path = os.path.join(rootdir, file) + filename = os.path.splitext(file.replace('/', '_'))[0] + name = os.path.join(tempdir, filename) + objfile = name + '.o' + asmfile = name + '.asm' + + if os.path.exists(objfile): + ret = disassemble('aarch64-linux-gnu-objdump', objfile, asmfile) + + if ret: + print(' file ' + file + ' failed to disassemble') + +# Analyse all +print('Begin analysis') + +for func in funcList: + path = os.path.join(rootdir, func[0]) + filename = os.path.splitext(func[0].replace('/', '_'))[0] + '.asm' + asmfile = os.path.join(tempdir, filename) + + if os.path.exists(asmfile): + insts = analyse(asmfile, func[1]) + + result.append([func[1], func[2], func[3], insts]) + else: + print('Assembly file for function ' + func[1] + ' not exists') + +# Everything is done +# Print result +template = """cpi.find({1})->second.insert( + {{{2}, InstStat({4}, {5}, {6}, {7}, {8}, {3}, clockPeriod)}});""" + +for data in result: + print(template.format(data[0], data[1], data[2], + data[3][0], data[3][1], data[3][2], + data[3][3], data[3][4], data[3][5])) + +# Remove temp directory +shutil.rmtree(tempdir) diff --git a/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/insts.py b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/insts.py new file mode 100644 index 0000000000..40db8c98c8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/cpu/generator/insts.py @@ -0,0 +1,160 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# [ Regex of instruction, CPI, TYPE ] +# TYPE: +# 0: Others +# 1: Branch +# 2: Load +# 3: Store +# 4: Arithmetic +# 5: FP +aarch64 = [ + ["NOP", 1, 0], + ["CAS[B|H|P|]", 1, 0], + ["SWP[B|H|]", 1, 0], + # Branch + ["B\.(EQ|NE|CS|HS|CC|LO|MI|PL|VS|VC|HI|LS|GE|LT|GT|LE|AL|NV)", 1, 1], + ["CBN?Z", 1, 1], + ["TBN?Z", 1, 1], + ["B", 1, 1], + ["BL", 1, 1], + ["BLR", 2, 1], + ["BR", 1, 1], + ["RET", 1, 1], + # Load + ["LDR(B|SB|H|SH|SW|)", 4, 2], + ["LDUR(B|SB|H|SH|SW|)", 4, 2], + ["LDP(SW|)", 4, 2], + ["LDNP", 4, 2], + ["LDTR(B|SB|H|SH|SW|)", 4, 2], + ["LDXR(B|H|)", 4, 2], + ["LDXP", 4, 2], + ["LDAPR(B|H|)", 4, 2], + ["LDAR(B|H|)", 4, 2], + ["LDAXR(B|H|)", 4, 2], + ["LDAXP", 4, 2], + ["LDLAR(B|H|)", 4, 2], + # Store + ["STR(B|H|)", 1, 3], + ["STUR(B|H|)", 1, 3], + ["STP", 2, 3], + ["STNP", 2, 3], + ["STTR(B|H|)", 1, 3], + ["STXR(B|H|)", 1, 3], + ["STXP", 1, 3], + ["STLR(B|H|)", 1, 3], + ["STLXR(B|H|)", 1, 3], + ["STLXP", 1, 3], + ["STLLR(B|H|)", 1, 3], + # Arithmetic + ["ADD(S|)", 1, 4], + ["SUB(S|)", 1, 4], + ["CMP", 1, 4], + ["CMN", 1, 4], + ["AND(S|)", 1, 4], + ["EOR", 1, 4], + ["ORR", 1, 4], + ["TST", 1, 4], + ["MOV(Z|N|K|)", 1, 4], + ["ADR(P|)", 1, 4], + ["BFM", 2, 4], + ["SBFM", 2, 4], + ["UBFM", 2, 4], + ["BFC", 2, 4], + ["BFI", 2, 4], + ["BFXIL", 1, 4], + ["SBFIZ", 2, 4], + ["SBFX", 1, 4], + ["UBFIZ", 2, 4], + ["UBFX", 1, 4], + ["EXTR", 1, 4], + ["ASR(V|)", 1, 4], + ["LSL(V|)", 1, 4], + ["LSR(V|)", 1, 4], + ["ROR(V|)", 1, 4], + ["SXT(B|H|W|)", 2, 4], + ["UXT(B|H|)", 2, 4], + ["NEG(S|)", 1, 4], + ["ADC(S|)", 1, 4], + ["SBC(S|)", 1, 4], + ["NGC(S|)", 1, 4], + ["BIC(S|)", 1, 4], + ["EON", 1, 4], + ["MNV", 1, 4], + ["ORN", 1, 4], + # Multiply and Divide + ["MADD", 3, 4], + ["MSUB", 3, 4], + ["MNEG", 3, 4], + ["MUL", 3, 4], + ["SMADDL", 3, 4], + ["SMSUBL", 3, 4], + ["SMNEGL", 3, 4], + ["SMULL", 3, 4], + ["SMULH", 6, 4], + ["UMADDL", 3, 4], + ["UMSUBL", 3, 4], + ["UMNEGL", 3, 4], + ["UMULL", 3, 4], + ["UMULH", 6, 4], + ["SDIV", 20, 4], + ["UDIV", 20, 4], + # Bit operation + ["CLS", 1, 4], + ["CLZ", 1, 4], + ["RBIT", 1, 4], + ["REV(16|32|64|)", 1, 4], + # Conditional select + ["CSEL", 1, 4], + ["CSINC", 1, 4], + ["CSINV", 1, 4], + ["CSNEG", 1, 4], + ["CSET(M|)", 1, 4], + ["CINC", 1, 4], + ["CINV", 1, 4], + ["CNEG", 1, 4], + # Conditional comparison + ["CCMN", 1, 4], + ["CCMP", 1, 4], + # Floating Point + ["FMOV", 5, 5], + ["FCVT(XN|)", 5, 5], + ["FCVT(AS|AU|MS|MU|NS|NU|PS|PU|ZS|ZU)", 10, 5], + ["FJCVTZS", 1, 5], + ["SCVTF", 10, 5], + ["UCVTF", 10, 5], + ["FRINT(A|I|M|N|P|X|Z|)", 5, 5], + ["FMADD", 9, 5], + ["FMSUB", 9, 5], + ["FNMADD", 9, 5], + ["FNMSUB", 9, 5], + ["FABS", 3, 5], + ["FNEG", 3, 5], + ["FSQRT", 20, 5], + ["FADD", 5, 5], + ["FDIV", 20, 5], + ["FMUL", 6, 5], + ["FNMUL", 6, 5], + ["FSUB", 5, 5], + ["FMAX", 5, 5], + ["FMAXNM", 5, 5], + ["FMIN", 5, 5], + ["FMINNM", 5, 5], + ["FCMP(E|P|PE|)", 3, 5], + ["FCSEL", 3, 5], +] diff --git a/hotness/SimpleSSD-Standalone/simplessd/dram/abstract_dram.cc b/hotness/SimpleSSD-Standalone/simplessd/dram/abstract_dram.cc new file mode 100644 index 0000000000..1ef6db56e2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/dram/abstract_dram.cc @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "dram/abstract_dram.hh" + +#include + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace DRAM { + +AbstractDRAM::AbstractDRAM(ConfigReader &c) + : conf(c), totalEnergy(0.0), totalPower(0.0) { + pStructure = conf.getDRAMStructure(); + pTiming = conf.getDRAMTiming(); + pPower = conf.getDRAMPower(); + + convertMemspec(); + + dramPower = new libDRAMPower(spec, false); +} + +AbstractDRAM::~AbstractDRAM() { + delete dramPower; +} + +void AbstractDRAM::convertMemspec() { + // Calculate datarate + uint32_t burstCycle = DIVCEIL(pTiming->tBURST, pTiming->tCK); + uint8_t dataRate = pStructure->burstLength / burstCycle; + + if (dataRate != 1 && dataRate != 2 && dataRate != 4) { + panic("Invalid DRAM data rate: %d", dataRate); + } + + // gem5 src/mem/drampower.cc + spec.memArchSpec.burstLength = pStructure->burstLength; + spec.memArchSpec.nbrOfBanks = pStructure->bank; + spec.memArchSpec.nbrOfRanks = pStructure->rank; + spec.memArchSpec.dataRate = dataRate; + spec.memArchSpec.nbrOfColumns = 0; + spec.memArchSpec.nbrOfRows = 0; + spec.memArchSpec.width = pStructure->busWidth; + spec.memArchSpec.nbrOfBankGroups = 0; + spec.memArchSpec.dll = pStructure->useDLL; + spec.memArchSpec.twoVoltageDomains = pPower->pVDD[1] != 0.f; + spec.memArchSpec.termination = false; + + spec.memTimingSpec.RC = DIVCEIL(pTiming->tRAS + pTiming->tRP, pTiming->tCK); + spec.memTimingSpec.RCD = DIVCEIL(pTiming->tRCD, pTiming->tCK); + spec.memTimingSpec.RL = DIVCEIL(pTiming->tCL, pTiming->tCK); + spec.memTimingSpec.RP = DIVCEIL(pTiming->tRP, pTiming->tCK); + spec.memTimingSpec.RFC = DIVCEIL(pTiming->tRFC, pTiming->tCK); + spec.memTimingSpec.RAS = DIVCEIL(pTiming->tRAS, pTiming->tCK); + spec.memTimingSpec.WL = spec.memTimingSpec.RL - 1; + spec.memTimingSpec.DQSCK = 0; + spec.memTimingSpec.RTP = DIVCEIL(pTiming->tRTP, pTiming->tCK); + spec.memTimingSpec.WR = DIVCEIL(pTiming->tWR, pTiming->tCK); + spec.memTimingSpec.XP = DIVCEIL(pTiming->tXP, pTiming->tCK); + spec.memTimingSpec.XPDLL = DIVCEIL(pTiming->tXPDLL, pTiming->tCK); + spec.memTimingSpec.XS = DIVCEIL(pTiming->tXS, pTiming->tCK); + spec.memTimingSpec.XSDLL = DIVCEIL(pTiming->tXSDLL, pTiming->tCK); + spec.memTimingSpec.clkPeriod = pTiming->tCK / 1000.; + + if (spec.memTimingSpec.clkPeriod == 0) { + panic("Invalid DRAM clock period"); + } + + spec.memTimingSpec.clkMhz = (1 / spec.memTimingSpec.clkPeriod) * 1000.; + + spec.memPowerSpec.idd0 = pPower->pIDD0[0]; + spec.memPowerSpec.idd02 = pPower->pIDD0[1]; + spec.memPowerSpec.idd2p0 = pPower->pIDD2P0[0]; + spec.memPowerSpec.idd2p02 = pPower->pIDD2P0[1]; + spec.memPowerSpec.idd2p1 = pPower->pIDD2P1[0]; + spec.memPowerSpec.idd2p12 = pPower->pIDD2P1[1]; + spec.memPowerSpec.idd2n = pPower->pIDD2N[0]; + spec.memPowerSpec.idd2n2 = pPower->pIDD2N[1]; + spec.memPowerSpec.idd3p0 = pPower->pIDD3P0[0]; + spec.memPowerSpec.idd3p02 = pPower->pIDD3P0[1]; + spec.memPowerSpec.idd3p1 = pPower->pIDD3P1[0]; + spec.memPowerSpec.idd3p12 = pPower->pIDD3P1[1]; + spec.memPowerSpec.idd3n = pPower->pIDD3N[0]; + spec.memPowerSpec.idd3n2 = pPower->pIDD3N[1]; + spec.memPowerSpec.idd4r = pPower->pIDD4R[0]; + spec.memPowerSpec.idd4r2 = pPower->pIDD4R[1]; + spec.memPowerSpec.idd4w = pPower->pIDD4W[0]; + spec.memPowerSpec.idd4w2 = pPower->pIDD4W[1]; + spec.memPowerSpec.idd5 = pPower->pIDD5[0]; + spec.memPowerSpec.idd52 = pPower->pIDD5[1]; + spec.memPowerSpec.idd6 = pPower->pIDD6[0]; + spec.memPowerSpec.idd62 = pPower->pIDD6[1]; + spec.memPowerSpec.vdd = pPower->pVDD[0]; + spec.memPowerSpec.vdd2 = pPower->pVDD[1]; +} + +void AbstractDRAM::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "energy"; + temp.desc = "Total energy comsumed by embedded DRAM (pJ)"; + list.push_back(temp); + + temp.name = prefix + "power"; + temp.desc = "Total power comsumed by embedded DRAM (mW)"; + list.push_back(temp); +} + +void AbstractDRAM::getStatValues(std::vector &values) { + values.push_back(totalEnergy); + values.push_back(totalPower); +} + +void AbstractDRAM::resetStatValues() { + // calcWindowEnergy clears old data + dramPower->calcWindowEnergy(getTick() / pTiming->tCK); + + totalEnergy = 0.0; + totalPower = 0.0; +} + +} // namespace DRAM + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/dram/abstract_dram.hh b/hotness/SimpleSSD-Standalone/simplessd/dram/abstract_dram.hh new file mode 100644 index 0000000000..0bec5b5ecb --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/dram/abstract_dram.hh @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __DRAM_ABSTRACT_DRAM__ +#define __DRAM_ABSTRACT_DRAM__ + +#include + +#include "libdrampower/LibDRAMPower.h" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace DRAM { + +typedef enum : uint8_t { + ACTIVE, //!< Row active + IDLE, //!< Precharged + POWER_DOWN_PRECHARGE, //!< Precharge power down + POWER_DOWN_ACTIVE, //!< Active power down + SELF_REFRESH, //!< Self refresh +} DRAMState; + +class AbstractDRAM : public StatObject { + protected: + ConfigReader &conf; + + Config::DRAMStructure *pStructure; + Config::DRAMTiming *pTiming; + Config::DRAMPower *pPower; + + Data::MemorySpecification spec; + libDRAMPower *dramPower; + + void convertMemspec(); + + double totalEnergy; // Unit: pJ + double totalPower; // Unit: mW + + public: + AbstractDRAM(ConfigReader &); + virtual ~AbstractDRAM(); + + virtual void read(void *, uint64_t, uint64_t &) = 0; + virtual void write(void *, uint64_t, uint64_t &) = 0; + + // TEMP: Should be removed on v2.2 + virtual void setScheduling(bool) {} + virtual bool isScheduling() { return true; } + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace DRAM + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/dram/config.cc b/hotness/SimpleSSD-Standalone/simplessd/dram/config.cc new file mode 100644 index 0000000000..6e10a0c422 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/dram/config.cc @@ -0,0 +1,345 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "dram/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace DRAM { + +const char NAME_DRAM_MODEL[] = "Model"; +const char NAME_DRAM_STRUCTURE_CHANNEL[] = "Channel"; +const char NAME_DRAM_STRUCTURE_RANK[] = "Rank"; +const char NAME_DRAM_STRUCTURE_BANK[] = "Bank"; +const char NAME_DRAM_STRUCTURE_CHIP[] = "Chip"; +const char NAME_DRAM_STRUCTURE_BUS_WIDTH[] = "BusWidth"; +const char NAME_DRAM_STRUCTURE_BURST_LENGTH[] = "BurstLength"; +const char NAME_DRAM_STRUCTURE_CHIP_SIZE[] = "ChipSize"; +const char NAME_DRAM_STRUCTURE_PAGE_SIZE[] = "PageSize"; +const char NAME_DRAM_TIMING_CK[] = "tCK"; +const char NAME_DRAM_TIMING_RCD[] = "tRCD"; +const char NAME_DRAM_TIMING_CL[] = "tCL"; +const char NAME_DRAM_TIMING_RP[] = "tRP"; +const char NAME_DRAM_TIMING_RAS[] = "tRAS"; +const char NAME_DRAM_TIMING_WR[] = "tWR"; +const char NAME_DRAM_TIMING_RTP[] = "tRTP"; +const char NAME_DRAM_TIMING_BURST[] = "tBURST"; +const char NAME_DRAM_TIMING_CCD_L[] = "tCCD_L"; +const char NAME_DRAM_TIMING_RFC[] = "tRFC"; +const char NAME_DRAM_TIMING_REFI[] = "tREFI"; +const char NAME_DRAM_TIMING_WTR[] = "tWTR"; +const char NAME_DRAM_TIMING_RTW[] = "tRTW"; +const char NAME_DRAM_TIMING_CS[] = "tCS"; +const char NAME_DRAM_TIMING_RRD[] = "tRRD"; +const char NAME_DRAM_TIMING_RRD_L[] = "tRRD_L"; +const char NAME_DRAM_TIMING_XAW[] = "tXAW"; +const char NAME_DRAM_TIMING_XP[] = "tXP"; +const char NAME_DRAM_TIMING_XPDLL[] = "tXPDLL"; +const char NAME_DRAM_TIMING_XS[] = "tXS"; +const char NAME_DRAM_TIMING_XSDLL[] = "tXSDLL"; +const char NAME_DRAM_POWER_IDD0_0[] = "IDD0_0"; +const char NAME_DRAM_POWER_IDD0_1[] = "IDD0_1"; +const char NAME_DRAM_POWER_IDD2P0_0[] = "IDD2P0_0"; +const char NAME_DRAM_POWER_IDD2P0_1[] = "IDD2P0_1"; +const char NAME_DRAM_POWER_IDD2P1_0[] = "IDD2P1_0"; +const char NAME_DRAM_POWER_IDD2P1_1[] = "IDD2P1_1"; +const char NAME_DRAM_POWER_IDD2N_0[] = "IDD2N_0"; +const char NAME_DRAM_POWER_IDD2N_1[] = "IDD2N_1"; +const char NAME_DRAM_POWER_IDD3P0_0[] = "IDD3P0_0"; +const char NAME_DRAM_POWER_IDD3P0_1[] = "IDD3P0_1"; +const char NAME_DRAM_POWER_IDD3P1_0[] = "IDD3P1_0"; +const char NAME_DRAM_POWER_IDD3P1_1[] = "IDD3P1_1"; +const char NAME_DRAM_POWER_IDD3N_0[] = "IDD3N_0"; +const char NAME_DRAM_POWER_IDD3N_1[] = "IDD3N_1"; +const char NAME_DRAM_POWER_IDD4R_0[] = "IDD4R_0"; +const char NAME_DRAM_POWER_IDD4R_1[] = "IDD4R_1"; +const char NAME_DRAM_POWER_IDD4W_0[] = "IDD4W_0"; +const char NAME_DRAM_POWER_IDD4W_1[] = "IDD4W_1"; +const char NAME_DRAM_POWER_IDD5_0[] = "IDD5_0"; +const char NAME_DRAM_POWER_IDD5_1[] = "IDD5_1"; +const char NAME_DRAM_POWER_IDD6_0[] = "IDD6_0"; +const char NAME_DRAM_POWER_IDD6_1[] = "IDD6_1"; +const char NAME_DRAM_POWER_VDD_0[] = "VDD_0"; +const char NAME_DRAM_POWER_VDD_1[] = "VDD_1"; + +Config::Config() { + model = SIMPLE_MODEL; + + /* LPDDR3-1600 4Gbit 1x32 */ + dram.channel = 1; + dram.rank = 1; + dram.bank = 8; + dram.chip = 1; + dram.chipSize = 536870912; + dram.busWidth = 32; + dram.burstLength = 8; + dram.activationLimit = 4; + dram.useDLL = false; + dram.pageSize = 4096; + + dramTiming.tCK = 1250; + dramTiming.tRCD = 18000; + dramTiming.tCL = 15000; + dramTiming.tRP = 18000; + dramTiming.tRAS = 42000; + dramTiming.tWR = 15000; + dramTiming.tRTP = 7500; + dramTiming.tBURST = 5000; + dramTiming.tCCD_L = 0; + dramTiming.tRFC = 130000; + dramTiming.tREFI = 3900; + dramTiming.tWTR = 7500; + dramTiming.tRTW = 2500; + dramTiming.tCS = 2500; + dramTiming.tRRD = 10000; + dramTiming.tRRD_L = 0; + dramTiming.tXAW = 50000; + dramTiming.tXP = 0; + dramTiming.tXPDLL = 0; + dramTiming.tXS = 0; + dramTiming.tXSDLL = 0; + + dramPower.pIDD0[0] = 8.f; + dramPower.pIDD0[1] = 60.f; + dramPower.pIDD2P0[0] = 0.f; + dramPower.pIDD2P0[1] = 0.f; + dramPower.pIDD2P1[0] = 0.8f; + dramPower.pIDD2P1[1] = 1.8f; + dramPower.pIDD2N[0] = 0.8f; + dramPower.pIDD2N[1] = 26.f; + dramPower.pIDD3P0[0] = 0.f; + dramPower.pIDD3P0[1] = 0.f; + dramPower.pIDD3P1[0] = 1.4f; + dramPower.pIDD3P1[1] = 11.f; + dramPower.pIDD3N[0] = 2.f; + dramPower.pIDD3N[1] = 34.f; + dramPower.pIDD4R[0] = 2.f; + dramPower.pIDD4R[1] = 230.f; + dramPower.pIDD4W[0] = 2.f; + dramPower.pIDD4W[1] = 190.f; + dramPower.pIDD5[0] = 28.f; + dramPower.pIDD5[1] = 150.f; + dramPower.pIDD6[0] = 0.5f; + dramPower.pIDD6[1] = 1.8f; + dramPower.pVDD[0] = 1.8f; + dramPower.pVDD[1] = 1.2f; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_DRAM_MODEL)) { + model = (MODEL)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_CHANNEL)) { + dram.channel = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_RANK)) { + dram.rank = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_BANK)) { + dram.bank = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_CHIP)) { + dram.chip = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_BUS_WIDTH)) { + dram.busWidth = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_BURST_LENGTH)) { + dram.burstLength = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_CHIP_SIZE)) { + dram.chipSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_STRUCTURE_PAGE_SIZE)) { + dram.pageSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CK)) { + dramTiming.tCK = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RCD)) { + dramTiming.tRCD = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CL)) { + dramTiming.tCL = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RP)) { + dramTiming.tRP = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RAS)) { + dramTiming.tRAS = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_WR)) { + dramTiming.tWR = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RTP)) { + dramTiming.tRTP = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_BURST)) { + dramTiming.tBURST = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CCD_L)) { + dramTiming.tCCD_L = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RFC)) { + dramTiming.tRFC = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_REFI)) { + dramTiming.tREFI = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_WTR)) { + dramTiming.tWTR = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RTW)) { + dramTiming.tRTW = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_CS)) { + dramTiming.tCS = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RRD)) { + dramTiming.tRRD = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_RRD_L)) { + dramTiming.tRRD_L = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XAW)) { + dramTiming.tXAW = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XP)) { + dramTiming.tXP = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XPDLL)) { + dramTiming.tXPDLL = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XS)) { + dramTiming.tXS = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_TIMING_XSDLL)) { + dramTiming.tXSDLL = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD0_0)) { + dramPower.pIDD0[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD0_1)) { + dramPower.pIDD0[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P0_0)) { + dramPower.pIDD2P0[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P0_1)) { + dramPower.pIDD2P0[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P1_0)) { + dramPower.pIDD2P1[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2P1_1)) { + dramPower.pIDD2P1[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2N_0)) { + dramPower.pIDD2N[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD2N_1)) { + dramPower.pIDD2N[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P0_0)) { + dramPower.pIDD3P0[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P0_1)) { + dramPower.pIDD3P0[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P1_0)) { + dramPower.pIDD3P1[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3P1_1)) { + dramPower.pIDD3P1[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3N_0)) { + dramPower.pIDD3N[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD3N_1)) { + dramPower.pIDD3N[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4R_0)) { + dramPower.pIDD4R[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4R_1)) { + dramPower.pIDD4R[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4W_0)) { + dramPower.pIDD4W[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD4W_1)) { + dramPower.pIDD4W[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD5_0)) { + dramPower.pIDD5[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD5_1)) { + dramPower.pIDD5[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD6_0)) { + dramPower.pIDD6[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_IDD6_1)) { + dramPower.pIDD6[1] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_VDD_0)) { + dramPower.pVDD[0] = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_DRAM_POWER_VDD_1)) { + dramPower.pVDD[1] = strtof(value, nullptr); + } + else { + ret = false; + } + + return ret; +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case DRAM_MODEL: + ret = model; + break; + } + + return ret; +} + +Config::DRAMStructure *Config::getDRAMStructure() { + return &dram; +} + +Config::DRAMTiming *Config::getDRAMTiming() { + return &dramTiming; +} + +Config::DRAMPower *Config::getDRAMPower() { + return &dramPower; +} + +} // namespace DRAM + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/dram/config.hh b/hotness/SimpleSSD-Standalone/simplessd/dram/config.hh new file mode 100644 index 0000000000..9aa655ea8f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/dram/config.hh @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __DRAM_CONFIG__ +#define __DRAM_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace DRAM { + +typedef enum { + DRAM_MODEL, +} DRAM_CONFIG; + +typedef enum { + SIMPLE_MODEL, +} MODEL; + +class Config : public BaseConfig { + public: + typedef struct { + uint32_t channel; //!< # of channel + uint32_t rank; //!< Rank / Channel + uint32_t bank; //!< Bank / Rank + uint32_t chip; //!< Chips / Rank + uint32_t busWidth; //!< Bus / Chip + uint32_t burstLength; + uint32_t activationLimit; + bool useDLL; + uint64_t chipSize; + uint64_t pageSize; + } DRAMStructure; + + typedef struct { // Unit: ps + uint32_t tCK; //!< Clock period + uint32_t tRCD; //!< RAS to CAS delay + uint32_t tCL; //!< CAS latency + uint32_t tRP; //!< Row precharge time + uint32_t tRAS; //!< ACT to PRE delay + uint32_t tWR; //!< Write recovery time + uint32_t tRTP; //!< Read to precharge delay + uint32_t tBURST; //!< Burst duration + uint32_t tCCD_L; //!< Same bank group CAS to CAS delay + uint32_t tRFC; //!< Refresh cycle time + uint32_t tREFI; //!< Refresh command interval + uint32_t tWTR; //!< Write to read, same rank switching time + uint32_t tRTW; //!< Read to write, same rank switching time + uint32_t tCS; //!< Rank to rank switching time + uint32_t tRRD; //!< ACT to ACT delay + uint32_t tRRD_L; //!< Same bank group RRD + uint32_t tXAW; //!< X activation window + uint32_t tXP; //!< Power-up delay + uint32_t tXPDLL; //!< Power-up delay with locked DLL + uint32_t tXS; //!< Self-refresh exit latency + uint32_t tXSDLL; //!< Self-refresh exit latency DLL + } DRAMTiming; + + typedef struct { // Unit: mA + float pIDD0[2]; //!< Active precharge current + float pIDD2P0[2]; //!< Precharge powerdown slow + float pIDD2P1[2]; //!< Precharge powerdown fast + float pIDD2N[2]; //!< Precharge standby current + float pIDD3P0[2]; //!< Active powerdown slow + float pIDD3P1[2]; //!< Active powerdown fast + float pIDD3N[2]; //!< Active standby current + float pIDD4R[2]; //!< READ current + float pIDD4W[2]; //!< WRITE current + float pIDD5[2]; //!< Refresh current + float pIDD6[2]; //!< Self-refresh current + float pVDD[2]; //!< Main voltage (Unit: V) + } DRAMPower; + + private: + MODEL model; + + DRAMStructure dram; + DRAMTiming dramTiming; + DRAMPower dramPower; + + public: + Config(); + + bool setConfig(const char *, const char *) override; + + int64_t readInt(uint32_t) override; + + DRAMStructure *getDRAMStructure(); + DRAMTiming *getDRAMTiming(); + DRAMPower *getDRAMPower(); +}; + +} // namespace DRAM + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/dram/simple.cc b/hotness/SimpleSSD-Standalone/simplessd/dram/simple.cc new file mode 100644 index 0000000000..9db42ba643 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/dram/simple.cc @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "dram/simple.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace DRAM { + +#define REFRESH_PERIOD 64000000000 + +SimpleDRAM::Stat::Stat() : count(0), size(0) {} + +SimpleDRAM::SimpleDRAM(ConfigReader &p) + : AbstractDRAM(p), lastDRAMAccess(0), ignoreScheduling(false) { + pageFetchLatency = pTiming->tRP + pTiming->tRAS; + interfaceBandwidth = 2.0 * pStructure->busWidth * pStructure->chip * + pStructure->channel / 8.0 / pTiming->tCK; + + autoRefresh = allocate([this](uint64_t now) { + dramPower->doCommand(Data::MemCommand::REF, 0, now / pTiming->tCK); + + lastDRAMAccess = MAX(lastDRAMAccess, now + pTiming->tRFC); + + schedule(autoRefresh, now + REFRESH_PERIOD); + }); + + schedule(autoRefresh, getTick() + REFRESH_PERIOD); +} + +SimpleDRAM::~SimpleDRAM() { + // DO NOTHING +} + +uint64_t SimpleDRAM::updateDelay(uint64_t latency, uint64_t &tick) { + uint64_t beginAt = tick; + + if (tick > 0) { + if (ignoreScheduling) { + tick += latency; + } + else { + if (lastDRAMAccess <= tick) { + lastDRAMAccess = tick + latency; + } + else { + beginAt = lastDRAMAccess; + lastDRAMAccess += latency; + } + + tick = lastDRAMAccess; + } + } + + return beginAt; +} + +void SimpleDRAM::updateStats(uint64_t cycle) { + dramPower->calcWindowEnergy(cycle); + + auto &energy = dramPower->getEnergy(); + auto &power = dramPower->getPower(); + + totalEnergy += energy.window_energy; + totalPower = power.average_power; +} + +void SimpleDRAM::setScheduling(bool enable) { + ignoreScheduling = !enable; +} + +bool SimpleDRAM::isScheduling() { + return !ignoreScheduling; +} + +void SimpleDRAM::read(void *, uint64_t size, uint64_t &tick) { + uint64_t pageCount = (size > 0) ? (size - 1) / pStructure->pageSize + 1 : 0; + uint64_t latency = + (uint64_t)(pageCount * (pageFetchLatency + + pStructure->pageSize / interfaceBandwidth)); + + uint64_t beginAt = updateDelay(latency, tick); + + // DRAMPower uses cycle unit + beginAt /= pTiming->tCK; + + dramPower->doCommand(Data::MemCommand::ACT, 0, beginAt); + + for (uint64_t i = 0; i < pageCount; i++) { + dramPower->doCommand(Data::MemCommand::RD, 0, + beginAt + spec.memTimingSpec.RCD); + + beginAt += spec.memTimingSpec.RCD; + } + + beginAt -= spec.memTimingSpec.RCD; + + dramPower->doCommand(Data::MemCommand::PRE, 0, + beginAt + spec.memTimingSpec.RAS); + + // Stat Update + updateStats(beginAt + spec.memTimingSpec.RAS + spec.memTimingSpec.RP); + readStat.count++; + readStat.size += size; +} + +void SimpleDRAM::write(void *, uint64_t size, uint64_t &tick) { + uint64_t pageCount = (size > 0) ? (size - 1) / pStructure->pageSize + 1 : 0; + uint64_t latency = + (uint64_t)(pageCount * (pageFetchLatency + + pStructure->pageSize / interfaceBandwidth)); + + uint64_t beginAt = updateDelay(latency, tick); + + // DRAMPower uses cycle unit + beginAt /= pTiming->tCK; + + dramPower->doCommand(Data::MemCommand::ACT, 0, beginAt); + + for (uint64_t i = 0; i < pageCount; i++) { + dramPower->doCommand(Data::MemCommand::WR, 0, + beginAt + spec.memTimingSpec.RCD); + + beginAt += spec.memTimingSpec.RCD; + } + + beginAt -= spec.memTimingSpec.RCD; + + dramPower->doCommand(Data::MemCommand::PRE, 0, + beginAt + spec.memTimingSpec.RAS); + + // Stat Update + updateStats(beginAt + spec.memTimingSpec.RAS + spec.memTimingSpec.RP); + writeStat.count++; + writeStat.size += size; +} + +void SimpleDRAM::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + AbstractDRAM::getStatList(list, prefix); + + temp.name = prefix + "read.request_count"; + temp.desc = "Read request count"; + list.push_back(temp); + + temp.name = prefix + "read.bytes"; + temp.desc = "Read data size in byte"; + list.push_back(temp); + + temp.name = prefix + "write.request_count"; + temp.desc = "Write request count"; + list.push_back(temp); + + temp.name = prefix + "write.bytes"; + temp.desc = "Write data size in byte"; + list.push_back(temp); + + temp.name = prefix + "request_count"; + temp.desc = "Total request count"; + list.push_back(temp); + + temp.name = prefix + "bytes"; + temp.desc = "Total data size in byte"; + list.push_back(temp); +} + +void SimpleDRAM::getStatValues(std::vector &values) { + AbstractDRAM::getStatValues(values); + + values.push_back(readStat.count); + values.push_back(readStat.size); + values.push_back(writeStat.count); + values.push_back(writeStat.size); + values.push_back(readStat.count + writeStat.count); + values.push_back(readStat.size + writeStat.size); +} + +void SimpleDRAM::resetStatValues() { + AbstractDRAM::resetStatValues(); + + readStat = Stat(); + writeStat = Stat(); +} + +} // namespace DRAM + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/dram/simple.hh b/hotness/SimpleSSD-Standalone/simplessd/dram/simple.hh new file mode 100644 index 0000000000..d1c19f0a06 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/dram/simple.hh @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __DRAM_SIMPLE__ +#define __DRAM_SIMPLE__ + +#include + +#include "dram/abstract_dram.hh" + +namespace SimpleSSD { + +namespace DRAM { + +class SimpleDRAM : public AbstractDRAM { + private: + struct Stat { + uint64_t count; + uint64_t size; + + Stat(); + }; + + uint64_t pageFetchLatency; + double interfaceBandwidth; + + uint64_t lastDRAMAccess; + bool ignoreScheduling; + + Event autoRefresh; + + Stat readStat; + Stat writeStat; + + uint64_t updateDelay(uint64_t, uint64_t &); + void updateStats(uint64_t); + + public: + SimpleDRAM(ConfigReader &p); + ~SimpleDRAM(); + + void read(void *, uint64_t, uint64_t &) override; + void write(void *, uint64_t, uint64_t &) override; + + void setScheduling(bool) override; + bool isScheduling() override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace DRAM + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/abstract_ftl.hh b/hotness/SimpleSSD-Standalone/simplessd/ftl/abstract_ftl.hh new file mode 100644 index 0000000000..bee59b8e28 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/abstract_ftl.hh @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_ABSTRACT_FTL__ +#define __FTL_ABSTRACT_FTL__ + +#include + +#include "ftl/ftl.hh" + +namespace SimpleSSD { + +namespace FTL { + +typedef struct _Status { + uint64_t totalLogicalPages; + uint64_t mappedLogicalPages; + uint64_t freePhysicalBlocks; +} Status; + +class AbstractFTL : public StatObject { + protected: + Parameter ¶m; + PAL::PAL *pPAL; + DRAM::AbstractDRAM *pDRAM; + Status status; + + public: + AbstractFTL(Parameter &p, PAL::PAL *l, DRAM::AbstractDRAM *d) + : param(p), pPAL(l), pDRAM(d) {} + virtual ~AbstractFTL() {} + + virtual bool initialize() = 0; + + virtual void read(Request &, uint64_t &) = 0; + virtual void write(Request &, uint64_t &) = 0; + virtual void trim(Request &, uint64_t &) = 0; + + virtual void format(LPNRange &, uint64_t &) = 0; + + virtual Status *getStatus(uint64_t, uint64_t) = 0; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/common/block.cc b/hotness/SimpleSSD-Standalone/simplessd/ftl/common/block.cc new file mode 100644 index 0000000000..d7be114032 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/common/block.cc @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/common/block.hh" + +#include +#include + +namespace SimpleSSD { + +namespace FTL { + +Block::Block(uint32_t blockIdx, uint32_t count, uint32_t ioUnit) + : idx(blockIdx), + pageCount(count), + ioUnitInPage(ioUnit), + pValidBits(nullptr), + pErasedBits(nullptr), + pLPNs(nullptr), + ppLPNs(nullptr), + lastAccessed(0), + eraseCount(0) { + if (ioUnitInPage == 1) { + pValidBits = new Bitset(pageCount); + pErasedBits = new Bitset(pageCount); + + pLPNs = (uint64_t *)calloc(pageCount, sizeof(uint64_t)); + } + else if (ioUnitInPage > 1) { + Bitset copy(ioUnitInPage); + + validBits = std::vector(pageCount, copy); + erasedBits = std::vector(pageCount, copy); + + ppLPNs = (uint64_t **)calloc(pageCount, sizeof(uint64_t *)); + + for (uint32_t i = 0; i < pageCount; i++) { + ppLPNs[i] = (uint64_t *)calloc(ioUnitInPage, sizeof(uint64_t)); + } + } + else { + panic("Invalid I/O unit in page"); + } + + // C-style allocation + pNextWritePageIndex = (uint32_t *)calloc(ioUnitInPage, sizeof(uint32_t)); + + erase(); + eraseCount = 0; +} + +Block::Block(const Block &old) + : Block(old.idx, old.pageCount, old.ioUnitInPage) { + if (ioUnitInPage == 1) { + *pValidBits = *old.pValidBits; + *pErasedBits = *old.pErasedBits; + + memcpy(pLPNs, old.pLPNs, pageCount * sizeof(uint64_t)); + } + else { + validBits = old.validBits; + erasedBits = old.erasedBits; + + for (uint32_t i = 0; i < pageCount; i++) { + memcpy(ppLPNs[i], old.ppLPNs[i], ioUnitInPage * sizeof(uint64_t)); + } + } + + memcpy(pNextWritePageIndex, old.pNextWritePageIndex, + ioUnitInPage * sizeof(uint32_t)); + + eraseCount = old.eraseCount; +} + +Block::Block(Block &&old) noexcept + : idx(std::move(old.idx)), + pageCount(std::move(old.pageCount)), + ioUnitInPage(std::move(old.ioUnitInPage)), + pNextWritePageIndex(std::move(old.pNextWritePageIndex)), + pValidBits(std::move(old.pValidBits)), + pErasedBits(std::move(old.pErasedBits)), + pLPNs(std::move(old.pLPNs)), + validBits(std::move(old.validBits)), + erasedBits(std::move(old.erasedBits)), + ppLPNs(std::move(old.ppLPNs)), + lastAccessed(std::move(old.lastAccessed)), + eraseCount(std::move(old.eraseCount)) { + // TODO Use std::exchange to set old value to null (C++14) + old.idx = 0; + old.pageCount = 0; + old.ioUnitInPage = 0; + old.pNextWritePageIndex = nullptr; + old.pValidBits = nullptr; + old.pErasedBits = nullptr; + old.pLPNs = nullptr; + old.ppLPNs = nullptr; + old.lastAccessed = 0; + old.eraseCount = 0; +} + +Block::~Block() { + free(pNextWritePageIndex); + free(pLPNs); + + delete pValidBits; + delete pErasedBits; + + if (ppLPNs) { + for (uint32_t i = 0; i < pageCount; i++) { + free(ppLPNs[i]); + } + + free(ppLPNs); + } + + pNextWritePageIndex = nullptr; + pLPNs = nullptr; + pValidBits = nullptr; + pErasedBits = nullptr; + ppLPNs = nullptr; +} + +Block &Block::operator=(const Block &rhs) { + if (this != &rhs) { + this->~Block(); + *this = Block(rhs); // Call copy constructor + } + + return *this; +} + +Block &Block::operator=(Block &&rhs) { + if (this != &rhs) { + this->~Block(); + + idx = std::move(rhs.idx); + pageCount = std::move(rhs.pageCount); + ioUnitInPage = std::move(rhs.ioUnitInPage); + pNextWritePageIndex = std::move(rhs.pNextWritePageIndex); + pValidBits = std::move(rhs.pValidBits); + pErasedBits = std::move(rhs.pErasedBits); + pLPNs = std::move(rhs.pLPNs); + validBits = std::move(rhs.validBits); + erasedBits = std::move(rhs.erasedBits); + ppLPNs = std::move(rhs.ppLPNs); + lastAccessed = std::move(rhs.lastAccessed); + eraseCount = std::move(rhs.eraseCount); + + rhs.pNextWritePageIndex = nullptr; + rhs.pValidBits = nullptr; + rhs.pErasedBits = nullptr; + rhs.pLPNs = nullptr; + rhs.ppLPNs = nullptr; + rhs.lastAccessed = 0; + rhs.eraseCount = 0; + } + + return *this; +} + +uint32_t Block::getBlockIndex() const { + return idx; +} + +uint64_t Block::getLastAccessedTime() { + return lastAccessed; +} + +uint32_t Block::getEraseCount() { + return eraseCount; +} + +uint32_t Block::getValidPageCount() { + uint32_t ret = 0; + + if (ioUnitInPage == 1) { + ret = pValidBits->count(); + } + else { + for (auto &iter : validBits) { + if (iter.any()) { + ret++; + } + } + } + + return ret; +} + +uint32_t Block::getValidPageCountRaw() { + uint32_t ret = 0; + + if (ioUnitInPage == 1) { + // Same as getValidPageCount() + ret = pValidBits->count(); + } + else { + for (auto &iter : validBits) { + ret += iter.count(); + } + } + + return ret; +} + +uint32_t Block::getDirtyPageCount() { + uint32_t ret = 0; + + if (ioUnitInPage == 1) { + ret = (~(*pValidBits | *pErasedBits)).count(); + } + else { + for (uint32_t i = 0; i < pageCount; i++) { + // Dirty: Valid(false), Erased(false) + if ((~(validBits.at(i) | erasedBits.at(i))).any()) { + ret++; + } + } + } + + return ret; +} + +uint32_t Block::getNextWritePageIndex() { + uint32_t idx = 0; + + for (uint32_t i = 0; i < ioUnitInPage; i++) { + if (idx < pNextWritePageIndex[i]) { + idx = pNextWritePageIndex[i]; + } + } + + return idx; +} + +uint32_t Block::getNextWritePageIndex(uint32_t idx) { + return pNextWritePageIndex[idx]; +} + +bool Block::getPageInfo(uint32_t pageIndex, std::vector &lpn, + Bitset &map) { + if (ioUnitInPage == 1 && map.size() == 1) { + map.set(); + lpn = std::vector(1, pLPNs[pageIndex]); + } + else if (map.size() == ioUnitInPage) { + map = validBits.at(pageIndex); + lpn = std::vector(ppLPNs[pageIndex], + ppLPNs[pageIndex] + ioUnitInPage); + } + else { + panic("I/O map size mismatch"); + } + + return map.any(); +} + +bool Block::read(uint32_t pageIndex, uint32_t idx, uint64_t tick) { + bool read = false; + + if (ioUnitInPage == 1 && idx == 0) { + read = pValidBits->test(pageIndex); + } + else if (idx < ioUnitInPage) { + read = validBits.at(pageIndex).test(idx); + } + else { + panic("I/O map size mismatch"); + } + + if (read) { + lastAccessed = tick; + } + + return read; +} + +bool Block::write(uint32_t pageIndex, uint64_t lpn, uint32_t idx, + uint64_t tick) { + bool write = false; + + if (ioUnitInPage == 1 && idx == 0) { + write = pErasedBits->test(pageIndex); + } + else if (idx < ioUnitInPage) { + write = erasedBits.at(pageIndex).test(idx); + } + else { + panic("I/O map size mismatch"); + } + + if (write) { + if (pageIndex < pNextWritePageIndex[idx]) { + panic("Write to block should sequential"); + } + + lastAccessed = tick; + + if (ioUnitInPage == 1) { + pErasedBits->reset(pageIndex); + pValidBits->set(pageIndex); + + pLPNs[pageIndex] = lpn; + } + else { + erasedBits.at(pageIndex).reset(idx); + validBits.at(pageIndex).set(idx); + + ppLPNs[pageIndex][idx] = lpn; + } + + pNextWritePageIndex[idx] = pageIndex + 1; + } + else { + panic("Write to non erased page"); + } + + return write; +} + +void Block::erase() { + if (ioUnitInPage == 1) { + pValidBits->reset(); + pErasedBits->set(); + } + else { + for (auto &iter : validBits) { + iter.reset(); + } + for (auto &iter : erasedBits) { + iter.set(); + } + } + + memset(pNextWritePageIndex, 0, sizeof(uint32_t) * ioUnitInPage); + + eraseCount++; +} + +void Block::invalidate(uint32_t pageIndex, uint32_t idx) { + if (ioUnitInPage == 1) { + pValidBits->reset(pageIndex); + } + else { + validBits.at(pageIndex).reset(idx); + } +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/common/block.hh b/hotness/SimpleSSD-Standalone/simplessd/ftl/common/block.hh new file mode 100644 index 0000000000..edceb4a155 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/common/block.hh @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_COMMON_BLOCK__ +#define __FTL_COMMON_BLOCK__ + +#include +#include + +#include "util/bitset.hh" + +namespace SimpleSSD { + +namespace FTL { + +class Block { + private: + uint32_t idx; + uint32_t pageCount; + uint32_t ioUnitInPage; + uint32_t *pNextWritePageIndex; + + // Following variables are used when ioUnitInPage == 1 + Bitset *pValidBits; + Bitset *pErasedBits; + uint64_t *pLPNs; + + // Following variables are used when ioUnitInPage > 1 + std::vector validBits; + std::vector erasedBits; + uint64_t **ppLPNs; + + uint64_t lastAccessed; + uint32_t eraseCount; + + public: + Block(uint32_t, uint32_t, uint32_t); + Block(const Block &); // Copy constructor + Block(Block &&) noexcept; // Move constructor + ~Block(); + + Block &operator=(const Block &); // Copy assignment + Block &operator=(Block &&); // Move assignment + + uint32_t getBlockIndex() const; + uint64_t getLastAccessedTime(); + uint32_t getEraseCount(); + uint32_t getValidPageCount(); + uint32_t getValidPageCountRaw(); + uint32_t getDirtyPageCount(); + uint32_t getNextWritePageIndex(); + uint32_t getNextWritePageIndex(uint32_t); + bool getPageInfo(uint32_t, std::vector &, Bitset &); + bool read(uint32_t, uint32_t, uint64_t); + bool write(uint32_t, uint64_t, uint32_t, uint64_t); + void erase(); + void invalidate(uint32_t, uint32_t); +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/config.cc b/hotness/SimpleSSD-Standalone/simplessd/ftl/config.cc new file mode 100644 index 0000000000..3db1048247 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/config.cc @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/config.hh" + +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace FTL { + +const char NAME_MAPPING_MODE[] = "MappingMode"; +const char NAME_OVERPROVISION_RATIO[] = "OverProvisioningRatio"; +const char NAME_GC_THRESHOLD[] = "GCThreshold"; +const char NAME_BAD_BLOCK_THRESHOLD[] = "EraseThreshold"; +const char NAME_FILLING_MODE[] = "FillingMode"; +const char NAME_FILL_RATIO[] = "FillRatio"; +const char NAME_INVALID_PAGE_RATIO[] = "InvalidPageRatio"; +const char NAME_GC_MODE[] = "GCMode"; +const char NAME_GC_RECLAIM_BLOCK[] = "GCReclaimBlocks"; +const char NAME_GC_RECLAIM_THRESHOLD[] = "GCReclaimThreshold"; +const char NAME_GC_EVICT_POLICY[] = "EvictPolicy"; +const char NAME_GC_D_CHOICE_PARAM[] = "DChoiceParam"; +const char NAME_USE_RANDOM_IO_TWEAK[] = "EnableRandomIOTweak"; + +Config::Config() { + mapping = PAGE_MAPPING; + overProvision = 0.25f; + gcThreshold = 0.05f; + badBlockThreshold = 100000; + fillingMode = FILLING_MODE_0; + fillingRatio = 0.f; + invalidRatio = 0.f; + reclaimBlock = 1; + reclaimThreshold = 0.1f; + gcMode = GC_MODE_0; + evictPolicy = POLICY_GREEDY; + dChoiceParam = 3; + randomIOTweak = true; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_MAPPING_MODE)) { + mapping = (MAPPING)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_OVERPROVISION_RATIO)) { + overProvision = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_GC_THRESHOLD)) { + gcThreshold = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_BAD_BLOCK_THRESHOLD)) { + badBlockThreshold = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FILLING_MODE)) { + fillingMode = (FILLING_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FILL_RATIO)) { + fillingRatio = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_INVALID_PAGE_RATIO)) { + invalidRatio = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_GC_MODE)) { + gcMode = (GC_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GC_RECLAIM_BLOCK)) { + reclaimBlock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GC_RECLAIM_THRESHOLD)) { + reclaimThreshold = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_GC_EVICT_POLICY)) { + evictPolicy = (EVICT_POLICY)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_GC_D_CHOICE_PARAM)) { + dChoiceParam = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_USE_RANDOM_IO_TWEAK)) { + randomIOTweak = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (gcMode == GC_MODE_0 && reclaimBlock == 0) { + panic("Invalid GCReclaimBlocks"); + } + + if (gcMode == GC_MODE_1 && reclaimThreshold < gcThreshold) { + panic("Invalid GCReclaimThreshold"); + } + + if (fillingRatio < 0.f || fillingRatio > 1.f) { + panic("Invalid FillingRatio"); + } + + if (invalidRatio < 0.f || invalidRatio > 1.f) { + panic("Invalid InvalidPageRatio"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case FTL_MAPPING_MODE: + ret = mapping; + break; + case FTL_GC_MODE: + ret = gcMode; + break; + case FTL_GC_EVICT_POLICY: + ret = evictPolicy; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case FTL_FILLING_MODE: + ret = fillingMode; + break; + case FTL_BAD_BLOCK_THRESHOLD: + ret = badBlockThreshold; + break; + case FTL_GC_RECLAIM_BLOCK: + ret = reclaimBlock; + break; + case FTL_GC_D_CHOICE_PARAM: + ret = dChoiceParam; + break; + } + + return ret; +} + +float Config::readFloat(uint32_t idx) { + float ret = 0.f; + + switch (idx) { + case FTL_OVERPROVISION_RATIO: + ret = overProvision; + break; + case FTL_GC_THRESHOLD_RATIO: + ret = gcThreshold; + break; + case FTL_FILL_RATIO: + ret = fillingRatio; + break; + case FTL_INVALID_PAGE_RATIO: + ret = invalidRatio; + break; + case FTL_GC_RECLAIM_THRESHOLD: + ret = reclaimThreshold; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case FTL_USE_RANDOM_IO_TWEAK: + ret = randomIOTweak; + break; + } + + return ret; +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/config.hh b/hotness/SimpleSSD-Standalone/simplessd/ftl/config.hh new file mode 100644 index 0000000000..e3e923f646 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/config.hh @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_CONFIG__ +#define __FTL_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace FTL { + +typedef enum { + /* Common FTL configuration */ + FTL_MAPPING_MODE, + FTL_OVERPROVISION_RATIO, + FTL_GC_THRESHOLD_RATIO, + FTL_BAD_BLOCK_THRESHOLD, + FTL_FILLING_MODE, + FTL_FILL_RATIO, + FTL_INVALID_PAGE_RATIO, + FTL_GC_MODE, + FTL_GC_RECLAIM_BLOCK, + FTL_GC_RECLAIM_THRESHOLD, + FTL_GC_EVICT_POLICY, + FTL_GC_D_CHOICE_PARAM, + FTL_USE_RANDOM_IO_TWEAK, + + /* N+K Mapping configuration*/ + FTL_NKMAP_N, + FTL_NKMAP_K, +} FTL_CONFIG; + +typedef enum { + PAGE_MAPPING, +} MAPPING; + +typedef enum { + GC_MODE_0, // Reclaim fixed number of blocks + GC_MODE_1, // Reclaim blocks until threshold +} GC_MODE; + +typedef enum { + FILLING_MODE_0, + FILLING_MODE_1, + FILLING_MODE_2, +} FILLING_MODE; + +typedef enum { + POLICY_GREEDY, // Select the block with the least valid pages + POLICY_COST_BENEFIT, + POLICY_RANDOM, // Select the block randomly + POLICY_DCHOICE, +} EVICT_POLICY; + +class Config : public BaseConfig { + private: + MAPPING mapping; //!< Default: PAGE_MAPPING + float overProvision; //!< Default: 0.25 (25%) + float gcThreshold; //!< Default: 0.05 (5%) + uint64_t badBlockThreshold; //!< Default: 100000 + FILLING_MODE fillingMode; //!< Default: FILLING_MODE_0 + float fillingRatio; //!< Default: 0.0 (0%) + float invalidRatio; //!< Default: 0.0 (0%) + uint64_t reclaimBlock; //!< Default: 1 + float reclaimThreshold; //!< Default: 0.1 (10%) + GC_MODE gcMode; //!< Default: FTL_GC_MODE_0 + EVICT_POLICY evictPolicy; //!< Default: POLICY_GREEDY + uint64_t dChoiceParam; //!< Default: 3 + bool randomIOTweak; //!< Default: true + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + float readFloat(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/ftl.cc b/hotness/SimpleSSD-Standalone/simplessd/ftl/ftl.cc new file mode 100644 index 0000000000..ae7176b3aa --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/ftl.cc @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/ftl.hh" + +#include "ftl/page_mapping_hotness.hh" + +namespace SimpleSSD { + +namespace FTL { + +FTL::FTL(ConfigReader &c, DRAM::AbstractDRAM *d) : conf(c), pDRAM(d) { + PAL::Parameter *palparam; + + pPAL = new PAL::PAL(conf); + palparam = pPAL->getInfo(); + + param.totalPhysicalBlocks = palparam->superBlock; + param.totalLogicalBlocks = + palparam->superBlock * + (1 - conf.readFloat(CONFIG_FTL, FTL_OVERPROVISION_RATIO)); + param.pagesInBlock = palparam->page; + param.pageSize = palparam->superPageSize; + param.ioUnitInPage = palparam->pageInSuperPage; + param.pageCountToMaxPerf = palparam->superBlock / palparam->block; + + switch (conf.readInt(CONFIG_FTL, FTL_MAPPING_MODE)) { + case PAGE_MAPPING: + pFTL = new PageMappingHotness(conf, param, pPAL, pDRAM); + break; + } + + if (param.totalPhysicalBlocks <= + param.totalLogicalBlocks + param.pageCountToMaxPerf) { + panic("FTL Over-Provision Ratio is too small"); + } + + // Print mapping Information + debugprint(LOG_FTL, "Total physical blocks %u", param.totalPhysicalBlocks); + debugprint(LOG_FTL, "Total logical blocks %u", param.totalLogicalBlocks); + debugprint(LOG_FTL, "Logical page size %u", param.pageSize); + + // Initialize pFTL + pFTL->initialize(); +} + +FTL::~FTL() { + delete pPAL; + delete pFTL; +} + +void FTL::read(Request &req, uint64_t &tick) { + debugprint(LOG_FTL, "READ | LPN %" PRIu64, req.lpn); + + pFTL->read(req, tick); + + tick += applyLatency(CPU::FTL, CPU::READ); +} + +void FTL::write(Request &req, uint64_t &tick) { + debugprint(LOG_FTL, "WRITE | LPN %" PRIu64, req.lpn); + + pFTL->write(req, tick); + + tick += applyLatency(CPU::FTL, CPU::WRITE); +} + +void FTL::trim(Request &req, uint64_t &tick) { + debugprint(LOG_FTL, "TRIM | LPN %" PRIu64, req.lpn); + + pFTL->trim(req, tick); + + tick += applyLatency(CPU::FTL, CPU::TRIM); +} + +void FTL::format(LPNRange &range, uint64_t &tick) { + pFTL->format(range, tick); + + tick += applyLatency(CPU::FTL, CPU::FORMAT); +} + +Parameter *FTL::getInfo() { + return ¶m; +} + +uint64_t FTL::getUsedPageCount(uint64_t lpnBegin, uint64_t lpnEnd) { + return pFTL->getStatus(lpnBegin, lpnEnd)->mappedLogicalPages; +} + +void FTL::getStatList(std::vector &list, std::string prefix) { + pFTL->getStatList(list, prefix + "ftl."); + pPAL->getStatList(list, prefix); +} + +void FTL::getStatValues(std::vector &values) { + pFTL->getStatValues(values); + pPAL->getStatValues(values); +} + +void FTL::resetStatValues() { + pFTL->resetStatValues(); + pPAL->resetStatValues(); +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/ftl.hh b/hotness/SimpleSSD-Standalone/simplessd/ftl/ftl.hh new file mode 100644 index 0000000000..c328dd5f5b --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/ftl.hh @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_FTL__ +#define __FTL_FTL__ + +#include "dram/abstract_dram.hh" +#include "pal/pal.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace FTL { + +class AbstractFTL; + +typedef struct { + uint64_t totalPhysicalBlocks; //!< (PAL::Parameter::superBlock) + uint64_t totalLogicalBlocks; + uint64_t pagesInBlock; //!< (PAL::Parameter::page) + uint32_t pageSize; //!< Mapping unit (PAL::Parameter::superPageSize) + uint32_t ioUnitInPage; //!< # smallest I/O unit in one page + uint32_t pageCountToMaxPerf; //!< # pages to fully utilize internal parallism +} Parameter; + +class FTL : public StatObject { + private: + Parameter param; + PAL::PAL *pPAL; + + ConfigReader &conf; + AbstractFTL *pFTL; + DRAM::AbstractDRAM *pDRAM; + + public: + FTL(ConfigReader &, DRAM::AbstractDRAM *); + ~FTL(); + + void read(Request &, uint64_t &); + void write(Request &, uint64_t &); + void trim(Request &, uint64_t &); + + void format(LPNRange &, uint64_t &); + + Parameter *getInfo(); + uint64_t getUsedPageCount(uint64_t, uint64_t); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping.cc b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping.cc new file mode 100644 index 0000000000..c6020c6c10 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping.cc @@ -0,0 +1,981 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "ftl/page_mapping.hh" + +#include +#include +#include + +#include "util/algorithm.hh" +#include "util/bitset.hh" + +namespace SimpleSSD { + +namespace FTL { + +PageMapping::PageMapping(ConfigReader &c, Parameter &p, PAL::PAL *l, + DRAM::AbstractDRAM *d) + : AbstractFTL(p, l, d), + pPAL(l), + conf(c), + lastFreeBlock(param.pageCountToMaxPerf), + lastFreeBlockIOMap(param.ioUnitInPage), + bReclaimMore(false) { + blocks.reserve(param.totalPhysicalBlocks); + table.reserve(param.totalLogicalBlocks * param.pagesInBlock); + + for (uint32_t i = 0; i < param.totalPhysicalBlocks; i++) { + freeBlocks.emplace_back(Block(i, param.pagesInBlock, param.ioUnitInPage)); + } + + nFreeBlocks = param.totalPhysicalBlocks; + + status.totalLogicalPages = param.totalLogicalBlocks * param.pagesInBlock; + + // Allocate free blocks + for (uint32_t i = 0; i < param.pageCountToMaxPerf; i++) { + lastFreeBlock.at(i) = getFreeBlock(i); + } + + lastFreeBlockIndex = 0; + + memset(&stat, 0, sizeof(stat)); + + bRandomTweak = conf.readBoolean(CONFIG_FTL, FTL_USE_RANDOM_IO_TWEAK); + bitsetSize = bRandomTweak ? param.ioUnitInPage : 1; +} + +PageMapping::~PageMapping() {} + +bool PageMapping::initialize() { + uint64_t nPagesToWarmup; + uint64_t nPagesToInvalidate; + uint64_t nTotalLogicalPages; + uint64_t maxPagesBeforeGC; + uint64_t tick; + uint64_t valid; + uint64_t invalid; + FILLING_MODE mode; + + Request req(param.ioUnitInPage); + + debugprint(LOG_FTL_PAGE_MAPPING, "Initialization started"); + + nTotalLogicalPages = param.totalLogicalBlocks * param.pagesInBlock; + nPagesToWarmup = + nTotalLogicalPages * conf.readFloat(CONFIG_FTL, FTL_FILL_RATIO); + nPagesToInvalidate = + nTotalLogicalPages * conf.readFloat(CONFIG_FTL, FTL_INVALID_PAGE_RATIO); + mode = (FILLING_MODE)conf.readUint(CONFIG_FTL, FTL_FILLING_MODE); + maxPagesBeforeGC = + param.pagesInBlock * + (param.totalPhysicalBlocks * + (1 - conf.readFloat(CONFIG_FTL, FTL_GC_THRESHOLD_RATIO)) - + param.pageCountToMaxPerf); // # free blocks to maintain + + if (nPagesToWarmup + nPagesToInvalidate > maxPagesBeforeGC) { + warn("ftl: Too high filling ratio. Adjusting invalidPageRatio."); + nPagesToInvalidate = maxPagesBeforeGC - nPagesToWarmup; + } + + debugprint(LOG_FTL_PAGE_MAPPING, "Total logical pages: %" PRIu64, + nTotalLogicalPages); + debugprint(LOG_FTL_PAGE_MAPPING, + "Total logical pages to fill: %" PRIu64 " (%.2f %%)", + nPagesToWarmup, nPagesToWarmup * 100.f / nTotalLogicalPages); + debugprint(LOG_FTL_PAGE_MAPPING, + "Total invalidated pages to create: %" PRIu64 " (%.2f %%)", + nPagesToInvalidate, + nPagesToInvalidate * 100.f / nTotalLogicalPages); + + req.ioFlag.set(); + + // Step 1. Filling + if (mode == FILLING_MODE_0 || mode == FILLING_MODE_1) { + // Sequential + for (uint64_t i = 0; i < nPagesToWarmup; i++) { + tick = 0; + req.lpn = i; + writeInternal(req, tick, false); + } + } + else { + // Random + std::random_device rd; + std::mt19937_64 gen(rd()); + std::uniform_int_distribution dist(0, nTotalLogicalPages - 1); + + for (uint64_t i = 0; i < nPagesToWarmup; i++) { + tick = 0; + req.lpn = dist(gen); + writeInternal(req, tick, false); + } + } + + // Step 2. Invalidating + if (mode == FILLING_MODE_0) { + // Sequential + for (uint64_t i = 0; i < nPagesToInvalidate; i++) { + tick = 0; + req.lpn = i; + writeInternal(req, tick, false); + } + } + else if (mode == FILLING_MODE_1) { + // Random + // We can successfully restrict range of LPN to create exact number of + // invalid pages because we wrote in sequential mannor in step 1. + std::random_device rd; + std::mt19937_64 gen(rd()); + std::uniform_int_distribution dist(0, nPagesToWarmup - 1); + + for (uint64_t i = 0; i < nPagesToInvalidate; i++) { + tick = 0; + req.lpn = dist(gen); + writeInternal(req, tick, false); + } + } + else { + // Random + std::random_device rd; + std::mt19937_64 gen(rd()); + std::uniform_int_distribution dist(0, nTotalLogicalPages - 1); + + for (uint64_t i = 0; i < nPagesToInvalidate; i++) { + tick = 0; + req.lpn = dist(gen); + writeInternal(req, tick, false); + } + } + + // Report + calculateTotalPages(valid, invalid); + debugprint(LOG_FTL_PAGE_MAPPING, "Filling finished. Page status:"); + debugprint(LOG_FTL_PAGE_MAPPING, + " Total valid physical pages: %" PRIu64 + " (%.2f %%, target: %" PRIu64 ", error: %" PRId64 ")", + valid, valid * 100.f / nTotalLogicalPages, nPagesToWarmup, + (int64_t)(valid - nPagesToWarmup)); + debugprint(LOG_FTL_PAGE_MAPPING, + " Total invalid physical pages: %" PRIu64 + " (%.2f %%, target: %" PRIu64 ", error: %" PRId64 ")", + invalid, invalid * 100.f / nTotalLogicalPages, nPagesToInvalidate, + (int64_t)(invalid - nPagesToInvalidate)); + debugprint(LOG_FTL_PAGE_MAPPING, "Initialization finished"); + + return true; +} + +void PageMapping::read(Request &req, uint64_t &tick) { + uint64_t begin = tick; + + if (req.ioFlag.count() > 0) { + readInternal(req, tick); + + debugprint(LOG_FTL_PAGE_MAPPING, + "READ | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + req.lpn, begin, tick, tick - begin); + } + else { + warn("FTL got empty request"); + } + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::READ); +} + +void PageMapping::write(Request &req, uint64_t &tick) { + uint64_t begin = tick; + + if (req.ioFlag.count() > 0) { + writeInternal(req, tick); + + debugprint(LOG_FTL_PAGE_MAPPING, + "WRITE | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + req.lpn, begin, tick, tick - begin); + } + else { + warn("FTL got empty request"); + } + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::WRITE); +} + +void PageMapping::trim(Request &req, uint64_t &tick) { + uint64_t begin = tick; + + trimInternal(req, tick); + + debugprint(LOG_FTL_PAGE_MAPPING, + "TRIM | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + req.lpn, begin, tick, tick - begin); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::TRIM); +} + +void PageMapping::format(LPNRange &range, uint64_t &tick) { + PAL::Request req(param.ioUnitInPage); + std::vector list; + + req.ioFlag.set(); + + for (auto iter = table.begin(); iter != table.end();) { + if (iter->first >= range.slpn && iter->first < range.slpn + range.nlp) { + auto &mappingList = iter->second; + + // Do trim + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + auto &mapping = mappingList.at(idx); + auto block = blocks.find(mapping.first); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + block->second.invalidate(mapping.second, idx); + + // Collect block indices + list.push_back(mapping.first); + } + + iter = table.erase(iter); + } + else { + iter++; + } + } + + // Get blocks to erase + std::sort(list.begin(), list.end()); + auto last = std::unique(list.begin(), list.end()); + list.erase(last, list.end()); + + // Do GC only in specified blocks + doGarbageCollection(list, tick); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::FORMAT); +} + +Status *PageMapping::getStatus(uint64_t lpnBegin, uint64_t lpnEnd) { + status.freePhysicalBlocks = nFreeBlocks; + + if (lpnBegin == 0 && lpnEnd >= status.totalLogicalPages) { + status.mappedLogicalPages = table.size(); + } + else { + status.mappedLogicalPages = 0; + + for (uint64_t lpn = lpnBegin; lpn < lpnEnd; lpn++) { + if (table.count(lpn) > 0) { + status.mappedLogicalPages++; + } + } + } + + return &status; +} + +float PageMapping::freeBlockRatio() { + return (float)nFreeBlocks / param.totalPhysicalBlocks; +} + +uint32_t PageMapping::convertBlockIdx(uint32_t blockIdx) { + return blockIdx % param.pageCountToMaxPerf; +} + +uint32_t PageMapping::getFreeBlock(uint32_t idx) { + uint32_t blockIndex = 0; + + if (idx >= param.pageCountToMaxPerf) { + panic("Index out of range"); + } + + if (nFreeBlocks > 0) { + // Search block which is blockIdx % param.pageCountToMaxPerf == idx + auto iter = freeBlocks.begin(); + + for (; iter != freeBlocks.end(); iter++) { + blockIndex = iter->getBlockIndex(); + + if (blockIndex % param.pageCountToMaxPerf == idx) { + break; + } + } + + // Sanity check + if (iter == freeBlocks.end()) { + // Just use first one + iter = freeBlocks.begin(); + blockIndex = iter->getBlockIndex(); + } + + // Insert found block to block list + if (blocks.find(blockIndex) != blocks.end()) { + panic("Corrupted"); + } + + blocks.emplace(blockIndex, std::move(*iter)); + + // Remove found block from free block list + freeBlocks.erase(iter); + nFreeBlocks--; + } + else { + panic("No free block left"); + } + + return blockIndex; +} + +uint32_t PageMapping::getLastFreeBlock(Bitset &iomap) { + if (!bRandomTweak || (lastFreeBlockIOMap & iomap).any()) { + // Update lastFreeBlockIndex + lastFreeBlockIndex++; + + if (lastFreeBlockIndex == param.pageCountToMaxPerf) { + lastFreeBlockIndex = 0; + } + + lastFreeBlockIOMap = iomap; + } + else { + lastFreeBlockIOMap |= iomap; + } + + auto freeBlock = blocks.find(lastFreeBlock.at(lastFreeBlockIndex)); + + // Sanity check + if (freeBlock == blocks.end()) { + panic("Corrupted"); + } + + // If current free block is full, get next block + if (freeBlock->second.getNextWritePageIndex() == param.pagesInBlock) { + lastFreeBlock.at(lastFreeBlockIndex) = getFreeBlock(lastFreeBlockIndex); + + bReclaimMore = true; + } + + return lastFreeBlock.at(lastFreeBlockIndex); +} + +// calculate weight of each block regarding victim selection policy +void PageMapping::calculateVictimWeight( + std::vector> &weight, const EVICT_POLICY policy, + uint64_t tick) { + float temp; + + weight.reserve(blocks.size()); + + switch (policy) { + case POLICY_GREEDY: + case POLICY_RANDOM: + case POLICY_DCHOICE: + for (auto &iter : blocks) { + if (iter.second.getNextWritePageIndex() != param.pagesInBlock) { + continue; + } + + weight.push_back({iter.first, iter.second.getValidPageCountRaw()}); + } + + break; + case POLICY_COST_BENEFIT: + for (auto &iter : blocks) { + if (iter.second.getNextWritePageIndex() != param.pagesInBlock) { + continue; + } + + temp = (float)(iter.second.getValidPageCountRaw()) / param.pagesInBlock; + + weight.push_back( + {iter.first, + temp / ((1 - temp) * (tick - iter.second.getLastAccessedTime()))}); + } + + break; + default: + panic("Invalid evict policy"); + } +} + +void PageMapping::selectVictimBlock(std::vector &list, + uint64_t &tick) { + static const GC_MODE mode = (GC_MODE)conf.readInt(CONFIG_FTL, FTL_GC_MODE); + static const EVICT_POLICY policy = + (EVICT_POLICY)conf.readInt(CONFIG_FTL, FTL_GC_EVICT_POLICY); + static uint32_t dChoiceParam = + conf.readUint(CONFIG_FTL, FTL_GC_D_CHOICE_PARAM); + uint64_t nBlocks = conf.readUint(CONFIG_FTL, FTL_GC_RECLAIM_BLOCK); + std::vector> weight; + + list.clear(); + + // Calculate number of blocks to reclaim + if (mode == GC_MODE_0) { + // DO NOTHING + } + else if (mode == GC_MODE_1) { + static const float t = conf.readFloat(CONFIG_FTL, FTL_GC_RECLAIM_THRESHOLD); + + nBlocks = param.totalPhysicalBlocks * t - nFreeBlocks; + } + else { + panic("Invalid GC mode"); + } + + // reclaim one more if last free block fully used + if (bReclaimMore) { + nBlocks += param.pageCountToMaxPerf; + + bReclaimMore = false; + } + + // Calculate weights of all blocks + calculateVictimWeight(weight, policy, tick); + + if (policy == POLICY_RANDOM || policy == POLICY_DCHOICE) { + uint64_t randomRange = + policy == POLICY_RANDOM ? nBlocks : dChoiceParam * nBlocks; + std::random_device rd; + std::mt19937 gen(rd()); + std::uniform_int_distribution dist(0, weight.size() - 1); + std::vector> selected; + + while (selected.size() < randomRange) { + uint64_t idx = dist(gen); + + if (weight.at(idx).first < std::numeric_limits::max()) { + selected.push_back(weight.at(idx)); + weight.at(idx).first = std::numeric_limits::max(); + } + } + + weight = std::move(selected); + } + + // Sort weights + std::sort( + weight.begin(), weight.end(), + [](std::pair a, std::pair b) -> bool { + return a.second < b.second; + }); + + // Select victims from the blocks with the lowest weight + nBlocks = MIN(nBlocks, weight.size()); + + for (uint64_t i = 0; i < nBlocks; i++) { + list.push_back(weight.at(i).first); + } + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::SELECT_VICTIM_BLOCK); +} + +void PageMapping::doGarbageCollection(std::vector &blocksToReclaim, + uint64_t &tick) { + PAL::Request req(param.ioUnitInPage); + std::vector readRequests; + std::vector writeRequests; + std::vector eraseRequests; + std::vector lpns; + Bitset bit(param.ioUnitInPage); + uint64_t beginAt = 0; + uint64_t readFinishedAt = tick; + uint64_t writeFinishedAt = tick; + uint64_t eraseFinishedAt = tick; + + if (blocksToReclaim.size() == 0) { + return; + } + + // For all blocks to reclaim, collecting request structure only + for (auto &iter : blocksToReclaim) { + auto block = blocks.find(iter); + + if (block == blocks.end()) { + panic("Invalid block"); + } + + // Copy valid pages to free block + for (uint32_t pageIndex = 0; pageIndex < param.pagesInBlock; pageIndex++) { + // Valid? + if (block->second.getPageInfo(pageIndex, lpns, bit)) { + if (!bRandomTweak) { + bit.set(); + } + + // Retrive free block + auto freeBlock = blocks.find(getLastFreeBlock(bit)); + + // Issue Read + req.blockIndex = block->first; + req.pageIndex = pageIndex; + req.ioFlag = bit; + + readRequests.push_back(req); + + // Update mapping table + uint32_t newBlockIdx = freeBlock->first; + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (bit.test(idx)) { + // Invalidate + block->second.invalidate(pageIndex, idx); + + auto mappingList = table.find(lpns.at(idx)); + + if (mappingList == table.end()) { + panic("Invalid mapping table entry"); + } + + pDRAM->read(&(*mappingList), 8 * param.ioUnitInPage, tick); + + auto &mapping = mappingList->second.at(idx); + + uint32_t newPageIdx = freeBlock->second.getNextWritePageIndex(idx); + + mapping.first = newBlockIdx; + mapping.second = newPageIdx; + + freeBlock->second.write(newPageIdx, lpns.at(idx), idx, beginAt); + + // Issue Write + req.blockIndex = newBlockIdx; + req.pageIndex = newPageIdx; + + if (bRandomTweak) { + req.ioFlag.reset(); + req.ioFlag.set(idx); + } + else { + req.ioFlag.set(); + } + + writeRequests.push_back(req); + + stat.validPageCopies++; + } + } + + stat.validSuperPageCopies++; + } + } + + // Erase block + req.blockIndex = block->first; + req.pageIndex = 0; + req.ioFlag.set(); + + eraseRequests.push_back(req); + } + + // Do actual I/O here + // This handles PAL2 limitation (SIGSEGV, infinite loop, or so-on) + for (auto &iter : readRequests) { + beginAt = tick; + + pPAL->read(iter, beginAt); + + readFinishedAt = MAX(readFinishedAt, beginAt); + } + + for (auto &iter : writeRequests) { + beginAt = readFinishedAt; + + pPAL->write(iter, beginAt); + + writeFinishedAt = MAX(writeFinishedAt, beginAt); + } + + for (auto &iter : eraseRequests) { + beginAt = readFinishedAt; + + eraseInternal(iter, beginAt); + + eraseFinishedAt = MAX(eraseFinishedAt, beginAt); + } + + tick = MAX(writeFinishedAt, eraseFinishedAt); + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::DO_GARBAGE_COLLECTION); +} + +void PageMapping::readInternal(Request &req, uint64_t &tick) { + PAL::Request palRequest(req); + uint64_t beginAt; + uint64_t finishedAt = tick; + + auto mappingList = table.find(req.lpn); + + if (mappingList != table.end()) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + } + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + auto &mapping = mappingList->second.at(idx); + + if (mapping.first < param.totalPhysicalBlocks && + mapping.second < param.pagesInBlock) { + palRequest.blockIndex = mapping.first; + palRequest.pageIndex = mapping.second; + + if (bRandomTweak) { + palRequest.ioFlag.reset(); + palRequest.ioFlag.set(idx); + } + else { + palRequest.ioFlag.set(); + } + + auto block = blocks.find(palRequest.blockIndex); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + beginAt = tick; + + block->second.read(palRequest.pageIndex, idx, beginAt); + pPAL->read(palRequest, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + } + } + + tick = finishedAt; + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::READ_INTERNAL); + } +} + +void PageMapping::writeInternal(Request &req, uint64_t &tick, bool sendToPAL) { + PAL::Request palRequest(req); + std::unordered_map::iterator block; + auto mappingList = table.find(req.lpn); + uint64_t beginAt; + uint64_t finishedAt = tick; + bool readBeforeWrite = false; + + if (mappingList != table.end()) { + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + auto &mapping = mappingList->second.at(idx); + + if (mapping.first < param.totalPhysicalBlocks && + mapping.second < param.pagesInBlock) { + block = blocks.find(mapping.first); + + // Invalidate current page + block->second.invalidate(mapping.second, idx); + } + } + } + } + else { + // Create empty mapping + auto ret = table.emplace( + req.lpn, + std::vector>( + bitsetSize, {param.totalPhysicalBlocks, param.pagesInBlock})); + + if (!ret.second) { + panic("Failed to insert new mapping"); + } + + mappingList = ret.first; + } + + // Write data to free block + block = blocks.find(getLastFreeBlock(req.ioFlag)); + + if (block == blocks.end()) { + panic("No such block"); + } + + if (sendToPAL) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + pDRAM->write(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + pDRAM->write(&(*mappingList), 8, tick); + } + } + + if (!bRandomTweak && !req.ioFlag.all()) { + // We have to read old data + readBeforeWrite = true; + } + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + uint32_t pageIndex = block->second.getNextWritePageIndex(idx); + auto &mapping = mappingList->second.at(idx); + + beginAt = tick; + + block->second.write(pageIndex, req.lpn, idx, beginAt); + + // Read old data if needed (Only executed when bRandomTweak = false) + // Maybe some other init procedures want to perform 'partial-write' + // So check sendToPAL variable + if (readBeforeWrite && sendToPAL) { + palRequest.blockIndex = mapping.first; + palRequest.pageIndex = mapping.second; + + // We don't need to read old data + palRequest.ioFlag = req.ioFlag; + palRequest.ioFlag.flip(); + + pPAL->read(palRequest, beginAt); + } + + // update mapping to table + mapping.first = block->first; + mapping.second = pageIndex; + + if (sendToPAL) { + palRequest.blockIndex = block->first; + palRequest.pageIndex = pageIndex; + + if (bRandomTweak) { + palRequest.ioFlag.reset(); + palRequest.ioFlag.set(idx); + } + else { + palRequest.ioFlag.set(); + } + + pPAL->write(palRequest, beginAt); + } + + finishedAt = MAX(finishedAt, beginAt); + } + } + + // Exclude CPU operation when initializing + if (sendToPAL) { + tick = finishedAt; + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::WRITE_INTERNAL); + } + + // GC if needed + // I assumed that init procedure never invokes GC + static float gcThreshold = conf.readFloat(CONFIG_FTL, FTL_GC_THRESHOLD_RATIO); + + if (freeBlockRatio() < gcThreshold) { + if (!sendToPAL) { + panic("ftl: GC triggered while in initialization"); + } + + std::vector list; + uint64_t beginAt = tick; + + selectVictimBlock(list, beginAt); + + debugprint(LOG_FTL_PAGE_MAPPING, + "GC | On-demand | %u blocks will be reclaimed", list.size()); + + doGarbageCollection(list, beginAt); + + debugprint(LOG_FTL_PAGE_MAPPING, + "GC | Done | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", tick, + beginAt, beginAt - tick); + + stat.gcCount++; + stat.reclaimedBlocks += list.size(); + } +} + +void PageMapping::trimInternal(Request &req, uint64_t &tick) { + auto mappingList = table.find(req.lpn); + + if (mappingList != table.end()) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + } + + // Do trim + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + auto &mapping = mappingList->second.at(idx); + auto block = blocks.find(mapping.first); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + block->second.invalidate(mapping.second, idx); + } + + // Remove mapping + table.erase(mappingList); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::TRIM_INTERNAL); + } +} + +void PageMapping::eraseInternal(PAL::Request &req, uint64_t &tick) { + static uint64_t threshold = + conf.readUint(CONFIG_FTL, FTL_BAD_BLOCK_THRESHOLD); + auto block = blocks.find(req.blockIndex); + + // Sanity checks + if (block == blocks.end()) { + panic("No such block"); + } + + if (block->second.getValidPageCount() != 0) { + panic("There are valid pages in victim block"); + } + + // Erase block + block->second.erase(); + + pPAL->erase(req, tick); + + // Check erase count + uint32_t erasedCount = block->second.getEraseCount(); + + if (erasedCount < threshold) { + // Reverse search + auto iter = freeBlocks.end(); + + while (true) { + iter--; + + if (iter->getEraseCount() <= erasedCount) { + // emplace: insert before pos + iter++; + + break; + } + + if (iter == freeBlocks.begin()) { + break; + } + } + + // Insert block to free block list + freeBlocks.emplace(iter, std::move(block->second)); + nFreeBlocks++; + } + + // Remove block from block list + blocks.erase(block); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::ERASE_INTERNAL); +} + +float PageMapping::calculateWearLeveling() { + uint64_t totalEraseCnt = 0; + uint64_t sumOfSquaredEraseCnt = 0; + uint64_t numOfBlocks = param.totalLogicalBlocks; + uint64_t eraseCnt; + + for (auto &iter : blocks) { + eraseCnt = iter.second.getEraseCount(); + totalEraseCnt += eraseCnt; + sumOfSquaredEraseCnt += eraseCnt * eraseCnt; + } + + // freeBlocks is sorted + // Calculate from backward, stop when eraseCnt is zero + for (auto riter = freeBlocks.rbegin(); riter != freeBlocks.rend(); riter++) { + eraseCnt = riter->getEraseCount(); + + if (eraseCnt == 0) { + break; + } + + totalEraseCnt += eraseCnt; + sumOfSquaredEraseCnt += eraseCnt * eraseCnt; + } + + if (sumOfSquaredEraseCnt == 0) { + return -1; // no meaning of wear-leveling + } + + return (float)totalEraseCnt * totalEraseCnt / + (numOfBlocks * sumOfSquaredEraseCnt); +} + +void PageMapping::calculateTotalPages(uint64_t &valid, uint64_t &invalid) { + valid = 0; + invalid = 0; + + for (auto &iter : blocks) { + valid += iter.second.getValidPageCount(); + invalid += iter.second.getDirtyPageCount(); + } +} + +void PageMapping::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "page_mapping.gc.count"; + temp.desc = "Total GC count"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.gc.reclaimed_blocks"; + temp.desc = "Total reclaimed blocks in GC"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.gc.superpage_copies"; + temp.desc = "Total copied valid superpages during GC"; + list.push_back(temp); + + temp.name = prefix + "page_mapping.gc.page_copies"; + temp.desc = "Total copied valid pages during GC"; + list.push_back(temp); + + // For the exact definition, see following paper: + // Li, Yongkun, Patrick PC Lee, and John Lui. + // "Stochastic modeling of large-scale solid-state storage systems: analysis, + // design tradeoffs and optimization." ACM SIGMETRICS (2013) + temp.name = prefix + "page_mapping.wear_leveling"; + temp.desc = "Wear-leveling factor"; + list.push_back(temp); +} + +void PageMapping::getStatValues(std::vector &values) { + values.push_back(stat.gcCount); + values.push_back(stat.reclaimedBlocks); + values.push_back(stat.validSuperPageCopies); + values.push_back(stat.validPageCopies); + values.push_back(calculateWearLeveling()); +} + +void PageMapping::resetStatValues() { + memset(&stat, 0, sizeof(stat)); +} + +} // namespace FTL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping.hh b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping.hh new file mode 100644 index 0000000000..5e89c57835 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping.hh @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __FTL_PAGE_MAPPING__ +#define __FTL_PAGE_MAPPING__ + +#include +#include +#include + +#include "ftl/abstract_ftl.hh" +#include "ftl/common/block.hh" +#include "ftl/ftl.hh" +#include "pal/pal.hh" + +namespace SimpleSSD { + +namespace FTL { + +class PageMapping : public AbstractFTL { + private: + PAL::PAL *pPAL; + + ConfigReader &conf; + + std::unordered_map>> + table; + std::unordered_map blocks; + std::list freeBlocks; + uint32_t nFreeBlocks; // For some libraries which std::list::size() is O(n) + std::vector lastFreeBlock; + Bitset lastFreeBlockIOMap; + uint32_t lastFreeBlockIndex; + + bool bReclaimMore; + bool bRandomTweak; + uint32_t bitsetSize; + + struct { + uint64_t gcCount; + uint64_t reclaimedBlocks; + uint64_t validSuperPageCopies; + uint64_t validPageCopies; + } stat; + + float freeBlockRatio(); + uint32_t convertBlockIdx(uint32_t); + uint32_t getFreeBlock(uint32_t); + uint32_t getLastFreeBlock(Bitset &); + void calculateVictimWeight(std::vector> &, + const EVICT_POLICY, uint64_t); + void selectVictimBlock(std::vector &, uint64_t &); + void doGarbageCollection(std::vector &, uint64_t &); + + float calculateWearLeveling(); + void calculateTotalPages(uint64_t &, uint64_t &); + + void readInternal(Request &, uint64_t &); + void writeInternal(Request &, uint64_t &, bool = true); + void trimInternal(Request &, uint64_t &); + void eraseInternal(PAL::Request &, uint64_t &); + + public: + PageMapping(ConfigReader &, Parameter &, PAL::PAL *, DRAM::AbstractDRAM *); + ~PageMapping(); + + bool initialize() override; + + void read(Request &, uint64_t &) override; + void write(Request &, uint64_t &) override; + void trim(Request &, uint64_t &) override; + + void format(LPNRange &, uint64_t &) override; + + Status *getStatus(uint64_t, uint64_t) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace FTL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping_hotness.cc b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping_hotness.cc new file mode 100644 index 0000000000..1fd4e392f3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping_hotness.cc @@ -0,0 +1,911 @@ +#include "ftl/page_mapping_hotness.hh" + +#include +#include +#include +#include +#include +#include "util/algorithm.hh" +#include "util/bitset.hh" +#include + +namespace SimpleSSD { namespace FTL { + +PageMappingHotness::PageMappingHotness(ConfigReader& c, Parameter& p, PAL::PAL* l, DRAM::AbstractDRAM* d) + : AbstractFTL(p,l,d), pPAL(l), conf(c), + lastFreeBlockIOMap(param.ioUnitInPage), + bReclaimMore(false), + reservePerPool(0) +{ + reservePerPool = std::max(1u, param.totalPhysicalBlocks / (4u * 64u)); + + // free block을 미지정 shard(4분할)로 균등 분배 (blockIdx % 4) + for (uint32_t i = 0; i < param.totalPhysicalBlocks; i++) { + uint8_t d = i & 3; + freeBlocksByT[d].emplace_back(Block(i, param.pagesInBlock, param.ioUnitInPage)); + nFreeByT[d]++; + } + + // last-free 초기화: 초기에는 어떤 풀에도 태깅하지 않음(미지정). + for (uint8_t t = 0; t < 4; ++t) { + lastFreeBlockByT[t].assign(param.pageCountToMaxPerf, param.totalPhysicalBlocks); // INVALID sentinel + lastFreeIdx[t] = 0; + } + + status.totalLogicalPages = param.totalLogicalBlocks * param.pagesInBlock; + +// memset(&stat, 0, sizeof(stat)); + bRandomTweak = conf.readBoolean(CONFIG_FTL, FTL_USE_RANDOM_IO_TWEAK); + bitsetSize = bRandomTweak ? param.ioUnitInPage : 1; +} + +PageMappingHotness::~PageMappingHotness() {} + +bool PageMappingHotness::initialize() { + debugprint(LOG_FTL_PAGE_MAPPING, "Hotness-FTL Initialization finished"); + return true; +} + +float PageMappingHotness::freeBlockRatio(uint8_t t) { + uint64_t headroomPages = 0; + + for (auto& kv : blocks) { + const uint32_t bid = kv.first; + auto& blk = kv.second; + + auto it = blockPool.find(bid); + if (it != blockPool.end() && it->second == t) { + const uint32_t wp = blk.getNextWritePageIndex(); + if (wp < param.pagesInBlock) { + headroomPages += (uint64_t)(param.pagesInBlock - wp); + } + } + } + + const uint64_t denom = (uint64_t)param.pagesInBlock; // 최소 1블록 헤드룸을 기준 + if (denom == 0) return 0.0f; + + float r = (float)headroomPages / (float)denom; + if (r > 1.0f) r = 1.0f; // 과도하게 많은 오픈 블록이 있어도 1로 클램프 + return r; +} + + +uint32_t PageMappingHotness::borrowFreeBlock(uint8_t t, uint32_t stripeIdx) { + for (uint8_t d = 0; d < 4; ++d) { + if (freeBlocksByT[d].empty()) continue; + + auto it = freeBlocksByT[d].begin(); + uint32_t blockIndex = 0; + for (; it != freeBlocksByT[d].end(); ++it) { + blockIndex = it->getBlockIndex(); + if (blockIndex % param.pageCountToMaxPerf == stripeIdx) break; + } + if (it == freeBlocksByT[d].end()) { it = freeBlocksByT[d].begin(); blockIndex = it->getBlockIndex(); } + + blocks.emplace(blockIndex, std::move(*it)); + freeBlocksByT[d].erase(it); + nFreeByT[d]--; + + stat.allocPop[d]++; + blockPool[blockIndex] = t; // 재태깅 중요 + return blockIndex; + } + return param.totalPhysicalBlocks; // 실패 +} + +uint32_t PageMappingHotness::getFreeBlock(uint8_t t, uint32_t stripeIdx) { + if (stripeIdx >= param.pageCountToMaxPerf) panic("Index out of range"); + + // Fully-unassigned: 어떤 도너 shard(0..3)에서든 하나 꺼내 첫-터치 태깅 + auto pick_from = [&](uint8_t d)->int32_t { + if (freeBlocksByT[d].empty()) return -1; + + // 같은 stripe 우선 + auto it = freeBlocksByT[d].end(); + uint32_t blockIndex = 0; + for (auto it2 = freeBlocksByT[d].begin(); it2 != freeBlocksByT[d].end(); ++it2) { + blockIndex = it2->getBlockIndex(); + if ((blockIndex % param.pageCountToMaxPerf) == stripeIdx) { it = it2; break; } + } + if (it == freeBlocksByT[d].end()) { + it = freeBlocksByT[d].begin(); + blockIndex = it->getBlockIndex(); + } + + if (blocks.find(blockIndex) != blocks.end()) + panic("Corrupted: free->alloc double-take"); + + // ★ 첫-터치 태깅 + blockPool[blockIndex] = t; + blocks.emplace(blockIndex, std::move(*it)); + freeBlocksByT[d].erase(it); + nFreeByT[d]--; + + stat.allocPop[d]++; + return static_cast(blockIndex); + }; + + // stripe 해시 기준 라운드로빈 + for (uint8_t off = 0; off < 4; ++off) { + const uint8_t d = static_cast((stripeIdx + off) & 3); + int32_t bid = pick_from(d); + if (bid >= 0) return static_cast(bid); + } + + // 최후 수단: 기존 borrow 경로 + auto b = borrowFreeBlock(t, stripeIdx); + if (b < param.totalPhysicalBlocks) return b; + + panic("No free block left"); + return param.totalPhysicalBlocks; // -Wreturn-type 억제 (panic이 noreturn 아닐 때) +} + + + +uint32_t PageMappingHotness::getLastFreeBlock(uint8_t t, Bitset& iomap) { + // 1) I/O lane 라운드로빈 (원본과 동일한 조건) + if (!bRandomTweak || (lastFreeBlockIOMap & iomap).any()) { + if (++lastFreeIdx[t] == param.pageCountToMaxPerf) lastFreeIdx[t] = 0; + lastFreeBlockIOMap = iomap; + } else { + lastFreeBlockIOMap |= iomap; + } + + const uint32_t lane = lastFreeIdx[t]; + uint32_t &bid = lastFreeBlockByT[t][lane]; + + // 2) 캐시된 블록이 없으면 즉시 확보(풀 t에서) + auto it = blocks.find(bid); + if (it == blocks.end()) { + bid = getFreeBlock(t, lane); // first-touch 기반: 글로벌 free에서 가져오고 태깅 + blockPool[bid] = t; // (안전) + return bid; + } + + // 3) 캐시된 free 블록이 꽉 찼으면 교체(+ bReclaimMore) + if (it->second.getNextWritePageIndex() >= param.pagesInBlock) { + bid = getFreeBlock(t, lane); // 글로벌 free에서 확보 + blockPool[bid] = t; // (안전) + bReclaimMore= true; + } + return bid; +} + + + +void PageMappingHotness::read(Request& req, uint64_t& tick) { + uint64_t begin = tick; + if (req.ioFlag.count() == 0) { warn("FTL got empty request"); return; } + readInternal(req, tick); + debugprint(LOG_FTL_PAGE_MAPPING, "READ | LPN %" PRIu64 " | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + req.lpn, begin, tick, tick - begin); + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::READ); +} + +void PageMappingHotness::write(Request& req, uint64_t& tick) { + writeInternal(req, tick, true); + } + +void PageMappingHotness::trim(Request& req, uint64_t& tick) { + trimInternal(req, tick); +} + +void PageMappingHotness::format(LPNRange& , uint64_t& tick) { + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::FORMAT); +} + +void PageMappingHotness::resetStatValues() { + uint64_t snap[4] = { stat.initFree[0], stat.initFree[1], stat.initFree[2], stat.initFree[3] }; + stat = decltype(stat){}; + for (int t=0; t<4; ++t) stat.initFree[t] = snap[t]; +} + +Status* PageMappingHotness::getStatus(uint64_t lpnBegin, uint64_t lpnEnd) { + status.freePhysicalBlocks = + nFreeByT[0] + nFreeByT[1] + nFreeByT[2] + nFreeByT[3]; + + if (lpnBegin == 0 && lpnEnd >= status.totalLogicalPages) { + status.mappedLogicalPages = table.size(); + return &status; + } + + uint64_t cnt = 0; + for (const auto& kv : table) { + uint64_t lpn = kv.first; // unordered_map 가정 + if (lpn >= lpnBegin && lpn < lpnEnd) ++cnt; + } + status.mappedLogicalPages = cnt; + return &status; +} + +// ===== 내부 동작 (기본 PageMapping과 거의 동일) ===== + +void PageMappingHotness::readInternal(Request& req, uint64_t& tick) { + PAL::Request palRequest(req); + uint64_t beginAt; + uint64_t finishedAt = tick; + + auto mappingList = table.find(req.lpn); + + if (mappingList != table.end()) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + } + else { + pDRAM->read(&(*mappingList), 8, tick); + } + + for (uint32_t idx = 0; idx < bitsetSize; idx++) { + if (req.ioFlag.test(idx) || !bRandomTweak) { + auto &mapping = mappingList->second.at(idx); + + if (mapping.first < param.totalPhysicalBlocks && + mapping.second < param.pagesInBlock) { + palRequest.blockIndex = mapping.first; + palRequest.pageIndex = mapping.second; + + if (bRandomTweak) { + palRequest.ioFlag.reset(); + palRequest.ioFlag.set(idx); + } + else { + palRequest.ioFlag.set(); + } + + auto block = blocks.find(palRequest.blockIndex); + + if (block == blocks.end()) { + panic("Block is not in use"); + } + + beginAt = tick; + + block->second.read(palRequest.pageIndex, idx, beginAt); + pPAL->read(palRequest, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + } + } + + tick = finishedAt; + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::READ_INTERNAL); + } +} + +void PageMappingHotness::writeInternal(Request& req, uint64_t& tick, bool sendToPAL) { + PAL::Request pal(req); + auto mappingList = table.find(req.lpn); + uint64_t beginAt; + uint64_t finishedAt = tick; + bool readBeforeWrite = false; + + // --- 기존 매핑 무효화 / 없으면 삽입 --- + if (mappingList != table.end()) { + for (uint32_t i = 0; i < bitsetSize; i++) { + if (req.ioFlag.test(i) || !bRandomTweak) { + auto& m = mappingList->second.at(i); + if (m.first < param.totalPhysicalBlocks && m.second < param.pagesInBlock) { + auto it = blocks.find(m.first); + if (it != blocks.end()) it->second.invalidate(m.second, i); + } + } + } + } else { + auto ret = table.emplace( + req.lpn, + std::vector>(bitsetSize, {param.totalPhysicalBlocks, param.pagesInBlock}) + ); + if (!ret.second) panic("Failed to insert mapping"); + mappingList = ret.first; + } + + // --- 라벨/서브페이지 수 --- + const int rawT = req.temperature; + const uint8_t reqT = clampTemp(rawT); + lpnTemp[req.lpn] = reqT; + + // (선택) FTL 입구 원시 라벨 히스토그램 + static uint64_t ftl_entry_raw[5] = {0}; // 0:-1, 1:0, 2:1, 3:2, 4:3 + if (rawT == -1) ftl_entry_raw[0]++; + else if (rawT == 0) ftl_entry_raw[1]++; + else if (rawT == 1) ftl_entry_raw[2]++; + else if (rawT == 2) ftl_entry_raw[3]++; + else ftl_entry_raw[4]++; // >=3 은 3으로 클램프 + + const uint32_t subpages = static_cast(req.ioFlag.count()); // ★ 4KiB 서브페이지 수 + + // --- 기본은 요청 풀 사용, 없으면 인접 풀로 폴백 --- + uint8_t useT = reqT; + + // --- 실제 사용 풀에서 free 블록 선택 --- + uint32_t blkId = getLastFreeBlock(useT, req.ioFlag); + auto blkIt = blocks.find(blkId); + if (blkIt == blocks.end()) panic("No such block"); + + // --- 블록 태그로 실제 사용 풀 확정 --- + uint8_t actualT = useT; + { + auto itp = blockPool.find(blkId); + if (itp != blockPool.end() && itp->second < 4) actualT = itp->second; + } + + // --- 통계: "서브페이지 수" 기준으로 딱 1번 누적 --- + if (reqT < 4) stat.writesReq[reqT] += (uint64_t)subpages; + if (actualT < 4) stat.writesUse[actualT] += (uint64_t)subpages; + if (reqT < 4 && actualT < 4 && reqT != actualT) { + stat.fallback[reqT][actualT] += (uint64_t)subpages; + } + + // --- DRAM 메타 I/O --- + if (sendToPAL) { + if (bRandomTweak) { + pDRAM->read(&(*mappingList), 8 * req.ioFlag.count(), tick); + pDRAM->write(&(*mappingList), 8 * req.ioFlag.count(), tick); + } else { + pDRAM->read(&(*mappingList), 8, tick); + pDRAM->write(&(*mappingList), 8, tick); + } + } + + if (!bRandomTweak && !req.ioFlag.all()) readBeforeWrite = true; + + // --- 실제 쓰기 --- +for (uint32_t i = 0; i < bitsetSize; i++) { + if (req.ioFlag.test(i) || !bRandomTweak) { + uint32_t pageIndex = blkIt->second.getNextWritePageIndex(i); + auto& m = mappingList->second.at(i); + beginAt = tick; + + blkIt->second.write(pageIndex, req.lpn, i, beginAt); + + if (readBeforeWrite && sendToPAL) { + pal.blockIndex = m.first; + pal.pageIndex = m.second; + pal.ioFlag = req.ioFlag; pal.ioFlag.flip(); + pPAL->read(pal, beginAt); + } + + m.first = blkIt->first; + m.second = pageIndex; + + if (sendToPAL) { + pal.blockIndex = blkIt->first; + pal.pageIndex = pageIndex; + if (bRandomTweak) { pal.ioFlag.reset(); pal.ioFlag.set(i); } + else pal.ioFlag.set(); + pPAL->write(pal, beginAt); + + { + const uint64_t bytesPerSub = param.pageSize / param.ioUnitInPage; + const uint64_t devBytesRaw = bytesPerSub * static_cast(pal.ioFlag.count()); + const uint64_t devBytes = devBytesRaw / 2; // PAL이 1/2 페이지 단위로 program.bytes를 집계 + stat.nandProgramBytes += devBytes; +} + + } + + finishedAt = MAX(finishedAt, beginAt); + } +} + + + if (sendToPAL) { + tick = finishedAt; + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::WRITE_INTERNAL); + } + + // --- GC 트리거(실사용 풀 기준) --- + auto clamp01 = [](float v, float def){ return (v>0.f && v<1.f) ? v : def; }; + float low = clamp01(conf.readFloat(CONFIG_FTL, FTL_GC_THRESHOLD_RATIO), 0.10f); + + if (freeBlockRatio(actualT) < low) { + if (!sendToPAL) panic("ftl: GC triggered during init"); + + uint64_t beginAt2 = tick; + std::vector victims; + + selectVictimBlock(actualT, victims, beginAt2); + debugprint(LOG_FTL_PAGE_MAPPING, "GC | pool=%u | victims=%zu", + (unsigned)actualT, victims.size()); + doGarbageCollection(actualT, victims, beginAt2); + + bReclaimMore = false; + } + + debugprint(LOG_FTL_PAGE_MAPPING, + "ALLOC_USE | lpn=%" PRIu64 " | reqT=%u -> useT=%u | blk=%u | pool=%u | free_left=%zu", + req.lpn, (unsigned)reqT, (unsigned)useT, blkId, (unsigned)actualT, + freeBlocksByT[useT].size()); +} + + + +void PageMappingHotness::trimInternal(Request& req, uint64_t& tick) { + auto it = table.find(req.lpn); + if (it != table.end()) { + if (bRandomTweak) pDRAM->read(&(*it), 8 * req.ioFlag.count(), tick); + else pDRAM->read(&(*it), 8, tick); + + for (uint32_t i = 0; i < bitsetSize; i++) { + auto& m = it->second.at(i); + auto b = blocks.find(m.first); + if (b == blocks.end()) panic("Block not in use"); + b->second.invalidate(m.second, i); + } + table.erase(it); + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::TRIM_INTERNAL); + } +} + +void PageMappingHotness::eraseInternal(PAL::Request& req, uint64_t& tick) { + // 1) victim block 찾기 + auto it = blocks.find(req.blockIndex); + if (it == blocks.end()) panic("No such block"); + + // 2) 유효 페이지 확인 + if (it->second.getValidPageCount() != 0) panic("Valid pages remain in victim"); + + // 3) 실제 erase + it->second.erase(); // 내부 상태 리셋 + pPAL->erase(req, tick); // PAL에 erase 발행 + + // 4) 완전 미지정 회수: 라벨 해제 후, donor shard를 stripe 기반으로 선택 + // (균형 유지를 위해 4개 shard로 라운드-로빈 분산) + uint32_t stripe = req.blockIndex % param.pageCountToMaxPerf; + uint8_t donor = (uint8_t)(stripe & 3); + + // 라벨 해제 + auto itp = blockPool.find(req.blockIndex); + if (itp != blockPool.end()) blockPool.erase(itp); + + // free 리스트로 회수 + freeBlocksByT[donor].push_back(std::move(it->second)); + nFreeByT[donor]++; + + // in-use 컨테이너에서 제거 + blocks.erase(it); + + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::ERASE_INTERNAL); + debugprint(LOG_FTL_PAGE_MAPPING, + "ERASE | to_unassigned donor=%u block=%u | free(size)=%zu", + (unsigned)donor, (unsigned)req.blockIndex, freeBlocksByT[donor].size()); +} + +void PageMappingHotness::calculateTotalPages(uint64_t& valid, uint64_t& invalid) { + valid = invalid = 0; + for (auto& kv : blocks) { + valid += kv.second.getValidPageCount(); + invalid += kv.second.getDirtyPageCount(); + } +} + +float PageMappingHotness::calculateWearLeveling() { + // Jain's fairness index: (Σe)^2 / (N * Σe^2), N = 물리 블록 수 + const uint64_t numOfBlocks = param.totalPhysicalBlocks; + + uint64_t totalErase = 0; // Σe + long double sumSq = 0.0L; // Σe^2 + + // 활성 블록들 + for (auto& kv : blocks) { + uint64_t e = kv.second.getEraseCount(); // Block::getEraseCount()가 non-const + totalErase += e; + sumSq += (long double)e * e; + } + + // 모든 풀(0..3)의 free 블록들 + for (int pool = 0; pool < 4; ++pool) { + for (auto& b : freeBlocksByT[pool]) { + uint64_t e = b.getEraseCount(); // 여기서도 non-const 필요 + totalErase += e; + sumSq += (long double)e * e; + } + } + + if (sumSq == 0.0L || numOfBlocks == 0) return -1.0f; + long double numer = (long double)totalErase * totalErase; + long double denom = (long double)numOfBlocks * sumSq; + return (float)(numer / denom); +} + +void PageMappingHotness::calculateVictimWeight( + uint8_t t, + std::vector>& weight, + const EVICT_POLICY policy, + uint64_t tick) +{ + weight.clear(); + weight.reserve(blocks.size()); + + for (auto &kv : blocks) { + // 같은 온도 풀의 '가득 찬' 블록만 후보 + auto itp = blockPool.find(kv.first); + if (itp == blockPool.end() || itp->second != t) continue; + + if (kv.second.getNextWritePageIndex() != param.pagesInBlock) continue; + + switch (policy) { + case POLICY_GREEDY: + case POLICY_RANDOM: + case POLICY_DCHOICE: { + // 유효 페이지 수가 적을수록 가벼움 + float w = static_cast(kv.second.getValidPageCountRaw()); + weight.emplace_back(kv.first, w); + break; + } + case POLICY_COST_BENEFIT: { + float u = static_cast(kv.second.getValidPageCountRaw()) / + static_cast(param.pagesInBlock); // 유효비율 + float age = static_cast(tick - kv.second.getLastAccessedTime()); + float denom = (1.0f - u) * (age <= 0.0f ? 1.0f : age); + float w = (denom <= 0.0f) ? std::numeric_limits::infinity() + : (u / denom); + weight.emplace_back(kv.first, w); + break; + } + default: + panic("Invalid GC evict policy"); + } + } +} + + +void PageMappingHotness::selectVictimBlock(uint8_t t, + std::vector& list, + uint64_t& tick) { + list.clear(); + + // 1) 한 번에 회수할 블록 수 (설정이 0이면 최소 1 보장) + uint64_t nBlocks = conf.readUint(CONFIG_FTL, FTL_GC_RECLAIM_BLOCK); + if (nBlocks == 0) nBlocks = 1; + + // 2) 후보 weight 계산: "풀 t" 이면서 "이미 꽉 찬 블록"만 + std::vector> weight; + weight.reserve(64); + + for (auto& kv : blocks) { + uint32_t bid = kv.first; + Block& blk = kv.second; + auto itp = blockPool.find(bid); + if (itp == blockPool.end() || itp->second != t) continue; // 다른 풀 + if (blk.getNextWritePageIndex() != param.pagesInBlock) continue; // 꽉 안 찬 블록 제외 + + // GREEDY: 유효 페이지 수가 적을수록 유리 + weight.push_back({ bid, (float)blk.getValidPageCountRaw() }); + } + + if (weight.empty()) { + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::SELECT_VICTIM_BLOCK); + return; + } + + std::sort(weight.begin(), weight.end(), + [](const std::pair& a, + const std::pair& b) { + return a.second < b.second; + }); + + nBlocks = std::min(nBlocks, weight.size()); + list.reserve(nBlocks); + for (uint64_t i=0; i& victims, + uint64_t& tick) { + if (victims.empty()) return; + + + PAL::Request req(param.ioUnitInPage); + std::vector reads, writes, erases; + Bitset bit(param.ioUnitInPage); + std::vector lpns; + uint64_t rFin=tick, wFin=tick, eFin=tick, beginAt=0; + const uint32_t INVALID_BLK = std::numeric_limits::max(); + + uint32_t openDst[4] = { + INVALID_BLK, INVALID_BLK, INVALID_BLK, INVALID_BLK +}; + +auto ensureOpenDst = [&](uint8_t pool, Bitset& iomap)->uint32_t { + uint32_t& cur = openDst[pool]; + if (cur != INVALID_BLK) { + auto it = blocks.find(cur); + if (it != blocks.end() && + it->second.getNextWritePageIndex() < param.pagesInBlock) { + // 아직 공간 남아 있으면 그대로 재사용 + return cur; + } + // 가득 찼거나 사라졌으면 무효화 + cur = INVALID_BLK; + } + // 새 오픈 블록 하나만 확보 (여기서 한 번만 getLastFreeBlock 호출) + cur = getLastFreeBlock(pool, iomap); + blockPool[cur] = pool; // 안전 태깅 + return cur; +}; + + auto poolOf = [&](uint32_t blk)->uint8_t { + auto itp = blockPool.find(blk); + if (itp != blockPool.end() && 0 <= itp->second && itp->second < 4) + return static_cast(itp->second); + stat.poolBug++; + return t; // 못 찾으면 호출 인자 t로 폴백 + }; + uint64_t victimsPerPool[4] = {0,0,0,0}; + + for (auto bid : victims) { + uint8_t pool = poolOf(bid); + victimsPerPool[pool]++; + + auto it = blocks.find(bid); + if (it == blocks.end()) panic("Invalid block"); + Block& vblk = it->second; + + for (uint32_t pg=0; pgsecond; // 포인터로 잡아두면 중간에 새 블록으로 스위칭 용이 +bool copied = false; // 이 superpage(페이지)에 실제 복사 발생 여부 + +// 유효 서브페이지별 복사 + 매핑 갱신 +for (uint32_t k = 0; k < bitsetSize; ++k) if (bit.test(k)) { + if (k >= lpns.size()) continue; + // ★ 중간에 데스티네이션 블록이 꽉 차면 즉시 새 오픈 블록으로 전환 + if (dst->getNextWritePageIndex() >= param.pagesInBlock) { + openDst[pool] = INVALID_BLK; // 캐시 무효화 + newBlkId = ensureOpenDst(pool, bit); // 새 오픈 블록 확보 + auto it2 = blocks.find(newBlkId); + if (it2 == blocks.end()) panic("No free block allocated"); + dst = &it2->second; // 포인터 리바인딩 + } + + vblk.invalidate(pg, k); + auto mIt = table.find(lpns[k]); if (mIt == table.end()) panic("Invalid mapping"); + if (bRandomTweak) pDRAM->read(&(*mIt), 8 * param.ioUnitInPage, tick); + else pDRAM->read(&(*mIt), 8, tick); + + uint32_t newPg = dst->getNextWritePageIndex(k); + beginAt = tick; // writeInternal과 동일하게 tick 기준 + dst->write(newPg, lpns[k], k, beginAt); + + auto& mapping = mIt->second.at(k); + mapping.first = newBlkId; + mapping.second = newPg; + + if (bRandomTweak) pDRAM->write(&(*mIt), 8 * param.ioUnitInPage, tick); + else pDRAM->write(&(*mIt), 8, tick); + + req.blockIndex = newBlkId; req.pageIndex = newPg; + if (bRandomTweak) { req.ioFlag.reset(); req.ioFlag.set(k); } else { req.ioFlag.set(); } + writes.push_back(req); + + //stat.validPageCopies[pool]++; + copied = true; +} + +// (선택) 페이지 종료 시점에 한 번 더 꽉 참 체크 → 다음 ensure에서 새로 열리도록 +if (dst->getNextWritePageIndex() >= param.pagesInBlock) { + openDst[pool] = INVALID_BLK; +} +// ★ 페이지(pg) 단위 처리 끝난 뒤, 실제 복사된 서브페이지 수를 누적 +const uint32_t nvalid = bitValid.count(); // <- 추가 +if (copied && nvalid > 0) { + stat.validSuperPageCopies[pool]++; // 기존 유지 + stat.validPageCopies[pool] += nvalid; // <- 기존의 ++ 대신 이 줄로 이동/교체 +} + +} + // ERASE 예약 + req.blockIndex = bid; req.pageIndex = 0; req.ioFlag.set(); + erases.push_back(req); + } + for (int p=0; p<4; ++p) { + if (victimsPerPool[p] > 0) { + stat.gcCount[p] += victimsPerPool[p]; + stat.reclaimedBlocks[p] += victimsPerPool[p]; + } + } + + for (auto& r: reads) { beginAt=tick; pPAL->read(r, beginAt); rFin = std::max(rFin, beginAt); } + for (auto& w: writes) { beginAt=rFin; pPAL->write(w, beginAt); + { + const uint64_t bytesPerSub = param.pageSize / param.ioUnitInPage; + const uint64_t devBytesRaw = bytesPerSub * static_cast(w.ioFlag.count()); + const uint64_t devBytes = devBytesRaw / 2; + stat.nandProgramBytes += devBytes; +} + + wFin = std::max(wFin, beginAt); } + for (auto& e: erases) { beginAt = wFin; eraseInternal(e, beginAt); eFin = std::max(eFin, beginAt); } + + tick = std::max(wFin, eFin); + tick += applyLatency(CPU::FTL__PAGE_MAPPING, CPU::DO_GARBAGE_COLLECTION); +} + + + +void PageMappingHotness::getStatList(std::vector& list, std::string prefix) { + // 기본 PageMapping 이름과 충돌 안나게 hotness 접두사 사용 + for (int t=0; t<4; ++t) { + Stats s; + s.name = prefix + "page_mapping_hotness.gc.count.t" + std::to_string(t); + s.desc = "GC count for pool t" + std::to_string(t); + list.push_back(s); + + s.name = prefix + "page_mapping_hotness.gc.reclaimed_blocks.t" + std::to_string(t); + s.desc = "Reclaimed blocks in GC for pool t" + std::to_string(t); + list.push_back(s); + + s.name = prefix + "page_mapping_hotness.gc.superpage_copies.t" + std::to_string(t); + s.desc = "Copied valid superpages in GC (pool t)"; + list.push_back(s); + + s.name = prefix + "page_mapping_hotness.gc.page_copies.t" + std::to_string(t); + s.desc = "Copied valid pages in GC (pool t)"; + list.push_back(s); + } + // 초기 free +/*for (int t=0; t<4; ++t) { + Stats s; + s.name = prefix + "page_mapping_hotness.init_free.t" + std::to_string(t); + s.desc = "Initial free blocks in pool t" + std::to_string(t); + list.push_back(s); +}*/ + + +// 요청/사용 분포 +for (int t=0; t<4; ++t) { + Stats s1, s2; + s1.name = prefix + "page_mapping_hotness.writes_req.t" + std::to_string(t); + s1.desc = "Writes by requested label t" + std::to_string(t); + list.push_back(s1); + s2.name = prefix + "page_mapping_hotness.writes_use.t" + std::to_string(t); + s2.desc = "Writes by actual pool t" + std::to_string(t); + list.push_back(s2); +} + +// 폴백 4x4 +//for (int r=0; r<4; ++r) for (int u=0; u<4; ++u) { + //Stats s; +// s.name = prefix + "page_mapping_hotness.fallback.req" + std::to_string(r) +// + "_to" + std::to_string(u); +// s.desc = "Fallback from req tier " + std::to_string(r) +// + " to use tier " + std::to_string(u); +// list.push_back(s); +//} + + +// free pop 카운트 +//for (int t=0; t<4; ++t) { +// Stats s; +// s.name = prefix + "page_mapping_hotness.alloc.pop.t" + std::to_string(t); +// s.desc = "Pops from free list (pool t)"; +// list.push_back(s); +//} + + +// pool 태깅 누락 +{ + Stats s; + s.name = prefix + "page_mapping_hotness.pool_bug"; + s.desc = "Victims with missing/invalid pool tag"; + list.push_back(s); +} + + Stats wl; + wl.name = prefix + "page_mapping_hotness.wear_leveling"; + wl.desc = "Wear-leveling factor (approx.)"; + list.push_back(wl); + + {// (교체) W/A 관련 통계 키 +{ + Stats s; + + s.name = prefix + "page_mapping_hotness.wa.ftl_new_prog_bytes"; + s.desc = "FTL new-program bytes (excl. GC)"; // GC 복사 제외한 실제 신규 프로그램 바이트 + list.push_back(s); + + s.name = prefix + "page_mapping_hotness.wa.device_total_bytes"; + s.desc = "Total NAND program bytes (incl. GC)"; // 기존 desc 유지 가능 + list.push_back(s); + + s.name = prefix + "page_mapping_hotness.wa.gc_only"; + s.desc = "Write Amplification (GC-only) = device_total_bytes / ftl_new_prog_bytes"; + list.push_back(s); +} + +} +} + +void PageMappingHotness::getStatValues(std::vector& values) { + const int TIERS = 4; + const size_t base = values.size(); + values.reserve( base + + TIERS*4 /*gc*/ + // + TIERS /*init_free*/ + + TIERS*2 /*writes req/use*/ + // + TIERS*TIERS /*fallback*/ + // + TIERS /*alloc.pop*/ + + 1 /*pool_bug*/ + + 1 /*wear*/ + +3 + ); + + // ---- GC (등록 순서와 동일) ---- + for (int t = 0; t < TIERS; ++t) { + values.push_back((double)stat.gcCount[t]); + values.push_back((double)stat.reclaimedBlocks[t]); + values.push_back((double)stat.validSuperPageCopies[t]); + values.push_back((double)stat.validPageCopies[t]); + } + + // ---- init_free ---- + //for (int t=0; t<4; ++t) values.push_back((double)stat.initFree[t]); + + // ---- writes_req / writes_use ---- + for (int t=0; t<4; ++t) { + values.push_back((double)stat.writesReq[t]); + values.push_back((double)stat.writesUse[t]); +} + + // ---- fallback 4x4 ---- + //for (int r=0; r<4; ++r) for (int u=0; u<4; ++u) + // values.push_back((double)stat.fallback[r][u]); + + // ---- alloc.pop ---- + //for (int t=0; t<4; ++t) values.push_back((double)stat.allocPop[t]); + + // ---- pool_bug ---- + values.push_back((double)stat.poolBug); + + // ---- wear_leveling (마지막) ---- + values.push_back((double)calculateWearLeveling()); + + // --- W/A (GC-only) 산출: devBytes / ftlNewBytes --- +const uint64_t bytesPerSub = + param.pageSize / param.ioUnitInPage; // 서브페이지(4KiB) → 물리 페이지 바이트 분배 + +const uint64_t devBytes = stat.nandProgramBytes; // 총 NAND program 바이트(=신규+GC) + +// GC가 복사한 서브페이지 수 합 +const uint64_t gcSubCopies = + (uint64_t)stat.validPageCopies[0] + + (uint64_t)stat.validPageCopies[1] + + (uint64_t)stat.validPageCopies[2] + + (uint64_t)stat.validPageCopies[3]; + +// devBytes 누적과 동일한 규칙(/2)으로 GC 바이트 환산 +const uint64_t gcBytes = (gcSubCopies * bytesPerSub) / 2; + +// FTL 신규 프로그램 바이트(= devBytes - gcBytes) +const uint64_t ftlNewBytes = (devBytes > gcBytes) ? (devBytes - gcBytes) : 0; + +const double wafGcOnly = ftlNewBytes + ? (double)devBytes / (double)ftlNewBytes + : 0.0; + +// --- 출력(등록 순서: ftl_new_prog_bytes, device_total_bytes, gc_only) --- +values.push_back((double)ftlNewBytes); +values.push_back((double)devBytes); +values.push_back(wafGcOnly); + + +} +} +} \ No newline at end of file diff --git a/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping_hotness.hh b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping_hotness.hh new file mode 100644 index 0000000000..43e4bf0e95 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/ftl/page_mapping_hotness.hh @@ -0,0 +1,109 @@ +#ifndef __FTL_PAGE_MAPPING_HOTNESS__ +#define __FTL_PAGE_MAPPING_HOTNESS__ + +#include +#include +#include +#include + +#include "ftl/abstract_ftl.hh" +#include "ftl/common/block.hh" +#include "ftl/ftl.hh" +#include "pal/pal.hh" + +namespace SimpleSSD { namespace FTL { + +class PageMappingHotness : public AbstractFTL { + private: + PAL::PAL* pPAL; + ConfigReader& conf; + // LPN -> [(block,page) * ioUnitInPage] + std::unordered_map>> table; + + // 활성 블록(실사용) + std::unordered_map blocks; + + // 온도별 free block 풀 (0..3) + std::array,4> freeBlocksByT {}; + std::array nFreeByT {{0,0,0,0}}; + + // 블록이 어느 풀(온도)에 속하는지 + std::unordered_map blockPool; + + // 온도별 최근 free block (채널/스트라이프 수만큼) + std::array,4> lastFreeBlockByT; + std::array lastFreeIdx {{0,0,0,0}}; + Bitset lastFreeBlockIOMap; + + // LPN의 최신 temperature 라벨 + std::unordered_map lpnTemp; + + + bool bReclaimMore = false; + bool bRandomTweak; + uint32_t bitsetSize; + uint32_t reservePerPool; // 각 풀당 예비 블록 개수 + + inline uint8_t clampTemp(int t) const { return (t < 0) ? 0 : (t > 3 ? 3 : (uint8_t)t); } + + // helpers + float freeBlockRatio(uint8_t t); + uint32_t getFreeBlock(uint8_t t, uint32_t stripeIdx); + uint32_t getLastFreeBlock(uint8_t t, Bitset& iomap); + uint32_t borrowFreeBlock(uint8_t t, uint32_t stripeIdx); + + void calculateVictimWeight(uint8_t t, + std::vector>& weight, + const EVICT_POLICY policy, uint64_t tick); + + void selectVictimBlock(uint8_t t, std::vector& list, uint64_t& tick); + void doGarbageCollection(uint8_t t, std::vector& blocksToReclaim, uint64_t& tick); + + void readInternal(Request& req, uint64_t& tick); + void writeInternal(Request& req, uint64_t& tick, bool sendToPAL = true); + void trimInternal(Request& req, uint64_t& tick); + void eraseInternal(PAL::Request& req, uint64_t& tick); + + float calculateWearLeveling(); + void calculateTotalPages(uint64_t& valid, uint64_t& invalid); + + struct { + uint64_t gcCount[4] {}; + uint64_t reclaimedBlocks[4] {}; + uint64_t validSuperPageCopies[4] {}; + uint64_t validPageCopies[4] {}; + + uint64_t initFree[4] = {0,0,0,0}; // 시작 시 풀별 free 스냅샷 + uint64_t writesReq[4] = {0,0,0,0}; // 요청 라벨 분포 + uint64_t writesUse[4] = {0,0,0,0}; // 실제 사용 풀 분포 + uint64_t fallback[4][4] = {{0}}; // [req][use] 폴백 매트릭스 + uint64_t allocPop[4] = {0,0,0,0}; // free 리스트에서 꺼낸 횟수(풀 기준) + int64_t poolBug = 0; // GC에서 blockPool 태깅 못 찾은 횟수 + + uint64_t hostProgramBytes = 0; // 호스트로 인해 FTL이 실제 프로그램한 바이트 + uint64_t nandProgramBytes = 0; // 디바이스 Program 총 바이트(분자, GC 포함) + uint64_t gcProgramBytes = 0; // GC로 인해 실제 디바이스에 프로그램된 바이트 누적 + } stat; + + public: + PageMappingHotness(ConfigReader& c, Parameter& p, PAL::PAL* l, DRAM::AbstractDRAM* d); + ~PageMappingHotness(); + + bool initialize() override; + + void read(Request& req, uint64_t& tick) override; + void write(Request& req, uint64_t& tick) override; + void trim(Request& req, uint64_t& tick) override; + + void format(LPNRange& range, uint64_t& tick) override; + + Status* getStatus(uint64_t lpnBegin, uint64_t lpnEnd) override; + + void getStatList(std::vector& list, std::string prefix) override; + void getStatValues(std::vector& values) override; + void resetStatValues() override; +}; + +}} // namespace + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/hil.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/hil.cc new file mode 100644 index 0000000000..73627c722d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/hil.cc @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/hil.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +HIL::HIL(ConfigReader &c) : conf(c), reqCount(0), lastScheduled(0) { + pICL = new ICL::ICL(conf); + + memset(&stat, 0, sizeof(stat)); + + completionEvent = allocate([this](uint64_t) { completion(); }); +} + +HIL::~HIL() { + delete pICL; +} + +void HIL::read(Request &req) { + + DMAFunction doRead = [this](uint64_t beginAt, void *context) { + auto pReq = (Request *)context; + uint64_t tick = beginAt; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, + "READ | REQ %7u | LCA %" PRIu64 " + %" PRIu64 " | BYTE %" PRIu64 + " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp, pReq->offset, + pReq->length); + + ICL::Request reqInternal(*pReq); + pICL->read(reqInternal, tick); + + stat.request[0]++; + stat.iosize[0] += pReq->length; + updateBusyTime(0, beginAt, tick); + updateBusyTime(2, beginAt, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::READ, doRead, new Request(req)); +} + +void HIL::write(Request &req) { + + DMAFunction doWrite = [this](uint64_t beginAt, void *context) { + auto pReq = (Request *)context; + uint64_t tick = beginAt; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, + "WRITE | REQ %7u | LCA %" PRIu64 " + %" PRIu64 " | BYTE %" PRIu64 + " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp, pReq->offset, + pReq->length); + + ICL::Request reqInternal(*pReq); + pICL->write(reqInternal, tick); + + stat.request[1]++; + stat.iosize[1] += pReq->length; + updateBusyTime(1, beginAt, tick); + updateBusyTime(2, beginAt, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::WRITE, doWrite, new Request(req)); +} + +void HIL::flush(Request &req) { + DMAFunction doFlush = [this](uint64_t tick, void *context) { + auto pReq = (Request *)context; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, "FLUSH | REQ %7u | LCA %" PRIu64 " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp); + + pICL->flush(pReq->range, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::FLUSH, doFlush, new Request(req)); +} + +void HIL::trim(Request &req) { + DMAFunction doFlush = [this](uint64_t tick, void *context) { + auto pReq = (Request *)context; + + pReq->reqID = ++reqCount; + + debugprint(LOG_HIL, "TRIM | REQ %7u | LCA %" PRIu64 " + %" PRIu64, + pReq->reqID, pReq->range.slpn, pReq->range.nlp); + + pICL->trim(pReq->range, tick); + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::FLUSH, doFlush, new Request(req)); +} + +void HIL::format(Request &req, bool erase) { + DMAFunction doFlush = [this, erase](uint64_t tick, void *context) { + auto pReq = (Request *)context; + + debugprint(LOG_HIL, "FORMAT| LCA %" PRIu64 " + %" PRIu64, pReq->reqID, + pReq->range.slpn, pReq->range.nlp); + + if (erase) { + pICL->format(pReq->range, tick); + } + else { + pICL->trim(pReq->range, tick); + } + + pReq->finishedAt = tick; + completionQueue.push(*pReq); + + updateCompletion(); + + delete pReq; + }; + + execute(CPU::HIL, CPU::FLUSH, doFlush, new Request(req)); +} + +void HIL::getLPNInfo(uint64_t &totalLogicalPages, uint32_t &logicalPageSize) { + pICL->getLPNInfo(totalLogicalPages, logicalPageSize); +} + +uint64_t HIL::getUsedPageCount(uint64_t lcaBegin, uint64_t lcaEnd) { + return pICL->getUsedPageCount(lcaBegin, lcaEnd); +} + +void HIL::updateBusyTime(int idx, uint64_t begin, uint64_t end) { + if (end <= stat.lastBusyAt[idx]) { + return; + } + + if (begin < stat.lastBusyAt[idx]) { + stat.busy[idx] += end - stat.lastBusyAt[idx]; + } + else { + stat.busy[idx] += end - begin; + } + + stat.lastBusyAt[idx] = end; +} + +void HIL::updateCompletion() { + if (completionQueue.size() > 0) { + if (lastScheduled != completionQueue.top().finishedAt) { + lastScheduled = completionQueue.top().finishedAt; + schedule(completionEvent, lastScheduled); + } + } +} + +void HIL::completion() { + uint64_t tick = getTick(); + + while (completionQueue.size() > 0) { + auto &req = completionQueue.top(); + + if (req.finishedAt <= tick) { + req.function(tick, req.context); + + completionQueue.pop(); + } + else { + break; + } + } + + updateCompletion(); +} + +void HIL::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "read.request_count"; + temp.desc = "Read request count"; + list.push_back(temp); + + temp.name = prefix + "read.bytes"; + temp.desc = "Read data size in byte"; + list.push_back(temp); + + temp.name = prefix + "read.busy"; + temp.desc = "Device busy time when read"; + list.push_back(temp); + + temp.name = prefix + "write.request_count"; + temp.desc = "Write request count"; + list.push_back(temp); + + temp.name = prefix + "write.bytes"; + temp.desc = "Write data size in byte"; + list.push_back(temp); + + temp.name = prefix + "write.busy"; + temp.desc = "Device busy time when write"; + list.push_back(temp); + + temp.name = prefix + "request_count"; + temp.desc = "Total request count"; + list.push_back(temp); + + temp.name = prefix + "bytes"; + temp.desc = "Total data size in byte"; + list.push_back(temp); + + temp.name = prefix + "busy"; + temp.desc = "Total device busy time"; + list.push_back(temp); + + pICL->getStatList(list, prefix); +} + +void HIL::getStatValues(std::vector &values) { + values.push_back(stat.request[0]); + values.push_back(stat.iosize[0]); + values.push_back(stat.busy[0]); + values.push_back(stat.request[1]); + values.push_back(stat.iosize[1]); + values.push_back(stat.busy[1]); + values.push_back(stat.request[0] + stat.request[1]); + values.push_back(stat.iosize[0] + stat.iosize[1]); + values.push_back(stat.busy[2]); + + pICL->getStatValues(values); +} + +void HIL::resetStatValues() { + memset(&stat, 0, sizeof(stat)); + + pICL->resetStatValues(); +} + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/hil.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/hil.hh new file mode 100644 index 0000000000..c5ba045ce0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/hil.hh @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_HIL__ +#define __HIL_HIL__ + +#include + +#include "icl/icl.hh" +#include "sim/dma_interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +class HIL : public StatObject { + private: + ConfigReader &conf; + ICL::ICL *pICL; + + uint64_t reqCount; + + uint64_t lastScheduled; + Event completionEvent; + std::priority_queue, Request> completionQueue; + + struct { + uint64_t request[2]; + uint64_t busy[3]; + uint64_t iosize[2]; + uint64_t lastBusyAt[3]; + } stat; + + void updateBusyTime(int, uint64_t, uint64_t); + void updateCompletion(); + void completion(); + + public: + HIL(ConfigReader &); + ~HIL(); + + void read(Request &); + void write(Request &); + void flush(Request &); + void trim(Request &); + + void format(Request &, bool); + + void getLPNInfo(uint64_t &, uint32_t &); + uint64_t getUsedPageCount(uint64_t, uint64_t); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/abstract_subsystem.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/abstract_subsystem.cc new file mode 100644 index 0000000000..1619ff2614 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/abstract_subsystem.cc @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/abstract_subsystem.hh" + +#include "hil/nvme/controller.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +AbstractSubsystem::AbstractSubsystem(Controller *c, ConfigData &cfg) + : pParent(c), cfgdata(cfg), conf(*cfg.pConfigReader) {} + +AbstractSubsystem::~AbstractSubsystem() {} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/abstract_subsystem.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/abstract_subsystem.hh new file mode 100644 index 0000000000..d2b816f252 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/abstract_subsystem.hh @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_ABSTRACT_SUBSYSTEM__ +#define __HIL_NVME_ABSTRACT_SUBSYSTEM__ + +#include "hil/nvme/namespace.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Controller; + +class AbstractSubsystem : public StatObject { + protected: + Controller *pParent; + + ConfigData &cfgdata; + ConfigReader &conf; + + public: + AbstractSubsystem(Controller *, ConfigData &); + virtual ~AbstractSubsystem(); + + virtual void init() = 0; + virtual void submitCommand(SQEntryWrapper &, RequestFunction) = 0; + virtual void getNVMCapacity(uint64_t &, uint64_t &) = 0; + virtual uint32_t validNamespaceCount() = 0; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/config.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/config.cc new file mode 100644 index 0000000000..e9e83b485b --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/config.cc @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +const char NAME_PCIE_GEN[] = "PCIEGeneration"; +const char NAME_PCIE_LANE[] = "PCIELane"; +const char NAME_AXI_BUS_WIDTH[] = "AXIBusWidth"; +const char NAME_AXI_CLOCK[] = "AXIClock"; +const char NAME_FIFO_UNIT[] = "FIFOTransferUnit"; +const char NAME_WORK_INTERVAL[] = "WorkInterval"; +const char NAME_MAX_REQUEST_COUNT[] = "MaxRequestCount"; +const char NAME_MAX_IO_CQUEUE[] = "MaxIOCQueue"; +const char NAME_MAX_IO_SQUEUE[] = "MaxIOSQueue"; +const char NAME_WRR_HIGH[] = "WRRHigh"; +const char NAME_WRR_MEDIUM[] = "WRRMedium"; +const char NAME_ENABLE_DEFAULT_NAMESPACE[] = "DefaultNamespace"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_ENABLE_DISK_IMAGE[] = "EnableDiskImage"; +const char NAME_STRICT_DISK_SIZE[] = "StrictSizeCheck"; +const char NAME_DISK_IMAGE_PATH[] = "DiskImageFile"; +const char NAME_USE_COW_DISK[] = "UseCopyOnWriteDisk"; + +Config::Config() { + pcieGen = PCIExpress::PCIE_3_X; + pcieLane = 4; + axiWidth = ARM::AXI::BUS_128BIT; + axiClock = 250000000; + fifoUnit = 4096; + workInterval = 50000; + maxRequestCount = 4; + maxIOCQueue = 16; + maxIOSQueue = 16; + wrrHigh = 2; + wrrMedium = 2; + lbaSize = 512; + defaultNamespace = 1; + enableDiskImage = false; + strictDiskSize = false; + useCopyOnWriteDisk = false; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_PCIE_GEN)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + pcieGen = PCIExpress::PCIE_1_X; + break; + case 1: + pcieGen = PCIExpress::PCIE_2_X; + break; + case 2: + pcieGen = PCIExpress::PCIE_3_X; + break; + default: + panic("Invalid PCI Express Generation"); + break; + } + } + else if (MATCH_NAME(NAME_PCIE_LANE)) { + pcieLane = (uint8_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_AXI_BUS_WIDTH)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + axiWidth = ARM::AXI::BUS_32BIT; + break; + case 1: + axiWidth = ARM::AXI::BUS_64BIT; + break; + case 2: + axiWidth = ARM::AXI::BUS_128BIT; + break; + case 3: + axiWidth = ARM::AXI::BUS_256BIT; + break; + case 4: + axiWidth = ARM::AXI::BUS_512BIT; + break; + case 5: + axiWidth = ARM::AXI::BUS_1024BIT; + break; + default: + panic("Invalid AXI Stream Bus Width"); + break; + } + } + else if (MATCH_NAME(NAME_AXI_CLOCK)) { + axiClock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FIFO_UNIT)) { + fifoUnit = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WORK_INTERVAL)) { + workInterval = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_REQUEST_COUNT)) { + maxRequestCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_IO_CQUEUE)) { + maxIOCQueue = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_IO_SQUEUE)) { + maxIOSQueue = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WRR_HIGH)) { + wrrHigh = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WRR_MEDIUM)) { + wrrMedium = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DEFAULT_NAMESPACE)) { + defaultNamespace = (uint16_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DISK_IMAGE)) { + enableDiskImage = convertBool(value); + } + else if (MATCH_NAME(NAME_STRICT_DISK_SIZE)) { + strictDiskSize = convertBool(value); + } + else if (strncmp(name, NAME_DISK_IMAGE_PATH, strlen(NAME_DISK_IMAGE_PATH)) == + 0) { + uint16_t index = + (uint16_t)strtoul(name + strlen(NAME_DISK_IMAGE_PATH), nullptr, 10); + + if (index > 0) { + auto find = diskImagePaths.find(index); + + if (find == diskImagePaths.end()) { + diskImagePaths.insert({index, value}); + } + else { + find->second = value; + } + } + } + else if (MATCH_NAME(NAME_USE_COW_DISK)) { + useCopyOnWriteDisk = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (popcount(lbaSize) != 1 || lbaSize < 512) { + panic("Invalid LBA size"); + } + if (maxRequestCount == 0) { + panic("MaxRequestCount should be larger then 0"); + } + if (fifoUnit > 4096) { + panic("FIFOTransferUnit should be less than or equal to 4096"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case NVME_PCIE_GEN: + ret = pcieGen; + break; + case NVME_AXI_BUS_WIDTH: + ret = axiWidth; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case NVME_PCIE_LANE: + ret = pcieLane; + break; + case NVME_AXI_CLOCK: + ret = axiClock; + break; + case NVME_FIFO_UNIT: + ret = fifoUnit; + break; + case NVME_WORK_INTERVAL: + ret = workInterval; + break; + case NVME_MAX_REQUEST_COUNT: + ret = maxRequestCount; + break; + case NVME_MAX_IO_CQUEUE: + ret = maxIOCQueue; + break; + case NVME_MAX_IO_SQUEUE: + ret = maxIOSQueue; + break; + case NVME_WRR_HIGH: + ret = wrrHigh; + break; + case NVME_WRR_MEDIUM: + ret = wrrMedium; + break; + case NVME_ENABLE_DEFAULT_NAMESPACE: + ret = defaultNamespace; + break; + case NVME_LBA_SIZE: + ret = lbaSize; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret(""); + + if (idx >= NVME_DISK_IMAGE_PATH) { + idx -= NVME_DISK_IMAGE_PATH; + + auto find = diskImagePaths.find((uint16_t)idx); + + if (find != diskImagePaths.end()) { + ret = find->second; + } + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case NVME_ENABLE_DISK_IMAGE: + ret = enableDiskImage; + break; + case NVME_STRICT_DISK_SIZE: + ret = strictDiskSize; + break; + case NVME_USE_COW_DISK: + ret = useCopyOnWriteDisk; + break; + } + + return ret; +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/config.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/config.hh new file mode 100644 index 0000000000..266ad35102 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/config.hh @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_CONFIG__ +#define __HIL_NVME_CONFIG__ + +#include + +#include "sim/base_config.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +typedef enum { + NVME_PCIE_GEN, + NVME_PCIE_LANE, + NVME_AXI_BUS_WIDTH, + NVME_AXI_CLOCK, + NVME_FIFO_UNIT, + NVME_WORK_INTERVAL, + NVME_MAX_REQUEST_COUNT, + NVME_MAX_IO_CQUEUE, + NVME_MAX_IO_SQUEUE, + NVME_WRR_HIGH, + NVME_WRR_MEDIUM, + NVME_ENABLE_DEFAULT_NAMESPACE, + NVME_LBA_SIZE, + NVME_ENABLE_DISK_IMAGE, + NVME_STRICT_DISK_SIZE, + NVME_DISK_IMAGE_PATH, + NVME_USE_COW_DISK +} NVME_CONFIG; + +class Config : public BaseConfig { + private: + PCIExpress::PCIE_GEN pcieGen; //!< Default: PCIE_3_X + uint8_t pcieLane; //!< Default: 4 + ARM::AXI::BUS_WIDTH axiWidth; //!< Default: BUS_128BIT + uint64_t axiClock; //!< Default: 250000000 (250MHz) + uint64_t fifoUnit; //!< Default: 4096 + uint64_t workInterval; //!< Default: 50000 (50ns) + uint64_t maxRequestCount; //!< Default: 4 + uint16_t maxIOCQueue; //!< Default: 16 + uint16_t maxIOSQueue; //!< Default: 16 + uint16_t wrrHigh; //!< Default: 2 + uint16_t wrrMedium; //!< Default: 2 + uint64_t lbaSize; //!< Default: 512 + uint16_t defaultNamespace; //!< Default: 1 + bool enableDiskImage; //!< Default: False + bool strictDiskSize; //!< Default: False + bool useCopyOnWriteDisk; //!< Default: False + std::unordered_map diskImagePaths; //!< Default: "" + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/controller.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/controller.cc new file mode 100644 index 0000000000..36db1252b2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/controller.cc @@ -0,0 +1,1839 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/controller.hh" + +#include +#include + +#include "hil/nvme/interface.hh" +#include "hil/nvme/ocssd.hh" +#include "hil/nvme/subsystem.hh" +#include "util/algorithm.hh" +#include "util/fifo.hh" +#include "util/interface.hh" + +#define BOOLEAN_STRING(b) ((b) ? "true" : "false") + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +RegisterTable::_RegisterTable() { + memset(data, 0, 64); +} + +Controller::Controller(Interface *intrface, ConfigReader &c) + : pParent(intrface), + adminQueueInited(false), + interruptMask(0), + shutdownReserved(false), + aggregationTime(0), + aggregationThreshold(0), + conf(c) { + ARM::AXI::BUS_WIDTH axiWidth; + uint64_t axiClock; + + // Get AXI setting + axiWidth = (ARM::AXI::BUS_WIDTH)conf.readInt(CONFIG_NVME, NVME_AXI_BUS_WIDTH); + axiClock = conf.readUint(CONFIG_NVME, NVME_AXI_CLOCK); + + // Allocate array for Command Queues + cqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_CQUEUE) + 1; + sqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_SQUEUE) + 1; + + ppCQueue = (CQueue **)calloc(cqsize, sizeof(CQueue *)); + ppSQueue = (SQueue **)calloc(sqsize, sizeof(SQueue *)); + + // [Bits ] Name : Description : Current Setting + // [63:56] Reserved + // [55:52] MPSMZX: Memory Page Size Maximum : 2^14 Bytes + // [51:48] MPSMIN: Memory Page Size Minimum : 2^12 Bytes + // [47:45] Reserved + // [44:37] CSS : Command Sets Supported : NVM command set + // [36:36] NSSRS : NVM Subsystem Reset Supported : No + // [35:32] DSTRD : Doorbell Stride : 0 (4 bytes) + // [31:24] TO : Timeout : 40 * 500ms + // [23:19] Reserved + // [18:17] AMS : Arbitration Mechanism Supported : Weighted Round Robin + // [16:16] CQR : Contiguous Queues Required : Yes + // [15:00] MQES : Maximum Queue Entries Supported : 4096 Entries + registers.capabilities = 0x0020002028010FFF; + registers.version = 0x00010201; // NVMe 1.2.1 + + FIFOParam fifoParam; + + // See Xilinx Gen3 Integrated Block for PCIe + fifoParam.rqSize = 8192; + fifoParam.wqSize = 8192; + fifoParam.transferUnit = conf.readUint(CONFIG_NVME, NVME_FIFO_UNIT); + fifoParam.latency = [](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(250000000, ARM::AXI::BUS_128BIT, + size); + }; + + pcieFIFO = new FIFO(pParent, fifoParam); + + if (axiWidth * axiClock == (uint64_t)250000000 * ARM::AXI::BUS_128BIT) { + // We don't need interconnect FIFO + interconnect = pcieFIFO; + pcieFIFO = nullptr; // Prevent double delete(free) + } + else { + fifoParam.latency = [axiWidth, axiClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(axiClock, axiWidth, size); + }; + + interconnect = new FIFO(pcieFIFO, fifoParam); + } + + cfgdata.pConfigReader = &c; + cfgdata.pInterface = interconnect; + cfgdata.maxQueueEntry = (registers.capabilities & 0xFFFF) + 1; + + workEvent = allocate([this](uint64_t) { work(); }); + requestEvent = allocate([this](uint64_t now) { handleRequest(now); }); + completionEvent = allocate([this](uint64_t) { completion(); }); + requestCounter = 0; + maxRequest = conf.readUint(CONFIG_NVME, NVME_MAX_REQUEST_COUNT); + workInterval = conf.readUint(CONFIG_NVME, NVME_WORK_INTERVAL); + requestInterval = workInterval / maxRequest; + + // Which subsystem should we use + uint16_t vid, ssvid; + + bUseOCSSD = false; + pParent->getVendorID(vid, ssvid); + + if (vid == OCSSD_VENDOR) { + bUseOCSSD = true; + + switch (ssvid) { + case OCSSD_SSVID_1_2: + pSubsystem = new OpenChannelSSD12(this, cfgdata); + + break; + case OCSSD_SSVID_2_0: + pSubsystem = new OpenChannelSSD20(this, cfgdata); + + break; + default: + panic("nvme_ctrl: Invalid SSVID for Open-Channel SSD"); + + break; + } + } + else { + pSubsystem = new Subsystem(this, cfgdata); + } + + // Initialize Subsystem + pSubsystem->init(); +} + +Controller::~Controller() { + delete pSubsystem; + + for (uint16_t i = 0; i < cqsize; i++) { + if (ppCQueue[i]) { + delete ppCQueue[i]; + } + } + + for (uint16_t i = 0; i < sqsize; i++) { + if (ppSQueue[i]) { + delete ppSQueue[i]; + } + } + + free(ppCQueue); + free(ppSQueue); + + delete interconnect; + delete pcieFIFO; +} + +void Controller::readRegister(uint64_t offset, uint64_t size, uint8_t *buffer, + uint64_t &) { + registers.interruptMaskSet = interruptMask; + registers.interruptMaskClear = interruptMask; + + memcpy(buffer, registers.data + offset, size); + + switch (offset) { + case REG_CONTROLLER_CAPABILITY: + case REG_CONTROLLER_CAPABILITY + 4: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Controller Capabilities"); + break; + case REG_VERSION: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Version"); + break; + case REG_INTERRUPT_MASK_SET: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Interrupt Mask Set"); + break; + case REG_INTERRUPT_MASK_CLEAR: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Interrupt Mask Clear"); + break; + case REG_CONTROLLER_CONFIG: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Controller Configuration"); + break; + case REG_CONTROLLER_STATUS: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Controller Status"); + break; + case REG_NVM_SUBSYSTEM_RESET: + debugprint(LOG_HIL_NVME, "BAR0 | READ | NVM Subsystem Reset"); + break; + case REG_ADMIN_QUEUE_ATTRIBUTE: + debugprint(LOG_HIL_NVME, "BAR0 | READ | Admin Queue Attributes"); + break; + case REG_ADMIN_SQUEUE_BASE_ADDR: + case REG_ADMIN_SQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Admin Submission Queue Base Address"); + break; + case REG_ADMIN_CQUEUE_BASE_ADDR: + case REG_ADMIN_CQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Admin Completion Queue Base Address"); + break; + case REG_CMB_LOCATION: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Controller Memory Buffer Location"); + break; + case REG_CMB_SIZE: + debugprint(LOG_HIL_NVME, + "BAR0 | READ | Controller Memory Buffer Size"); + break; + } + + if (size == 4) { + debugprint(LOG_HIL_NVME, "DMAPORT | READ | DATA %08" PRIX32, + *(uint32_t *)buffer); + } + else { + debugprint(LOG_HIL_NVME, "DMAPORT | READ | DATA %016" PRIX64, + *(uint64_t *)buffer); + } +} + +void Controller::writeRegister(uint64_t offset, uint64_t size, uint8_t *buffer, + uint64_t &) { + static DMAFunction empty = [](uint64_t, void *) {}; + uint32_t uiTemp32; + uint64_t uiTemp64; + + if (size == 4) { + memcpy(&uiTemp32, buffer, 4); + + switch (offset) { + case REG_INTERRUPT_MASK_SET: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Interrupt Mask Set"); + + interruptMask |= uiTemp32; + + break; + case REG_INTERRUPT_MASK_CLEAR: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Interrupt Mask Clear"); + + interruptMask &= ~uiTemp32; + + break; + case REG_CONTROLLER_CONFIG: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Controller Configuration"); + + registers.configuration &= 0xFF00000E; + registers.configuration |= (uiTemp32 & 0x00FFFFF1); + + // Update entry size + sqstride = (int)powf(2.f, (registers.configuration & 0x000F0000) >> 16); + cqstride = (int)powf(2.f, (registers.configuration & 0x00F00000) >> 20); + + // Update Memory Page Size + cfgdata.memoryPageSizeOrder = + ((registers.configuration & 0x780) >> 7) + 11; // CC.MPS + 12 - 1 + cfgdata.memoryPageSize = + (int)powf(2.f, cfgdata.memoryPageSizeOrder + 1); + + // Update Arbitration Mechanism + arbitration = (registers.configuration & 0x00003800) >> 11; + + // Apply to admin queue + if (ppCQueue[0]) { + ppCQueue[0]->setBase( + new PRPList(cfgdata, empty, nullptr, + registers.adminCQueueBaseAddress, + ppCQueue[0]->getSize() * cqstride, true), + cqstride); + } + if (ppSQueue[0]) { + ppSQueue[0]->setBase( + new PRPList(cfgdata, empty, nullptr, + registers.adminSQueueBaseAddress, + ppSQueue[0]->getSize() * sqstride, true), + sqstride); + } + + // Shotdown notification + if (registers.configuration & 0x0000C000) { + registers.status &= 0xFFFFFFF2; // RDY = 1 + registers.status |= 0x00000005; // Shutdown processing occurring + + shutdownReserved = true; + } + // If EN = 1, Set CSTS.RDY = 1 + else if (registers.configuration & 0x00000001) { + registers.status |= 0x00000001; + + schedule(workEvent, getTick() + workInterval); + } + // If EN = 0, Set CSTS.RDY = 0 + else { + registers.status &= 0xFFFFFFFE; + + deschedule(workEvent); + } + + break; + case REG_CONTROLLER_STATUS: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Controller Status"); + + // Clear NSSRO if set + if (uiTemp32 & 0x00000010) { + registers.status &= 0xFFFFFFEF; + } + + break; + case REG_NVM_SUBSYSTEM_RESET: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | NVM Subsystem Reset"); + + registers.subsystemReset = uiTemp32; + + // FIXME: If NSSR is same as NVMe(0x4E564D65), do NVMe Subsystem reset + // (when CAP.NSSRS is 1) + break; + case REG_ADMIN_QUEUE_ATTRIBUTE: + debugprint(LOG_HIL_NVME, "BAR0 | WRITE | Admin Queue Attributes"); + + registers.adminQueueAttributes &= 0xF000F000; + registers.adminQueueAttributes |= (uiTemp32 & 0x0FFF0FFF); + + break; + case REG_ADMIN_CQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Completion Queue Base Address | L"); + + memcpy(&(registers.adminCQueueBaseAddress), buffer, 4); + adminQueueInited++; + + break; + case REG_ADMIN_CQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Completion Queue Base Address | H"); + + memcpy(((uint8_t *)&(registers.adminCQueueBaseAddress)) + 4, buffer, 4); + adminQueueInited++; + + break; + case REG_ADMIN_SQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Submission Queue Base Address | L"); + memcpy(&(registers.adminSQueueBaseAddress), buffer, 4); + adminQueueInited++; + + break; + case REG_ADMIN_SQUEUE_BASE_ADDR + 4: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Submission Queue Base Address | H"); + memcpy(((uint8_t *)&(registers.adminSQueueBaseAddress)) + 4, buffer, 4); + adminQueueInited++; + + break; + default: + panic("nvme_ctrl: Write on read only register"); + break; + } + + debugprint(LOG_HIL_NVME, "DMAPORT | WRITE | DATA %08" PRIX32, uiTemp32); + } + else if (size == 8) { + memcpy(&uiTemp64, buffer, 8); + + switch (offset) { + case REG_ADMIN_CQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Completion Queue Base Address"); + + registers.adminCQueueBaseAddress = uiTemp64; + adminQueueInited += 2; + + break; + case REG_ADMIN_SQUEUE_BASE_ADDR: + debugprint(LOG_HIL_NVME, + "BAR0 | WRITE | Admin Submission Queue Base Address"); + + registers.adminSQueueBaseAddress = uiTemp64; + adminQueueInited += 2; + + break; + default: + panic("nvme_ctrl: Write on read only register"); + break; + } + + debugprint(LOG_HIL_NVME, "DMAPORT | WRITE | DATA %016" PRIX64, uiTemp64); + } + else { + panic("nvme_ctrl: Invalid read size(%d) on controller register", size); + } + + if (adminQueueInited == 4) { + uint16_t entrySize = 0; + + adminQueueInited = 0; + + entrySize = ((registers.adminQueueAttributes & 0x0FFF0000) >> 16) + 1; + ppCQueue[0] = new CQueue(0, true, 0, entrySize); + + debugprint(LOG_HIL_NVME, "CQ 0 | CREATE | Entry size %d", entrySize); + + entrySize = (registers.adminQueueAttributes & 0x0FFF) + 1; + ppSQueue[0] = new SQueue(0, 0, 0, entrySize); + + debugprint(LOG_HIL_NVME, "SQ 0 | CREATE | Entry size %d", entrySize); + } +} // namespace NVMe + +void Controller::ringCQHeadDoorbell(uint16_t qid, uint16_t head, uint64_t &) { + CQueue *pQueue = ppCQueue[qid]; + + if (pQueue) { + uint16_t oldhead = pQueue->getHead(); + uint32_t oldcount = pQueue->getItemCount(); + + pQueue->setHead(head); + + debugprint(LOG_HIL_NVME, + "CQ %-5d| Completion Queue Head Doorbell | Item count in queue " + "%d -> %d | head %d -> %d | tail %d", + qid, oldcount, pQueue->getItemCount(), oldhead, + pQueue->getHead(), pQueue->getTail()); + + if (pQueue->interruptEnabled()) { + clearInterrupt(pQueue->getInterruptVector()); + } + } +} + +void Controller::ringSQTailDoorbell(uint16_t qid, uint16_t tail, uint64_t &) { + SQueue *pQueue = ppSQueue[qid]; + + if (pQueue) { + uint16_t oldtail = pQueue->getTail(); + uint32_t oldcount = pQueue->getItemCount(); + + pQueue->setTail(tail); + + debugprint(LOG_HIL_NVME, + "SQ %-5d| Submission Queue Tail Doorbell | Item count in queue " + "%d -> %d | head %d | tail %d -> %d", + qid, oldcount, pQueue->getItemCount(), pQueue->getHead(), + oldtail, pQueue->getTail()); + } +} + +void Controller::clearInterrupt(uint16_t interruptVector) { + uint16_t notFinished = 0; + + // Check all queues associated with same interrupt vector are processed + for (uint16_t i = 0; i < cqsize; i++) { + if (ppCQueue[i]) { + if (ppCQueue[i]->getInterruptVector() == interruptVector) { + notFinished += ppCQueue[i]->getItemCount(); + } + } + } + + // Update interrupt + updateInterrupt(interruptVector, notFinished > 0); +} + +void Controller::updateInterrupt(uint16_t interruptVector, bool post) { + pParent->updateInterrupt(interruptVector, post); +} + +int Controller::createCQueue(uint16_t cqid, uint16_t size, uint16_t iv, + bool ien, bool pc, uint64_t prp1, + DMAFunction &func, void *context) { + int ret = 1; // Invalid Queue ID + CPUContext *pContext = + new CPUContext(func, context, CPU::NVME__CONTROLLER, CPU::CREATE_CQ); + + if (ppCQueue[cqid] == NULL) { + ppCQueue[cqid] = new CQueue(iv, ien, cqid, size); + ppCQueue[cqid]->setBase( + new PRPList(cfgdata, cpuHandler, pContext, prp1, size * cqstride, pc), + cqstride); + + ret = 0; + + debugprint(LOG_HIL_NVME, + "CQ %-5d| CREATE | Entry size %d | IV %04X | IEN %s | PC %s", + cqid, size, iv, BOOLEAN_STRING(ien), BOOLEAN_STRING(pc)); + + // Interrupt coalescing config + auto iter = aggregationMap.find(iv); + AggregationInfo info; + + info.valid = false; + info.nextTime = 0; + info.requestCount = 0; + + if (iter == aggregationMap.end()) { + aggregationMap.insert({iv, info}); + } + else { + iter->second = info; + } + } + + return ret; +} + +int Controller::createSQueue(uint16_t sqid, uint16_t cqid, uint16_t size, + uint8_t priority, bool pc, uint64_t prp1, + DMAFunction &func, void *context) { + int ret = 1; // Invalid Queue ID + CPUContext *pContext = + new CPUContext(func, context, CPU::NVME__CONTROLLER, CPU::CREATE_SQ); + + if (ppSQueue[sqid] == NULL) { + if (ppCQueue[cqid] != NULL) { + ppSQueue[sqid] = new SQueue(cqid, priority, sqid, size); + ppSQueue[sqid]->setBase( + new PRPList(cfgdata, cpuHandler, pContext, prp1, size * sqstride, pc), + sqstride); + + ret = 0; + + debugprint(LOG_HIL_NVME, + "SQ %-5d| CREATE | Entry size %d | Priority %d | PC %s", cqid, + size, priority, BOOLEAN_STRING(pc)); + } + else { + ret = 2; // Invalid CQueue + } + } + + return ret; +} + +int Controller::deleteCQueue(uint16_t cqid) { + int ret = 0; // Success + + if (ppCQueue[cqid] != NULL && cqid > 0) { + for (uint16_t i = 1; i < cqsize; i++) { + if (ppSQueue[i]) { + if (ppSQueue[i]->getCQID() == cqid) { + ret = 2; // Invalid Queue Deletion + break; + } + } + } + + if (ret == 0) { + uint16_t iv = ppCQueue[cqid]->getInterruptVector(); + bool sameIV = false; + + delete ppCQueue[cqid]; + ppCQueue[cqid] = NULL; + + debugprint(LOG_HIL_NVME, "CQ %-5d| DELETE", cqid); + + // Interrupt coalescing config + for (uint16_t i = 1; i < cqsize; i++) { + if (ppCQueue[i]) { + if (ppCQueue[i]->getInterruptVector() == iv) { + sameIV = true; + + break; + } + } + } + + if (!sameIV) { + aggregationMap.erase(aggregationMap.find(iv)); + } + } + } + else { + ret = 1; // Invalid Queue ID + } + + return ret; +} + +int Controller::deleteSQueue(uint16_t sqid) { + int ret = 0; // Success + + if (ppSQueue[sqid] != NULL && sqid > 0) { + // Create abort response + uint16_t sqHead = ppSQueue[sqid]->getHead(); + uint16_t status = 0x8000 | (TYPE_GENERIC_COMMAND_STATUS << 9) | + (STATUS_ABORT_DUE_TO_SQ_DELETE << 1); + + // Abort all commands in SQueue + for (auto iter = lSQFIFO.begin(); iter != lSQFIFO.end(); iter++) { + if (iter->sqID == sqid) { + CQEntryWrapper wrapper(*iter); + wrapper.entry.dword2.sqHead = sqHead; + wrapper.entry.dword3.status = status; + submit(wrapper); + + iter = lSQFIFO.erase(iter); + } + } + + // Delete SQueue + delete ppSQueue[sqid]; + ppSQueue[sqid] = NULL; + + debugprint(LOG_HIL_NVME, "SQ %-5d| DELETE", sqid); + } + else { + ret = 1; // Invalid Queue ID + } + + return ret; +} + +int Controller::abort(uint16_t sqid, uint16_t cid) { + int ret = 0; // Not aborted + uint16_t sqHead; + uint16_t status; + + for (auto iter = lSQFIFO.begin(); iter != lSQFIFO.end(); iter++) { + if (iter->sqID == sqid && iter->entry.dword0.commandID == cid) { + CQEntry entry; + + // Create abort response + sqHead = ppSQueue[sqid]->getHead(); + status = 0x8000 | (TYPE_GENERIC_COMMAND_STATUS << 9) | + (STATUS_ABORT_REQUESTED << 1); + + // Submit abort + CQEntryWrapper wrapper(*iter); + wrapper.entry.dword2.sqHead = sqHead; + wrapper.entry.dword3.status = status; + + submit(wrapper); + + // Remove + iter = lSQFIFO.erase(iter); + ret = 1; // Aborted + + break; + } + } + + return ret; +} + +void Controller::identify(uint8_t *data) { + uint16_t vid, ssvid; + uint64_t totalSize; + uint64_t unallocated; + + pParent->getVendorID(vid, ssvid); + pSubsystem->getNVMCapacity(totalSize, unallocated); + + unallocated = totalSize - unallocated; + + /** Controller Capabilities and Features **/ + { + // PCI Vendor ID + memcpy(data + 0x0000, &vid, 2); + + // PCI Subsystem Vendor ID + memcpy(data + 0x0002, &ssvid, 2); + + // Serial Number + memcpy(data + 0x0004, "00000000000000000000", 0x14); + + // Model Number + if (bUseOCSSD) { + memcpy(data + 0x0018, "SimpleSSD OCSSD Controller by CAMELab ", 0x28); + } + else { + memcpy(data + 0x0018, "SimpleSSD NVMe Controller by CAMELab ", 0x28); + } + + // Firmware Revision + memcpy(data + 0x0040, "02.01.03", 0x08); + + // Recommended Arbitration Burst + data[0x0048] = 0x00; + + // IEEE OUI Identifier + { + data[0x0049] = 0x00; + data[0x004A] = 0x00; + data[0x004B] = 0x00; + } + + // Controller Multi-Path I/O and Namespace Sharing Capabilities + // [Bits ] Description + // [07:04] Reserved + // [03:03] 1 for Asymmetric Namespace Access Reporting + // [02:02] 1 for SR-IOV Virtual Function, 0 for PCI (Physical) Function + // [01:01] 1 for more than one host may connected to NVM subsystem + // [00:00] 1 for NVM subsystem may has more than one NVM subsystem port + data[0x004C] = 0x00; + + // Maximum Data Transfer Size + data[0x004D] = 0x00; // No limit + + // Controller ID + { + data[0x004E] = 0x00; + data[0x004F] = 0x00; + } + + // Version + { + data[0x0050] = 0x01; + data[0x0051] = 0x04; + data[0x0052] = 0x00; + data[0x0053] = 0x00; + } // NVM Express 1.4 Compliant Controller + + // RTD3 Resume Latency + { + data[0x0054] = 0x00; + data[0x0055] = 0x00; + data[0x0056] = 0x00; + data[0x0057] = 0x00; + } // Not reported + + // RTD3 Enter Latency + { + data[0x0058] = 0x00; + data[0x0059] = 0x00; + data[0x005A] = 0x00; + data[0x005B] = 0x00; + } // Not repotred + + // Optional Asynchronous Events Supported + { + // [Bits ] Description + // [31:15] Reserved + // [14:14] 1 for Support Endurance Group Event Aggregate Log Page Change + // Notice + // [13:13] 1 for Support LBA Status Information Notice + // [12:12] 1 for Support Predictable Latency Event Aggregate Log Change + // Notice + // [11:11] 1 for Support Asymmetric Namespace Access Change Notice + // [10:10] Reserved + // [09:09] 1 for Support Firmware Activation Notice + // [08:08] 1 for Support Namespace Attributes Notice + // [07:00] Reserved + data[0x005C] = 0x00; + data[0x005D] = 0x00; + data[0x005E] = 0x00; + data[0x005F] = 0x00; + } + + // Controller Attributes + { + // [Bits ] Description + // [31:01] Reserved + // [09:09] 1 for Support UUID List + // [08:08] 1 for Support SQ Associations + // [07:07] 1 for Support Namespace Granularity + // [06:06] 1 for Traffic Based Keep Alive Support + // [05:05] 1 for Support Predictable Latency Mode + // [04:04] 1 for Support Endurance Group + // [03:03] 1 for Support Read Recovery Levels + // [02:02] 1 for Support NVM Sets + // [01:01] 1 for Support Non-Operational Power State Permissive Mode + // [00:00] 1 for Support 128-bit Host Identifier + data[0x0060] = 0x00; + data[0x0061] = 0x00; + data[0x0062] = 0x00; + data[0x0063] = 0x00; + } + + // Read Recovery Levels Supported + { + // [Bits ] Description + // [15:15] 1 for Read Recovery Level 15 - Fast Fail + // ... + // [04:04] 1 for Read Recovery Level 4 - Default + // ... + // [00:00] 1 for Read Recovery Level 0 + data[0x0064] = 0x00; + data[0x0065] = 0x00; + } + + memset(data + 0x0066, 0, 9); // Reserved + + // Controller Type + // [Value] Description + // [ 0h] Reserved (Controller Type not reported) + // [ 1h] I/O Controller + // [ 2h] Discovery Controller + // [ 3h] Administrative Controller + // [4h to FFh] Reserved + data[0x006F] = 0x01; + + // FRU Globally Unique Identifier + memset(data + 0x0070, 0, 16); + + // Command Retry Delay Time 1 + { + data[0x0080] = 0x00; + data[0x0081] = 0x00; + } + + // Command Retry Delay Time 2 + { + data[0x0082] = 0x00; + data[0x0083] = 0x00; + } + + // Command Retry Delay Time 3 + { + data[0x0084] = 0x00; + data[0x0085] = 0x00; + } + + memset(data + 0x0086, 0, 106); // Reserved + memset(data + 0x00F0, 0, 16); // See NVMe-MI Specification + } + + /** Admin Command Set Attributes & Optional Controller Capabilities **/ + { + // Optional Admin Command Support + { + // [Bits ] Description + // [15:10] Reserved + // [09:09] 1 for SupportGet LBA Status capability + // [08:08] 1 for Support Doorbell Buffer Config command + // [07:07] 1 for Support Virtualization Management command + // [06:06] 1 for Support NVMe-MI Send and NVMe-MI Receive commands + // [05:05] 1 for Support Directives + // [04:04] 1 for Support Device Self-Test command + // [03:03] 1 for Support Namespace Management and Namespace Attachment + // commands + // [02:02] 1 for Support Firmware Commit and Firmware Image Download + // commands + // [01:01] 1 for Support Format NVM command + // [00:00] 1 for Support Security Send and Security Receive commands + if (bUseOCSSD) { + data[0x0100] = 0x00; + } + else { + data[0x0100] = 0x0A; + } + data[0x0101] = 0x00; + } + + // Abort Command Limit + data[0x0102] = 0x03; // Recommanded value is 4 (3 + 1) + + // Asynchronous Event Request Limit + data[0x0103] = 0x03; // Recommanded value is 4 (3 + 1)) + + // Firmware Updates + // [Bits ] Description + // [07:05] Reserved + // [04:04] 1 for Support firmware activation without a reset + // [03:01] The number of firmware slot + // [00:00] 1 for First firmware slot is read only, 0 for read/write + data[0x0104] = 0x00; + + // Log Page Attributes + // [Bits ] Description + // [07:05] Reserved + // [04:04] 1 for Support Persisten Event log + // [03:03] 1 for Support Telemetry Host-Initiated and Telemetry Controller- + // Initiated log pages and Telemetry Log Notices + // [02:02] 1 for Support extended data for Get Log Page command + // [01:01] 1 for Support Command Effects log page + // [00:00] 1 for Support S.M.A.R.T. / Health information log page per + // namespace basis + data[0x0105] = 0x01; + + // Error Log Page Entries, 0's based value + data[0x0106] = 0x63; // 64 entries + + // Number of Power States Support, 0's based value + data[0x0107] = 0x00; // 1 states + + // Admin Vendor Specific Command Configuration + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for all vendor specific commands use the format at Figure 12. + // 0 for format is vendor specific + data[0x0108] = 0x00; + + // Autonomous Power State Transition Attributes + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for Support autonomous power state transitions + data[0x0109] = 0x00; + + // Warning Composite Temperature Threshold + { + data[0x010A] = 0x00; + data[0x010B] = 0x00; + } + + // Critical Composite Temperature Threshold + { + data[0x010C] = 0x00; + data[0x010D] = 0x00; + } + + // Maximum Time for Firmware Activation + { + data[0x010E] = 0x00; + data[0x010F] = 0x00; + } + + // Host Memory Buffer Preferred Size + { + data[0x0110] = 0x00; + data[0x0111] = 0x00; + data[0x0112] = 0x00; + data[0x0113] = 0x00; + } + + // Host Memory Buffer Minimum Size + { + data[0x0114] = 0x00; + data[0x0115] = 0x00; + data[0x0116] = 0x00; + data[0x0117] = 0x00; + } + + // Total NVM Capacity + { + memcpy(data + 0x118, &totalSize, 8); + memset(data + 0x120, 0, 8); + } + + // Unallocated NVM Capacity + { + memcpy(data + 0x118, &unallocated, 8); + memset(data + 0x120, 0, 8); + } + + // Replay Protected Memory Block Support + { + // [Bits ] Description + // [31:24] Access Size + // [23:16] Total Size + // [15:06] Reserved + // [05:03] Authentication Method + // [02:00] Number of RPMB Units + data[0x0138] = 0x00; + data[0x0139] = 0x00; + data[0x013A] = 0x00; + data[0x013B] = 0x00; + } + + // Extended Device Self-Test Time + { + data[0x013C] = 0x00; + data[0x013D] = 0x00; + } + + // Device Self-Test Options + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for Support only one device self-test operation in process at + // a time + data[0x013E] = 0x00; + + // Firmware Update Granularity + data[0x013F] = 0x00; + + // Keep Alive Support + { + data[0x0140] = 0x00; + data[0x0141] = 0x00; + } + + // Host Controlled Thermal Management Attributes + { + // [Bits ] Description + // [15:01] Reserved + // [00:00] 1 for Support host controlled thermal management + data[0x0142] = 0x00; + data[0x0143] = 0x00; + } + + // Minimum Thernam Management Temperature + { + data[0x0144] = 0x00; + data[0x0145] = 0x00; + } + + // Maximum Thernam Management Temperature + { + data[0x0146] = 0x00; + data[0x0147] = 0x00; + } + + // Sanitize Capabilities + { + // [Bits ] Description + // [31:30] No-Deallocate Modifies Media After Sanitize + // [29:29] No-Deallocate Inhibited + // [28:03] Reserved + // [02:02] 1 for Support Overwrite + // [01:01] 1 for Support Block Erase + // [00:00] 1 for Support Crypto Erase + data[0x0148] = 0x00; + data[0x0149] = 0x00; + data[0x014A] = 0x00; + data[0x014B] = 0x00; + } + + // Host Memory Buffer Minimum Descriptor Entry Size + { + data[0x014C] = 0x00; + data[0x014D] = 0x00; + data[0x014E] = 0x00; + data[0x014F] = 0x00; + } + + // Host Memory Maximum Descriptors Entries + { + data[0x0150] = 0x00; + data[0x0151] = 0x00; + } + + // NVM Set Identifier Maximum + { + data[0x0152] = 0x00; + data[0x0153] = 0x00; + } + + // Endurance Group Identifier Maximum + { + data[0x0154] = 0x00; + data[0x0155] = 0x00; + } + + // ANA Transition Time + data[0x0156] = 0x00; + + // Asymmetric Namespace Access Capabilities + // [Bits ] Description + // [07:07] 1 for Support non-zero ANAGRPID + // [06:06] 1 for ANAGRPID does not change while namespace is attached + // [05:05] Reserved + // [04:04] 1 for Support ANA Change state + // [03:03] 1 for Support ANA Persistent Loss state + // [02:02] 1 for Support ANA Inaccessible state + // [01:01] 1 for Support ANA Non-Optimized state + // [00:00] 1 for Support ANA Optimized state + data[0x157] = 0x00; + + // ANA Group Identifier Maximum + { + data[0x0158] = 0x00; + data[0x0159] = 0x00; + data[0x015A] = 0x00; + data[0x015B] = 0x00; + } + + // Number of ANA AGroup Identifiers + { + data[0x015C] = 0x00; + data[0x015D] = 0x00; + data[0x015E] = 0x00; + data[0x015F] = 0x00; + } + + // Persistent Event Log Size + { + data[0x0160] = 0x00; + data[0x0161] = 0x00; + data[0x0162] = 0x00; + data[0x0163] = 0x00; + } + + // Reserved + memset(data + 0x0164, 0, 156); + } + + /** NVM Command Set Attributes **/ + { + // Submission Queue Entry Size + // [Bits ] Description + // [07:04] Maximum Submission Queue Entry Size + // [03:00] Minimum Submission Queue Entry Size + data[0x0200] = 0x66; // 64Bytes, 64Bytes + + // Completion Queue Entry Size + // [Bits ] Description + // [07:04] Maximum Completion Queue Entry Size + // [03:00] Minimum Completion Queue Entry Size + data[0x0201] = 0x44; // 16Bytes, 16Bytes + + // Maximum Outstanding Commands + { + data[0x0202] = 0x00; + data[0x0203] = 0x00; + } + + // Number of Namespaces + // SimpleSSD supports infinite number of namespaces (0xFFFFFFFD) + // But kernel's DIV_ROUND_UP has problem when number is too big + // #define _KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + // This wrong macro introduces DIV_ROUND_UP(0xFFFFFFFD, 1024) to zero + // So we use 1024 here, for only one IDENTIFY NSLIST command + *(uint32_t *)(data + 0x0204) = 1024; + + // Optional NVM Command Support + { + // [Bits ] Description + // [15:08] Reserved + // [07:07] 1 for Support Verify command + // [06:06] 1 for Support Timestamp features + // [05:05] 1 for Support reservations + // [04:04] 1 for Support Save field in Set Features command and Select + // field in Get Features command + // [03:03] 1 for Support Write Zeros command + // [02:02] 1 for Support Dataset Management command + // [01:01] 1 for Support Write Uncorrectable command + // [00:00] 1 for Support Compare command + data[0x0208] = 0x05; + data[0x0209] = 0x00; + } + + // Fused Operation Support + { + // [Bits ] Description + // [15:01] Reserved + // [00:00] 1 for Support Compare and Write fused operation + data[0x020A] = 0x00; + data[0x020B] = 0x00; + } + + // Format NVM Attributes + // [Bits ] Description + // [07:03] Reserved + // [02:02] 1 for Support cryptographic erase + // [01:01] 1 for Support cryptographic erase performed on all namespaces, + // 0 for namespace basis + // [00:00] 1 for Format on specific namespace results on format on all + // namespaces, 0 for namespace basis + data[0x020C] = 0x00; + + // Volatile Write Cache + // [Bits ] Description + // [07:03] Reserved + // [02:01] Indicated Flush comand behavior if the NSID is 0xFFFFFFFF + // [00:00] 1 for volatile write cache is present + data[0x020D] = + conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE) ? 0x01 : 0x00; + data[0x020D] |= 0x06; + + // Atomic Write Unit Normal + { + data[0x020E] = 0x00; + data[0x020F] = 0x00; + } + + // Atomic Write Unit Power Fail + { + data[0x0210] = 0x00; + data[0x0211] = 0x00; + } + + // NVM Vendor Specific Command Configuration + // [Bits ] Description + // [07:01] Reserved + // [00:00] 1 for all vendor specific commands use the format at Figure 12. + // 0 for format is vendor specific + data[0x0212] = 0x00; + + // Namespace Write Protection Capabilities + // [Bits ] Description + // [07:03] Reserved + // [02:02] 1 for Support Permenant Write Protect state + // [01:01] 1 for Support Write Protect Until Power Cycle state + // [00:00] 1 for Support No Write Protect and Write Protect state + data[0x0213] = 0x00; + + // Atomic Compare & Write Unit + { + data[0x0214] = 0x00; + data[0x0215] = 0x00; + } + + // Reserved + memset(data + 0x0216, 0, 2); + + // SGL Support + { + // [Bits ] Description + // [31:22] Reserved + // [21:21] 1 for Support Ransport SGL Data Block + // [20:20] 1 for Support Address field in SGL Data Block + // [19:19] 1 for Support MPTR containing SGL descriptor + // [18:18] 1 for Support MPTR/DPTR containing SGL with larger than amount + // of data to be trasferred + // [17:17] 1 for Support byte aligned contiguous physical buffer of + // metadata is supported + // [16:16] 1 for Support SGL Bit Bucket descriptor + // [15:03] Reserved + // [02:02] 1 for Support Keyed SGL Data Block descriptor + // [01:01] Reserved + // [00:00] 1 for Support SGLs in NVM Command Set + data[0x0218] = 0x01; + data[0x0219] = 0x00; + data[0x021A] = 0x17; + data[0x021B] = 0x00; + } + + // Maximun Number of Allowed Namespaces + *(uint32_t *)(data + 0x021C) = 0; + + // Reserved + memset(data + 0x0220, 0, 224); + + // NVM Subsystem NVMe Qualified Name + { + memset(data + 0x300, 0, 0x100); + strncpy((char *)data + 0x0300, + "nqn.2014-08.org.nvmexpress:uuid:270a1c70-962c-4116-6f1e340b9321", + 0x44); + } + + // Reserved + memset(data + 0x0400, 0, 768); + + // NVMe over Fabric + memset(data + 0x0700, 0, 256); + } + + /** Power State Descriptors **/ + // Power State 0 + /// Descriptor + { + // Maximum Power + { + data[0x0800] = 0xC4; + data[0x0801] = 0x09; + } + + // Reserved + data[0x0802] = 0x00; + + // [Bits ] Description + // [31:26] Reserved + // [25:25] Non-Operational State + // [24:24] Max Power Scale + data[0x0803] = 0x00; + + // Entry Latency + { + data[0x0804] = 0x00; + data[0x0805] = 0x00; + data[0x0806] = 0x00; + data[0x0807] = 0x00; + } + + // Exit Latency + { + data[0x0808] = 0x00; + data[0x0809] = 0x00; + data[0x080A] = 0x00; + data[0x080B] = 0x00; + } + + // [Bits ] Description + // [103:101] Reserved + // [100:096] Relative Read Throughput + data[0x080C] = 0x00; + + // [Bits ] Description + // [111:109] Reserved + // [108:104] Relative Read Latency + data[0x080D] = 0x00; + + // [Bits ] Description + // [119:117] Reserved + // [116:112] Relative Write Throughput + data[0x080E] = 0x00; + + // [Bits ] Description + // [127:125] Reserved + // [124:120] Relative Write Latency + data[0x080E] = 0x00; + + // Idle Power + { + data[0x080F] = 0x00; + data[0x0810] = 0x00; + } + + // [Bits ] Description + // [151:150] Idle Power Scale + // [149:144] Reserved + data[0x0811] = 0x00; + + // Reserved + data[0x0812] = 0x00; + + // Active Power + { + data[0x0813] = 0x00; + data[0x0814] = 0x00; + } + + // [Bits ] Description + // [183:182] Active Power Scale + // [181:179] Reserved + // [178:176] Active Power Workload + data[0x0815] = 0x00; + + // Reserved + memset(data + 0x0816, 0, 9); + } + + // PSD1 ~ PSD31 + memset(data + 0x0820, 0, 992); + + // Vendor specific area + memset(data + 0x0C00, 0, 1024); +} + +void Controller::setCoalescingParameter(uint8_t time, uint8_t thres) { + debugprint(LOG_HIL_NVME, + "INTR | Update coalescing parameters | TIME %u | THRES %u", + time, thres); + + aggregationTime = time * 100000000; + aggregationThreshold = thres; +} + +void Controller::getCoalescingParameter(uint8_t *time, uint8_t *thres) { + if (time) { + *time = aggregationTime / 100000000; + } + if (thres) { + *thres = aggregationThreshold; + } +} + +void Controller::setCoalescing(uint16_t iv, bool enable) { + auto iter = aggregationMap.find(iv); + + if (iter != aggregationMap.end()) { + debugprint(LOG_HIL_NVME, "INTR | %s interrupt coalescing | IV %u", + enable ? "Enable" : "Disable", iv); + + iter->second.valid = enable; + iter->second.nextTime = 0; + iter->second.requestCount = 0; + iter->second.pending = false; + } +} + +bool Controller::getCoalescing(uint16_t iv) { + auto iter = aggregationMap.find(iv); + + if (iter != aggregationMap.end()) { + return iter->second.valid; + } + + return false; +} + +void Controller::collectSQueue(DMAFunction &func, void *context) { + static uint16_t wrrHigh = conf.readUint(CONFIG_NVME, NVME_WRR_HIGH); + static uint16_t wrrMedium = conf.readUint(CONFIG_NVME, NVME_WRR_MEDIUM); + DMAContext *pContext = new DMAContext(func, context); + + static DMAFunction doQueue = [](uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + + delete pContext; + } + }; + + // Check ready + if (!(registers.status & 0x00000001)) { + return; + } + + // Round robin + if (arbitration == ROUND_ROBIN) { + SQueue *pQueue; + + uint16_t updated = 0; + + while (true) { + for (uint16_t i = 0; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + } + } + } + + if (updated == 0) { + break; + } + + updated = 0; + } + } + // Weighted round robin + else if (arbitration == WEIGHTED_ROUND_ROBIN) { + SQueue *pQueue; + + uint16_t updated = 0; + + // Collect all Admin Commands + pQueue = ppSQueue[0]; + + while (true) { + if (!checkQueue(pQueue, doQueue, pContext)) { + break; + } + else { + pContext->counter++; + } + } + + // Round robin all urgent command queues + while (true) { + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_URGENT) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + } + } + } + } + + if (updated == 0) { + break; + } + + updated = 0; + } + + // Weighted Round robin + uint32_t total_updated = 0; + + while (true) { + // Round robin all high-priority command queues + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_HIGH) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + total_updated++; + + if (updated == wrrHigh) { + updated = 0; + break; + } + } + } + } + } + + // Round robin all medium-priority command queues + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_MEDIUM) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + updated++; + total_updated++; + + if (updated == wrrMedium) { + updated = 0; + break; + } + } + } + } + } + + // Round robin all low-priority command queues + for (uint16_t i = 1; i < sqsize; i++) { + pQueue = ppSQueue[i]; + + if (pQueue) { + if (pQueue->getPriority() == PRIORITY_MEDIUM) { + if (checkQueue(pQueue, doQueue, pContext)) { + pContext->counter++; + total_updated++; + + break; + } + } + } + } + + // Check finished + if (total_updated == 0) { + break; + } + + total_updated = 0; + } + } + else { + panic("nvme_ctrl: Invalid arbitration method"); + } + + if (pContext->counter == 0) { + // No item in submission queues + func(getTick(), context); + + delete pContext; + } +} + +void Controller::work() { + DMAFunction queueFunction = [this](uint64_t now, void *) { + DMAFunction doRequest = [this](uint64_t, void *) { + DMAFunction handle = [this](uint64_t now, void *) { handleRequest(now); }; + + execute(CPU::NVME__CONTROLLER, CPU::HANDLE_REQUEST, handle); + }; + + lastWorkAt = now; + + // Check NVMe shutdown + if (shutdownReserved) { + deschedule(workEvent); + + registers.status &= 0xFFFFFFF2; // RDY = 0 + registers.status |= 0x00000008; // Shutdown processing complete + + shutdownReserved = false; + + lSQFIFO.clear(); + } + + // Call request event + requestCounter = 0; + + execute(CPU::NVME__CONTROLLER, CPU::COLLECT_SQ, doRequest); + }; + + // Check ready + if (!(registers.status & 0x00000001)) { + return; + } + + // Collect requests in SQs + CPUContext *pContext = + new CPUContext(queueFunction, nullptr, CPU::NVME__CONTROLLER, CPU::WORK); + + collectSQueue(cpuHandler, pContext); +} + +void Controller::handleRequest(uint64_t now) { + // Check SQFIFO + if (lSQFIFO.size() > 0) { + SQEntryWrapper *front = new SQEntryWrapper(lSQFIFO.front()); + lSQFIFO.pop_front(); + + // Process command + DMAFunction doSubmit = [this](uint64_t, void *context) { + SQEntryWrapper *req = (SQEntryWrapper *)context; + + pSubsystem->submitCommand( + *req, [this](CQEntryWrapper &response) { submit(response); }); + + delete req; + }; + + if (bUseOCSSD) { + execute(CPU::NVME__OCSSD, CPU::SUBMIT_COMMAND, doSubmit, front); + } + else { + execute(CPU::NVME__SUBSYSTEM, CPU::SUBMIT_COMMAND, doSubmit, front); + } + } + + // Call request event + requestCounter++; + + if (lSQFIFO.size() > 0 && requestCounter < maxRequest) { + schedule(requestEvent, now + requestInterval); + } + else { + schedule(workEvent, MAX(now + requestInterval, lastWorkAt + workInterval)); + } +} + +bool Controller::checkQueue(SQueue *pQueue, DMAFunction &func, void *context) { + struct QueueContext { + SQEntry entry; + SQueue *pQueue; + DMAFunction function; + void *context; + uint16_t oldhead; + + QueueContext(DMAFunction &f) : pQueue(nullptr), function(f) {} + }; + + QueueContext *queueContext = new QueueContext(func); + queueContext->pQueue = pQueue; + queueContext->context = context; + + DMAFunction doRead = [this](uint64_t now, void *context) { + QueueContext *pContext = (QueueContext *)context; + + lSQFIFO.push_back(SQEntryWrapper( + pContext->entry, pContext->pQueue->getID(), pContext->pQueue->getCQID(), + pContext->pQueue->getHead(), pContext->oldhead)); + pContext->function(now, pContext->context); + + delete pContext; + }; + + if (pQueue->getItemCount() > 0) { + queueContext->oldhead = pQueue->getHead(); + pQueue->getData(&queueContext->entry, doRead, queueContext); + + return true; + } + else { + delete queueContext; + } + + return false; +} + +void Controller::submit(CQEntryWrapper &entry) { + CQueue *pQueue = ppCQueue[entry.cqID]; + + if (pQueue == NULL) { + panic("nvme_ctrl: Completion Queue not created! CQID %d", entry.cqID); + } + + // Set submit time + entry.submitAt = getTick(); + + // Enqueue with delay + auto iter = lCQFIFO.begin(); + + for (; iter != lCQFIFO.end(); iter++) { + if (iter->submitAt > entry.submitAt) { + break; + } + } + + lCQFIFO.insert(iter, entry); + + reserveCompletion(); +} + +void Controller::reserveCompletion() { + uint64_t tick = std::numeric_limits::max(); + bool valid = false; + + if (lCQFIFO.size() > 0) { + valid = true; + tick = lCQFIFO.front().submitAt; + } + + for (auto &iter : aggregationMap) { + if (iter.second.valid && iter.second.pending) { + if (!valid) { + valid = true; + tick = iter.second.nextTime; + } + else if (tick > iter.second.nextTime) { + tick = iter.second.nextTime; + } + } + } + + if (valid) { + schedule(completionEvent, tick); + } +} + +void Controller::completion() { + struct CompletionContext { + std::vector entryToPost; + std::vector ivToPost; + }; + + uint64_t tick = getTick(); + CQueue *pQueue = nullptr; + + DMAFunction doSubmit = [this](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + CompletionContext *pData = (CompletionContext *)pContext->context; + + pContext->counter--; + + if (pContext->counter == 0) { + DMAFunction send = [this](uint64_t, void *context) { + CompletionContext *pData = (CompletionContext *)context; + + if (pData->ivToPost.size() > 0) { + std::sort(pData->ivToPost.begin(), pData->ivToPost.end()); + auto end = + std::unique(pData->ivToPost.begin(), pData->ivToPost.end()); + + for (auto iter = pData->ivToPost.begin(); iter != end; iter++) { + // Update interrupt + updateInterrupt(*iter, true); + } + } + + reserveCompletion(); + + delete pData; + }; + + execute(CPU::NVME__CONTROLLER, CPU::COMPLETION, send, pData); + + delete pContext; + } + }; + + DMAContext *submitContext = new DMAContext(doSubmit); + CompletionContext *pData = new CompletionContext(); + + submitContext->context = pData; + + for (auto iter = lCQFIFO.begin(); iter != lCQFIFO.end();) { + if (iter->submitAt <= tick) { + // Copy CQ + pData->entryToPost.push_back(*iter); + + // Delete entry + iter = lCQFIFO.erase(iter); + } + else { + iter++; + } + } + + for (auto &iter : pData->entryToPost) { + pQueue = ppCQueue[iter.cqID]; + + submitContext->counter++; + pQueue->setData(&iter.entry, doSubmit, submitContext); + + // Collect interrupt vector + if (pQueue->interruptEnabled()) { + uint16_t iv = pQueue->getInterruptVector(); + bool post = true; + + if (iter.cqID > 0) { + // Interrupt Coalescing does not applied to admin queues + auto map = aggregationMap.find(iv); + + if (map != aggregationMap.end()) { + if (map->second.valid) { + map->second.requestCount++; + + if (iter.submitAt < map->second.nextTime && + map->second.requestCount <= aggregationThreshold) { + post = false; + map->second.pending = true; + } + + if (post) { + map->second.nextTime = tick + aggregationTime; + map->second.requestCount = 0; + } + } + } + } + + if (post) { + // Prepare for merge + pData->ivToPost.push_back(iv); + } + } + } + + for (auto &iter : aggregationMap) { + if (iter.second.valid && iter.second.nextTime <= tick && + iter.second.pending) { + iter.second.nextTime = tick + aggregationTime; + iter.second.requestCount = 0; + iter.second.pending = false; + + pData->ivToPost.push_back(iter.first); + } + } + + if (submitContext->counter == 0) { + delete pData; + delete submitContext; + } +} + +void Controller::getStatList(std::vector &list, std::string prefix) { + pSubsystem->getStatList(list, prefix); +} + +void Controller::getStatValues(std::vector &values) { + pSubsystem->getStatValues(values); +} + +void Controller::resetStatValues() { + pSubsystem->resetStatValues(); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/controller.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/controller.hh new file mode 100644 index 0000000000..d6f3267aef --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/controller.hh @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_CONTROLLER__ +#define __HIL_NVME_CONTROLLER__ + +#include +#include + +#include "hil/nvme/abstract_subsystem.hh" +#include "hil/nvme/def.hh" +#include "hil/nvme/dma.hh" +#include "hil/nvme/queue.hh" +#include "util/bitset.hh" +#include "util/def.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Interface; + +typedef union _RegisterTable { + uint8_t data[64]; + struct { + uint64_t capabilities; + uint32_t version; + uint32_t interruptMaskSet; + uint32_t interruptMaskClear; + uint32_t configuration; + uint32_t reserved; + uint32_t status; + uint32_t subsystemReset; + uint32_t adminQueueAttributes; + uint64_t adminSQueueBaseAddress; + uint64_t adminCQueueBaseAddress; + uint32_t memoryBufferLocation; + uint32_t memoryBufferSize; + }; + + _RegisterTable(); +} RegisterTable; + +typedef struct { + uint64_t nextTime; + uint32_t requestCount; + bool valid; + bool pending; +} AggregationInfo; + +class Controller : public StatObject { + private: + Interface *pParent; //!< NVMe::Interface passed from constructor + AbstractSubsystem *pSubsystem; //!< NVMe::Subsystem allocate in constructor + + bool bUseOCSSD; + + SimpleSSD::DMAInterface *pcieFIFO; + SimpleSSD::DMAInterface *interconnect; + + RegisterTable registers; //!< Table for NVMe Controller Registers + uint64_t sqstride; //!< Calculated SQ Stride + uint64_t cqstride; //!< Calculated CQ stride + uint8_t adminQueueInited; //!< Flag for initialization of Admin CQ/SQ + uint16_t arbitration; //!< Selected Arbitration Mechanism + uint32_t interruptMask; //!< Variable to store current interrupt mask + + uint32_t cqsize; + uint32_t sqsize; + CQueue **ppCQueue; //!< Completion Queue array + SQueue **ppSQueue; //!< Submission Queue array + + std::list lSQFIFO; //!< Internal FIFO queue for submission + std::list lCQFIFO; //!< Internal FIFO queue for completion + + bool shutdownReserved; + + uint64_t aggregationTime; + uint32_t aggregationThreshold; + std::unordered_map aggregationMap; + + ConfigData cfgdata; + ConfigReader &conf; + + Event workEvent; + Event requestEvent; + Event completionEvent; + uint32_t requestCounter; + uint32_t maxRequest; + uint64_t requestInterval; + uint64_t workInterval; + uint64_t lastWorkAt; + + bool checkQueue(SQueue *, DMAFunction &, void *); + + public: + Controller(Interface *, ConfigReader &); + ~Controller(); + + void readRegister(uint64_t, uint64_t, uint8_t *, uint64_t &); + void writeRegister(uint64_t, uint64_t, uint8_t *, uint64_t &); + void ringCQHeadDoorbell(uint16_t, uint16_t, uint64_t &); + void ringSQTailDoorbell(uint16_t, uint16_t, uint64_t &); + + void clearInterrupt(uint16_t); + void updateInterrupt(uint16_t, bool); + + int createCQueue(uint16_t, uint16_t, uint16_t, bool, bool, uint64_t, + DMAFunction &, void *); + int createSQueue(uint16_t, uint16_t, uint16_t, uint8_t, bool, uint64_t, + DMAFunction &, void *); + int deleteCQueue(uint16_t); + int deleteSQueue(uint16_t); + int abort(uint16_t, uint16_t); + void identify(uint8_t *); + void setCoalescingParameter(uint8_t, uint8_t); + void getCoalescingParameter(uint8_t *, uint8_t *); + void setCoalescing(uint16_t, bool); + bool getCoalescing(uint16_t); + + void collectSQueue(DMAFunction &, void *); + void handleRequest(uint64_t); + void work(); + + void submit(CQEntryWrapper &); + void reserveCompletion(); + void completion(); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/def.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/def.hh new file mode 100644 index 0000000000..8e67542568 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/def.hh @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_DEF__ +#define __HIL_NVME_DEF__ + +#include +#include + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +#define NSID_NONE 0x00000000 +#define NSID_LOWEST 0x00000001 +#define NSID_ALL 0xFFFFFFFF + +#define MAKE_SGL_ID(type, subtype) \ + (uint8_t)(((type << 4) & 0xF0) | (subtype & 0x0F)) +#define SGL_TYPE(id) (uint8_t)(id >> 4) +#define SGL_SUBTYPE(id) (uint8_t)(id & 0x0F) + +#define OCSSD_VENDOR 0x1D1D +#define OCSSD_SSVID_1_2 0x0102 +#define OCSSD_SSVID_2_0 0x0200 + +typedef union _HealthInfo { + uint8_t data[0x200]; + struct { + uint8_t status; + uint16_t temperature; + uint8_t availableSpare; + uint8_t spareThreshold; + uint8_t lifeUsed; + uint8_t reserved[26]; + uint64_t readL; + uint64_t readH; + uint64_t writeL; + uint64_t writeH; + uint64_t readCommandL; + uint64_t readCommandH; + uint64_t writeCommandL; + uint64_t writeCommandH; + }; + + _HealthInfo() { memset(data, 0, 0x200); } +} HealthInfo; + +typedef enum : uint8_t { + TYPE_DATA_BLOCK_DESCRIPTOR = 0x00, + TYPE_BIT_BUCKET_DESCRIPTOR = 0x01, + TYPE_SEGMENT_DESCRIPTOR = 0x02, + TYPE_LAST_SEGMENT_DESCRIPTOR = 0x03, + TYPE_KEYED_DATA_BLOCK_DESCRIPTOR = 0x04 +} SGL_DESCRIPTOR_TYPE; + +typedef enum : uint8_t { + SUBTYPE_ADDRESS = 0x00, + SUBTYPE_OFFSET = 0x01, + SUBTYPE_NVME_TRANSPORT_SPECIFIC = 0x02 +} SGL_DESCRIPTOR_SUBTYPE; + +typedef enum { + PRIORITY_URGENT, + PRIORITY_HIGH, + PRIORITY_MEDIUM, + PRIORITY_LOW +} SQUEUE_PRIORITY; + +typedef enum { + REG_CONTROLLER_CAPABILITY = 0x00, + REG_VERSION = 0x08, + REG_INTERRUPT_MASK_SET = 0x0C, + REG_INTERRUPT_MASK_CLEAR = 0x10, + REG_CONTROLLER_CONFIG = 0x14, + REG_CONTROLLER_STATUS = 0x1C, + REG_NVM_SUBSYSTEM_RESET = 0x20, + REG_ADMIN_QUEUE_ATTRIBUTE = 0x24, + REG_ADMIN_SQUEUE_BASE_ADDR = 0x28, + REG_ADMIN_CQUEUE_BASE_ADDR = 0x30, + REG_CMB_LOCATION = 0x38, + REG_CMB_SIZE = 0x3C, + REG_DOORBELL_BEGIN = 0x1000 +} COMMAND_REGISTER; + +typedef enum { ROUND_ROBIN, WEIGHTED_ROUND_ROBIN } ARBITRATION_METHOD; + +typedef enum { + OPCODE_PROPERTY_SET = 0x00, + OPCODE_CONNECT = 0x01, + OPCODE_PROPERTY_GET = 0x04, + OPCODE_AUTHENTICATION_SEND = 0x05, + OPCODE_AUTHENTICATION_RECEIVE = 0x06 +} FABRIC_OPCODE; + +typedef enum { + OPCODE_DELETE_IO_SQUEUE = 0x00, + OPCODE_CREATE_IO_SQUEUE = 0x01, + OPCODE_GET_LOG_PAGE = 0x02, + OPCODE_DELETE_IO_CQUEUE = 0x04, + OPCODE_CREATE_IO_CQUEUE = 0x05, + OPCODE_IDENTIFY = 0x06, + OPCODE_ABORT = 0x08, + OPCODE_SET_FEATURES = 0x09, + OPCODE_GET_FEATURES = 0x0A, + OPCODE_ASYNC_EVENT_REQ = 0x0C, + OPCODE_NAMESPACE_MANAGEMENT = 0x0D, + OPCODE_FIRMWARE_COMMIT = 0x10, + OPCODE_FIRMWARE_DOWNLOAD = 0x11, + OPCODE_DEVICE_SELF_TEST = 0x14, + OPCODE_NAMESPACE_ATTACHMENT = 0x15, + OPCODE_KEEPALIVE = 0x18, + OPCODE_DIRECTIVE_SEND = 0x19, + OPCODE_DIRECTIVE_RECEIVE = 0x1A, + OPCODE_VIRTUALIZATION_MANAGEMENT = 0x1C, + OPCODE_NVME_MI_SEND = 0x1D, + OPCODE_NVME_MI_RECEIVE = 0x1E, + OPCODE_DOORBELL_BUFFER_CONFIG = 0x7C, + OPCODE_FORMAT_NVM = 0x80, + OPCODE_SECURITY_SEND = 0x81, + OPCODE_SECURITY_RECEIVE = 0x82, + OPCODE_SANITIZE = 0x84, + + // OpenChannel SSD 1.2 + OPCODE_DEVICE_IDENTIFICATION = 0xE2, + OPCODE_SET_BAD_BLOCK_TABLE = 0xF1, + OPCODE_GET_BAD_BLOCK_TABLE = 0xF2, + + // OpenChannel SSD 2.0 + OPCODE_GEOMETRY = 0xE2 +} ADMIN_OPCODE; + +typedef enum { + OPCODE_FLUSH = 0x00, + OPCODE_WRITE = 0x01, + OPCODE_READ = 0x02, + OPCODE_WRITE_UNCORRECTABLE = 0x04, + OPCODE_COMPARE = 0x05, + OPCODE_WRITE_ZEROS = 0x08, + OPCODE_DATASET_MANAGEMEMT = 0x09, + OPCODE_RESERVATION_REGISTER = 0x0D, + OPCODE_RESERVATION_REPORT = 0x0E, + OPCODE_RESERVATION_ACQUIRE = 0x11, + OPCODE_RESERVATION_RELEASE = 0x15, + + // OpenChannel SSD 1.2 + OPCODE_PHYSICAL_BLOCK_ERASE = 0x90, + OPCODE_PHYSICAL_PAGE_WRITE, + OPCODE_PHYSICAL_PAGE_READ, + OPCODE_PHYSICAL_PAGE_RAW_WRITE = 0x95, + OPCODE_PHYSICAL_PAGE_RAW_READ, + + // OpenChannel SSD 2.0 + OPCODE_VECTOR_CHUNK_RESET = 0x90, + OPCODE_VECTOR_CHUNK_WRITE, + OPCODE_VECTOR_CHUNK_READ, + OPCODE_VECTOR_CHUNK_COPY +} NVM_OPCODE; + +typedef enum { + LOG_ERROR_INFORMATION = 0x01, + LOG_SMART_HEALTH_INFORMATION, + LOG_FIRMWARE_SLOT_INFORMATION, + LOG_CHANGED_NAMESPACE_LIST, + LOG_COMMAND_EFFECTS_LOG, + LOG_RESERVATION_NOTIFICATION = 0x80, + + // OpenChannel SSD + LOG_CHUNK_INFORMATION = 0xCA +} LOG_PAGE; + +typedef enum { + CNS_IDENTIFY_NAMESPACE = 0x00, + CNS_IDENTIFY_CONTROLLER = 0x01, + CNS_ACTIVE_NAMESPACE_LIST = 0x02, + CNS_ALLOCATED_NAMESPACE_LIST = 0x10, + CNS_IDENTIFY_ALLOCATED_NAMESPACE = 0x11, + CNS_ATTACHED_CONTROLLER_LIST = 0x12, + CNS_CONTROLLER_LIST = 0x13 +} IDENTIFY_CNS; + +typedef enum { + FEATURE_ARBITRATION = 0x01, + FEATURE_POWER_MANAGEMENT, + FEATURE_LBA_RANGE_TYPE, + FEATURE_TEMPERATURE_THRESHOLD, + FEATURE_ERROR_RECOVERY, + FEATURE_VOLATILE_WRITE_CACHE, + FEATURE_NUMBER_OF_QUEUES, + FEATURE_INTERRUPT_COALESCING, + FEATURE_INTERRUPT_VECTOR_CONFIGURATION, + FEATURE_WRITE_ATOMICITY_NORMAL, + FEATURE_ASYNC_EVENT_CONFIGURATION, + FEATURE_AUTO_POWER_STATE_TRANSITION, + FEATURE_HOST_MEMORY_BUFFER, + FEATURE_TIMESTAMP, + FEATURE_KEEPALIVE_TIMER, + FEATURE_HOST_CONTROLLED_THERMAL_MANAGEMENT, + FEATURE_NON_OPERATIONAL_POWER_STATE_CONFIG, + FEATURE_SOFTWARE_PROGRESS_MARKER = 0x80, + FEATURE_HOST_IDENTIFIER, + FEATURE_RESERVATION_NOTIFICATION_MASK, + FEATURE_RESERVATION_PERSISTANCE, + + // OpenChannel SSD + FEATURE_MEDIA_FEEDBACH = 0xCA +} FEATURE; + +typedef enum { + TYPE_GENERIC_COMMAND_STATUS, // -> NVME_STATUS_CODE + TYPE_COMMAND_SPECIFIC_STATUS, // -> NVME_ERROR_CODE + TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, +} STATUS_CODE_TYPE; + +typedef enum { + /** Generic Command Status **/ + STATUS_SUCCESS, + STATUS_INVALID_OPCODE, + STATUS_INVALID_FIELD, + STATUS_CID_CONFLICT, + STATUS_DATA_TRANSFER_ERROR, + STATUS_ABORT_DUE_TO_POWER_LOSS, + STATUS_INTERNAL_ERROR, + STATUS_ABORT_REQUESTED, + STATUS_ABORT_DUE_TO_SQ_DELETE, + STATUS_ABORT_DUE_TO_FAILED_FUSE, + STATUS_ABORT_DUE_TO_MISSING_FUSE, + STATUS_ABORT_INVALID_NAMESPACE, + STATUS_ABORT_INVALID_FORMAT = STATUS_ABORT_INVALID_NAMESPACE, + STATUS_COMMAND_SEQUENCE_ERROR, + STATUS_INVALID_SGL_SEGMENT_DESCRIPTOR, + STATUS_INVALID_NUMBER_OF_SGL_DESCRIPTOR, + STATUS_INVALID_DATA_SGL_LENGTH, + STATUS_INVALID_METADATA_SGL_LENGTH, + STATUS_INVALID_SGL_DESCRIPTOR_TYPE, + STATUS_INVALID_USE_OF_MEMORY_BUFFER, + STATUS_PRP_OFFSET_INVALID, + STATUS_ATOMIC_WRITE_UNIT_EXCEEDED, + STATUS_INVALID_SGL_OFFSET = 0x16, + STATUS_INVALID_SGL_SUB_TYPE, + STATUS_HOST_ID_INCONSISTENT_FORMAT, + STATUS_KEEPALIVE_TIMEOUT_EXPIRED, + STATUS_INVALID_KEEPALIVE_TIMEOUT, + + /** NVM Command Status **/ + STATUS_LBA_OUT_OF_RANGE = 0x80, + STATUS_CAPACITY_EXCEEDED, + STATUS_NAMESPACE_NOT_READY, + STATUE_RESERVATION_CONFLICT, + STATUS_FORMAT_IN_PROGRESS +} STATUS_CODE; + +typedef enum { + /** Generic Command Errors **/ + STATUS_INVALID_COMPLETION_QUEUE, + STATUS_INVALID_QUEUE_ID, + STATUS_INVALID_QUEUE_SIZE, + STATUS_ABORT_COMMAND_LIMIT_EXCEEDED, + STATUS_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, + STATUS_INVALID_FIRMWARE_SLOT, + STATUS_INVALID_FIRMWARE_IMAGE, + STATUS_INVALID_INTERRUPT_VECTOR, + STATUS_INVALID_LOG_PAGE, + STATUS_INVALID_FORMAT, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_CONVENTIONAL_RESET, + STATUS_INVALID_QUEUE_DELETE, + STATUS_FEATURE_ID_NOT_SAVEABLE, + STATUS_FEATURE_NOT_CHANGABLE, + STATUS_FEATURE_NOT_NAMESPACE_SPECIFIC, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_NVM_SUBSYSTEM_RESET, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_RESET, + STATUS_FIRMWARE_ACTIVATION_REQUIRES_MAXIMUM_TIME_VIOLATION, + STATUS_FIRMWARE_ACTIVATION_PROHIBITED, + STATUS_OVERLAPPING_RANGE, + STATUS_NAMESPACE_INSUFFICIENT_CAPACITY, + STATUS_NAMESPACE_ID_UNAVAILABLE, + STATUS_NAMESPACE_ALREADY_ATTACHED = 0x18, + STATUS_NAMESPACE_IS_PRIVATE, + STATUS_NAMESPACE_NOT_ATTACHED, + STATUS_THIN_PROVISIONING_NOT_SUPPORTED, + STATUS_CONTROLLER_LIST_INVALID, + + /** NVM Command Errors **/ + STATUS_ATTRIBUTE_CONFLICT = 0x80, + STATUS_INVALID_PROTECTION_INFORMATION, + STATUS_WRITE_TO_READ_ONLY_RANGE, +} ERROR_CODE; + +typedef enum { + /** I/O Command Media Errors **/ + STATUS_WRITE_FAULT = 0x80, + STATUS_UNRECOVERED_READ_ERROR, + STATUS_END_TO_END_GUARD_CHECK_ERROR, + STATUS_END_TO_END_APPLICATION_TAG_CHECK_ERROR, + STATUS_END_TO_END_REFERENCE_TAG_CHECK_ERROR, + STATUS_COMPARE_FAILURE, + STATUS_ACCESS_DENIED, + STATUS_DEALLOCATED_OR_UNWRITTEN_LOGICAL_BLOCK +} MEDIA_ERROR_CODE; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/dma.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/dma.cc new file mode 100644 index 0000000000..fba747aaf2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/dma.cc @@ -0,0 +1,543 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/dma.hh" + +#include "hil/nvme/controller.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +DMAInterface::DMAInterface(ConfigData &cfg, DMAFunction &f, void *c) + : pInterface(cfg.pInterface), + initFunction(f), + callCounter(0), + context(c), + dmaHandler(commonDMAHandler) { + immediateEvent = + allocate([this](uint64_t now) { initFunction(now, context); }); +} + +DMAInterface::~DMAInterface() {} + +void DMAInterface::commonDMAHandler(uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + delete pContext; + } +} + +PRP::PRP() : addr(0), size(0) {} + +PRP::PRP(uint64_t address, uint64_t s) : addr(address), size(s) {} + +PRPList::PRPList(ConfigData &cfg, DMAFunction &f, void *c, uint64_t prp1, + uint64_t prp2, uint64_t size) + : DMAInterface(cfg, f, c), totalSize(size), pagesize(cfg.memoryPageSize) { + bool immediate = true; + uint64_t prp1Size = getPRPSize(prp1); + uint64_t prp2Size = getPRPSize(prp2); + + // Determine PRP1 and PRP2 + if (totalSize <= pagesize) { + if (totalSize <= prp1Size) { + // PRP1 is PRP pointer, PRP2 is not used + prpList.push_back(PRP(prp1, totalSize)); + } + else { + // PRP1 is PRP pointer, PRP2 is PRP pointer + prpList.push_back(PRP(prp1, prp1Size)); + prpList.push_back(PRP(prp2, prp2Size)); + + if (prp1Size + prp2Size < totalSize) { + panic("prp_list: Invalid DPTR size"); + } + } + } + else if (totalSize <= pagesize * 2) { + if (prp1Size == pagesize) { + // PRP1 is PRP pointer, PRP2 is PRP pointer + prpList.push_back(PRP(prp1, prp1Size)); + prpList.push_back(PRP(prp2, prp2Size)); + + if (prp1Size + prp2Size < totalSize) { + panic("prp_list: Invalid DPTR size"); + } + } + else { + immediate = false; + + // PRP1 is PRP pointer, PRP2 is PRP list + prpList.push_back(PRP(prp1, prp1Size)); + getPRPListFromPRP(prp2, totalSize - prp1Size); + } + } + else { + immediate = false; + + // PRP1 is PRP pointer, PRP2 is PRP list + prpList.push_back(PRP(prp1, prp1Size)); + getPRPListFromPRP(prp2, totalSize - prp1Size); + } + + if (immediate) { + schedule(immediateEvent, getTick()); + } +} + +PRPList::PRPList(ConfigData &cfg, DMAFunction &f, void *c, uint64_t base, + uint64_t size, bool cont) + : DMAInterface(cfg, f, c), totalSize(size), pagesize(cfg.memoryPageSize) { + if (cont) { + prpList.push_back(PRP(base, size)); + + schedule(immediateEvent, getTick()); + } + else { + getPRPListFromPRP(base, size); + } +} + +PRPList::~PRPList() {} + +void PRPList::getPRPListFromPRP(uint64_t base, uint64_t size) { + static DMAFunction doRead = [](uint64_t now, void *context) { + DMAInitContext *pContext = (DMAInitContext *)context; + PRPList *pThis = (PRPList *)pContext->pThis; + uint64_t listPRP; + uint64_t listPRPSize; + uint64_t currentSize = 0; + + pThis->callCounter--; + + for (size_t i = 0; i < pContext->currentSize; i += 8) { + listPRP = *((uint64_t *)(pContext->buffer + i)); + listPRPSize = pThis->getPRPSize(listPRP); + currentSize += listPRPSize; + + if (listPRP == 0) { + panic("prp_list: Invalid PRP in PRP List"); + } + + pThis->prpList.push_back(PRP(listPRP, listPRPSize)); + + if (currentSize >= pContext->totalSize) { + break; + } + } + + free(pContext->buffer); + + if (currentSize < pContext->totalSize) { + // PRP list ends but size is not full + // Last item of PRP list is pointer of another PRP + // list + listPRP = pThis->prpList.back().addr; + pThis->prpList.pop_back(); + + pThis->getPRPListFromPRP(listPRP, pContext->totalSize - currentSize); + } + + if (pThis->callCounter == 0) { + // Everything is done + pThis->initFunction(now, pThis->context); + } + + delete pContext; + }; + + DMAInitContext *pContext = new DMAInitContext(); + + callCounter++; + + pContext->pThis = this; + pContext->totalSize = size; + + // Get PRP size + pContext->currentSize = getPRPSize(base); + + // Allocate buffer + pContext->buffer = (uint8_t *)malloc(pContext->currentSize); + + if (pContext->buffer) { + // Read PRP + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::NVME__PRPLIST, + CPU::GET_PRPLIST_FROM_PRP); + pInterface->dmaRead(base, pContext->currentSize, pContext->buffer, + cpuHandler, pCPU); + } + else { + delete pContext; + + panic("prp_list: ENOMEM"); + } +} + +uint64_t PRPList::getPRPSize(uint64_t addr) { + return pagesize - (addr & (pagesize - 1)); +} + +void PRPList::read(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doRead = [this, offset, length, buffer](uint64_t, void *context) { + uint64_t totalRead = 0; + uint64_t currentOffset = 0; + uint64_t read; + bool begin = false; + + DMAContext *readContext = (DMAContext *)context; + + for (auto &iter : prpList) { + if (begin) { + read = MIN(iter.size, length - totalRead); + readContext->counter++; + pInterface->dmaRead(iter.addr, read, buffer ? buffer + totalRead : NULL, + dmaHandler, readContext); + totalRead += read; + + if (totalRead == length) { + break; + } + } + + if (!begin && currentOffset + iter.size > offset) { + begin = true; + totalRead = offset - currentOffset; + read = MIN(iter.size - totalRead, length); + readContext->counter++; + pInterface->dmaRead(iter.addr + totalRead, read, buffer, dmaHandler, + readContext); + totalRead = read; + } + + currentOffset += iter.size; + } + + if (readContext->counter == 0) { + readContext->counter = 1; + + dmaHandler(getTick(), readContext); + } + }; + + DMAContext *readContext = new DMAContext(func, context); + + execute(CPU::NVME__PRPLIST, CPU::READ, doRead, readContext); +} + +void PRPList::write(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doWrite = [this, offset, length, buffer](uint64_t, + void *context) { + uint64_t totalWritten = 0; + uint64_t currentOffset = 0; + uint64_t written; + bool begin = false; + + DMAContext *writeContext = (DMAContext *)context; + + for (auto &iter : prpList) { + if (begin) { + written = MIN(iter.size, length - totalWritten); + writeContext->counter++; + pInterface->dmaWrite(iter.addr, written, + buffer ? buffer + totalWritten : NULL, dmaHandler, + writeContext); + totalWritten += written; + + if (totalWritten == length) { + break; + } + } + + if (!begin && currentOffset + iter.size > offset) { + begin = true; + totalWritten = offset - currentOffset; + written = MIN(iter.size - totalWritten, length); + writeContext->counter++; + pInterface->dmaWrite(iter.addr + totalWritten, written, buffer, + dmaHandler, writeContext); + totalWritten = written; + } + + currentOffset += iter.size; + } + + if (writeContext->counter == 0) { + writeContext->counter = 1; + + dmaHandler(getTick(), writeContext); + } + }; + + DMAContext *writeContext = new DMAContext(func, context); + + execute(CPU::NVME__PRPLIST, CPU::WRITE, doWrite, writeContext); +} + +SGLDescriptor::SGLDescriptor() { + memset(data, 0, 16); +} + +Chunk::Chunk() : addr(0), length(0), ignore(true) {} + +Chunk::Chunk(uint64_t a, uint32_t l, bool i) : addr(a), length(l), ignore(i) {} + +SGL::SGL(ConfigData &cfg, DMAFunction &f, void *c, uint64_t prp1, uint64_t prp2) + : DMAInterface(cfg, f, c), totalSize(0) { + SGLDescriptor desc; + + // Create first SGL descriptor from PRP pointers + memcpy(desc.data, &prp1, 8); + memcpy(desc.data + 8, &prp2, 8); + + // Check type + if (SGL_TYPE(desc.id) == TYPE_DATA_BLOCK_DESCRIPTOR || + SGL_TYPE(desc.id) == TYPE_KEYED_DATA_BLOCK_DESCRIPTOR) { + // This is entire buffer + parseSGLDescriptor(desc); + + schedule(immediateEvent, getTick()); + } + else if (SGL_TYPE(desc.id) == TYPE_SEGMENT_DESCRIPTOR || + SGL_TYPE(desc.id) == TYPE_LAST_SEGMENT_DESCRIPTOR) { + // This points segment + parseSGLSegment(desc.address, desc.length); + } +} + +SGL::~SGL() {} + +void SGL::parseSGLDescriptor(SGLDescriptor &desc) { + switch (SGL_TYPE(desc.id)) { + case TYPE_DATA_BLOCK_DESCRIPTOR: + case TYPE_KEYED_DATA_BLOCK_DESCRIPTOR: + chunkList.push_back(Chunk(desc.address, desc.length, false)); + totalSize += desc.length; + + break; + case TYPE_BIT_BUCKET_DESCRIPTOR: + chunkList.push_back(Chunk(desc.address, desc.length, true)); + totalSize += desc.length; + + break; + default: + panic("Invalid SGL descriptor"); + break; + } + + if (SGL_SUBTYPE(desc.id) != SUBTYPE_ADDRESS) { + panic("Unexpected SGL subtype"); + } +} + +void SGL::parseSGLSegment(uint64_t address, uint32_t length) { + static DMAFunction doRead = [](uint64_t now, void *context) { + SGLDescriptor desc; + DMAInitContext *pContext = (DMAInitContext *)context; + SGL *pThis = (SGL *)pContext->pThis; + bool next = false; + + pThis->callCounter--; + + for (uint32_t i = 0; i < pContext->currentSize; i += 16) { + memcpy(desc.data, pContext->buffer + i, 16); + + switch (SGL_TYPE(desc.id)) { + case TYPE_DATA_BLOCK_DESCRIPTOR: + case TYPE_KEYED_DATA_BLOCK_DESCRIPTOR: + case TYPE_BIT_BUCKET_DESCRIPTOR: + pThis->parseSGLDescriptor(desc); + + break; + case TYPE_SEGMENT_DESCRIPTOR: + case TYPE_LAST_SEGMENT_DESCRIPTOR: + if (i != pContext->currentSize - 16) { + panic("Invalid SGL segment"); + } + next = true; + + break; + } + } + + free(pContext->buffer); + + // Go to next + if (next) { + pThis->parseSGLSegment(desc.address, desc.length); + } + + if (pThis->callCounter == 0) { + pThis->initFunction(now, pThis->context); + } + + delete pContext; + }; + + DMAInitContext *pContext = new DMAInitContext(); + + callCounter++; + + // Allocate buffer + pContext->pThis = this; + pContext->currentSize = length; + pContext->buffer = (uint8_t *)calloc(length, 1); + + if (pContext->buffer) { + // Read segment + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::NVME__SGL, + CPU::PARSE_SGL_SEGMENT); + pInterface->dmaRead(address, length, pContext->buffer, cpuHandler, pCPU); + } + else { + delete pContext; + + panic("sgl: ENOMEM"); + } +} + +void SGL::read(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doRead = [this, offset, length, buffer](uint64_t, void *context) { + uint64_t totalRead = 0; + uint64_t currentOffset = 0; + uint64_t read; + bool begin = false; + + DMAContext *readContext = (DMAContext *)context; + + for (auto &iter : chunkList) { + if (begin) { + read = MIN(iter.length, length - totalRead); + + if (!iter.ignore) { + readContext->counter++; + pInterface->dmaRead(iter.addr, read, + buffer ? buffer + totalRead : NULL, dmaHandler, + readContext); + } + + totalRead += read; + + if (totalRead == length) { + break; + } + } + + if (!begin && currentOffset + iter.length > offset) { + begin = true; + totalRead = offset - currentOffset; + read = MIN(iter.length - totalRead, length); + + if (!iter.ignore) { + readContext->counter++; + pInterface->dmaRead(iter.addr + totalRead, read, buffer, dmaHandler, + readContext); + } + + totalRead = read; + } + + currentOffset += iter.length; + } + + if (readContext->counter == 0) { + readContext->counter = 1; + + dmaHandler(getTick(), readContext); + } + }; + + DMAContext *readContext = new DMAContext(func, context); + + execute(CPU::NVME__SGL, CPU::READ, doRead, readContext); +} + +void SGL::write(uint64_t offset, uint64_t length, uint8_t *buffer, + DMAFunction &func, void *context) { + DMAFunction doWrite = [this, offset, length, buffer](uint64_t, + void *context) { + uint64_t totalWritten = 0; + uint64_t currentOffset = 0; + uint64_t written; + bool begin = false; + + DMAContext *writeContext = (DMAContext *)context; + + for (auto &iter : chunkList) { + if (begin) { + written = MIN(iter.length, length - totalWritten); + + if (!iter.ignore) { + writeContext->counter++; + pInterface->dmaWrite(iter.addr, written, + buffer ? buffer + totalWritten : NULL, + dmaHandler, writeContext); + } + + totalWritten += written; + + if (totalWritten == length) { + break; + } + } + + if (!begin && currentOffset + iter.length > offset) { + begin = true; + totalWritten = offset - currentOffset; + written = MIN(iter.length - totalWritten, length); + + if (!iter.ignore) { + writeContext->counter++; + pInterface->dmaWrite(iter.addr + totalWritten, written, buffer, + dmaHandler, writeContext); + } + + totalWritten = written; + } + + currentOffset += iter.length; + } + + if (writeContext->counter == 0) { + writeContext->counter = 1; + + dmaHandler(getTick(), writeContext); + } + }; + + DMAContext *writeContext = new DMAContext(func, context); + + execute(CPU::NVME__SGL, CPU::WRITE, doWrite, writeContext); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/dma.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/dma.hh new file mode 100644 index 0000000000..90b8a41e2f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/dma.hh @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_DMA__ +#define __HIL_NVME_DMA__ + +#include + +#include "hil/nvme/config.hh" +#include "hil/nvme/def.hh" +#include "sim/dma_interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Controller; + +typedef struct { + ConfigReader *pConfigReader; + DMAInterface *pInterface; + uint64_t memoryPageSize; + uint8_t memoryPageSizeOrder; + uint16_t maxQueueEntry; +} ConfigData; + +class DMAInterface { + protected: + SimpleSSD::DMAInterface *pInterface; + DMAFunction initFunction; + uint64_t callCounter; + void *context; + + Event immediateEvent; + + DMAFunction dmaHandler; + static void commonDMAHandler(uint64_t, void *); + + public: + DMAInterface(ConfigData &, DMAFunction &, void *); + virtual ~DMAInterface(); + + virtual void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; + virtual void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; +}; + +struct DMAInitContext { + DMAInterface *pThis; + uint64_t totalSize; + uint64_t currentSize; + uint8_t *buffer; +}; + +struct PRP { + uint64_t addr; + uint64_t size; + + PRP(); + PRP(uint64_t, uint64_t); +}; + +class PRPList : public DMAInterface { + private: + std::vector prpList; + uint64_t totalSize; + uint64_t pagesize; + + void getPRPListFromPRP(uint64_t, uint64_t); + uint64_t getPRPSize(uint64_t); + + public: + PRPList(ConfigData &, DMAFunction &, void *, uint64_t, uint64_t, uint64_t); + PRPList(ConfigData &, DMAFunction &, void *, uint64_t, uint64_t, bool); + ~PRPList(); + + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; +}; + +union SGLDescriptor { + uint8_t data[16]; + struct { + uint64_t address; + uint32_t length; + uint8_t reserved[3]; + uint8_t id; + }; + + SGLDescriptor(); +}; + +struct Chunk { + uint64_t addr; + uint32_t length; + + bool ignore; + + Chunk(); + Chunk(uint64_t, uint32_t, bool); +}; + +class SGL : public DMAInterface { + private: + std::vector chunkList; + uint64_t totalSize; + + void parseSGLDescriptor(SGLDescriptor &); + void parseSGLSegment(uint64_t, uint32_t); + + public: + SGL(ConfigData &, DMAFunction &, void *, uint64_t, uint64_t); + ~SGL(); + + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/interface.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/interface.hh new file mode 100644 index 0000000000..5e1dd83ad3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/interface.hh @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_INTERFACE__ +#define __HIL_NVME_INTERFACE__ + +#include + +#include "sim/dma_interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Controller; + +class Interface : public SimpleSSD::DMAInterface { + protected: + Controller *pController; + + public: + virtual void updateInterrupt(uint16_t, bool) = 0; + virtual void getVendorID(uint16_t &, uint16_t &) = 0; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/namespace.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/namespace.cc new file mode 100644 index 0000000000..d80a72941d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/namespace.cc @@ -0,0 +1,689 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/namespace.hh" + +#include "hil/nvme/subsystem.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +Namespace::Namespace(Subsystem *p, ConfigData &c) + : pParent(p), + pDisk(nullptr), + cfgdata(c), + conf(*c.pConfigReader), + nsid(NSID_NONE), + attached(false), + allocated(false), + formatFinishedAt(0) {} + +Namespace::~Namespace() { + if (pDisk) { + delete pDisk; + } +} + +void Namespace::submitCommand(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + bool response = false; + + if (getTick() < formatFinishedAt) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_FORMAT_IN_PROGRESS); + + response = true; + } + else { + // Admin commands + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_GET_LOG_PAGE: + getLogPage(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + + response = true; + + break; + } + } + + // NVM commands + else { + switch (req.entry.dword0.opcode) { + case OPCODE_FLUSH: + flush(req, func); + break; + case OPCODE_WRITE: + write(req, func); + break; + case OPCODE_READ: + read(req, func); + break; + case OPCODE_COMPARE: + compare(req, func); + break; + case OPCODE_DATASET_MANAGEMEMT: + datasetManagement(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + + response = true; + + break; + } + } + } + + if (response) { + func(resp); + } +} + +void Namespace::setData(uint32_t id, Information *data) { + nsid = id; + memcpy(&info, data, sizeof(Information)); + + if (conf.readBoolean(CONFIG_NVME, NVME_ENABLE_DISK_IMAGE)) { + uint64_t diskSize; + + std::string filename = + conf.readString(CONFIG_NVME, NVME_DISK_IMAGE_PATH + nsid); + + if (filename.length() == 0) { + pDisk = new MemDisk(); + } + else if (conf.readBoolean(CONFIG_NVME, NVME_USE_COW_DISK)) { + pDisk = new CoWDisk(); + } + else { + pDisk = new Disk(); + } + + diskSize = pDisk->open(filename, info.size * info.lbaSize, info.lbaSize); + + if (diskSize == 0) { + panic("Failed to open disk image"); + } + else if (diskSize != info.size * info.lbaSize) { + if (conf.readBoolean(CONFIG_NVME, NVME_STRICT_DISK_SIZE)) { + panic("Disk size not match"); + } + } + + if (filename.length() > 0) { + SimpleSSD::info("Using disk image at %s for NSID %u", filename.c_str(), + nsid); + } + } + + allocated = true; +} + +void Namespace::attach(bool attach) { + attached = attach; +} + +uint32_t Namespace::getNSID() { + return nsid; +} + +Namespace::Information *Namespace::getInfo() { + return &info; +} + +bool Namespace::isAttached() { + return attached; +} + +void Namespace::format(uint64_t tick) { + formatFinishedAt = tick; + + health = HealthInfo(); + + if (pDisk) { + delete pDisk; + pDisk = nullptr; + } +} + +void Namespace::getLogPage(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t numdl = (req.entry.dword10 & 0xFFFF0000) >> 16; + uint16_t lid = req.entry.dword10 & 0xFFFF; + uint16_t numdu = req.entry.dword11 & 0xFFFF; + uint32_t lopl = req.entry.dword12; + uint32_t lopu = req.entry.dword13; + bool submit = true; + + uint32_t req_size = (((uint32_t)numdu << 16 | numdl) + 1) * 4; + uint64_t offset = ((uint64_t)lopu << 32) | lopl; + + debugprint(LOG_HIL_NVME, + "ADMIN | Get Log Page | Log %d | Size %d | NSID %d", lid, + req_size, nsid); + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + DMAFunction smartInfo = [offset](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(offset, 512, pContext->buffer, dmaDone, context); + }; + + switch (lid) { + case LOG_SMART_HEALTH_INFORMATION: + if (req.entry.namespaceID == nsid) { + submit = false; + RequestContext *pContext = new RequestContext(func, resp); + + pContext->buffer = health.data; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2, (uint64_t)req_size); + } + } + else { + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + + break; + default: + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_LOG_PAGE); + break; + } + + if (submit) { + func(resp); + } +} + +void Namespace::flush(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + + func(resp); + } + + if (!err) { + DMAFunction begin = [this](uint64_t, void *context) { + DMAFunction doFlush = [this](uint64_t now, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint( + LOG_HIL_NVME, + "NVM | FLUSH | CQ %u | SQ %u:%u | CID %u | NSID %-5d | %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + pParent->flush(this, doFlush, context); + }; + + debugprint(LOG_HIL_NVME, "NVM | FLUSH | SQ %u:%u | CID %u | NSID %-5d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid); + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + + execute(CPU::NVME__NAMESPACE, CPU::FLUSH, begin, pContext); + } +} + +void Namespace::write(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to write 0 blocks"); + } + + debugprint(LOG_HIL_NVME, + "NVM | WRITE | SQ %u:%u | CID %u | NSID %-5d | %" PRIX64 + " + %d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->beginAt++; + + if (pContext->beginAt == 2) { + debugprint( + LOG_HIL_NVME, + "NVM | WRITE | CQ %u | SQ %u:%u | CID %u | NSID %-5d | " + "%" PRIX64 " + %d | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + pContext->function(pContext->resp); + + if (pContext->buffer) { + pDisk->write(pContext->slba, pContext->nlb, pContext->buffer); + + free(pContext->buffer); + } + + delete pContext->dma; + delete pContext; + } + }; + + IOContext *pContext = (IOContext *)context; + + pContext->tick = tick; + pContext->beginAt = 0; + + if (pDisk) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + + pContext->dma->read(0, pContext->nlb * info.lbaSize, pContext->buffer, + dmaDone, context); + } + else { + pContext->dma->read(0, pContext->nlb * info.lbaSize, nullptr, dmaDone, + context); + } + + pParent->write(this, pContext->slba, pContext->nlb, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__NAMESPACE, CPU::WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nlb * info.lbaSize); + } + } + else { + func(resp); + } +} + +void Namespace::read(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + // bool fua = req.entry.dword12 & 0x40000000; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to read 0 blocks"); + } + + debugprint(LOG_HIL_NVME, + "NVM | READ | SQ %u:%u | CID %u | NSID %-5d | %" PRIX64 + " + %d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->beginAt++; + + if (pContext->beginAt == 2) { + debugprint( + LOG_HIL_NVME, + "NVM | READ | CQ %u | SQ %u:%u | CID %u | NSID %-5d | " + "%" PRIX64 " + %d | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + if (pContext->buffer) { + free(pContext->buffer); + } + + delete pContext->dma; + delete pContext; + } + }; + + IOContext *pContext = (IOContext *)context; + + pContext->tick = tick; + pContext->beginAt = 0; + + pParent->read(this, pContext->slba, pContext->nlb, dmaDone, pContext); + + pContext->buffer = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + + if (pDisk) { + pDisk->read(pContext->slba, pContext->nlb, pContext->buffer); + } + + pContext->dma->write(0, pContext->nlb * info.lbaSize, pContext->buffer, + dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__NAMESPACE, CPU::READ); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * info.lbaSize); + } + } + else { + func(resp); + } +} + +void Namespace::compare(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + // bool fua = req.entry.dword12 & 0x40000000; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to read 0 blocks"); + } + + debugprint(LOG_HIL_NVME, + "NVM | COMP | SQ %u:%u | CID %u | NSID %-5d | %" PRIX64 + " + %d", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + CompareContext *pContext = (CompareContext *)context; + + pContext->beginAt++; + + if (pContext->beginAt == 2) { + // Compare buffer! + // Always success if no disk + if (pDisk && memcmp(pContext->buffer, pContext->hostContent, + pContext->nlb * info.lbaSize) != 0) { + pContext->resp.makeStatus(false, false, + TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + STATUS_COMPARE_FAILURE); + } + + debugprint( + LOG_HIL_NVME, + "NVM | COMP | CQ %u | SQ %u:%u | CID %u | NSID %-5d | " + "%" PRIX64 " + %d | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, pContext->resp.entry.dword3.commandID, nsid, + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + if (pContext->buffer) { + free(pContext->buffer); + } + if (pContext->hostContent) { + free(pContext->hostContent); + } + + delete pContext->dma; + delete pContext; + } + }; + + CompareContext *pContext = (CompareContext *)context; + + pContext->tick = tick; + pContext->beginAt = 0; + + pParent->read(this, pContext->slba, pContext->nlb, dmaDone, pContext); + + pContext->buffer = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + pContext->hostContent = (uint8_t *)calloc(pContext->nlb, info.lbaSize); + + if (pDisk) { + pDisk->read(pContext->slba, pContext->nlb, pContext->buffer); + } + + pContext->dma->read(0, pContext->nlb * info.lbaSize, + pContext->hostContent, dmaDone, context); + }; + + CompareContext *pContext = new CompareContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__NAMESPACE, CPU::READ); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * info.lbaSize); + } + } + else { + func(resp); + } +} + +void Namespace::datasetManagement(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + int nr = (req.entry.dword10 & 0xFF) + 1; + bool ad = req.entry.dword11 & 0x04; + + if (!attached) { + err = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + if (!ad) { + err = true; + // Just ignore + } + + debugprint( + LOG_HIL_NVME, + "NVM | TRIM | SQ %u:%u | CID %u | NSID %-5d| %d ranges | Attr %1X", + req.sqID, req.sqUID, req.entry.dword0.commandID, nsid, nr, + req.entry.dword11 & 0x0F); + + if (!err) { + static DMAFunction eachTrimDone = [](uint64_t tick, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(tick, pContext->context); + } + + delete pContext; + }; + DMAFunction doTrim = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t, void *context) { + DMAFunction trimDone = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "NVM | TRIM | CQ %u | SQ %u:%u | CID %u | NSID %-5d| " + "%" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->resp.cqID, pContext->resp.entry.dword2.sqID, + pContext->resp.sqUID, + pContext->resp.entry.dword3.commandID, nsid, + pContext->beginAt, tick, tick - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + DatasetManagementRange range; + IOContext *pContext = (IOContext *)context; + DMAContext *pDMA = new DMAContext(trimDone); + + pDMA->context = context; + + for (uint64_t i = 0; i < pContext->slba; i++) { + memcpy(range.data, + pContext->buffer + i * sizeof(DatasetManagementRange), + sizeof(DatasetManagementRange)); + + pDMA->counter++; + pParent->trim(this, range.slba, range.nlb, eachTrimDone, pDMA); + } + + if (pDMA->counter == 0) { + pDMA->counter = 1; + + eachTrimDone(getTick(), pDMA); + } + + free(pContext->buffer); + delete pContext->dma; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = + (uint8_t *)calloc(pContext->slba, sizeof(DatasetManagementRange)); + + pContext->dma->read(0, pContext->slba * sizeof(DatasetManagementRange), + pContext->buffer, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = nr; + + CPUContext *pCPU = new CPUContext(doTrim, pContext, CPU::NVME__NAMESPACE, + CPU::DATASET_MANAGEMENT); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nr * 0x10); + } + } + else { + func(resp); + } +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/namespace.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/namespace.hh new file mode 100644 index 0000000000..8475bf6db1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/namespace.hh @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_NAMESPACE__ +#define __HIL_NVME_NAMESPACE__ + +#include + +#include "hil/nvme/def.hh" +#include "hil/nvme/dma.hh" +#include "hil/nvme/queue.hh" +#include "util/def.hh" +#include "util/disk.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Subsystem; + +typedef union _DatasetManagementRange { + uint8_t data[0x10]; + struct { + uint32_t attr; + uint32_t nlb; + uint64_t slba; + }; +} DatasetManagementRange; + +typedef std::function RequestFunction; + +class RequestContext { + public: + DMAInterface *dma; + RequestFunction function; + CQEntryWrapper resp; + + uint8_t *buffer; + + RequestContext(RequestFunction &f, CQEntryWrapper &r) + : dma(nullptr), function(f), resp(r), buffer(nullptr) {} +}; + +class IOContext : public RequestContext { + public: + uint64_t beginAt; + uint64_t slba; + uint64_t nlb; + uint64_t tick; + + IOContext(RequestFunction &f, CQEntryWrapper &r) : RequestContext(f, r) {} +}; + +class CompareContext : public IOContext { + public: + uint8_t *hostContent; + + CompareContext(RequestFunction &f, CQEntryWrapper &r) + : IOContext(f, r), hostContent(nullptr) {} +}; + +class Namespace { + public: + typedef struct _Information { + uint64_t size; //!< NSZE + uint64_t capacity; //!< NCAP + uint64_t utilization; //!< NUSE + uint64_t sizeInByteL; //. + */ + +#include "hil/nvme/ocssd.hh" + +#include "hil/nvme/controller.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +struct OCSSDContext { + Request req; + std::vector<::CPDPBP> list; + uint64_t beginAt; +}; + +BlockData::_BlockData() : index(0), value(0) {} + +BlockData::_BlockData(uint32_t i, uint8_t v) : index(i), value(v) {} + +ChunkUpdateEntry::_ChunkUpdateEntry(ChunkDescriptor *p, uint32_t i) + : pDesc(p), pageIdx(i) {} + +OpenChannelSSD12::OpenChannelSSD12(Controller *c, ConfigData &cfg) + : Subsystem(c, cfg), + lastScheduled(0), + eraseCount(0), + readCount(0), + writeCount(0) { + completionEvent = allocate([this](uint64_t) { completion(); }); +} + +OpenChannelSSD12::~OpenChannelSSD12() { + for (auto &iter : lNamespaces) { + delete iter; + } + + delete pPALOLD; + delete pDisk; +} + +void OpenChannelSSD12::init() { + bool useMP = conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + param.channel = conf.readUint(CONFIG_PAL, PAL::PAL_CHANNEL); + param.package = conf.readUint(CONFIG_PAL, PAL::PAL_PACKAGE); + + param.die = conf.readUint(CONFIG_PAL, PAL::NAND_DIE); + param.plane = conf.readUint(CONFIG_PAL, PAL::NAND_PLANE); + param.block = conf.readUint(CONFIG_PAL, PAL::NAND_BLOCK); + param.page = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE); + param.pageSize = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE_SIZE); + param.superPageSize = param.pageSize; + + // Super block includes plane + if (useMP) { + param.superPageSize *= param.plane; + } + + // Print super block information + debugprint(LOG_PAL, + "Channel | Way | Die | Plane | Block | Page "); + debugprint(LOG_PAL, "%7u | %7u | %7u | %7u | %7u | %7u", param.channel, + param.package, param.die, param.plane, param.block, param.page); + debugprint(LOG_PAL, "Multi-plane mode %s", useMP ? "enabled" : "disabled"); + debugprint(LOG_PAL, "Page size %u -> %u", param.pageSize, + param.superPageSize); + debugprint( + LOG_PAL, "Total block count %u -> %u", + param.channel * param.package * param.die * param.plane * param.block, + param.superBlock); + + pPALOLD = new PAL::PALOLD(param, conf); + + // Set geometry + structure.group = param.channel; + structure.parallelUnit = param.package; + structure.parallelUnit *= param.die; + structure.chunk = param.block; + structure.chunk *= useMP ? 1 : param.plane; + structure.chunkSize = param.page * param.superPageSize / LBA_SIZE; + structure.writeSize = param.superPageSize / LBA_SIZE; + + // Print structure + debugprint(LOG_HIL_NVME, "OpenChannel SSD v1.2"); + debugprint(LOG_HIL_NVME, "OpenChannel SSD Structure: (Blk size is %u)", + LBA_SIZE); + debugprint(LOG_HIL_NVME, " Group | PU (LUN) | Chunk | Chunk Size " + "| Write Size"); + debugprint(LOG_HIL_NVME, " %4u | %6u | %6u | %6u Blk | %6u Blk", + structure.group, structure.parallelUnit, structure.chunk, + structure.chunkSize, structure.writeSize); + debugprint(LOG_HIL_NVME, + " In total: | %6u | %6u | %u Blk / %" PRIu64 " Bytes", + structure.group * structure.parallelUnit, + structure.group * structure.parallelUnit * structure.chunk, + structure.group * structure.parallelUnit * structure.chunk * + structure.chunkSize, + (uint64_t)structure.group * structure.parallelUnit * + structure.chunk * structure.chunkSize * LBA_SIZE); + debugprint(LOG_HIL_NVME, "nvm notation (old): [%u/1/%u/%u/%u/%u]", + structure.writeSize, param.page, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + debugprint(LOG_HIL_NVME, "nvm notation (new): [%u/%u/%u/%u/%u]", + structure.writeSize, structure.writeSize, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + + // Calculate mask + uint32_t lastidx = 0; + uint64_t sum = 0; + + int sectorPerPage = param.superPageSize / LBA_SIZE; + + ppaMask.sectorMask = generateMask(sectorPerPage, lastidx); + ppaMask.pageShift = lastidx; + ppaMask.pageMask = generateMask(param.page, lastidx); + ppaMask.blockShift = lastidx; + ppaMask.blockMask = generateMask(structure.chunk, lastidx); + ppaMask.planeShift = lastidx; + ppaMask.planeMask = 0; // No plane + ppaMask.dieShift = lastidx; + ppaMask.dieMask = 0; // No die + ppaMask.wayShift = lastidx; + ppaMask.wayMask = generateMask(structure.parallelUnit, lastidx); + ppaMask.channelShift = lastidx; + ppaMask.channelMask = generateMask(structure.group, lastidx); + + sum ^= ppaMask.sectorMask; + sum ^= ppaMask.pageMask; + sum ^= ppaMask.blockMask; + sum ^= ppaMask.planeMask; + sum ^= ppaMask.dieMask; + sum ^= ppaMask.wayMask; + sum ^= ppaMask.channelMask; + + ppaMask.padding = ~sum; + + // Create default namespace + Namespace::Information info; + + info.lbaSize = LBA_SIZE; + info.lbaFormatIndex = 3; // See subsystem.cc + info.dataProtectionSettings = 0; + info.namespaceSharingCapabilities = 0; + info.sizeInByteL = structure.group * structure.parallelUnit * structure.chunk; + info.size = info.sizeInByteL * structure.chunkSize; + info.sizeInByteL *= LBA_SIZE * structure.chunkSize; + info.sizeInByteH = 0; + info.capacity = info.size; + info.utilization = info.size; + + Namespace *pNS = new Namespace(this, cfgdata); + + pNS->setData(1, &info); + pNS->attach(true); + + lNamespaces.push_back(pNS); + + // Open Disk image + pDisk = new MemDisk(); + + pDisk->open("", info.sizeInByteL, LBA_SIZE); +} + +void OpenChannelSSD12::submitCommand(SQEntryWrapper &req, + RequestFunction func) { + struct CommandContext { + SQEntryWrapper req; + RequestFunction func; + + CommandContext(SQEntryWrapper &r, RequestFunction &f) : req(r), func(f) {} + }; + + CQEntryWrapper resp(req); + bool processed = false; + + commandCount++; + + // Admin command + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_DELETE_IO_SQUEUE: + processed = deleteSQueue(req, func); + break; + case OPCODE_CREATE_IO_SQUEUE: + processed = createSQueue(req, func); + break; + case OPCODE_GET_LOG_PAGE: + processed = getLogPage(req, func); + break; + case OPCODE_DELETE_IO_CQUEUE: + processed = deleteCQueue(req, func); + break; + case OPCODE_CREATE_IO_CQUEUE: + processed = createCQueue(req, func); + break; + case OPCODE_IDENTIFY: + processed = identify(req, func); + break; + case OPCODE_ABORT: + processed = abort(req, func); + break; + case OPCODE_SET_FEATURES: + processed = setFeatures(req, func); + break; + case OPCODE_GET_FEATURES: + processed = getFeatures(req, func); + break; + case OPCODE_ASYNC_EVENT_REQ: + break; + case OPCODE_DEVICE_IDENTIFICATION: + processed = deviceIdentification(req, func); + break; + case OPCODE_GET_BAD_BLOCK_TABLE: + processed = getBadBlockTable(req, func); + break; + case OPCODE_SET_BAD_BLOCK_TABLE: + processed = setBadBlockTable(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + break; + } + } + + // NVM commands or Namespace specific Admin commands + if (!processed) { + if (req.entry.namespaceID == NSID_ALL || req.entry.namespaceID == 1) { + processed = true; + + switch (req.entry.dword0.opcode) { + case OPCODE_READ: + // This for automatic partition table detection + // Just return SUCCESS, which means null data + debugprint(LOG_HIL_NVME, "OCSSD | READ | Ignored"); + + func(resp); + break; + case OPCODE_PHYSICAL_BLOCK_ERASE: + physicalBlockErase(req, func); + break; + case OPCODE_PHYSICAL_PAGE_READ: + physicalPageRead(req, func); + break; + case OPCODE_PHYSICAL_PAGE_WRITE: + physicalPageWrite(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + processed = false; + break; + } + } + } + + // Invalid namespace + if (!processed) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + + func(resp); + } +} + +void OpenChannelSSD12::getNVMCapacity(uint64_t &total, uint64_t &used) { + total = structure.group * structure.parallelUnit * structure.chunk * + structure.chunkSize; + used = total; +} + +uint32_t OpenChannelSSD12::validNamespaceCount() { + return 1; +} + +bool OpenChannelSSD12::parsePPA(uint64_t ppa, ::CPDPBP &addr) { + if ((ppa & ppaMask.padding) == 0) { + addr.Channel = (ppa & ppaMask.channelMask) >> ppaMask.channelShift; + addr.Package = (ppa & ppaMask.wayMask) >> ppaMask.wayShift; + addr.Die = (ppa & ppaMask.dieMask) >> ppaMask.dieShift; + addr.Plane = (ppa & ppaMask.planeMask) >> ppaMask.planeShift; + addr.Block = (ppa & ppaMask.blockMask) >> ppaMask.blockShift; + addr.Page = (ppa & ppaMask.pageMask) >> ppaMask.pageShift; + + return true; + } + + return false; +} + +void OpenChannelSSD12::convertUnit(::CPDPBP &addr) { + static bool useMP = + conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + addr.Die = addr.Package % param.die; + addr.Package = addr.Package / param.die; + if (useMP) { + addr.Plane = 0; + } + else { + addr.Plane = addr.Block % param.plane; + addr.Block = addr.Block / param.plane; + } +} + +void OpenChannelSSD12::mergeList(std::vector &lbaList, + std::vector<::CPDPBP> &list, bool block) { + ::CPDPBP temp; + + list.clear(); + + for (auto &lba : lbaList) { + if (parsePPA(lba, temp)) { + convertUnit(temp); + + if (list.size() > 0) { + auto &back = list.back(); + + if (back.Channel == temp.Channel && back.Package == temp.Package && + back.Die == temp.Die && back.Plane == temp.Plane && + back.Block == temp.Block && (block || back.Page == temp.Page)) { + continue; + } + } + + list.push_back(temp); + } + } +} + +void OpenChannelSSD12::updateCompletion() { + if (completionQueue.size() > 0) { + if (lastScheduled != completionQueue.top().finishedAt) { + lastScheduled = completionQueue.top().finishedAt; + + if (lastScheduled < getTick()) { + warn("Invalid tick %" PRIu64, lastScheduled); + lastScheduled = getTick(); + } + + schedule(completionEvent, lastScheduled); + } + } +} + +void OpenChannelSSD12::completion() { + uint64_t tick = getTick(); + + while (completionQueue.size() > 0) { + auto &req = completionQueue.top(); + + if (req.finishedAt <= tick) { + req.function(tick, req.context); + + completionQueue.pop(); + } + else { + break; + } + } + + updateCompletion(); +} + +bool OpenChannelSSD12::deviceIdentification(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + PAL::NAND_TYPE type = + (PAL::NAND_TYPE)conf.readInt(CONFIG_PAL, PAL::NAND_FLASH_TYPE); + + RequestContext *pContext = new RequestContext(func, resp); + + uint8_t *data = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + debugprint(LOG_HIL_NVME, "OCSSD | Device Identification"); + + // Version + data[0x00] = 0x01; // OpenChannel SSD v1.x + + // Vendor NVM opcode command set + data[0x01] = 0x00; + + // Configuration groups + data[0x02] = 0x01; + data[0x03] = 0x00; // Reserved + + // Device capabilities and feature support + // [Bits ] Description + // [31:02] Reserved + // [01:01] 1 for support hybrid command + // [00:00] 1 for support bad block table management + data[0x04] = 0x01; + data[0x05] = 0x00; + data[0x06] = 0x00; + data[0x07] = 0x00; + + // Device operating mode + // [Bits ] Description + // [31:02] Reserved + // [01:01] 1 for ECC is provided by host + // [00:00] 1 for operating in hybrid mode + data[0x08] = 0x00; + data[0x09] = 0x00; + data[0x0A] = 0x00; + data[0x0B] = 0x00; + + // PPA Format + { + data[0x0C] = ppaMask.channelShift; + data[0x0D] = popcount(ppaMask.channelMask); + data[0x0E] = __builtin_ffsl(ppaMask.wayMask | ppaMask.dieMask) - 1; + data[0x0F] = popcount(ppaMask.wayMask | ppaMask.dieMask); + data[0x10] = ppaMask.planeShift; + data[0x11] = popcount(ppaMask.planeMask); + data[0x12] = ppaMask.blockShift; + data[0x13] = popcount(ppaMask.blockMask); + data[0x14] = ppaMask.pageShift; + data[0x15] = popcount(ppaMask.pageMask); + data[0x16] = 0; + data[0x17] = popcount(ppaMask.sectorMask); + } + + // Description of 1st group + { + // Media type + data[0x100] = 0x00; // NAND Flash + + // Flash type + switch (type) { + case PAL::NAND_SLC: + data[0x101] = 0; + break; + case PAL::NAND_MLC: + data[0x101] = 1; + break; + default: + panic("Unsupported NAND type in OpenChannel SSD v1.2"); + break; + } + + // Number of channels + data[0x104] = structure.group; + + // Number of LUNs + data[0x105] = structure.parallelUnit; + + // Number of planes + data[0x106] = 1; + + // Number of blocks + *(uint16_t *)(data + 0x108) = structure.chunk; + + // Number of pages + *(uint16_t *)(data + 0x10A) = param.page; + + // Size of page + *(uint16_t *)(data + 0x10C) = param.superPageSize; + + // Size of sector + *(uint16_t *)(data + 0x10E) = LBA_SIZE; + + // Sector meta size + *(uint16_t *)(data + 0x110) = 0; + + // Performance Related Metrics + PAL::Config::NANDTiming *pNANDTiming = conf.getNANDTiming(); + + // Typical page read time + *(uint32_t *)(data + 0x114) = pNANDTiming->msb.read / 1000; + + // Typical page write time + *(uint32_t *)(data + 0x11C) = pNANDTiming->msb.write / 1000; + + if (conf.readInt(CONFIG_PAL, PAL::NAND_FLASH_TYPE) != PAL::NAND_SLC) { + // Max page read time + *(uint32_t *)(data + 0x118) = pNANDTiming->lsb.read / 1000; + + // Max page write time + *(uint32_t *)(data + 0x120) = pNANDTiming->lsb.write / 1000; + } + else { + // Max page read time + *(uint32_t *)(data + 0x118) = pNANDTiming->msb.read / 1000; + + // Max page write time + *(uint32_t *)(data + 0x120) = pNANDTiming->msb.write / 1000; + } + + // Typical block erase time + *(uint32_t *)(data + 0x124) = pNANDTiming->erase / 1000; + + // Max block erase time + *(uint32_t *)(data + 0x128) = pNANDTiming->erase / 1000; + + // Multi-plane operations + // [Bits ] Description + // [31:19] Reserved + // [18:18] 1 for Quad plane erase + // [17:17] 1 for Dual plane erase + // [16:16] 1 for Single plane erase + // [15:11] Reserved + // [10:10] 1 for Quad plane write + // [09:09] 1 for Dual plane write + // [08:08] 1 for Single plane write + // [07:03] Reserved + // [02:02] 1 for Quad plane read + // [01:01] 1 for Dual plane read + // [00:00] 1 for Single plane read + data[0x12C] = 0x00; + data[0x12D] = 0x00; + data[0x12E] = 0x00; + data[0x12F] = 0x00; + + // Media and Controller Capabilities + // [Bits ] Description + // [31:04] Reserved + // [03:03] 1 for support Encryption + // [02:02] 1 for support Scramble On/Off + // [01:01] 1 for support Command suspension + // [00:00] 1 for support SLC mode + data[0x130] = 0x01; + data[0x131] = 0x00; + data[0x132] = 0x00; + data[0x133] = 0x00; + + // Channel parallelism + *(uint16_t *)(data + 0x134) = 1; + + // Media type specific data + memset(data + 0x140, 0, 896); + + if (type == PAL::NAND_MLC) { + *(uint16_t *)(data + 0x148) = 1; + data[0x14A] = 0x11; + } + } + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + static DMAFunction doWrite = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + pContext->buffer = data; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + + return true; +} + +bool OpenChannelSSD12::setBadBlockTable(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + IOContext *pContext = new IOContext(func, resp); + + uint16_t nppa = (req.entry.dword12 & 0xFFFF) + 1; + uint8_t val = (req.entry.dword12 & 0xFF0000) >> 16; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + debugprint(LOG_HIL_NVME, "OCSSD | Set Badblock Table"); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + std::vector ppaList; + CPDPBP addr; + uint8_t val = pContext->tick; + + if (pContext->nlb == 1) { + ppaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + ppaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + for (auto &iter : ppaList) { + if (parsePPA(iter, addr)) { + auto data = badBlocks.find(iter); + + if (data == badBlocks.end()) { + // Push new value + if (val != 0) { + badBlocks.insert({iter, BlockData(addr.Block, val)}); + } + } + else { + if (val == 0) { + badBlocks.erase(data); + } + else { + data->second.index = addr.Block; + data->second.value = val; + } + } + + convertUnit(addr); + + debugprint( + LOG_HIL_NVME, + "OCSSD | C %5u | W %5u | D %5u | P %5u | B %5u | P %5u", + addr.Channel, addr.Package, addr.Die, addr.Plane, addr.Block, + addr.Page); + } + } + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + pContext->dma->read(0, pContext->nlb * 8, pContext->buffer, dmaDone, + context); + }; + + pContext->tick = val; + pContext->dma = new PRPList(cfgdata, doRead, pContext, pContext->slba, + (uint64_t)nppa * 8, true); + } + + if (err) { + func(resp); + } + + return true; +} + +bool OpenChannelSSD12::getBadBlockTable(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + CPDPBP addr; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint64_t prpsize = 64 + structure.chunk; + + RequestContext *pContext = new RequestContext(func, resp); + + debugprint(LOG_HIL_NVME, "OCSSD | Get Badblock Table"); + + uint64_t mask = ppaMask.channelMask | ppaMask.wayMask | ppaMask.dieMask; + uint8_t *data = (uint8_t *)calloc(prpsize, 1); + + if (parsePPA(ppa, addr) && data) { + convertUnit(addr); + + debugprint(LOG_HIL_NVME, + "OCSSD | C %5u | W %5u | D %5u | P %5u | B %5u | P %5u", + addr.Channel, addr.Package, addr.Die, addr.Plane, addr.Block, + addr.Page); + + // Table ID + memcpy(data, "BBLT", 4); + // Version number + *(uint16_t *)(data + 0x04) = 1; + // Total number of blocks in this LUN + *(uint32_t *)(data + 0x0C) = prpsize - 64; + // Number of factory bad blocks + *(uint32_t *)(data + 0x10) = 0; + // Number of grown bad blocks + *(uint32_t *)(data + 0x14) = 0; + // Number of device reserved blocks + *(uint32_t *)(data + 0x18) = 0; + // Number of host reserved blocks + *(uint32_t *)(data + 0x1C) = 0; + memset(data + 0x20, 0, 32); // Reserved + // Block table + memset(data + 0x40, 0, prpsize - 64); + + for (auto iter = badBlocks.begin(); iter != badBlocks.end(); iter++) { + if ((iter->first & mask) == (ppa & mask)) { + data[0x40 + iter->second.index] = iter->second.value; + } + } + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + DMAFunction doWrite = [prpsize](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, prpsize, pContext->buffer, dmaDone, context); + }; + + pContext->buffer = data; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, prpsize); + } + } + else { + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + + func(resp); + } + + return true; +} + +void OpenChannelSSD12::physicalBlockErase(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + IOContext *pContext = new IOContext(func, resp); + + uint8_t nppa = (req.entry.dword12 & 0x3F) + 1; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + eraseCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Physical Block Erase | %d lbas", nppa); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doErase = [this](uint64_t now, void *context) { + DMAFunction dmaDone = [this](uint64_t now, void *context) { + DMAFunction nandDone = [](uint64_t now, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Physical Block Erase | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + std::vector ppaList; + std::vector<::CPDPBP> list; + uint64_t beginAt; + uint64_t finishedAt = now; + + if (pContext->nlb == 1) { + ppaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + ppaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + for (uint64_t i = 0; i < pContext->nlb; i++) { + pDisk->erase(ppaList.at(i), 1); + } + + mergeList(ppaList, list, true); + + for (auto &iter : list) { + beginAt = now; + pPALOLD->erase(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + Request req = Request(nandDone, context); + req.finishedAt = finishedAt; + + completionQueue.push(req); + updateCompletion(); + + delete pContext->dma; + }; + + IOContext *pContext = (IOContext *)context; + + if (pContext->nlb > 1) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + pContext->dma->read(0, pContext->nlb * 8, pContext->buffer, dmaDone, + context); + } + else { + dmaDone(now, context); + } + }; + + CPUContext *pCPU = new CPUContext(doErase, pContext, CPU::NVME__OCSSD, + CPU::PHYSICAL_BLOCK_ERASE); + + pContext->beginAt = getTick(); + + if (pContext->nlb > 1) { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, pContext->slba, + (uint64_t)nppa * 8, true); + } + else { + pContext->dma = nullptr; + + cpuHandler(getTick(), pCPU); + } + } + + if (err) { + func(resp); + } +} + +void OpenChannelSSD12::physicalPageWrite(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + VectorContext *pContext = new VectorContext(func, resp); + + uint8_t nppa = (req.entry.dword12 & 0x3F) + 1; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + writeCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Physical Page Write | %d lbas", nppa); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doDMA = [this](uint64_t now, void *context) { + DMAFunction doWrite = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t now, void *context) { + DMAFunction nandDone = [](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Physical Page Write | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->resp.entry.dword0 = 0xFFFFFFFF; + pContext->resp.entry.reserved = 0xFFFFFFFF; + + pContext->function(pContext->resp); + + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + uint64_t beginAt; + uint64_t finishedAt = now; + std::vector<::CPDPBP> list; + + for (uint64_t i = 0; i < pContext->nlb; i++) { + pDisk->write(pContext->lbaList.at(i), 1, + pContext->buffer + i * LBA_SIZE); + } + + mergeList(pContext->lbaList, list); + + for (auto &iter : list) { + beginAt = now; + + pPALOLD->write(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + Request req = Request(nandDone, context); + req.finishedAt = finishedAt; + + completionQueue.push(req); + updateCompletion(); + + free(pContext->buffer); + delete pContext->dma; + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb == 1) { + pContext->lbaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back( + *(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + pContext->buffer = (uint8_t *)calloc(pContext->nlb * LBA_SIZE, 1); + pContext->dma->read(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, pContext->nlb * 8, + pContext->buffer, doWrite, context); + } + else { + doWrite(now, context); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::PHYSICAL_PAGE_WRITE); + + pContext->beginAt = getTick(); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nppa * LBA_SIZE); + } + } + + if (err) { + func(resp); + } +} + +void OpenChannelSSD12::physicalPageRead(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + VectorContext *pContext = new VectorContext(func, resp); + + uint8_t nppa = (req.entry.dword12 & 0x3F) + 1; + uint64_t ppa = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + + readCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Physical Page Read | %d lbas", nppa); + + if (nppa < 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + pContext->slba = ppa; + pContext->nlb = nppa; + + DMAFunction doDMA = [this](uint64_t now, void *context) { + DMAFunction doRead = [this](uint64_t now, void *context) { + DMAFunction nandDone = [](uint64_t, void *context) { + DMAFunction dmaDone = [](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Physical Block Read | %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->resp.entry.dword0 = 0xFFFFFFFF; + pContext->resp.entry.reserved = 0xFFFFFFFF; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + pContext->dma->write(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + + std::vector<::CPDPBP> list; + uint64_t beginAt; + uint64_t finishedAt = now; + + if (pContext->nlb == 1) { + pContext->lbaList.push_back(pContext->slba); + } + else { + for (uint8_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back( + *(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + + pContext->buffer = (uint8_t *)calloc(pContext->nlb * LBA_SIZE, 1); + + for (uint64_t i = 0; i < pContext->nlb; i++) { + pDisk->read(pContext->lbaList.at(i), 1, + pContext->buffer + i * LBA_SIZE); + } + + mergeList(pContext->lbaList, list); + + for (auto &iter : list) { + beginAt = now; + + pPALOLD->read(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + Request req = Request(nandDone, context); + req.finishedAt = finishedAt; + + completionQueue.push(req); + updateCompletion(); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + pContext->buffer = (uint8_t *)calloc(pContext->nlb * 8, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, pContext->nlb * 8, + pContext->buffer, doRead, context); + } + else { + doRead(now, context); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::PHYSICAL_PAGE_READ); + + pContext->beginAt = getTick(); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nppa * LBA_SIZE); + } + } + + if (err) { + func(resp); + } +} + +void OpenChannelSSD12::getStatList(std::vector &list, + std::string prefix) { + Stats temp; + + temp.name = prefix + "command_count"; + temp.desc = "Total number of OCSSD command handled"; + list.push_back(temp); + + temp.name = prefix + "erase"; + temp.desc = "Total number of Physical Block Erase command"; + list.push_back(temp); + + temp.name = prefix + "read"; + temp.desc = "Total number of Physical Page Read command"; + list.push_back(temp); + + temp.name = prefix + "write"; + temp.desc = "Total number of Physical Page Write command"; + list.push_back(temp); + + pPALOLD->getStatList(list, prefix + "pal."); +} + +void OpenChannelSSD12::getStatValues(std::vector &values) { + values.push_back(commandCount); + values.push_back(eraseCount); + values.push_back(readCount); + values.push_back(writeCount); + + pPALOLD->getStatValues(values); +} + +void OpenChannelSSD12::resetStatValues() { + commandCount = 0; + eraseCount = 0; + readCount = 0; + writeCount = 0; + + pPALOLD->resetStatValues(); +} + +OpenChannelSSD20::OpenChannelSSD20(Controller *c, ConfigData &cfg) + : OpenChannelSSD12(c, cfg), + pDescriptor(nullptr), + vectorEraseCount(0), + vectorReadCount(0), + vectorWriteCount(0) {} + +OpenChannelSSD20::~OpenChannelSSD20() { + free(pDescriptor); +} + +void OpenChannelSSD20::init() { + bool useMP = conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + param.channel = conf.readUint(CONFIG_PAL, PAL::PAL_CHANNEL); + param.package = conf.readUint(CONFIG_PAL, PAL::PAL_PACKAGE); + + param.die = conf.readUint(CONFIG_PAL, PAL::NAND_DIE); + param.plane = conf.readUint(CONFIG_PAL, PAL::NAND_PLANE); + param.block = conf.readUint(CONFIG_PAL, PAL::NAND_BLOCK); + param.page = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE); + param.pageSize = conf.readUint(CONFIG_PAL, PAL::NAND_PAGE_SIZE); + param.superPageSize = param.pageSize; + + // Super block includes plane + if (useMP) { + param.superPageSize *= param.plane; + } + + // Print super block information + debugprint(LOG_PAL, + "Channel | Way | Die | Plane | Block | Page "); + debugprint(LOG_PAL, "%7u | %7u | %7u | %7u | %7u | %7u", param.channel, + param.package, param.die, param.plane, param.block, param.page); + debugprint(LOG_PAL, "Multi-plane mode %s", useMP ? "enabled" : "disabled"); + debugprint(LOG_PAL, "Page size %u -> %u", param.pageSize, + param.superPageSize); + debugprint( + LOG_PAL, "Total block count %u -> %u", + param.channel * param.package * param.die * param.plane * param.block, + param.superBlock); + + pPALOLD = new PAL::PALOLD(param, conf); + + // Set geometry + structure.group = param.channel; + structure.parallelUnit = param.package; + structure.parallelUnit *= param.die; + structure.chunk = param.block; + structure.chunk *= useMP ? 1 : param.plane; + structure.chunkSize = param.page * param.superPageSize / LBA_SIZE; + structure.writeSize = param.superPageSize / LBA_SIZE; + + // Print structure + debugprint(LOG_HIL_NVME, "OpenChannel SSD v2.0"); + debugprint(LOG_HIL_NVME, "OpenChannel SSD Structure: (Blk size is %u)", + LBA_SIZE); + debugprint(LOG_HIL_NVME, " Group | PU (LUN) | Chunk | Chunk Size " + "| Write Size"); + debugprint(LOG_HIL_NVME, " %4u | %6u | %6u | %6u Blk | %6u Blk", + structure.group, structure.parallelUnit, structure.chunk, + structure.chunkSize, structure.writeSize); + debugprint(LOG_HIL_NVME, + " In total: | %6u | %6u | %u Blk / %" PRIu64 " Bytes", + structure.group * structure.parallelUnit, + structure.group * structure.parallelUnit * structure.chunk, + structure.group * structure.parallelUnit * structure.chunk * + structure.chunkSize, + (uint64_t)structure.group * structure.parallelUnit * + structure.chunk * structure.chunkSize * LBA_SIZE); + debugprint(LOG_HIL_NVME, "nvm notation (old): [%u/1/%u/%u/%u/%u]", + structure.writeSize, param.page, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + debugprint(LOG_HIL_NVME, "nvm notation (new): [%u/%u/%u/%u/%u]", + structure.writeSize, structure.writeSize, structure.chunk, + structure.group * structure.parallelUnit, structure.group); + + // Calculate mask + uint32_t lastidx = 0; + + ppaMask.sectorMask = generateMask(structure.chunkSize, lastidx); + ppaMask.blockShift = lastidx; + ppaMask.blockMask = generateMask(structure.chunk, lastidx); + ppaMask.wayShift = lastidx; + ppaMask.wayMask = generateMask(structure.parallelUnit, lastidx); + ppaMask.channelShift = lastidx; + ppaMask.channelMask = generateMask(structure.group, lastidx); + + // Chunk Descriptor + descriptorLength = structure.group * structure.parallelUnit * structure.chunk; + pDescriptor = + (ChunkDescriptor *)calloc(descriptorLength, sizeof(ChunkDescriptor)); + + for (uint32_t g = 0; g < structure.group; g++) { + for (uint32_t p = 0; p < structure.parallelUnit; p++) { + for (uint32_t c = 0; c < structure.chunk; c++) { + auto desc = getChunkDescriptor(g, p, c); + + desc->chunkState = FREE; + desc->chunkType = 0x01; // Force sequential write + desc->slba = makeLBA(g, p, c, 0); + desc->nlb = structure.chunkSize; + } + } + } + + // Create default namespace + Namespace::Information info; + + info.lbaSize = LBA_SIZE; + info.lbaFormatIndex = 3; // See subsystem.cc + info.dataProtectionSettings = 0; + info.namespaceSharingCapabilities = 0; + info.sizeInByteL = structure.group * structure.parallelUnit * structure.chunk; + info.size = info.sizeInByteL * structure.chunkSize; + info.sizeInByteL *= LBA_SIZE * structure.chunkSize; + info.sizeInByteH = 0; + info.capacity = info.size; + info.utilization = info.size; + + Namespace *pNS = new Namespace(this, cfgdata); + + pNS->setData(1, &info); + pNS->attach(true); + + lNamespaces.push_back(pNS); + + // Open Disk image + pDisk = new MemDisk(); + + pDisk->open("", info.sizeInByteL, LBA_SIZE); +} + +void OpenChannelSSD20::submitCommand(SQEntryWrapper &req, + RequestFunction func) { + struct CommandContext { + SQEntryWrapper req; + RequestFunction func; + + CommandContext(SQEntryWrapper &r, RequestFunction &f) : req(r), func(f) {} + }; + + CQEntryWrapper resp(req); + bool processed = false; + + commandCount++; + + // Admin command + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_DELETE_IO_SQUEUE: + processed = deleteSQueue(req, func); + break; + case OPCODE_CREATE_IO_SQUEUE: + processed = createSQueue(req, func); + break; + case OPCODE_GET_LOG_PAGE: + processed = getLogPage(req, func); + break; + case OPCODE_DELETE_IO_CQUEUE: + processed = deleteCQueue(req, func); + break; + case OPCODE_CREATE_IO_CQUEUE: + processed = createCQueue(req, func); + break; + case OPCODE_IDENTIFY: + processed = identify(req, func); + break; + case OPCODE_ABORT: + processed = abort(req, func); + break; + case OPCODE_SET_FEATURES: + processed = setFeatures(req, func); + break; + case OPCODE_GET_FEATURES: + processed = getFeatures(req, func); + break; + case OPCODE_ASYNC_EVENT_REQ: + break; + case OPCODE_GEOMETRY: + processed = geometry(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + break; + } + } + + // NVM commands or Namespace specific Admin commands + if (!processed) { + if (req.entry.namespaceID == NSID_ALL || req.entry.namespaceID == 1) { + processed = true; + + switch (req.entry.dword0.opcode) { + case OPCODE_READ: + read(req, func); + break; + case OPCODE_WRITE: + write(req, func); + break; + case OPCODE_DATASET_MANAGEMEMT: + datasetManagement(req, func); + break; + case OPCODE_VECTOR_CHUNK_RESET: + vectorChunkReset(req, func); + break; + case OPCODE_VECTOR_CHUNK_READ: + vectorChunkRead(req, func); + break; + case OPCODE_VECTOR_CHUNK_WRITE: + vectorChunkWrite(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + processed = false; + break; + } + } + } + + // Invalid namespace + if (!processed) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + + func(resp); + } +} + +ChunkDescriptor *OpenChannelSSD20::getChunkDescriptor(uint32_t g, uint32_t p, + uint32_t c) { + return &pDescriptor[g * structure.parallelUnit * structure.chunk + + p * structure.chunk + c]; +} + +uint64_t OpenChannelSSD20::makeLBA(uint32_t g, uint32_t p, uint32_t c, + uint32_t l) { + uint64_t ret = 0; + + ret = l & ppaMask.sectorMask; + ret |= (c << ppaMask.blockShift) & ppaMask.blockMask; + ret |= (p << ppaMask.wayShift) & ppaMask.wayMask; + ret |= (g << ppaMask.channelShift) & ppaMask.channelMask; + + return ret; +} + +void OpenChannelSSD20::parseLBA(uint64_t lba, uint32_t &g, uint32_t &p, + uint32_t &c, uint32_t &l) { + l = lba & ppaMask.sectorMask; + c = (lba & ppaMask.blockMask) >> ppaMask.blockShift; + p = (lba & ppaMask.wayMask) >> ppaMask.wayShift; + g = (lba & ppaMask.channelMask) >> ppaMask.channelShift; +} + +void OpenChannelSSD20::convertUnit(std::vector &lbaList, + std::vector<::CPDPBP> &list, + std::vector &chunk, + bool block, bool mode) { + static bool useMP = + conf.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP); + + list.clear(); + chunk.clear(); + + // Optimize this + auto convert = [&](uint64_t lba) { + ::CPDPBP temp; + uint32_t g, p, c, l; + + parseLBA(lba, g, p, c, l); + + // Group -> [Channel] + // Parallel Unit -> [Package][Die] + // Chunk -> [Block][Plane] + temp.Channel = g; + temp.Package = p / param.die; + temp.Die = p % param.die; + + if (useMP) { + temp.Plane = 0; + temp.Block = c; + } + else { + temp.Plane = c % param.plane; + temp.Block = c / param.plane; + } + + temp.Page = l / structure.writeSize; + + if (list.size() > 0) { + auto &back = list.back(); + + if (back.Channel == temp.Channel && back.Package == temp.Package && + back.Die == temp.Die && back.Plane == temp.Plane && + back.Block == temp.Block && (block || back.Page == temp.Page)) { + return; + } + } + + chunk.push_back(ChunkUpdateEntry(getChunkDescriptor(g, p, c), temp.Page)); + list.push_back(temp); + }; + + if (mode) { + for (auto &lba : lbaList) { + convert(lba); + } + } + else { + for (uint64_t lba = lbaList.front(); lba < lbaList.back(); lba++) { + convert(lba); + } + } +} + +void OpenChannelSSD20::readInternal(std::vector &lbaList, + DMAFunction &func, void *context, + bool mode) { + OCSSDContext *pContext = new OCSSDContext(); + std::vector chunks; + bool err = false; + uint64_t idx = 1; + + pContext->req = Request(func, context); + pContext->beginAt = + getTick() + applyLatency(CPU::NVME__OCSSD, CPU::CONVERT_UNIT); + + convertUnit(lbaList, pContext->list, chunks, false, mode); + + // Update ChunkDescriptor + for (auto &iter : chunks) { + // Check block status + if (iter.pDesc->chunkState == OFFLINE) { + warn("Reading dead block"); + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + STATUS_DEALLOCATED_OR_UNWRITTEN_LOGICAL_BLOCK); + } + + if (err) { + if (idx <= 0xFFFFFFFF) { + ((IOContext *)context)->resp.entry.dword0 |= idx; + } + else { + ((IOContext *)context)->resp.entry.reserved |= (idx >> 32); + } + } + + idx <<= 1; + } + + if (!err) { + ((IOContext *)context)->resp.entry.dword0 = 0xFFFFFFFF; + ((IOContext *)context)->resp.entry.reserved = 0xFFFFFFFF; + } + else { + // Remove invalid LBAs + uint64_t mask = ((IOContext *)context)->resp.entry.reserved; + idx = 1; + + mask <<= 32; + mask |= ((IOContext *)context)->resp.entry.dword0; + + for (auto iter = pContext->list.begin(); iter != pContext->list.end();) { + if (mask & idx) { + iter = pContext->list.erase(iter); + } + else { + iter++; + } + + idx <<= 1; + } + } + + DMAFunction doRead = [this](uint64_t tick, void *context) { + auto pContext = (OCSSDContext *)context; + + tick = MAX(tick, pContext->beginAt); + + uint64_t beginAt; + uint64_t finishedAt = tick; + + for (auto &iter : pContext->list) { + beginAt = pContext->beginAt; + + pPALOLD->read(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + pContext->req.finishedAt = finishedAt; + completionQueue.push(pContext->req); + + updateCompletion(); + + delete pContext; + }; + + execute(CPU::NVME__OCSSD, CPU::READ_INTERNAL, doRead, pContext); +} + +void OpenChannelSSD20::writeInternal(std::vector &lbaList, + DMAFunction &func, void *context, + bool mode) { + OCSSDContext *pContext = new OCSSDContext(); + std::vector chunks; + bool err = false; + uint64_t idx = 1; + + pContext->req = Request(func, context); + pContext->beginAt = + getTick() + applyLatency(CPU::NVME__OCSSD, CPU::CONVERT_UNIT); + + convertUnit(lbaList, pContext->list, chunks, false, mode); + + // Update ChunkDescriptor + for (auto &iter : chunks) { + // Check block status + if (iter.pDesc->chunkState == OFFLINE) { + err = true; + warn("Writing to dead chunk"); + } + else if (iter.pDesc->chunkState == CLOSED) { + err = true; + warn("Writing to closed chunk"); + } + // Check write pointer + else if (iter.pDesc->chunkState == OPEN && + iter.pDesc->writePointer / structure.writeSize > iter.pageIdx) { + err = true; + warn("Write pointer violation"); + } + + if (err) { + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + 0xF2); // Out of order write + } + else { + // Update write pointer + iter.pDesc->writePointer = (iter.pageIdx + 1) * structure.writeSize; + iter.pDesc->chunkState = OPEN; + + // Do we need to close this chunk? + if (iter.pageIdx == param.page - 1) { + iter.pDesc->chunkState = CLOSED; + } + } + + if (err) { + if (idx <= 0xFFFFFFFF) { + ((IOContext *)context)->resp.entry.dword0 |= idx; + } + else { + ((IOContext *)context)->resp.entry.reserved |= (idx >> 32); + } + } + + idx <<= 1; + } + + if (!err) { + ((IOContext *)context)->resp.entry.dword0 = 0xFFFFFFFF; + ((IOContext *)context)->resp.entry.reserved = 0xFFFFFFFF; + } + else { + // Remove invalid LBAs + uint64_t mask = ((IOContext *)context)->resp.entry.reserved; + idx = 1; + + mask <<= 32; + mask |= ((IOContext *)context)->resp.entry.dword0; + + for (auto iter = pContext->list.begin(); iter != pContext->list.end();) { + if (mask & idx) { + iter = pContext->list.erase(iter); + } + else { + iter++; + } + + idx <<= 1; + } + } + + DMAFunction doWrite = [this](uint64_t tick, void *context) { + auto pContext = (OCSSDContext *)context; + + tick = MAX(tick, pContext->beginAt); + + uint64_t beginAt; + uint64_t finishedAt = tick; + + for (auto &iter : pContext->list) { + beginAt = pContext->beginAt; + + pPALOLD->write(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + pContext->req.finishedAt = finishedAt; + completionQueue.push(pContext->req); + + updateCompletion(); + + delete pContext; + }; + + execute(CPU::NVME__OCSSD, CPU::WRITE_INTERNAL, doWrite, pContext); +} + +void OpenChannelSSD20::eraseInternal(std::vector &lbaList, + DMAFunction &func, void *context, + bool mode) { + OCSSDContext *pContext = new OCSSDContext(); + std::vector chunks; + bool err = false; + uint64_t idx = 1; + + pContext->req = Request(func, context); + pContext->beginAt = + getTick() + applyLatency(CPU::NVME__OCSSD, CPU::CONVERT_UNIT); + + convertUnit(lbaList, pContext->list, chunks, true, mode); + + ((IOContext *)context)->resp.entry.dword0 = 0; + ((IOContext *)context)->resp.entry.reserved = 0; + + // Update ChunkDescriptor + for (auto &iter : chunks) { + // Check block status + if (iter.pDesc->chunkState == OFFLINE) { + err = true; + warn("Erasing dead chunk"); + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + 0xC0); // Offline chunk + } + else if (iter.pDesc->chunkState == FREE || iter.pDesc->chunkState == OPEN) { + err = true; + warn("Erasing free or open chunk"); + + ((IOContext *)context) + ->resp.makeStatus(false, false, TYPE_MEDIA_AND_DATA_INTEGRITY_ERROR, + 0xC1); // Invalid reset + } + else { + // Update + iter.pDesc->writePointer = 0; + iter.pDesc->chunkState = FREE; + } + + if (err) { + if (idx <= 0xFFFFFFFF) { + ((IOContext *)context)->resp.entry.dword0 |= idx; + } + else { + ((IOContext *)context)->resp.entry.reserved |= (idx >> 32); + } + } + + idx <<= 1; + } + + if (!err) { + ((IOContext *)context)->resp.entry.dword0 = 0xFFFFFFFF; + ((IOContext *)context)->resp.entry.reserved = 0xFFFFFFFF; + } + else { + // Remove invalid LBAs + uint64_t mask = ((IOContext *)context)->resp.entry.reserved; + idx = 1; + + mask <<= 32; + mask |= ((IOContext *)context)->resp.entry.dword0; + + for (auto iter = pContext->list.begin(); iter != pContext->list.end();) { + if (mask & idx) { + iter = pContext->list.erase(iter); + } + else { + iter++; + } + + idx <<= 1; + } + } + + DMAFunction doErase = [this](uint64_t tick, void *context) { + auto pContext = (OCSSDContext *)context; + + tick = MAX(tick, pContext->beginAt); + + uint64_t beginAt; + uint64_t finishedAt = tick; + + for (auto &iter : pContext->list) { + beginAt = pContext->beginAt; + pPALOLD->erase(iter, beginAt); + + finishedAt = MAX(finishedAt, beginAt); + } + + pContext->req.finishedAt = finishedAt; + completionQueue.push(pContext->req); + + updateCompletion(); + + delete pContext; + }; + + execute(CPU::NVME__OCSSD, CPU::ERASE_INTERNAL, doErase, pContext); +} + +bool OpenChannelSSD20::getLogPage(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t numdl = (req.entry.dword10 & 0xFFFF0000) >> 16; + uint16_t lid = req.entry.dword10 & 0xFFFF; + uint16_t numdu = req.entry.dword11 & 0xFFFF; + uint32_t lopl = req.entry.dword12; + uint32_t lopu = req.entry.dword13; + bool ret = false; + bool submit = true; + + uint32_t req_size = (((uint32_t)numdu << 16 | numdl) + 1) * 4; + uint64_t offset = ((uint64_t)lopu << 32) | lopl; + + debugprint(LOG_HIL_NVME, + "ADMIN | Get Log Page | Log %d | Size %d | NSID %d", lid, + req_size, req.entry.namespaceID); + + static DMAFunction dmaDone = [](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + DMAFunction smartInfo = [offset](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->dma->write(offset, pContext->nlb, pContext->buffer, dmaDone, + context); + }; + + switch (lid) { + case LOG_ERROR_INFORMATION: + case LOG_SMART_HEALTH_INFORMATION: + case LOG_FIRMWARE_SLOT_INFORMATION: + ret = true; + break; + case LOG_CHUNK_INFORMATION: { + ret = true; + submit = false; + IOContext *pContext = new IOContext(func, resp); + + // Fill data + pContext->buffer = (uint8_t *)pDescriptor; + pContext->nlb = req_size; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2, (uint64_t)req_size); + } + } break; + default: + ret = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_LOG_PAGE); + break; + } + + if (submit) { + func(resp); + } + + return ret; +} + +bool OpenChannelSSD20::geometry(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + + RequestContext *pContext = new RequestContext(func, resp); + + pContext->buffer = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + debugprint(LOG_HIL_NVME, "OCSSD | Geometry"); + + // Fill Geometry Information + pContext->buffer[0x00] = 2; // OpenChannel SSD Spec Rev. 2.0 + pContext->buffer[0x01] = 0; + pContext->buffer[0x08] = popcount(ppaMask.channelMask); + pContext->buffer[0x09] = popcount(ppaMask.wayMask); + pContext->buffer[0x0A] = popcount(ppaMask.blockMask); + pContext->buffer[0x0B] = popcount(ppaMask.sectorMask); + pContext->buffer[0x20] = 0x7F; + + // Geometry Related + *(uint16_t *)(pContext->buffer + 0x40) = structure.group; + *(uint16_t *)(pContext->buffer + 0x42) = structure.parallelUnit; + *(uint32_t *)(pContext->buffer + 0x44) = structure.chunk; + *(uint32_t *)(pContext->buffer + 0x48) = structure.chunkSize; + + // Write Data Requrements + *(uint32_t *)(pContext->buffer + 0x80) = structure.writeSize; + *(uint32_t *)(pContext->buffer + 0x84) = structure.writeSize; + + // Performance Related Metrics + PAL::Config::NANDTiming *pNANDTiming = conf.getNANDTiming(); + + *(uint32_t *)(pContext->buffer + 0xC0) = pNANDTiming->msb.read / 1000; + *(uint32_t *)(pContext->buffer + 0xC8) = pNANDTiming->msb.write / 1000; + + if (conf.readInt(CONFIG_PAL, PAL::NAND_FLASH_TYPE) != PAL::NAND_SLC) { + *(uint32_t *)(pContext->buffer + 0xC4) = pNANDTiming->lsb.read / 1000; + *(uint32_t *)(pContext->buffer + 0xCC) = pNANDTiming->lsb.write / 1000; + } + else { + *(uint32_t *)(pContext->buffer + 0xC4) = pNANDTiming->msb.read / 1000; + *(uint32_t *)(pContext->buffer + 0xCC) = pNANDTiming->msb.write / 1000; + } + + *(uint32_t *)(pContext->buffer + 0xD0) = pNANDTiming->erase / 1000; + *(uint32_t *)(pContext->buffer + 0xD4) = pNANDTiming->erase / 1000; + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + static DMAFunction doWrite = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + + return true; +} + +void OpenChannelSSD20::read(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + // bool fua = req.entry.dword12 & 0x40000000; + + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to read 0 blocks"); + } + + readCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | READ | %" PRIX64 " + %d", slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction doWrite = [this](uint64_t tick, void *context) { + DMAFunction dmaDone = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | READ | %" PRIX64 " + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + if (pContext->buffer) { + free(pContext->buffer); + } + + delete pContext->dma; + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | READ | %" PRIX64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + pContext->buffer = (uint8_t *)calloc(pContext->nlb, LBA_SIZE); + + pDisk->read(pContext->slba, pContext->nlb, pContext->buffer); + pContext->dma->write(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + IOContext *pContext = (IOContext *)context; + std::vector input = {pContext->slba, pContext->nlb}; + + readInternal(input, doWrite, pContext); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__OCSSD, CPU::READ); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * LBA_SIZE); + } + } + else { + func(resp); + } +} + +void OpenChannelSSD20::write(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint64_t slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + uint16_t nlb = (req.entry.dword12 & 0xFFFF) + 1; + + if (nlb == 0) { + err = true; + warn("nvme_namespace: host tried to write 0 blocks"); + } + + writeCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | WRITE | %" PRIX64 " + %d", slba, nlb); + + if (!err) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | WRITE | %" PRIX64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->function(pContext->resp); + + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->tick = tick; + + if (pContext->buffer) { + pDisk->write(pContext->slba, pContext->nlb, pContext->buffer); + + free(pContext->buffer); + } + + debugprint(LOG_HIL_NVME, + "OCSSD | WRITE | %" PRIX64 " + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + delete pContext->dma; + + std::vector input = {pContext->slba, pContext->nlb}; + + writeInternal(input, doWrite, context); + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = (uint8_t *)calloc(pContext->nlb, LBA_SIZE); + pContext->dma->read(0, pContext->nlb * LBA_SIZE, pContext->buffer, + dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = slba; + pContext->nlb = nlb; + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::NVME__OCSSD, CPU::WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nlb * LBA_SIZE); + } + } + else { + func(resp); + } +} + +void OpenChannelSSD20::datasetManagement(SQEntryWrapper &req, + RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + int nr = (req.entry.dword10 & 0xFF) + 1; + bool ad = req.entry.dword11 & 0x04; + + if (!ad) { + err = true; + // Just ignore + } + + eraseCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | TRIM | %d ranges | Attr %1X", nr, + req.entry.dword11 & 0x0F); + + if (!err) { + static DMAFunction eachTrimDone = [](uint64_t tick, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(tick, pContext->context); + } + + delete pContext; + }; + DMAFunction doTrim = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t, void *context) { + DMAFunction trimDone = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "NVM | ERASE | %" PRIu64 " - %" PRIu64 " (%" PRIu64 + ")", + pContext->beginAt, tick, tick - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + DatasetManagementRange range; + IOContext *pContext = (IOContext *)context; + DMAContext *pDMA = new DMAContext(trimDone); + + pDMA->context = context; + + for (uint64_t i = 0; i < pContext->slba; i++) { + memcpy(range.data, + pContext->buffer + i * sizeof(DatasetManagementRange), + sizeof(DatasetManagementRange)); + + pDMA->counter++; + + pDisk->erase(range.slba, range.nlb); + + std::vector input = {range.slba, range.nlb}; + + eraseInternal(input, eachTrimDone, pDMA); + } + + free(pContext->buffer); + delete pContext->dma; + }; + + IOContext *pContext = (IOContext *)context; + + pContext->buffer = + (uint8_t *)calloc(pContext->slba, sizeof(DatasetManagementRange)); + + pContext->dma->read(0, pContext->slba * sizeof(DatasetManagementRange), + pContext->buffer, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->beginAt = getTick(); + pContext->slba = nr; + + CPUContext *pCPU = new CPUContext(doTrim, pContext, CPU::NVME__OCSSD, + CPU::DATASET_MANAGEMENT); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, (uint64_t)nr * 0x10); + } + } + else { + func(resp); + } +} + +void OpenChannelSSD20::vectorChunkRead(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + VectorContext *pContext = new VectorContext(func, resp); + + pContext->slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + pContext->nlb = (req.entry.dword12 & 0x0000003F) + 1; + pContext->beginAt = getTick(); + + vectorReadCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Vector Chunk Read | %d lbas", + pContext->nlb); + + DMAFunction doDMA = [this](uint64_t, void *context) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction eachRead = [this](uint64_t, void *context) { + DMAFunction dmaDone = [](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + + // Done + debugprint(LOG_HIL_NVME, + "OCSSD | Vector Chunk Read | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + // Do Read + uint64_t size = (pContext->nlb + 1) * LBA_SIZE; + pContext->buffer = (uint8_t *)calloc(size, 1); + + for (uint64_t i = 0; i < pContext->nlb; i++) { + uint64_t lba = pContext->lbaList.at(i); + + pDisk->read(lba, 1, pContext->buffer + i * LBA_SIZE); + } + + pContext->dma->write(0, size, pContext->buffer, dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + std::vector<::CPDPBP> list; + + // Collect LBA List + if (pContext->nlb > 1) { + for (uint64_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + else { + pContext->lbaList.push_back(pContext->slba); + } + + // Do Read + readInternal(pContext->lbaList, eachRead, context, true); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + uint64_t size = pContext->nlb * 8; + + pContext->buffer = (uint8_t *)calloc(size, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, size, pContext->buffer, + doRead, pContext); + } + else { + doRead(0, pContext); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::VECTOR_CHUNK_WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * LBA_SIZE); + } +} + +void OpenChannelSSD20::vectorChunkWrite(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + VectorContext *pContext = new VectorContext(func, resp); + + pContext->slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + pContext->nlb = (req.entry.dword12 & 0x0000003F) + 1; + pContext->beginAt = getTick(); + + vectorWriteCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Vector Chunk Write | %d lbas", + pContext->nlb); + + DMAFunction doDMA = [this](uint64_t, void *context) { + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction eachWrite = [this](uint64_t, void *context) { + DMAFunction dmaDone = [this](uint64_t now, void *context) { + VectorContext *pContext = (VectorContext *)context; + uint64_t mask = pContext->resp.entry.reserved; + + mask <<= 32; + mask |= pContext->resp.entry.dword0; + + if (pContext->resp.entry.dword3.status == 0) { + mask = 0; + } + + // Write to disk + for (uint64_t i = 0; i < pContext->nlb; i++) { + if ((1 << i) & mask) { + continue; + } + + uint64_t lba = pContext->lbaList.at(i); + + pDisk->write(lba, 1, pContext->buffer + i * LBA_SIZE); + } + + // Done + debugprint(LOG_HIL_NVME, + "OCSSD | Vector Chunk Write | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + VectorContext *pContext = (VectorContext *)context; + + // Do Read + uint64_t size = pContext->nlb * LBA_SIZE; + pContext->buffer = (uint8_t *)calloc(size, 1); + pContext->dma->read(0, size, pContext->buffer, dmaDone, context); + }; + + VectorContext *pContext = (VectorContext *)context; + std::vector<::CPDPBP> list; + + // Collect LBA List + if (pContext->nlb > 1) { + for (uint64_t i = 0; i < pContext->nlb; i++) { + pContext->lbaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + else { + pContext->lbaList.push_back(pContext->slba); + } + + // Do Write + writeInternal(pContext->lbaList, eachWrite, context, true); + }; + + VectorContext *pContext = (VectorContext *)context; + + if (pContext->nlb > 1) { + uint64_t size = pContext->nlb * 8; + + pContext->buffer = (uint8_t *)calloc(size, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, size, pContext->buffer, + doRead, pContext); + } + else { + doRead(0, pContext); + } + }; + + CPUContext *pCPU = new CPUContext(doDMA, pContext, CPU::NVME__OCSSD, + CPU::VECTOR_CHUNK_WRITE); + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, cpuHandler, pCPU, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, cpuHandler, pCPU, req.entry.data1, + req.entry.data2, pContext->nlb * LBA_SIZE); + } +} + +void OpenChannelSSD20::vectorChunkReset(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + IOContext *pContext = new IOContext(func, resp); + + pContext->slba = ((uint64_t)req.entry.dword11 << 32) | req.entry.dword10; + pContext->nlb = (req.entry.dword12 & 0x0000003F) + 1; + pContext->beginAt = getTick(); + + vectorEraseCount++; + + debugprint(LOG_HIL_NVME, "OCSSD | Vector Chunk Reset | %d lbas", + pContext->nlb); + + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction eachErase = [](uint64_t now, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_NVME, + "OCSSD | Vector Chunk Reset | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->beginAt, now, now - pContext->beginAt); + + pContext->function(pContext->resp); + + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + std::vector lbaList; + std::vector<::CPDPBP> list; + + // Collect LBA List + if (pContext->nlb > 1) { + for (uint64_t i = 0; i < pContext->nlb; i++) { + lbaList.push_back(*(uint64_t *)(pContext->buffer + i * 8)); + } + + free(pContext->buffer); + } + else { + lbaList.push_back(pContext->slba); + } + + // Do Reset + eraseInternal(lbaList, eachErase, context, true); + }; + + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::NVME__OCSSD, + CPU::VECTOR_CHUNK_RESET); + + if (pContext->nlb > 1) { + uint64_t size = pContext->nlb * 8; + + pContext->buffer = (uint8_t *)calloc(size, 1); + + cfgdata.pInterface->dmaRead(pContext->slba, size, pContext->buffer, + cpuHandler, pCPU); + } + else { + doRead(0, pContext); + } +} + +void OpenChannelSSD20::getStatList(std::vector &list, + std::string prefix) { + Stats temp; + + temp.name = prefix + "command_count"; + temp.desc = "Total number of OCSSD command handled"; + list.push_back(temp); + + temp.name = prefix + "erase"; + temp.desc = "Total number of TRIM (Erase) command"; + list.push_back(temp); + + temp.name = prefix + "read"; + temp.desc = "Total number of Read command"; + list.push_back(temp); + + temp.name = prefix + "write"; + temp.desc = "Total number of Write command"; + list.push_back(temp); + + temp.name = prefix + "vector.erase"; + temp.desc = "Total number of Vector Chunk Reset command"; + list.push_back(temp); + + temp.name = prefix + "vector.read"; + temp.desc = "Total number of Vector Chunk Read command"; + list.push_back(temp); + + temp.name = prefix + "vector.write"; + temp.desc = "Total number of Vector Chunk Write command"; + list.push_back(temp); + + pPALOLD->getStatList(list, prefix + "pal."); +} + +void OpenChannelSSD20::getStatValues(std::vector &values) { + values.push_back(commandCount); + values.push_back(eraseCount); + values.push_back(readCount); + values.push_back(writeCount); + values.push_back(vectorEraseCount); + values.push_back(vectorReadCount); + values.push_back(vectorWriteCount); + + pPALOLD->getStatValues(values); +} + +void OpenChannelSSD20::resetStatValues() { + commandCount = 0; + eraseCount = 0; + readCount = 0; + writeCount = 0; + vectorEraseCount = 0; + vectorReadCount = 0; + vectorWriteCount = 0; + + pPALOLD->resetStatValues(); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/ocssd.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/ocssd.hh new file mode 100644 index 0000000000..326c413b8d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/ocssd.hh @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_OCSSD__ +#define __HIL_NVME_OCSSD__ + +#include "hil/nvme/subsystem.hh" +#include "pal/pal.hh" +#include "pal/pal_old.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +#define LBA_SIZE 4096 // Always OCSSD's logical block size is 4K + +typedef struct _BlockData { + uint32_t index; + uint8_t value; + + _BlockData(); + _BlockData(uint32_t, uint8_t); +} BlockData; + +typedef union _ChunkDescriptor { + uint8_t data[32]; + struct { + uint8_t chunkState; + uint8_t chunkType; + uint8_t wearLevelIndex; + uint8_t reserved1; + uint32_t reserved2; + uint64_t slba; + uint64_t nlb; + uint64_t writePointer; + }; +} ChunkDescriptor; + +typedef enum { + FREE = 0x01, //!< Erased (WP = 0) + CLOSED = 0x02, //!< Fulled (WP = max) + OPEN = 0x04, //!< Writing (WP < max) + OFFLINE = 0x08, //!< Dead +} CHUNK_STATE; + +typedef struct _ChunkUpdateEntry { + ChunkDescriptor *pDesc; + uint32_t pageIdx; + + _ChunkUpdateEntry(ChunkDescriptor *, uint32_t); +} ChunkUpdateEntry; + +typedef struct { + uint32_t group; // Channel + uint32_t parallelUnit; // Way + uint32_t chunk; // Blocks + uint32_t chunkSize; // Block Size / LBA_SIZE + uint32_t writeSize; // Page Size / LBA_SIZE +} Geometry; + +typedef struct { + uint64_t padding; + uint64_t channelMask; + uint32_t channelShift; + uint64_t wayMask; + uint32_t wayShift; + uint64_t dieMask; + uint32_t dieShift; + uint64_t planeMask; + uint32_t planeShift; + uint64_t blockMask; + uint32_t blockShift; + uint64_t pageMask; + uint32_t pageShift; + uint64_t sectorMask; +} Mask; + +class VectorContext : public IOContext { + public: + std::vector lbaList; + + VectorContext(RequestFunction &f, CQEntryWrapper &r) : IOContext(f, r) {} +}; + +class OpenChannelSSD12 : public Subsystem { + protected: + PAL::Parameter param; + PAL::PALOLD *pPALOLD; + + Disk *pDisk; + + Geometry structure; + Mask ppaMask; + + uint64_t lastScheduled; + Event completionEvent; + std::priority_queue, Request> completionQueue; + + // Stats + uint64_t eraseCount; + uint64_t readCount; + uint64_t writeCount; + + void updateCompletion(); + void completion(); + + private: + std::unordered_map badBlocks; + + bool parsePPA(uint64_t, ::CPDPBP &); + void convertUnit(::CPDPBP &); + void mergeList(std::vector &, std::vector<::CPDPBP> &, + bool = false); + + // Commands + bool deviceIdentification(SQEntryWrapper &, RequestFunction &); + bool setBadBlockTable(SQEntryWrapper &, RequestFunction &); + bool getBadBlockTable(SQEntryWrapper &, RequestFunction &); + void physicalBlockErase(SQEntryWrapper &, RequestFunction &); + void physicalPageWrite(SQEntryWrapper &, RequestFunction &); + void physicalPageRead(SQEntryWrapper &, RequestFunction &); + + public: + OpenChannelSSD12(Controller *, ConfigData &); + ~OpenChannelSSD12(); + + void init() override; + + void submitCommand(SQEntryWrapper &, RequestFunction) override; + void getNVMCapacity(uint64_t &, uint64_t &) override; + uint32_t validNamespaceCount() override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +class OpenChannelSSD20 : public OpenChannelSSD12 { + private: + ChunkDescriptor *pDescriptor; + uint64_t descriptorLength; + + uint64_t vectorEraseCount; + uint64_t vectorReadCount; + uint64_t vectorWriteCount; + + ChunkDescriptor *getChunkDescriptor(uint32_t, uint32_t, uint32_t); + uint64_t makeLBA(uint32_t, uint32_t, uint32_t, uint32_t); + void parseLBA(uint64_t, uint32_t &, uint32_t &, uint32_t &, uint32_t &); + void convertUnit(std::vector &, std::vector<::CPDPBP> &, + std::vector &, bool = false, bool = false); + void readInternal(std::vector &, DMAFunction &, void *, + bool = false); + void writeInternal(std::vector &, DMAFunction &, void *, + bool = false); + void eraseInternal(std::vector &, DMAFunction &, void *, + bool = false); + + // Commands + bool getLogPage(SQEntryWrapper &, RequestFunction &); + bool geometry(SQEntryWrapper &, RequestFunction &); + void read(SQEntryWrapper &, RequestFunction &); + void write(SQEntryWrapper &, RequestFunction &); + void datasetManagement(SQEntryWrapper &, RequestFunction &); + void vectorChunkRead(SQEntryWrapper &, RequestFunction &); + void vectorChunkWrite(SQEntryWrapper &, RequestFunction &); + void vectorChunkReset(SQEntryWrapper &, RequestFunction &); + + public: + OpenChannelSSD20(Controller *, ConfigData &); + ~OpenChannelSSD20(); + + void init() override; + + void submitCommand(SQEntryWrapper &, RequestFunction) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/queue.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/queue.cc new file mode 100644 index 0000000000..a9287575a7 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/queue.cc @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/queue.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +SQEntry::_SQEntry() { + memset(data, 0, 64); +} + +CQEntry::_CQEntry() { + memset(data, 0, 16); +} + +SQEntryWrapper::_SQEntryWrapper(SQEntry &sqdata, uint16_t sqid, uint16_t cqid, + uint16_t sqhead, uint16_t squid) + : entry(sqdata), + sqID(sqid), + cqID(cqid), + sqHead(sqhead), + sqUID(squid), + useSGL(true) { + if ((sqdata.dword0.fuse >> 6) == 0x00) { + useSGL = false; + } +} + +CQEntryWrapper::_CQEntryWrapper(SQEntryWrapper &sqew) { + cqID = sqew.cqID; + sqUID = sqew.sqUID; + entry.dword2.sqHead = sqew.sqHead; + entry.dword2.sqID = sqew.sqID; + entry.dword3.commandID = sqew.entry.dword0.commandID; +} + +void CQEntryWrapper::makeStatus(bool dnr, bool more, STATUS_CODE_TYPE sct, + int sc) { + entry.dword3.status = 0x0000; + + entry.dword3.status = ((dnr ? 1 : 0) << 15); + entry.dword3.status |= ((more ? 1 : 0) << 14); + entry.dword3.status |= ((sct & 0x07) << 9); + entry.dword3.status |= ((sc & 0xFF) << 1); +} + +Queue::Queue(uint16_t qid, uint16_t length) + : id(qid), head(0), tail(0), size(length), stride(0), base(nullptr) {} + +Queue::~Queue() { + if (base) { + delete base; + } +} + +uint16_t Queue::getID() { + return id; +} + +uint16_t Queue::getItemCount() { + if (tail >= head) { + return tail - head; + } + else { + return (size - head) + tail; + } +} + +uint16_t Queue::getHead() { + return head; +} + +uint16_t Queue::getTail() { + return tail; +} + +uint16_t Queue::getSize() { + return size; +} + +void Queue::setBase(DMAInterface *p, uint64_t s) { + base = p; + stride = s; +} + +CQueue::CQueue(uint16_t iv, bool en, uint16_t qid, uint16_t size) + : Queue(qid, size), ien(en), phase(true), interruptVector(iv) {} + +void CQueue::setData(CQEntry *entry, DMAFunction func, void *context) { + if (entry) { + // Set phase + entry->dword3.status &= 0xFFFE; + entry->dword3.status |= (phase ? 0x0001 : 0x0000); + + // Write entry + base->write(tail * stride, 0x10, entry->data, func, context); + + // Increase tail + tail++; + + if (tail == size) { + tail = 0; + phase = !phase; + } + + if (head == tail) { + panic("Completion queue overflow"); + } + } +} + +uint16_t CQueue::incHead() { + head++; + + if (head == size) { + head = 0; + } + + return head; +} + +void CQueue::setHead(uint16_t newHead) { + head = newHead; +} + +bool CQueue::interruptEnabled() { + return ien; +} + +uint16_t CQueue::getInterruptVector() { + return interruptVector; +} + +SQueue::SQueue(uint16_t cqid, uint8_t pri, uint16_t qid, uint16_t size) + : Queue(qid, size), cqID(cqid), priority(pri) {} + +uint16_t SQueue::getCQID() { + return cqID; +} + +void SQueue::setTail(uint16_t newTail) { + tail = newTail; +} + +void SQueue::getData(SQEntry *entry, DMAFunction func, void *context) { + if (entry && head != tail) { + // Read entry + base->read(head * stride, 0x40, entry->data, func, context); + + // Increase head + head++; + + if (head == size) { + head = 0; + } + } +} + +uint8_t SQueue::getPriority() { + return priority; +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/queue.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/queue.hh new file mode 100644 index 0000000000..5846f292f4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/queue.hh @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_NVME_QUEUE__ +#define __HIL_NVME_QUEUE__ + +#include "hil/nvme/def.hh" +#include "hil/nvme/dma.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +typedef union _SQEntry { + uint8_t data[64]; + struct { + struct { + uint8_t opcode; + uint8_t fuse; + uint16_t commandID; + } dword0; + uint32_t namespaceID; + uint32_t reserved1; + uint32_t reserved2; + uint64_t metadata; + uint64_t data1; + uint64_t data2; + uint32_t dword10; + uint32_t dword11; + uint32_t dword12; + uint32_t dword13; + uint32_t dword14; + uint32_t dword15; + }; + + _SQEntry(); +} SQEntry; + +typedef union _CQEntry { + uint8_t data[16]; + struct { + uint32_t dword0; + uint32_t reserved; + struct { + uint16_t sqHead; + uint16_t sqID; + } dword2; + struct { + uint16_t commandID; + uint16_t status; + } dword3; + }; + + _CQEntry(); +} CQEntry; + +typedef struct _SQEntryWrapper { + SQEntry entry; + + uint16_t sqID; + uint16_t cqID; + uint16_t sqHead; + uint16_t sqUID; //!< HEAD - 1 + + bool useSGL; + + _SQEntryWrapper(SQEntry &, uint16_t, uint16_t, uint16_t, uint16_t); +} SQEntryWrapper; + +typedef struct _CQEntryWrapper { + CQEntry entry; + + uint64_t submitAt; + + uint16_t cqID; //!< sqID at entry.dword2 + uint16_t sqUID; //!< Head - 1 + + _CQEntryWrapper(SQEntryWrapper &); + void makeStatus(bool, bool, STATUS_CODE_TYPE, int); +} CQEntryWrapper; + +class Queue { + protected: + uint16_t id; + + uint16_t head; + uint16_t tail; + + uint16_t size; + uint64_t stride; + + DMAInterface *base; + + public: + Queue(uint16_t, uint16_t); + ~Queue(); + + uint16_t getID(); + uint16_t getItemCount(); + uint16_t getHead(); + uint16_t getTail(); + uint16_t getSize(); + void setBase(DMAInterface *, uint64_t); +}; + +class CQueue : public Queue { + protected: + bool ien; + bool phase; + uint16_t interruptVector; + + public: + CQueue(uint16_t, bool, uint16_t, uint16_t); + + void setData(CQEntry *, DMAFunction, void *); + uint16_t incHead(); + void setHead(uint16_t); + bool interruptEnabled(); + uint16_t getInterruptVector(); +}; + +class SQueue : public Queue { + protected: + uint16_t cqID; + uint8_t priority; + + public: + SQueue(uint16_t, uint8_t, uint16_t, uint16_t); + + uint16_t getCQID(); + void setTail(uint16_t); + void getData(SQEntry *, DMAFunction, void *); + uint8_t getPriority(); +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/subsystem.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/subsystem.cc new file mode 100644 index 0000000000..ae7cace698 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/subsystem.cc @@ -0,0 +1,1320 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/nvme/subsystem.hh" + +#include +#include + +#include "hil/nvme/controller.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +const uint32_t nLBAFormat = 4; +const uint32_t lbaFormat[nLBAFormat] = { + 0x02090000, // 512B + 0, Good performance + 0x020A0000, // 1KB + 0, Good performance + 0x010B0000, // 2KB + 0, Better performance + 0x000C0000, // 4KB + 0, Best performance +}; +const uint32_t lbaSize[nLBAFormat] = { + 512, // 512B + 1024, // 1KB + 2048, // 2KB + 4096, // 4KB +}; + +Subsystem::Subsystem(Controller *ctrl, ConfigData &cfg) + : AbstractSubsystem(ctrl, cfg), + pHIL(nullptr), + allocatedLogicalPages(0), + commandCount(0) {} + +Subsystem::~Subsystem() { + for (auto &iter : lNamespaces) { + delete iter; + } + + delete pHIL; +} + +void Subsystem::init() { + pHIL = new HIL(conf); + uint16_t nNamespaces = + (uint16_t)conf.readUint(CONFIG_NVME, NVME_ENABLE_DEFAULT_NAMESPACE); + + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + if (nNamespaces > 0) { + Namespace::Information info; + uint64_t totalSize; + uint32_t lba = (uint32_t)conf.readUint(CONFIG_NVME, NVME_LBA_SIZE); + + for (info.lbaFormatIndex = 0; info.lbaFormatIndex < nLBAFormat; + info.lbaFormatIndex++) { + if (lbaSize[info.lbaFormatIndex] == lba) { + info.lbaSize = lbaSize[info.lbaFormatIndex]; + + break; + } + } + + if (info.lbaFormatIndex == nLBAFormat) { + panic("Failed to setting LBA size (512B ~ 4KB)"); + } + + // Fill Namespace information + totalSize = totalLogicalPages * logicalPageSize / lba; + info.dataProtectionSettings = 0x00; + info.namespaceSharingCapabilities = 0x00; + + for (uint16_t i = 0; i < nNamespaces; i++) { + info.size = totalSize / nNamespaces; + info.capacity = info.size; + + if (createNamespace(NSID_LOWEST + i, &info)) { + lNamespaces.back()->attach(true); + } + else { + panic("Failed to create namespace"); + } + } + } +} + +void Subsystem::convertUnit(Namespace *ns, uint64_t slba, uint64_t nlblk, + Request &req) { + Namespace::Information *info = ns->getInfo(); + uint32_t lbaratio = logicalPageSize / info->lbaSize; + uint64_t slpn; + uint64_t nlp; + uint64_t off; + + if (lbaratio == 0) { + lbaratio = info->lbaSize / logicalPageSize; + + slpn = slba * lbaratio; + nlp = nlblk * lbaratio; + + req.range.slpn = slpn + info->range.slpn; + req.range.nlp = nlp; + req.offset = 0; + req.length = nlblk * info->lbaSize; + } + else { + slpn = slba / lbaratio; + off = slba % lbaratio; + nlp = (nlblk + off + lbaratio - 1) / lbaratio; + + req.range.slpn = slpn + info->range.slpn; + req.range.nlp = nlp; + req.offset = off * info->lbaSize; + req.length = nlblk * info->lbaSize; + } +} + +bool Subsystem::createNamespace(uint32_t nsid, Namespace::Information *info) { + std::list allocated; + std::list unallocated; + + // Allocate LPN + uint64_t requestedLogicalPages = + info->size / logicalPageSize * lbaSize[info->lbaFormatIndex]; + uint64_t unallocatedLogicalPages = totalLogicalPages - allocatedLogicalPages; + + if (requestedLogicalPages > unallocatedLogicalPages) { + return false; + } + + // Collect allocated slots + for (auto &iter : lNamespaces) { + allocated.push_back(iter->getInfo()->range); + } + + // Sort + allocated.sort([](const LPNRange &a, const LPNRange &b) -> bool { + return a.slpn < b.slpn; + }); + + // Merge + auto iter = allocated.begin(); + + if (iter != allocated.end()) { + auto next = iter; + + while (true) { + next++; + + if (iter != allocated.end() || next == allocated.end()) { + break; + } + + if (iter->slpn + iter->nlp == next->slpn) { + iter = allocated.erase(iter); + next = iter; + } + else { + iter++; + } + } + } + + // Invert + unallocated.push_back(LPNRange(0, totalLogicalPages)); + + for (auto &iter : allocated) { + // Split last item + auto &last = unallocated.back(); + + if (last.slpn <= iter.slpn && + last.slpn + last.nlp >= iter.slpn + iter.nlp) { + unallocated.push_back(LPNRange( + iter.slpn + iter.nlp, last.slpn + last.nlp - iter.slpn - iter.nlp)); + last.nlp = iter.slpn - last.slpn; + } + else { + panic("BUG"); + } + } + + // Allocated unallocated area to namespace + for (auto iter = unallocated.begin(); iter != unallocated.end(); iter++) { + if (iter->nlp >= requestedLogicalPages) { + info->range = *iter; + info->range.nlp = requestedLogicalPages; + + break; + } + } + + if (info->range.nlp == 0) { + return false; + } + + allocatedLogicalPages += requestedLogicalPages; + + // Fill Information + info->sizeInByteL = requestedLogicalPages * logicalPageSize; + info->sizeInByteH = 0; + + // Create namespace + Namespace *pNS = new Namespace(this, cfgdata); + pNS->setData(nsid, info); + + lNamespaces.push_back(pNS); + debugprint(LOG_HIL_NVME, + "NS %-5d| CREATE | LBA size %" PRIu32 " | Capacity %" PRIu64, nsid, + info->lbaSize, info->size); + + lNamespaces.sort([](Namespace *lhs, Namespace *rhs) -> bool { + return lhs->getNSID() < rhs->getNSID(); + }); + + return true; +} + +bool Subsystem::destroyNamespace(uint32_t nsid) { + bool found = false; + Namespace::Information *info; + + for (auto iter = lNamespaces.begin(); iter != lNamespaces.end(); iter++) { + if ((*iter)->getNSID() == nsid) { + found = true; + + debugprint(LOG_HIL_NVME, "NS %-5d| DELETE", nsid); + + info = (*iter)->getInfo(); + allocatedLogicalPages -= info->size * info->lbaSize / logicalPageSize; + + delete *iter; + + lNamespaces.erase(iter); + + break; + } + } + + return found; +} + +void Subsystem::fillIdentifyNamespace(uint8_t *buffer, + Namespace::Information *info) { + // Namespace Size + memcpy(buffer + 0, &info->size, 8); + + // Namespace Capacity + memcpy(buffer + 8, &info->capacity, 8); + + // Namespace Utilization + // This function also called from OpenChannelSSD subsystem + if (pHIL) { + info->utilization = + pHIL->getUsedPageCount(info->range.slpn, + info->range.slpn + info->range.nlp) * + logicalPageSize / info->lbaSize; + } + + memcpy(buffer + 16, &info->utilization, 8); + + // Namespace Features + // [Bits ] Description + // [07:05] Reserved + // [04:04] NVM Set capabilities + // [03:03] Reuse of NGUID field + // [02:02] 1 for Support Deallocated or Unwritten Logical Block error + // [01:01] 1 for NAWUN, NAWUPF, NACWU are defined + // [00:00] 1 for Support Thin Provisioning + buffer[24] = 0x04; // Trim supported + + // Number of LBA Formats + buffer[25] = nLBAFormat - 1; // 0's based + + // Formatted LBA Size + buffer[26] = info->lbaFormatIndex; + + // End-to-end Data Protection Capabilities + buffer[28] = info->dataProtectionSettings; + + // Namespace Multi-path I/O and Namespace Sharing Capabilities + buffer[30] = info->namespaceSharingCapabilities; + + // NVM capacity + memcpy(buffer + 48, &info->sizeInByteL, 8); + memcpy(buffer + 56, &info->sizeInByteH, 8); + + // LBA Formats + for (uint32_t i = 0; i < nLBAFormat; i++) { + memcpy(buffer + 128 + i * 4, lbaFormat + i, 4); + } + + // OpenChannel SSD + if (!pHIL) { + buffer[384] = 0x01; + } +} + +void Subsystem::submitCommand(SQEntryWrapper &req, RequestFunction func) { + struct CommandContext { + SQEntryWrapper req; + RequestFunction func; + + CommandContext(SQEntryWrapper &r, RequestFunction &f) : req(r), func(f) {} + }; + + CQEntryWrapper resp(req); + bool processed = false; + + commandCount++; + + // Admin command + if (req.sqID == 0) { + switch (req.entry.dword0.opcode) { + case OPCODE_DELETE_IO_SQUEUE: + processed = deleteSQueue(req, func); + break; + case OPCODE_CREATE_IO_SQUEUE: + processed = createSQueue(req, func); + break; + case OPCODE_GET_LOG_PAGE: + processed = getLogPage(req, func); + break; + case OPCODE_DELETE_IO_CQUEUE: + processed = deleteCQueue(req, func); + break; + case OPCODE_CREATE_IO_CQUEUE: + processed = createCQueue(req, func); + break; + case OPCODE_IDENTIFY: + processed = identify(req, func); + break; + case OPCODE_ABORT: + processed = abort(req, func); + break; + case OPCODE_SET_FEATURES: + processed = setFeatures(req, func); + break; + case OPCODE_GET_FEATURES: + processed = getFeatures(req, func); + break; + case OPCODE_ASYNC_EVENT_REQ: + break; + case OPCODE_NAMESPACE_MANAGEMENT: + processed = namespaceManagement(req, func); + break; + case OPCODE_NAMESPACE_ATTACHMENT: + processed = namespaceAttachment(req, func); + break; + case OPCODE_FORMAT_NVM: + processed = formatNVM(req, func); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_OPCODE); + break; + } + } + + // NVM commands or Namespace specific Admin commands + if (!processed) { + if (req.entry.namespaceID < NSID_ALL) { + for (auto &iter : lNamespaces) { + if (iter->getNSID() == req.entry.namespaceID) { + auto pContext = new CommandContext(req, func); + DMAFunction doSubmit = [iter](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + iter->submitCommand(pContext->req, pContext->func); + + delete pContext; + }; + + execute(CPU::NVME__NAMESPACE, CPU::SUBMIT_COMMAND, doSubmit, + pContext); + + return; + } + } + } + else { + if (lNamespaces.size() > 0) { + auto pContext = new CommandContext(req, func); + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + lNamespaces.front()->submitCommand(pContext->req, pContext->func); + + delete pContext; + }; + + execute(CPU::NVME__NAMESPACE, CPU::SUBMIT_COMMAND, doSubmit, pContext); + + processed = true; + } + } + } + + // Invalid namespace + if (!processed) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + + func(resp); + } +} + +void Subsystem::getNVMCapacity(uint64_t &total, uint64_t &used) { + total = totalLogicalPages * logicalPageSize; + used = allocatedLogicalPages * logicalPageSize; +} + +uint32_t Subsystem::validNamespaceCount() { + return (uint32_t)lNamespaces.size(); +} + +void Subsystem::read(Namespace *ns, uint64_t slba, uint64_t nlblk, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doRead = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->read(*req); + + delete req; + }; + + convertUnit(ns, slba, nlblk, *req); + + execute(CPU::NVME__SUBSYSTEM, CPU::CONVERT_UNIT, doRead, req); +} + +void Subsystem::write(Namespace *ns, uint64_t slba, uint64_t nlblk, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doWrite = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->write(*req); + + delete req; + }; + + convertUnit(ns, slba, nlblk, *req); + + execute(CPU::NVME__SUBSYSTEM, CPU::CONVERT_UNIT, doWrite, req); +} + +void Subsystem::flush(Namespace *ns, DMAFunction &func, void *context) { + Request req(func, context); + Namespace::Information *info = ns->getInfo(); + + req.range.slpn = info->range.slpn; + req.range.nlp = info->range.nlp; + req.offset = 0; + req.length = info->range.nlp * logicalPageSize; + + pHIL->flush(req); +} + +void Subsystem::trim(Namespace *ns, uint64_t slba, uint64_t nlblk, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doTrim = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->trim(*req); + + delete req; + }; + + convertUnit(ns, slba, nlblk, *req); + + execute(CPU::NVME__SUBSYSTEM, CPU::CONVERT_UNIT, doTrim, req); +} + +bool Subsystem::deleteSQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t sqid = req.entry.dword10 & 0xFFFF; + + debugprint(LOG_HIL_NVME, "ADMIN | Delete I/O Submission Queue"); + + int ret = pParent->deleteSQueue(sqid); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + + func(resp); + + return true; +} + +bool Subsystem::createSQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + bool err = false; + + uint16_t sqid = req.entry.dword10 & 0xFFFF; + uint16_t entrySize = ((req.entry.dword10 & 0xFFFF0000) >> 16) + 1; + uint16_t cqid = (req.entry.dword11 & 0xFFFF0000) >> 16; + uint8_t priority = (req.entry.dword11 & 0x06) >> 1; + bool pc = req.entry.dword11 & 0x01; + + debugprint(LOG_HIL_NVME, "ADMIN | Create I/O Submission Queue"); + + if (entrySize > cfgdata.maxQueueEntry) { + err = true; + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_SIZE); + } + + if (!err) { + RequestContext *pContext = new RequestContext(func, resp); + static DMAFunction doQueue = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext; + }; + + int ret = pParent->createSQueue(sqid, cqid, entrySize, priority, pc, + req.entry.data1, doQueue, pContext); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + else if (ret == 2) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_COMPLETION_QUEUE); + } + } + else { + func(resp); + } + + return true; +} + +bool Subsystem::getLogPage(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t numdl = (req.entry.dword10 & 0xFFFF0000) >> 16; + uint16_t lid = req.entry.dword10 & 0xFFFF; + uint16_t numdu = req.entry.dword11 & 0xFFFF; + uint32_t lopl = req.entry.dword12; + uint32_t lopu = req.entry.dword13; + bool ret = false; + bool submit = true; + + uint32_t req_size = (((uint32_t)numdu << 16 | numdl) + 1) * 4; + uint64_t offset = ((uint64_t)lopu << 32) | lopl; + + debugprint(LOG_HIL_NVME, + "ADMIN | Get Log Page | Log %d | Size %d | NSID %d", lid, + req_size, req.entry.namespaceID); + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext->dma; + delete pContext; + }; + DMAFunction smartInfo = [offset](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(offset, 512, pContext->buffer, dmaDone, context); + }; + + switch (lid) { + case LOG_ERROR_INFORMATION: + ret = true; + break; + case LOG_SMART_HEALTH_INFORMATION: { + if (req.entry.namespaceID == NSID_ALL) { + ret = true; + submit = false; + RequestContext *pContext = new RequestContext(func, resp); + + pContext->buffer = globalHealth.data; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, smartInfo, pContext, req.entry.data1, + req.entry.data2, (uint64_t)req_size); + } + } + } break; + case LOG_FIRMWARE_SLOT_INFORMATION: + ret = true; + break; + default: + ret = true; + resp.makeStatus(true, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_LOG_PAGE); + break; + } + + if (submit) { + func(resp); + } + + return ret; +} + +bool Subsystem::deleteCQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t cqid = req.entry.dword10 & 0xFFFF; + + debugprint(LOG_HIL_NVME, "ADMIN | Delete I/O Completion Queue"); + + int ret = pParent->deleteCQueue(cqid); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + else if (ret == 2) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_DELETE); + } + + func(resp); + + return true; +} + +bool Subsystem::createCQueue(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + bool err = false; + + uint16_t cqid = req.entry.dword10 & 0xFFFF; + uint16_t entrySize = ((req.entry.dword10 & 0xFFFF0000) >> 16) + 1; + uint16_t iv = (req.entry.dword11 & 0xFFFF0000) >> 16; + bool ien = req.entry.dword11 & 0x02; + bool pc = req.entry.dword11 & 0x01; + + debugprint(LOG_HIL_NVME, "ADMIN | Create I/O Completion Queue"); + + if (entrySize > cfgdata.maxQueueEntry) { + err = true; + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_SIZE); + } + + if (!err) { + RequestContext *pContext = new RequestContext(func, resp); + static DMAFunction doQueue = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext; + }; + + int ret = pParent->createCQueue(cqid, entrySize, iv, ien, pc, + req.entry.data1, doQueue, pContext); + + if (ret == 1) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_INVALID_QUEUE_ID); + } + } + else { + func(resp); + } + + return true; +} + +bool Subsystem::identify(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint8_t cns = req.entry.dword10 & 0xFF; + uint16_t cntid = (req.entry.dword10 & 0xFFFF0000) >> 16; + bool ret = true; + + RequestContext *pContext = new RequestContext(func, resp); + uint16_t idx = 0; + + pContext->buffer = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + debugprint(LOG_HIL_NVME, "ADMIN | Identify | CNS %d | CNTID %d | NSID %d", + cns, cntid, req.entry.namespaceID); + + switch (cns) { + case CNS_IDENTIFY_NAMESPACE: + if (req.entry.namespaceID == NSID_ALL) { + // FIXME: Not called by current(4.9.32) NVMe driver + } + else { + for (auto &iter : lNamespaces) { + if (iter->isAttached() && iter->getNSID() == req.entry.namespaceID) { + fillIdentifyNamespace(pContext->buffer, iter->getInfo()); + } + } + } + + break; + case CNS_IDENTIFY_CONTROLLER: + pParent->identify(pContext->buffer); + + break; + case CNS_ACTIVE_NAMESPACE_LIST: + if (req.entry.namespaceID >= NSID_ALL - 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + else { + for (auto &iter : lNamespaces) { + if (iter->isAttached() && iter->getNSID() > req.entry.namespaceID) { + ((uint32_t *)pContext->buffer)[idx++] = iter->getNSID(); + } + } + } + + break; + case CNS_ALLOCATED_NAMESPACE_LIST: + if (req.entry.namespaceID >= NSID_ALL - 1) { + err = true; + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + else { + for (auto &iter : lNamespaces) { + if (iter->getNSID() > req.entry.namespaceID) { + ((uint32_t *)pContext->buffer)[idx++] = iter->getNSID(); + } + } + } + + break; + case CNS_IDENTIFY_ALLOCATED_NAMESPACE: + for (auto &iter : lNamespaces) { + if (iter->getNSID() == req.entry.namespaceID) { + fillIdentifyNamespace(pContext->buffer, iter->getInfo()); + } + } + + break; + case CNS_ATTACHED_CONTROLLER_LIST: + // Only one controller + if (cntid == 0) { + ((uint16_t *)pContext->buffer)[idx++] = 1; + } + + break; + case CNS_CONTROLLER_LIST: + // Only one controller + if (cntid == 0) { + ((uint16_t *)pContext->buffer)[idx++] = 1; + } + + break; + } + + static DMAFunction dmaDone = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + static DMAFunction doWrite = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->write(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + if (ret && !err) { + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doWrite, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doWrite, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + } + else { + func(resp); + free(pContext->buffer); + delete pContext; + } + + return ret; +} + +bool Subsystem::abort(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t sqid = req.entry.dword10 & 0xFFFF; + uint16_t cid = (req.entry.dword10 & 0xFFFF0000) >> 16; + + debugprint(LOG_HIL_NVME, "ADMIN | Abort | SQID %d | CID %d", sqid, cid); + + int ret = pParent->abort(sqid, cid); + + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, STATUS_SUCCESS); + + if (ret == 0) { + resp.entry.dword0 = 1; + } + else { + resp.entry.dword0 = 0; + } + + func(resp); + + return true; +} + +bool Subsystem::setFeatures(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + static uint32_t cqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_CQUEUE); + static uint32_t sqsize = conf.readUint(CONFIG_NVME, NVME_MAX_IO_SQUEUE); + + CQEntryWrapper resp(req); + uint16_t fid = req.entry.dword10 & 0x00FF; + bool save = req.entry.dword10 & 0x80000000; + + debugprint(LOG_HIL_NVME, "ADMIN | Set Features | Feature %d | NSID %d", fid, + req.entry.namespaceID); + + if (save) { + err = true; + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_FEATURE_ID_NOT_SAVEABLE); + } + + if (!err) { + switch (fid) { + case FEATURE_NUMBER_OF_QUEUES: + if ((req.entry.dword11 & 0xFFFF) == 0xFFFF || + (req.entry.dword11 & 0xFFFF0000) == 0xFFFF0000) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + else { + if ((req.entry.dword11 & 0xFFFF) >= sqsize) { + req.entry.dword11 = (req.entry.dword11 & 0xFFFF0000) | (sqsize - 1); + } + if (((req.entry.dword11 & 0xFFFF0000) >> 16) >= cqsize) { + req.entry.dword11 = + (req.entry.dword11 & 0xFFFF) | ((uint32_t)(cqsize - 1) << 16); + } + + resp.entry.dword0 = req.entry.dword11; + queueAllocated = resp.entry.dword0; + } + + break; + case FEATURE_INTERRUPT_COALESCING: + pParent->setCoalescingParameter((req.entry.dword11 >> 8) & 0xFF, + req.entry.dword11 & 0xFF); + break; + case FEATURE_INTERRUPT_VECTOR_CONFIGURATION: + pParent->setCoalescing(req.entry.dword11 & 0xFFFF, + req.entry.dword11 & 0x10000); + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + break; + } + } + + func(resp); + + return true; +} + +bool Subsystem::getFeatures(SQEntryWrapper &req, RequestFunction &func) { + CQEntryWrapper resp(req); + uint16_t fid = req.entry.dword10 & 0x00FF; + + debugprint(LOG_HIL_NVME, "ADMIN | Get Features | Feature %d | NSID %d", fid, + req.entry.namespaceID); + + switch (fid) { + case FEATURE_ARBITRATION: + resp.entry.dword0 = + ((uint8_t)(conf.readUint(CONFIG_NVME, NVME_WRR_HIGH) * + conf.readUint(CONFIG_NVME, NVME_WRR_MEDIUM) - + 1) + << 24) | + ((conf.readUint(CONFIG_NVME, NVME_WRR_MEDIUM) - 1) << 16) | 0x03; + break; + case FEATURE_VOLATILE_WRITE_CACHE: + resp.entry.dword0 = + conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE) ? 0x01 : 0x00; + break; + case FEATURE_NUMBER_OF_QUEUES: + resp.entry.dword0 = queueAllocated; + break; + case FEATURE_INTERRUPT_COALESCING: + pParent->getCoalescingParameter(resp.entry.data + 1, resp.entry.data); + break; + case FEATURE_INTERRUPT_VECTOR_CONFIGURATION: + resp.entry.dword0 = (req.entry.dword11 & 0xFFFF) | 0; + + if (pParent->getCoalescing(req.entry.dword11 & 0xFFFF)) { + resp.entry.dword0 |= 0x10000; + } + + break; + default: + resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + break; + } + + func(resp); + + return true; +} + +bool Subsystem::asyncEventReq(SQEntryWrapper &, RequestFunction &) { + // FIXME: Not implemented + return true; +} + +bool Subsystem::namespaceManagement(SQEntryWrapper &req, + RequestFunction &func) { + struct NamespaceManagementContext : public RequestContext { + uint32_t nsid; + + NamespaceManagementContext(RequestFunction &f, CQEntryWrapper &r) + : RequestContext(f, r), nsid(NSID_NONE) {} + }; + + bool err = false; + + CQEntryWrapper resp(req); + uint8_t sel = req.entry.dword10 & 0x0F; + + debugprint(LOG_HIL_NVME, "ADMIN | Namespace Management | OP %d | NSID %d", + sel, req.entry.namespaceID); + + static DMAFunction dmaDone = [this](uint64_t, void *context) { + Namespace::Information info; + NamespaceManagementContext *pContext = + (NamespaceManagementContext *)context; + + // Copy data + memcpy(&info.size, pContext->buffer + 0, 8); + memcpy(&info.capacity, pContext->buffer + 8, 8); + info.lbaFormatIndex = pContext->buffer[26]; + info.dataProtectionSettings = pContext->buffer[29]; + info.namespaceSharingCapabilities = pContext->buffer[30]; + + if (info.lbaFormatIndex >= nLBAFormat) { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_FORMAT); + } + else if (info.namespaceSharingCapabilities != 0x00) { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + else if (info.dataProtectionSettings != 0x00) { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + info.lbaSize = lbaSize[info.lbaFormatIndex]; + + bool ret = createNamespace(pContext->nsid, &info); + + if (ret) { + pContext->resp.entry.dword0 = pContext->nsid; + } + else { + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_INSUFFICIENT_CAPACITY); + } + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + static DMAFunction doRead = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->dma->read(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + if ((sel == 0x00 && req.entry.namespaceID != NSID_NONE) || sel > 0x01) { + err = true; + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + + if (!err) { + err = false; + + if (sel == 0x00) { // Create + uint32_t nsid = NSID_LOWEST; + + for (auto &iter : lNamespaces) { + if (iter->getNSID() == nsid) { + nsid++; + } + else { + break; + } + } + + if (nsid == NSID_ALL) { + resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_ID_UNAVAILABLE); + } + else { + // Do not response immediately + err = true; + + NamespaceManagementContext *pContext = + new NamespaceManagementContext(func, resp); + + pContext->buffer = (uint8_t *)calloc(0x1000, sizeof(uint8_t)); + pContext->nsid = nsid; + + if (req.useSGL) { + pContext->dma = new SGL(cfgdata, doRead, pContext, req.entry.data1, + req.entry.data2); + } + else { + pContext->dma = + new PRPList(cfgdata, doRead, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + } + } + else { // Delete + bool found = destroyNamespace(req.entry.namespaceID); + + if (!found) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + } + } + + if (!err) { + func(resp); + } + + return true; +} + +bool Subsystem::namespaceAttachment(SQEntryWrapper &req, + RequestFunction &func) { + CQEntryWrapper resp(req); + + uint8_t sel = req.entry.dword10 & 0x0F; + uint32_t nsid = req.entry.namespaceID; + + debugprint(LOG_HIL_NVME, "ADMIN | Namespace Attachment | OP %d | NSID %d", + req.entry.dword10 & 0x0F, req.entry.namespaceID); + + static DMAFunction dmaDone = [this](uint64_t, void *context) { + bool err = false; + IOContext *pContext = (IOContext *)context; + uint16_t *ctrlList = (uint16_t *)pContext->buffer; + std::vector list; + + uint8_t sel = (uint8_t)pContext->slba; + uint32_t nsid = (uint32_t)pContext->nlb; + + for (uint16_t i = 1; i <= ctrlList[0]; i++) { + list.push_back(ctrlList[i]); + } + + if (list.size() > 1 && sel == 0x00) { + err = true; + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_IS_PRIVATE); + } + else if (list.size() == 0) { + err = true; + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_CONTROLLER_LIST_INVALID); + } + else if (list.at(0) != 0) { // Controller ID is zero + err = true; + pContext->resp.makeStatus(false, false, TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_CONTROLLER_LIST_INVALID); + } + + if (!err) { + if (sel == 0x00) { // Attach + bool exist = false; + + for (auto &iter : lNamespaces) { + if (iter->getNSID() == nsid) { + exist = true; + + if (iter->isAttached()) { + err = true; + pContext->resp.makeStatus(true, false, + TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_ALREADY_ATTACHED); + } + else { + iter->attach(true); + } + } + } + + if (!exist) { + err = true; + pContext->resp.makeStatus(true, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + } + else if (sel == 0x01) { // Detach + for (auto &iter : lNamespaces) { + if (iter->getNSID() == nsid) { + if (iter->isAttached()) { + iter->attach(false); + } + else { + err = true; + pContext->resp.makeStatus(true, false, + TYPE_COMMAND_SPECIFIC_STATUS, + STATUS_NAMESPACE_NOT_ATTACHED); + } + } + } + } + else { + pContext->resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FIELD); + } + } + + pContext->function(pContext->resp); + + free(pContext->buffer); + delete pContext->dma; + delete pContext; + }; + + static DMAFunction doRead = [](uint64_t, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->dma->read(0, 0x1000, pContext->buffer, dmaDone, context); + }; + + IOContext *pContext = new IOContext(func, resp); + + pContext->buffer = (uint8_t *)calloc(0x1000, 1); + pContext->slba = sel; + pContext->nlb = nsid; + + if (req.useSGL) { + pContext->dma = + new SGL(cfgdata, doRead, pContext, req.entry.data1, req.entry.data2); + } + else { + pContext->dma = new PRPList(cfgdata, doRead, pContext, req.entry.data1, + req.entry.data2, (uint64_t)0x1000); + } + + return true; +} + +bool Subsystem::formatNVM(SQEntryWrapper &req, RequestFunction &func) { + bool err = false; + + CQEntryWrapper resp(req); + uint8_t ses = (req.entry.dword10 & 0x0E00) >> 9; + bool pil = req.entry.dword10 & 0x0100; + uint8_t pi = (req.entry.dword10 & 0xE0) >> 5; + bool mset = req.entry.dword10 & 0x10; + uint8_t lbaf = req.entry.dword10 & 0x0F; + bool submit = true; + + debugprint(LOG_HIL_NVME, "ADMIN | Format NVM | SES %d | NSID %d", ses, + req.entry.namespaceID); + + static DMAFunction doFormat = [](uint64_t, void *context) { + RequestContext *pContext = (RequestContext *)context; + + pContext->function(pContext->resp); + + delete pContext; + }; + + if (ses != 0x00 && ses != 0x01) { + err = true; + } + if (pil || mset) { + err = true; + } + if (pi != 0x00) { + err = true; + } + if (lbaf >= nLBAFormat) { + err = true; + } + + if (err) { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_INVALID_FORMAT); + } + else { + // Update Namespace + auto iter = lNamespaces.begin(); + Namespace::Information *info = nullptr; + + for (; iter != lNamespaces.end(); iter++) { + if ((*iter)->getNSID() == req.entry.namespaceID) { + info = (*iter)->getInfo(); + + break; + } + } + + if (info) { + submit = false; + + info->lbaFormatIndex = lbaf; + info->lbaSize = lbaSize[lbaf]; + info->size = totalLogicalPages * logicalPageSize / info->lbaSize; + info->capacity = info->size; + + // Reset health stat and set format progress + (*iter)->format(getTick()); + + info->utilization = + pHIL->getUsedPageCount(info->range.slpn, + info->range.slpn + info->range.nlp) * + logicalPageSize / info->lbaSize; + + // Send format command to HIL + RequestContext *pContext = new RequestContext(func, resp); + Request *req = new Request(doFormat, pContext); + + req->range = info->range; + + DMAFunction job = [this, ses](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->format(*req, ses == 0x01); + + delete req; + }; + + execute(CPU::NVME__SUBSYSTEM, CPU::FORMAT_NVM, job, req); + } + else { + resp.makeStatus(false, false, TYPE_GENERIC_COMMAND_STATUS, + STATUS_ABORT_INVALID_NAMESPACE); + } + } + + if (submit) { + func(resp); + } + + return true; +} + +void Subsystem::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "command_count"; + temp.desc = "Total number of NVMe command handled"; + list.push_back(temp); + + pHIL->getStatList(list, prefix); +} + +void Subsystem::getStatValues(std::vector &values) { + values.push_back(commandCount); + + pHIL->getStatValues(values); +} + +void Subsystem::resetStatValues() { + commandCount = 0; + + pHIL->resetStatValues(); +} + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/subsystem.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/subsystem.hh new file mode 100644 index 0000000000..daf0536144 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/nvme/subsystem.hh @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_NVME_SUBSYSTEM__ +#define __HIL_NVME_SUBSYSTEM__ + +#include "hil/hil.hh" +#include "hil/nvme/abstract_subsystem.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace NVMe { + +class Subsystem : public AbstractSubsystem { + protected: + HIL *pHIL; + + std::list lNamespaces; + uint32_t queueAllocated; + + HealthInfo globalHealth; + uint32_t logicalPageSize; + uint64_t totalLogicalPages; + uint64_t allocatedLogicalPages; + + // Stats + uint64_t commandCount; + + void convertUnit(Namespace *, uint64_t, uint64_t, Request &); + bool createNamespace(uint32_t, Namespace::Information *); + bool destroyNamespace(uint32_t); + void fillIdentifyNamespace(uint8_t *, Namespace::Information *); + + // Admin commands + bool deleteSQueue(SQEntryWrapper &, RequestFunction &); + bool createSQueue(SQEntryWrapper &, RequestFunction &); + bool getLogPage(SQEntryWrapper &, RequestFunction &); + bool deleteCQueue(SQEntryWrapper &, RequestFunction &); + bool createCQueue(SQEntryWrapper &, RequestFunction &); + bool identify(SQEntryWrapper &, RequestFunction &); + bool abort(SQEntryWrapper &, RequestFunction &); + bool setFeatures(SQEntryWrapper &, RequestFunction &); + bool getFeatures(SQEntryWrapper &, RequestFunction &); + bool asyncEventReq(SQEntryWrapper &, RequestFunction &); + bool namespaceManagement(SQEntryWrapper &, RequestFunction &); + bool namespaceAttachment(SQEntryWrapper &, RequestFunction &); + bool formatNVM(SQEntryWrapper &, RequestFunction &); + + public: + Subsystem(Controller *, ConfigData &); + ~Subsystem(); + + void init() override; + + void submitCommand(SQEntryWrapper &, RequestFunction) override; + void getNVMCapacity(uint64_t &, uint64_t &) override; + uint32_t validNamespaceCount() override; + + void read(Namespace *, uint64_t, uint64_t, DMAFunction &, void *); + void write(Namespace *, uint64_t, uint64_t, DMAFunction &, void *); + void flush(Namespace *, DMAFunction &, void *); + void trim(Namespace *, uint64_t, uint64_t, DMAFunction &, void *); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace NVMe + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/config.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/config.cc new file mode 100644 index 0000000000..40f331cb57 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/config.cc @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/sata/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +const char NAME_PCIE_GEN[] = "PCIEGeneration"; +const char NAME_PCIE_LANE[] = "PCIELane"; +const char NAME_AXI_BUS_WIDTH[] = "AXIBusWidth"; +const char NAME_AXI_CLOCK[] = "AXIClock"; +const char NAME_SATA_MODE[] = "SATAMode"; +const char NAME_WORK_INTERVAL[] = "WorkInterval"; +const char NAME_MAX_REQUEST_COUNT[] = "MaxRequestCount"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_ENABLE_DISK_IMAGE[] = "EnableDiskImage"; +const char NAME_STRICT_DISK_SIZE[] = "StrictSizeCheck"; +const char NAME_DISK_IMAGE_PATH[] = "DiskImageFile"; +const char NAME_USE_COW_DISK[] = "UseCopyOnWriteDisk"; + +Config::Config() { + pcieGen = PCIExpress::PCIE_3_X; + pcieLane = 4; + axiWidth = ARM::AXI::BUS_128BIT; + axiClock = 250000000; + sataMode = SimpleSSD::SATA::SATA_3_0; + workInterval = 50000; + maxRequestCount = 4; + lbaSize = 512; + enableDiskImage = false; + strictDiskSize = false; + diskImagePath = ""; + useCopyOnWriteDisk = false; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_PCIE_GEN)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + pcieGen = PCIExpress::PCIE_1_X; + break; + case 1: + pcieGen = PCIExpress::PCIE_2_X; + break; + case 2: + pcieGen = PCIExpress::PCIE_3_X; + break; + default: + panic("Invalid PCI Express Generation"); + break; + } + } + else if (MATCH_NAME(NAME_PCIE_LANE)) { + pcieLane = (uint8_t)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_AXI_BUS_WIDTH)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + axiWidth = ARM::AXI::BUS_32BIT; + break; + case 1: + axiWidth = ARM::AXI::BUS_64BIT; + break; + case 2: + axiWidth = ARM::AXI::BUS_128BIT; + break; + case 3: + axiWidth = ARM::AXI::BUS_256BIT; + break; + case 4: + axiWidth = ARM::AXI::BUS_512BIT; + break; + case 5: + axiWidth = ARM::AXI::BUS_1024BIT; + break; + default: + panic("Invalid AXI Stream Bus Width"); + break; + } + } + else if (MATCH_NAME(NAME_AXI_CLOCK)) { + axiClock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SATA_MODE)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + sataMode = SimpleSSD::SATA::SATA_1_0; + break; + case 1: + sataMode = SimpleSSD::SATA::SATA_2_0; + break; + case 2: + sataMode = SimpleSSD::SATA::SATA_3_0; + break; + default: + panic("Invalid SATA Generation"); + break; + } + } + else if (MATCH_NAME(NAME_WORK_INTERVAL)) { + workInterval = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_REQUEST_COUNT)) { + maxRequestCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DISK_IMAGE)) { + enableDiskImage = convertBool(value); + } + else if (MATCH_NAME(NAME_STRICT_DISK_SIZE)) { + strictDiskSize = convertBool(value); + } + else if (MATCH_NAME(NAME_DISK_IMAGE_PATH)) { + diskImagePath = value; + } + else if (MATCH_NAME(NAME_USE_COW_DISK)) { + useCopyOnWriteDisk = convertBool(value); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (popcount(lbaSize) != 1) { + panic("Invalid LBA size"); + } + if (maxRequestCount == 0) { + panic("MaxRequestCount should be larger then 0"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case SATA_PCIE_GEN: + ret = pcieGen; + break; + case SATA_AXI_BUS_WIDTH: + ret = axiWidth; + break; + case SATA_MODE: + ret = sataMode; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case SATA_PCIE_LANE: + ret = pcieLane; + break; + case SATA_AXI_CLOCK: + ret = axiClock; + break; + case SATA_WORK_INTERVAL: + ret = workInterval; + break; + case SATA_MAX_REQUEST_COUNT: + ret = maxRequestCount; + break; + case SATA_LBA_SIZE: + ret = lbaSize; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret(""); + + switch (idx) { + case SATA_DISK_IMAGE_PATH: + ret = diskImagePath; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case SATA_ENABLE_DISK_IMAGE: + ret = enableDiskImage; + break; + case SATA_STRICT_DISK_SIZE: + ret = strictDiskSize; + break; + case SATA_USE_COW_DISK: + ret = useCopyOnWriteDisk; + break; + } + + return ret; +} + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/config.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/config.hh new file mode 100644 index 0000000000..4f6b01f1e1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/config.hh @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_CONFIG__ +#define __HIL_SATA_CONFIG__ + +#include "sim/base_config.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +typedef enum { + SATA_PCIE_GEN, + SATA_PCIE_LANE, + SATA_AXI_BUS_WIDTH, + SATA_AXI_CLOCK, + SATA_MODE, + SATA_WORK_INTERVAL, + SATA_MAX_REQUEST_COUNT, + SATA_LBA_SIZE, + SATA_ENABLE_DISK_IMAGE, + SATA_STRICT_DISK_SIZE, + SATA_DISK_IMAGE_PATH, + SATA_USE_COW_DISK +} SATA_CONFIG; + +class Config : public BaseConfig { + private: + PCIExpress::PCIE_GEN pcieGen; //!< Default: PCIE_3_X + uint8_t pcieLane; //!< Default: 4 + ARM::AXI::BUS_WIDTH axiWidth; //!< Default: BUS_128BIT + uint64_t axiClock; //!< Default: 250000000 (250MHz) + SimpleSSD::SATA::SATA_GEN sataMode; //!< Default SATA_3_0 + uint64_t workInterval; //!< Default: 50000 (50ns) + uint64_t maxRequestCount; //!< Default: 4 + uint64_t lbaSize; //!< Default: 512 + bool enableDiskImage; //!< Default: False + bool strictDiskSize; //!< Default: False + bool useCopyOnWriteDisk; //!< Default: False + std::string diskImagePath; //!< Default: "" + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/def.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/def.hh new file mode 100644 index 0000000000..7d1035e870 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/def.hh @@ -0,0 +1,381 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_DEF__ +#define __HIL_SATA_DEF__ + +#include + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +// AHCI Generic Host Controller Register +typedef union { + uint8_t data[0x100]; + struct { + uint32_t capability; + uint32_t globalHBAControl; + uint32_t interruptStatus; + uint32_t portsImplemented; + uint32_t AHCIVersion; + uint32_t commandCompletionCoalescingControl; + uint32_t commandCompletionCoalescingPorts; + uint32_t enclosureManagementLocation; + uint32_t enclosureManagementControl; + uint32_t HBACapabilityExtended; + uint32_t handoffControlAndStatus; + }; +} AHCIGHCRegister; + +// AHCI Port Register +typedef union { + uint8_t data[0x80]; + struct { + uint64_t commandListBaseAddress; + uint64_t FISBaseAddress; + uint32_t interruptStatus; + uint32_t interruptEnable; + uint32_t commandAndStatus; + uint32_t reserved1; + uint32_t taskFileData; + uint32_t signature; + uint32_t status; + uint32_t control; + uint32_t error; + uint32_t active; + uint32_t commandIssue; + uint32_t notification; + uint32_t switchingControl; + uint32_t deviceSleep; + }; +} AHCIPortRegister; + +// Index of AHCI GHC Register +enum : uint8_t { + REG_CAP = 0x00, + REG_GHC = 0x04, + REG_IS = 0x08, + REG_PI = 0x0C, + REG_VS = 0x10, + REG_CCC_CTL = 0x14, + REG_CCC_PORTS = 0x18, + REG_EM_LOC = 0x1C, + REG_EM_CTL = 0x20, + REG_CAP2 = 0x24, + REG_BOHC = 0x28, +}; + +// Index of AHCI Port Register +enum : uint8_t { + REG_P0CLB = 0x00, + REG_P0CLBU = 0x04, + REG_P0FB = 0x08, + REG_P0FBU = 0x0C, + REG_P0IS = 0x10, + REG_P0IE = 0x14, + REG_P0CMD = 0x18, + REG_P0TFD = 0x20, + REG_P0SIG = 0x24, + REG_P0SSTS = 0x28, + REG_P0SCTL = 0x2C, + REG_P0SERR = 0x30, + REG_P0SACT = 0x34, + REG_P0CI = 0x38, + REG_P0SNTF = 0x3C, + REG_P0FBS = 0x40, + REG_P0DEVSLP = 0x44 +}; + +// Register bits +enum : uint32_t { + // GHC > GHC (Generic HBA Control) + HOST_RESET = (1 << 0), /* reset controller; self-clear */ + HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ + HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ + HOST_AHCI_EN = ((uint32_t)1 << 31), /* AHCI enabled */ + + // GHC > EM_CTL + EM_CTL_RST = (1 << 9), /* Reset */ + EM_CTL_TM = (1 << 8), /* Transmit Message */ + EM_CTL_MR = (1 << 0), /* Message Received */ + EM_CTL_ALHD = (1 << 26), /* Activity LED */ + EM_CTL_XMT = (1 << 25), /* Transmit Only */ + EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ + EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ + EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ + EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ + EM_CTL_LED = (1 << 16), /* LED messages supported */ + + // Port > IS/IE + PORT_IRQ_COLD_PRES = ((uint32_t)1 << 31), /* cold presence detect */ + PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ + PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ + PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ + PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ + PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ + PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ + PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ + + PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ + PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ + PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ + PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ + PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ + PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ + PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ + PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ + PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ + + // Port > CMD + PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ + PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ + PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ + PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ + PORT_CMD_ESP = (1 << 21), /* External Sata Port */ + PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ + PORT_CMD_PMP = (1 << 17), /* PMP attached */ + PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ + PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ + PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ + PORT_CMD_CLO = (1 << 3), /* Command list override */ + PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ + PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ + PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ + + // ATA Status + ATA_BUSY = (1 << 7), /* BSY status bit */ + ATA_DRDY = (1 << 6), /* device ready */ + ATA_DF = (1 << 5), /* device fault */ + ATA_DSC = (1 << 4), /* drive seek complete */ + ATA_DRQ = (1 << 3), /* data request i/o */ + ATA_CORR = (1 << 2), /* corrected data error */ + ATA_SENSE = (1 << 1), /* sense code available */ + ATA_ERR = (1 << 0), /* have an error */ + + // ATA Error + ATA_ICRC = (1 << 7), /* interface CRC error */ + ATA_BBK = ATA_ICRC, /* pre-EIDE: block marked bad */ + ATA_UNC = (1 << 6), /* uncorrectable media error */ + ATA_MC = (1 << 5), /* media changed */ + ATA_IDNF = (1 << 4), /* ID not found */ + ATA_MCR = (1 << 3), /* media change requested */ + ATA_ABORTED = (1 << 2), /* command aborted */ + ATA_TRK0NF = (1 << 1), /* track 0 not found */ + ATA_AMNF = (1 << 0), /* address mark not found */ +}; + +typedef union { + uint8_t data[32]; + struct { + uint16_t flags; + uint16_t prdtLength; + uint32_t prdByteCount; + uint64_t commandTableBaseAddress; + uint32_t reserved[4]; + }; +} CommandHeader; + +typedef union { + uint8_t data[16]; + struct { + uint64_t dataBaseAddress; + uint32_t reserved; + uint32_t dw3; + }; +} PRDT; + +// FIS Type +typedef enum : uint8_t { + FIS_TYPE_REG_H2D = 0x27, + FIS_TYPE_REG_D2H = 0x34, + FIS_TYPE_DMA_ACT = 0x39, + FIS_TYPE_DMA_SETUP = 0x41, + FIS_TYPE_DATA = 0x46, + FIS_TYPE_BIST = 0x58, + FIS_TYPE_PIO_SETUP = 0x5F, + FIS_TYPE_DEV_BITS = 0xA1, +} FIS_TYPE; + +// Register - H2D +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t command; + uint8_t featureL; + uint8_t lbaL[3]; + uint8_t device; + uint8_t lbaH[3]; + uint8_t featureH; + uint8_t countL; + uint8_t countH; + uint8_t icc; + uint8_t control; +} RegisterH2D; + +// Register - D2H +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t status; + uint8_t error; + uint8_t lbaL[3]; + uint8_t device; + uint8_t lbaH[3]; + uint8_t reserved; + uint8_t countL; + uint8_t countH; +} RegisterD2H; + +// Set Device Bits +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t status; + uint8_t command; + uint32_t payload; +} SetDeviceBits; + +// DMA Activate +typedef struct { + uint8_t type; + uint8_t flag; +} DMAActivate; + +// DMA Setup +typedef struct { + uint8_t type; + uint8_t flag; + uint16_t reserved1; + uint32_t reserved2[3]; + uint32_t bufferOffset; + uint32_t transferCount; +} DMASetup; + +// PIO Setup +typedef struct { + uint8_t type; + uint8_t flag; + uint8_t status; + uint8_t error; + uint8_t lbaL[3]; + uint8_t device; + uint8_t lbaH[3]; + uint8_t reserved1; + uint8_t countL; + uint8_t countH; + uint8_t reserved2; + uint8_t e_status; + uint16_t transferCount; +} PIOSetup; + +// FIS +typedef union { + uint8_t data[64]; + union { + RegisterH2D regH2D; + RegisterD2H regD2H; + SetDeviceBits sdb; + DMAActivate dmaAct; + DMASetup dmaSetup; + PIOSetup pioSetup; + }; +} FIS; + +// ACS-2 IDENTIFY DEVICE +enum { + ATA_ID_CONFIG = 0, + ATA_ID_SERNO = 10, + ATA_ID_FW_REV = 23, + ATA_ID_PROD = 27, + ATA_ID_MAX_MULTSECT = 47, + ATA_ID_DWORD_IO = 48, + ATA_ID_CAPABILITY = 49, + ATA_ID_FIELD_VALID = 53, + ATA_ID_MULTSECT = 59, + ATA_ID_LBA_CAPACITY = 60, + ATA_ID_MWDMA_MODES = 63, + ATA_ID_PIO_MODES = 64, + ATA_ID_EIDE_DMA_MIN = 65, + ATA_ID_EIDE_DMA_TIME = 66, + ATA_ID_EIDE_PIO = 67, + ATA_ID_EIDE_PIO_IORDY = 68, + ATA_ID_QUEUE_DEPTH = 75, + ATA_ID_SATA_CAPABILITY = 76, + ATA_ID_SATA_CAPABILITY_2 = 77, + ATA_ID_FEATURE_SUPP = 78, + ATA_ID_MAJOR_VER = 80, + ATA_ID_COMMAND_SET_1 = 82, + ATA_ID_COMMAND_SET_2 = 83, + ATA_ID_CFSSE = 84, + ATA_ID_CFS_ENABLE_1 = 85, + ATA_ID_CFS_ENABLE_2 = 86, + ATA_ID_CSF_DEFAULT = 87, + ATA_ID_UDMA_MODES = 88, + ATA_ID_HW_CONFIG = 93, + ATA_ID_SPG = 98, + ATA_ID_LBA_CAPACITY_2 = 100, + ATA_ID_SECTOR_SIZE = 106, + ATA_ID_WWN = 108, + ATA_ID_LOGICAL_SECTOR_SIZE = 117, /* and 118 */ + ATA_ID_COMMAND_SET_3 = 119, + ATA_ID_COMMAND_SET_4 = 120, + ATA_ID_LAST_LUN = 126, + ATA_ID_DLF = 128, + ATA_ID_DATA_SET_MGMT = 169, +}; + +// ACS-2 Command Set +typedef enum : uint8_t { + OPCODE_DATASET_MANAGEMENT = 0x06, + OPCODE_EXECUTE_DEVICE_DIAGNOSTIC = 0x90, + OPCODE_FLUSH_CACHE = 0xE7, + OPCODE_FLUSH_CACHE_EXT = 0xEA, + OPCODE_IDENTIFY_DEVICE = 0xEC, + OPCODE_READ_DMA = 0xC8, + OPCODE_READ_DMA_EXT = 0x25, + OPCODE_READ_FPDMA_QUEUED = 0x60, + OPCODE_READ_SECTOR = 0x20, + OPCODE_READ_SECTOR_EXT = 0x24, + OPCODE_READ_VERIFY_SECTOR = 0x40, + OPCODE_READ_VERIFY_SECTOR_EXT = 0x42, + OPCODE_SET_FEATURE = 0xEF, + OPCODE_SET_MULTIPLE_MODE = 0xC6, + OPCODE_WRITE_DMA = 0xCA, + OPCODE_WRITE_DMA_EXT = 0x35, + OPCODE_WRITE_FPDMA_QUEUED = 0x61, + OPCODE_WRITE_SECTOR = 0x30, + OPCODE_WRITE_SECTOR_EXT = 0x34, +} OPCODE; + +// ACS-2 SET FEATURE Fields +enum : uint8_t { + FEATURE_ENABLE_VOLATILE_CACHE = 0x02, + FEATURE_SET_XFER_MODE, +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/device.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/device.cc new file mode 100644 index 0000000000..c45727e2bd --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/device.cc @@ -0,0 +1,931 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/sata/device.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +#define MAKE_LBA(req) \ + ((uint64_t)req.regH2D.lbaL[0] | ((uint64_t)req.regH2D.lbaL[1] << 8) | \ + ((uint64_t)req.regH2D.lbaL[2] << 16)) +#define MAKE_LBA_EXT(req) \ + (((uint64_t)req.regH2D.lbaH[0] << 24) | \ + ((uint64_t)req.regH2D.lbaH[1] << 32) | \ + ((uint64_t)req.regH2D.lbaH[2] << 40) | MAKE_LBA(req)) + +uint32_t makeCount(FIS &req) { + uint32_t count = req.regH2D.countL; + + if (count == 0) { + count = 0x100; + } + + return count; +} + +uint32_t makeCountExt(FIS &req) { + uint32_t count = ((uint16_t)req.regH2D.countH << 8) | req.regH2D.countL; + + if (count == 0) { + count = 0x10000; + } + + return count; +} + +Device::Device(HBA *p, DMAInterface *d, ConfigReader &c) + : pParent(p), pDMA(d), pDisk(nullptr), conf(c) { + pHIL = new HIL(c); + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + lbaSize = conf.readUint(CONFIG_SATA, SATA_LBA_SIZE); + + // DMA Handler for PRDT + dmaHandler = [](uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + delete pContext; + } + }; + writeDMASetup = [this](uint64_t tick, void *context) { + _writeDMASetup(tick, context); + }; + writeDMADone = [this](uint64_t tick, void *context) { + _writeDMADone(tick, context); + }; + readDMASetup = [this](uint64_t tick, void *context) { + _readDMASetup(tick, context); + }; + readDMADone = [this](uint64_t tick, void *context) { + _readDMADone(tick, context); + }; + + if (conf.readBoolean(CONFIG_SATA, SATA_ENABLE_DISK_IMAGE)) { + uint64_t diskSize; + uint64_t expected; + + expected = totalLogicalPages * logicalPageSize; + + if (conf.readBoolean(CONFIG_SATA, SATA_USE_COW_DISK)) { + pDisk = new CoWDisk(); + } + else { + pDisk = new Disk(); + } + + std::string filename = conf.readString(CONFIG_SATA, SATA_DISK_IMAGE_PATH); + + diskSize = pDisk->open(filename, expected, + conf.readUint(CONFIG_SATA, SATA_LBA_SIZE)); + + if (diskSize == 0) { + panic("Failed to open disk image"); + } + else if (diskSize != expected) { + if (conf.readBoolean(CONFIG_SATA, SATA_STRICT_DISK_SIZE)) { + panic("Disk size not match"); + } + } + } +} + +Device::~Device() { + delete pHIL; + delete pDisk; +} + +void Device::init() { + debugprint(LOG_HIL_SATA, "ATA | COMRESET"); + + // COMRESET received + Completion resp; + + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + resp.fis.regD2H.error = 0x01; + resp.fis.regD2H.lbaL[0] = 0x01; + resp.fis.regD2H.countL = 0x01; + + pParent->submitSignal(resp); +} + +void Device::prdtRead(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doRead = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t read = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - read); + + pContext->counter++; + pDMA->dmaRead(table[idx].dataBaseAddress, size, buffer + read, dmaHandler, + context); + + read += size; + + if (read >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::SATA__DEVICE, CPU::PRDT_READ, doRead, pContext); +} + +void Device::prdtWrite(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doWrite = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t written = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - written); + + pContext->counter++; + pDMA->dmaWrite(table[idx].dataBaseAddress, size, buffer + written, + dmaHandler, context); + + written += size; + + if (written >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::SATA__DEVICE, CPU::PRDT_WRITE, doWrite, pContext); +} + +void Device::convertUnit(uint64_t slba, uint64_t nlblk, Request &req) { + uint32_t lbaratio = logicalPageSize / lbaSize; + uint64_t slpn; + uint64_t nlp; + uint64_t off; + + slpn = slba / lbaratio; + off = slba % lbaratio; + nlp = (nlblk + off + lbaratio - 1) / lbaratio; + + req.range.slpn = slpn; + req.range.nlp = nlp; + req.offset = off * lbaSize; + req.length = nlblk * lbaSize; +} + +void Device::read(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doRead = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->read(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->read(slba, nlb, buffer); + } + + execute(CPU::SATA__DEVICE, CPU::READ, doRead, req); +} + +void Device::write(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doWrite = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->write(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->write(slba, nlb, buffer); + } + + execute(CPU::SATA__DEVICE, CPU::WRITE, doWrite, req); +} + +void Device::flush(DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doFlush = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->flush(*req); + + delete req; + }; + + req->range.slpn = 0; + req->range.nlp = totalLogicalPages; + req->offset = 0; + req->length = totalLogicalPages * logicalPageSize; + + execute(CPU::SATA__DEVICE, CPU::FLUSH, doFlush, req); +} + +void Device::_writeDMASetup(uint64_t, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, "ATA | WRITE FPDMA QUEUED | Tag %d | Setup DMA", + pContext->tag); + + Completion resp; + + resp.fis.dmaSetup.type = FIS_TYPE_DMA_SETUP; + resp.fis.dmaSetup.flag = 0x00; // DMA from Host to Device + resp.fis.dmaSetup.reserved2[0] = pContext->tag; + resp.fis.dmaSetup.transferCount = + pContext->nlb * lbaSize; // TODO: Unit correct? + pContext->buffer = (uint8_t *)calloc(pContext->nlb, lbaSize); + pContext->beginAt = getTick(); + + pParent->submitFIS(resp); + + // Begin DMA + CPUContext *pCPU = new CPUContext(writeDMADone, pContext, CPU::SATA__DEVICE, + CPU::WRITE_DMA_SETUP); + + prdtRead(pContext->prdt, pContext->prdtLength, pContext->nlb * lbaSize, + pContext->buffer, cpuHandler, pCPU); +} + +void Device::_writeDMADone(uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "NVM | WRITE FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | DMA %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->beginAt, + tick, tick - pContext->beginAt); + + DMAFunction nandDone = [this](uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "NVM | WRITE FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | NAND %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->tick, + tick, tick - pContext->tick); + + Completion resp; + + resp.fis.sdb.type = FIS_TYPE_DEV_BITS; + resp.fis.sdb.flag = 0x40; + resp.fis.sdb.payload = (1 << pContext->tag); + + pParent->submitFIS(resp); + pContext->release(); + }; + + pContext->tick = tick; + + CPUContext *pCPU = new CPUContext(nandDone, pContext, CPU::SATA__DEVICE, + CPU::WRITE_DMA_DONE); + + write(pContext->slba, pContext->nlb, pContext->buffer, cpuHandler, pCPU); +} + +void Device::_readDMASetup(uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | READ FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | NAND %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->beginAt, + tick, tick - pContext->beginAt); + + Completion resp; + + resp.fis.dmaSetup.type = FIS_TYPE_DMA_SETUP; + resp.fis.dmaSetup.flag = 0x20; // DMA from Device to Host + resp.fis.dmaSetup.reserved2[0] = pContext->tag; + resp.fis.dmaSetup.transferCount = + pContext->nlb * lbaSize; // TODO: Unit correct? + pContext->tick = tick; + + pParent->submitFIS(resp); + + // Begin DMA + CPUContext *pCPU = new CPUContext(readDMADone, pContext, CPU::SATA__DEVICE, + CPU::READ_DMA_SETUP); + + prdtWrite(pContext->prdt, pContext->prdtLength, pContext->nlb * lbaSize, + pContext->buffer, cpuHandler, pCPU); +} + +void Device::_readDMADone(uint64_t tick, void *context) { + NCQContext *pContext = (NCQContext *)context; + + debugprint(LOG_HIL_SATA, + "NVM | READ FPDMA QUEUED | Tag %d | %" PRIu64 + " + %d | DMA %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + pContext->tag, pContext->slba, pContext->nlb, pContext->beginAt, + tick, tick - pContext->beginAt); + + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (NCQContext *)context; + + Completion resp; + + resp.fis.sdb.type = FIS_TYPE_DEV_BITS; + resp.fis.sdb.flag = 0x40; + resp.fis.sdb.payload = (1 << pContext->tag); + + pParent->submitFIS(resp); + pContext->release(); + }; + + execute(CPU::SATA__DEVICE, CPU::READ_DMA_DONE, doSubmit, pContext); +} + +void Device::identifyDevice(CommandContext *cmd) { + static uint16_t data[256]; + uint64_t sectors = totalLogicalPages / lbaSize * logicalPageSize; + + debugprint(LOG_HIL_SATA, "ATA | IDENTIFY DEVICE"); + + // Fill IDENTIFY DEVICE structure based on ACS-2 + { + memset(data, 0, 512); + + // General configuration + data[ATA_ID_CONFIG] = 0x0000; + data[0x02] = 0xC837; + + strcpy((char *)(data + ATA_ID_SERNO), "00000000000000000000"); + strcpy((char *)(data + ATA_ID_FW_REV), "02.01.00"); + strcpy((char *)(data + ATA_ID_PROD), "SimpleSSD SATA Device by CAMELab"); + + for (int i = 10; i < 47; i++) { + data[i] = bswap16(data[i]); + } + + data[ATA_ID_MAX_MULTSECT] = 0x8000; + data[ATA_ID_CAPABILITY] = 0x0F00; + data[ATA_ID_FIELD_VALID] = 0x0006; + data[ATA_ID_MWDMA_MODES] = 0x0007; + data[ATA_ID_PIO_MODES] = 0x0003; + data[ATA_ID_EIDE_DMA_MIN] = 120; + data[ATA_ID_EIDE_DMA_TIME] = 120; + data[ATA_ID_EIDE_PIO] = 120; + data[ATA_ID_EIDE_PIO_IORDY] = 120; + data[ATA_ID_QUEUE_DEPTH] = 0x001F; + data[ATA_ID_SATA_CAPABILITY] = 0x010E; // Support 1.5/3/6Gbps + NCQ + data[ATA_ID_SATA_CAPABILITY_2] = 0x0006; // TODO: Set speed + data[ATA_ID_FEATURE_SUPP] = 0x0000; + data[ATA_ID_FEATURE_SUPP + 1] = 0x0000; + data[ATA_ID_MAJOR_VER] = 0x0300; // ACS-2 + ATA8-ACS + data[ATA_ID_COMMAND_SET_1] = 0x0020; + data[ATA_ID_COMMAND_SET_2] = 0x7400; // FLUSH CACHE [EXT] and 48bit + data[ATA_ID_CFSSE] = 0x4000; + + if (conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE)) { + data[ATA_ID_CFS_ENABLE_1] = 0x0020; + } + else { + data[ATA_ID_CFS_ENABLE_1] = 0x0000; + } + + data[ATA_ID_CFS_ENABLE_2] = 0x2400; + data[ATA_ID_CSF_DEFAULT] = 0x4000; + data[ATA_ID_UDMA_MODES] = 0x003F; + + if (sectors < 0x0FFFFFFF) { + *(uint32_t *)(data + ATA_ID_LBA_CAPACITY) = sectors; + } + else { + *(uint32_t *)(data + ATA_ID_LBA_CAPACITY) = 0x0FFFFFFF; + } + *(uint64_t *)(data + ATA_ID_LBA_CAPACITY_2) = sectors; + + if (logicalPageSize > lbaSize) { + data[ATA_ID_SECTOR_SIZE] |= 0x6000; + } + if (lbaSize > 512) { + data[ATA_ID_SECTOR_SIZE] |= 0x5000; + } + if (lbaSize != logicalPageSize) { + data[ATA_ID_SECTOR_SIZE] |= + ((uint8_t)log2(logicalPageSize / lbaSize)) & 0x0F; + } + + *(uint32_t *)(data + ATA_ID_LOGICAL_SECTOR_SIZE) = lbaSize / 2; + data[ATA_ID_DATA_SET_MGMT] = 0x0001; + + data[0xDE] = 0x1020; // Transport major version: SATA Rev 3.0 + } + + DMAFunction doWrite = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.maskIS |= PORT_IRQ_SG_DONE; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->release(); + }; + + prdtWrite(cmd->prdt, cmd->prdtLength, 512, (uint8_t *)data, doWrite, cmd); +} + +void Device::setMode(CommandContext *cmd) { + uint8_t fid = cmd->request.regH2D.featureL; + uint8_t id = cmd->request.regH2D.countL; + + switch (fid) { + case FEATURE_SET_XFER_MODE: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | Set Transfer Mode"); + + switch (id & 0xF8) { + case 0: + if (id & 0x01) { + debugprint(LOG_HIL_SATA, + "ATA | SET MODE | PIO default mode, disable IORDY"); + } + else { + debugprint(LOG_HIL_SATA, "ATA | SET MODE | PIO default mode"); + } + + break; + case 1: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | PIO%d", id & 0x07); + break; + case 4: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | MWDMA%d", id & 0x07); + break; + case 8: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | UDMA%d", id & 0x07); + break; + } + + break; + default: + debugprint(LOG_HIL_SATA, "ATA | SET MODE | Not supported feature"); + break; + } + + Completion resp; + + resp.slotIndex = cmd->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + cmd->release(); +} + +void Device::readVerify(CommandContext *cmd) { + Request reqInternal; + uint64_t slba; + uint32_t nlb; + + if (cmd->request.regH2D.command == OPCODE_READ_VERIFY_SECTOR) { + debugprint(LOG_HIL_SATA, "ATA | READ VERIFY"); + + slba = MAKE_LBA(cmd->request); + nlb = makeCount(cmd->request); + } + else { + debugprint(LOG_HIL_SATA, "ATA | READ VERIFY EXT"); + + slba = MAKE_LBA_EXT(cmd->request); + nlb = makeCountExt(cmd->request); + } + + convertUnit(slba, nlb, reqInternal); + + // Check range + Completion resp; + + resp.slotIndex = cmd->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + if (reqInternal.range.nlp >= totalLogicalPages) { + resp.fis.regD2H.status = ATA_ERR; + resp.fis.regD2H.error = ATA_ABORTED; + } + + pParent->submitFIS(resp); + cmd->release(); +} + +void Device::readDMA(CommandContext *cmd, bool isPIO) { + uint64_t slba; + uint32_t nlb; + + if (cmd->request.regH2D.command == OPCODE_READ_SECTOR || + cmd->request.regH2D.command == OPCODE_READ_DMA) { + slba = MAKE_LBA(cmd->request); + nlb = makeCount(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "READ SECTOR" : "READ DMA", slba, nlb); + } + else { + slba = MAKE_LBA_EXT(cmd->request); + nlb = makeCountExt(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "READ SECTOR EXT" : "READ DMA EXT", slba, nlb); + } + + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | READ | %" PRIu64 " + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + Completion resp; + + resp.slotIndex = pContext->cmd->slotIndex; + resp.maskIS |= PORT_IRQ_SG_DONE; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + + pContext->cmd->release(); + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | READ | %" PRIu64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + prdtWrite(pContext->cmd->prdt, pContext->cmd->prdtLength, + pContext->nlb * lbaSize, pContext->buffer, doWrite, context); + }; + + IOContext *pContext = new IOContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->buffer = (uint8_t *)calloc(nlb, lbaSize); + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::SATA__DEVICE, CPU::READ_DMA); + + read(slba, nlb, pContext->buffer, cpuHandler, pCPU); +} + +void Device::readNCQ(CommandContext *cmd) { + uint64_t slba = MAKE_LBA_EXT(cmd->request); + uint32_t nlb = (cmd->request.regH2D.featureL | + ((uint32_t)cmd->request.regH2D.featureH << 8)); + uint8_t tag = (cmd->request.regH2D.countL >> 3) & 0x1F; + + if (nlb == 0) { + nlb = 0x10000; + } + + debugprint(LOG_HIL_SATA, + "ATA | READ FPDMA QUEUED | Tag %d | %" PRIu64 " + %d", tag, + slba, nlb); + + // Schedule read + NCQContext *pContext = new NCQContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->tag = tag; + pContext->buffer = (uint8_t *)calloc(pContext->nlb, lbaSize); + + read(slba, nlb, pContext->buffer, readDMASetup, pContext); + + // Send read scheduled + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->release(); + }; + + execute(CPU::SATA__DEVICE, CPU::READ_NCQ, doSubmit, cmd); +} + +void Device::writeDMA(CommandContext *cmd, bool isPIO) { + uint64_t slba; + uint32_t nlb; + + if (cmd->request.regH2D.command == OPCODE_WRITE_SECTOR || + cmd->request.regH2D.command == OPCODE_WRITE_DMA) { + slba = MAKE_LBA(cmd->request); + nlb = makeCount(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "WRITE SECTOR" : "WRITE DMA", slba, nlb); + } + else { + slba = MAKE_LBA_EXT(cmd->request); + nlb = makeCountExt(cmd->request); + + debugprint(LOG_HIL_SATA, "ATA | %s | %" PRIu64 " + %d", + isPIO ? "WRITE SECTOR EXT" : "WRITE DMA EXT", slba, nlb); + } + + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [this](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | WRITE | %" PRIu64 " + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + Completion resp; + + resp.slotIndex = pContext->cmd->slotIndex; + resp.maskIS |= PORT_IRQ_SG_DONE; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + + pContext->cmd->release(); + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_SATA, + "ATA | WRITE | %" PRIu64 " + %d | DMA %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + write(pContext->slba, pContext->nlb, pContext->buffer, doWrite, context); + }; + + IOContext *pContext = new IOContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->buffer = (uint8_t *)calloc(nlb, lbaSize); + + CPUContext *pCPU = + new CPUContext(doRead, pContext, CPU::SATA__DEVICE, CPU::WRITE_DMA); + + prdtRead(pContext->cmd->prdt, pContext->cmd->prdtLength, nlb * lbaSize, + pContext->buffer, cpuHandler, pCPU); +} + +void Device::writeNCQ(CommandContext *cmd) { + struct Wrapper { + CommandContext *cmd; + NCQContext *ncq; + }; + + uint64_t slba = MAKE_LBA_EXT(cmd->request); + uint32_t nlb = (cmd->request.regH2D.featureL | + ((uint32_t)cmd->request.regH2D.featureH << 8)); + uint8_t tag = (cmd->request.regH2D.countL >> 3) & 0x1F; + + if (nlb == 0) { + nlb = 0x10000; + } + + debugprint(LOG_HIL_SATA, + "ATA | WRITE FPDMA QUEUED | Tag %d | %" PRIu64 " + %d", tag, + slba, nlb); + + // Schedule write + NCQContext *pContext = new NCQContext(cmd); + + pContext->slba = slba; + pContext->nlb = nlb; + pContext->tag = tag; + + // Send write scheduled + DMAFunction doSubmit = [this](uint64_t, void *context) { + auto pContext = (Wrapper *)context; + + Completion resp(writeDMASetup, pContext->ncq); + + resp.slotIndex = pContext->cmd->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->cmd->release(); + + delete pContext; + }; + + Wrapper *wrapper = new Wrapper(); + wrapper->cmd = cmd; + wrapper->ncq = pContext; + + execute(CPU::SATA__DEVICE, CPU::WRITE_NCQ, doSubmit, wrapper); +} + +void Device::flushCache(CommandContext *cmd) { + if (cmd->request.regH2D.command == OPCODE_READ_VERIFY_SECTOR) { + debugprint(LOG_HIL_SATA, "ATA | FLUSH CACHE"); + } + else { + debugprint(LOG_HIL_SATA, "ATA | FLUSH CACHE EXT"); + } + + DMAFunction doFlush = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; + + pParent->submitFIS(resp); + pContext->release(); + }; + + flush(doFlush, cmd); +} + +void Device::submitCommand(RequestContext *req) { + DMAFunction doRequest = [this](uint64_t, void *context) { + auto pContext = (CommandContext *)context; + + bool processed = true; + + // Just use Register H2D because we are printing header only + debugprint(LOG_HIL_SATA, "QUEUE | FIS Type %02Xh | Command %02Xh", + pContext->request.regH2D.type, pContext->request.regH2D.command); + + switch (pContext->request.regH2D.command) { + case OPCODE_FLUSH_CACHE: + case OPCODE_FLUSH_CACHE_EXT: + flushCache(pContext); + break; + case OPCODE_IDENTIFY_DEVICE: + identifyDevice(pContext); + break; + case OPCODE_READ_DMA: + case OPCODE_READ_DMA_EXT: + readDMA(pContext); + break; + case OPCODE_READ_FPDMA_QUEUED: + readNCQ(pContext); + break; + case OPCODE_READ_SECTOR: + case OPCODE_READ_SECTOR_EXT: + readDMA(pContext, true); + break; + case OPCODE_READ_VERIFY_SECTOR: + case OPCODE_READ_VERIFY_SECTOR_EXT: + readVerify(pContext); + break; + case OPCODE_SET_FEATURE: + setMode(pContext); + break; + case OPCODE_WRITE_DMA: + case OPCODE_WRITE_DMA_EXT: + writeDMA(pContext); + break; + case OPCODE_WRITE_FPDMA_QUEUED: + writeNCQ(pContext); + break; + case OPCODE_WRITE_SECTOR: + case OPCODE_WRITE_SECTOR_EXT: + writeDMA(pContext, true); + break; + default: + processed = false; + break; + } + + if (!processed) { + Completion resp; + + resp.slotIndex = pContext->slotIndex; + resp.fis.regD2H.type = FIS_TYPE_REG_D2H; // Type + resp.fis.regD2H.status = 0x01; // Status (Error) + resp.fis.regD2H.error = 0x04; // Error (Abort) + + pParent->submitFIS(resp); + pContext->release(); + } + }; + + CommandContext *pContext = new CommandContext(); + + pContext->slotIndex = req->idx; + + // Read Command Table from Command List + DMAFunction doReqRead = [doRequest](uint64_t now, void *context) { + auto pContext = (CommandContext *)context; + + pContext->reqDone = true; + + if (pContext->prdtDone) { + doRequest(now, context); + } + }; + + pDMA->dmaRead(req->header.commandTableBaseAddress, 64, pContext->request.data, + doReqRead, pContext); + + // We have PRDT + if (req->header.prdtLength > 0) { + DMAFunction doPRDTRead = [doRequest](uint64_t now, void *context) { + auto pContext = (CommandContext *)context; + + pContext->prdtDone = true; + + if (pContext->reqDone) { + doRequest(now, context); + } + }; + + pContext->prdtLength = req->header.prdtLength; + pContext->prdt = (uint8_t *)calloc(req->header.prdtLength, sizeof(PRDT)); + + pDMA->dmaRead(req->header.commandTableBaseAddress + 0x80, + pContext->prdtLength * sizeof(PRDT), pContext->prdt, + doPRDTRead, pContext); + } + else { + pContext->prdtDone = true; + } +} + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/device.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/device.hh new file mode 100644 index 0000000000..0d92b344ae --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/device.hh @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_DEVICE__ +#define __HIL_SATA_DEVICE__ + +#include "hil/hil.hh" +#include "hil/sata/def.hh" +#include "hil/sata/hba.hh" +#include "util/disk.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +struct CommandContext { + FIS request; + uint8_t *prdt; + uint16_t prdtLength; + + uint32_t slotIndex; + bool reqDone; + bool prdtDone; + + CommandContext() + : prdt(nullptr), + prdtLength(0), + slotIndex(0), + reqDone(false), + prdtDone(false) {} + + void release() { + if (prdtLength > 0) { + free(prdt); + } + + delete this; + } +}; + +struct IOContext { + uint64_t beginAt; + uint64_t tick; + uint64_t slba; + uint64_t nlb; + uint8_t *buffer; + + CommandContext *cmd; + + IOContext(CommandContext *c) + : beginAt(getTick()), tick(0), slba(0), nlb(0), buffer(nullptr), cmd(c) {} +}; + +struct NCQContext : public IOContext { + uint8_t tag; + + // Copy of PRDT + uint8_t *prdt; + uint16_t prdtLength; + + NCQContext(CommandContext *c) : IOContext(c), tag(0) { + prdt = c->prdt; + prdtLength = c->prdtLength; + + // Prevent prdt being freed + c->prdtLength = 0; + } + + void release() { + if (prdtLength > 0) { + free(prdt); + } + + delete this; + } +}; + +class Device : public StatObject { + private: + HBA *pParent; + DMAInterface *pDMA; + HIL *pHIL; + Disk *pDisk; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + uint32_t lbaSize; + + ConfigReader &conf; + + // Handlers + DMAFunction dmaHandler; + + // PRDT + void prdtRead(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void *); + void prdtWrite(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void *); + + // SimpleSSD + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void flush(DMAFunction &, void *); + void convertUnit(uint64_t, uint64_t, SimpleSSD::HIL::Request &); + + // FPDMA + DMAFunction writeDMASetup; + void _writeDMASetup(uint64_t, void *); + DMAFunction writeDMADone; + void _writeDMADone(uint64_t, void *); + DMAFunction readDMASetup; + void _readDMASetup(uint64_t, void *); + DMAFunction readDMADone; + void _readDMADone(uint64_t, void *); + + // SATA / ATA8-ACS commands + void identifyDevice(CommandContext *); + void setMode(CommandContext *); + void readVerify(CommandContext *); + void readDMA(CommandContext *, bool = false); + void readNCQ(CommandContext *); + void writeDMA(CommandContext *, bool = false); + void writeNCQ(CommandContext *); + void flushCache(CommandContext *); + + public: + Device(HBA *, DMAInterface *, ConfigReader &); + ~Device(); + + // For AHCI + void init(); + void submitCommand(RequestContext *); +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/hba.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/hba.cc new file mode 100644 index 0000000000..a55e1af433 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/hba.cc @@ -0,0 +1,532 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/sata/hba.hh" + +#include "hil/sata/device.hh" +#include "util/fifo.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +Completion::Completion() + : slotIndex(0), maskIS(0), func([](uint64_t, void *) {}), context(nullptr) { + memset(fis.data, 0, 64); +} + +Completion::Completion(DMAFunction &f, void *c) + : slotIndex(0), maskIS(0), func(f), context(c) { + memset(fis.data, 0, 64); +} + +HBA::HBA(Interface *i, ConfigReader &c) : pInterface(i), conf(c) { + ARM::AXI::BUS_WIDTH hostBusWidth; + SimpleSSD::SATA::SATA_GEN sataMode; + uint64_t hostBusClock; + + // Get AXI setting + hostBusWidth = + (ARM::AXI::BUS_WIDTH)conf.readInt(CONFIG_SATA, SATA_AXI_BUS_WIDTH); + hostBusClock = conf.readUint(CONFIG_SATA, SATA_AXI_CLOCK); + sataMode = (SimpleSSD::SATA::SATA_GEN)conf.readInt(CONFIG_SATA, SATA_MODE); + + memset(ghc.data, 0, 0x100); + memset(port.data, 0, 0x80); + + ghc.capability = 0xC0341F00; // NCQ with 32 entry, one port + ghc.globalHBAControl = 0x80000000; + ghc.portsImplemented = 0x00000001; // Bit 0 (Port 0) + ghc.AHCIVersion = 0x00010301; // AHCI version 1.3.1 + ghc.commandCompletionCoalescingControl = 0x00010100; + ghc.enclosureManagementLocation = 0x00280020; // 0xA0 + 0x20 + ghc.enclosureManagementControl = 0x03000000; + ghc.HBACapabilityExtended = 0x00000020; // BOHC not implemented + + port.commandAndStatus = 0x00000006; + port.taskFileData = 0x0000007F; + port.signature = 0xFFFFFFFF; + + workEvent = allocate([this](uint64_t) { work(); }); + requestEvent = allocate([this](uint64_t) { handleRequest(); }); + + maxRequest = conf.readUint(CONFIG_SATA, SATA_MAX_REQUEST_COUNT); + workInterval = conf.readUint(CONFIG_SATA, SATA_WORK_INTERVAL); + requestInterval = workInterval / maxRequest; + requestCounter = 0; + + submitFISPending = false; + + // FIFO + FIFOParam fifoParam; + + fifoParam.rqSize = 8192; + fifoParam.wqSize = 8192; + fifoParam.transferUnit = 2048; + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + pHostDMA = new FIFO(pInterface, fifoParam); + + fifoParam.latency = [sataMode](uint64_t size) -> uint64_t { + return SimpleSSD::SATA::calculateDelay(sataMode, size); + }; + + pPHY = new FIFO(pHostDMA, fifoParam); + + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + pDeviceDMA = new FIFO(pPHY, fifoParam); + + pDevice = new Device(this, pDeviceDMA, conf); +} + +HBA::~HBA() { + delete pDevice; + delete pDeviceDMA; + delete pPHY; + delete pHostDMA; +} + +void HBA::init() { + ghc.globalHBAControl = HOST_AHCI_EN; + ghc.interruptStatus = 0x00000000; + + // Reset is done + ghc.globalHBAControl &= ~HOST_RESET; + + // Port + deviceInited = false; +} + +void HBA::readAHCIRegister(uint32_t offset, uint32_t size, uint8_t *buffer) { + uint64_t temp = 0; + + for (uint32_t i = 0; i < size; i++) { + if (offset + i < 0x100) { + buffer[i] = ghc.data[offset + i]; + } + else if (offset + i < 0x180) { + buffer[i] = port.data[offset + i - 0x100]; + } + } + + if (size <= 8) { + memcpy(&temp, buffer, size); + } + else { + panic("Invalid register access size"); + } + + // debugprint(LOG_HIL_SATA, "REG | READ | %02Xh + %d | %08" PRIX64, + // offset, size, temp); +} + +void HBA::writeAHCIRegister(uint32_t offset, uint32_t size, uint8_t *buffer) { + uint32_t temp = 0; + + if (size <= 8) { + memcpy(&temp, buffer, 4); + } + else { + panic("Invalid register access size"); + } + + // debugprint(LOG_HIL_SATA, "REG | WRITE | %02Xh + %d | %08X", offset, + // size, temp); + + // Access to AHCI Generic Host Control Register + if (offset < 0x100) { + switch (offset) { + case REG_GHC: + ghc.globalHBAControl &= 0xFFFFFFFC; + ghc.globalHBAControl |= temp & 0x00000003; + + if (ghc.globalHBAControl & HOST_RESET) { + // HBA Reset + init(); + } + + break; + case REG_IS: + ghc.interruptStatus &= ~temp; + + break; + case REG_CCC_CTL: + ghc.commandCompletionCoalescingControl &= 0x000000FE; + ghc.commandCompletionCoalescingControl |= temp & 0xFFFFFF01; + + break; + case REG_CCC_PORTS: + ghc.commandCompletionCoalescingPorts = temp; + + break; + case REG_EM_CTL: + ghc.enclosureManagementControl &= 0xFFFFFCFE | ((~temp) & 0x00000001); + ghc.enclosureManagementControl |= temp & 0x00000300; + + if (ghc.enclosureManagementControl & EM_CTL_RST) { + // Reset EM message logic + ghc.enclosureManagementControl &= ~EM_CTL_RST; + } + + if (ghc.enclosureManagementControl & EM_CTL_TM) { + // Transmit message + ghc.enclosureManagementControl &= ~EM_CTL_TM; + } + + break; + case REG_BOHC: + ghc.handoffControlAndStatus &= 0xFFFFFFE0 | ((~temp) & 0x00000008); + ghc.handoffControlAndStatus |= temp & 0x00000017; + + break; + } + } + // Access to Port 0 Register + else if (offset < 0x180) { + offset -= 0x100; + + switch (offset) { + case REG_P0CLB: + port.commandListBaseAddress &= 0xFFFFFFFF00000000; + port.commandListBaseAddress |= temp & 0xFFFFFC00; + + break; + case REG_P0CLBU: + port.commandListBaseAddress &= 0xFFFFFFFF; + port.commandListBaseAddress |= (uint64_t)temp << 32; + + break; + case REG_P0FB: + port.FISBaseAddress &= 0xFFFFFFFF00000000; + port.FISBaseAddress |= temp & 0xFFFFFF00; + + break; + case REG_P0FBU: + port.FISBaseAddress &= 0xFFFFFFFF; + port.FISBaseAddress |= (uint64_t)temp << 32; + + break; + case REG_P0IS: + port.interruptStatus &= (~temp) & 0x037FFF50; + + interruptCleared(); + + break; + case REG_P0IE: + port.interruptEnable &= 0x823FFF80; + port.interruptEnable |= temp & 0x7DC0007F; + + updateInterrupt(); + + break; + case REG_P0CMD: + port.commandAndStatus &= 0x0CFFFFE6 | ((~temp) & 0x00000008); + port.commandAndStatus |= temp & 0xF3000011; + + if (port.commandAndStatus & PORT_CMD_START) { + if (!scheduled(workEvent) && !scheduled(requestEvent)) { + // Enable controller + schedule(workEvent, getTick() + workInterval); + + port.commandAndStatus |= PORT_CMD_LIST_ON; + } + } + else { + // Disable controller + deschedule(workEvent); + + port.commandAndStatus &= ~PORT_CMD_LIST_ON; + } + + // Set FR + if (port.commandAndStatus & PORT_CMD_FIS_RX) { + port.commandAndStatus |= PORT_CMD_FIS_ON; + } + else { + port.commandAndStatus &= ~PORT_CMD_FIS_ON; + } + + break; + case REG_P0SCTL: + port.control &= 0xFFFFF000; + port.control |= temp & 0x00000FFF; + + if ((port.control & 0x0F) == 0x01 && !deviceInited) { + deviceInited = true; + + pDevice->init(); + } + + break; + case REG_P0SERR: + port.error &= ~temp; + + break; + case REG_P0SACT: + port.active |= temp; + + break; + case REG_P0CI: { + uint32_t old = port.commandIssue; + port.commandIssue |= temp; + + processCommand(old ^ port.commandIssue); + + } break; + case REG_P0SNTF: + port.notification &= 0xFFFF0000 | ((~temp) & 0x0000FFFF); + + break; + case REG_P0FBS: + port.switchingControl &= 0xFFFFF0FC | ((~temp) & 0x00000002); + port.switchingControl |= temp & 0x00000F03; + + break; + default: + warn("Write to read only register 0x%X", offset); + + break; + } + } + + if (size > 4) { + writeAHCIRegister(offset + 4, size - 4, buffer + 4); + } +} + +void HBA::updateInterrupt() { + if (ghc.globalHBAControl & HOST_IRQ_EN) { + if ((ghc.interruptStatus & 0x01) && + (port.interruptStatus & port.interruptEnable)) { + pInterface->updateInterrupt(true); + } + } +} + +void HBA::processCommand(uint32_t ci) { + uint32_t bit = 0; + + for (int i = 0; i < 32; i++) { + bit = 1 << i; + + if (ci & bit) { + lRequestQueue.push(i); + } + } +} + +void HBA::work() { + lastWorkAt = getTick(); + + handleRequest(); +} + +void HBA::handleRequest() { + uint64_t tick = getTick(); + + if (lRequestQueue.size() > 0) { + auto pContext = new RequestContext(); + + pContext->idx = lRequestQueue.front(); + lRequestQueue.pop(); + + DMAFunction doRead = [this](uint64_t, void *context) { + auto pContext = (RequestContext *)context; + + debugprint(LOG_HIL_SATA, "QUEUE | Entry %d", pContext->idx); + pDevice->submitCommand(pContext); + + delete pContext; + }; + + uint64_t addr = + port.commandListBaseAddress + pContext->idx * sizeof(CommandHeader); + + CPUContext *pCPU = new CPUContext(doRead, pContext, CPU::SATA__DEVICE, + CPU::SUBMIT_COMMAND); + + pHostDMA->dmaRead(addr, sizeof(CommandHeader), pContext->header.data, + cpuHandler, pCPU); + } + + if (lRequestQueue.size() > 0 && requestCounter < maxRequest) { + schedule(requestEvent, tick + requestInterval); + } + else { + schedule(workEvent, MAX(tick + requestInterval, lastWorkAt + workInterval)); + } +} + +void HBA::submitFIS(Completion &resp) { + switch (resp.fis.data[0]) { + case FIS_TYPE_DMA_SETUP: + resp.maskIS |= PORT_IRQ_DMAS_FIS; + break; + case FIS_TYPE_PIO_SETUP: + resp.maskIS |= PORT_IRQ_PIOS_FIS; + break; + case FIS_TYPE_REG_D2H: + resp.maskIS |= PORT_IRQ_D2H_REG_FIS; + break; + case FIS_TYPE_DEV_BITS: + resp.maskIS |= PORT_IRQ_SDB_FIS; + break; + default: + resp.maskIS |= PORT_IRQ_UNK_FIS; + break; + } + + if (resp.fis.data[2] & ATA_ERR) { + resp.maskIS |= PORT_IRQ_TF_ERR; + } + + if (resp.fis.data[0] == FIS_TYPE_DEV_BITS) { + // Reset PxSACT + port.active &= ~resp.fis.sdb.payload; + } + + lResponseQueue.push(resp); + handleResponse(); +} + +void HBA::submitSignal(Completion &resp) { + if (resp.fis.data[0] != FIS_TYPE_REG_D2H) { + panic("Invalid FIS to submitSignal"); + } + + resp.maskIS = PORT_IRQ_TF_ERR | PORT_IRQ_D2H_REG_FIS; + + // Set PxSIG + port.signature = 0x00000101; // SATA drive + + // Set PxSSTS + // TODO: set interface speed + port.status = 0x00000133; + + lResponseQueue.push(resp); + + DMAFunction doCompletion = [this](uint64_t, void *context) { + uint32_t mask = (uint64_t)context; + + // Set interrupt mask + port.interruptStatus |= mask; + ghc.interruptStatus |= 0x01; // Port 0 has interrupt + + pInterface->updateInterrupt(true); + }; + + pHostDMA->dmaWrite(port.FISBaseAddress + 0x40, 0x14, resp.fis.data, + doCompletion, (void *)(uint64_t)resp.maskIS); +} + +void HBA::handleResponse() { + auto &iter = lResponseQueue.front(); + + // There is ongoing response + if (submitFISPending) { + return; + } + + // Write FIS entry + uint64_t base = port.FISBaseAddress; + uint64_t size; + + switch (iter.fis.data[0]) { + case FIS_TYPE_DMA_SETUP: + size = 0x1C; + break; + case FIS_TYPE_PIO_SETUP: + base += 0x20; + size = 0x14; + break; + case FIS_TYPE_REG_D2H: + base += 0x40; + size = 0x14; + break; + case FIS_TYPE_DEV_BITS: + base += 0x58; + size = 0x08; + break; + default: + base += 0x60; + size = 64; + break; + } + + DMAFunction doCompletion = [this](uint64_t, void *context) { + uint32_t mask = (uint64_t)context; + + // Set interrupt mask + port.interruptStatus |= mask; + ghc.interruptStatus |= 0x01; // Port 0 has interrupt + + updateInterrupt(); + }; + + debugprint(LOG_HIL_SATA, "QUEUE | submitting FIS for entry %d", + iter.slotIndex); + + pHostDMA->dmaWrite(base, size, iter.fis.data, doCompletion, + (void *)(uint64_t)iter.maskIS); +} + +void HBA::interruptCleared() { + if (lResponseQueue.size() > 0) { + auto &iter = lResponseQueue.front(); + + // Interrupt cleared + if (!(port.interruptStatus & iter.maskIS)) { + debugprint(LOG_HIL_SATA, "QUEUE | FIS completed for entry %d", + iter.slotIndex); + + pInterface->updateInterrupt(false); + + // Copy function + auto func = iter.func; + auto context = iter.context; + + // Clear PxCI + port.commandIssue &= ~((uint32_t)1 << iter.slotIndex); + + // Pop + submitFISPending = false; + lResponseQueue.pop(); + + if (lResponseQueue.size() > 0) { + handleResponse(); + } + + func(getTick(), context); + } + } +} + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/hba.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/hba.hh new file mode 100644 index 0000000000..cadc243606 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/hba.hh @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_SATA_HBA__ +#define __HIL_SATA_HBA__ + +#include + +#include "hil/sata/def.hh" +#include "hil/sata/interface.hh" +#include "sim/config_reader.hh" +#include "sim/simulator.hh" +#include "sim/statistics.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +class Device; + +class Completion { + public: + uint32_t slotIndex; // PxCI bit index + uint32_t maskIS; // PxIS bit mask + + // Received FIS + FIS fis; + + // Function handler when completion is done + // This only for NCQ operations (READ/WRITE FPDMA QUEUED) + DMAFunction func; + void *context; + + Completion(); + Completion(DMAFunction &, void *); +}; + +struct RequestContext { + uint32_t idx; + CommandHeader header; +}; + +typedef std::function RequestFunction; + +class HBA : public StatObject { + private: + Interface *pInterface; + Device *pDevice; + ConfigReader &conf; + + DMAInterface *pHostDMA; + DMAInterface *pPHY; + DMAInterface *pDeviceDMA; + + AHCIGHCRegister ghc; + AHCIPortRegister port; + + // Request handling + Event workEvent; + Event requestEvent; + uint64_t workInterval; + uint64_t requestInterval; + uint64_t maxRequest; + uint64_t requestCounter; + uint64_t lastWorkAt; + + bool submitFISPending; + std::queue lRequestQueue; + std::queue lResponseQueue; + + // Port state + bool deviceInited; + + void init(); + void updateInterrupt(); + + void processCommand(uint32_t); + void work(); + void handleRequest(); + void handleResponse(); + void interruptCleared(); + + public: + HBA(Interface *, ConfigReader &); + ~HBA(); + + // For Device + void submitFIS(Completion &); + void submitSignal(Completion &); + + // For Interface + void readAHCIRegister(uint32_t, uint32_t, uint8_t *); + void writeAHCIRegister(uint32_t, uint32_t, uint8_t *); +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/sata/interface.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/interface.hh new file mode 100644 index 0000000000..7f3ef1d9f4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/sata/interface.hh @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __HIL_SATA_INTERFACE__ +#define __HIL_SATA_INTERFACE__ + +#include + +#include "sim/dma_interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace SATA { + +class HBA; + +class Interface : public SimpleSSD::DMAInterface { + protected: + HBA *pController; + + public: + virtual void updateInterrupt(bool) = 0; +}; + +} // namespace SATA + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/config.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/config.cc new file mode 100644 index 0000000000..c5f5077d65 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/config.cc @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/ufs/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +const char NAME_WORK_INTERVAL[] = "WorkInterval"; +const char NAME_MAX_REQUEST_COUNT[] = "MaxRequestCount"; +const char NAME_LBA_SIZE[] = "LBASize"; +const char NAME_ENABLE_DISK_IMAGE[] = "EnableDiskImage"; +const char NAME_STRICT_DISK_SIZE[] = "StrictSizeCheck"; +const char NAME_DISK_IMAGE_PATH[] = "DiskImageFile"; +const char NAME_USE_COW_DISK[] = "UseCopyOnWriteDisk"; +const char NAME_HOST_AXI_BUS_WIDTH[] = "AXIBusWidth"; +const char NAME_HOST_AXI_CLOCK[] = "AXIClock"; +const char NAME_MPHY_MODE[] = "MPHYMode"; +const char NAME_MPHY_LANE[] = "MPHYLane"; + +Config::Config() { + workInterval = 50000; + maxRequestCount = 4; + lbaSize = 512; + enableDiskImage = false; + strictDiskSize = false; + diskImagePath = ""; + useCopyOnWriteDisk = false; + axiWidth = ARM::AXI::BUS_64BIT; + axiClock = 300000000; + mphyMode = MIPI::M_PHY::HS_G3; + mphyLane = 2; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_WORK_INTERVAL)) { + workInterval = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MAX_REQUEST_COUNT)) { + maxRequestCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_LBA_SIZE)) { + lbaSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_ENABLE_DISK_IMAGE)) { + enableDiskImage = convertBool(value); + } + else if (MATCH_NAME(NAME_STRICT_DISK_SIZE)) { + strictDiskSize = convertBool(value); + } + else if (MATCH_NAME(NAME_DISK_IMAGE_PATH)) { + diskImagePath = value; + } + else if (MATCH_NAME(NAME_USE_COW_DISK)) { + useCopyOnWriteDisk = convertBool(value); + } + else if (MATCH_NAME(NAME_HOST_AXI_BUS_WIDTH)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + axiWidth = ARM::AXI::BUS_32BIT; + break; + case 1: + axiWidth = ARM::AXI::BUS_64BIT; + break; + case 2: + axiWidth = ARM::AXI::BUS_128BIT; + break; + case 3: + axiWidth = ARM::AXI::BUS_256BIT; + break; + case 4: + axiWidth = ARM::AXI::BUS_512BIT; + break; + case 5: + axiWidth = ARM::AXI::BUS_1024BIT; + break; + default: + panic("Invalid AXI Stream Bus Width"); + break; + } + } + else if (MATCH_NAME(NAME_HOST_AXI_CLOCK)) { + axiClock = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_MPHY_MODE)) { + switch (strtoul(value, nullptr, 10)) { + case 0: + mphyMode = MIPI::M_PHY::HS_G1; + break; + case 1: + mphyMode = MIPI::M_PHY::HS_G2; + break; + case 2: + mphyMode = MIPI::M_PHY::HS_G3; + break; + case 3: + mphyMode = MIPI::M_PHY::HS_G4; + break; + default: + panic("Invalid M-PHY Mode"); + break; + } + } + else if (MATCH_NAME(NAME_MPHY_LANE)) { + mphyLane = (uint8_t)strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (popcount(lbaSize) != 1 || lbaSize < 512) { + panic("Invalid LBA size"); + } + if (maxRequestCount == 0) { + panic("MaxRequestCount should be larger then 0"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case UFS_HOST_AXI_BUS_WIDTH: + ret = axiWidth; + break; + case UFS_MPHY_MODE: + ret = mphyMode; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case UFS_WORK_INTERVAL: + ret = workInterval; + break; + case UFS_MAX_REQUEST_COUNT: + ret = maxRequestCount; + break; + case UFS_LBA_SIZE: + ret = lbaSize; + break; + case UFS_HOST_AXI_CLOCK: + ret = axiClock; + break; + case UFS_MPHY_LANE: + ret = mphyLane; + break; + } + + return ret; +} + +std::string Config::readString(uint32_t idx) { + std::string ret(""); + + switch (idx) { + case UFS_DISK_IMAGE_PATH: + ret = diskImagePath; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case UFS_ENABLE_DISK_IMAGE: + ret = enableDiskImage; + break; + case UFS_STRICT_DISK_SIZE: + ret = strictDiskSize; + break; + case UFS_USE_COW_DISK: + ret = useCopyOnWriteDisk; + break; + } + + return ret; +} + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/config.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/config.hh new file mode 100644 index 0000000000..460af3bc10 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/config.hh @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_CONFIG__ +#define __HIL_UFS_CONFIG__ + +#include "sim/base_config.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +typedef enum { + UFS_WORK_INTERVAL, + UFS_MAX_REQUEST_COUNT, + UFS_LBA_SIZE, + UFS_ENABLE_DISK_IMAGE, + UFS_STRICT_DISK_SIZE, + UFS_DISK_IMAGE_PATH, + UFS_USE_COW_DISK, + UFS_HOST_AXI_BUS_WIDTH, + UFS_HOST_AXI_CLOCK, + UFS_MPHY_MODE, + UFS_MPHY_LANE, +} UFS_CONFIG; + +class Config : public BaseConfig { + private: + ARM::AXI::BUS_WIDTH axiWidth; //!< Default: BUS_64BIT + uint64_t axiClock; //!< Default: 300MHz + uint64_t workInterval; //!< Default: 50000 (50ns) + uint64_t maxRequestCount; //!< Default: 4 + uint64_t lbaSize; //!< Default: 512 + bool enableDiskImage; //!< Default: False + bool strictDiskSize; //!< Default: False + bool useCopyOnWriteDisk; //!< Default: False + std::string diskImagePath; //!< Default: "" + MIPI::M_PHY::M_PHY_MODE mphyMode; //!< Default: HS_G3 + uint8_t mphyLane; //!< Default: 2 + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + std::string readString(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/def.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/def.cc new file mode 100644 index 0000000000..a2703be7d0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/def.cc @@ -0,0 +1,580 @@ +/* + * UFS Definitions + * + * Author: Donghyun Gouk + */ + +#include "hil/ufs/def.hh" + +#ifdef _MSC_VER +#define htobe16(x) ((x) >> 8 | ((x)&0xFF) << 8) +#define htobe32(x) (htobe16((x) >> 16) & 0xFFFF | htobe16((x)&0xFFFF) << 16) +#define be16toh(x) htobe16(x) +#define be32toh(x) htobe32(x) + +#elif defined(__APPLE__) +#include +#define htobe16(x) OSSwapHostToBigInt16(x) +#define htobe32(x) OSSwapHostToBigInt32(x) +#define be16toh(x) OSSwapBigToHostInt16(x) +#define be32toh(x) OSSwapBigToHostInt32(x) +#else +#include +#endif + +#include +#include + +UFSHCIRegister::UFSHCIRegister() { + memset(data, 0, 0xB0); +} + +UPIU::UPIU() { + header.transactionType = 0; + header.flags = 0; + header.lun = 0; + header.taskTag = 0; + header.commandSetType = 0; + header.function = 0; + header.response = 0; + header.status = 0; + header.ehsLength = 0; + header.deviceInfo = 0; + header.dataSegmentLength = 0; +} + +UPIU::~UPIU() {} + +bool UPIU::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 11) { + header.transactionType = buffer[0]; + header.flags = buffer[1]; + header.lun = buffer[2]; + header.taskTag = buffer[3]; + header.commandSetType = buffer[4]; + header.function = buffer[5]; + header.response = buffer[6]; + header.status = buffer[7]; + header.ehsLength = buffer[8]; + header.deviceInfo = buffer[9]; + header.dataSegmentLength = ((uint16_t)buffer[10] << 8) | buffer[11]; + + ret = true; + } + + return ret; +} + +bool UPIU::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 11) { + buffer[0] = header.transactionType & 0x3F; + buffer[1] = header.flags; + buffer[2] = header.lun; + buffer[3] = header.taskTag; + buffer[4] = header.commandSetType; + buffer[5] = header.function; + buffer[6] = header.response; + buffer[7] = header.status; + buffer[8] = header.ehsLength; + buffer[9] = header.deviceInfo; + buffer[10] = header.dataSegmentLength >> 8; + buffer[11] = header.dataSegmentLength & 0xFF; + + ret = true; + } + + return ret; +} + +uint32_t UPIU::getLength() { + return 12; +} + +UPIUCommand::UPIUCommand() : UPIU(), expectedDataLength(0) { + memset(cdb, 0, 16); +} + +UPIUCommand::~UPIUCommand() {} + +bool UPIUCommand::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_COMMAND && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + expectedDataLength = be32toh(temp); + + memcpy(cdb, buffer + 16, 16); + } + + return ret; +} + +bool UPIUCommand::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_COMMAND; + ret = UPIU::get(buffer, length); + + temp = htobe32(expectedDataLength); + memcpy(buffer + 12, &temp, 4); + + memcpy(buffer + 16, cdb, 16); + } + + return ret; +} + +uint32_t UPIUCommand::getLength() { + return 32; +} + +UPIUResponse::UPIUResponse() : UPIU(), residualCount(0), senseLength(0) { + memset(senseData, 0, 18); +} + +UPIUResponse::~UPIUResponse() {} + +bool UPIUResponse::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_RESPONSE && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + residualCount = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31 + offset + header.dataSegmentLength) { + senseLength = + ((uint16_t)buffer[32 + offset] << 8) | buffer[33 + offset]; + memcpy(senseData, buffer + 34 + offset, senseLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUResponse::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_RESPONSE; + ret = UPIU::get(buffer, length); + + temp = htobe32(residualCount); + memcpy(buffer + 12, &temp, 4); + + memset(buffer + 16, 0, 16); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + buffer[32] = senseLength >> 8; + buffer[33] = senseLength & 0xFF; + memcpy(buffer + 34, senseData, senseLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUResponse::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUQueryReq::UPIUQueryReq() : UPIU(), data(nullptr) {} + +UPIUQueryReq::~UPIUQueryReq() { + if (data) { + free(data); + } +} + +bool UPIUQueryReq::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_QUERY_REQUEST && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + opcode = buffer[12]; + idn = buffer[13]; + index = buffer[14]; + selector = buffer[15]; + this->length = ((uint16_t)buffer[18] << 8) | buffer[19]; + + memcpy(&temp, buffer + 20, 4); + val1 = be32toh(temp); + + memcpy(&temp, buffer + 24, 4); + val2 = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUQueryReq::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_QUERY_REQUEST; + ret = UPIU::get(buffer, length); + + buffer[12] = opcode; + buffer[13] = idn; + buffer[14] = index; + buffer[15] = selector; + buffer[18] = this->length >> 8; + buffer[19] = this->length & 0xFF; + + temp = htobe32(val1); + memcpy(buffer + 20, &temp, 4); + + temp = htobe32(val2); + memcpy(buffer + 24, &temp, 4); + + memset(buffer + 28, 0, 4); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUQueryReq::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUQueryResp::UPIUQueryResp() : UPIU(), data(nullptr) {} + +UPIUQueryResp::~UPIUQueryResp() { + if (data) { + free(data); + } +} + +bool UPIUQueryResp::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_QUERY_RESPONSE && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + opcode = buffer[12]; + idn = buffer[13]; + index = buffer[14]; + selector = buffer[15]; + this->length = ((uint16_t)buffer[18] << 8) | buffer[19]; + + memcpy(&temp, buffer + 20, 4); + val1 = be32toh(temp); + + memcpy(&temp, buffer + 24, 4); + val2 = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUQueryResp::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_QUERY_RESPONSE; + ret = UPIU::get(buffer, length); + + buffer[12] = opcode; + buffer[13] = idn; + buffer[14] = index; + buffer[15] = selector; + buffer[18] = this->length >> 8; + buffer[19] = this->length & 0xFF; + + temp = htobe32(val1); + memcpy(buffer + 20, &temp, 4); + + temp = htobe32(val2); + memcpy(buffer + 24, &temp, 4); + + memset(buffer + 28, 0, 4); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUQueryResp::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUDataOut::UPIUDataOut() : UPIU(), offset(0), count(0), data(nullptr) {} + +UPIUDataOut::~UPIUDataOut() { + if (data) { + free(data); + } +} + +bool UPIUDataOut::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_DATA_OUT && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + offset = be32toh(temp); + + memcpy(&temp, buffer + 16, 4); + count = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUDataOut::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_DATA_OUT; + ret = UPIU::get(buffer, length); + + temp = htobe32(offset); + memcpy(buffer + 12, &temp, 4); + + temp = htobe32(count); + memcpy(buffer + 16, &temp, 4); + + memset(buffer + 20, 0, 12); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUDataOut::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUDataIn::UPIUDataIn() : UPIU(), offset(0), count(0), data(nullptr) {} + +UPIUDataIn::~UPIUDataIn() { + if (data) { + free(data); + } +} + +bool UPIUDataIn::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_DATA_IN && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + offset = be32toh(temp); + + memcpy(&temp, buffer + 16, 4); + count = be32toh(temp); + + if (header.dataSegmentLength > 0) { + uint32_t offset = (header.transactionType & 0x80) ? 4 : 0; + + if (length > 31ul + offset + header.dataSegmentLength) { + if (data) { + free(data); + } + data = (uint8_t *)calloc(header.dataSegmentLength, 1); + memcpy(data, buffer + 32 + offset, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +bool UPIUDataIn::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_DATA_IN; + ret = UPIU::get(buffer, length); + + temp = htobe32(offset); + memcpy(buffer + 12, &temp, 4); + + temp = htobe32(count); + memcpy(buffer + 16, &temp, 4); + + memset(buffer + 20, 0, 12); + + if (header.dataSegmentLength > 0) { + if (length > 31ul + header.dataSegmentLength) { + memcpy(buffer + 32, data, header.dataSegmentLength); + } + else { + ret = false; + } + } + } + + return ret; +} + +uint32_t UPIUDataIn::getLength() { + return 32 + header.dataSegmentLength; +} + +UPIUReadyToTransfer::UPIUReadyToTransfer() : UPIU(), offset(0), count(0) {} + +UPIUReadyToTransfer::~UPIUReadyToTransfer() {} + +bool UPIUReadyToTransfer::set(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if ((buffer[0] & 0x3F) == OPCODE_DATA_IN && length > 31) { + uint32_t temp; + + ret = UPIU::set(buffer, length); + + memcpy(&temp, buffer + 12, 4); + offset = be32toh(temp); + + memcpy(&temp, buffer + 16, 4); + count = be32toh(temp); + } + + return ret; +} + +bool UPIUReadyToTransfer::get(uint8_t *buffer, uint32_t length) { + bool ret = false; + + if (length > 31) { + uint32_t temp; + + header.transactionType = OPCODE_READY_TO_TRANSFER; + ret = UPIU::get(buffer, length); + + temp = htobe32(offset); + memcpy(buffer + 12, &temp, 4); + + temp = htobe32(count); + memcpy(buffer + 16, &temp, 4); + + memset(buffer + 20, 0, 12); + } + + return ret; +} + +uint32_t UPIUReadyToTransfer::getLength() { + return 32; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/def.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/def.hh new file mode 100644 index 0000000000..35bb0c5b43 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/def.hh @@ -0,0 +1,416 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_DEF__ +#define __HIL_UFS_DEF__ + +#include + +union UFSHCIRegister { + uint8_t data[0xB0]; + struct { + /* Host Capabilities */ + uint32_t cap; + uint32_t reserved0; + uint32_t version; + uint32_t reserved1; + uint32_t hcddid; + uint32_t hcpmid; + uint32_t reserved2[2]; + + /* Operation Runtime */ + uint32_t is; + uint32_t ie; + uint32_t reserved3[2]; + uint32_t hcs; + uint32_t hce; + uint32_t uecpa; + uint32_t uecdl; + uint32_t uecn; + uint32_t uect; + uint32_t uecdme; + uint32_t utriacr; + + /* UFS Transport Protocol Transfer */ + uint64_t utrlba; + uint32_t utrldbr; + uint32_t utrlclr; + uint32_t utrlrsr; + uint32_t reserved4[3]; + + /* UFS Transport Protocol Task Management */ + uint64_t utmrlba; + uint32_t utmrldbr; + uint32_t utmrlclr; + uint32_t utmrlrsr; + uint32_t reserved5[3]; + + /* UFS InterConnect Command */ + uint32_t uiccmdr; + uint32_t ucmdarg1; + uint32_t ucmdarg2; + uint32_t ucmdarg3; + uint32_t reserved6[4]; + }; + + UFSHCIRegister(); +}; + +enum UFSHCIREG { + REG_CAP = 0x00, + REG_VER = 0x08, + REG_HCDDID = 0x10, + REG_HCPMID = 0x14, + REG_IS = 0x20, + REG_IE = 0x24, + REG_HCS = 0x30, + REG_HCE = 0x34, + REG_UECPA = 0x38, + REG_UECDL = 0x3C, + REG_UECN = 0x40, + REG_UECT = 0x44, + REG_UECDME = 0x48, + REG_UTRIACR = 0x4C, + REG_UTRLBA = 0x50, + REG_UTRLBAU = 0x54, + REG_UTRLDBR = 0x58, + REG_UTRLCLR = 0x5C, + REG_UTRLRSR = 0x60, + REG_UTMRLBA = 0x70, + REG_UTMRLBAU = 0x74, + REG_UTMRLDBR = 0x78, + REG_UTMRLCLR = 0x7C, + REG_UTMRLRSR = 0x80, + REG_UICCMDR = 0x90, + REG_UCMDARG1 = 0x94, + REG_UCMDARG2 = 0x98, + REG_UCMDARG3 = 0x9C, +}; + +enum DMECMD { + DME_GET = 0x01, + DME_SET, + DME_PEER_GET, + DME_PEER_SET, + DME_POWERON = 0x10, + DME_POWEROFF, + DME_ENABLE, + DME_RESET = 0x14, + DME_ENDPOINTRESET, + DME_LINKSTARTUP, + DME_HIBERNATE_ENTER, + DME_HIBERNATE_EXIT, + DME_TEST_MODE = 0x1A +}; + +enum DMEERR { + ERR_SUCCESS, + ERR_INVALID_MIB, + ERR_INVALID_MIB_VALUE, + ERR_READ_ONLY_MIB, + ERR_WRITE_ONLY_MIB, + ERR_BAD_INDEX, + ERR_LOCKED_MIB, + ERR_BAD_TEST_FEATURE_INDEX, + ERR_PEER_COMMUNICATION_FAILURE, + ERR_BUSY, + ERR_DME_FAILURE +}; + +enum MIB { + // See Linux kernel /drivers/scsi/ufs/unipro.h + MIB_VS_POWERSTATE = 0xD083 +}; + +enum UFSLINK { + // See Linux kernel /drivers/scsi/ufs/unihci.h + UFSHCD_LINK_IS_DOWN = 1, + UFSHCD_LINK_IS_UP +}; + +#define MAKE_UICARG(mib, selector) \ + (((uint32_t)(mib) << 16) | ((uint32_t)(selector)&0xFFFF)) + +#define UFS_BIT(x) (1L << (x)) + +#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0) +#define UIC_DME_END_PT_RESET UFS_BIT(1) +#define UIC_ERROR UFS_BIT(2) +#define UIC_TEST_MODE UFS_BIT(3) +#define UIC_POWER_MODE UFS_BIT(4) +#define UIC_HIBERNATE_EXIT UFS_BIT(5) +#define UIC_HIBERNATE_ENTER UFS_BIT(6) +#define UIC_LINK_LOST UFS_BIT(7) +#define UIC_LINK_STARTUP UFS_BIT(8) +#define UTP_TASK_REQ_COMPL UFS_BIT(9) +#define UIC_COMMAND_COMPL UFS_BIT(10) +#define DEVICE_FATAL_ERROR UFS_BIT(11) +#define CONTROLLER_FATAL_ERROR UFS_BIT(16) +#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17) + +#define UTP_TRANSFER_REQ_DESC_SIZE 32 + +union UTPTransferReqDesc { + uint8_t data[UTP_TRANSFER_REQ_DESC_SIZE]; + struct { + uint32_t dw0; + uint32_t dw1; + uint32_t dw2; + uint32_t dw3; + uint32_t cmdAddress; + uint32_t cmdAddressUpper; + uint16_t respUPIULength; + uint16_t respUPIUOffset; + uint16_t prdtLength; + uint16_t prdtOffset; + }; +}; + +enum UTP_TRANSFER_CMD { + CMD_SCSI, + CMD_NATIVE_UFS_COMMAND, + CMD_DEVICE_MGMT_FUNCTION +}; + +union PRDT { + uint8_t data[16]; + struct { + uint64_t dataAddress; + uint32_t dw2; + uint32_t dw3; + }; +}; + +enum UPIU_OPCODE { // Response OPCODE + OPCODE_NOP_OUT = 0x00, // OPCODE_NOP_IN + OPCODE_COMMAND, // OPCODE_RESPONSE + OPCODE_DATA_OUT, // OPCODE_RESPONSE + OPCODE_TASK_MGMT_REQ = 0x04, // OPCODE_TASK_MGMT_RESP + OPCODE_QUERY_REQUEST = 0x16, // OPCODE_QUERY_RESPONSE + OPCODE_NOP_IN = 0x20, + OPCODE_RESPONSE, + OPCODE_DATA_IN, + OPCODE_TASK_MGMT_RESP = 0x24, + OPCODE_READY_TO_TRANSFER = 0x31, + OPCODE_QUERY_RESPONSE = 0x36, + OPCODE_REJECT_UPIU = 0x3F +}; + +struct UPIUHeader { + uint8_t transactionType; + uint8_t flags; + uint8_t lun; + uint8_t taskTag; + uint8_t commandSetType; + uint8_t function; + uint8_t response; + uint8_t status; + uint8_t ehsLength; + uint8_t deviceInfo; + uint16_t dataSegmentLength; +}; + +struct UPIU { + UPIUHeader header; + + UPIU(); + virtual ~UPIU(); + + virtual bool set(uint8_t *, uint32_t); + virtual bool get(uint8_t *, uint32_t); + virtual uint32_t getLength(); +}; + +struct UPIUCommand : public UPIU { + uint32_t expectedDataLength; + uint8_t cdb[16]; + + UPIUCommand(); + ~UPIUCommand(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUResponse : public UPIU { + uint32_t residualCount; + + uint16_t senseLength; + uint8_t senseData[18]; + + UPIUResponse(); + ~UPIUResponse(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUQueryReq : public UPIU { + uint8_t opcode; + uint8_t idn; + uint8_t index; + uint8_t selector; + uint16_t length; + uint32_t val1; + uint32_t val2; + + uint8_t *data; + + UPIUQueryReq(); + ~UPIUQueryReq(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUQueryResp : public UPIU { + uint8_t opcode; + uint8_t idn; + uint8_t index; + uint8_t selector; + uint16_t length; + uint32_t val1; + uint32_t val2; + + uint8_t *data; + + UPIUQueryResp(); + ~UPIUQueryResp(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUDataOut : public UPIU { + uint32_t offset; + uint32_t count; + + uint8_t *data; + + UPIUDataOut(); + ~UPIUDataOut(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUDataIn : public UPIU { + uint32_t offset; + uint32_t count; + + uint8_t *data; + + UPIUDataIn(); + ~UPIUDataIn(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +struct UPIUReadyToTransfer : public UPIU { + uint32_t offset; + uint32_t count; + + UPIUReadyToTransfer(); + ~UPIUReadyToTransfer(); + + bool set(uint8_t *, uint32_t); + bool get(uint8_t *, uint32_t); + uint32_t getLength(); +}; + +enum QUERY_OPCODE { + OPCODE_NOP, + OPCODE_READ_DESCRIPTOR, + OPCODE_WRITE_DESCRIPTOR, + OPCODE_READ_ATTRIBUTE, + OPCODE_WRITE_ATTRIBUTE, + OPCODE_READ_FLAG, + OPCODE_SET_FLAG, + OPCODE_CLEAR_FLAG, + OPCODE_TOGGLE_FLAG +}; + +enum DESCRIPTOR_IDN { + IDN_DEVICE, + IDN_CONFIGURATION, + IDN_UNIT, + IDN_INTERCONNECT = 0x04, + IDN_STRING, + IDN_GEOMETRY = 0x07, + IDN_POWER, + IDN_DEVICE_HEALTH +}; + +#define IDN_DEVICE_LENGTH 0x1F // Linux kernel v4.9.30 /driver/scsi/ufs/ufs.h +#define IDN_POWER_LENGTH 0x62 +#define IDN_STRING_LENGTH 0xFE // Linux kernel v4.9.30 /driver/scsi/ufs/ufs.h +#define IDN_UNIT_LENGTH 0x23 + +enum SCSI_COMMAND { + /* SPC-4 */ + CMD_INQUIRY = 0x12, + CMD_MODE_SELECT_10 = 0x55, + CMD_MODE_SENSE_10 = 0x5A, + CMD_REPORT_LUNS = 0xA0, + CMD_REQUEST_SENSE = 0x03, + CMD_SECURITY_PROTOCOL_IN = 0xA2, + CMD_SECURITY_PROTOCOL_OUT = 0xB5, + CMD_SEND_DIAGNOSTIC = 0x1D, + CMD_TEST_UNIT_READY = 0x00, + + /* SBC-3 */ + CMD_FORMAT_UNIT = 0x04, + CMD_PREFETCH_10 = 0x34, + CMD_READ_6 = 0x08, + CMD_READ_10 = 0x28, + CMD_READ_CAPACITY_10 = 0x25, + CMD_READ_CAPACITY_16 = 0x9E, + CMD_START_STOP_UNIT = 0x1B, + CMD_VERIFY_10 = 0x2F, + CMD_WRITE_6 = 0x0A, + CMD_WRITE_10 = 0x2A, + CMD_SYNCHRONIZE_CACHE_10 = 0x35, +}; + +#define SCSI_INQUIRY_LENGTH 36 + +enum WLUN { + WLUN_REPORT_LUNS = 0x01, + WLUN_UFS_DEVICE = 0x50, + WLUN_BOOT = 0x30, + WLUN_RPMB = 0x44, +}; + +/* This is vendor specific */ +enum DEVICE_STRING_INDEX { + STRING_MANUFACTURER, + STRING_PRODUCT_NAME, + STRING_SERIAL_NUMBER, + STRING_OEM_ID, + STRING_PRODUCT_REVISION_LEVEL +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/device.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/device.cc new file mode 100644 index 0000000000..69ccb0db03 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/device.cc @@ -0,0 +1,969 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/ufs/device.hh" + +#include + +#include "hil/ufs/interface.hh" +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +struct IOContext { + uint64_t beginAt; + uint32_t slba; + uint32_t nlb; + uint64_t tick; + + uint8_t *buffer; + + uint8_t *prdt; + uint32_t prdtLength; + + DMAFunction func; + void *context; + + IOContext(DMAFunction &f) : beginAt(getTick()), func(f) {} +}; + +LUN::_LUN(bool b, uint8_t n, ConfigReader &cfg) : bWellknown(b), id(n) { + uint8_t wn = bWellknown ? 0x80 : 0x00; + + // Initialize unit descriptor + memset(unitDescriptor, 0, IDN_UNIT_LENGTH); + unitDescriptor[0x00] = IDN_UNIT_LENGTH; + unitDescriptor[0x01] = IDN_UNIT; + unitDescriptor[0x02] = wn | id; // Unit index + unitDescriptor[0x03] = 0x01; // LU enabled + unitDescriptor[0x04] = 0x01; // Boot LUN ID + unitDescriptor[0x05] = 0x00; // Write protect + unitDescriptor[0x06] = 0x00; // Queue depth + unitDescriptor[0x07] = 0x00; // PSA Sensitive + unitDescriptor[0x08] = 0x00; // Memory type + unitDescriptor[0x09] = 0x00; // Data reliability + + if (bWellknown) { + unitDescriptor[0x0A] = 0x00; // LBA size + *(uint64_t *)(unitDescriptor + 0x0B) = 0; // Total logical LBA + *(uint32_t *)(unitDescriptor + 0x13) = 0; // Total LBA in physical block + unitDescriptor[0x17] = 0x00; // Thin provisioning + *(uint64_t *)(unitDescriptor + 0x18) = 0; // Total physical LBA + } + else { + // TODO: Fix this code (duplicated) + uint64_t lbaSize = cfg.readUint(CONFIG_UFS, UFS_LBA_SIZE); + uint64_t blockSize = cfg.readUint(CONFIG_PAL, PAL::NAND_PAGE_SIZE); + uint64_t totalSize = cfg.readUint(CONFIG_PAL, PAL::PAL_CHANNEL); + + blockSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_PAGE); + + totalSize *= cfg.readUint(CONFIG_PAL, PAL::PAL_PACKAGE); + totalSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_DIE); + totalSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_PLANE); + totalSize *= cfg.readUint(CONFIG_PAL, PAL::NAND_BLOCK); + totalSize *= blockSize; + + blockSize *= cfg.readBoolean(CONFIG_PAL, PAL::NAND_USE_MULTI_PLANE_OP) + ? cfg.readUint(CONFIG_PAL, PAL::NAND_PLANE) + : 1; + + unitDescriptor[0x0A] = (uint8_t)log2f(lbaSize); // LBA size + *(uint64_t *)(unitDescriptor + 0x0B) = + (totalSize * + (1 - cfg.readFloat(CONFIG_FTL, FTL::FTL_OVERPROVISION_RATIO))) / + lbaSize; // Total logical LBA + *(uint32_t *)(unitDescriptor + 0x13) = + blockSize / lbaSize; // Total LBA in physical block + unitDescriptor[0x17] = 0x00; // Thin provisioning + *(uint64_t *)(unitDescriptor + 0x18) = + totalSize / lbaSize; // Total physical LBA + } + + unitDescriptor[0x20] = 0x00; + unitDescriptor[0x21] = 0x00; // Context capabilityes + unitDescriptor[0x22] = 0x00; // Large unit granuality + + // Initialize INQUIRY structure + memset(inquiry, 0, SCSI_INQUIRY_LENGTH); + inquiry[0] = bWellknown ? 0x1E : 0x00; + inquiry[2] = 0x06; + inquiry[3] = 0x02; + inquiry[4] = 31; + inquiry[7] = 0x02; + + sprintf((char *)inquiry + 8, "SimpleSSD UFS Device"); +} + +Device::Device(DMAInterface *d, ConfigReader &c) + : pDMA(d), + pHIL(nullptr), + pDisk(nullptr), + conf(c), + lunReportLuns(true, WLUN_REPORT_LUNS, c), + lunUFSDevice(true, WLUN_UFS_DEVICE, c), + lunBoot(true, WLUN_BOOT, c), + lunRPMB(true, WLUN_RPMB, c), + lun(false, 0x00, c) { + // Initialize Strings + sprintf((char *)strManufacturer, "CAMELab"); + sprintf((char *)strProductName, "SimpleSSD UFS Device"); + sprintf((char *)strSerialNumber, "000000000000"); + sprintf((char *)strOEMID, "None"); + sprintf((char *)strProductRevision, "v02.01"); + + // Initialize device descriptor + memset(deviceDescriptor, 0, IDN_DEVICE_LENGTH); + deviceDescriptor[0x00] = IDN_DEVICE_LENGTH; // Length + deviceDescriptor[0x01] = IDN_DEVICE; // Descriptor IDN + deviceDescriptor[0x02] = 0x00; // Device Type + deviceDescriptor[0x03] = 0x00; // UFS Device Class + deviceDescriptor[0x04] = 0x00; // UFS Mass Storage Subclass + deviceDescriptor[0x05] = 0x00; // Protocol supported by UFS Device + deviceDescriptor[0x06] = 0x01; // Number of Logical Units + deviceDescriptor[0x07] = 0x04; // Number of Well known Logical Units + deviceDescriptor[0x08] = 0x01; // Boot Enable + deviceDescriptor[0x09] = 0x00; // Descriptor Access Enable + deviceDescriptor[0x0A] = 0x01; // Initial Power Mode + deviceDescriptor[0x0B] = 0x7F; // High Priority LUN + deviceDescriptor[0x0C] = 0x00; // Secure Removal Type + deviceDescriptor[0x0D] = 0x00; // Support for security LU + deviceDescriptor[0x0E] = 0x00; // Background Operations Termination Latency + deviceDescriptor[0x0F] = 0x00; // Initial Active ICC Level + deviceDescriptor[0x10] = 0x10; + deviceDescriptor[0x11] = 0x02; // UFS Version 2.1 + deviceDescriptor[0x12] = 0x00; + deviceDescriptor[0x13] = 0x00; // Manufacturing Date + deviceDescriptor[0x14] = STRING_MANUFACTURER; + deviceDescriptor[0x15] = STRING_PRODUCT_NAME; + deviceDescriptor[0x16] = STRING_SERIAL_NUMBER; + deviceDescriptor[0x17] = STRING_OEM_ID; + deviceDescriptor[0x18] = 0x00; + deviceDescriptor[0x19] = 0x00; // Manufacturer ID + deviceDescriptor[0x1A] = 0x10; // Unit Descriptor 0 Base Offset + deviceDescriptor[0x1B] = 0x10; // Unit Descriptor Config Parameter Length + deviceDescriptor[0x1C] = 0x02; // RTT Capability of device + deviceDescriptor[0x1D] = 0x00; + deviceDescriptor[0x1E] = 0x00; + // deviceDescriptor[0x1F] = 0x00; // UFS Features Support + // deviceDescriptor[0x20] = 0x00; // Field Firmware Update Timeout + // deviceDescriptor[0x21] = 0x20; // Queue Depth + // deviceDescriptor[0x22] = 0x00; + // deviceDescriptor[0x23] = 0x00; // Device version + // deviceDescriptor[0x24] = 0x00; // Number of Secure Write Protection Areas + // deviceDescriptor[0x25] = 0x00; + // deviceDescriptor[0x26] = 0x00; + // deviceDescriptor[0x27] = 0x00; + // deviceDescriptor[0x28] = 0x00; // PSA Maximum Data Size + // deviceDescriptor[0x29] = 0x00; // PSA State Timeout + // deviceDescriptor[0x2A] = STRING_PRODUCT_REVISION_LEVEL; + + // Initialize power descriptor + memset(powerDescriptor, 0, IDN_POWER_LENGTH); + powerDescriptor[0x00] = IDN_POWER_LENGTH; // Length + powerDescriptor[0x01] = IDN_POWER; // Descriptor IDN + *(uint16_t *)(powerDescriptor + 0x02) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x04) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x06) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x08) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x0A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x0C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x0E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x10) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x12) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x14) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x16) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x18) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x1A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x1C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x1E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x20) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x22) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x24) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x26) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x28) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x2A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x2C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x2E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x30) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x32) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x34) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x36) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x38) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x3A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x3C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x3E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x40) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x42) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x44) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x46) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x48) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x4A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x4C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x4E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x50) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x52) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x54) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x56) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x58) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x5A) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x5C) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x5E) = 0x0100; + *(uint16_t *)(powerDescriptor + 0x60) = 0x0100; + + // Create HIL + pHIL = new HIL(c); + pHIL->getLPNInfo(totalLogicalPages, logicalPageSize); + + // Create Disk + if (conf.readBoolean(CONFIG_UFS, UFS_ENABLE_DISK_IMAGE)) { + uint64_t diskSize; + uint64_t expected; + + expected = totalLogicalPages * logicalPageSize; + + if (conf.readBoolean(CONFIG_UFS, UFS_USE_COW_DISK)) { + pDisk = new CoWDisk(); + } + else { + pDisk = new Disk(); + } + + std::string filename = conf.readString(CONFIG_UFS, UFS_DISK_IMAGE_PATH); + + diskSize = pDisk->open(filename, expected, + conf.readUint(CONFIG_UFS, UFS_LBA_SIZE)); + + if (diskSize == 0) { + panic("Failed to open disk image"); + } + else if (diskSize != expected) { + if (conf.readBoolean(CONFIG_UFS, UFS_STRICT_DISK_SIZE)) { + panic("Disk size not match"); + } + } + } + + // Set cache info + bReadCache = conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_READ_CACHE); + bWriteCache = conf.readBoolean(CONFIG_ICL, ICL::ICL_USE_WRITE_CACHE); + + // DMA Handler for PRDT + dmaHandler = [](uint64_t now, void *context) { + DMAContext *pContext = (DMAContext *)context; + + pContext->counter--; + + if (pContext->counter == 0) { + pContext->function(now, pContext->context); + delete pContext; + } + }; +} + +Device::~Device() { + delete pHIL; + delete pDisk; +} + +void Device::processQueryCommand(UPIUQueryReq *req, UPIUQueryResp *resp) { + resp->opcode = req->opcode; + resp->idn = req->idn; + resp->index = req->index; + resp->selector = req->selector; + resp->length = req->length; + + debugprint( + LOG_HIL_UFS, + "COMMAND | UPIU Query Request | OPCODE %d | IDN %d | LUN 0x%X | Tag " + "0x%X", + req->opcode, req->idn, req->header.lun, req->header.taskTag); + + switch (req->opcode) { + case OPCODE_NOP: + break; + case OPCODE_READ_DESCRIPTOR: { + switch (req->idn) { + case IDN_DEVICE: + resp->header.dataSegmentLength = req->length; + resp->length = IDN_DEVICE_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + memcpy(resp->data, deviceDescriptor, req->length); + break; + case IDN_UNIT: { + uint8_t *buffer = nullptr; + + switch (req->header.lun) { + case 0x80 | WLUN_REPORT_LUNS: + buffer = lunReportLuns.unitDescriptor; + break; + case 0x80 | WLUN_UFS_DEVICE: + buffer = lunUFSDevice.unitDescriptor; + break; + case 0x80 | WLUN_BOOT: + buffer = lunBoot.unitDescriptor; + break; + case 0x80 | WLUN_RPMB: + buffer = lunRPMB.unitDescriptor; + break; + case 0x00: + buffer = lun.unitDescriptor; + break; + default: + warn("Unknown LUN 0x%2X", req->header.lun); + } + + resp->header.dataSegmentLength = req->length; + resp->length = IDN_UNIT_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + + if (buffer) { + memcpy(resp->data, buffer, req->length); + } + } break; + case IDN_POWER: + resp->header.dataSegmentLength = req->length; + resp->length = IDN_POWER_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + memcpy(resp->data, powerDescriptor, req->length); + break; + case IDN_STRING: { + resp->header.dataSegmentLength = req->length; + resp->length = IDN_STRING_LENGTH; + req->length = MIN(req->length, resp->length); + resp->data = (uint8_t *)calloc(req->length, 1); + + resp->data[0] = IDN_STRING_LENGTH; + resp->data[1] = IDN_STRING; + + switch (req->index) { + case STRING_MANUFACTURER: + memcpy(resp->data + 2, strManufacturer, req->length - 2); + break; + case STRING_PRODUCT_NAME: + memcpy(resp->data + 2, strProductName, req->length - 2); + break; + case STRING_SERIAL_NUMBER: + memcpy(resp->data + 2, strSerialNumber, req->length - 2); + break; + case STRING_OEM_ID: + memcpy(resp->data + 2, strOEMID, req->length - 2); + break; + case STRING_PRODUCT_REVISION_LEVEL: + memcpy(resp->data + 2, strProductRevision, req->length - 2); + break; + default: + warn("Unknown string index %#x", req->index); + + break; + } + } break; + default: + warn("Not implemented descriptor idn %#x", req->idn); + + break; + } + } break; + default: + warn("Not implemented query opcode %#x", req->opcode); + + break; + } +} + +void Device::processCommand(UTP_TRANSFER_CMD cmd, UPIUCommand *req, + UPIUResponse *resp, uint8_t *prdt, + uint32_t prdtLength, DMAFunction &func, + void *context) { + static uint64_t lbaSize = conf.readUint(CONFIG_UFS, UFS_LBA_SIZE); + bool immediate = true; + uint8_t *buffer = nullptr; + uint64_t length = 0; + + resp->header.lun = req->header.lun; + + // debugprint(LOG_HIL_UFS, "COMMAND | UPIU Command | CT %d", + // cmd); + + // TODO: Check LUN for I/O + + switch (cmd) { + case CMD_SCSI: { + uint8_t opcode = req->cdb[0]; + uint32_t slba = 0; + uint16_t nlb = 0; + + debugprint(LOG_HIL_UFS, + "COMMAND | SCSI Command 0x%X | LUN 0x%X | Tag 0x%X", opcode, + req->header.lun, req->header.taskTag); + + switch (opcode) { + case CMD_INQUIRY: { + buffer = nullptr; + + switch (req->header.lun) { + case 0x80 | WLUN_REPORT_LUNS: + buffer = lunReportLuns.inquiry; + break; + case 0x80 | WLUN_UFS_DEVICE: + buffer = lunUFSDevice.inquiry; + break; + case 0x80 | WLUN_BOOT: + buffer = lunBoot.inquiry; + break; + case 0x80 | WLUN_RPMB: + buffer = lunRPMB.inquiry; + break; + case 0x00: + buffer = lun.inquiry; + break; + default: + warn("Unknown LUN 0x%2X", req->header.lun); + } + + if (buffer) { + prdtWrite(prdt, prdtLength, 36, buffer, func, context); + immediate = false; + } + } break; + case CMD_MODE_SELECT_10: + // Not Implemented + break; + case CMD_MODE_SENSE_10: { + uint32_t size = 0; + + switch (req->cdb[2] & 0x3F) { + case 0x0A: { + size = 20; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x12; // Length + + buffer[8] = 0x0A; // Control Page + buffer[9] = 0x0A; // Length + } break; + case 0x01: { + size = 20; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x12; // Length + + buffer[8] = 0x01; // Recovery Page + buffer[9] = 0x0A; // Length + } break; + case 0x08: { + size = 28; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x1A; // Length + + buffer[8] = 0x08; // Caching Page + buffer[9] = 0x12; // Length + buffer[10] = 0x00; + + buffer[10] |= bReadCache ? 0x00 : 0x01; // Set RCD + buffer[10] |= bWriteCache ? 0x04 : 0x00; // Set WCE + } break; + case 0x3F: { + size = 52; + buffer = (uint8_t *)calloc(size, 1); + + // UFS Mode parameter header + buffer[1] = 0x32; // Length + + buffer[8] = 0x01; // Recovery Page + buffer[9] = 0x0A; // Length + buffer[20] = 0x0A; // Control Page + buffer[21] = 0x0A; // Length + buffer[32] = 0x08; // Caching Page + buffer[33] = 0x12; // Length + buffer[34] = 0x00; + + buffer[34] |= bReadCache ? 0x00 : 0x01; // Set RCD + buffer[34] |= bWriteCache ? 0x04 : 0x00; // Set WCE + } break; + default: + warn("Not implemented mode page %#x", req->cdb[2] & 0x3F); + buffer = nullptr; + break; + } + + length = size; + } break; + case CMD_READ_6: { + slba = (((uint64_t)(req->cdb[1]) & 0x1F) << 16) | + ((uint64_t)req->cdb[2] << 8) | req->cdb[3]; + nlb = req->cdb[4] == 0 ? 256 : req->cdb[4]; + } break; + case CMD_READ_10: { + // bool fua = req->cdb[1] & 0x08; + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + } break; + case CMD_READ_CAPACITY_10: { + uint32_t temp; + // TODO: fill appropriate value for lba count + buffer = (uint8_t *)calloc(8, 1); + + temp = + (uint32_t)((totalLogicalPages * logicalPageSize / lbaSize) - 1); + temp = __builtin_bswap32(temp); + memcpy(buffer, &temp, 4); + + temp = lbaSize; + temp = __builtin_bswap32(temp); + memcpy(buffer + 4, &temp, 4); + + length = 8; + } break; + case CMD_READ_CAPACITY_16: { + uint32_t temp32; + uint64_t temp64; + + buffer = (uint8_t *)calloc(32, 1); + + temp64 = (totalLogicalPages * logicalPageSize) / lbaSize - 1; + temp64 = __builtin_bswap64(temp64); + memcpy(buffer, &temp64, 8); + + temp32 = lbaSize; + temp32 = __builtin_bswap32(temp32); + memcpy(buffer + 8, &temp32, 4); + + length = 32; + } break; + case CMD_START_STOP_UNIT: + // Just response + break; + case CMD_TEST_UNIT_READY: + // Just response + break; + case CMD_REPORT_LUNS: { + uint8_t sel = req->cdb[2]; + + buffer = (uint8_t *)calloc(40, 1); + + if (sel == 0) { + // Return one LUN + buffer[3] = 8; // 8 bytes in Big Endian + } + else if (sel == 1) { + // Return three LUN + buffer[3] = 24; + buffer[8] = 0xC1; + buffer[9] = WLUN_REPORT_LUNS; + buffer[16] = 0xC1; + buffer[17] = WLUN_UFS_DEVICE; + buffer[24] = 0xC1; + buffer[25] = WLUN_BOOT; + } + else if (sel == 2) { + // Return four LUN + buffer[3] = 32; + buffer[8] = 0xC1; + buffer[9] = WLUN_REPORT_LUNS; + buffer[16] = 0xC1; + buffer[17] = WLUN_UFS_DEVICE; + buffer[24] = 0xC1; + buffer[25] = WLUN_BOOT; + } + else { + warn("Unknown select report field %#x", sel); + } + + length = 40; + } break; + case CMD_VERIFY_10: { + uint32_t slba; + uint16_t nlb; + + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + + if (slba + nlb > totalLogicalPages * logicalPageSize) { + resp->header.status = 0x0; // Check condition + // Fill sense data + // TODO: modulize this error sense part + resp->header.dataSegmentLength = 20; + resp->senseLength = 18; + resp->senseData[0] = 0x70; + resp->senseData[2] = 0x05; // Illegal Request + resp->senseData[7] = 0x0A; + } + } break; + case CMD_WRITE_6: { + slba = (((uint64_t)(req->cdb[1]) & 0x1F) << 16) | + ((uint64_t)req->cdb[2] << 8) | req->cdb[3]; + nlb = req->cdb[4] == 0 ? 256 : req->cdb[4]; + } break; + case CMD_WRITE_10: { + // bool fua = req->cdb[1] & 0x08; + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + } break; + case CMD_REQUEST_SENSE: + case CMD_FORMAT_UNIT: + case CMD_PREFETCH_10: + case CMD_SECURITY_PROTOCOL_IN: + case CMD_SECURITY_PROTOCOL_OUT: + case CMD_SEND_DIAGNOSTIC: + // Not implemented + break; + case CMD_SYNCHRONIZE_CACHE_10: { + bool immed = req->cdb[1] & 0x10; + memcpy(&slba, req->cdb + 2, 4); + memcpy(&nlb, req->cdb + 7, 2); + + slba = __builtin_bswap32(slba); + nlb = __builtin_bswap16(nlb); + + if (immed) { + static DMAFunction dummy = [](uint64_t, void *) {}; + + flush(dummy, nullptr); + } + else { + flush(func, context); + + immediate = false; + } + } break; + default: + warn("Not implemented SCSI command %#x", opcode); + break; + } + + if (opcode == CMD_READ_10 || opcode == CMD_READ_6) { + if (nlb > 0) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | READ | %d + %d | DMA %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->func(tick, pContext->context); + + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | READ | %d + %d | NAND %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + prdtWrite(pContext->prdt, pContext->prdtLength, + pContext->nlb * lbaSize, pContext->buffer, doWrite, + context); + }; + + IOContext *pContext = new IOContext(func); + + pContext->buffer = (uint8_t *)calloc(nlb * lbaSize, 1); + pContext->context = context; + pContext->slba = slba; + pContext->nlb = nlb; + pContext->prdt = prdt; + pContext->prdtLength = prdtLength; + + debugprint(LOG_HIL_UFS, "NVM | READ | %d + %d", pContext->slba, + pContext->nlb); + + read(slba, nlb, pContext->buffer, doRead, pContext); + + immediate = false; + } + } + else if (opcode == CMD_WRITE_10 || opcode == CMD_WRITE_6) { + if (nlb > 0) { + DMAFunction doRead = [this](uint64_t tick, void *context) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | WRITE | %d + %d | NAND %" PRIu64 + " - %" PRIu64 " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->tick, tick, + tick - pContext->tick); + + pContext->func(tick, pContext->context); + + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = (IOContext *)context; + + debugprint(LOG_HIL_UFS, + "NVM | WRITE | %d + %d | DMA %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + pContext->slba, pContext->nlb, pContext->beginAt, tick, + tick - pContext->beginAt); + + pContext->tick = tick; + + write(pContext->slba, pContext->nlb, pContext->buffer, doWrite, + context); + }; + + IOContext *pContext = new IOContext(func); + + pContext->buffer = (uint8_t *)calloc(nlb * lbaSize, 1); + pContext->context = context; + pContext->slba = slba; + pContext->nlb = nlb; + + debugprint(LOG_HIL_UFS, "NVM | WRITE | %d + %d", pContext->slba, + pContext->nlb); + + prdtRead(prdt, prdtLength, nlb * lbaSize, pContext->buffer, doRead, + pContext); + + immediate = false; + } + } + else if (opcode == CMD_MODE_SENSE_10 || opcode == CMD_READ_CAPACITY_10 || + opcode == CMD_READ_CAPACITY_16 || opcode == CMD_REPORT_LUNS) { + if (buffer) { + DMAFunction doWrite = [](uint64_t tick, void *context) { + IOContext *pContext = (IOContext *)context; + + pContext->func(tick, pContext->context); + + free(pContext->buffer); + delete pContext; + }; + + IOContext *pContext = new IOContext(func); + pContext->buffer = buffer; + pContext->context = context; + + prdtWrite(prdt, prdtLength, length, buffer, doWrite, pContext); + + immediate = false; + } + } + + if (immediate) { + func(getTick(), context); + } + } break; + case CMD_NATIVE_UFS_COMMAND: + // Not used in UFS v2.1 + break; + case CMD_DEVICE_MGMT_FUNCTION: + // Should processed in processQueryCommand + warn("Device management function on UPIU Command is not " + "defined operation"); + break; + } +} + +void Device::prdtRead(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doRead = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t read = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - read); + + pContext->counter++; + pDMA->dmaRead(table[idx].dataAddress, size, buffer + read, dmaHandler, + context); + + read += size; + + if (read >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::UFS__DEVICE, CPU::PRDT_READ, doRead, pContext); +} + +void Device::prdtWrite(uint8_t *prdt, uint32_t prdtLength, uint32_t length, + uint8_t *buffer, DMAFunction &func, void *context) { + DMAFunction doWrite = [=](uint64_t, void *context) { + DMAContext *pContext = (DMAContext *)context; + + PRDT *table = (PRDT *)prdt; + uint64_t written = 0; + + for (uint32_t idx = 0; idx < prdtLength; idx++) { + uint32_t size = (table[idx].dw3 & 0x3FFFF) + 1; + + size = MIN(size, length - written); + + pContext->counter++; + pDMA->dmaWrite(table[idx].dataAddress, size, buffer + written, dmaHandler, + context); + + written += size; + + if (written >= length) { + break; + } + } + + if (pContext->counter == 0) { + pContext->counter = 1; + + dmaHandler(getTick(), context); + } + }; + + DMAContext *pContext = new DMAContext(func, context); + + execute(CPU::UFS__DEVICE, CPU::PRDT_WRITE, doWrite, pContext); +} + +void Device::convertUnit(uint64_t slba, uint64_t nlblk, Request &req) { + static uint64_t lbaSize = conf.readUint(CONFIG_UFS, UFS_LBA_SIZE); + uint32_t lbaratio = logicalPageSize / lbaSize; + uint64_t slpn; + uint64_t nlp; + uint64_t off; + + slpn = slba / lbaratio; + off = slba % lbaratio; + nlp = (nlblk + off + lbaratio - 1) / lbaratio; + + req.range.slpn = slpn; + req.range.nlp = nlp; + req.offset = off * lbaSize; + req.length = nlblk * lbaSize; +} + +void Device::read(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doRead = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->read(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->read(slba, nlb, buffer); + } + + execute(CPU::UFS__DEVICE, CPU::READ, doRead, req); +} + +void Device::write(uint64_t slba, uint64_t nlb, uint8_t *buffer, + DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doWrite = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->write(*req); + + delete req; + }; + + convertUnit(slba, nlb, *req); + + if (pDisk) { + pDisk->write(slba, nlb, buffer); + } + + execute(CPU::UFS__DEVICE, CPU::WRITE, doWrite, req); +} + +void Device::flush(DMAFunction &func, void *context) { + Request *req = new Request(func, context); + DMAFunction doFlush = [this](uint64_t, void *context) { + auto req = (Request *)context; + + pHIL->flush(*req); + + delete req; + }; + + req->range.slpn = 0; + req->range.nlp = totalLogicalPages; + req->offset = 0; + req->length = totalLogicalPages * logicalPageSize; + + execute(CPU::UFS__DEVICE, CPU::FLUSH, doFlush, req); +} + +void Device::getStatList(std::vector &list, std::string prefix) { + pHIL->getStatList(list, prefix); +} + +void Device::getStatValues(std::vector &values) { + pHIL->getStatValues(values); +} + +void Device::resetStatValues() { + pHIL->resetStatValues(); +} + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/device.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/device.hh new file mode 100644 index 0000000000..ef9ba9a3b8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/device.hh @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_DEVICE__ +#define __HIL_UFS_DEVICE__ + +#include + +#include "hil/hil.hh" +#include "hil/ufs/config.hh" +#include "hil/ufs/def.hh" +#include "hil/ufs/host.hh" +#include "util/disk.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +typedef struct _LUN { + bool bWellknown; + uint8_t id; + + uint8_t unitDescriptor[IDN_UNIT_LENGTH]; + uint8_t inquiry[SCSI_INQUIRY_LENGTH]; + + _LUN(bool, uint8_t, ConfigReader &); +} LUN; + +class Device : public StatObject { + private: + DMAInterface *pDMA; + HIL *pHIL; + Disk *pDisk; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + + ConfigReader &conf; + + // Cache info + bool bReadCache; + bool bWriteCache; + + // Well-known LUNs + LUN lunReportLuns; + LUN lunUFSDevice; + LUN lunBoot; + LUN lunRPMB; + + // LUN + LUN lun; + + // Descriptors + uint8_t deviceDescriptor[IDN_DEVICE_LENGTH]; + uint8_t powerDescriptor[IDN_POWER_LENGTH]; + + uint8_t strManufacturer[IDN_STRING_LENGTH - 2]; + uint8_t strProductName[IDN_STRING_LENGTH - 2]; + uint8_t strSerialNumber[IDN_STRING_LENGTH - 2]; + uint8_t strOEMID[IDN_STRING_LENGTH - 2]; + uint8_t strProductRevision[IDN_STRING_LENGTH - 2]; + + // PRDT + DMAFunction dmaHandler; + + void prdtRead(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void * = nullptr); + void prdtWrite(uint8_t *, uint32_t, uint32_t, uint8_t *, DMAFunction &, + void * = nullptr); + + // IO + void convertUnit(uint64_t, uint64_t, Request &); + void read(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void write(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); + void flush(DMAFunction &, void *); + + public: + Device(DMAInterface *, ConfigReader &); + ~Device(); + + void processQueryCommand(UPIUQueryReq *, UPIUQueryResp *); + void processCommand(UTP_TRANSFER_CMD, UPIUCommand *, UPIUResponse *, + uint8_t *, uint32_t, DMAFunction &, void * = nullptr); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/host.cc b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/host.cc new file mode 100644 index 0000000000..2d35a89305 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/host.cc @@ -0,0 +1,658 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "hil/ufs/host.hh" + +#include "hil/ufs/device.hh" +#include "util/algorithm.hh" +#include "util/fifo.hh" +#include "util/interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +struct RequestContext { + uint32_t bitMask; + uint32_t index; + UTPTransferReqDesc transferReqDesc; +}; + +Host::Host(Interface *i, ConfigReader &c) + : pInterface(i), + conf(c), + requestCounter(0), + lastWorkAt(0), + pendingInterrupt(0) { + ARM::AXI::BUS_WIDTH hostBusWidth; + uint64_t hostBusClock; + + // Get AXI setting + hostBusWidth = + (ARM::AXI::BUS_WIDTH)conf.readInt(CONFIG_UFS, UFS_HOST_AXI_BUS_WIDTH); + hostBusClock = conf.readUint(CONFIG_UFS, UFS_HOST_AXI_CLOCK); + + FIFOParam fifoParam; + + fifoParam.rqSize = 8192; + fifoParam.wqSize = 8192; + fifoParam.transferUnit = 2048; + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + axiFIFO = new FIFO(pInterface, fifoParam); + + // Calculate AXI Stream bus width/speed for M-PHY layer + auto mode = (MIPI::M_PHY::M_PHY_MODE)conf.readInt(CONFIG_UFS, UFS_MPHY_MODE); + uint8_t lane = (uint8_t)conf.readUint(CONFIG_UFS, UFS_MPHY_LANE); + + // Assume maximum 2 lanes + switch (mode) { + case MIPI::M_PHY::HS_G1: // 1.248 Gbps + case MIPI::M_PHY::HS_G2: // 2.496 Gbps + case MIPI::M_PHY::HS_G3: // 4.992 Gbps + hostBusWidth = ARM::AXI::BUS_64BIT; + hostBusClock = 200000000; // 64Bit @ 200MHz -> 1.6GB/s + + break; + case MIPI::M_PHY::HS_G4: // 9.984 Gbps + hostBusWidth = ARM::AXI::BUS_128BIT; + hostBusClock = 200000000; // 128Bit @ 200MHz -> 3.2GB/s + + break; + default: // Suppress warning + break; + } + + fifoParam.latency = [mode, lane](uint64_t size) -> uint64_t { + return MIPI::M_PHY::calculateDelay(mode, lane, size); + }; + + mphyFIFO = new FIFO(axiFIFO, fifoParam); + + fifoParam.latency = [hostBusWidth, hostBusClock](uint64_t size) -> uint64_t { + return ARM::AXI::Stream::calculateDelay(hostBusClock, hostBusWidth, size); + }; + + deviceFIFO = new FIFO(mphyFIFO, fifoParam); + + pDevice = new Device(deviceFIFO, c); + + // Initialize registers + register_table.cap = 0x0707001F; + register_table.version = 0x00010000; + register_table.hcddid = 0xAA003C3C; + register_table.hcpmid = 0x41524D48; + register_table.hcs = 0x00000008; + + memset(&stat, 0, sizeof(stat)); + + // Allocate events + workEvent = allocate([this](uint64_t) { work(); }); + requestEvent = allocate([this](uint64_t) { handleRequest(); }); + completionEvent = allocate([this](uint64_t) { completion(); }); + + maxRequest = conf.readUint(CONFIG_UFS, UFS_MAX_REQUEST_COUNT); + workInterval = conf.readUint(CONFIG_UFS, UFS_WORK_INTERVAL); + requestInterval = workInterval / maxRequest; +} + +Host::~Host() { + delete pDevice; + delete deviceFIFO; + delete mphyFIFO; + delete axiFIFO; +} + +void Host::processUIC() { + uint8_t opcode = register_table.uiccmdr & 0xFF; + + register_table.ucmdarg2 = ERR_SUCCESS; + + debugprint(LOG_HIL_UFS, + "COMMAND | UIC Command | CMD %08X | ARGS %08X, %08X, %08X", + register_table.uiccmdr, register_table.ucmdarg1, + register_table.ucmdarg2, register_table.ucmdarg3); + + switch (opcode) { + case DME_LINKSTARTUP: + register_table.hcs |= 0x0F; + + schedule(workEvent, getTick() + workInterval); + + break; + case DME_GET: + if (register_table.ucmdarg1 == MAKE_UICARG(MIB_VS_POWERSTATE, 0)) { + register_table.ucmdarg3 = UFSHCD_LINK_IS_UP; + } + + break; + default: + // Do Nothing + break; + } + + register_table.is |= UIC_COMMAND_COMPL; + + pInterface->generateInterrupt(); + + register_table.uiccmdr = 0; + + stat.uicCommand++; +} + +void Host::processUTPTask() { + // Not Implemented + panic("UTP Task is not implemented"); +} + +void Host::processUTPTransfer(uint64_t) { + uint32_t bit = 0; + + for (int i = 0; i < 32; i++) { + bit = 1 << i; + + if ((register_table.utrldbr & bit) && !(pendingInterrupt & bit)) { + pendingInterrupt |= bit; + + lRequestQueue.push(i); + } + } +} + +void Host::processUTPCommand(UTPTransferReqDesc &req, UTP_TRANSFER_CMD cmd, + DMAFunction &func, void *context) { + struct UTPCommandContext { + uint8_t *transferReq; + uint8_t *transferResp; + uint8_t *prdt; + UPIU *transferReqUPIU; + UPIU *transferRespUPIU; + + bool reqDone; + bool respDone; + bool prdtDone; + + uint64_t base; + uint32_t offUPIUResp; + uint32_t sizeUPIUResp; + + UTP_TRANSFER_CMD cmd; + + DMAFunction func; + void *context; + + UTPCommandContext(DMAFunction &f, void *c) + : transferReq(nullptr), + transferResp(nullptr), + prdt(nullptr), + reqDone(false), + respDone(false), + prdtDone(false), + func(f), + context(c) {} + }; + + uint32_t offPRDT = req.prdtOffset * 4; + uint32_t sizePRDT = req.prdtLength * sizeof(PRDT); + + UTPCommandContext *commandContext = new UTPCommandContext(func, context); + + DMAFunction doRequest = [this](uint64_t now, void *context) { + DMAFunction done = [this](uint64_t, void *context) { + DMAFunction doWrite = [](uint64_t now, void *context) { + auto pContext = (UTPCommandContext *)context; + auto pResult = (RequestContext *)pContext->context; + + // debugprint(LOG_HIL_UFS, + // "COMMAND | UPIU Transfer Response | TT 0x%X", + // transferRespUPIU->header.transactionType); + + // Write status to DW2 + pResult->transferReqDesc.dw2 = 0; + + // Cleanup + free(pContext->transferReq); + free(pContext->transferResp); + if (pContext->prdt) { + free(pContext->prdt); + } + + delete pContext->transferReqUPIU; + delete pContext->transferRespUPIU; + + pContext->func(now, pContext->context); + + delete pContext; + }; + + auto pContext = (UTPCommandContext *)context; + + // Transfer response + pContext->transferRespUPIU->header.taskTag = + pContext->transferReqUPIU->header.taskTag; + pContext->transferRespUPIU->get(pContext->transferResp, + pContext->sizeUPIUResp); + axiFIFO->dmaWrite(pContext->base + pContext->offUPIUResp, + pContext->sizeUPIUResp, pContext->transferResp, doWrite, + context); + }; + + auto pContext = (UTPCommandContext *)context; + auto pResult = (RequestContext *)pContext->context; + + // Create Request UPIU structure + uint8_t reqType = pContext->transferReq[0] & 0x3F; + pContext->transferReqUPIU = getUPIU((UPIU_OPCODE)reqType); + pContext->transferReqUPIU->set(pContext->transferReq, + pContext->offUPIUResp); + + // debugprint(LOG_HIL_UFS, + // "COMMAND | UPIU Transfer Request | TT 0x%X", reqType); + + // Process + switch (reqType) { + case OPCODE_NOP_OUT: + pContext->transferRespUPIU = getUPIU(OPCODE_NOP_IN); + + done(now, context); + + break; + case OPCODE_QUERY_REQUEST: + pContext->transferRespUPIU = getUPIU(OPCODE_QUERY_RESPONSE); + pDevice->processQueryCommand( + (UPIUQueryReq *)pContext->transferReqUPIU, + (UPIUQueryResp *)pContext->transferRespUPIU); + + execute(CPU::UFS__DEVICE, CPU::PROCESS_QUERY_COMMAND, done, context); + + break; + case OPCODE_COMMAND: + pContext->transferRespUPIU = getUPIU(OPCODE_RESPONSE); + + { + CPUContext *pCPU = new CPUContext(done, context, CPU::UFS__DEVICE, + CPU::PROCESS_COMMAND); + + pDevice->processCommand( + pContext->cmd, (UPIUCommand *)pContext->transferReqUPIU, + (UPIUResponse *)pContext->transferRespUPIU, pContext->prdt, + pResult->transferReqDesc.prdtLength, cpuHandler, pCPU); + } + + break; + default: + panic("Unapplicable UPIU command type"); + + break; + } + }; + DMAFunction doReqRead = [doRequest](uint64_t now, void *context) { + auto pContext = (UTPCommandContext *)context; + + pContext->reqDone = true; + + if (pContext->prdtDone) { + doRequest(now, context); + } + }; + + commandContext->offUPIUResp = req.respUPIUOffset * 4; + commandContext->sizeUPIUResp = req.respUPIULength * 4; + commandContext->cmd = cmd; + + // Retrive UTP Command Descriptor + commandContext->base = ((uint64_t)req.cmdAddressUpper << 32) | req.cmdAddress; + commandContext->transferReq = + (uint8_t *)calloc(commandContext->offUPIUResp, 1); + commandContext->transferResp = + (uint8_t *)calloc(commandContext->sizeUPIUResp, 1); + + axiFIFO->dmaRead(commandContext->base, commandContext->offUPIUResp, + commandContext->transferReq, doReqRead, commandContext); + + if (req.prdtLength > 0) { + DMAFunction doPRDTRead = [doRequest](uint64_t now, void *context) { + auto pContext = (UTPCommandContext *)context; + + pContext->prdtDone = true; + + if (pContext->reqDone) { + doRequest(now, context); + } + }; + + commandContext->prdt = (uint8_t *)calloc(sizePRDT, 1); + + axiFIFO->dmaRead(commandContext->base + offPRDT, sizePRDT, + commandContext->prdt, doPRDTRead, commandContext); + } + else { + commandContext->prdtDone = true; + } +} + +UPIU *Host::getUPIU(UPIU_OPCODE code) { + switch (code) { + case OPCODE_COMMAND: + return new UPIUCommand(); + case OPCODE_DATA_OUT: + return new UPIUDataOut(); + case OPCODE_QUERY_REQUEST: + return new UPIUQueryReq(); + case OPCODE_RESPONSE: + return new UPIUResponse(); + case OPCODE_DATA_IN: + return new UPIUDataIn(); + case OPCODE_READY_TO_TRANSFER: + return new UPIUReadyToTransfer(); + case OPCODE_QUERY_RESPONSE: + return new UPIUQueryResp(); + default: + break; + } + + UPIU *ret = new UPIU(); + ret->header.transactionType = code; + + return ret; +} + +void Host::readRegister(uint32_t offset, uint32_t &data) { + for (uint32_t i = 0; i < 4; i++) { + if (offset + i < 0xB0) { + data |= register_table.data[offset + i] << (i * 8); + } + } + + // debugprint(LOG_HIL_UFS, + // "REG | READ | Offset 0x%02X | Data %08X", offset, + // data); +} + +void Host::writeRegister(uint32_t offset, uint32_t data, uint64_t tick) { + // debugprint(LOG_HIL_UFS, + // "REG | WRITE | Offset 0x%02X | Data %08X", offset, + // data); + + switch (offset) { + case REG_IS: + register_table.is &= (~data) & 0x00030FFF; + + pInterface->clearInterrupt(); + + break; + case REG_IE: + register_table.ie &= 0x00000FFF; + register_table.ie |= data & 0x00030FFF; // Spec differs with Linux kernel + + break; + case REG_HCS: + register_table.hcs &= (~data) & 0x00000030; + register_table.hcs |= data & 0x00000700; + + break; + case REG_HCE: + register_table.hce = data & 0x00000001; + + break; + case REG_UTRIACR: + register_table.utriacr = data & 0x81111FFF; + + break; + case REG_UTRLBA: + register_table.utrlba &= 0xFFFFFFFF00000000; + register_table.utrlba |= data & 0xFFFFFC00; + + break; + case REG_UTRLBAU: + register_table.utrlba &= 0xFFFFFFFF; + register_table.utrlba |= (uint64_t)data << 32; + + break; + case REG_UTRLDBR: + register_table.utrldbr |= data; + + processUTPTransfer(tick); + + break; + case REG_UTRLCLR: + register_table.utrlclr = data; + // TODO: abort command + + break; + case REG_UTRLRSR: + register_table.utrlrsr = data & 0x00000001; + + break; + case REG_UTMRLBA: + register_table.utmrlba &= 0xFFFFFFFF00000000; + register_table.utmrlba |= data & 0xFFFFFC00; + + break; + case REG_UTMRLBAU: + register_table.utmrlba &= 0xFFFFFFFF; + register_table.utmrlba |= (uint64_t)data << 32; + + break; + case REG_UTMRLDBR: + register_table.utmrldbr |= data; + + processUTPTask(); + + break; + case REG_UTMRLCLR: + register_table.utmrlclr = data; + // TODO: abort command + + break; + case REG_UTMRLRSR: + register_table.utmrlrsr = data & 0x00000001; + + break; + case REG_UICCMDR: + register_table.uiccmdr = data & 0x000000FF; + + processUIC(); + + break; + case REG_UCMDARG1: + register_table.ucmdarg1 = data; + + break; + case REG_UCMDARG2: + register_table.ucmdarg2 = data; + + break; + case REG_UCMDARG3: + register_table.ucmdarg3 = data; + + break; + default: + warn("Write to read only register 0x%X", offset); + + break; + } +} + +void Host::completion() { + uint32_t count = 0; + uint64_t tick = getTick(); + bool intr = false; + + while (lResponseQueue.size() > 0) { + auto &iter = lResponseQueue.top(); + + if (iter.finishedAt <= tick) { + intr = true; + + // Clear doorbell + register_table.utrldbr &= ~iter.bitmask; + pendingInterrupt &= ~iter.bitmask; + + // Remove entry + lResponseQueue.pop(); + count++; + } + else { + break; + } + } + + if (intr) { + debugprint(LOG_HIL_UFS, "INTR | Completing %u requests", count); + + // Set Interrupt Status + register_table.is |= UTP_TRANSFER_REQ_COMPL; + + // Post interrupt + pInterface->generateInterrupt(); + } + + // Schedule for next interrupt + if (lResponseQueue.size() > 0) { + schedule(completionEvent, lResponseQueue.top().finishedAt); + } +} + +void Host::work() { + lastWorkAt = getTick(); + + // Queue is already collected. Just call handleRequest + handleRequest(); +} + +void Host::handleRequest() { + uint64_t tick = getTick(); + + if (lRequestQueue.size() > 0) { + RequestContext *reqContext = new RequestContext(); + reqContext->index = lRequestQueue.front(); + reqContext->bitMask = 1 << reqContext->index; + + lRequestQueue.pop(); + + DMAFunction doRead = [this](uint64_t, void *context) { + DMAFunction doRequest = [this](uint64_t, void *context) { + DMAFunction doWrite = [this](uint64_t now, void *context) { + auto *pContext = (RequestContext *)context; + + // Schedule interrupt + lResponseQueue.push( + Completion(now, pContext->bitMask, + pContext->transferReqDesc.dw0 & 0x01000000)); + schedule(completionEvent, lResponseQueue.top().finishedAt); + + stat.utpCommand++; + + delete pContext; + }; + + auto *pContext = (RequestContext *)context; + + // Write result to descriptor (DW2) + uint64_t start = register_table.utrlba + + UTP_TRANSFER_REQ_DESC_SIZE * pContext->index; + + axiFIFO->dmaWrite(start, UTP_TRANSFER_REQ_DESC_SIZE, + pContext->transferReqDesc.data, doWrite, context); + }; + + auto *pContext = (RequestContext *)context; + + // Parse and process each commands + uint8_t ct = pContext->transferReqDesc.dw0 >> 28; + + debugprint(LOG_HIL_UFS, + "COMMAND | UTP Transfer Request | Entry %d | CT %d", + pContext->index, ct); + + switch (ct) { + case CMD_SCSI: + case CMD_NATIVE_UFS_COMMAND: + case CMD_DEVICE_MGMT_FUNCTION: + processUTPCommand(pContext->transferReqDesc, (UTP_TRANSFER_CMD)ct, + doRequest, context); + + break; + default: + panic("Undefined UTP Transfer command type %#x", ct); + + break; + } + }; + + // We have data at slot i + uint64_t start = + register_table.utrlba + UTP_TRANSFER_REQ_DESC_SIZE * reqContext->index; + + // Read description + axiFIFO->dmaRead(start, UTP_TRANSFER_REQ_DESC_SIZE, + reqContext->transferReqDesc.data, doRead, reqContext); + + requestCounter++; + } + + if (lRequestQueue.size() > 0 && requestCounter < maxRequest) { + schedule(requestEvent, tick + requestInterval); + } + else { + schedule(workEvent, MAX(tick + requestInterval, lastWorkAt + workInterval)); + } +} + +UFSHCIRegister &Host::getRegisterTable() { + return register_table; +} + +void Host::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "uic_count"; + temp.desc = "Total UIC Command handled"; + list.push_back(temp); + + temp.name = prefix + "utp_transfer_count"; + temp.desc = "Total UTP Transfer Command handled"; + list.push_back(temp); + + pDevice->getStatList(list, prefix); +} + +void Host::getStatValues(std::vector &values) { + values.push_back(stat.uicCommand); + values.push_back(stat.utpCommand); + + pDevice->getStatValues(values); +} + +void Host::resetStatValues() { + memset(&stat, 0, sizeof(stat)); + + pDevice->resetStatValues(); +} + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/host.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/host.hh new file mode 100644 index 0000000000..1e4c861564 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/host.hh @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_HOST__ +#define __HIL_UFS_HOST__ + +#include +#include +#include + +#include "hil/ufs/def.hh" +#include "hil/ufs/interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +class Device; + +typedef struct _Completion { + bool interruptEnable; + uint32_t bitmask; + uint64_t finishedAt; + + _Completion() : interruptEnable(false), bitmask(0), finishedAt(0) {} + + _Completion(uint64_t t, uint32_t b, bool i) + : interruptEnable(i), bitmask(b), finishedAt(t) {} + + bool operator()(const _Completion &a, const _Completion &b) { + return a.finishedAt > b.finishedAt; + } +} Completion; + +class Host : public StatObject { + private: + Interface *pInterface; + Device *pDevice; + + ConfigReader &conf; + + DMAInterface *axiFIFO; + DMAInterface *mphyFIFO; + DMAInterface *deviceFIFO; + + Event workEvent; + Event requestEvent; + Event completionEvent; + uint64_t workInterval; + uint64_t requestInterval; + uint64_t maxRequest; + uint64_t requestCounter; + uint64_t lastWorkAt; + + UFSHCIRegister register_table; + uint32_t pendingInterrupt; + + std::queue lRequestQueue; + std::priority_queue, Completion> + lResponseQueue; + + struct { + uint64_t uicCommand; + uint64_t utpCommand; + } stat; + + void processUIC(); + void processUTPTask(); + void processUTPTransfer(uint64_t); + + void processUTPCommand(UTPTransferReqDesc &, UTP_TRANSFER_CMD, DMAFunction &, + void * = nullptr); + + UPIU *getUPIU(UPIU_OPCODE); + + public: + Host(Interface *, ConfigReader &); + ~Host(); + + // For Interface + void readRegister(uint32_t, uint32_t &); + void writeRegister(uint32_t, uint32_t, uint64_t); + + void completion(); + void handleRequest(); + void work(); + + UFSHCIRegister &getRegisterTable(); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/interface.hh b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/interface.hh new file mode 100644 index 0000000000..a9d6531ae8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/hil/ufs/interface.hh @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __HIL_UFS_INTERFACE__ +#define __HIL_UFS_INTERFACE__ + +#include + +#include "sim/dma_interface.hh" + +namespace SimpleSSD { + +namespace HIL { + +namespace UFS { + +class Host; + +class Interface : public SimpleSSD::DMAInterface { + protected: + Host *pController; + + public: + virtual void generateInterrupt() = 0; + virtual void clearInterrupt() = 0; +}; + +} // namespace UFS + +} // namespace HIL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/abstract_cache.cc b/hotness/SimpleSSD-Standalone/simplessd/icl/abstract_cache.cc new file mode 100644 index 0000000000..c5047498f4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/abstract_cache.cc @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/abstract_cache.hh" + +namespace SimpleSSD { + +namespace ICL { + +Line::_Line() + : tag(0), lastAccessed(0), insertedAt(0), dirty(false), valid(false) {} + +Line::_Line(uint64_t t, bool d) + : tag(t), lastAccessed(0), insertedAt(0), dirty(d), valid(true) {} + +AbstractCache::AbstractCache(ConfigReader &c, FTL::FTL *f, + DRAM::AbstractDRAM *d) + : conf(c), pFTL(f), pDRAM(d) {} + +AbstractCache::~AbstractCache() {} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/abstract_cache.hh b/hotness/SimpleSSD-Standalone/simplessd/icl/abstract_cache.hh new file mode 100644 index 0000000000..31cd08935a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/abstract_cache.hh @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_CACHE__ +#define __ICL_CACHE__ + +#include "dram/abstract_dram.hh" +#include "ftl/ftl.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace ICL { + +typedef struct _Line { + uint64_t tag; + uint64_t lastAccessed; + uint64_t insertedAt; + bool dirty; + bool valid; + + _Line(); + _Line(uint64_t, bool); +} Line; + +class AbstractCache : public StatObject { + protected: + ConfigReader &conf; + FTL::FTL *pFTL; + DRAM::AbstractDRAM *pDRAM; + + public: + AbstractCache(ConfigReader &, FTL::FTL *, DRAM::AbstractDRAM *); + virtual ~AbstractCache(); + + virtual bool read(Request &, uint64_t &) = 0; + virtual bool write(Request &, uint64_t &) = 0; + + virtual void flush(LPNRange &, uint64_t &) = 0; + virtual void trim(LPNRange &, uint64_t &) = 0; + virtual void format(LPNRange &, uint64_t &) = 0; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/config.cc b/hotness/SimpleSSD-Standalone/simplessd/icl/config.cc new file mode 100644 index 0000000000..3f199acc97 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/config.cc @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/config.hh" + +#include "util/algorithm.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace ICL { + +const char NAME_USE_READ_CACHE[] = "EnableReadCache"; +const char NAME_USE_WRITE_CACHE[] = "EnableWriteCache"; +const char NAME_USE_READ_PREFETCH[] = "EnableReadPrefetch"; +const char NAME_EVICT_POLICY[] = "EvictPolicy"; +const char NAME_EVICT_MODE[] = "EvictMode"; +const char NAME_CACHE_SIZE[] = "CacheSize"; +const char NAME_WAY_SIZE[] = "CacheWaySize"; +const char NAME_PREFETCH_COUNT[] = "ReadPrefetchCount"; +const char NAME_PREFETCH_RATIO[] = "ReadPrefetchRatio"; +const char NAME_PREFETCH_MODE[] = "ReadPrefetchMode"; +const char NAME_CACHE_LATENCY[] = "CacheLatency"; + +Config::Config() { + readCaching = false; + writeCaching = true; + readPrefetch = false; + evictPolicy = POLICY_LEAST_RECENTLY_USED; + cacheSize = 33554432; + cacheWaySize = 1; + prefetchCount = 1; + prefetchRatio = 0.5; + prefetchMode = MODE_ALL; + evictMode = MODE_ALL; + cacheLatency = 10; +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_USE_READ_CACHE)) { + readCaching = convertBool(value); + } + else if (MATCH_NAME(NAME_USE_WRITE_CACHE)) { + writeCaching = convertBool(value); + } + else if (MATCH_NAME(NAME_USE_READ_PREFETCH)) { + readPrefetch = convertBool(value); + } + else if (MATCH_NAME(NAME_PREFETCH_COUNT)) { + prefetchCount = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PREFETCH_RATIO)) { + prefetchRatio = strtof(value, nullptr); + } + else if (MATCH_NAME(NAME_EVICT_POLICY)) { + evictPolicy = (EVICT_POLICY)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_EVICT_MODE)) { + evictMode = (EVICT_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CACHE_SIZE)) { + cacheSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_WAY_SIZE)) { + cacheWaySize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PREFETCH_MODE)) { + prefetchMode = (PREFETCH_MODE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_CACHE_LATENCY)) { + cacheLatency = strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (prefetchCount == 0) { + panic("Invalid ReadPrefetchCount"); + } + if (prefetchRatio <= 0.f) { + panic("Invalid ReadPrefetchRatio"); + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case ICL_EVICT_POLICY: + ret = evictPolicy; + break; + case ICL_PREFETCH_GRANULARITY: + ret = prefetchMode; + break; + case ICL_EVICT_GRANULARITY: + ret = evictMode; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case ICL_CACHE_SIZE: + ret = cacheSize; + break; + case ICL_WAY_SIZE: + ret = cacheWaySize; + break; + case ICL_PREFETCH_COUNT: + ret = prefetchCount; + break; + case ICL_CACHE_LATENCY: + ret = cacheLatency; + break; + } + + return ret; +} + +float Config::readFloat(uint32_t idx) { + float ret = 0.f; + + switch (idx) { + case ICL_PREFETCH_RATIO: + ret = prefetchRatio; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case ICL_USE_READ_CACHE: + ret = readCaching; + break; + case ICL_USE_WRITE_CACHE: + ret = writeCaching; + break; + case ICL_USE_READ_PREFETCH: + ret = readPrefetch; + break; + } + + return ret; +} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/config.hh b/hotness/SimpleSSD-Standalone/simplessd/icl/config.hh new file mode 100644 index 0000000000..7ff581310f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/config.hh @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_CONFIG__ +#define __ICL_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace ICL { + +typedef enum { + /* Cache config */ + ICL_USE_READ_CACHE, + ICL_USE_WRITE_CACHE, + ICL_USE_READ_PREFETCH, + ICL_PREFETCH_COUNT, + ICL_PREFETCH_RATIO, + ICL_PREFETCH_GRANULARITY, + ICL_EVICT_POLICY, + ICL_EVICT_GRANULARITY, + ICL_CACHE_SIZE, + ICL_WAY_SIZE, + ICL_CACHE_LATENCY, +} ICL_CONFIG; + +typedef enum { + POLICY_RANDOM, //!< Select way in random + POLICY_FIFO, //!< Select way that lastly inserted + POLICY_LEAST_RECENTLY_USED, //!< Select way that least recently used +} EVICT_POLICY; + +typedef enum { + MODE_SUPERPAGE, //!< Read one page from one super block (super page) + MODE_ALL, //!< Read one page from all NAND flashes +} PREFETCH_MODE; + +typedef PREFETCH_MODE EVICT_MODE; + +class Config : public BaseConfig { + private: + bool readCaching; //!< Default: false + bool writeCaching; //!< Default: true + bool readPrefetch; //!< Default: false + EVICT_POLICY evictPolicy; //!< Default: POLICY_LEAST_RECENTLY_USED + uint64_t cacheWaySize; //!< Default: 1 + uint64_t cacheSize; //!< Default: 33554432 (32MiB) + uint64_t prefetchCount; //!< Default: 1 + float prefetchRatio; //!< Default: 0.5 + PREFETCH_MODE prefetchMode; //!< Default: MODE_ALL + EVICT_MODE evictMode; //!< Default: MODE_ALL + uint64_t cacheLatency; //!< Default: + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + float readFloat(uint32_t) override; + bool readBoolean(uint32_t) override; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/generic_cache.cc b/hotness/SimpleSSD-Standalone/simplessd/icl/generic_cache.cc new file mode 100644 index 0000000000..869b04c9ef --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/generic_cache.cc @@ -0,0 +1,925 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/generic_cache.hh" + +#include +#include +#include + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace ICL { + static GenericCache* g_last_generic_cache = nullptr; // 내부 저장소 + GenericCache* getLastGenericCache() { // ★ 자유 함수 정의 + return g_last_generic_cache; + } + +GenericCache::GenericCache(ConfigReader &c, FTL::FTL *f, DRAM::AbstractDRAM *d) + : AbstractCache(c, f, d), + superPageSize(f->getInfo()->pageSize), + parallelIO(f->getInfo()->pageCountToMaxPerf), + lineCountInSuperPage(f->getInfo()->ioUnitInPage), + lineCountInMaxIO(parallelIO * lineCountInSuperPage), + waySize(conf.readUint(CONFIG_ICL, ICL_WAY_SIZE)), + prefetchIOCount(conf.readUint(CONFIG_ICL, ICL_PREFETCH_COUNT)), + prefetchIORatio(conf.readFloat(CONFIG_ICL, ICL_PREFETCH_RATIO)), + useReadCaching(conf.readBoolean(CONFIG_ICL, ICL_USE_READ_CACHE)), + useWriteCaching(conf.readBoolean(CONFIG_ICL, ICL_USE_WRITE_CACHE)), + useReadPrefetch(conf.readBoolean(CONFIG_ICL, ICL_USE_READ_PREFETCH)), + gen(rd()), + dist(std::uniform_int_distribution(0, waySize - 1)) { + uint64_t cacheSize = conf.readUint(CONFIG_ICL, ICL_CACHE_SIZE); + + lineSize = superPageSize / lineCountInSuperPage; + + if (lineSize != superPageSize) { + bSuperPage = true; + } + + if (!conf.readBoolean(CONFIG_FTL, FTL::FTL_USE_RANDOM_IO_TWEAK)) { + lineSize = superPageSize; + lineCountInSuperPage = 1; + lineCountInMaxIO = parallelIO; + } + + if (!useReadCaching && !useWriteCaching) { + return; + } + + // Fully-associated? + if (waySize == 0) { + setSize = 1; + waySize = MAX(cacheSize / lineSize, 1); + } + else { + setSize = MAX(cacheSize / lineSize / waySize, 1); + } + + debugprint( + LOG_ICL_GENERIC_CACHE, + "CREATE | Set size %u | Way size %u | Line size %u | Capacity %" PRIu64, + setSize, waySize, lineSize, (uint64_t)setSize * waySize * lineSize); + debugprint(LOG_ICL_GENERIC_CACHE, + "CREATE | line count in super page %u | line count in max I/O %u", + lineCountInSuperPage, lineCountInMaxIO); + + cacheData.resize(setSize); + + for (uint32_t i = 0; i < setSize; i++) { + cacheData[i] = new Line[waySize](); + } + + evictData.resize(lineCountInSuperPage); + + for (uint32_t i = 0; i < lineCountInSuperPage; i++) { + evictData[i] = (Line **)calloc(parallelIO, sizeof(Line *)); + } + + prefetchTrigger = std::numeric_limits::max(); + + evictMode = (EVICT_MODE)conf.readInt(CONFIG_ICL, ICL_EVICT_GRANULARITY); + prefetchMode = + (PREFETCH_MODE)conf.readInt(CONFIG_ICL, ICL_PREFETCH_GRANULARITY); + + // Set evict policy functional + policy = (EVICT_POLICY)conf.readInt(CONFIG_ICL, ICL_EVICT_POLICY); + + switch (policy) { + case POLICY_RANDOM: + evictFunction = [this](uint32_t, uint64_t &) -> uint32_t { + return dist(gen); + }; + compareFunction = [this](Line *a, Line *b) -> Line * { + if (a && b) { + return dist(gen) > waySize / 2 ? a : b; + } + else if (a || b) { + return a ? a : b; + } + else { + return nullptr; + } + }; + + break; + case POLICY_FIFO: + evictFunction = [this](uint32_t setIdx, uint64_t &tick) -> uint32_t { + uint32_t wayIdx = 0; + uint64_t min = std::numeric_limits::max(); + + for (uint32_t i = 0; i < waySize; i++) { + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, i, offsetof(Line, insertedAt)), + // 8, tick); + + if (cacheData[setIdx][i].insertedAt < min) { + min = cacheData[setIdx][i].insertedAt; + wayIdx = i; + } + } + + return wayIdx; + }; + compareFunction = [](Line *a, Line *b) -> Line * { + if (a && b) { + if (a->insertedAt < b->insertedAt) { + return a; + } + else { + return b; + } + } + else if (a || b) { + return a ? a : b; + } + else { + return nullptr; + } + }; + + break; + case POLICY_LEAST_RECENTLY_USED: + evictFunction = [this](uint32_t setIdx, uint64_t &tick) -> uint32_t { + uint32_t wayIdx = 0; + uint64_t min = std::numeric_limits::max(); + + for (uint32_t i = 0; i < waySize; i++) { + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, i, offsetof(Line, + // lastAccessed)), 8, tick); + + if (cacheData[setIdx][i].lastAccessed < min) { + min = cacheData[setIdx][i].lastAccessed; + wayIdx = i; + } + } + + return wayIdx; + }; + compareFunction = [](Line *a, Line *b) -> Line * { + if (a && b) { + if (a->lastAccessed < b->lastAccessed) { + return a; + } + else { + return b; + } + } + else if (a || b) { + return a ? a : b; + } + else { + return nullptr; + } + }; + + break; + default: + panic("Undefined cache evict policy"); + + break; + } + g_last_generic_cache = this; + memset(&stat, 0, sizeof(stat)); +} + +GenericCache::~GenericCache() { + if (!useReadCaching && !useWriteCaching) { + return; + } + + for (uint32_t i = 0; i < setSize; i++) { + delete[] cacheData[i]; + } + + for (uint32_t i = 0; i < lineCountInSuperPage; i++) { + free(evictData[i]); + } + + if (g_last_generic_cache == this) // ★ 안전하게 해제 + g_last_generic_cache = nullptr; +} + +uint64_t GenericCache::getCacheLatency() { + static uint64_t latency = conf.readUint(CONFIG_ICL, ICL_CACHE_LATENCY); + static uint64_t core = conf.readUint(CONFIG_CPU, CPU::CPU_CORE_ICL); + + return (core == 0) ? 0 : latency / core; +} + +uint32_t GenericCache::calcSetIndex(uint64_t lca) { + return lca % setSize; +} + +void GenericCache::calcIOPosition(uint64_t lca, uint32_t &row, uint32_t &col) { + uint32_t tmp = lca % lineCountInMaxIO; + + row = tmp % lineCountInSuperPage; + col = tmp / lineCountInSuperPage; +} + +uint32_t GenericCache::getEmptyWay(uint32_t setIdx, uint64_t &tick) { + uint32_t retIdx = waySize; + uint64_t minInsertedAt = std::numeric_limits::max(); + + for (uint32_t wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + if (!line.valid) { + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, wayIdx, offsetof(Line, insertedAt)), + // 8, tick); + + if (minInsertedAt > line.insertedAt) { + minInsertedAt = line.insertedAt; + retIdx = wayIdx; + } + } + } + + return retIdx; +} + +uint32_t GenericCache::getValidWay(uint64_t lca, uint64_t &tick) { + uint32_t setIdx = calcSetIndex(lca); + uint32_t wayIdx; + + for (wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + tick += getCacheLatency() * 8; + // pDRAM->read(MAKE_META_ADDR(setIdx, wayIdx, offsetof(Line, tag)), 8, + // tick); + + if (line.valid && line.tag == lca) { + break; + } + } + + return wayIdx; +} + +void GenericCache::checkSequential(Request &req, SequentialDetect &data) { + if (data.lastRequest.reqID == req.reqID) { + data.lastRequest.range = req.range; + data.lastRequest.offset = req.offset; + data.lastRequest.length = req.length; + + return; + } + + if (data.lastRequest.range.slpn * lineSize + data.lastRequest.offset + + data.lastRequest.length == + req.range.slpn * lineSize + req.offset) { + if (!data.enabled) { + data.hitCounter++; + data.accessCounter += data.lastRequest.offset + data.lastRequest.length; + + if (data.hitCounter >= prefetchIOCount && + (float)data.accessCounter / superPageSize >= prefetchIORatio) { + data.enabled = true; + } + } + } + else { + data.enabled = false; + data.hitCounter = 0; + data.accessCounter = 0; + } + + data.lastRequest = req; +} + +void GenericCache::evictCache(uint64_t tick, bool flush) { + FTL::Request reqInternal(lineCountInSuperPage); + reqInternal.temperature = 0; + + uint64_t beginAt; + uint64_t finishedAt = tick; + + debugprint(LOG_ICL_GENERIC_CACHE, "----- | Begin eviction"); + + for (uint32_t row = 0; row < lineCountInSuperPage; row++) { + for (uint32_t col = 0; col < parallelIO; col++) { + beginAt = tick; + + if (evictData[row][col] == nullptr) { + continue; + } + + if (evictData[row][col]->valid && evictData[row][col]->dirty) { + reqInternal.lpn = evictData[row][col]->tag / lineCountInSuperPage; + reqInternal.ioFlag.reset(); + reqInternal.ioFlag.set(row); + + // 1) 캐시 메타에 저장돼 있으면 그것을 복원 + auto it = lineTemp.find(evictData[row][col]); + if (it != lineTemp.end()) { + reqInternal.temperature = it->second; + } + + pFTL->write(reqInternal, beginAt); + //추가 + lineTemp.erase(evictData[row][col]); + } + + if (flush) { + evictData[row][col]->valid = false; + evictData[row][col]->tag = 0; + } + + evictData[row][col]->insertedAt = beginAt; + evictData[row][col]->lastAccessed = beginAt; + evictData[row][col]->dirty = false; + evictData[row][col] = nullptr; + + finishedAt = MAX(finishedAt, beginAt); + } + } + + debugprint(LOG_ICL_GENERIC_CACHE, + "----- | End eviction | %" PRIu64 " - %" PRIu64 " (%" PRIu64 ")", + tick, finishedAt, finishedAt - tick); +} + +// True when hit +bool GenericCache::read(Request &req, uint64_t &tick) { + bool ret = false; + + debugprint(LOG_ICL_GENERIC_CACHE, + "READ | REQ %7u-%-4u | LCA %" PRIu64 " | SIZE %" PRIu64, + req.reqID, req.reqSubID, req.range.slpn, req.length); + + if (useReadCaching) { + uint32_t setIdx = calcSetIndex(req.range.slpn); + uint32_t wayIdx; + uint64_t arrived = tick; + + if (useReadPrefetch) { + checkSequential(req, readDetect); + } + + wayIdx = getValidWay(req.range.slpn, tick); + + // Do we have valid data? + if (wayIdx != waySize) { + uint64_t tickBackup = tick; + + // Wait cache to be valid + if (tick < cacheData[setIdx][wayIdx].insertedAt) { + tick = cacheData[setIdx][wayIdx].insertedAt; + } + + // Update last accessed time + cacheData[setIdx][wayIdx].lastAccessed = tick; + + // DRAM access + pDRAM->read(&cacheData[setIdx][wayIdx], req.length, tick); + + debugprint(LOG_ICL_GENERIC_CACHE, + "READ | Cache hit at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + setIdx, wayIdx, arrived, tick, tick - arrived); + + ret = true; + + // Do we need to prefetch data? + if (useReadPrefetch && req.range.slpn == prefetchTrigger) { + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Prefetch triggered"); + + req.range.slpn = lastPrefetched; + + // Backup tick + arrived = tick; + tick = tickBackup; + + goto ICL_GENERIC_CACHE_READ; + } + } + // We should read data from NVM + else { + ICL_GENERIC_CACHE_READ: + FTL::Request reqInternal(lineCountInSuperPage, req); + std::vector> readList; + uint32_t row, col; // Variable for I/O position (IOFlag) + uint64_t dramAt; + uint64_t beginLCA, endLCA; + uint64_t beginAt, finishedAt = tick; + + if (readDetect.enabled) { + // TEMP: Disable DRAM calculation for prevent conflict + pDRAM->setScheduling(false); + + if (!ret) { + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Read ahead triggered"); + } + + beginLCA = req.range.slpn; + + // If super-page is disabled, just read all pages from all planes + if (prefetchMode == MODE_ALL || !bSuperPage) { + endLCA = beginLCA + lineCountInMaxIO; + prefetchTrigger = beginLCA + lineCountInMaxIO / 2; + } + else { + endLCA = beginLCA + lineCountInSuperPage; + prefetchTrigger = beginLCA + lineCountInSuperPage / 2; + } + + lastPrefetched = endLCA; + } + else { + beginLCA = req.range.slpn; + endLCA = beginLCA + 1; + } + + for (uint64_t lca = beginLCA; lca < endLCA; lca++) { + beginAt = tick; + + // Check cache + if (getValidWay(lca, beginAt) != waySize) { + continue; + } + + // Find way to write data read from NVM + setIdx = calcSetIndex(lca); + wayIdx = getEmptyWay(setIdx, beginAt); + + if (wayIdx == waySize) { + wayIdx = evictFunction(setIdx, beginAt); + + if (cacheData[setIdx][wayIdx].dirty) { + // We need to evict data before write + calcIOPosition(cacheData[setIdx][wayIdx].tag, row, col); + evictData[row][col] = cacheData[setIdx] + wayIdx; + } + } + + cacheData[setIdx][wayIdx].insertedAt = beginAt; + cacheData[setIdx][wayIdx].lastAccessed = beginAt; + cacheData[setIdx][wayIdx].valid = true; + cacheData[setIdx][wayIdx].dirty = false; + + readList.push_back({lca, ((uint64_t)setIdx << 32) | wayIdx}); + + finishedAt = MAX(finishedAt, beginAt); + } + + tick = finishedAt; + + evictCache(tick); + + for (auto &iter : readList) { + Line *pLine = &cacheData[iter.second >> 32][iter.second & 0xFFFFFFFF]; + + // Read data + reqInternal.lpn = iter.first / lineCountInSuperPage; + reqInternal.ioFlag.reset(); + reqInternal.ioFlag.set(iter.first % lineCountInSuperPage); + + beginAt = tick; // Ignore cache metadata access + + // If superPageSizeData is true, read first LPN only + pFTL->read(reqInternal, beginAt); + + // DRAM delay + dramAt = pLine->insertedAt; + pDRAM->write(pLine, lineSize, dramAt); + + // Set cache data + beginAt = MAX(beginAt, dramAt); + + pLine->insertedAt = beginAt; + pLine->lastAccessed = beginAt; + pLine->tag = iter.first; + + if (pLine->tag == req.range.slpn) { + finishedAt = beginAt; + } + + debugprint(LOG_ICL_GENERIC_CACHE, + "READ | Cache miss at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + iter.second >> 32, iter.second & 0xFFFFFFFF, tick, beginAt, + beginAt - tick); + } + + tick = finishedAt; + + if (readDetect.enabled) { + if (ret) { + // This request was prefetch + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Prefetch done"); + + // Restore tick + tick = arrived; + } + else { + debugprint(LOG_ICL_GENERIC_CACHE, "READ | Read ahead done"); + } + + // TEMP: Restore + pDRAM->setScheduling(true); + } + } + + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::READ); + } + else { + FTL::Request reqInternal(lineCountInSuperPage, req); + + pDRAM->write(nullptr, req.length, tick); + + pFTL->read(reqInternal, tick); + } + + stat.request[0]++; + + if (ret) { + stat.cache[0]++; + } + + return ret; +} + +// True when cold-miss/hit +bool GenericCache::write(Request &req, uint64_t &tick) { + bool ret = false; + uint64_t flash = tick; + bool dirty = false; + + debugprint(LOG_ICL_GENERIC_CACHE, + "WRITE | REQ %7u-%-4u | LCA %" PRIu64 " | SIZE %" PRIu64, + req.reqID, req.reqSubID, req.range.slpn, req.length); + + FTL::Request reqInternal(lineCountInSuperPage, req); + + if (req.length < lineSize) { + dirty = true; + } + else { + pFTL->write(reqInternal, flash); + } + + if (useWriteCaching) { + uint32_t setIdx = calcSetIndex(req.range.slpn); + uint32_t wayIdx; + + wayIdx = getValidWay(req.range.slpn, tick); + + // Can we update old data? + if (wayIdx != waySize) { + uint64_t arrived = tick; + + // Wait cache to be valid + if (tick < cacheData[setIdx][wayIdx].insertedAt) { + tick = cacheData[setIdx][wayIdx].insertedAt; + } + + // TODO: TEMPORAL CODE + // We should only show DRAM latency when cache become dirty + if (dirty) { + // Update last accessed time + cacheData[setIdx][wayIdx].insertedAt = tick; + cacheData[setIdx][wayIdx].lastAccessed = tick; + } + else { + cacheData[setIdx][wayIdx].insertedAt = flash; + cacheData[setIdx][wayIdx].lastAccessed = flash; + } + + // Update last accessed time + cacheData[setIdx][wayIdx].dirty = dirty; + + // Update last accessed time, 추가함 + if (dirty) { + lineTemp[&cacheData[setIdx][wayIdx]] = (uint8_t)req.temperature; + } else { + lineTemp.erase(&cacheData[setIdx][wayIdx]); + } + + // DRAM access + pDRAM->write(&cacheData[setIdx][wayIdx], req.length, tick); + + debugprint(LOG_ICL_GENERIC_CACHE, + "WRITE | Cache hit at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + setIdx, wayIdx, arrived, tick, tick - arrived); + + ret = true; + } + else { + uint64_t arrived = tick; + + wayIdx = getEmptyWay(setIdx, tick); + + // Do we have place to write data? + if (wayIdx != waySize) { + // Wait cache to be valid + if (tick < cacheData[setIdx][wayIdx].insertedAt) { + tick = cacheData[setIdx][wayIdx].insertedAt; + } + + // TODO: TEMPORAL CODE + // We should only show DRAM latency when cache become dirty + if (dirty) { + // Update last accessed time + cacheData[setIdx][wayIdx].insertedAt = tick; + cacheData[setIdx][wayIdx].lastAccessed = tick; + } + else { + cacheData[setIdx][wayIdx].insertedAt = flash; + cacheData[setIdx][wayIdx].lastAccessed = flash; + } + + // Update last accessed time + cacheData[setIdx][wayIdx].valid = true; + cacheData[setIdx][wayIdx].dirty = dirty; + cacheData[setIdx][wayIdx].tag = req.range.slpn; + lineTemp[&cacheData[setIdx][wayIdx]] = (uint8_t)req.temperature; + + //추가 + if (dirty) { + lineTemp[&cacheData[setIdx][wayIdx]] = (uint8_t)req.temperature; + } else { + lineTemp.erase(&cacheData[setIdx][wayIdx]); + } + // DRAM access + pDRAM->write(&cacheData[setIdx][wayIdx], req.length, tick); + + ret = true; + } + // We have to flush + else { + uint32_t row, col; // Variable for I/O position (IOFlag) + uint32_t setToFlush = calcSetIndex(req.range.slpn); + + for (setIdx = 0; setIdx < setSize; setIdx++) { + for (wayIdx = 0; wayIdx < waySize; wayIdx++) { + if (cacheData[setIdx][wayIdx].valid) { + calcIOPosition(cacheData[setIdx][wayIdx].tag, row, col); + + evictData[row][col] = compareFunction(evictData[row][col], + cacheData[setIdx] + wayIdx); + } + } + } + + if (evictMode == MODE_SUPERPAGE) { + uint32_t row, col; // Variable for I/O position (IOFlag) + + for (row = 0; row < lineCountInSuperPage; row++) { + for (col = 0; col < parallelIO - 1; col++) { + evictData[row][col + 1] = + compareFunction(evictData[row][col], evictData[row][col + 1]); + evictData[row][col] = nullptr; + } + } + } + + // We must flush setToFlush set + bool have = false; + + for (row = 0; row < lineCountInSuperPage; row++) { + for (col = 0; col < parallelIO; col++) { + if (evictData[row][col] && + calcSetIndex(evictData[row][col]->tag) == setToFlush) { + have = true; + } + } + } + + // We don't have setToFlush + if (!have) { + Line *pLineToFlush = nullptr; + + for (wayIdx = 0; wayIdx < waySize; wayIdx++) { + if (cacheData[setToFlush][wayIdx].valid) { + pLineToFlush = + compareFunction(pLineToFlush, cacheData[setToFlush] + wayIdx); + } + } + + if (pLineToFlush) { + calcIOPosition(pLineToFlush->tag, row, col); + + evictData[row][col] = pLineToFlush; + } + } + + tick += getCacheLatency() * setSize * waySize * 8; + + evictCache(tick, true); + + // Update cacheline of current request + setIdx = setToFlush; + wayIdx = getEmptyWay(setIdx, tick); + + if (wayIdx == waySize) { + panic("Cache corrupted!"); + } + + // DRAM latency + pDRAM->write(&cacheData[setIdx][wayIdx], req.length, tick); + + // Update cache data + cacheData[setIdx][wayIdx].insertedAt = tick; + cacheData[setIdx][wayIdx].lastAccessed = tick; + cacheData[setIdx][wayIdx].valid = true; + cacheData[setIdx][wayIdx].dirty = true; + cacheData[setIdx][wayIdx].tag = req.range.slpn; + } + + debugprint(LOG_ICL_GENERIC_CACHE, + "WRITE | Cache miss at (%u, %u) | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + setIdx, wayIdx, arrived, tick, tick - arrived); + } + + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::WRITE); + } + else { + if (dirty) { + pFTL->write(reqInternal, tick); + } + else { + tick = flash; + } + + // TEMP: Disable DRAM calculation for prevent conflict + pDRAM->setScheduling(false); + + pDRAM->read(nullptr, req.length, tick); + + pDRAM->setScheduling(true); + } + + stat.request[1]++; + + if (ret) { + stat.cache[1]++; + } + + return ret; +} + +// True when flushed +void GenericCache::flush(LPNRange &range, uint64_t &tick) { + if (useReadCaching || useWriteCaching) { + uint64_t ftlTick = tick; + uint64_t finishedAt = tick; + FTL::Request reqInternal(lineCountInSuperPage); + + for (uint32_t setIdx = 0; setIdx < setSize; setIdx++) { + for (uint32_t wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + tick += getCacheLatency() * 8; + + if (line.tag >= range.slpn && line.tag < range.slpn + range.nlp) { + if (line.dirty) { + reqInternal.ioFlag.reset(); + reqInternal.lpn = line.tag / lineCountInSuperPage; + reqInternal.ioFlag.set(line.tag % lineCountInSuperPage); + + //추가 + auto it = lineTemp.find(&line); + if (it != lineTemp.end()) { + reqInternal.temperature = it->second; + } + + ftlTick = tick; + + pFTL->write(reqInternal, ftlTick); + finishedAt = MAX(finishedAt, ftlTick); + } + + line.valid = false; + lineTemp.erase(&line); + } + } + } + + tick = MAX(tick, finishedAt); + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::FLUSH); + } +} + +// True when hit +void GenericCache::trim(LPNRange &range, uint64_t &tick) { + if (useReadCaching || useWriteCaching) { + uint64_t ftlTick = tick; + uint64_t finishedAt = tick; + FTL::Request reqInternal(lineCountInSuperPage); + + for (uint32_t setIdx = 0; setIdx < setSize; setIdx++) { + for (uint32_t wayIdx = 0; wayIdx < waySize; wayIdx++) { + Line &line = cacheData[setIdx][wayIdx]; + + tick += getCacheLatency() * 8; + + if (line.tag >= range.slpn && line.tag < range.slpn + range.nlp) { + reqInternal.lpn = line.tag / lineCountInSuperPage; + reqInternal.ioFlag.reset(); + reqInternal.ioFlag.set(line.tag % lineCountInSuperPage); + + ftlTick = tick; + pFTL->trim(reqInternal, ftlTick); + finishedAt = MAX(finishedAt, ftlTick); + + line.valid = false; + } + } + } + + tick = MAX(tick, finishedAt); + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::TRIM); + } +} + +void GenericCache::format(LPNRange &range, uint64_t &tick) { + if (useReadCaching || useWriteCaching) { + uint64_t lpn; + uint32_t setIdx; + uint32_t wayIdx; + + for (uint64_t i = 0; i < range.nlp; i++) { + lpn = range.slpn + i; + setIdx = calcSetIndex(lpn); + wayIdx = getValidWay(lpn, tick); + + if (wayIdx != waySize) { + // Invalidate + lineTemp.erase(&cacheData[setIdx][wayIdx]); + cacheData[setIdx][wayIdx].valid = false; + } + } + } + + // Convert unit + range.slpn /= lineCountInSuperPage; + range.nlp = (range.nlp - 1) / lineCountInSuperPage + 1; + + pFTL->format(range, tick); + tick += applyLatency(CPU::ICL__GENERIC_CACHE, CPU::FORMAT); +} + +void GenericCache::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "generic_cache.read.request_count"; + temp.desc = "Read request count"; + list.push_back(temp); + + temp.name = prefix + "generic_cache.read.from_cache"; + temp.desc = "Read requests that served from cache"; + list.push_back(temp); + + temp.name = prefix + "generic_cache.write.request_count"; + temp.desc = "Write request count"; + list.push_back(temp); + + temp.name = prefix + "generic_cache.write.to_cache"; + temp.desc = "Write requests that served to cache"; + list.push_back(temp); +} + +void GenericCache::getStatValues(std::vector &values) { + values.push_back(stat.request[0]); + values.push_back(stat.cache[0]); + values.push_back(stat.request[1]); + values.push_back(stat.cache[1]); +} + +void GenericCache::resetStatValues() { + memset(&stat, 0, sizeof(stat)); +} + +void GenericCache::flushAll(uint64_t &tick) { + if (!(useReadCaching || useWriteCaching)) return; + LPNRange all{0, std::numeric_limits::max()}; + flush(all, tick); +} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/generic_cache.hh b/hotness/SimpleSSD-Standalone/simplessd/icl/generic_cache.hh new file mode 100644 index 0000000000..134e724bb6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/generic_cache.hh @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_GENERIC_CACHE__ +#define __ICL_GENERIC_CACHE__ + +#include +#include +#include +#include +#include "icl/abstract_cache.hh" + +namespace SimpleSSD { + +namespace ICL { +class GenericCache : public AbstractCache { + private: + const uint32_t superPageSize; + const uint32_t parallelIO; + uint32_t lineCountInSuperPage; + uint32_t lineCountInMaxIO; + uint32_t lineSize; + uint32_t setSize; + uint32_t waySize; + + const uint32_t prefetchIOCount; + const float prefetchIORatio; + + const bool useReadCaching; + const bool useWriteCaching; + const bool useReadPrefetch; + + bool bSuperPage; + + struct SequentialDetect { + bool enabled; + Request lastRequest; + uint32_t hitCounter; + uint32_t accessCounter; + + SequentialDetect() : enabled(false), hitCounter(0), accessCounter(0) { + lastRequest.reqID = 1; + } + } readDetect; + + uint64_t prefetchTrigger; + uint64_t lastPrefetched; + + PREFETCH_MODE prefetchMode; + EVICT_MODE evictMode; + EVICT_POLICY policy; + std::function evictFunction; + std::function compareFunction; + std::random_device rd; + std::mt19937 gen; + std::uniform_int_distribution dist; + + std::vector cacheData; + std::vector evictData; + std::unordered_map lineTemp; + + uint64_t getCacheLatency(); + + uint32_t calcSetIndex(uint64_t); + void calcIOPosition(uint64_t, uint32_t &, uint32_t &); + + uint32_t getEmptyWay(uint32_t, uint64_t &); + uint32_t getValidWay(uint64_t, uint64_t &); + void checkSequential(Request &, SequentialDetect &); + + void evictCache(uint64_t, bool = true); + + // Stats + struct { + uint64_t request[2]; + uint64_t cache[2]; + } stat; + + public: + GenericCache(ConfigReader &, FTL::FTL *, DRAM::AbstractDRAM *); + ~GenericCache(); + + bool read(Request &, uint64_t &) override; + bool write(Request &, uint64_t &) override; + + void flush(LPNRange &, uint64_t &) override; + void trim(LPNRange &, uint64_t &) override; + void format(LPNRange &, uint64_t &) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; + // public: + void flushAll(uint64_t &tick); + +}; + +GenericCache* getLastGenericCache(); +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/icl.cc b/hotness/SimpleSSD-Standalone/simplessd/icl/icl.cc new file mode 100644 index 0000000000..43c7810ddc --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/icl.cc @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "icl/icl.hh" + +#include "dram/simple.hh" +#include "icl/generic_cache.hh" +#include "util/algorithm.hh" +#include "util/def.hh" + +namespace SimpleSSD { + +namespace ICL { + +ICL::ICL(ConfigReader &c) : conf(c) { + switch (conf.readInt(CONFIG_DRAM, DRAM::DRAM_MODEL)) { + case DRAM::SIMPLE_MODEL: + pDRAM = new DRAM::SimpleDRAM(conf); + + break; + default: + panic("Undefined DRAM model"); + + break; + } + + pFTL = new FTL::FTL(conf, pDRAM); + + FTL::Parameter *param = pFTL->getInfo(); + + if (conf.readBoolean(CONFIG_FTL, FTL::FTL_USE_RANDOM_IO_TWEAK)) { + totalLogicalPages = + param->totalLogicalBlocks * param->pagesInBlock * param->ioUnitInPage; + logicalPageSize = param->pageSize / param->ioUnitInPage; + } + else { + totalLogicalPages = param->totalLogicalBlocks * param->pagesInBlock; + logicalPageSize = param->pageSize; + } + + pCache = new GenericCache(conf, pFTL, pDRAM); +} + +ICL::~ICL() { + delete pCache; + delete pFTL; + delete pDRAM; +} + +void ICL::read(Request &req, uint64_t &tick) { + uint64_t beginAt; + uint64_t finishedAt = tick; + uint64_t reqRemain = req.length; + Request reqInternal; + + reqInternal.reqID = req.reqID; + reqInternal.offset = req.offset; + + for (uint64_t i = 0; i < req.range.nlp; i++) { + beginAt = tick; + + reqInternal.reqSubID = i + 1; + reqInternal.range.slpn = req.range.slpn + i; + reqInternal.length = MIN(reqRemain, logicalPageSize - reqInternal.offset); + pCache->read(reqInternal, beginAt); + reqRemain -= reqInternal.length; + reqInternal.offset = 0; + + finishedAt = MAX(finishedAt, beginAt); + } + + debugprint(LOG_ICL, + "READ | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + req.range.slpn, req.range.nlp, tick, finishedAt, + finishedAt - tick); + + tick = finishedAt; + tick += applyLatency(CPU::ICL, CPU::READ); +} + +void ICL::write(Request &req, uint64_t &tick) { + uint64_t beginAt; + uint64_t finishedAt = tick; + uint64_t reqRemain = req.length; + Request reqInternal; + + reqInternal.reqID = req.reqID; + reqInternal.offset = req.offset; + reqInternal.temperature = req.temperature; + + + for (uint64_t i = 0; i < req.range.nlp; i++) { + beginAt = tick; + + reqInternal.reqSubID = i + 1; + reqInternal.range.slpn = req.range.slpn + i; + reqInternal.length = MIN(reqRemain, logicalPageSize - reqInternal.offset); + pCache->write(reqInternal, beginAt); + reqRemain -= reqInternal.length; + reqInternal.offset = 0; + + finishedAt = MAX(finishedAt, beginAt); + } + + debugprint(LOG_ICL, + "WRITE | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + req.range.slpn, req.range.nlp, tick, finishedAt, + finishedAt - tick); + + tick = finishedAt; + tick += applyLatency(CPU::ICL, CPU::WRITE); +} + +void ICL::flush(LPNRange &range, uint64_t &tick) { + uint64_t beginAt = tick; + + pCache->flush(range, tick); + + debugprint(LOG_ICL, + "FLUSH | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + range.slpn, range.nlp, beginAt, tick, tick - beginAt); + + tick += applyLatency(CPU::ICL, CPU::FLUSH); +} + +void ICL::trim(LPNRange &range, uint64_t &tick) { + uint64_t beginAt = tick; + + pCache->trim(range, tick); + + debugprint(LOG_ICL, + "TRIM | LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + range.slpn, range.nlp, beginAt, tick, tick - beginAt); + + tick += applyLatency(CPU::ICL, CPU::TRIM); +} + +void ICL::format(LPNRange &range, uint64_t &tick) { + uint64_t beginAt = tick; + + pCache->format(range, tick); + + debugprint(LOG_ICL, + "FORMAT| LCA %" PRIu64 " + %" PRIu64 " | %" PRIu64 " - %" PRIu64 + " (%" PRIu64 ")", + range.slpn, range.nlp, beginAt, tick, tick - beginAt); + + tick += applyLatency(CPU::ICL, CPU::FORMAT); +} + +void ICL::getLPNInfo(uint64_t &t, uint32_t &s) { + t = totalLogicalPages; + s = logicalPageSize; +} + +uint64_t ICL::getUsedPageCount(uint64_t lcaBegin, uint64_t lcaEnd) { + uint32_t ratio = pFTL->getInfo()->ioUnitInPage; + + return pFTL->getUsedPageCount(lcaBegin / ratio, lcaEnd / ratio) * ratio; +} + +void ICL::getStatList(std::vector &list, std::string prefix) { + pCache->getStatList(list, prefix + "icl."); + pDRAM->getStatList(list, prefix + "dram."); + pFTL->getStatList(list, prefix); +} + +void ICL::getStatValues(std::vector &values) { + pCache->getStatValues(values); + pDRAM->getStatValues(values); + pFTL->getStatValues(values); +} + +void ICL::resetStatValues() { + pCache->resetStatValues(); + pDRAM->resetStatValues(); + pFTL->resetStatValues(); +} + +} // namespace ICL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/icl/icl.hh b/hotness/SimpleSSD-Standalone/simplessd/icl/icl.hh new file mode 100644 index 0000000000..91ebc9b36a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/icl/icl.hh @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __ICL_ICL__ +#define __ICL_ICL__ + +#include "dram/abstract_dram.hh" +#include "ftl/ftl.hh" +#include "icl/abstract_cache.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace ICL { + +class ICL : public StatObject { + private: + FTL::FTL *pFTL; + DRAM::AbstractDRAM *pDRAM; + + ConfigReader &conf; + AbstractCache *pCache; + + uint64_t totalLogicalPages; + uint32_t logicalPageSize; + + public: + ICL(ConfigReader &); + ~ICL(); + + void read(Request &, uint64_t &); + void write(Request &, uint64_t &); + + void flush(LPNRange &, uint64_t &); + void trim(LPNRange &, uint64_t &); + void format(LPNRange &, uint64_t &); + + void getLPNInfo(uint64_t &, uint32_t &); + uint64_t getUsedPageCount(uint64_t, uint64_t); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace ICL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/inih/LICENSE.txt b/hotness/SimpleSSD-Standalone/simplessd/lib/inih/LICENSE.txt new file mode 100644 index 0000000000..cb7ee2d017 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/inih/LICENSE.txt @@ -0,0 +1,27 @@ + +The "inih" library is distributed under the New BSD license: + +Copyright (c) 2009, Ben Hoyt +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Ben Hoyt nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY BEN HOYT ''AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL BEN HOYT BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/inih/ini.c b/hotness/SimpleSSD-Standalone/simplessd/lib/inih/ini.c new file mode 100644 index 0000000000..602908b926 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/inih/ini.c @@ -0,0 +1,244 @@ +/* inih -- simple .INI file parser + +inih is released under the New BSD license (see LICENSE.txt). Go to the project +home page for more info: + +https://github.com/benhoyt/inih + +*/ + +#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS) +#define _CRT_SECURE_NO_WARNINGS +#endif + +#include +#include +#include + +#include "ini.h" + +#if !INI_USE_STACK +#include +#endif + +#define MAX_SECTION 50 +#define MAX_NAME 50 + +/* Used by ini_parse_string() to keep track of string parsing state. */ +typedef struct { + const char* ptr; + size_t num_left; +} ini_parse_string_ctx; + +/* Strip whitespace chars off end of given string, in place. Return s. */ +static char* rstrip(char* s) +{ + char* p = s + strlen(s); + while (p > s && isspace((unsigned char)(*--p))) + *p = '\0'; + return s; +} + +/* Return pointer to first non-whitespace char in given string. */ +static char* lskip(const char* s) +{ + while (*s && isspace((unsigned char)(*s))) + s++; + return (char*)s; +} + +/* Return pointer to first char (of chars) or inline comment in given string, + or pointer to null at end of string if neither found. Inline comment must + be prefixed by a whitespace character to register as a comment. */ +static char* find_chars_or_comment(const char* s, const char* chars) +{ +#if INI_ALLOW_INLINE_COMMENTS + int was_space = 0; + while (*s && (!chars || !strchr(chars, *s)) && + !(was_space && strchr(INI_INLINE_COMMENT_PREFIXES, *s))) { + was_space = isspace((unsigned char)(*s)); + s++; + } +#else + while (*s && (!chars || !strchr(chars, *s))) { + s++; + } +#endif + return (char*)s; +} + +/* Version of strncpy that ensures dest (size bytes) is null-terminated. */ +static char* strncpy0(char* dest, const char* src, size_t size) +{ + strncpy(dest, src, size); + dest[size - 1] = '\0'; + return dest; +} + +/* See documentation in header file. */ +int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler, + void* user) +{ + /* Uses a fair bit of stack (use heap instead if you need to) */ +#if INI_USE_STACK + char line[INI_MAX_LINE]; +#else + char* line; +#endif + char section[MAX_SECTION] = ""; + char prev_name[MAX_NAME] = ""; + + char* start; + char* end; + char* name; + char* value; + int lineno = 0; + int error = 0; + +#if !INI_USE_STACK + line = (char*)malloc(INI_MAX_LINE); + if (!line) { + return -2; + } +#endif + +#if INI_HANDLER_LINENO +#define HANDLER(u, s, n, v) handler(u, s, n, v, lineno) +#else +#define HANDLER(u, s, n, v) handler(u, s, n, v) +#endif + + /* Scan through stream line by line */ + while (reader(line, INI_MAX_LINE, stream) != NULL) { + lineno++; + + start = line; +#if INI_ALLOW_BOM + if (lineno == 1 && (unsigned char)start[0] == 0xEF && + (unsigned char)start[1] == 0xBB && (unsigned char)start[2] == 0xBF) { + start += 3; + } +#endif + start = lskip(rstrip(start)); + + if (*start == ';' || *start == '#') { + /* Per Python configparser, allow both ; and # comments at the + start of a line */ + } +#if INI_ALLOW_MULTILINE + else if (*prev_name && *start && start > line) { + /* Non-blank line with leading whitespace, treat as continuation + of previous name's value (as per Python configparser). */ + if (!HANDLER(user, section, prev_name, start) && !error) + error = lineno; + } +#endif + else if (*start == '[') { + /* A "[section]" line */ + end = find_chars_or_comment(start + 1, "]"); + if (*end == ']') { + *end = '\0'; + strncpy0(section, start + 1, sizeof(section)); + *prev_name = '\0'; + } + else if (!error) { + /* No ']' found on section line */ + error = lineno; + } + } + else if (*start) { + /* Not a comment, must be a name[=:]value pair */ + end = find_chars_or_comment(start, "=:"); + if (*end == '=' || *end == ':') { + *end = '\0'; + name = rstrip(start); + value = end + 1; +#if INI_ALLOW_INLINE_COMMENTS + end = find_chars_or_comment(value, NULL); + if (*end) + *end = '\0'; +#endif + value = lskip(value); + rstrip(value); + + /* Valid name[=:]value pair found, call handler */ + strncpy0(prev_name, name, sizeof(prev_name)); + if (!HANDLER(user, section, name, value) && !error) + error = lineno; + } + else if (!error) { + /* No '=' or ':' found on name[=:]value line */ + error = lineno; + } + } + +#if INI_STOP_ON_FIRST_ERROR + if (error) + break; +#endif + } + +#if !INI_USE_STACK + free(line); +#endif + + return error; +} + +/* See documentation in header file. */ +int ini_parse_file(FILE* file, ini_handler handler, void* user) +{ + return ini_parse_stream((ini_reader)fgets, file, handler, user); +} + +/* See documentation in header file. */ +int ini_parse(const char* filename, ini_handler handler, void* user) +{ + FILE* file; + int error; + + file = fopen(filename, "r"); + if (!file) + return -1; + error = ini_parse_file(file, handler, user); + fclose(file); + return error; +} + +/* An ini_reader function to read the next line from a string buffer. This + is the fgets() equivalent used by ini_parse_string(). */ +static char* ini_reader_string(char* str, int num, void* stream) +{ + ini_parse_string_ctx* ctx = (ini_parse_string_ctx*)stream; + const char* ctx_ptr = ctx->ptr; + size_t ctx_num_left = ctx->num_left; + char* strp = str; + char c; + + if (ctx_num_left == 0 || num < 2) + return NULL; + + while (num > 1 && ctx_num_left != 0) { + c = *ctx_ptr++; + ctx_num_left--; + *strp++ = c; + if (c == '\n') + break; + num--; + } + + *strp = '\0'; + ctx->ptr = ctx_ptr; + ctx->num_left = ctx_num_left; + return str; +} + +/* See documentation in header file. */ +int ini_parse_string(const char* string, ini_handler handler, void* user) +{ + ini_parse_string_ctx ctx; + + ctx.ptr = string; + ctx.num_left = strlen(string); + return ini_parse_stream((ini_reader)ini_reader_string, &ctx, handler, user); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/inih/ini.h b/hotness/SimpleSSD-Standalone/simplessd/lib/inih/ini.h new file mode 100644 index 0000000000..9e2808123f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/inih/ini.h @@ -0,0 +1,111 @@ +/* inih -- simple .INI file parser + +inih is released under the New BSD license (see LICENSE.txt). Go to the project +home page for more info: + +https://github.com/benhoyt/inih + +Modified by CAMELab + +*/ + +#ifndef __INI_H__ +#define __INI_H__ + +/* Make this header file easier to include in C++ code */ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Nonzero if ini_handler callback should accept lineno parameter. */ +#ifndef INI_HANDLER_LINENO +#define INI_HANDLER_LINENO 0 +#endif + +/* Typedef for prototype of handler function. */ +#if INI_HANDLER_LINENO +typedef int (*ini_handler)(void* user, const char* section, const char* name, + const char* value, int lineno); +#else +typedef int (*ini_handler)(void* user, const char* section, const char* name, + const char* value); +#endif + +/* Typedef for prototype of fgets-style reader function. */ +typedef char* (*ini_reader)(char* str, int num, void* stream); + +/* Parse given INI-style file. May have [section]s, name=value pairs + (whitespace stripped), and comments starting with ';' (semicolon). Section + is "" if name=value pair parsed before any section heading. name:value + pairs are also supported as a concession to Python's configparser. + + For each name=value pair parsed, call handler function with given user + pointer as well as section, name, and value (data only valid for duration + of handler call). Handler should return nonzero on success, zero on error. + + Returns 0 on success, line number of first error on parse error (doesn't + stop on first error), -1 on file open error, or -2 on memory allocation + error (only when INI_USE_STACK is zero). +*/ +int ini_parse(const char* filename, ini_handler handler, void* user); + +/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't + close the file when it's finished -- the caller must do that. */ +int ini_parse_file(FILE* file, ini_handler handler, void* user); + +/* Same as ini_parse(), but takes an ini_reader function pointer instead of + filename. Used for implementing custom or string-based I/O (see also + ini_parse_string). */ +int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler, + void* user); + +/* Same as ini_parse(), but takes a zero-terminated string with the INI data +instead of a file. Useful for parsing INI data from a network socket or +already in memory. */ +int ini_parse_string(const char* string, ini_handler handler, void* user); + +/* Nonzero to allow multi-line value parsing, in the style of Python's + configparser. If allowed, ini_parse() will call the handler with the same + name for each subsequent line parsed. */ +#ifndef INI_ALLOW_MULTILINE +#define INI_ALLOW_MULTILINE 1 +#endif + +/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of + the file. See http://code.google.com/p/inih/issues/detail?id=21 */ +#ifndef INI_ALLOW_BOM +#define INI_ALLOW_BOM 1 +#endif + +/* Nonzero to allow inline comments (with valid inline comment characters + specified by INI_INLINE_COMMENT_PREFIXES). Set to 0 to turn off and match + Python 3.2+ configparser behaviour. */ +#ifndef INI_ALLOW_INLINE_COMMENTS +#define INI_ALLOW_INLINE_COMMENTS 1 +#endif +#ifndef INI_INLINE_COMMENT_PREFIXES +#define INI_INLINE_COMMENT_PREFIXES "#" +#endif + +/* Nonzero to use stack, zero to use heap (malloc/free). */ +#ifndef INI_USE_STACK +#define INI_USE_STACK 1 +#endif + +/* Stop parsing on first error (default is to keep parsing). */ +#ifndef INI_STOP_ON_FIRST_ERROR +#define INI_STOP_ON_FIRST_ERROR 0 +#endif + +/* Maximum line length for any line in INI file. */ +#ifndef INI_MAX_LINE +#define INI_MAX_LINE 200 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __INI_H__ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/.clang-format b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/.clang-format new file mode 100644 index 0000000000..38a9d1af6b --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/.clang-format @@ -0,0 +1,27 @@ +# Generated by clang-format v5.0.0 +--- +Language: Cpp +BasedOnStyle: Google +AllowShortFunctionsOnASingleLine: Inline +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakBeforeMultilineStrings: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + BeforeCatch: true + BeforeElse: true + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBraces: Custom +DerivePointerAlignment: false +PointerAlignment: Right +... diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/.gitignore b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/.gitignore new file mode 100644 index 0000000000..86443d979f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/.gitignore @@ -0,0 +1,56 @@ +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app + +# McPAT custom +mcpat +obj_opt/ + +# CMake Specific +CMakeCache.txt +CMakeFiles +CMakeScripts +Testing +Makefile +cmake_install.cmake +install_manifest.txt +compile_commands.json +CTestTestfile.cmake + +# Visual Studio Specific +.vs/ +*.sln +*.db +*.opendb +*.vcproj +*.filters +*.vcxproj +Debug/ +Release/ +x64/ +.vscode/ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/CMakeLists.txt b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/CMakeLists.txt new file mode 100644 index 0000000000..d6c2f7acac --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/CMakeLists.txt @@ -0,0 +1,102 @@ +# Copyright (C) 2017 CAMELab +# +# This file is part of SimpleSSD. +# +# SimpleSSD is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# SimpleSSD is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with SimpleSSD. If not, see . + +# Set version and project name +cmake_minimum_required(VERSION 3.10) +project(mcpat) + +# Set output directory +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) + +# Set include directories +include_directories( + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/cacti +) + +# Platform specific settings +if (MSVC) + add_definitions(-D_CRT_SECURE_NO_WARNINGS) + add_compile_options(/wd4819) # Surpress unicode warning + add_compile_options(/wd4305) # Surpress truncation warning + add_compile_options(/wd4800) # Surpress int -> boolean waring + add_compile_options(/wd4129) # Surpress escape warning + add_compile_options(/wd4244) # Surpress conversion warning + add_compile_options(/wd4267) # Surpress conversion warning +else () + if (DEBUG_BUILD) + set(CMAKE_CXX_FLAGS + "-O0 -g ${CMAKE_CXX_FLAGS}") + else () + set(CMAKE_CXX_FLAGS + "-O2 ${CMAKE_CXX_FLAGS}") + endif () +endif () + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Specify source files +set(SRC_MCPAT_CACTI + cacti/arbiter.cc + cacti/area.cc + cacti/bank.cc + cacti/basic_circuit.cc + cacti/cacti_interface.cc + cacti/component.cc + cacti/crossbar.cc + cacti/decoder.cc + cacti/htree2.cc + cacti/io.cc + cacti/main.cc + cacti/mat.cc + cacti/nuca.cc + cacti/parameter.cc + cacti/powergating.cc + cacti/router.cc + cacti/subarray.cc + cacti/technology.cc + cacti/uca.cc + cacti/Ucache.cc + cacti/wire.cc +) +set(SRC_MCPAT + array.cc + basic_components.cc + core.cc + interconnect.cc + iocontrollers.cc + logic.cc + mcpat.cc + memoryctrl.cc + noc.cc + processor.cc + sharedcache.cc + XML_Parse.cc +) + +# Source group for MSVC +SOURCE_GROUP("Source Files\\" FILES ${SRC_MCPAT}) +SOURCE_GROUP("Source Files\\cacti" FILES ${SRC_MCPAT_CACTI}) + +# Define library +add_library(mcpat STATIC + ${SRC_MCPAT} + ${SRC_MCPAT_CACTI} +) diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz.xml b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz.xml new file mode 100644 index 0000000000..b97ddd97a0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz.xml @@ -0,0 +1,442 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz_withIOC.xml b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz_withIOC.xml new file mode 100644 index 0000000000..e8099b4a8c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/ARM_A9_2GHz_withIOC.xml @@ -0,0 +1,442 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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new file mode 100644 index 0000000000..9135b0b281 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_SBT.xml @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_ST.xml b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_ST.xml new file mode 100644 index 0000000000..e5f2d2a37f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/ProcessorDescriptionFiles/Niagara1_sharing_ST.xml @@ -0,0 +1,432 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/README b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/README new file mode 100644 index 0000000000..d5473afe41 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/README @@ -0,0 +1,228 @@ + __ __ ____ _ _____ + | \/ | ___| _ \ / \|_ _| + | |\/| |/ __| |_) / _ \ | | + | | | | (__| __/ ___ \| | + |_| |_|\___|_| /_/ \_\_| + +McPAT: (M)ulti(c)ore (P)ower, (A)rea, and (T)iming +Current version 1.3 +================================================== + +* What McPAT is: + + --Architectural integrated power, area, and timing modeling framework, focuses on power and area modeling, with a target clock rate as a design constraint. + -Consider power, area, and timing simultaneously + -Complete power envelope + -Power management techniques + ---Manycore processor modeling framework + -Different cores, uncore, and system (I/O) components + -Holistically modeling across stacks: Technology models from ITRS projections (also supports user defined vdd), processor modeling based on modern processors + ---Flexible, extensible, and high (i.e., architecture) level framework + -A framework for architecture research + -Flexible to make researchers's life easier + Pre-populated micro-architecture configurations (can be changed by experienced users too!) + Multilevel automatic optimization + -Hierarchical modeling framework for easy extension and porting + Standalone for TDP + Paired up with performance simulators (or machine profiling statistics) for fine-grained study + +* What McPAT is NOT + + ---a hardware design EDA platform; nor a performance simulator + -Use RTL/SPICE/...(not McPAT) if focusing on details of complex logic or analog components + Empirical and curve-fitting based modeling for complex logic and analog building blocks (the most practical modeling methodology for high level framework). + Solution1: Users replace those models with in-house models obtained from EDA tools + Solution2: Users contribute their EDA based detailed models back to the community for sharing + -Use performance simulators for performance (McPAT cannot do performance simulations) + ---a restrictive environment + -It is a framework (rather than a black-box tool) + -Its built-in models are for references and for providing methodological examples. + McPAT's built-in model includes simplified assumptions (e.g. unified instruction window for all instruction types) + McPAT provides building blocks so that it is composable + Users should always understand the methodology when using the built-in models or compose their own models. + ---finished! + -There is always room for improvement . . . + -Thanks for the continueous contributing from the user community! + +==================== +For complete documentation of the McPAT, please refer to the following paper, +"McPAT: An Integrated Power, Area, and Timing Modeling + Framework for Multicore and Manycore Architectures", +that appears in MICRO 2009. Please cite the paper, if you use +McPAT in your work. The bibtex entry is provided below for your convenience. + + @inproceedings{mcpat:micro, + author = {Sheng Li and Jung Ho Ahn and Richard D. Strong and Jay B. Brockman and Dean M. Tullsen and Norman P. Jouppi}, + title = "{McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures}", + booktitle = {MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture}, + year = {2009}, + pages = {469--480}, + } + + +How to use the tool? +==================== + +McPAT takes input parameters from an XML-based interface, +then it computes area and peak power of the +Please note that the peak power is the absolute worst case power, +which could be even higher than TDP. + +1. Steps to run McPAT: + -> define the target processor using inorder.xml or OOO.xml + -> run the "mcpat" binary: + ./mcpat -infile <*.xml> -print_level < level of detailed output> + ./mcpat -h (or mcpat --help) will show the quick help message. + +2. Optimization: + McPAT will try its best to satisfy the target clock rate. + When it cannot find a valid solution, it gives out warnings, + while still giving a solution that is closest to the timing + constraints and calculate power based on it. The optimization + will lead to larger power/area numbers for target higher clock + rate. McPAT also provides the option "-opt_for_clk" to turn on + ("-opt_for_clk 1") and off this strict optimization for the + timing constraint. When it is off, McPAT always optimize + component for ED^2P without worrying about meeting the + target clock frequency. By turning it off, the computation time + can be reduced, which suites for situations where target clock rate + is conservative. + +3. Outputs: + McPAT outputs results in a hierarchical manner. Increasing + the "-print_level" will show detailed results inside each + component. For each component, major parts are shown, and associated + pipeline registers/control logic are added up in total area/power of each + components. In general, McPAT does not model the area/overhead of the pad + frame used in a processor die. + +4. How to use the XML interface for McPAT + 4.1 Set up the parameters + Parameters of target designs need to be set in the *.xml file for + entries tagged as "param". McPAT have very detailed parameter settings. + please remove the structure parameter from the file if you want + to use the default values. Otherwise, the parameters in the xml file + will override the default values. + + 4.2 Pass the statistics + There are two options to get the correct stats: a) the performance + simulator can capture all the stats in detail and pass them to McPAT; + b). Performance simulator can only capture partial stats and pass + them to McPAT, while McPAT can reason about the complete stats using + the partial information and the configuration. Therefore, there are + some overlap for the stats. + + 4.3 Interface XML file structures (PLEASE READ!) + The XML is hierarchical from processor level to micro-architecture + level. McPAT support both heterogeneous and homogeneous manycore processors. + + 1). For heterogeneous processor setup, each component (core, NoC, cache, + and etc) must have its own instantiations (core0, core1, ..., coreN). + Each instantiation will have different parameters as well as its stats. + Thus, the XML file must have multiple "instantiation" of each type of + heterogeneous components and the corresponding hetero flags must be set + in the XML file. Then state in the XML should be the stats of "a" instantiation + (e.g. "a" cores). The reported runtime dynamic is of a single instantiation + (e.g. "a" cores). Since the stats for each (e.g. "a" cores) may be different, + we will see a whole list of (e.g. "a" cores) with different dynamic power, + and total power is just a sum of them. + + 2). For homogeneous processors, the same method for heterogeneous can + also be used by treating all homogeneous instantiations as heterogeneous. + However, a preferred approach is to use a single representative for all + the same components (e.g. core0 to represent all cores) and set the + processor to have homogeneous components (e.g. ). Thus, the XML file only has one instantiation to represent + all others with the same architectural parameters. The corresponding homo + flags must be set in the XML file. Then, the stats in the XML should be + the aggregated stats of the sum of all instantiations (e.g. aggregated stats + of all cores). In the final results, McPAT will only report a single + instantiation of each type of component, and the reported runtime dynamic power + is the sum of all instantiations of the same type. This approach can run fast + and use much less memory. + +5. Guide for integrating McPAT into performance simulators and bypassing the XML interface + The detailed work flow of McPAT has two phases: the initialization phase and + the computation phase. Specifically, in order to start the initialization phase a + user specifies static configurations, including parameters at all three levels, + namely, architectural, circuit, and technology levels. During the initialization + phase, McPAT will generate the internal chip representation using the configurations + set by the user. + The computation phase of McPAT is called by McPAT or the performance simulator + during simulation to generate runtime power numbers. Before calling McPAT to + compute runtime power numbers, the performance simulator needs to pass the + statistics, namely, the activity factors of each individual components to McPAT + via the XML interface. + The initialization phase is very time-consuming, since it will repeat many + times until valid configurations are found or the possible configurations are + exhausted. To reduce the overhead, a user can let the simulator to call McPAT + directly for computation phase and only call initialization phase once at the + beginning of simulation. In this case, the XML interface file is bypassed, + please refer to processor.cc to see how the two phases are called. + +6. Sample input files: + This package provide sample XML files for validating target processors. Please find the + enclosed Niagara1.xml (for the Sun Niagara1 processor), Niagara2.xml (for the Sun Niagara2 + processor), Alpha21364.xml (for the Alpha21364 processor), Xeon.xml (for the Intel + Xeon Tulsa processor), and ARM_A9_2GHz.xml (for ARM Cortex A9 hard core 2GHz implementation from + ARM) + +7. Modeling of power management techniques: + McPAT supports both DVS and power-gating. For DVS, users can use default ITRS projected vdd + at each technology node as supply voltage at DVS level 0 (DVS0) or define voltage at DVS0. + For power-gating, McPAT supports both default power-saving virtual supply voltage computed + automatically using technology parameters. Default means using technology (ITRS based) + lowest value for state-retaining power-gating User can also defined voltage for Power-saving states, + as shown in example file of Xeon.xml (search for power_gating_vcc). When using user-defined power-saving + virtual supply voltage, please understand the implications when setting up voltage for different sleep states. + For example, when deep sleep state is used (voltage lower than the technology allowed state retaining supply voltage), + the effects of losing data and cold start effects (beyond the scope of McPAT) must be considered when waking up the architecture. + Power-gating and DVS cannot happen at the same time. Because power-gating happens when circuit is idle, while DVS happens when + circuit blocks are active. + + +==================== +McPAT includes its special version of Cacti (called Cacti-P) based on Cacti6.5 release. The major changes of +the special Cacti, called Cacti-P in this distro, (compared to cacti6.5) include the following new features. +The inclosed Cacti-P can run stand-alone if users want to use these features. + + * CAM and fully associative cache modeling + * Improved leakage power modeling with consideration of device/gate topology + * long channel device for reduce sub-threshold leakage power + * Sleep transistor based power-gating modeling + * gate leakage power + * Support user defined voltage supply (Vdd) + * Dynamic voltage scaling (DVS) + +For complete documentation of Cacti-P, please refer to the following paper, +"CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques", +that appeared in ICCAD2011. Please cite the paper, if you use +Cacti-P in your work. The bibtex entry is provided below for your convenience. + +@inproceedings{cacti-p:iccad, + author = {Sheng Li and Ke Chen and Jung Ho Ahn and Jay B. Brockman and Norman P. Jouppi}, + title = {CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques}, + booktitle = {ICCAD: International Conference on Computer-Aided Design}, + year = {2011}, + pages = {694-701}, +} + + +==================== +McPAT uses an opensource XML parser written and kindly specially licensed by Mr. Frank Vanden Berghen. +The detailed information about this XML parser can be found at the license information in xmlParse.cc/xmlParse.h + +==================== +McPAT is in its beginning stage. We are still improving the tool. +Please come back to its website for newer versions. +McPAT has been constantly and rapidly improved with new models and latest technology. +Please always refer to its code for most up-to-date and most accurate information. +If you have any comments, questions, or suggestions, please write to us: + + +Sheng Li +Sheng.sli@gmail.com + + + + diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/XML_Parse.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/XML_Parse.cc new file mode 100644 index 0000000000..642f766bb3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/XML_Parse.cc @@ -0,0 +1,488 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "XML_Parse.h" +#include +#include +#include + +using namespace std; + +void ParseXML::parse(char *filepath) { + // Initialize all structures + ParseXML::initialize(); +} +void ParseXML::initialize() // Initialize all +{ + // All number_of_* at the level of 'system' 03/21/2009 + sys.number_of_cores = 1; + sys.number_of_L1Directories = 1; + sys.number_of_L2Directories = 1; + sys.number_of_L2s = 1; + sys.Private_L2 = false; + sys.number_of_L3s = 1; + sys.number_of_NoCs = 1; + // All params at the level of 'system' + // strcpy(sys.homogeneous_cores,"default"); + sys.core_tech_node = 1; + sys.target_core_clockrate = 1; + sys.target_chip_area = 1; + sys.temperature = 360; + sys.number_cache_levels = 1; + sys.homogeneous_cores = 1; + sys.homogeneous_L1Directories = 1; + sys.homogeneous_L2Directories = 1; + sys.homogeneous_L2s = 1; + sys.homogeneous_L3s = 1; + sys.homogeneous_NoCs = 1; + sys.homogeneous_ccs = 1; + + sys.Max_area_deviation = 1; + sys.Max_power_deviation = 1; + sys.device_type = 1; + sys.longer_channel_device = true; + sys.power_gating = false; + sys.Embedded = false; + sys.opt_dynamic_power = false; + sys.opt_lakage_power = false; + sys.opt_clockrate = true; + sys.opt_area = false; + sys.interconnect_projection_type = 1; + sys.vdd = 0; + sys.power_gating_vcc = -1; + int i, j; + for (i = 0; i <= 63; i++) { + sys.core[i].vdd = 0; + sys.core[i].power_gating_vcc = -1; + sys.core[i].clock_rate = 1; + sys.core[i].opt_local = true; + sys.core[i].x86 = false; + sys.core[i].machine_bits = 1; + sys.core[i].virtual_address_width = 1; + sys.core[i].physical_address_width = 1; + sys.core[i].opcode_width = 1; + sys.core[i].micro_opcode_width = 1; + // strcpy(sys.core[i].machine_type,"default"); + sys.core[i].internal_datapath_width = 1; + sys.core[i].number_hardware_threads = 1; + sys.core[i].fetch_width = 1; + sys.core[i].number_instruction_fetch_ports = 1; + sys.core[i].decode_width = 1; + sys.core[i].issue_width = 1; + sys.core[i].peak_issue_width = 1; + sys.core[i].commit_width = 1; + for (j = 0; j < 20; j++) + sys.core[i].pipelines_per_core[j] = 1; + for (j = 0; j < 20; j++) + sys.core[i].pipeline_depth[j] = 1; + strcpy(sys.core[i].FPU, "default"); + strcpy(sys.core[i].divider_multiplier, "default"); + sys.core[i].ALU_per_core = 1; + sys.core[i].FPU_per_core = 1.0; + sys.core[i].MUL_per_core = 1; + sys.core[i].instruction_buffer_size = 1; + sys.core[i].decoded_stream_buffer_size = 1; + // strcpy(sys.core[i].instruction_window_scheme,"default"); + sys.core[i].instruction_window_size = 1; + sys.core[i].ROB_size = 1; + sys.core[i].archi_Regs_IRF_size = 1; + sys.core[i].archi_Regs_FRF_size = 1; + sys.core[i].phy_Regs_IRF_size = 1; + sys.core[i].phy_Regs_FRF_size = 1; + // strcpy(sys.core[i].rename_scheme,"default"); + sys.core[i].checkpoint_depth = 1; + sys.core[i].register_windows_size = 1; + strcpy(sys.core[i].LSU_order, "default"); + sys.core[i].store_buffer_size = 1; + sys.core[i].load_buffer_size = 1; + sys.core[i].memory_ports = 1; + strcpy(sys.core[i].Dcache_dual_pump, "default"); + sys.core[i].RAS_size = 1; + // all stats at the level of system.core(0-n) + sys.core[i].total_instructions = 1; + sys.core[i].int_instructions = 1; + sys.core[i].fp_instructions = 1; + sys.core[i].branch_instructions = 1; + sys.core[i].branch_mispredictions = 1; + sys.core[i].committed_instructions = 1; + sys.core[i].load_instructions = 1; + sys.core[i].store_instructions = 1; + sys.core[i].total_cycles = 1; + sys.core[i].idle_cycles = 1; + sys.core[i].busy_cycles = 1; + sys.core[i].instruction_buffer_reads = 1; + sys.core[i].instruction_buffer_write = 1; + sys.core[i].ROB_reads = 1; + sys.core[i].ROB_writes = 1; + sys.core[i].rename_accesses = 1; + sys.core[i].inst_window_reads = 1; + sys.core[i].inst_window_writes = 1; + sys.core[i].inst_window_wakeup_accesses = 1; + sys.core[i].inst_window_selections = 1; + sys.core[i].archi_int_regfile_reads = 1; + sys.core[i].archi_float_regfile_reads = 1; + sys.core[i].phy_int_regfile_reads = 1; + sys.core[i].phy_float_regfile_reads = 1; + sys.core[i].windowed_reg_accesses = 1; + sys.core[i].windowed_reg_transports = 1; + sys.core[i].function_calls = 1; + sys.core[i].ialu_accesses = 1; + sys.core[i].fpu_accesses = 1; + sys.core[i].mul_accesses = 1; + sys.core[i].cdb_alu_accesses = 1; + sys.core[i].cdb_mul_accesses = 1; + sys.core[i].cdb_fpu_accesses = 1; + sys.core[i].load_buffer_reads = 1; + sys.core[i].load_buffer_writes = 1; + sys.core[i].load_buffer_cams = 1; + sys.core[i].store_buffer_reads = 1; + sys.core[i].store_buffer_writes = 1; + sys.core[i].store_buffer_cams = 1; + sys.core[i].store_buffer_forwards = 1; + sys.core[i].main_memory_access = 1; + sys.core[i].main_memory_read = 1; + sys.core[i].main_memory_write = 1; + sys.core[i].IFU_duty_cycle = 1; + sys.core[i].BR_duty_cycle = 1; + sys.core[i].LSU_duty_cycle = 1; + sys.core[i].MemManU_I_duty_cycle = 1; + sys.core[i].MemManU_D_duty_cycle = 1; + sys.core[i].ALU_duty_cycle = 1; + sys.core[i].MUL_duty_cycle = 1; + sys.core[i].FPU_duty_cycle = 1; + sys.core[i].ALU_cdb_duty_cycle = 1; + sys.core[i].MUL_cdb_duty_cycle = 1; + sys.core[i].FPU_cdb_duty_cycle = 1; + // system.core?.predictor + sys.core[i].predictor.prediction_width = 1; + strcpy(sys.core[i].predictor.prediction_scheme, "default"); + sys.core[i].predictor.predictor_size = 1; + sys.core[i].predictor.predictor_entries = 1; + sys.core[i].predictor.local_predictor_entries = 1; + for (j = 0; j < 20; j++) + sys.core[i].predictor.local_predictor_size[j] = 1; + sys.core[i].predictor.global_predictor_entries = 1; + sys.core[i].predictor.global_predictor_bits = 1; + sys.core[i].predictor.chooser_predictor_entries = 1; + sys.core[i].predictor.chooser_predictor_bits = 1; + sys.core[i].predictor.predictor_accesses = 1; + // system.core?.itlb + sys.core[i].itlb.number_entries = 1; + sys.core[i].itlb.total_hits = 1; + sys.core[i].itlb.total_accesses = 1; + sys.core[i].itlb.total_misses = 1; + // system.core?.icache + for (j = 0; j < 20; j++) + sys.core[i].icache.icache_config[j] = 1; + // strcpy(sys.core[i].icache.buffer_sizes,"default"); + sys.core[i].icache.total_accesses = 1; + sys.core[i].icache.read_accesses = 1; + sys.core[i].icache.read_misses = 1; + sys.core[i].icache.replacements = 1; + sys.core[i].icache.read_hits = 1; + sys.core[i].icache.total_hits = 1; + sys.core[i].icache.total_misses = 1; + sys.core[i].icache.miss_buffer_access = 1; + sys.core[i].icache.fill_buffer_accesses = 1; + sys.core[i].icache.prefetch_buffer_accesses = 1; + sys.core[i].icache.prefetch_buffer_writes = 1; + sys.core[i].icache.prefetch_buffer_reads = 1; + sys.core[i].icache.prefetch_buffer_hits = 1; + // system.core?.dtlb + sys.core[i].dtlb.number_entries = 1; + sys.core[i].dtlb.total_accesses = 1; + sys.core[i].dtlb.read_accesses = 1; + sys.core[i].dtlb.write_accesses = 1; + sys.core[i].dtlb.write_hits = 1; + sys.core[i].dtlb.read_hits = 1; + sys.core[i].dtlb.read_misses = 1; + sys.core[i].dtlb.write_misses = 1; + sys.core[i].dtlb.total_hits = 1; + sys.core[i].dtlb.total_misses = 1; + // system.core?.dcache + for (j = 0; j < 20; j++) + sys.core[i].dcache.dcache_config[j] = 1; + // strcpy(sys.core[i].dcache.buffer_sizes,"default"); + sys.core[i].dcache.total_accesses = 1; + sys.core[i].dcache.read_accesses = 1; + sys.core[i].dcache.write_accesses = 1; + sys.core[i].dcache.total_hits = 1; + sys.core[i].dcache.total_misses = 1; + sys.core[i].dcache.read_hits = 1; + sys.core[i].dcache.write_hits = 1; + sys.core[i].dcache.read_misses = 1; + sys.core[i].dcache.write_misses = 1; + sys.core[i].dcache.replacements = 1; + sys.core[i].dcache.write_backs = 1; + sys.core[i].dcache.miss_buffer_access = 1; + sys.core[i].dcache.fill_buffer_accesses = 1; + sys.core[i].dcache.prefetch_buffer_accesses = 1; + sys.core[i].dcache.prefetch_buffer_writes = 1; + sys.core[i].dcache.prefetch_buffer_reads = 1; + sys.core[i].dcache.prefetch_buffer_hits = 1; + sys.core[i].dcache.wbb_writes = 1; + sys.core[i].dcache.wbb_reads = 1; + // system.core?.BTB + for (j = 0; j < 20; j++) + sys.core[i].BTB.BTB_config[j] = 1; + sys.core[i].BTB.total_accesses = 1; + sys.core[i].BTB.read_accesses = 1; + sys.core[i].BTB.write_accesses = 1; + sys.core[i].BTB.total_hits = 1; + sys.core[i].BTB.total_misses = 1; + sys.core[i].BTB.read_hits = 1; + sys.core[i].BTB.write_hits = 1; + sys.core[i].BTB.read_misses = 1; + sys.core[i].BTB.write_misses = 1; + sys.core[i].BTB.replacements = 1; + } + + // system_L1directory + for (i = 0; i <= 63; i++) { + for (j = 0; j < 20; j++) + sys.L1Directory[i].Dir_config[j] = 1; + for (j = 0; j < 20; j++) + sys.L1Directory[i].buffer_sizes[j] = 1; + sys.L1Directory[i].clockrate = 1; + sys.L1Directory[i].ports[19] = 1; + sys.L1Directory[i].device_type = 1; + sys.L1Directory[i].vdd = 0; + sys.L1Directory[i].power_gating_vcc = -1; + strcpy(sys.L1Directory[i].threeD_stack, "default"); + sys.L1Directory[i].total_accesses = 1; + sys.L1Directory[i].read_accesses = 1; + sys.L1Directory[i].write_accesses = 1; + sys.L1Directory[i].duty_cycle = 1; + } + // system_L2directory + for (i = 0; i <= 63; i++) { + for (j = 0; j < 20; j++) + sys.L2Directory[i].Dir_config[j] = 1; + for (j = 0; j < 20; j++) + sys.L2Directory[i].buffer_sizes[j] = 1; + sys.L2Directory[i].clockrate = 1; + sys.L2Directory[i].ports[19] = 1; + sys.L2Directory[i].device_type = 1; + sys.L2Directory[i].vdd = 0; + sys.L2Directory[i].power_gating_vcc = -1; + strcpy(sys.L2Directory[i].threeD_stack, "default"); + sys.L2Directory[i].total_accesses = 1; + sys.L2Directory[i].read_accesses = 1; + sys.L2Directory[i].write_accesses = 1; + sys.L2Directory[i].duty_cycle = 1; + } + for (i = 0; i <= 63; i++) { + // system_L2 + for (j = 0; j < 20; j++) + sys.L2[i].L2_config[j] = 1; + sys.L2[i].clockrate = 1; + for (j = 0; j < 20; j++) + sys.L2[i].ports[j] = 1; + sys.L2[i].device_type = 1; + sys.L2[i].vdd = 0; + sys.L2[i].power_gating_vcc = -1; + strcpy(sys.L2[i].threeD_stack, "default"); + for (j = 0; j < 20; j++) + sys.L2[i].buffer_sizes[j] = 1; + sys.L2[i].total_accesses = 1; + sys.L2[i].read_accesses = 1; + sys.L2[i].write_accesses = 1; + sys.L2[i].total_hits = 1; + sys.L2[i].total_misses = 1; + sys.L2[i].read_hits = 1; + sys.L2[i].write_hits = 1; + sys.L2[i].read_misses = 1; + sys.L2[i].write_misses = 1; + sys.L2[i].replacements = 1; + sys.L2[i].write_backs = 1; + sys.L2[i].miss_buffer_accesses = 1; + sys.L2[i].fill_buffer_accesses = 1; + sys.L2[i].prefetch_buffer_accesses = 1; + sys.L2[i].prefetch_buffer_writes = 1; + sys.L2[i].prefetch_buffer_reads = 1; + sys.L2[i].prefetch_buffer_hits = 1; + sys.L2[i].wbb_writes = 1; + sys.L2[i].wbb_reads = 1; + sys.L2[i].duty_cycle = 1; + sys.L2[i].merged_dir = false; + sys.L2[i].homenode_read_accesses = 1; + sys.L2[i].homenode_write_accesses = 1; + sys.L2[i].homenode_read_hits = 1; + sys.L2[i].homenode_write_hits = 1; + sys.L2[i].homenode_read_misses = 1; + sys.L2[i].homenode_write_misses = 1; + sys.L2[i].dir_duty_cycle = 1; + } + for (i = 0; i <= 63; i++) { + // system_L3 + for (j = 0; j < 20; j++) + sys.L3[i].L3_config[j] = 1; + sys.L3[i].clockrate = 1; + for (j = 0; j < 20; j++) + sys.L3[i].ports[j] = 1; + sys.L3[i].device_type = 1; + sys.L3[i].vdd = 0; + sys.L2[i].power_gating_vcc = -1; + strcpy(sys.L3[i].threeD_stack, "default"); + for (j = 0; j < 20; j++) + sys.L3[i].buffer_sizes[j] = 1; + sys.L3[i].total_accesses = 1; + sys.L3[i].read_accesses = 1; + sys.L3[i].write_accesses = 1; + sys.L3[i].total_hits = 1; + sys.L3[i].total_misses = 1; + sys.L3[i].read_hits = 1; + sys.L3[i].write_hits = 1; + sys.L3[i].read_misses = 1; + sys.L3[i].write_misses = 1; + sys.L3[i].replacements = 1; + sys.L3[i].write_backs = 1; + sys.L3[i].miss_buffer_accesses = 1; + sys.L3[i].fill_buffer_accesses = 1; + sys.L3[i].prefetch_buffer_accesses = 1; + sys.L3[i].prefetch_buffer_writes = 1; + sys.L3[i].prefetch_buffer_reads = 1; + sys.L3[i].prefetch_buffer_hits = 1; + sys.L3[i].wbb_writes = 1; + sys.L3[i].wbb_reads = 1; + sys.L3[i].duty_cycle = 1; + sys.L3[i].merged_dir = false; + sys.L3[i].homenode_read_accesses = 1; + sys.L3[i].homenode_write_accesses = 1; + sys.L3[i].homenode_read_hits = 1; + sys.L3[i].homenode_write_hits = 1; + sys.L3[i].homenode_read_misses = 1; + sys.L3[i].homenode_write_misses = 1; + sys.L3[i].dir_duty_cycle = 1; + } + // system_NoC + for (i = 0; i <= 63; i++) { + sys.NoC[i].clockrate = 1; + sys.NoC[i].type = true; + sys.NoC[i].chip_coverage = 1; + sys.NoC[i].vdd = 0; + sys.NoC[i].power_gating_vcc = -1; + sys.NoC[i].has_global_link = true; + strcpy(sys.NoC[i].topology, "default"); + sys.NoC[i].horizontal_nodes = 1; + sys.NoC[i].vertical_nodes = 1; + sys.NoC[i].input_ports = 1; + sys.NoC[i].output_ports = 1; + sys.NoC[i].virtual_channel_per_port = 1; + sys.NoC[i].flit_bits = 1; + sys.NoC[i].input_buffer_entries_per_vc = 1; + sys.NoC[i].total_accesses = 1; + sys.NoC[i].duty_cycle = 1; + sys.NoC[i].route_over_perc = 0.5; + for (j = 0; j < 20; j++) + sys.NoC[i].ports_of_input_buffer[j] = 1; + sys.NoC[i].number_of_crossbars = 1; + strcpy(sys.NoC[i].crossbar_type, "default"); + strcpy(sys.NoC[i].crosspoint_type, "default"); + // system.NoC?.xbar0; + sys.NoC[i].xbar0.number_of_inputs_of_crossbars = 1; + sys.NoC[i].xbar0.number_of_outputs_of_crossbars = 1; + sys.NoC[i].xbar0.flit_bits = 1; + sys.NoC[i].xbar0.input_buffer_entries_per_port = 1; + sys.NoC[i].xbar0.ports_of_input_buffer[19] = 1; + sys.NoC[i].xbar0.crossbar_accesses = 1; + } + // system_mem + sys.mem.mem_tech_node = 1; + sys.mem.device_clock = 1; + sys.mem.capacity_per_channel = 1; + sys.mem.number_ranks = 1; + sys.mem.peak_transfer_rate = 1; + sys.mem.num_banks_of_DRAM_chip = 1; + sys.mem.Block_width_of_DRAM_chip = 1; + sys.mem.output_width_of_DRAM_chip = 1; + sys.mem.page_size_of_DRAM_chip = 1; + sys.mem.burstlength_of_DRAM_chip = 1; + sys.mem.internal_prefetch_of_DRAM_chip = 1; + sys.mem.memory_accesses = 1; + sys.mem.memory_reads = 1; + sys.mem.memory_writes = 1; + // system_mc + sys.mc.mc_clock = 1; + sys.mc.number_mcs = 1; + sys.mc.peak_transfer_rate = 1; + sys.mc.memory_channels_per_mc = 1; + sys.mc.number_ranks = 1; + sys.mc.req_window_size_per_channel = 1; + sys.mc.IO_buffer_size_per_channel = 1; + sys.mc.databus_width = 1; + sys.mc.addressbus_width = 1; + sys.mc.memory_accesses = 1; + sys.mc.memory_reads = 1; + sys.mc.memory_writes = 1; + sys.mc.LVDS = true; + sys.mc.type = 1; + sys.mc.vdd = 0; + sys.mc.power_gating_vcc = -1; + // system_niu + sys.niu.clockrate = 1; + sys.niu.number_units = 1; + sys.niu.type = 1; + sys.niu.vdd = 0; + sys.niu.power_gating_vcc = -1; + sys.niu.duty_cycle = 1; + sys.niu.total_load_perc = 1; + // system_pcie + sys.pcie.clockrate = 1; + sys.pcie.number_units = 1; + sys.pcie.num_channels = 1; + sys.pcie.type = 1; + sys.pcie.vdd = 0; + sys.pcie.power_gating_vcc = -1; + sys.pcie.withPHY = false; + sys.pcie.duty_cycle = 1; + sys.pcie.total_load_perc = 1; + // system_flash_controller + sys.flashc.mc_clock = 1; + sys.flashc.number_mcs = 1; + sys.flashc.vdd = 0; + sys.flashc.power_gating_vcc = -1; + sys.flashc.peak_transfer_rate = 1; + sys.flashc.memory_channels_per_mc = 1; + sys.flashc.number_ranks = 1; + sys.flashc.req_window_size_per_channel = 1; + sys.flashc.IO_buffer_size_per_channel = 1; + sys.flashc.databus_width = 1; + sys.flashc.addressbus_width = 1; + sys.flashc.memory_accesses = 1; + sys.flashc.memory_reads = 1; + sys.flashc.memory_writes = 1; + sys.flashc.LVDS = true; + sys.flashc.withPHY = false; + sys.flashc.type = 1; + sys.flashc.duty_cycle = 1; + sys.flashc.total_load_perc = 1; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/XML_Parse.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/XML_Parse.h new file mode 100644 index 0000000000..539deb5391 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/XML_Parse.h @@ -0,0 +1,614 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef XML_PARSE_H_ +#define XML_PARSE_H_ + +//#ifdef WIN32 +//#define _CRT_SECURE_NO_DEPRECATE +//#endif + +#include +#include +#include +using namespace std; + +/* +void myfree(char *t); // {free(t);} +ToXMLStringTool tx,tx2; +*/ +// all subnodes at the level of system.core(0-n) +// cache_policy is added into cache property arrays;//0 no write or write-though +// with non-write allocate;1 write-back with write-allocate + +typedef struct { + int prediction_width; + char prediction_scheme[20]; + int predictor_size; + int predictor_entries; + int local_predictor_size[20]; + int local_predictor_entries; + int global_predictor_entries; + int global_predictor_bits; + int chooser_predictor_entries; + int chooser_predictor_bits; + double predictor_accesses; +} predictor_systemcore; +typedef struct { + int number_entries; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + double total_hits; + double total_accesses; + double total_misses; + double conflicts; +} itlb_systemcore; +typedef struct { + // params + double icache_config[20]; + int buffer_sizes[20]; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + // stats + double total_accesses; + double read_accesses; + double read_misses; + double replacements; + double read_hits; + double total_hits; + double total_misses; + double miss_buffer_access; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double conflicts; +} icache_systemcore; +typedef struct { + // params + int number_entries; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double write_hits; + double read_hits; + double read_misses; + double write_misses; + double total_hits; + double total_misses; + double conflicts; +} dtlb_systemcore; +typedef struct { + // params + double dcache_config[20]; + int buffer_sizes[20]; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; + double write_backs; + double miss_buffer_access; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double wbb_writes; + double wbb_reads; + double conflicts; +} dcache_systemcore; +typedef struct { + // params + int BTB_config[20]; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; +} BTB_systemcore; +typedef struct { + // all params at the level of system.core(0-n) + int clock_rate; + bool opt_local; + bool x86; + int machine_bits; + int virtual_address_width; + int physical_address_width; + int opcode_width; + int micro_opcode_width; + int instruction_length; + int machine_type; + int internal_datapath_width; + int number_hardware_threads; + int fetch_width; + int number_instruction_fetch_ports; + int decode_width; + int issue_width; + int peak_issue_width; + int commit_width; + int pipelines_per_core[20]; + int pipeline_depth[20]; + char FPU[20]; + char divider_multiplier[20]; + int ALU_per_core; + double FPU_per_core; + int MUL_per_core; + int instruction_buffer_size; + int decoded_stream_buffer_size; + int instruction_window_scheme; + int instruction_window_size; + int fp_instruction_window_size; + int ROB_size; + int archi_Regs_IRF_size; + int archi_Regs_FRF_size; + int phy_Regs_IRF_size; + int phy_Regs_FRF_size; + int rename_scheme; + int checkpoint_depth; + int register_windows_size; + char LSU_order[20]; + int store_buffer_size; + int load_buffer_size; + int memory_ports; + char Dcache_dual_pump[20]; + int RAS_size; + int fp_issue_width; + int prediction_width; + int number_of_BTB; + int number_of_BPT; + + // all stats at the level of system.core(0-n) + double total_instructions; + double int_instructions; + double fp_instructions; + double branch_instructions; + double branch_mispredictions; + double committed_instructions; + double committed_int_instructions; + double committed_fp_instructions; + double load_instructions; + double store_instructions; + double total_cycles; + double idle_cycles; + double busy_cycles; + double instruction_buffer_reads; + double instruction_buffer_write; + double ROB_reads; + double ROB_writes; + double rename_accesses; + double fp_rename_accesses; + double rename_reads; + double rename_writes; + double fp_rename_reads; + double fp_rename_writes; + double inst_window_reads; + double inst_window_writes; + double inst_window_wakeup_accesses; + double inst_window_selections; + double fp_inst_window_reads; + double fp_inst_window_writes; + double fp_inst_window_wakeup_accesses; + double fp_inst_window_selections; + double archi_int_regfile_reads; + double archi_float_regfile_reads; + double phy_int_regfile_reads; + double phy_float_regfile_reads; + double phy_int_regfile_writes; + double phy_float_regfile_writes; + double archi_int_regfile_writes; + double archi_float_regfile_writes; + double int_regfile_reads; + double float_regfile_reads; + double int_regfile_writes; + double float_regfile_writes; + double windowed_reg_accesses; + double windowed_reg_transports; + double function_calls; + double context_switches; + double ialu_accesses; + double fpu_accesses; + double mul_accesses; + double cdb_alu_accesses; + double cdb_mul_accesses; + double cdb_fpu_accesses; + double load_buffer_reads; + double load_buffer_writes; + double load_buffer_cams; + double store_buffer_reads; + double store_buffer_writes; + double store_buffer_cams; + double store_buffer_forwards; + double main_memory_access; + double main_memory_read; + double main_memory_write; + double pipeline_duty_cycle; + + double IFU_duty_cycle; + double BR_duty_cycle; + double LSU_duty_cycle; + double MemManU_I_duty_cycle; + double MemManU_D_duty_cycle; + double ALU_duty_cycle; + double MUL_duty_cycle; + double FPU_duty_cycle; + double ALU_cdb_duty_cycle; + double MUL_cdb_duty_cycle; + double FPU_cdb_duty_cycle; + + double vdd; + double power_gating_vcc; + + // all subnodes at the level of system.core(0-n) + predictor_systemcore predictor; + itlb_systemcore itlb; + icache_systemcore icache; + dtlb_systemcore dtlb; + dcache_systemcore dcache; + BTB_systemcore BTB; + +} system_core; +typedef struct { + // params + int Directory_type; + double Dir_config[20]; + int buffer_sizes[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double read_misses; + double write_misses; + double conflicts; + double duty_cycle; +} system_L1Directory; +typedef struct { + // params + int Directory_type; + double Dir_config[20]; + int buffer_sizes[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double read_misses; + double write_misses; + double conflicts; + double duty_cycle; +} system_L2Directory; +typedef struct { + // params + double L2_config[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + int buffer_sizes[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; + double write_backs; + double miss_buffer_accesses; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double wbb_writes; + double wbb_reads; + double conflicts; + double duty_cycle; + + bool merged_dir; + double homenode_read_accesses; + double homenode_write_accesses; + double homenode_read_hits; + double homenode_write_hits; + double homenode_read_misses; + double homenode_write_misses; + double dir_duty_cycle; +} system_L2; +typedef struct { + // params + double L3_config[20]; + int clockrate; + int ports[20]; + int device_type; + int cache_policy; // 0 no write or write-though with non-write allocate;1 + // write-back with write-allocate + char threeD_stack[20]; + int buffer_sizes[20]; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double read_accesses; + double write_accesses; + double total_hits; + double total_misses; + double read_hits; + double write_hits; + double read_misses; + double write_misses; + double replacements; + double write_backs; + double miss_buffer_accesses; + double fill_buffer_accesses; + double prefetch_buffer_accesses; + double prefetch_buffer_writes; + double prefetch_buffer_reads; + double prefetch_buffer_hits; + double wbb_writes; + double wbb_reads; + double conflicts; + double duty_cycle; + + bool merged_dir; + double homenode_read_accesses; + double homenode_write_accesses; + double homenode_read_hits; + double homenode_write_hits; + double homenode_read_misses; + double homenode_write_misses; + double dir_duty_cycle; +} system_L3; +typedef struct { + // params + int number_of_inputs_of_crossbars; + int number_of_outputs_of_crossbars; + int flit_bits; + int input_buffer_entries_per_port; + int ports_of_input_buffer[20]; + // stats + double crossbar_accesses; +} xbar0_systemNoC; +typedef struct { + // params + int clockrate; + bool type; + bool has_global_link; + char topology[20]; + int horizontal_nodes; + int vertical_nodes; + int link_throughput; + int link_latency; + int input_ports; + int output_ports; + int virtual_channel_per_port; + int flit_bits; + int input_buffer_entries_per_vc; + int ports_of_input_buffer[20]; + int dual_pump; + int number_of_crossbars; + char crossbar_type[20]; + char crosspoint_type[20]; + xbar0_systemNoC xbar0; + int arbiter_type; + double chip_coverage; + double vdd; + double power_gating_vcc; + // stats + double total_accesses; + double duty_cycle; + double route_over_perc; +} system_NoC; +typedef struct { + // params + int mem_tech_node; + int device_clock; + int peak_transfer_rate; + int internal_prefetch_of_DRAM_chip; + int capacity_per_channel; + int number_ranks; + int num_banks_of_DRAM_chip; + int Block_width_of_DRAM_chip; + int output_width_of_DRAM_chip; + int page_size_of_DRAM_chip; + int burstlength_of_DRAM_chip; + // stats + double memory_accesses; + double memory_reads; + double memory_writes; +} system_mem; +typedef struct { + // params + // Common Param for mc and fc + double peak_transfer_rate; + int number_mcs; + bool withPHY; + int type; + + // FCParam + // stats + double duty_cycle; + double total_load_perc; + + // McParam + int mc_clock; + int llc_line_length; + int memory_channels_per_mc; + int number_ranks; + int req_window_size_per_channel; + int IO_buffer_size_per_channel; + int databus_width; + int addressbus_width; + bool LVDS; + double vdd; + double power_gating_vcc; + + // stats + double memory_accesses; + double memory_reads; + double memory_writes; +} system_mc; + +typedef struct { + // params + int clockrate; + int number_units; + int type; + double vdd; + double power_gating_vcc; + // stats + double duty_cycle; + double total_load_perc; +} system_niu; + +typedef struct { + // params + int clockrate; + int number_units; + int num_channels; + int type; + bool withPHY; + double vdd; + double power_gating_vcc; + // stats + double duty_cycle; + double total_load_perc; +} system_pcie; + +typedef struct { + // All number_of_* at the level of 'system' Ying 03/21/2009 + int number_of_cores; + int number_of_L1Directories; + int number_of_L2Directories; + int number_of_L2s; + bool Private_L2; + int number_of_L3s; + int number_of_NoCs; + int number_of_dir_levels; + int domain_size; + int first_level_dir; + // All params at the level of 'system' + int homogeneous_cores; + int homogeneous_L1Directories; + int homogeneous_L2Directories; + double core_tech_node; + int target_core_clockrate; + int target_chip_area; + int temperature; + int number_cache_levels; + int L1_property; + int L2_property; + int homogeneous_L2s; + int L3_property; + int homogeneous_L3s; + int homogeneous_NoCs; + int homogeneous_ccs; + int Max_area_deviation; + int Max_power_deviation; + int device_type; + bool longer_channel_device; + bool power_gating; + bool Embedded; + bool opt_dynamic_power; + bool opt_lakage_power; + bool opt_clockrate; + bool opt_area; + int interconnect_projection_type; + int machine_bits; + int virtual_address_width; + int physical_address_width; + int virtual_memory_page_size; + double total_cycles; + double vdd; + double power_gating_vcc; + // system.core(0-n):3rd level + system_core core[64]; + system_L1Directory L1Directory[64]; + system_L2Directory L2Directory[64]; + system_L2 L2[64]; + system_L3 L3[64]; + system_NoC NoC[64]; + system_mem mem; + system_mc mc; + system_mc flashc; + system_niu niu; + system_pcie pcie; +} root_system; + +class ParseXML { + public: + void parse(char *filepath); + void initialize(); + + public: + root_system sys; +}; + +#endif /* XML_PARSE_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/arch_const.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/arch_const.h new file mode 100644 index 0000000000..32c60b3102 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/arch_const.h @@ -0,0 +1,255 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef ARCH_CONST_H_ +#define ARCH_CONST_H_ + +typedef struct { + unsigned int capacity; + unsigned int assoc; // fully + unsigned int blocksize; +} array_inputs; + +// Do Not change, unless you want to bypass the XML interface and do not care +// about the default values. Global parameters +const int number_of_cores = 8; +const int number_of_L2s = 1; +const int number_of_L3s = 1; +const int number_of_NoCs = 1; + +const double archi_F_sz_nm = 90.0; +const unsigned int dev_type = 0; +const double CLOCKRATE = 1.2 * 1e9; +const double AF = 0.5; +// const bool inorder = true; +const bool embedded = false; // NEW + +const bool homogeneous_cores = true; +const bool temperature = 360; +const int number_cache_levels = 3; +const int L1_property = 0; // private 0; coherent 1, shared 2. +const int L2_property = 2; +const bool homogeneous_L2s = true; +const bool L3_property = 2; +const bool homogeneous_L3s = true; +const double Max_area_deviation = 50; +const double Max_dynamic_deviation = 50; // New +const int opt_dynamic_power = 1; +const int opt_lakage_power = 0; +const int opt_area = 0; +const int interconnect_projection_type = 0; + +//******************************Core Parameters +const int opcode_length = 8; // 16;//Niagara +const int reg_length = 7; // Niagara +const int instruction_length = 32; // Niagara +const int data_width = 64; + +// Caches +// itlb +const int itlbsize = 512; +const int itlbassoc = 0; // fully +const int itlbblocksize = 8; +// icache +const int icachesize = 32768; +const int icacheassoc = 4; +const int icacheblocksize = 32; +// dtlb +const int dtlbsize = 512; +const int dtlbassoc = 0; // fully +const int dtlbblocksize = 8; +// dcache +const int dcachesize = 32768; +const int dcacheassoc = 4; +const int dcacheblocksize = 32; +const int dcache_write_buffers = 8; + +// cache controllers +// IB, +const int numIBEntries = 64; +const int IBsize = 64; // 2*4*instruction_length/8*2; +const int IBassoc = 0; // In Niagara it is still fully associ +const int IBblocksize = 4; + +// IFB and MIL should have the same parameters CAM +const int IFBsize = 128; // +const int IFBassoc = 0; // In Niagara it is still fully associ +const int IFBblocksize = 4; + +const int icache_write_buffers = 8; + +// register file RAM +const int regfilesize = 5760; +const int regfileassoc = 1; +const int regfileblocksize = 18; +// regwin RAM +const int regwinsize = 256; +const int regwinassoc = 1; +const int regwinblocksize = 8; + +// store buffer, lsq +const int lsqsize = 512; +const int lsqassoc = 0; +const int lsqblocksize = 8; + +// data fill queue RAM +const int dfqsize = 1024; +const int dfqassoc = 1; +const int dfqblocksize = 16; + +// outside the cores +// L2 cache bank +const int l2cachesize = 262144; +const int l2cacheassoc = 16; +const int l2cacheblocksize = 64; + +// L2 directory +const int l2dirsize = 1024; +const int l2dirassoc = 0; +const int l2dirblocksize = 2; + +// crossbar +// PCX +const int PCX_NUMBER_INPUT_PORTS_CROSSBAR = 8; +const int PCX_NUMBER_OUTPUT_PORTS_CROSSBAR = 9; +const int PCX_NUMBER_SIGNALS_PER_PORT_CROSSBAR = 144; +// PCX buffer RAM +const int pcx_buffersize = 1024; +const int pcx_bufferassoc = 1; +const int pcx_bufferblocksize = 32; +const int pcx_numbuffer = 5; +// pcx arbiter +const int pcx_arbsize = 128; +const int pcx_arbassoc = 1; +const int pcx_arbblocksize = 2; +const int pcx_numarb = 5; + +// CPX +const int CPX_NUMBER_INPUT_PORTS_CROSSBAR = 5; +const int CPX_NUMBER_OUTPUT_PORTS_CROSSBAR = 8; +const int CPX_NUMBER_SIGNALS_PER_PORT_CROSSBAR = 150; +// CPX buffer RAM +const int cpx_buffersize = 1024; +const int cpx_bufferassoc = 1; +const int cpx_bufferblocksize = 32; +const int cpx_numbuffer = 8; +// cpx arbiter +const int cpx_arbsize = 128; +const int cpx_arbassoc = 1; +const int cpx_arbblocksize = 2; +const int cpx_numarb = 8; + +const int numPhysFloatRegs = 256; +const int numPhysIntRegs = 32; +const int numROBEntries = 192; +const int umRobs = 1; + +const int BTBEntries = 4096; +const int BTBTagSize = 16; +const int LFSTSize = 1024; +const int LQEntries = 32; +const int RASSize = 16; +const int SQEntries = 32; +const int SSITSize = 1024; +const int activity = 0; +const int backComSize = 5; +const int cachePorts = 200; +const int choiceCtrBits = 2; +const int choicePredictorSize = 8192; + +const int commitWidth = 8; +const int decodeWidth = 8; +const int dispatchWidth = 8; +const int fetchWidth = 8; +const int issueWidth = 1; +const int renameWidth = 8; +// what is this forwardComSize=5?? + +const int globalCtrBits = 2; +const int globalHistoryBits = 13; +const int globalPredictorSize = 8192; + +const int localCtrBits = 2; +const int localHistoryBits = 11; +const int localHistoryTableSize = 2048; +const int localPredictorSize = 2048; + +const double Woutdrvnandn = 30 * 0.09; //(24.0 * LSCALE) +const double Woutdrvnandp = 12.5 * 0.09; //(10.0 * LSCALE) +const double Woutdrvnorn = 7.5 * 0.09; //(6.0 * LSCALE) +const double Woutdrvnorp = 50 * 0.09; // (40.0 * LSCALE) +const double Woutdrivern = 60 * 0.09; //(48.0 * LSCALE) +const double Woutdriverp = 100 * 0.09; //(80.0 * LSCALE) + +/* +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +*/ + +/* +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null + + +split=false +split_size=0 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false + +cpu_side=system.cpu0.dcache_port +mem_side=system.tol2bus.port[2] +*/ + +//[system.cpu0.dtb] +// type=AlphaDT + +#endif /* ARCH_CONST_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/array.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/array.cc new file mode 100644 index 0000000000..2d425ab120 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/array.cc @@ -0,0 +1,379 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#define GLOBALVAR +#include "array.h" +#include +#include +#include +#include "cacti/area.h" +#include "cacti/decoder.h" +#include "cacti/parameter.h" +#include "globalvar.h" + +using namespace std; + +ArrayST::ArrayST(const InputParameter *configure_interface, string _name, + enum Device_ty device_ty_, bool opt_local_, + enum Core_type core_ty_, bool _is_default) + : l_ip(*configure_interface), + name(_name), + device_ty(device_ty_), + opt_local(opt_local_), + core_ty(core_ty_), + is_default(_is_default) { + if (l_ip.cache_sz < 64) + l_ip.cache_sz = 64; + if (l_ip.power_gating && (l_ip.assoc == 0)) { + l_ip.power_gating = false; + } + l_ip.error_checking(); // not only do the error checking but also fill some + // missing parameters + optimize_array(); +} + +void ArrayST::compute_base_power() { + // l_ip.out_w =l_ip.line_sz*8; + local_result = cacti_interface(&l_ip); + assert(local_result.cycle_time > 0); + assert(local_result.access_time > 0); + // if (name == "Int FrontRAT") + // { + // cout< (candidate_iter)->power.readOp.dynamic) { + min_dynamic_energy = (candidate_iter)->power.readOp.dynamic; + min_dynamic_energy_iter = candidate_iter; + local_result = *(min_dynamic_energy_iter); + // TODO: since results are reordered results and l_ip may miss match. + // Therefore, the final output spread sheets may show the miss match. + } + else { + candidate_iter->cleanup(); + } + } + } + candidate_solutions.clear(); + } + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + double pg_reduction = power_gating_leakage_reduction( + false); // array structure all retain state; + + double macro_layout_overhead = g_tp.macro_layout_overhead; + double chip_PR_overhead = g_tp.chip_layout_overhead; + double total_overhead = macro_layout_overhead * chip_PR_overhead; + local_result.area *= total_overhead; + + // maintain constant power density + double pppm_t[4] = {total_overhead, 1, 1, total_overhead}; + + double sckRation = g_tp.sckt_co_eff; + local_result.power.readOp.dynamic *= sckRation; + local_result.power.writeOp.dynamic *= sckRation; + local_result.power.searchOp.dynamic *= sckRation; + local_result.power.readOp.leakage *= l_ip.nbanks; + local_result.power.readOp.longer_channel_leakage = + local_result.power.readOp.leakage * long_channel_device_reduction; + + if (l_ip.assoc == 0) // only use this function for CAM/FA since other array + // types compute pg leakage automatically + { + local_result.power.readOp.power_gated_leakage = + local_result.power.readOp.leakage * pg_reduction; + } + else { + local_result.power.readOp.power_gated_leakage *= + l_ip.nbanks; // normal array types + } + + local_result.power.readOp.power_gated_with_long_channel_leakage = + local_result.power.readOp.power_gated_leakage * + long_channel_device_reduction; // power-gating atop long channel + + local_result.power = local_result.power * pppm_t; + + local_result.data_array2->power.readOp.dynamic *= sckRation; + local_result.data_array2->power.writeOp.dynamic *= sckRation; + local_result.data_array2->power.searchOp.dynamic *= sckRation; + local_result.data_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.data_array2->power.readOp.longer_channel_leakage = + local_result.data_array2->power.readOp.leakage * + long_channel_device_reduction; + if (l_ip.assoc == 0) // only use this function for CAM/FA since other array + // types compute pg leakage automatically + { + local_result.data_array2->power.readOp.power_gated_leakage = + local_result.data_array2->power.readOp.leakage * pg_reduction; + } + else { + local_result.data_array2->power.readOp.power_gated_leakage *= + l_ip.nbanks; // normal array types + } + local_result.data_array2->power.readOp.power_gated_with_long_channel_leakage = + local_result.data_array2->power.readOp.power_gated_leakage * + long_channel_device_reduction; + + local_result.data_array2->power = local_result.data_array2->power * pppm_t; + + if (!(l_ip.pure_cam || l_ip.pure_ram || l_ip.fully_assoc) && l_ip.is_cache) { + local_result.tag_array2->power.readOp.dynamic *= sckRation; + local_result.tag_array2->power.writeOp.dynamic *= sckRation; + local_result.tag_array2->power.searchOp.dynamic *= sckRation; + local_result.tag_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.tag_array2->power.readOp.power_gated_leakage *= l_ip.nbanks; + local_result.tag_array2->power.readOp.longer_channel_leakage = + local_result.tag_array2->power.readOp.leakage * + long_channel_device_reduction; + + local_result.tag_array2->power.readOp + .power_gated_with_long_channel_leakage = + local_result.tag_array2->power.readOp.power_gated_leakage * + long_channel_device_reduction; + local_result.tag_array2->power = local_result.tag_array2->power * pppm_t; + } +} + +void ArrayST::leakage_feedback( + double temperature) // TODO: add the code to process power-gating leakage +{ + // Update the temperature. l_ip is already set and error-checked in the + // creator function. + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + + // This corresponds to cacti_interface() in the initialization process. + // Leakage power is updated here. + reconfigure(&l_ip, &local_result); + + // Scale the power values. This is part of ArrayST::optimize_array(). + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + + double macro_layout_overhead = g_tp.macro_layout_overhead; + double chip_PR_overhead = g_tp.chip_layout_overhead; + double total_overhead = macro_layout_overhead * chip_PR_overhead; + + double pppm_t[4] = {total_overhead, 1, 1, total_overhead}; + + double sckRation = g_tp.sckt_co_eff; + local_result.power.readOp.dynamic *= sckRation; + local_result.power.writeOp.dynamic *= sckRation; + local_result.power.searchOp.dynamic *= sckRation; + local_result.power.readOp.leakage *= l_ip.nbanks; + local_result.power.readOp.longer_channel_leakage = + local_result.power.readOp.leakage * long_channel_device_reduction; + local_result.power = local_result.power * pppm_t; + + local_result.data_array2->power.readOp.dynamic *= sckRation; + local_result.data_array2->power.writeOp.dynamic *= sckRation; + local_result.data_array2->power.searchOp.dynamic *= sckRation; + local_result.data_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.data_array2->power.readOp.longer_channel_leakage = + local_result.data_array2->power.readOp.leakage * + long_channel_device_reduction; + local_result.data_array2->power = local_result.data_array2->power * pppm_t; + + if (!(l_ip.pure_cam || l_ip.pure_ram || l_ip.fully_assoc) && l_ip.is_cache) { + local_result.tag_array2->power.readOp.dynamic *= sckRation; + local_result.tag_array2->power.writeOp.dynamic *= sckRation; + local_result.tag_array2->power.searchOp.dynamic *= sckRation; + local_result.tag_array2->power.readOp.leakage *= l_ip.nbanks; + local_result.tag_array2->power.readOp.longer_channel_leakage = + local_result.tag_array2->power.readOp.leakage * + long_channel_device_reduction; + local_result.tag_array2->power = local_result.tag_array2->power * pppm_t; + } +} + +ArrayST::~ArrayST() { + local_result.cleanup(); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/array.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/array.h new file mode 100644 index 0000000000..539c1df860 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/array.h @@ -0,0 +1,118 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef ARRAY_H_ +#define ARRAY_H_ + +#include +#include +#include "basic_components.h" +#include "cacti/cacti_interface.h" +#include "cacti/component.h" +#include "cacti/const.h" +#include "cacti/parameter.h" + +using namespace std; +using namespace cacti; + +class ArrayST : public Component { + public: + ArrayST(){}; + ArrayST(const InputParameter *configure_interface, string _name, + enum Device_ty device_ty_, bool opt_local_ = true, + enum Core_type core_ty_ = Inorder, bool _is_default = true); + + InputParameter l_ip; + string name; + enum Device_ty device_ty; + bool opt_local; + enum Core_type core_ty; + bool is_default; + uca_org_t local_result; + + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + + virtual void optimize_array(); + virtual void compute_base_power(); + virtual ~ArrayST(); + + void leakage_feedback(double temperature); +}; + +class InstCache : public Component { + public: + ArrayST *caches; + ArrayST *missb; + ArrayST *ifb; + ArrayST *prefetchb; + powerDef power_t; // temp value holder for both (max) power and runtime power + InstCache() { + caches = 0; + missb = 0; + ifb = 0; + prefetchb = 0; + }; + ~InstCache() { + if (caches) { // caches->local_result.cleanup(); + delete caches; + caches = 0; + } + if (missb) { // missb->local_result.cleanup(); + delete missb; + missb = 0; + } + if (ifb) { // ifb->local_result.cleanup(); + delete ifb; + ifb = 0; + } + if (prefetchb) { // prefetchb->local_result.cleanup(); + delete prefetchb; + prefetchb = 0; + } + }; +}; + +class DataCache : public InstCache { + public: + ArrayST *wbb; + DataCache() { wbb = 0; }; + ~DataCache() { + if (wbb) { // wbb->local_result.cleanup(); + delete wbb; + wbb = 0; + } + }; +}; + +#endif /* TLB_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/basic_components.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/basic_components.cc new file mode 100644 index 0000000000..f3e197a4b8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/basic_components.cc @@ -0,0 +1,138 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "basic_components.h" +#include +#include +#include + +using namespace cacti; + +double longer_channel_device_reduction(enum Device_ty device_ty, + enum Core_type core_ty) { + double longer_channel_device_percentage_core; + double longer_channel_device_percentage_uncore; + double longer_channel_device_percentage_llc; + + double long_channel_device_reduction; + + longer_channel_device_percentage_llc = 1.0; + longer_channel_device_percentage_uncore = 0.82; + if (core_ty == OOO) { + longer_channel_device_percentage_core = + 0.56; // 0.54 Xeon Tulsa //0.58 Nehelam + // longer_channel_device_percentage_uncore = 0.76;//0.85 Nehelam + } + else { + longer_channel_device_percentage_core = 0.8; // 0.8;//Niagara + // longer_channel_device_percentage_uncore = 0.9;//Niagara + } + + if (device_ty == Core_device) { + long_channel_device_reduction = + (1 - longer_channel_device_percentage_core) + + longer_channel_device_percentage_core * + g_tp.peri_global.long_channel_leakage_reduction; + } + else if (device_ty == Uncore_device) { + long_channel_device_reduction = + (1 - longer_channel_device_percentage_uncore) + + longer_channel_device_percentage_uncore * + g_tp.peri_global.long_channel_leakage_reduction; + } + else if (device_ty == LLC_device) { + long_channel_device_reduction = + (1 - longer_channel_device_percentage_llc) + + longer_channel_device_percentage_llc * + g_tp.peri_global.long_channel_leakage_reduction; + } + else { + cout << "unknown device category" << endl; + exit(0); + } + + return long_channel_device_reduction; +} + +double power_gating_leakage_reduction(bool retain_state) { + double state_retain_deduction = 1 - 0.43; + + double powergating_leakage_reduction; + + if (retain_state) { + powergating_leakage_reduction = + state_retain_deduction; // 0.55 based on most runs of cactip + } + else { + powergating_leakage_reduction = + g_tp.peri_global.Vcc_min / g_tp.peri_global.Vdd; + } + + return powergating_leakage_reduction; +} + +statsComponents operator+(const statsComponents &x, const statsComponents &y) { + statsComponents z; + + z.access = x.access + y.access; + z.hit = x.hit + y.hit; + z.miss = x.miss + y.miss; + + return z; +} + +statsComponents operator*(const statsComponents &x, double const *const y) { + statsComponents z; + + z.access = x.access * y[0]; + z.hit = x.hit * y[1]; + z.miss = x.miss * y[2]; + + return z; +} + +statsDef operator+(const statsDef &x, const statsDef &y) { + statsDef z; + + z.readAc = x.readAc + y.readAc; + z.writeAc = x.writeAc + y.writeAc; + z.searchAc = x.searchAc + y.searchAc; + return z; +} + +statsDef operator*(const statsDef &x, double const *const y) { + statsDef z; + + z.readAc = x.readAc * y; + z.writeAc = x.writeAc * y; + z.searchAc = x.searchAc * y; + return z; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/basic_components.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/basic_components.h new file mode 100644 index 0000000000..2fac864ce8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/basic_components.h @@ -0,0 +1,262 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef BASIC_COMPONENTS_H_ +#define BASIC_COMPONENTS_H_ + +#include +#include "XML_Parse.h" +#include "cacti/parameter.h" + +const double cdb_overhead = 1.1; + +enum FU_type { FPU, ALU, MUL }; + +enum Renaming_type { RAMbased, CAMbased }; + +enum Scheduler_type { PhysicalRegFile, ReservationStation }; + +enum cache_level { L2, L3, L1Directory, L2Directory }; + +enum MemoryCtrl_type { + MC, // memory controller + FLASHC // flash controller +}; + +enum Dir_type { + ST, // shadowed tag + DC, // directory cache + SBT, // static bank tag + NonDir + +}; + +enum Cache_policy { Write_through, Write_back }; + +enum Device_ty { Core_device, Uncore_device, LLC_device }; + +enum Core_type { OOO, Inorder }; + +class statsComponents { + public: + double access; + double hit; + double miss; + + statsComponents() : access(0), hit(0), miss(0) {} + statsComponents(const statsComponents &obj) { *this = obj; } + statsComponents &operator=(const statsComponents &rhs) { + access = rhs.access; + hit = rhs.hit; + miss = rhs.miss; + return *this; + } + void reset() { + access = 0; + hit = 0; + miss = 0; + } + + friend statsComponents operator+(const statsComponents &x, + const statsComponents &y); + friend statsComponents operator*(const statsComponents &x, + double const *const y); +}; + +class statsDef { + public: + statsComponents readAc; + statsComponents writeAc; + statsComponents searchAc; + + statsDef() : readAc(), writeAc(), searchAc() {} + void reset() { + readAc.reset(); + writeAc.reset(); + searchAc.reset(); + } + + friend statsDef operator+(const statsDef &x, const statsDef &y); + friend statsDef operator*(const statsDef &x, double const *const y); +}; + +double longer_channel_device_reduction(enum Device_ty device_ty = Core_device, + enum Core_type core_ty = Inorder); + +double power_gating_leakage_reduction(bool retain_state = false); + +class CoreDynParam { + public: + CoreDynParam(){}; + CoreDynParam(ParseXML *XML_interface, int ithCore_); + // :XML(XML_interface), + // ithCore(ithCore_) + // core_ty(inorder), + // rm_ty(CAMbased), + // scheu_ty(PhysicalRegFile), + // clockRate(1e9),//1GHz + // arch_ireg_width(32), + // arch_freg_width(32), + // phy_ireg_width(128), + // phy_freg_width(128), + // perThreadState(8), + // globalCheckpoint(32), + // instructionLength(32){}; + // ParseXML * XML; + bool opt_local; + bool x86; + bool Embedded; + enum Core_type core_ty; + enum Renaming_type rm_ty; + enum Scheduler_type scheu_ty; + double clockRate, executionTime; + int arch_ireg_width, arch_freg_width, phy_ireg_width, phy_freg_width, + hthread_width; + int num_IRF_entry, num_FRF_entry, num_ifreelist_entries, + num_ffreelist_entries; + int fetchW, decodeW, issueW, peak_issueW, commitW, peak_commitW, predictionW, + fp_issueW, fp_decodeW; + int perThreadState, globalCheckpoint, instruction_length, pc_width, + opcode_length, micro_opcode_length; + int num_hthreads, pipeline_stages, fp_pipeline_stages, num_pipelines, + num_fp_pipelines; + int num_alus, num_muls; + double num_fpus; + int int_data_width, fp_data_width, v_address_width, p_address_width; + double pipeline_duty_cycle, total_cycles, busy_cycles, idle_cycles; + bool regWindowing, multithreaded; + double pppm_lkg_multhread[4]; + double IFU_duty_cycle, BR_duty_cycle, LSU_duty_cycle, MemManU_I_duty_cycle, + MemManU_D_duty_cycle, ALU_duty_cycle, MUL_duty_cycle, FPU_duty_cycle, + ALU_cdb_duty_cycle, MUL_cdb_duty_cycle, FPU_cdb_duty_cycle; + double vdd; + double power_gating_vcc; + ~CoreDynParam(){}; +}; + +class CacheDynParam { + public: + CacheDynParam(){}; + CacheDynParam(ParseXML *XML_interface, int ithCache_); + string name; + enum Dir_type dir_ty; + double clockRate, executionTime; + double capacity, blockW, assoc, nbanks; + double throughput, latency; + double duty_cycle, dir_duty_cycle; + // double duty_cycle; + int missb_size, fu_size, prefetchb_size, wbb_size; + double vdd; + double power_gating_vcc; + ~CacheDynParam(){}; +}; + +class MCParam { + public: + MCParam(){}; + MCParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate, num_mcs, peakDataTransferRate, num_channels; + // double mcTEPowerperGhz; + // double mcPHYperGbit; + // double area; + int llcBlockSize, dataBusWidth, addressBusWidth; + int opcodeW; + int memAccesses; + int memRank; + int type; + double frontend_duty_cycle, duty_cycle, perc_load; + double executionTime, reads, writes; + bool LVDS, withPHY; + double vdd; + double power_gating_vcc; + ~MCParam(){}; +}; + +class NoCParam { + public: + NoCParam(){}; + NoCParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate; + int flit_size; + int input_ports, output_ports, min_ports, global_linked_ports; + int virtual_channel_per_port, input_buffer_entries_per_vc; + int horizontal_nodes, vertical_nodes, total_nodes; + double executionTime, total_access, link_throughput, link_latency, duty_cycle, + chip_coverage, route_over_perc; + bool has_global_link, type; + double vdd; + double power_gating_vcc; + ~NoCParam(){}; +}; + +class ProcParam { + public: + ProcParam(){}; + ProcParam(ParseXML *XML_interface, int ithCache_); + string name; + int numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir, numMC, numMCChannel; + bool homoCore, homoL2, homoL3, homoNOC, homoL1Dir, homoL2Dir; + double vdd; + double power_gating_vcc; + ~ProcParam(){}; +}; + +class NIUParam { + public: + NIUParam(){}; + NIUParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate; + int num_units; + int type; + double duty_cycle, perc_load; + double vdd; + double power_gating_vcc; + ~NIUParam(){}; +}; + +class PCIeParam { + public: + PCIeParam(){}; + PCIeParam(ParseXML *XML_interface, int ithCache_); + string name; + double clockRate; + int num_channels, num_units; + bool withPHY; + int type; + double duty_cycle, perc_load; + double vdd; + double power_gating_vcc; + ~PCIeParam(){}; +}; +#endif /* BASIC_COMPONENTS_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/README b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/README new file mode 100644 index 0000000000..43ff59f27d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/README @@ -0,0 +1,131 @@ +----------------------------------------------------------- + ____ _ ____ _____ ___ ____ + / ___| / \ / ___|_ _|_ _| | _ \ + | | / _ \| | | | | |_____| |_) | + | |___ / ___ \ |___ | | | |_____| __/ + \____/_/ \_\____| |_| |___| |_| + + + A Tool to Model Caches/Memories +----------------------------------------------------------- + +CACTI is an analytical tool that takes a set of cache/memory para- +meters as input and calculates its access time, power, cycle +time, and area. +CACTI was originally developed by Dr. Jouppi and Dr. Wilton +in 1993 and since then it has undergone five major +revisions. + +About Cacti-P (contact: sheng.sli@gmail.com) +=================== +This is a special version of Cacti based on Cacti6.5 release for McPAT. The major +changes of this special Cacti, called Cacti-P in this distro, +(compared to cacti6.5) includes the following new features. +The inclosed Cacti-P can run stand-alone if users want to use these features. + + * CAM and fully associative cache modeling + * Improved leakage power modeling with consideration of device/gate topology + * long channel device for reduce sub-threshold leakage power + * Sleep transistor based power-gating modeling + * gate leakage power + * Support user defined voltage supply (Vdd) + * Dynamic voltage scaling (DVS) + +In the output results, either ITRS default or user defined vdd is used as baseline supply vdd. +When DVS is enabled, this vdd is denoted as @DVS_Level0. The user defined DVS voltage levels are +denoted as @DVS_Level1~@DVS_Leveln. + +Power-gating and DVS cannot happen at the same time. Because power-gating happens when circuit is idle, +while DVS happens when circuit is active. +When waking up from power-gating status, it is assumed that the system will first wakeup to DVS0 (full speed) state, +if DVS is enabled in the system. + +For complete documentation of Cacti-P, please refer to the following paper, +"CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques", +that appeared in ICCAD2011. Please cite the paper, if you use +Cacti-P in your work. The bibtex entry is provided below for your convenience. + +@inproceedings{cacti-p:iccad, + author = {Sheng Li and Ke Chen and Jung Ho Ahn and Jay B. Brockman and Norman P. Jouppi}, + title = {CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques}, + booktitle = {ICCAD: International Conference on Computer-Aided Design}, + year = {2011}, + pages = {694-701}, +} + +List of features (version 1-6.5): +=============================== +The following is the list of features supported by the tool. + +* Power, delay, area, and cycle time model for + direct mapped caches + set-associative caches + fully associative caches + Embedded DRAM memories + Commodity DRAM memories + +* Support for modeling multi-ported uniform cache access (UCA) + and multi-banked, multi-ported non-uniform cache access (NUCA). + +* Leakage power calculation that also considers the operating + temperature of the cache. + +* Router power model. + +* Interconnect model with different delay, power, and area + properties including low-swing wire model. + +* An interface to perform trade-off analysis involving power, delay, + area, and bandwidth. + +* All process specific values used by the tool are obtained + from ITRS and currently, the tool supports 90nm, 65nm, 45nm, + and 32nm technology nodes. + +Version 6.5 has a new c++ code base and includes numerous bug fixes. +CACTI 5.3 and 6.0 activate an entire row of mats to read/write a single +block of data. This technique improves reliability at the cost of +power. CACTI 6.5 activates minimum number of mats just enough to retrieve +a block to minimize power. + +How to use the tool? +==================== +Prior versions of CACTI take input parameters such as cache +size and technology node as a set of command line arguments. +To avoid a long list of command line arguments, +CACTI 6.5 lets users specify their cache model in a more +detailed manner by using a config file (cache.cfg). + +-> define the cache model using cache.cfg +-> run the "cacti" binary <./cacti -infile cache.cfg> + +CACTI6.5 also provides a command line interface similar to earlier versions +of CACTI. The command line interface can be used as + +./cacti cache_size line_size associativity rw_ports excl_read_ports excl_write_ports + single_ended_read_ports search_ports banks tech_node output_width specific_tag tag_width + access_mode cache main_mem obj_func_delay obj_func_dynamic_power obj_func_leakage_power + obj_func_cycle_time obj_func_area dev_func_delay dev_func_dynamic_power dev_func_leakage_power + dev_func_area dev_func_cycle_time ed_ed2_none temp wt data_arr_ram_cell_tech_flavor_in + data_arr_peri_global_tech_flavor_in tag_arr_ram_cell_tech_flavor_in tag_arr_peri_global_tech_flavor_in + interconnect_projection_type_in wire_inside_mat_type_in wire_outside_mat_type_in + REPEATERS_IN_HTREE_SEGMENTS_in VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in + BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in PAGE_SIZE_BITS_in BURST_LENGTH_in + INTERNAL_PREFETCH_WIDTH_in force_wiretype wiretype force_config ndwl ndbl nspd ndcm + ndsam1 ndsam2 ecc + +For complete documentation of the tool, please refer CACTI-5.3 and 6.0 +technical reports and the following paper, +"Optimizing NUCA Organizations and Wiring Alternatives for +Large Caches With CACTI 6.0", that appears in MICRO 2007. + +We are still improving the tool and refining the code. If you +have any comments, questions, or suggestions please write to +us. + +Naveen Muralimanohar Jung Ho Ahn Sheng Li +naveen.muralimanohar@hp.com gajh@snu.ac.kr sheng.li@hp.com + + + + diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/Ucache.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/Ucache.cc new file mode 100644 index 0000000000..74750568b9 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/Ucache.cc @@ -0,0 +1,1140 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include + +#include "Ucache.h" +#include "area.h" +#include "bank.h" +#include "basic_circuit.h" +#include "component.h" +#include "const.h" +#include "decoder.h" +#include "parameter.h" +#include "subarray.h" +#include "uca.h" + +#include +#include +#include +#include + +using namespace std; + +#ifndef NTHREADS +#define NTHREADS 4 +#endif + +namespace cacti { + +const uint32_t nthreads = NTHREADS; + +void min_values_t::update_min_values(const min_values_t *val) { + min_delay = (min_delay > val->min_delay) ? val->min_delay : min_delay; + min_dyn = (min_dyn > val->min_dyn) ? val->min_dyn : min_dyn; + min_leakage = + (min_leakage > val->min_leakage) ? val->min_leakage : min_leakage; + min_area = (min_area > val->min_area) ? val->min_area : min_area; + min_cyc = (min_cyc > val->min_cyc) ? val->min_cyc : min_cyc; +} + +void min_values_t::update_min_values(const uca_org_t &res) { + min_delay = (min_delay > res.access_time) ? res.access_time : min_delay; + min_dyn = + (min_dyn > res.power.readOp.dynamic) ? res.power.readOp.dynamic : min_dyn; + min_leakage = (min_leakage > res.power.readOp.leakage) + ? res.power.readOp.leakage + : min_leakage; + min_area = (min_area > res.area) ? res.area : min_area; + min_cyc = (min_cyc > res.cycle_time) ? res.cycle_time : min_cyc; +} + +void min_values_t::update_min_values(const nuca_org_t *res) { + min_delay = + (min_delay > res->nuca_pda.delay) ? res->nuca_pda.delay : min_delay; + min_dyn = (min_dyn > res->nuca_pda.power.readOp.dynamic) + ? res->nuca_pda.power.readOp.dynamic + : min_dyn; + min_leakage = (min_leakage > res->nuca_pda.power.readOp.leakage) + ? res->nuca_pda.power.readOp.leakage + : min_leakage; + min_area = (min_area > res->nuca_pda.area.get_area()) + ? res->nuca_pda.area.get_area() + : min_area; + min_cyc = + (min_cyc > res->nuca_pda.cycle_time) ? res->nuca_pda.cycle_time : min_cyc; +} + +void min_values_t::update_min_values(const mem_array *res) { + min_delay = (min_delay > res->access_time) ? res->access_time : min_delay; + min_dyn = (min_dyn > res->power.readOp.dynamic) ? res->power.readOp.dynamic + : min_dyn; + min_leakage = (min_leakage > res->power.readOp.leakage) + ? res->power.readOp.leakage + : min_leakage; + min_area = (min_area > res->area) ? res->area : min_area; + min_cyc = (min_cyc > res->cycle_time) ? res->cycle_time : min_cyc; +} + +void calc_time_mt_wrapper(void *void_obj) { + calc_time_mt_wrapper_struct *calc_obj = + (calc_time_mt_wrapper_struct *)void_obj; + uint32_t tid = calc_obj->tid; + list &data_arr = calc_obj->data_arr; + list &tag_arr = calc_obj->tag_arr; + bool is_tag = calc_obj->is_tag; + bool pure_ram = calc_obj->pure_ram; + bool pure_cam = calc_obj->pure_cam; + bool is_main_mem = calc_obj->is_main_mem; + double Nspd_min = calc_obj->Nspd_min; + min_values_t *data_res = calc_obj->data_res; + min_values_t *tag_res = calc_obj->tag_res; + + data_arr.clear(); + data_arr.push_back(new mem_array); + tag_arr.clear(); + tag_arr.push_back(new mem_array); + + uint32_t Ndwl_niter = _log2(MAXDATAN) + 1; + uint32_t Ndbl_niter = _log2(MAXDATAN) + 1; + uint32_t Ndcm_niter = _log2(MAX_COL_MUX) + 1; + uint32_t niter = Ndwl_niter * Ndbl_niter * Ndcm_niter; + + bool is_valid_partition; + int wt_min, wt_max; + + if (g_ip->force_wiretype) { + if (g_ip->wt == 0) { + wt_min = Low_swing; + wt_max = Low_swing; + } + else { + wt_min = Global; + wt_max = Low_swing - 1; + } + } + else { + wt_min = Global; + wt_max = Low_swing; + } + + for (double Nspd = Nspd_min; Nspd <= MAXDATASPD; Nspd *= 2) { + for (int wr = wt_min; wr <= wt_max; wr++) { + for (uint32_t iter = tid; iter < niter; iter += nthreads) { + // reconstruct Ndwl, Ndbl, Ndcm + unsigned int Ndwl = 1 << (iter / (Ndbl_niter * Ndcm_niter)); + unsigned int Ndbl = 1 << ((iter / (Ndcm_niter)) % Ndbl_niter); + unsigned int Ndcm = 1 << (iter % Ndcm_niter); + for (unsigned int Ndsam_lev_1 = 1; Ndsam_lev_1 <= MAX_COL_MUX; + Ndsam_lev_1 *= 2) { + for (unsigned int Ndsam_lev_2 = 1; Ndsam_lev_2 <= MAX_COL_MUX; + Ndsam_lev_2 *= 2) { + // for debuging + if (g_ip->force_cache_config && is_tag == false) { + wr = g_ip->wt; + Ndwl = g_ip->ndwl; + Ndbl = g_ip->ndbl; + Ndcm = g_ip->ndcm; + if (g_ip->nspd != 0) { + Nspd = g_ip->nspd; + } + if (g_ip->ndsam1 != 0) { + Ndsam_lev_1 = g_ip->ndsam1; + Ndsam_lev_2 = g_ip->ndsam2; + } + } + + if (is_tag == true) { + is_valid_partition = + calculate_time(is_tag, pure_ram, pure_cam, Nspd, Ndwl, Ndbl, + Ndcm, Ndsam_lev_1, Ndsam_lev_2, tag_arr.back(), + 0, NULL, NULL, is_main_mem); + } + // If it's a fully-associative cache, the data array partition + // parameters are identical to that of the tag array, so compute + // data array partition properties also here. + if (is_tag == false || g_ip->fully_assoc) { + is_valid_partition = + calculate_time(is_tag /*false*/, pure_ram, pure_cam, Nspd, + Ndwl, Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, + data_arr.back(), 0, NULL, NULL, is_main_mem); + } + + if (is_valid_partition) { + if (is_tag == true) { + tag_arr.back()->wt = (enum Wire_type)wr; + tag_res->update_min_values(tag_arr.back()); + tag_arr.push_back(new mem_array); + } + if (is_tag == false || g_ip->fully_assoc) { + data_arr.back()->wt = (enum Wire_type)wr; + data_res->update_min_values(data_arr.back()); + data_arr.push_back(new mem_array); + } + } + + if (g_ip->force_cache_config && is_tag == false) { + wr = wt_max; + iter = niter; + if (g_ip->nspd != 0) { + Nspd = MAXDATASPD; + } + if (g_ip->ndsam1 != 0) { + Ndsam_lev_1 = MAX_COL_MUX + 1; + Ndsam_lev_2 = MAX_COL_MUX + 1; + } + } + } + } + } + } + } + + delete data_arr.back(); + delete tag_arr.back(); + data_arr.pop_back(); + tag_arr.pop_back(); +} + +bool calculate_time(bool is_tag, int pure_ram, bool pure_cam, double Nspd, + unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, + mem_array *ptr_array, int flag_results_populate, + results_mem_array *ptr_results, uca_org_t *ptr_fin_res, + bool is_main_mem) { + DynamicParameter dyn_p(is_tag, pure_ram, pure_cam, Nspd, Ndwl, Ndbl, Ndcm, + Ndsam_lev_1, Ndsam_lev_2, is_main_mem); + + if (dyn_p.is_valid == false) { + return false; + } + + UCA *uca = new UCA(dyn_p); + + if (flag_results_populate) { // For the final solution, populate the + // ptr_results data structure -- TODO: copy + // only necessary variables + } + else { + collect_uca_results(Nspd, Ndwl, Ndbl, Ndcm, Ndsam_lev_1, Ndsam_lev_2, uca, + ptr_array, is_main_mem); + } + + delete uca; + return true; +} + +void collect_uca_results( + // bool is_tag, + // int pure_ram, + // bool pure_cam, + double Nspd, unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, UCA const *const uca, + mem_array *const ptr_array, + // int flag_results_populate, + // results_mem_array *ptr_results, + // uca_org_t *ptr_fin_res, + bool is_main_mem) { + int num_act_mats_hor_dir = uca->bank.dp.num_act_mats_hor_dir; + int num_mats = uca->bank.dp.num_mats; + bool is_fa = uca->bank.dp.fully_assoc; + bool pure_cam = uca->bank.dp.pure_cam; + ptr_array->Ndwl = Ndwl; + ptr_array->Ndbl = Ndbl; + ptr_array->Nspd = Nspd; + ptr_array->deg_bl_muxing = uca->bank.dp.deg_bl_muxing; + ptr_array->Ndsam_lev_1 = Ndsam_lev_1; + ptr_array->Ndsam_lev_2 = Ndsam_lev_2; + ptr_array->access_time = uca->access_time; + ptr_array->cycle_time = uca->cycle_time; + ptr_array->multisubbank_interleave_cycle_time = + uca->multisubbank_interleave_cycle_time; + ptr_array->area_ram_cells = uca->area_all_dataramcells; + ptr_array->area = uca->area.get_area(); + ptr_array->height = uca->area.h; + ptr_array->width = uca->area.w; + ptr_array->mat_height = uca->bank.mat.area.h; + ptr_array->mat_length = uca->bank.mat.area.w; + ptr_array->subarray_height = uca->bank.mat.subarray.area.h; + ptr_array->subarray_length = uca->bank.mat.subarray.area.w; + ptr_array->power = uca->power; + ptr_array->delay_senseamp_mux_decoder = + MAX(uca->delay_array_to_sa_mux_lev_1_decoder, + uca->delay_array_to_sa_mux_lev_2_decoder); + ptr_array->delay_before_subarray_output_driver = + uca->delay_before_subarray_output_driver; + ptr_array->delay_from_subarray_output_driver_to_output = + uca->delay_from_subarray_out_drv_to_out; + + ptr_array->delay_route_to_bank = uca->htree_in_add->delay; + ptr_array->delay_input_htree = uca->bank.htree_in_add->delay; + ptr_array->delay_row_predecode_driver_and_block = + uca->bank.mat.r_predec->delay; + ptr_array->delay_row_decoder = uca->bank.mat.row_dec->delay; + ptr_array->delay_bitlines = uca->bank.mat.delay_bitline; + ptr_array->delay_matchlines = uca->bank.mat.delay_matchchline; + ptr_array->delay_sense_amp = uca->bank.mat.delay_sa; + ptr_array->delay_subarray_output_driver = + uca->bank.mat.delay_subarray_out_drv_htree; + ptr_array->delay_dout_htree = uca->bank.htree_out_data->delay; + ptr_array->delay_comparator = uca->bank.mat.delay_comparator; + + ptr_array->all_banks_height = uca->area.h; + ptr_array->all_banks_width = uca->area.w; + ptr_array->area_efficiency = + uca->area_all_dataramcells * 100 / (uca->area.get_area()); + + ptr_array->power_routing_to_bank = uca->power_routing_to_bank; + ptr_array->power_addr_input_htree = uca->bank.htree_in_add->power; + ptr_array->power_data_input_htree = uca->bank.htree_in_data->power; + // cout<<"power_data_input_htree"<bank.htree_in_data->power.readOp.leakage<power_data_output_htree = uca->bank.htree_out_data->power; + // cout<<"power_data_output_htree"<bank.htree_out_data->power.readOp.leakage<power_row_predecoder_drivers = + uca->bank.mat.r_predec->driver_power; + ptr_array->power_row_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_row_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_row_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_row_predecoder_blocks = uca->bank.mat.r_predec->block_power; + ptr_array->power_row_predecoder_blocks.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_row_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_row_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_row_decoders = uca->bank.mat.power_row_decoders; + ptr_array->power_row_decoders.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_row_decoders.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_row_decoders.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_bit_mux_predecoder_drivers = + uca->bank.mat.b_mux_predec->driver_power; + ptr_array->power_bit_mux_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_bit_mux_predecoder_blocks = + uca->bank.mat.b_mux_predec->block_power; + ptr_array->power_bit_mux_predecoder_blocks.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_bit_mux_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_bit_mux_decoders = uca->bank.mat.power_bit_mux_decoders; + ptr_array->power_bit_mux_decoders.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bit_mux_decoders.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bit_mux_decoders.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers = + uca->bank.mat.sa_mux_lev_1_predec->driver_power; + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks = + uca->bank.mat.sa_mux_lev_1_predec->block_power; + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_1_decoders = + uca->bank.mat.power_sa_mux_lev_1_decoders; + ptr_array->power_senseamp_mux_lev_1_decoders.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_decoders.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_1_decoders.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers = + uca->bank.mat.sa_mux_lev_2_predec->driver_power; + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_drivers.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks = + uca->bank.mat.sa_mux_lev_2_predec->block_power; + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_predecoder_blocks.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_senseamp_mux_lev_2_decoders = + uca->bank.mat.power_sa_mux_lev_2_decoders; + ptr_array->power_senseamp_mux_lev_2_decoders.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_decoders.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_senseamp_mux_lev_2_decoders.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_bitlines = uca->bank.mat.power_bitline; + ptr_array->power_bitlines.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bitlines.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_bitlines.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_sense_amps = uca->bank.mat.power_sa; + ptr_array->power_sense_amps.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_sense_amps.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_sense_amps.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_prechg_eq_drivers = uca->bank.mat.power_bl_precharge_eq_drv; + ptr_array->power_prechg_eq_drivers.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_prechg_eq_drivers.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_prechg_eq_drivers.searchOp.dynamic *= num_act_mats_hor_dir; + + ptr_array->power_output_drivers_at_subarray = + uca->bank.mat.power_subarray_out_drv; + ptr_array->power_output_drivers_at_subarray.readOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_output_drivers_at_subarray.writeOp.dynamic *= + num_act_mats_hor_dir; + ptr_array->power_output_drivers_at_subarray.searchOp.dynamic *= + num_act_mats_hor_dir; + + ptr_array->power_comparators = uca->bank.mat.power_comparator; + ptr_array->power_comparators.readOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_comparators.writeOp.dynamic *= num_act_mats_hor_dir; + ptr_array->power_comparators.searchOp.dynamic *= num_act_mats_hor_dir; + + // cout << " num of mats: " << dyn_p.num_mats << endl; + if (is_fa || pure_cam) { + ptr_array->power_htree_in_search = uca->bank.htree_in_search->power; + // cout<<"power_htree_in_search"<bank.htree_in_search->power.readOp.leakage<power_htree_out_search = uca->bank.htree_out_search->power; + // cout<<"power_htree_out_search"<bank.htree_out_search->power.readOp.leakage<power_searchline = uca->bank.mat.power_searchline; + // cout<<"power_searchlineh"<bank.mat.power_searchline.readOp.leakage<power_searchline.searchOp.dynamic *= num_mats; + ptr_array->power_searchline_precharge = + uca->bank.mat.power_searchline_precharge; + ptr_array->power_searchline_precharge.searchOp.dynamic *= num_mats; + ptr_array->power_matchlines = uca->bank.mat.power_matchline; + ptr_array->power_matchlines.searchOp.dynamic *= num_mats; + ptr_array->power_matchline_precharge = + uca->bank.mat.power_matchline_precharge; + ptr_array->power_matchline_precharge.searchOp.dynamic *= num_mats; + ptr_array->power_matchline_to_wordline_drv = + uca->bank.mat.power_ml_to_ram_wl_drv; + // cout<<"power_matchline.searchOp.leakage"<bank.mat.power_matchline.searchOp.leakage<activate_energy = uca->activate_energy; + ptr_array->read_energy = uca->read_energy; + ptr_array->write_energy = uca->write_energy; + ptr_array->precharge_energy = uca->precharge_energy; + ptr_array->refresh_power = uca->refresh_power; + ptr_array->leak_power_subbank_closed_page = + uca->leak_power_subbank_closed_page; + ptr_array->leak_power_subbank_open_page = uca->leak_power_subbank_open_page; + ptr_array->leak_power_request_and_reply_networks = + uca->leak_power_request_and_reply_networks; + + ptr_array->precharge_delay = uca->precharge_delay; + + // cout<<"power_matchline.searchOp.leakage"<bank.mat.<bank.mat.subarray.get_total_cell_area()<array_leakage = uca->bank.array_leakage; + ptr_array->wl_leakage = uca->bank.wl_leakage; + ptr_array->cl_leakage = uca->bank.cl_leakage; + if (g_ip->power_gating) { + ptr_array->sram_sleep_tx_width = uca->bank.mat.sram_sleep_tx->width; + ptr_array->sram_sleep_tx_area = uca->bank.mat.array_sleep_tx_area; + ptr_array->sram_sleep_wakeup_latency = uca->bank.mat.array_wakeup_t; + ptr_array->sram_sleep_wakeup_energy = + uca->bank.mat.array_wakeup_e.readOp.dynamic; + + ptr_array->wl_sleep_tx_width = uca->bank.mat.row_dec->sleeptx->width; + ptr_array->wl_sleep_tx_area = uca->bank.mat.wl_sleep_tx_area; + ptr_array->wl_sleep_wakeup_latency = uca->bank.mat.wl_wakeup_t; + ptr_array->wl_sleep_wakeup_energy = + uca->bank.mat.wl_wakeup_e.readOp.dynamic; + + ptr_array->bl_floating_wakeup_latency = uca->bank.mat.blfloating_wakeup_t; + ptr_array->bl_floating_wakeup_energy = + uca->bank.mat.blfloating_wakeup_e.readOp.dynamic; + } + + ptr_array->num_active_mats = uca->bank.dp.num_act_mats_hor_dir; + ptr_array->num_submarray_mats = uca->bank.mat.num_subarrays_per_mat; + // cout<<"array_leakage"<array_leakage<wl_leakage<cl_leakage<long_channel_leakage_reduction_periperal = + uca->long_channel_leakage_reduction_periperal; + ptr_array->long_channel_leakage_reduction_memcell = + uca->long_channel_leakage_reduction_memcell; +} + +bool check_uca_org(uca_org_t &u, min_values_t *minval) { + if (((u.access_time - minval->min_delay) * 100 / minval->min_delay) > + g_ip->delay_dev) { + return false; + } + if (((u.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn) * 100 > + g_ip->dynamic_power_dev) { + return false; + } + if (((u.power.readOp.leakage - minval->min_leakage) / minval->min_leakage) * + 100 > + g_ip->leakage_power_dev) { + return false; + } + if (((u.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > + g_ip->cycle_time_dev) { + return false; + } + if (((u.area - minval->min_area) / minval->min_area) * 100 > g_ip->area_dev) { + return false; + } + return true; +} + +bool check_mem_org(mem_array &u, const min_values_t *minval) { + if (((u.access_time - minval->min_delay) * 100 / minval->min_delay) > + g_ip->delay_dev) { + return false; + } + if (((u.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn) * 100 > + g_ip->dynamic_power_dev) { + return false; + } + if (((u.power.readOp.leakage - minval->min_leakage) / minval->min_leakage) * + 100 > + g_ip->leakage_power_dev) { + return false; + } + if (((u.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > + g_ip->cycle_time_dev) { + return false; + } + if (((u.area - minval->min_area) / minval->min_area) * 100 > g_ip->area_dev) { + return false; + } + return true; +} + +void find_optimal_uca(uca_org_t *res, min_values_t *minval, + list &ulist) { + double cost = 0; + double min_cost = BIGNUM; + float d, a, dp, lp, c; + + dp = g_ip->dynamic_power_wt; + lp = g_ip->leakage_power_wt; + a = g_ip->area_wt; + d = g_ip->delay_wt; + c = g_ip->cycle_time_wt; + + if (ulist.empty() == true) { + cout << "ERROR: no valid cache organizations found" << endl; + exit(0); + } + + for (list::iterator niter = ulist.begin(); niter != ulist.end(); + niter++) { + if (g_ip->ed == 1) { + cost = ((niter)->access_time / minval->min_delay) * + ((niter)->power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + *res = (*(niter)); + } + } + else if (g_ip->ed == 2) { + cost = ((niter)->access_time / minval->min_delay) * + ((niter)->access_time / minval->min_delay) * + ((niter)->power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + *res = (*(niter)); + } + } + else { + /* + * check whether the current organization + * meets the input deviation constraints + */ + bool v = check_uca_org(*niter, minval); + // if (minval->min_leakage == 0) minval->min_leakage = 0.1; //FIXME remove + // this after leakage modeling + + if (v) { + cost = (d * ((niter)->access_time / minval->min_delay) + + c * ((niter)->cycle_time / minval->min_cyc) + + dp * ((niter)->power.readOp.dynamic / minval->min_dyn) + + lp * ((niter)->power.readOp.leakage / minval->min_leakage) + + a * ((niter)->area / minval->min_area)); + // fprintf(stderr, "cost = %g\n", cost); + + if (min_cost > cost) { + min_cost = cost; + *res = (*(niter)); + niter = ulist.erase(niter); + if (niter != ulist.begin()) + niter--; + } + } + else { + niter = ulist.erase(niter); + if (niter != ulist.begin()) + niter--; + } + } + } + + if (min_cost == BIGNUM) { + cout << "ERROR: no cache organizations met optimization criteria" << endl; + exit(0); + } +} + +void filter_tag_arr(const min_values_t *min, list &list) { + double cost = BIGNUM; + double cur_cost; + double wt_delay = g_ip->delay_wt, wt_dyn = g_ip->dynamic_power_wt, + wt_leakage = g_ip->leakage_power_wt, wt_cyc = g_ip->cycle_time_wt, + wt_area = g_ip->area_wt; + mem_array *res = NULL; + + if (list.empty() == true) { + cout << "ERROR: no valid tag organizations found" << endl; + exit(1); + } + + while (list.empty() != true) { + bool v = check_mem_org(*list.back(), min); + if (v) { + cur_cost = + wt_delay * (list.back()->access_time / min->min_delay) + + wt_dyn * (list.back()->power.readOp.dynamic / min->min_dyn) + + wt_leakage * (list.back()->power.readOp.leakage / min->min_leakage) + + wt_area * (list.back()->area / min->min_area) + + wt_cyc * (list.back()->cycle_time / min->min_cyc); + } + else { + cur_cost = BIGNUM; + } + if (cur_cost < cost) { + if (res != NULL) { + delete res; + } + cost = cur_cost; + res = list.back(); + } + else { + delete list.back(); + } + list.pop_back(); + } + if (!res) { + cout << "ERROR: no valid tag organizations found" << endl; + exit(0); + } + + list.push_back(res); +} + +void filter_data_arr(list &curr_list) { + if (curr_list.empty() == true) { + cout << "ERROR: no valid data array organizations found" << endl; + exit(1); + } + + list::iterator iter; + + for (iter = curr_list.begin(); iter != curr_list.end(); ++iter) { + mem_array *m = *iter; + + if (m == NULL) + exit(1); + + if (((m->access_time - m->arr_min->min_delay) / m->arr_min->min_delay > + 0.5) && + ((m->power.readOp.dynamic - m->arr_min->min_dyn) / m->arr_min->min_dyn > + 0.5)) { + delete m; + iter = curr_list.erase(iter); + iter--; + } + } +} + +/* + * Performs exhaustive search across different sub-array sizes, + * wire types and aspect ratios to find an optimal UCA organization + * 1. First different valid tag array organizations are calculated + * and stored in tag_arr array + * 2. The exhaustive search is repeated to find valid data array + * organizations and stored in data_arr array + * 3. Cache area, delay, power, and cycle time for different + * cache organizations are calculated based on the + * above results + * 4. Cache model with least cost is picked from sol_list + */ +void solve(uca_org_t *fin_res) { + // bool is_dram = false; + int pure_ram = g_ip->pure_ram; + bool pure_cam = g_ip->pure_cam; + + init_tech_params(g_ip->F_sz_um, false); + + list tag_arr(0); + list data_arr(0); + list::iterator miter; + list sol_list(1, uca_org_t()); + + fin_res->tag_array.access_time = 0; + fin_res->tag_array.Ndwl = 0; + fin_res->tag_array.Ndbl = 0; + fin_res->tag_array.Nspd = 0; + fin_res->tag_array.deg_bl_muxing = 0; + fin_res->tag_array.Ndsam_lev_1 = 0; + fin_res->tag_array.Ndsam_lev_2 = 0; + + // distribute calculate_time() execution to multiple threads + calc_time_mt_wrapper_struct *calc_array = + new calc_time_mt_wrapper_struct[nthreads]; + std::thread threads[nthreads]; + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].tid = t; + calc_array[t].pure_ram = pure_ram; + calc_array[t].pure_cam = pure_cam; + calc_array[t].data_res = new min_values_t(); + calc_array[t].tag_res = new min_values_t(); + } + + bool is_tag; + // uint32_t ram_cell_tech_type; + + // If it's a cache, first calculate the area, delay and power for all tag + // array partitions. + if (!(pure_ram || pure_cam || g_ip->fully_assoc)) { // cache + is_tag = true; + // ram_cell_tech_type = g_ip->tag_arr_ram_cell_tech_type; + // is_dram = + // ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == + // comm_dram)); + init_tech_params(g_ip->F_sz_um, is_tag); + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].is_tag = is_tag; + calc_array[t].is_main_mem = false; + calc_array[t].Nspd_min = 0.125; + threads[t] = std::thread(calc_time_mt_wrapper,(void *)(&(calc_array[t]))); + } + + for (uint32_t t = 0; t < nthreads; t++) { + threads[t].join(); + } + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].data_arr.sort(mem_array::lt); + data_arr.merge(calc_array[t].data_arr, mem_array::lt); + calc_array[t].tag_arr.sort(mem_array::lt); + tag_arr.merge(calc_array[t].tag_arr, mem_array::lt); + } + } + + // calculate the area, delay and power for all data array partitions (for + // cache or plain RAM). + // if (!g_ip->fully_assoc) + // {//in the new cacti, cam, fully_associative cache are processed as single + // array in the data portion + is_tag = false; + // ram_cell_tech_type = g_ip->data_arr_ram_cell_tech_type; + // is_dram = + // ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram)); + init_tech_params(g_ip->F_sz_um, is_tag); + + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].is_tag = is_tag; + calc_array[t].is_main_mem = g_ip->is_main_mem; + if (!(pure_cam || g_ip->fully_assoc)) { + calc_array[t].Nspd_min = + (double)(g_ip->out_w) / (double)(g_ip->block_sz * 8); + } + else { + calc_array[t].Nspd_min = 1; + } + + threads[t] = std::thread(calc_time_mt_wrapper,(void *)(&(calc_array[t]))); + } + + for (uint32_t t = 0; t < nthreads; t++) { + threads[t].join(); + } + + data_arr.clear(); + for (uint32_t t = 0; t < nthreads; t++) { + calc_array[t].data_arr.sort(mem_array::lt); + data_arr.merge(calc_array[t].data_arr, mem_array::lt); + } + // } + + min_values_t *d_min = new min_values_t(); + min_values_t *t_min = new min_values_t(); + min_values_t *cache_min = new min_values_t(); + + for (uint32_t t = 0; t < nthreads; t++) { + d_min->update_min_values(calc_array[t].data_res); + t_min->update_min_values(calc_array[t].tag_res); + } + + for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { + (*miter)->arr_min = d_min; + } + + // cout << data_arr.size() << "\t" << tag_arr.size() <<" before\n"; + filter_data_arr(data_arr); + if (!(pure_ram || pure_cam || g_ip->fully_assoc)) { + filter_tag_arr(t_min, tag_arr); + } + // cout << data_arr.size() << "\t" << tag_arr.size() <<" after\n"; + + if (pure_ram || pure_cam || g_ip->fully_assoc) { + for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { + uca_org_t &curr_org = sol_list.back(); // essentially adds value to + // sol_list, with no extra memory + // copying. + curr_org.tag_array2 = NULL; + curr_org.data_array2 = (*miter); + + curr_org.find_delay(); + curr_org.find_energy(); + curr_org.find_area(); + curr_org.find_cyc(); + + // update min values for the entire cache + cache_min->update_min_values(curr_org); + + sol_list.push_back(uca_org_t()); // add a new node to the back + } + } + else { + while (tag_arr.empty() != true) { + mem_array *arr_temp = (tag_arr.back()); + // delete tag_arr.back(); + tag_arr + .pop_back(); // this causes double free problem if uca_org_t has a + // destructor to release all contained pointers---when + // called by sol_list.clear(); so uca_org_t does not + // use destructor to delete contained pointers + + for (miter = data_arr.begin(); miter != data_arr.end(); miter++) { + uca_org_t &curr_org = sol_list.back(); + curr_org.tag_array2 = arr_temp; + curr_org.data_array2 = + (*miter); // try all combinations of tag and data array + + curr_org.find_delay(); + curr_org.find_energy(); + curr_org.find_area(); + curr_org.find_cyc(); + + // update min values for the entire cache + cache_min->update_min_values(curr_org); + + sol_list.push_back(uca_org_t()); + } + } + } + + sol_list.pop_back(); // delete the last unused node added in the loop above + + find_optimal_uca(fin_res, cache_min, sol_list); + + sol_list.clear(); + + for (miter = data_arr.begin(); miter != data_arr.end(); ++miter) { + if (*miter != fin_res->data_array2) { + delete *miter; + } + } + data_arr.clear(); + + for (uint32_t t = 0; t < nthreads; t++) { + delete calc_array[t].data_res; + delete calc_array[t].tag_res; + } + + delete[] calc_array; + delete cache_min; + delete d_min; + delete t_min; +} + +void update_dvs(uca_org_t *fin_res) { + if (fin_res->tag_array2 || fin_res->data_array2) { + // Wire::print_wire(); + Wire winit; // init before changing dvs + // fin_res->uca_q = vector(g_ip->dvs_voltage.size()); + for (unsigned int i = 0; i < g_ip->dvs_voltage.size(); i++) { + fin_res->uca_q.push_back(new uca_org_t()); + + g_ip->hp_Vdd = g_ip->dvs_voltage[i]; + g_ip->specific_hp_vdd = true; + g_ip->lstp_Vdd = g_ip->dvs_voltage[i]; + g_ip->specific_lstp_vdd = true; + g_ip->lop_Vdd = g_ip->dvs_voltage[i]; + g_ip->specific_lop_vdd = true; + // g_ip->power_gating = false; + // g_ip->bitline_floating = false; + // g_ip->wl_power_gated = false; + // g_ip->interconect_power_gated = false; + // g_ip->cl_power_gated = false; + // g_ip->array_power_gated = false; + + init_tech_params(g_ip->F_sz_um, true); + winit.wire_dvs_update(); // Wire::wire_dvs_update();//Wire winit (1,1, + // false); + // Wire::print_wire(); + + if (fin_res->tag_array2) { + DynamicParameter tag_arr_dyn_p( + true, g_ip->pure_ram, g_ip->pure_cam, fin_res->tag_array2->Nspd, + fin_res->tag_array2->Ndwl, fin_res->tag_array2->Ndbl, + fin_res->tag_array2->deg_bl_muxing, + fin_res->tag_array2->Ndsam_lev_1, fin_res->tag_array2->Ndsam_lev_2, + g_ip->is_main_mem); + if (tag_arr_dyn_p.is_valid) { + UCA *tag_arr = new UCA(tag_arr_dyn_p); + fin_res->uca_q[i]->tag_array2 = new mem_array(); + + collect_uca_results( + fin_res->tag_array2->Nspd, fin_res->tag_array2->Ndwl, + fin_res->tag_array2->Ndbl, fin_res->tag_array2->deg_bl_muxing, + fin_res->tag_array2->Ndsam_lev_1, + fin_res->tag_array2->Ndsam_lev_2, tag_arr, + fin_res->uca_q[i]->tag_array2, g_ip->is_main_mem); + delete tag_arr; + } + } + DynamicParameter data_arr_dyn_p( + false, g_ip->pure_ram, g_ip->pure_cam, fin_res->data_array2->Nspd, + fin_res->data_array2->Ndwl, fin_res->data_array2->Ndbl, + fin_res->data_array2->deg_bl_muxing, + fin_res->data_array2->Ndsam_lev_1, fin_res->data_array2->Ndsam_lev_2, + g_ip->is_main_mem); + if (data_arr_dyn_p.is_valid) { + UCA *data_arr = new UCA(data_arr_dyn_p); + fin_res->uca_q[i]->data_array2 = new mem_array(); + collect_uca_results( + fin_res->data_array2->Nspd, fin_res->data_array2->Ndwl, + fin_res->data_array2->Ndbl, fin_res->data_array2->deg_bl_muxing, + fin_res->data_array2->Ndsam_lev_1, + fin_res->data_array2->Ndsam_lev_2, data_arr, + fin_res->uca_q[i]->data_array2, g_ip->is_main_mem); + delete data_arr; + } + + fin_res->uca_q[i]->find_delay(); + fin_res->uca_q[i]->find_energy(); + fin_res->uca_q[i]->find_area(); + fin_res->uca_q[i]->find_cyc(); + + // output_UCA(fin_res->uca_q[i]); + // Wire::print_wire(); + } + // reset input to original values in *.cfg file + g_ip->specific_hp_vdd = false; + g_ip->specific_lstp_vdd = false; + g_ip->specific_lop_vdd = false; + init_tech_params(g_ip->F_sz_um, true); + } + else { + cout << "ERROR: Cannot retrieve array structure for tag and data array" + << endl; + exit(1); + } +} + +void update_pg(uca_org_t *fin_res) { + if (fin_res->tag_array2 || fin_res->data_array2) { + Wire winit; + fin_res->uca_pg_reference = new uca_org_t(); + /* + if (i == 0) {g_ip->hp_Vdd = 0.8; } + else g_ip->hp_Vdd = 1.1; + g_ip->specific_hp_vdd = true; + cout<<"VDD=====" << g_ip->hp_Vdd <F_sz_um,true); + winit.wire_dvs_update();//Wire::wire_dvs_update();//Wire winit (1,1, + false); Wire::print_wire(); + */ + g_ip->array_power_gated = false; + g_ip->bitline_floating = false; + g_ip->wl_power_gated = false; + g_ip->cl_power_gated = false; + g_ip->interconect_power_gated = false; + g_ip->power_gating = false; + // winit.wire_dvs_update(); + // Wire::print_wire(); + // init_tech_params(g_ip->F_sz_um,true); + // winit.wire_dvs_update();//Wire::wire_dvs_update();//Wire winit + //(1,1, false); Wire::print_wire(); + if (fin_res->tag_array2) { + // init_tech_params(g_ip->F_sz_um,true); + DynamicParameter tag_arr_dyn_p( + true, g_ip->pure_ram, g_ip->pure_cam, fin_res->tag_array2->Nspd, + fin_res->tag_array2->Ndwl, fin_res->tag_array2->Ndbl, + fin_res->tag_array2->deg_bl_muxing, fin_res->tag_array2->Ndsam_lev_1, + fin_res->tag_array2->Ndsam_lev_2, g_ip->is_main_mem); + if (tag_arr_dyn_p.is_valid) { + UCA *tag_arr = new UCA(tag_arr_dyn_p); + fin_res->uca_pg_reference->tag_array2 = new mem_array(); + + collect_uca_results( + fin_res->tag_array2->Nspd, fin_res->tag_array2->Ndwl, + fin_res->tag_array2->Ndbl, fin_res->tag_array2->deg_bl_muxing, + fin_res->tag_array2->Ndsam_lev_1, fin_res->tag_array2->Ndsam_lev_2, + tag_arr, fin_res->uca_pg_reference->tag_array2, g_ip->is_main_mem); + delete tag_arr; + } + } + // init_tech_params(g_ip->F_sz_um,false); + DynamicParameter data_arr_dyn_p( + false, g_ip->pure_ram, g_ip->pure_cam, fin_res->data_array2->Nspd, + fin_res->data_array2->Ndwl, fin_res->data_array2->Ndbl, + fin_res->data_array2->deg_bl_muxing, fin_res->data_array2->Ndsam_lev_1, + fin_res->data_array2->Ndsam_lev_2, g_ip->is_main_mem); + if (data_arr_dyn_p.is_valid) { + UCA *data_arr = new UCA(data_arr_dyn_p); + fin_res->uca_pg_reference->data_array2 = new mem_array(); + collect_uca_results( + fin_res->data_array2->Nspd, fin_res->data_array2->Ndwl, + fin_res->data_array2->Ndbl, fin_res->data_array2->deg_bl_muxing, + fin_res->data_array2->Ndsam_lev_1, fin_res->data_array2->Ndsam_lev_2, + data_arr, fin_res->uca_pg_reference->data_array2, g_ip->is_main_mem); + delete data_arr; + } + + fin_res->uca_pg_reference->find_delay(); + fin_res->uca_pg_reference->find_energy(); + fin_res->uca_pg_reference->find_area(); + fin_res->uca_pg_reference->find_cyc(); + + // output_UCA(fin_res->uca_pg_reference); + // Wire::print_wire(); + } + else { + cout << "ERROR: Cannot retrieve array structure for tag and data array" + << endl; + exit(1); + } + // reset input to original values in *.cfg file + g_ip->array_power_gated = true; + g_ip->bitline_floating = true; + g_ip->wl_power_gated = true; + g_ip->cl_power_gated = true; + g_ip->interconect_power_gated = true; + g_ip->power_gating = true; +} + +/* update for thermal +void update(uca_org_t *fin_res) +{ + if(fin_res->tag_array2) + { + init_tech_params(g_ip->F_sz_um,true); + DynamicParameter tag_arr_dyn_p(true, g_ip->pure_ram, g_ip->pure_cam, +fin_res->tag_array2->Nspd, fin_res->tag_array2->Ndwl, fin_res->tag_array2->Ndbl, +fin_res->tag_array2->Ndcm, fin_res->tag_array2->Ndsam_lev_1, +fin_res->tag_array2->Ndsam_lev_2, g_ip->is_main_mem); if(tag_arr_dyn_p.is_valid) + { + UCA * tag_arr = new UCA(tag_arr_dyn_p); + fin_res->tag_array2->power = tag_arr->power; + } + else + { + cout << "ERROR: Cannot retrieve array structure for leakage feedback" << +endl; exit(1); + } + } + init_tech_params(g_ip->F_sz_um,false); + DynamicParameter data_arr_dyn_p(false, g_ip->pure_ram, g_ip->pure_cam, +fin_res->data_array2->Nspd, fin_res->data_array2->Ndwl, +fin_res->data_array2->Ndbl, fin_res->data_array2->Ndcm, +fin_res->data_array2->Ndsam_lev_1, fin_res->data_array2->Ndsam_lev_2, +g_ip->is_main_mem); if(data_arr_dyn_p.is_valid) + { + UCA * data_arr = new UCA(data_arr_dyn_p); + fin_res->data_array2->power = data_arr->power; + } + else + { + cout << "ERROR: Cannot retrieve array structure for leakage feedback" << +endl; exit(1); + } + + fin_res->find_energy(); +} +*/ + +} // namespace cacti diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/Ucache.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/Ucache.h new file mode 100644 index 0000000000..15efbbcfea --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/Ucache.h @@ -0,0 +1,120 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __UCACHE_H__ +#define __UCACHE_H__ + +#include +#include "area.h" +#include "nuca.h" +#include "router.h" +#include "uca.h" + +namespace cacti { + +class min_values_t { + public: + double min_delay; + double min_dyn; + double min_leakage; + double min_area; + double min_cyc; + + min_values_t() + : min_delay(BIGNUM), + min_dyn(BIGNUM), + min_leakage(BIGNUM), + min_area(BIGNUM), + min_cyc(BIGNUM) {} + + void update_min_values(const min_values_t *val); + void update_min_values(const uca_org_t &res); + void update_min_values(const nuca_org_t *res); + void update_min_values(const mem_array *res); +}; + +struct solution { + int tag_array_index; + int data_array_index; + list::iterator tag_array_iter; + list::iterator data_array_iter; + double access_time; + double cycle_time; + double area; + double efficiency; + powerDef total_power; +}; + +bool calculate_time(bool is_tag, int pure_ram, bool pure_cam, double Nspd, + unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, + mem_array *ptr_array, int flag_results_populate, + results_mem_array *ptr_results, uca_org_t *ptr_fin_res, + bool is_main_mem); + +void collect_uca_results( + // bool is_tag, + // int pure_ram, + // bool pure_cam, + double Nspd, unsigned int Ndwl, unsigned int Ndbl, unsigned int Ndcm, + unsigned int Ndsam_lev_1, unsigned int Ndsam_lev_2, UCA const *const uca, + mem_array *const ptr_array, + // int flag_results_populate, + // results_mem_array *ptr_results, + // uca_org_t *ptr_fin_res, + bool is_main_mem); + +void update_dvs(uca_org_t *fin_res); +void update_pg(uca_org_t *fin_res); + +void solve(uca_org_t *fin_res); +void init_tech_params(double tech, bool is_tag); + +struct calc_time_mt_wrapper_struct { + uint32_t tid; + bool is_tag; + bool pure_ram; + bool pure_cam; + bool is_main_mem; + double Nspd_min; + + min_values_t *data_res; + min_values_t *tag_res; + + list data_arr; + list tag_arr; +}; + +void calc_time_mt_wrapper(void *void_obj); + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/arbiter.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/arbiter.cc new file mode 100644 index 0000000000..e7698cb981 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/arbiter.cc @@ -0,0 +1,131 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "arbiter.h" +using namespace cacti; + +Arbiter::Arbiter(double n_req, double flit_size_, double output_len, + TechnologyParameter::DeviceType *dt) + : R(n_req), flit_size(flit_size_), o_len(output_len), deviceType(dt) { + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + Vdd = dt->Vdd; + double technology = g_ip->F_sz_um; + NTn1 = 13.5 * technology / 2; + PTn1 = 76 * technology / 2; + NTn2 = 13.5 * technology / 2; + PTn2 = 76 * technology / 2; + NTi = 12.5 * technology / 2; + PTi = 25 * technology / 2; + NTtr = 10 * technology / 2; /*Transmission gate's nmos tr. length*/ + PTtr = 20 * technology / 2; /* pmos tr. length*/ +} + +Arbiter::~Arbiter() {} + +double Arbiter::arb_req() { + double temp = ((R - 1) * (2 * gate_C(NTn1, 0) + gate_C(PTn1, 0)) + + 2 * gate_C(NTn2, 0) + gate_C(PTn2, 0) + gate_C(NTi, 0) + + gate_C(PTi, 0) + drain_C_(NTi, 0, 1, 1, g_tp.cell_h_def) + + drain_C_(PTi, 1, 1, 1, g_tp.cell_h_def)); + return temp; +} + +double Arbiter::arb_pri() { + double temp = + 2 * (2 * gate_C(NTn1, 0) + gate_C(PTn1, 0)); /* switching capacitance + of flip-flop is ignored */ + return temp; +} + +double Arbiter::arb_grant() { + double temp = drain_C_(NTn1, 0, 1, 1, g_tp.cell_h_def) * 2 + + drain_C_(PTn1, 1, 1, 1, g_tp.cell_h_def) + crossbar_ctrline(); + return temp; +} + +double Arbiter::arb_int() { + double temp = (drain_C_(NTn1, 0, 1, 1, g_tp.cell_h_def) * 2 + + drain_C_(PTn1, 1, 1, 1, g_tp.cell_h_def) + + 2 * gate_C(NTn2, 0) + gate_C(PTn2, 0)); + return temp; +} + +void Arbiter::compute_power() { + power.readOp.dynamic = + (R * arb_req() * Vdd * Vdd / 2 + R * arb_pri() * Vdd * Vdd / 2 + + arb_grant() * Vdd * Vdd + arb_int() * 0.5 * Vdd * Vdd); + double nor1_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTn1 * 2, + min_w_pmos * PTn1 * 2, 2, nor); + double nor2_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTn2 * R, + min_w_pmos * PTn2 * R, 2, nor); + double not_leak = + cmos_Isub_leakage(g_tp.min_w_nmos_ * NTi, min_w_pmos * PTi, 1, inv); + double nor1_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTn1 * 2, + min_w_pmos * PTn1 * 2, 2, nor); + double nor2_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTn2 * R, + min_w_pmos * PTn2 * R, 2, nor); + double not_leak_gate = + cmos_Ig_leakage(g_tp.min_w_nmos_ * NTi, min_w_pmos * PTi, 1, inv); + power.readOp.leakage = (nor1_leak + nor2_leak + not_leak) * + Vdd; // FIXME include priority table leakage + power.readOp.gate_leakage = + nor1_leak_gate * Vdd + nor2_leak_gate * Vdd + not_leak_gate * Vdd; +} + +double // wire cap with triple spacing +Arbiter::Cw3(double length) { + Wire wc(g_ip->wt, length, 1, 3, 3); + double temp = (wc.wire_cap(length, true)); + return temp; +} + +double Arbiter::crossbar_ctrline() { + double temp = + (Cw3(o_len * 1e-6 /* m */) + drain_C_(NTi, 0, 1, 1, g_tp.cell_h_def) + + drain_C_(PTi, 1, 1, 1, g_tp.cell_h_def) + gate_C(NTi, 0) + + gate_C(PTi, 0)); + return temp; +} + +double Arbiter::transmission_buf_ctrcap() { + double temp = gate_C(NTtr, 0) + gate_C(PTtr, 0); + return temp; +} + +void Arbiter::print_arbiter() { + cout << "\nArbiter Stats (" << R << " input arbiter" + << ")\n\n"; + cout << "Flit size : " << flit_size << " bits" << endl; + cout << "Dynamic Power : " << power.readOp.dynamic * 1e9 << " (nJ)" + << endl; + cout << "Leakage Power : " << power.readOp.leakage * 1e3 << " (mW)" + << endl; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/arbiter.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/arbiter.h new file mode 100644 index 0000000000..be6320ebd4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/arbiter.h @@ -0,0 +1,74 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __ARBITER__ +#define __ARBITER__ + +#include +#include +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "mat.h" +#include "parameter.h" +#include "wire.h" + +namespace cacti { + +class Arbiter : public Component { + public: + Arbiter(double Req, double flit_sz, double output_len, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + ~Arbiter(); + + void print_arbiter(); + double arb_req(); + double arb_pri(); + double arb_grant(); + double arb_int(); + void compute_power(); + double Cw3(double len); + double crossbar_ctrline(); + double transmission_buf_ctrcap(); + + private: + double NTn1, PTn1, NTn2, PTn2, R, PTi, NTi; + double flit_size; + double NTtr, PTtr; + double o_len; + TechnologyParameter::DeviceType *deviceType; + double TriS1, TriS2; + double min_w_pmos, Vdd; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/area.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/area.cc new file mode 100644 index 0000000000..b125106496 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/area.cc @@ -0,0 +1,41 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "area.h" +#include +#include +#include +#include "basic_circuit.h" +#include "component.h" +#include "decoder.h" +#include "parameter.h" + +using namespace std; diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/area.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/area.h new file mode 100644 index 0000000000..1927338998 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/area.h @@ -0,0 +1,68 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __AREA_H__ +#define __AREA_H__ + +#include "basic_circuit.h" +#include "cacti_interface.h" + +using namespace std; + +namespace cacti { + +class Area { + public: + double w; + double h; + + Area() : w(0), h(0), area(0) {} + double get_w() const { return w; } + double get_h() const { return h; } + double get_area() const { + if (w == 0 && h == 0) { + return area; + } + else { + return w * h; + } + } + void set_w(double w_) { w = w_; } + void set_h(double h_) { h = h_; } + void set_area(double a_) { area = a_; } + + private: + double area; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/bank.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/bank.cc new file mode 100644 index 0000000000..dfffc77d5a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/bank.cc @@ -0,0 +1,211 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "bank.h" +#include +using namespace cacti; + +Bank::Bank(const DynamicParameter &dyn_p) + : dp(dyn_p), + mat(dp), + num_addr_b_mat(dyn_p.number_addr_bits_mat), + num_mats_hor_dir(dyn_p.num_mats_h_dir), + num_mats_ver_dir(dyn_p.num_mats_v_dir), + array_leakage(0), + wl_leakage(0), + cl_leakage(0) { + int RWP; + int ERP; + int EWP; + int SCHP; + + if (dp.use_inp_params) { + RWP = dp.num_rw_ports; + ERP = dp.num_rd_ports; + EWP = dp.num_wr_ports; + SCHP = dp.num_search_ports; + } + else { + RWP = g_ip->num_rw_ports; + ERP = g_ip->num_rd_ports; + EWP = g_ip->num_wr_ports; + SCHP = g_ip->num_search_ports; + } + + int total_addrbits = + (dp.number_addr_bits_mat + dp.number_subbanks_decode) * (RWP + ERP + EWP); + int datainbits = dp.num_di_b_bank_per_port * (RWP + EWP); + int dataoutbits = dp.num_do_b_bank_per_port * (RWP + ERP); + int searchinbits; + int searchoutbits; + + if (dp.fully_assoc || dp.pure_cam) { + datainbits = dp.num_di_b_bank_per_port * (RWP + EWP); + dataoutbits = dp.num_do_b_bank_per_port * (RWP + ERP); + searchinbits = dp.num_si_b_bank_per_port * SCHP; + searchoutbits = dp.num_so_b_bank_per_port * SCHP; + } + + if (!(dp.fully_assoc || dp.pure_cam)) { + if (g_ip->fast_access && dp.is_tag == false) { + dataoutbits *= g_ip->data_assoc; + } + + htree_in_add = + new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, 0, dataoutbits, 0, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Add_htree); + htree_in_data = + new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, 0, dataoutbits, 0, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_in_htree); + htree_out_data = + new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, 0, dataoutbits, 0, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_out_htree); + + // htree_out_data = new Htree2 (g_ip->wt,(double) 100, (double)100, + // total_addrbits, datainbits, 0,dataoutbits,0, + // num_mats_ver_dir*2, num_mats_hor_dir*2, Data_out_htree); + + area.w = htree_in_data->area.w; + area.h = htree_in_data->area.h; + } + else { + htree_in_add = new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, searchinbits, + dataoutbits, searchoutbits, num_mats_ver_dir * 2, + num_mats_hor_dir * 2, Add_htree); + htree_in_data = new Htree2(g_ip->wt, (double)mat.area.w, (double)mat.area.h, + total_addrbits, datainbits, searchinbits, + dataoutbits, searchoutbits, num_mats_ver_dir * 2, + num_mats_hor_dir * 2, Data_in_htree); + htree_out_data = new Htree2( + g_ip->wt, (double)mat.area.w, (double)mat.area.h, total_addrbits, + datainbits, searchinbits, dataoutbits, searchoutbits, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_out_htree); + htree_in_search = new Htree2( + g_ip->wt, (double)mat.area.w, (double)mat.area.h, total_addrbits, + datainbits, searchinbits, dataoutbits, searchoutbits, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_in_htree, true, true); + htree_out_search = new Htree2( + g_ip->wt, (double)mat.area.w, (double)mat.area.h, total_addrbits, + datainbits, searchinbits, dataoutbits, searchoutbits, + num_mats_ver_dir * 2, num_mats_hor_dir * 2, Data_out_htree, true); + + area.w = htree_in_data->area.w; + area.h = htree_in_data->area.h; + } + + num_addr_b_row_dec = _log2(mat.subarray.num_rows); + num_addr_b_routed_to_mat_for_act = num_addr_b_row_dec; + num_addr_b_routed_to_mat_for_rd_or_wr = num_addr_b_mat - num_addr_b_row_dec; +} + +Bank::~Bank() { + delete htree_in_add; + delete htree_out_data; + delete htree_in_data; + if (dp.fully_assoc || dp.pure_cam) { + delete htree_in_search; + delete htree_out_search; + } +} + +double Bank::compute_delays(double inrisetime) { + return mat.compute_delays(inrisetime); +} + +void Bank::compute_power_energy() { + mat.compute_power_energy(); + + if (!(dp.fully_assoc || dp.pure_cam)) { + power.readOp.dynamic += mat.power.readOp.dynamic * dp.num_act_mats_hor_dir; + power.readOp.leakage += mat.power.readOp.leakage * dp.num_mats; + power.readOp.gate_leakage += mat.power.readOp.gate_leakage * dp.num_mats; + power.readOp.power_gated_leakage += + mat.power.readOp.power_gated_leakage * dp.num_mats; + + power.readOp.dynamic += htree_in_add->power.readOp.dynamic; + power.readOp.dynamic += htree_out_data->power.readOp.dynamic; + + array_leakage += mat.array_leakage * dp.num_mats; + wl_leakage += mat.wl_leakage * dp.num_mats; + cl_leakage += mat.cl_leakage * dp.num_mats; + + power.readOp.leakage += htree_in_add->power.readOp.leakage; + power.readOp.leakage += htree_in_data->power.readOp.leakage; + power.readOp.leakage += htree_out_data->power.readOp.leakage; + + power.readOp.power_gated_leakage += + htree_in_add->power.readOp.power_gated_leakage; + power.readOp.power_gated_leakage += + htree_in_data->power.readOp.power_gated_leakage; + power.readOp.power_gated_leakage += + htree_out_data->power.readOp.power_gated_leakage; + + power.readOp.gate_leakage += htree_in_add->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_in_data->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_out_data->power.readOp.gate_leakage; + } + else { + power.readOp.dynamic += + mat.power.readOp + .dynamic; // for fa and cam num_act_mats_hor_dir is 1 for plain r/w + power.readOp.leakage += mat.power.readOp.leakage * dp.num_mats; + power.readOp.gate_leakage += mat.power.readOp.gate_leakage * dp.num_mats; + + power.searchOp.dynamic += mat.power.searchOp.dynamic * dp.num_mats; + power.searchOp.dynamic += mat.power_bl_precharge_eq_drv.searchOp.dynamic + + mat.power_sa.searchOp.dynamic + + mat.power_bitline.searchOp.dynamic + + mat.power_subarray_out_drv.searchOp.dynamic + + mat.ml_to_ram_wl_drv->power.readOp.dynamic; + + power.readOp.dynamic += htree_in_add->power.readOp.dynamic; + power.readOp.dynamic += htree_out_data->power.readOp.dynamic; + + power.searchOp.dynamic += htree_in_search->power.searchOp.dynamic; + power.searchOp.dynamic += htree_out_search->power.searchOp.dynamic; + + power.readOp.leakage += htree_in_add->power.readOp.leakage; + power.readOp.leakage += htree_in_data->power.readOp.leakage; + power.readOp.leakage += htree_out_data->power.readOp.leakage; + power.readOp.leakage += htree_in_search->power.readOp.leakage; + power.readOp.leakage += htree_out_search->power.readOp.leakage; + + power.readOp.gate_leakage += htree_in_add->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_in_data->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_out_data->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_in_search->power.readOp.gate_leakage; + power.readOp.gate_leakage += htree_out_search->power.readOp.gate_leakage; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/bank.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/bank.h new file mode 100644 index 0000000000..928993a048 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/bank.h @@ -0,0 +1,72 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __BANK_H__ +#define __BANK_H__ + +#include "component.h" +#include "decoder.h" +#include "htree2.h" +#include "mat.h" + +namespace cacti { + +class Bank : public Component { + public: + Bank(const DynamicParameter &dyn_p); + ~Bank(); + double compute_delays(double inrisetime); // return outrisetime + void compute_power_energy(); + + const DynamicParameter &dp; + Mat mat; + Htree2 *htree_in_add; + Htree2 *htree_in_data; + Htree2 *htree_out_data; + Htree2 *htree_in_search; + Htree2 *htree_out_search; + + int num_addr_b_mat; + int num_mats_hor_dir; + int num_mats_ver_dir; + + int num_addr_b_row_dec; + int num_addr_b_routed_to_mat_for_act; + int num_addr_b_routed_to_mat_for_rd_or_wr; + + double array_leakage; + double wl_leakage; + double cl_leakage; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/basic_circuit.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/basic_circuit.cc new file mode 100644 index 0000000000..abbffe7ab1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/basic_circuit.cc @@ -0,0 +1,823 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "basic_circuit.h" +#include +#include +#include +#include "parameter.h" +using namespace cacti; + +uint32_t _log2(uint64_t num) { + uint32_t log2 = 0; + + if (num == 0) { + std::cerr << "log0?" << std::endl; + exit(1); + } + + while (num > 1) { + num = (num >> 1); + log2++; + } + + return log2; +} + +bool is_pow2(int64_t val) { + if (val <= 0) { + return false; + } + else if (val == 1) { + return true; + } + else { + return (_log2(val) != _log2(val - 1)); + } +} + +int powers(int base, int n) { + int i, p; + + p = 1; + for (i = 1; i <= n; ++i) + p *= base; + return p; +} + +/*----------------------------------------------------------------------*/ + +double logtwo(double x) { + assert(x > 0); + return ((double)(log(x) / log(2.0))); +} + +/*----------------------------------------------------------------------*/ + +double gate_C(double width, double wirelength, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + const TechnologyParameter::DeviceType *dt; + + if (_is_dram && _is_cell) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if (_is_dram && _is_wl_tr) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if (!_is_dram && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + return (dt->C_g_ideal + dt->C_overlap + 3 * dt->C_fringe) * width + + dt->l_phy * Cpolywire; +} + +// returns gate capacitance in Farads +// actually this function is the same as gate_C() now +double gate_C_pass( + double width, // gate width in um (length is Lphy_periph_global) + double wirelength, // poly wire length going to gate in lambda + bool _is_dram, bool _is_cell, bool _is_wl_tr, bool _is_sleep_tx) { + // v5.0 + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + return (dt->C_g_ideal + dt->C_overlap + 3 * dt->C_fringe) * width + + dt->l_phy * Cpolywire; +} + +double drain_C_(double width, int nchannel, int stack, + int next_arg_thresh_folding_width_or_height_cell, + double fold_dimension, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + double w_folded_tr; + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + double c_junc_area = dt->C_junc; + double c_junc_sidewall = dt->C_junc_sidewall; + double c_fringe = 2 * dt->C_fringe; + double c_overlap = 2 * dt->C_overlap; + double drain_C_metal_connecting_folded_tr = 0; + + // determine the width of the transistor after folding (if it is getting + // folded) + if (next_arg_thresh_folding_width_or_height_cell == + 0) { // interpret fold_dimension as the the folding width threshold + // i.e. the value of transistor width above which the transistor gets folded + w_folded_tr = fold_dimension; + } + else { // interpret fold_dimension as the height of the cell that this + // transistor is part of. + double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL; + // TODO : w_folded_tr must come from Component::compute_gate_area() + double ratio_p_to_n = 2.0 / (2.0 + 1.0); + if (nchannel) { + w_folded_tr = + (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS); + } + else { + w_folded_tr = + ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS); + } + } + int num_folded_tr = (int)(ceil(width / w_folded_tr)); + + if (num_folded_tr < 2) { + w_folded_tr = width; + } + + double total_drain_w = (g_tp.w_poly_contact + + 2 * g_tp.spacing_poly_to_contact) + // only for drain + (stack - 1) * g_tp.spacing_poly_to_poly; + double drain_h_for_sidewall = w_folded_tr; + double total_drain_height_for_cap_wrt_gate = + w_folded_tr + 2 * w_folded_tr * (stack - 1); + if (num_folded_tr > 1) { + total_drain_w += + (num_folded_tr - 2) * + (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + + (num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly); + + if (num_folded_tr % 2 == 0) { + drain_h_for_sidewall = 0; + } + total_drain_height_for_cap_wrt_gate *= num_folded_tr; + drain_C_metal_connecting_folded_tr = + g_tp.wire_local.C_per_um * total_drain_w; + } + + double drain_C_area = c_junc_area * total_drain_w * w_folded_tr; + double drain_C_sidewall = + c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w); + double drain_C_wrt_gate = + (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate; + + return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + + drain_C_metal_connecting_folded_tr); +} + +double tr_R_on(double width, int nchannel, int stack, bool _is_dram, + bool _is_cell, bool _is_wl_tr, bool _is_sleep_tx) { + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && _is_cell) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on; + return (stack * restrans / width); +} + +/* This routine operates in reverse: given a resistance, it finds + * the transistor width that would have this R. It is used in the + * data wordline to estimate the wordline driver size. */ + +// returns width in um +double R_to_w(double res, int nchannel, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + const TechnologyParameter::DeviceType *dt; + + if ((_is_dram) && (_is_cell)) { + dt = &g_tp.dram_acc; // DRAM cell access transistor + } + else if ((_is_dram) && (_is_wl_tr)) { + dt = &g_tp.dram_wl; // DRAM wordline transistor + } + else if ((!_is_dram) && (_is_cell)) { + dt = &g_tp.sram_cell; // SRAM cell access transistor + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { + dt = &g_tp.peri_global; + } + + double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on; + return (restrans / res); +} + +double pmos_to_nmos_sz_ratio(bool _is_dram, bool _is_wl_tr, bool _is_sleep_tx) { + double p_to_n_sizing_ratio; + if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio; + } + else if (_is_sleep_tx) { + p_to_n_sizing_ratio = + g_tp.sleep_tx.n_to_p_eff_curr_drv_ratio; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio; + } + return p_to_n_sizing_ratio; +} + +// "Timing Models for MOS Circuits" by Mark Horowitz, 1984 +double horowitz(double inputramptime, // input rise time + double tf, // time constant of gate + double vs1, // threshold voltage1/Vdd + double vs2, // threshold voltage2/vdd + int rise) // whether input rises or fall +{ + if (inputramptime == 0 && vs1 == vs2) { + return tf * (vs1 < 1 ? -log(vs1) : log(vs1)); + } + double a, b, td; + + a = inputramptime / tf; + if (rise == RISE) { + b = 0.5; + td = tf * sqrt(log(vs1) * log(vs1) + 2 * a * b * (1.0 - vs1)) + + tf * (log(vs1) - log(vs2)); + } + else { + b = 0.4; + td = tf * sqrt(log(1.0 - vs1) * log(1.0 - vs1) + 2 * a * b * (vs1)) + + tf * (log(1.0 - vs1) - log(1.0 - vs2)); + } + return (td); +} + +double cmos_Ileak(double nWidth, double pWidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nWidth * dt->I_off_n + pWidth * dt->I_off_p; +} + +int factorial(int n, int m) { + int fa = m, i; + for (i = m + 1; i <= n; i++) + fa *= i; + return fa; +} + +int combination(int n, int m) { + int ret; + ret = factorial(n, m + 1) / factorial(n - m); + return ret; +} + +double simplified_nmos_Isat(double nwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nwidth * dt->I_on_n; +} + +double simplified_pmos_Isat(double pwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return pwidth * dt->I_on_n / dt->n_to_p_eff_curr_drv_ratio; +} + +double simplified_nmos_leakage(double nwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nwidth * dt->I_off_n; +} + +double simplified_pmos_leakage(double pwidth, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return pwidth * dt->I_off_p; +} + +double cmos_Ig_n(double nWidth, bool _is_dram, bool _is_cell, bool _is_wl_tr, + bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return nWidth * dt->I_g_on_n; +} + +double cmos_Ig_p(double pWidth, bool _is_dram, bool _is_cell, bool _is_wl_tr, + bool _is_sleep_tx) { + TechnologyParameter::DeviceType *dt; + + if ((!_is_dram) && (_is_cell)) { // SRAM cell access transistor + dt = &(g_tp.sram_cell); + } + else if ((_is_dram) && (_is_wl_tr)) { // DRAM wordline transistor + dt = &(g_tp.dram_wl); + } + else if (_is_sleep_tx) { + dt = &g_tp.sleep_tx; // Sleep transistor + } + else { // DRAM or SRAM all other transistors + dt = &(g_tp.peri_global); + } + return pWidth * dt->I_g_on_p; +} + +double cmos_Isub_leakage(double nWidth, double pWidth, int fanin, + enum Gate_type g_type, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx, + enum Half_net_topology topo) { + assert(fanin >= 1); + double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, + _is_wl_tr, _is_sleep_tx); + double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, + _is_wl_tr, _is_sleep_tx); + double Isub = 0; + int num_states; + int num_off_tx; + + num_states = int(pow(2.0, fanin)); + + switch (g_type) { + case nmos: + if (fanin == 1) { + Isub = nmos_leak / num_states; + } + else { + if (topo == parallel) { + Isub = nmos_leak * fanin / num_states; // only when all tx are off, + // leakage power is non-zero. + // The possibility of this + // state is 1/num_states + } + else { + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // when num_off_tx ==0 there is no leakage power + { + // Isub += + // nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub /= num_states; + } + } + break; + case pmos: + if (fanin == 1) { + Isub = pmos_leak / num_states; + } + else { + if (topo == parallel) { + Isub = pmos_leak * fanin / num_states; // only when all tx are off, + // leakage power is non-zero. + // The possibility of this + // state is 1/num_states + } + else { + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // when num_off_tx ==0 there is no leakage power + { + // Isub += + // pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub /= num_states; + } + } + break; + case inv: + Isub = (nmos_leak + pmos_leak) / 2; + break; + case nand: + Isub += fanin * pmos_leak; // the pullup network + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // the pulldown network + { + // Isub += + // nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub /= num_states; + break; + case nor: + for (num_off_tx = 1; num_off_tx <= fanin; + num_off_tx++) // the pullup network + { + // Isub += + // pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, + // num_off_tx)*factorial(num_off_tx))); + Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR, (num_off_tx - 1)) * + combination(fanin, num_off_tx); + } + Isub += fanin * nmos_leak; // the pulldown network + Isub /= num_states; + break; + case tri: + Isub += (nmos_leak + pmos_leak) / 2; // enabled + Isub += nmos_leak * + UNI_LEAK_STACK_FACTOR; // disabled upper bound of leakage power + Isub /= 2; + break; + case tg: + Isub = (nmos_leak + pmos_leak) / 2; + break; + default: + assert(0); + break; + } + + return Isub; +} + +double cmos_Ig_leakage(double nWidth, double pWidth, int fanin, + enum Gate_type g_type, bool _is_dram, bool _is_cell, + bool _is_wl_tr, bool _is_sleep_tx, + enum Half_net_topology topo) { + assert(fanin >= 1); + double nmos_leak = + cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr, _is_sleep_tx); + double pmos_leak = + cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr, _is_sleep_tx); + double Ig_on = 0; + int num_states; + int num_on_tx; + + num_states = int(pow(2.0, fanin)); + + switch (g_type) { + case nmos: + if (fanin == 1) { + Ig_on = nmos_leak / num_states; + } + else { + if (topo == parallel) { + for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + } + else { + Ig_on += nmos_leak * fanin; // pull down network when all TXs are on. + // num_on_tx is the number of on tx + for (num_on_tx = 1; num_on_tx < fanin; + num_on_tx++) // when num_on_tx=[1,n-1] + { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx / + 2; // TODO: this is a approximation now, a precise + // computation will be very complicated. + } + Ig_on /= num_states; + } + } + break; + case pmos: + if (fanin == 1) { + Ig_on = pmos_leak / num_states; + } + else { + if (topo == parallel) { + for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + } + else { + Ig_on += pmos_leak * fanin; // pull down network when all TXs are on. + // num_on_tx is the number of on tx + for (num_on_tx = 1; num_on_tx < fanin; + num_on_tx++) // when num_on_tx=[1,n-1] + { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx / + 2; // TODO: this is a approximation now, a precise + // computation will be very complicated. + } + Ig_on /= num_states; + } + } + break; + + case inv: + Ig_on = (nmos_leak + pmos_leak) / 2; + break; + case nand: + // pull up network + for (num_on_tx = 1; num_on_tx <= fanin; + num_on_tx++) // when num_on_tx=[1,n] + { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + + // pull down network + Ig_on += nmos_leak * fanin; // pull down network when all TXs are on. + // num_on_tx is the number of on tx + for (num_on_tx = 1; num_on_tx < fanin; + num_on_tx++) // when num_on_tx=[1,n-1] + { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx / + 2; // TODO: this is a approximation now, a precise computation + // will be very complicated. + } + Ig_on /= num_states; + break; + case nor: + // num_on_tx is the number of on tx in pull up network + Ig_on += pmos_leak * fanin; // pull up network when all TXs are on. + for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) { + Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx / 2; + } + // pull down network + for (num_on_tx = 1; num_on_tx <= fanin; + num_on_tx++) // when num_on_tx=[1,n] + { + Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx; + } + Ig_on /= num_states; + break; + case tri: + Ig_on += (2 * nmos_leak + 2 * pmos_leak) / 2; // enabled + Ig_on += + (nmos_leak + pmos_leak) / 2; // disabled upper bound of leakage power + Ig_on /= 2; + break; + case tg: + Ig_on = (nmos_leak + pmos_leak) / 2; + break; + default: + assert(0); + break; + } + + return Ig_on; +} + +double shortcircuit_simple(double vt, double velocity_index, double c_in, + double c_out, double w_nmos, double w_pmos, + double i_on_n, double i_on_p, double i_on_n_in, + double i_on_p_in, double vdd) { + double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, + p_short_circuit_discharge_low, // p_short_circuit_discharge_high, + p_short_circuit_charge_low; //, + // p_short_circuit_charge_high; // this is actually energy + double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio; + + fo_n = i_on_n / i_on_n_in; + fo_p = i_on_p / i_on_p_in; + fanout = c_out / c_in; + beta_ratio = i_on_p / i_on_n; + vt_to_vdd_ratio = vt / vdd; + + // p_short_circuit_discharge_low = + // 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio; + p_short_circuit_discharge_low = + 10 / 3 * + (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) / pow(velocity_index, 2.0) / + pow(2.0, 3 * vt_to_vdd_ratio * vt_to_vdd_ratio)) * + c_in * vdd * vdd * fo_p * fo_p / fanout / beta_ratio; + p_short_circuit_charge_low = + 10 / 3 * + (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) / pow(velocity_index, 2.0) / + pow(2.0, 3 * vt_to_vdd_ratio * vt_to_vdd_ratio)) * + c_in * vdd * vdd * fo_n * fo_n / fanout * beta_ratio; + // double t1, t2, t3, t4, t5; + // t1=pow(((vdd-vt)-vt_to_vdd_ratio),3); + // t2=pow(velocity_index,2.0); + // t3=pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio); + // t4=t1/t2/t3; + // cout < +#include + +#include "Ucache.h" +#include "area.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "const.h" +#include "parameter.h" + +#include +#include + +using namespace std; +using namespace cacti; + +bool mem_array::lt(const mem_array *m1, const mem_array *m2) { + if (m1->Nspd < m2->Nspd) + return true; + else if (m1->Nspd > m2->Nspd) + return false; + else if (m1->Ndwl < m2->Ndwl) + return true; + else if (m1->Ndwl > m2->Ndwl) + return false; + else if (m1->Ndbl < m2->Ndbl) + return true; + else if (m1->Ndbl > m2->Ndbl) + return false; + else if (m1->deg_bl_muxing < m2->deg_bl_muxing) + return true; + else if (m1->deg_bl_muxing > m2->deg_bl_muxing) + return false; + else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) + return true; + else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) + return false; + else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) + return true; + else + return false; +} + +void uca_org_t::find_delay() { + mem_array *data_arr = data_array2; + mem_array *tag_arr = tag_array2; + + // check whether it is a regular cache or scratch ram + if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) { + access_time = data_arr->access_time; + } + // Both tag and data lookup happen in parallel + // and the entire set is sent over the data array h-tree without + // waiting for the way-select signal --TODO add the corresponding + // power overhead Nav + else if (g_ip->fast_access == true) { + access_time = MAX(tag_arr->access_time, data_arr->access_time); + } + // Tag is accessed first. On a hit, way-select signal along with the + // address is sent to read/write the appropriate block in the data + // array + else if (g_ip->is_seq_acc == true) { + access_time = tag_arr->access_time + data_arr->access_time; + } + // Normal access: tag array access and data array access happen in parallel. + // But, the data array will wait for the way-select and transfer only the + // appropriate block over the h-tree. + else { + access_time = + MAX(tag_arr->access_time + data_arr->delay_senseamp_mux_decoder, + data_arr->delay_before_subarray_output_driver) + + data_arr->delay_from_subarray_output_driver_to_output; + } +} + +void uca_org_t::find_energy() { + if (!(g_ip->pure_ram || g_ip->pure_cam || + g_ip->fully_assoc)) //(g_ip->is_cache) + power = data_array2->power + tag_array2->power; + else + power = data_array2->power; +} + +void uca_org_t::find_area() { + if (g_ip->pure_ram || g_ip->pure_cam || + g_ip->fully_assoc) //(g_ip->is_cache == false) + { + cache_ht = data_array2->height; + cache_len = data_array2->width; + } + else { + cache_ht = MAX(tag_array2->height, data_array2->height); + cache_len = tag_array2->width + data_array2->width; + } + area = cache_ht * cache_len; +} + +void uca_org_t::adjust_area() { + double area_adjust; + if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) { + if (data_array2->area_efficiency / 100.0 < 0.2) { + // area_adjust = + // sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2)); + area_adjust = sqrt(0.2 / (data_array2->area_efficiency / 100.0)); + cache_ht = cache_ht / area_adjust; + cache_len = cache_len / area_adjust; + } + } + area = cache_ht * cache_len; +} + +void uca_org_t::find_cyc() { + if ((g_ip->pure_ram || g_ip->pure_cam || + g_ip->fully_assoc)) //(g_ip->is_cache == false) + { + cycle_time = data_array2->cycle_time; + } + else { + cycle_time = MAX(tag_array2->cycle_time, data_array2->cycle_time); + } +} + +uca_org_t ::uca_org_t() : tag_array2(0), data_array2(0), uca_pg_reference(0) { + uca_q = vector(0); +} + +void uca_org_t ::cleanup() { + // uca_org_t * it_uca_org; + if (data_array2 != 0) { + delete data_array2; + data_array2 = 0; + } + + if (tag_array2 != 0) { + delete tag_array2; + tag_array2 = 0; + } + + std::vector::size_type sz = uca_q.size(); + for (int i = sz - 1; i >= 0; i--) { + if (uca_q[i]->data_array2 != 0) { + delete uca_q[i]->data_array2; + uca_q[i]->data_array2 = 0; + } + if (uca_q[i]->tag_array2 != 0) { + delete uca_q[i]->tag_array2; + uca_q[i]->tag_array2 = 0; + } + delete uca_q[i]; + uca_q[i] = 0; + uca_q.pop_back(); + } + + if (uca_pg_reference != 0) { + if (uca_pg_reference->data_array2 != 0) { + delete uca_pg_reference->data_array2; + uca_pg_reference->data_array2 = 0; + } + if (uca_pg_reference->tag_array2 != 0) { + delete uca_pg_reference->tag_array2; + uca_pg_reference->tag_array2 = 0; + } + delete uca_pg_reference; + uca_pg_reference = 0; + } +} + +uca_org_t ::~uca_org_t() { + // cleanup(); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/cacti_interface.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/cacti_interface.h new file mode 100644 index 0000000000..c4cfd18fe3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/cacti_interface.h @@ -0,0 +1,635 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __CACTI_INTERFACE_H__ +#define __CACTI_INTERFACE_H__ + +#include +#include +#include +#include +#include +#include "const.h" + +using namespace std; + +namespace cacti { + +class min_values_t; +class mem_array; +class uca_org_t; + +class powerComponents { + public: + double dynamic; + double leakage; + double gate_leakage; + double short_circuit; + double longer_channel_leakage; + double power_gated_leakage; + double power_gated_with_long_channel_leakage; + + powerComponents() + : dynamic(0), + leakage(0), + gate_leakage(0), + short_circuit(0), + longer_channel_leakage(0), + power_gated_leakage(0), + power_gated_with_long_channel_leakage(0) {} + powerComponents(const powerComponents &obj) { *this = obj; } + powerComponents &operator=(const powerComponents &rhs) { + dynamic = rhs.dynamic; + leakage = rhs.leakage; + gate_leakage = rhs.gate_leakage; + short_circuit = rhs.short_circuit; + longer_channel_leakage = rhs.longer_channel_leakage; + power_gated_leakage = rhs.power_gated_leakage; + power_gated_with_long_channel_leakage = + rhs.power_gated_with_long_channel_leakage; + return *this; + } + void reset() { + dynamic = 0; + leakage = 0; + gate_leakage = 0; + short_circuit = 0; + longer_channel_leakage = 0; + power_gated_leakage = 0; + power_gated_with_long_channel_leakage = 0; + } + + friend powerComponents operator+(const powerComponents &x, + const powerComponents &y); + friend powerComponents operator*(const powerComponents &x, + double const *const y); +}; + +class powerDef { + public: + powerComponents readOp; + powerComponents writeOp; + powerComponents searchOp; // Sheng: for CAM and FA + + powerDef() : readOp(), writeOp(), searchOp() {} + void reset() { + readOp.reset(); + writeOp.reset(); + searchOp.reset(); + } + + friend powerDef operator+(const powerDef &x, const powerDef &y); + friend powerDef operator*(const powerDef &x, double const *const y); +}; + +enum Wire_type { + Global /* gloabl wires with repeaters */, + Global_5 /* 5% delay penalty */, + Global_10 /* 10% delay penalty */, + Global_20 /* 20% delay penalty */, + Global_30 /* 30% delay penalty */, + Low_swing /* differential low power wires with high area overhead */, + Semi_global /* mid-level wires with repeaters*/, + Transmission /* tranmission lines with high area overhead */, + Optical /* optical wires */, + Invalid_wtype +}; + +class InputParameter { + public: + InputParameter(); + void parse_cfg(const string &infile); + + bool + error_checking(); // return false if the input parameters are problematic + void display_ip(); + + unsigned int cache_sz; // in bytes + unsigned int line_sz; + unsigned int assoc; + unsigned int nbanks; + unsigned int out_w; // == nr_bits_out + bool specific_tag; + unsigned int tag_w; + unsigned int access_mode; + unsigned int obj_func_dyn_energy; + unsigned int obj_func_dyn_power; + unsigned int obj_func_leak_power; + unsigned int obj_func_cycle_t; + + double F_sz_nm; // feature size in nm + double F_sz_um; // feature size in um + bool specific_hp_vdd; // whether to have user defined vdd that is different + // from ITRS + double hp_Vdd; // user specified vdd + bool specific_lstp_vdd; // whether to have user defined vdd that is different + // from ITRS + double lstp_Vdd; + bool specific_lop_vdd; // whether to have user defined vdd that is different + // from ITRS + double lop_Vdd; + bool specific_vcc_min; // whether to have user defined vcc_min for + // power-gating that is different from the value + // constrained by technology for maintaining states + double user_defined_vcc_min; + bool user_defined_vcc_underflow; // flag to indicate when user defined vcc is + // too low for the circuit to retain state + unsigned int num_rw_ports; + unsigned int num_rd_ports; + unsigned int num_wr_ports; + unsigned int num_se_rd_ports; // number of single ended read ports + unsigned int num_search_ports; // number of search ports for CAM + bool is_main_mem; + bool is_cache; + bool pure_ram; + bool pure_cam; + bool rpters_in_htree; // if there are repeaters in htree segment + unsigned int ver_htree_wires_over_array; + unsigned int broadcast_addr_din_over_ver_htrees; + unsigned int temp; + + unsigned int ram_cell_tech_type; + unsigned int peri_global_tech_type; + unsigned int data_arr_ram_cell_tech_type; + unsigned int data_arr_peri_global_tech_type; + unsigned int tag_arr_ram_cell_tech_type; + unsigned int tag_arr_peri_global_tech_type; + + unsigned int burst_len; + unsigned int int_prefetch_w; + unsigned int page_sz_bits; + + unsigned int ic_proj_type; // interconnect_projection_type + unsigned int wire_is_mat_type; // wire_inside_mat_type + unsigned int wire_os_mat_type; // wire_outside_mat_type + enum Wire_type wt; + int force_wiretype; + bool print_input_args; + unsigned int nuca_cache_sz; // TODO + int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm; + bool force_cache_config; + + int cache_level; + int cores; + int nuca_bank_count; + int force_nuca_bank; + + int delay_wt, dynamic_power_wt, leakage_power_wt, cycle_time_wt, area_wt; + int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca, + cycle_time_wt_nuca, area_wt_nuca; + + int delay_dev, dynamic_power_dev, leakage_power_dev, cycle_time_dev, area_dev; + int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca, + cycle_time_dev_nuca, area_dev_nuca; + int ed; // ED or ED2 optimization + int nuca; + + bool fast_access; + unsigned int block_sz; // bytes + unsigned int tag_assoc; + unsigned int data_assoc; + bool is_seq_acc; + bool fully_assoc; + unsigned int nsets; // == number_of_sets + int print_detail; + + bool add_ecc_b_; + // parameters for design constraint + double throughput; + double latency; + bool pipelinable; + int pipeline_stages; + int per_stage_vector; + bool with_clock_grid; + + bool array_power_gated; + bool bitline_floating; + bool wl_power_gated; + bool cl_power_gated; + bool interconect_power_gated; + bool power_gating; + + double perfloss; + + bool cl_vertical; + + std::vector dvs_voltage; + + bool long_channel_device; +}; + +typedef struct { + int Ndwl; + int Ndbl; + double Nspd; + int deg_bl_muxing; + int Ndsam_lev_1; + int Ndsam_lev_2; + int number_activated_mats_horizontal_direction; + int number_subbanks; + int page_size_in_bits; + double delay_route_to_bank; + double delay_crossbar; + double delay_addr_din_horizontal_htree; + double delay_addr_din_vertical_htree; + double delay_row_predecode_driver_and_block; + double delay_row_decoder; + double delay_bitlines; + double delay_sense_amp; + double delay_subarray_output_driver; + double delay_bit_mux_predecode_driver_and_block; + double delay_bit_mux_decoder; + double delay_senseamp_mux_lev_1_predecode_driver_and_block; + double delay_senseamp_mux_lev_1_decoder; + double delay_senseamp_mux_lev_2_predecode_driver_and_block; + double delay_senseamp_mux_lev_2_decoder; + double delay_input_htree; + double delay_output_htree; + double delay_dout_vertical_htree; + double delay_dout_horizontal_htree; + double delay_comparator; + double access_time; + double cycle_time; + double multisubbank_interleave_cycle_time; + double delay_request_network; + double delay_inside_mat; + double delay_reply_network; + double trcd; + double cas_latency; + double precharge_delay; + powerDef power_routing_to_bank; + powerDef power_addr_input_htree; + powerDef power_data_input_htree; + powerDef power_data_output_htree; + powerDef power_addr_horizontal_htree; + powerDef power_datain_horizontal_htree; + powerDef power_dataout_horizontal_htree; + powerDef power_addr_vertical_htree; + powerDef power_datain_vertical_htree; + powerDef power_row_predecoder_drivers; + powerDef power_row_predecoder_blocks; + powerDef power_row_decoders; + powerDef power_bit_mux_predecoder_drivers; + powerDef power_bit_mux_predecoder_blocks; + powerDef power_bit_mux_decoders; + powerDef power_senseamp_mux_lev_1_predecoder_drivers; + powerDef power_senseamp_mux_lev_1_predecoder_blocks; + powerDef power_senseamp_mux_lev_1_decoders; + powerDef power_senseamp_mux_lev_2_predecoder_drivers; + powerDef power_senseamp_mux_lev_2_predecoder_blocks; + powerDef power_senseamp_mux_lev_2_decoders; + powerDef power_bitlines; + powerDef power_sense_amps; + powerDef power_prechg_eq_drivers; + powerDef power_output_drivers_at_subarray; + powerDef power_dataout_vertical_htree; + powerDef power_comparators; + powerDef power_crossbar; + powerDef total_power; + double area; + double all_banks_height; + double all_banks_width; + double bank_height; + double bank_width; + double subarray_memory_cell_area_height; + double subarray_memory_cell_area_width; + double mat_height; + double mat_width; + double routing_area_height_within_bank; + double routing_area_width_within_bank; + double area_efficiency; + // double perc_power_dyn_routing_to_bank; + // double perc_power_dyn_addr_horizontal_htree; + // double perc_power_dyn_datain_horizontal_htree; + // double perc_power_dyn_dataout_horizontal_htree; + // double perc_power_dyn_addr_vertical_htree; + // double perc_power_dyn_datain_vertical_htree; + // double perc_power_dyn_row_predecoder_drivers; + // double perc_power_dyn_row_predecoder_blocks; + // double perc_power_dyn_row_decoders; + // double perc_power_dyn_bit_mux_predecoder_drivers; + // double perc_power_dyn_bit_mux_predecoder_blocks; + // double perc_power_dyn_bit_mux_decoders; + // double perc_power_dyn_senseamp_mux_lev_1_predecoder_drivers; + // double perc_power_dyn_senseamp_mux_lev_1_predecoder_blocks; + // double perc_power_dyn_senseamp_mux_lev_1_decoders; + // double perc_power_dyn_senseamp_mux_lev_2_predecoder_drivers; + // double perc_power_dyn_senseamp_mux_lev_2_predecoder_blocks; + // double perc_power_dyn_senseamp_mux_lev_2_decoders; + // double perc_power_dyn_bitlines; + // double perc_power_dyn_sense_amps; + // double perc_power_dyn_prechg_eq_drivers; + // double perc_power_dyn_subarray_output_drivers; + // double perc_power_dyn_dataout_vertical_htree; + // double perc_power_dyn_comparators; + // double perc_power_dyn_crossbar; + // double perc_power_dyn_spent_outside_mats; + // double perc_power_leak_routing_to_bank; + // double perc_power_leak_addr_horizontal_htree; + // double perc_power_leak_datain_horizontal_htree; + // double perc_power_leak_dataout_horizontal_htree; + // double perc_power_leak_addr_vertical_htree; + // double perc_power_leak_datain_vertical_htree; + // double perc_power_leak_row_predecoder_drivers; + // double perc_power_leak_row_predecoder_blocks; + // double perc_power_leak_row_decoders; + // double perc_power_leak_bit_mux_predecoder_drivers; + // double perc_power_leak_bit_mux_predecoder_blocks; + // double perc_power_leak_bit_mux_decoders; + // double perc_power_leak_senseamp_mux_lev_1_predecoder_drivers; + // double perc_power_leak_senseamp_mux_lev_1_predecoder_blocks; + // double perc_power_leak_senseamp_mux_lev_1_decoders; + // double perc_power_leak_senseamp_mux_lev_2_predecoder_drivers; + // double perc_power_leak_senseamp_mux_lev_2_predecoder_blocks; + // double perc_power_leak_senseamp_mux_lev_2_decoders; + // double perc_power_leak_bitlines; + // double perc_power_leak_sense_amps; + // double perc_power_leak_prechg_eq_drivers; + // double perc_power_leak_subarray_output_drivers; + // double perc_power_leak_dataout_vertical_htree; + // double perc_power_leak_comparators; + // double perc_power_leak_crossbar; + // double perc_leak_mats; + // double perc_active_mats; + double refresh_power; + double dram_refresh_period; + double dram_array_availability; + double dyn_read_energy_from_closed_page; + double dyn_read_energy_from_open_page; + double leak_power_subbank_closed_page; + double leak_power_subbank_open_page; + double leak_power_request_and_reply_networks; + double activate_energy; + double read_energy; + double write_energy; + double precharge_energy; +} results_mem_array; + +class uca_org_t { + public: + mem_array *tag_array2; + mem_array *data_array2; + double access_time; + double cycle_time; + double area; + double area_efficiency; + powerDef power; + double leak_power_with_sleep_transistors_in_mats; + double cache_ht; + double cache_len; + char file_n[100]; + double vdd_periph_global; + bool valid; + results_mem_array tag_array; + results_mem_array data_array; + std::vector + uca_q; // for results share the same settings (g_ip + // and dyn_p) but with different tech settings + // such as DVFS + uca_org_t * + uca_pg_reference; // for references results when power gating is enabled. + uca_org_t(); + void find_delay(); + void find_energy(); + void find_area(); + void find_cyc(); + void adjust_area(); // for McPAT only to adjust routing overhead + void cleanup(); + ~uca_org_t(); +}; + +void reconfigure(InputParameter *local_interface, uca_org_t *fin_res); + +uca_org_t cacti_interface(const string &infile_name); +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface(InputParameter *const local_interface); +// McPAT's plain interface, please keep !!! +uca_org_t init_interface(InputParameter *const local_interface); +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, int excl_write_ports, int single_ended_read_ports, + int search_ports, int banks, double tech_node, int output_width, + int specific_tag, int tag_width, int access_mode, int cache, int main_mem, + int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, + int obj_func_cycle_time, int obj_func_area, int dev_func_delay, + int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, + int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, int wire_inside_mat_type_in, + int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, + int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, + int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, int PAGE_SIZE_BITS_in, + int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, + int wiretype, int force_config, int ndwl, int ndbl, int nspd, int ndcm, + int ndsam1, int ndsam2, int ecc); +// int cache_size, +// int line_size, +// int associativity, +// int rw_ports, +// int excl_read_ports, +// int excl_write_ports, +// int single_ended_read_ports, +// int banks, +// double tech_node, +// int output_width, +// int specific_tag, +// int tag_width, +// int access_mode, +// int cache, +// int main_mem, +// int obj_func_delay, +// int obj_func_dynamic_power, +// int obj_func_leakage_power, +// int obj_func_area, +// int obj_func_cycle_time, +// int dev_func_delay, +// int dev_func_dynamic_power, +// int dev_func_leakage_power, +// int dev_func_area, +// int dev_func_cycle_time, +// int temp, +// int data_arr_ram_cell_tech_flavor_in, +// int data_arr_peri_global_tech_flavor_in, +// int tag_arr_ram_cell_tech_flavor_in, +// int tag_arr_peri_global_tech_flavor_in, +// int interconnect_projection_type_in, +// int wire_inside_mat_type_in, +// int wire_outside_mat_type_in, +// int REPEATERS_IN_HTREE_SEGMENTS_in, +// int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, +// int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, +//// double MAXAREACONSTRAINT_PERC_in, +//// double MAXACCTIMECONSTRAINT_PERC_in, +//// double MAX_PERC_DIFF_IN_DELAY_FROM_BEST_DELAY_REPEATER_SOLUTION_in, +// int PAGE_SIZE_BITS_in, +// int BURST_LENGTH_in, +// int INTERNAL_PREFETCH_WIDTH_in); + +// Naveen's interface +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, int excl_write_ports, int single_ended_read_ports, + int banks, double tech_node, int page_sz, int burst_length, int pre_width, + int output_width, int specific_tag, int tag_width, + int access_mode, // 0 normal, 1 seq, 2 fast + int cache, // scratch ram or cache + int main_mem, int obj_func_delay, int obj_func_dynamic_power, + int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, + int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, + int dev_func_area, int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, // 0 - aggressive, 1 - normal + int wire_inside_mat_type_in, int wire_outside_mat_type_in, + int is_nuca, // 0 - UCA, 1 - NUCA + int core_count, + int cache_level, // 0 - L2, 1 - L3 + int nuca_bank_count, int nuca_obj_func_delay, + int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, + int nuca_obj_func_area, int nuca_obj_func_cycle_time, + int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, + int nuca_dev_func_leakage_power, int nuca_dev_func_area, + int nuca_dev_func_cycle_time, + int REPEATERS_IN_HTREE_SEGMENTS_in, // TODO for now only wires with + // repeaters are supported + int p_input); + +class mem_array { + public: + int Ndcm; + int Ndwl; + int Ndbl; + double Nspd; + int deg_bl_muxing; + int Ndsam_lev_1; + int Ndsam_lev_2; + double access_time; + double cycle_time; + double multisubbank_interleave_cycle_time; + double area_ram_cells; + double area; + powerDef power; + double delay_senseamp_mux_decoder; + double delay_before_subarray_output_driver; + double delay_from_subarray_output_driver_to_output; + double height; + double width; + + double mat_height; + double mat_length; + double subarray_length; + double subarray_height; + + double delay_route_to_bank, delay_input_htree, + delay_row_predecode_driver_and_block, delay_row_decoder, delay_bitlines, + delay_sense_amp, delay_subarray_output_driver, delay_dout_htree, + delay_comparator, delay_matchlines; + + double all_banks_height, all_banks_width, area_efficiency; + + powerDef power_routing_to_bank; + powerDef power_addr_input_htree; + powerDef power_data_input_htree; + powerDef power_data_output_htree; + powerDef power_htree_in_search; + powerDef power_htree_out_search; + powerDef power_row_predecoder_drivers; + powerDef power_row_predecoder_blocks; + powerDef power_row_decoders; + powerDef power_bit_mux_predecoder_drivers; + powerDef power_bit_mux_predecoder_blocks; + powerDef power_bit_mux_decoders; + powerDef power_senseamp_mux_lev_1_predecoder_drivers; + powerDef power_senseamp_mux_lev_1_predecoder_blocks; + powerDef power_senseamp_mux_lev_1_decoders; + powerDef power_senseamp_mux_lev_2_predecoder_drivers; + powerDef power_senseamp_mux_lev_2_predecoder_blocks; + powerDef power_senseamp_mux_lev_2_decoders; + powerDef power_bitlines; + powerDef power_sense_amps; + powerDef power_prechg_eq_drivers; + powerDef power_output_drivers_at_subarray; + powerDef power_dataout_vertical_htree; + powerDef power_comparators; + + powerDef power_cam_bitline_precharge_eq_drv; + powerDef power_searchline; + powerDef power_searchline_precharge; + powerDef power_matchlines; + powerDef power_matchline_precharge; + powerDef power_matchline_to_wordline_drv; + + min_values_t *arr_min; + enum Wire_type wt; + + // dram stats + double activate_energy, read_energy, write_energy, precharge_energy, + refresh_power, leak_power_subbank_closed_page, + leak_power_subbank_open_page, leak_power_request_and_reply_networks; + + double precharge_delay; + + // Power-gating stats + double array_leakage; + double wl_leakage; + double cl_leakage; + + double sram_sleep_tx_width, wl_sleep_tx_width, cl_sleep_tx_width; + double sram_sleep_tx_area, wl_sleep_tx_area, cl_sleep_tx_area; + double sram_sleep_wakeup_latency, wl_sleep_wakeup_latency, + cl_sleep_wakeup_latency, bl_floating_wakeup_latency; + double sram_sleep_wakeup_energy, wl_sleep_wakeup_energy, + cl_sleep_wakeup_energy, bl_floating_wakeup_energy; + + int num_active_mats; + int num_submarray_mats; + + double long_channel_leakage_reduction_periperal; + double long_channel_leakage_reduction_memcell; + + static bool lt(const mem_array *m1, const mem_array *m2); +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/component.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/component.cc new file mode 100644 index 0000000000..d076e6bfc2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/component.cc @@ -0,0 +1,203 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include +#include + +#include "bank.h" +#include "component.h" +#include "decoder.h" + +using namespace std; +using namespace cacti; + +Component::Component() : area(), power(), rt_power(), delay(0) {} + +Component::~Component() {} + +double Component::compute_diffusion_width(int num_stacked_in, + int num_folded_tr) { + double w_poly = g_ip->F_sz_um; + double spacing_poly_to_poly = + g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact; + double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain + num_stacked_in * w_poly + + (num_stacked_in - 1) * g_tp.spacing_poly_to_poly; + + if (num_folded_tr > 1) { + total_diff_w += + (num_folded_tr - 2) * 2 * spacing_poly_to_poly + + (num_folded_tr - 1) * num_stacked_in * w_poly + + (num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly; + } + + return total_diff_w; +} + +double Component::compute_gate_area(int gate_type, int num_inputs, + double w_pmos, double w_nmos, + double h_gate) { + if (w_pmos <= 0.0 || w_nmos <= 0.0) { + return 0.0; + } + + double w_folded_pmos, w_folded_nmos; + int num_folded_pmos, num_folded_nmos; + double total_ndiff_w, total_pdiff_w; + Area gate; + + double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL; + double ratio_p_to_n = w_pmos / (w_pmos + w_nmos); + + if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0) { + return 0.0; + } + + w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n; + w_folded_nmos = + (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n); + assert(w_folded_pmos > 0); + + num_folded_pmos = (int)(ceil(w_pmos / w_folded_pmos)); + num_folded_nmos = (int)(ceil(w_nmos / w_folded_nmos)); + + switch (gate_type) { + case INV: + total_ndiff_w = compute_diffusion_width(1, num_folded_nmos); + total_pdiff_w = compute_diffusion_width(1, num_folded_pmos); + break; + + case NOR: + total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos); + total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos); + break; + + case NAND: + total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos); + total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos); + break; + default: + cout << "Unknown gate type: " << gate_type << endl; + exit(1); + } + + gate.w = MAX(total_ndiff_w, total_pdiff_w); + + if (w_folded_nmos > w_nmos) { + // means that the height of the gate can + // be made smaller than the input height specified, so calculate the height + // of the gate. + gate.h = + w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL; + } + else { + gate.h = h_gate; + } + return gate.get_area(); +} + +double Component::compute_tr_width_after_folding( + double input_width, + double threshold_folding_width) { // This is actually the width of the cell + // not the width of a device. + // The width of a cell and the width of a device is orthogonal. + if (input_width <= 0) { + return 0; + } + + int num_folded_tr = (int)(ceil(input_width / threshold_folding_width)); + double spacing_poly_to_poly = + g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact; + double width_poly = g_ip->F_sz_um; + double total_diff_width = + num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly; + + return total_diff_width; +} + +double Component::height_sense_amplifier(double pitch_sense_amp) { + // compute the height occupied by all PMOS transistors + double h_pmos_tr = + compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 + + compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) + + 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS; + + // compute the height occupied by all NMOS transistors + double h_nmos_tr = + compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 + + compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) + + 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS; + + // compute total height by considering gap between the p and n diffusion areas + return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS; +} + +int Component::logical_effort(int num_gates_min, double g, double F, + double *w_n, double *w_p, double C_load, + double p_to_n_sz_ratio, bool is_dram_, + bool is_wl_tr_, double max_w_nmos) { + int num_gates = (int)(log(F) / log(fopt)); + + // check if num_gates is odd. if so, add 1 to make it even + num_gates += (num_gates % 2) ? 1 : 0; + num_gates = MAX(num_gates, num_gates_min); + + // recalculate the effective fanout of each stage + double f = pow(F, 1.0 / num_gates); + int i = num_gates - 1; + double C_in = C_load / f; + w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / + gate_C(1, 0, is_dram_, false, is_wl_tr_); + w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_); + w_p[i] = p_to_n_sz_ratio * w_n[i]; + + if (w_n[i] > max_w_nmos) { + double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, + is_wl_tr_); + F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_); + num_gates = (int)(log(F) / log(fopt)) + 1; + num_gates += (num_gates % 2) ? 1 : 0; + num_gates = MAX(num_gates, num_gates_min); + f = pow(F, 1.0 / (num_gates - 1)); + i = num_gates - 1; + w_n[i] = max_w_nmos; + w_p[i] = p_to_n_sz_ratio * w_n[i]; + } + + for (i = num_gates - 2; i >= 1; i--) { + w_n[i] = MAX(w_n[i + 1] / f, g_tp.min_w_nmos_); + w_p[i] = p_to_n_sz_ratio * w_n[i]; + } + + assert(num_gates <= MAX_NUMBER_GATES_STAGE); + return num_gates; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/component.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/component.h new file mode 100644 index 0000000000..713fe4b086 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/component.h @@ -0,0 +1,73 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __COMPONENT_H__ +#define __COMPONENT_H__ + +#include "area.h" +#include "parameter.h" + +using namespace std; + +namespace cacti { + +class Crossbar; +class Bank; + +class Component { + public: + Component(); + ~Component(); + + Area area; + powerDef power, rt_power; + double delay; + double cycle_time; + + double compute_gate_area(int gate_type, int num_inputs, double w_pmos, + double w_nmos, double h_gate); + + double compute_tr_width_after_folding(double input_width, + double threshold_folding_width); + double height_sense_amplifier(double pitch_sense_amp); + + protected: + int logical_effort(int num_gates_min, double g, double F, double *w_n, + double *w_p, double C_load, double p_to_n_sz_ratio, + bool is_dram_, bool is_wl_tr_, double max_w_nmos); + + private: + double compute_diffusion_width(int num_stacked_in, int num_folded_tr); +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/const.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/const.h new file mode 100644 index 0000000000..b92ffeb3a9 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/const.h @@ -0,0 +1,271 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __CONST_H__ +#define __CONST_H__ + +#include +#include +#include +#include +#include + +/* The following are things you might want to change + * when compiling + */ + +/* + * Address bits in a word, and number of output bits from the cache + */ + +/* +was: #define ADDRESS_BITS 32 +now: I'm using 42 bits as in the Power4, +since that's bigger then the 36 bits on the Pentium 4 +and 40 bits on the Opteron +*/ +const int ADDRESS_BITS = 42; + +/*dt: In addition to the tag bits, the tags also include 1 valid bit, 1 dirty + bit, 2 bits for a 4-state cache coherency protocoll (MESI), 1 bit for MRU + (change this to log(ways) for full LRU). So in total we have 1 + 1 + 2 + 1 = 5 +*/ +const int EXTRA_TAG_BITS = 5; + +/* limits on the various N parameters */ + +const unsigned int MAXDATAN = 512; // maximum for Ndwl and Ndbl +const unsigned int MAXSUBARRAYS = + 1048576; // maximum subarrays for data and tag arrays +const unsigned int MAXDATASPD = 256; // maximum for Nspd +const unsigned int MAX_COL_MUX = 256; + +#define ROUTER_TYPES 3 +#define WIRE_TYPES 6 + +const double Cpolywire = 0; + +/* Threshold voltages (as a proportion of Vdd) + If you don't know them, set all values to 0.5 */ +#define VTHFA1 0.452 +#define VTHFA2 0.304 +#define VTHFA3 0.420 +#define VTHFA4 0.413 +#define VTHFA5 0.405 +#define VTHFA6 0.452 +#define VSINV 0.452 +#define VTHCOMPINV 0.437 +#define VTHMUXNAND 0.548 // TODO : this constant must be revisited +#define VTHEVALINV 0.452 +#define VTHSENSEEXTDRV 0.438 + +// WmuxdrvNANDn and WmuxdrvNANDp are no longer being used but it's part of the +// old delay_comparator function which we are using exactly as it used to be, +// so just setting these to 0 +const double WmuxdrvNANDn = 0; +const double WmuxdrvNANDp = 0; + +/*===================================================================*/ +/* + * The following are things you probably wouldn't want to change. + */ + +#define BIGNUM 1e30 +#define INF 9999999 +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/* Used to communicate with the horowitz model */ +#define RISE 1 +#define FALL 0 +#define NCH 1 +#define PCH 0 + +#define EPSILON \ + 0.5 // v4.1: This constant is being used in order to fix floating point -> + // integer +// conversion problems that were occuring within CACTI. Typical problem that was +// occuring was that with different compilers a floating point number like 3.0 +// would get represented as either 2.9999....or 3.00000001 and then the integer +// part of the floating point number (3.0) would be computed differently +// depending on the compiler. What we are doing now is to replace int (x) with +// (int) (x+EPSILON) where EPSILON is 0.5. This would fix such problems. Note +// that this works only when x is an integer >= 0. +/* + * Sheng thinks this is more a solution to solve the simple truncate problem + * (http://www.cs.tut.fi/~jkorpela/round.html) rather than the problem mentioned + * above. Unfortunately, this solution causes nasty bugs (different results when + * using O0 and O3). Moreover, round is not correct in CACTI since when an extra + * fraction of bit/line is needed, we need to provide a complete bit/line even + * the fraction is just 0.01. So, in later version than 6.5 we use (int)ceil() + * to get double to int conversion. + */ + +#define EPSILON2 0.1 +#define EPSILON3 0.6 + +#define MINSUBARRAYROWS \ + 16 // For simplicity in modeling, for the row decoding structure, we assume +// that each row predecode block is composed of at least one 2-4 decoder. When +// the outputs from the row predecode blocks are combined this means that there +// are at least 4*4=16 row decode outputs +#define MAXSUBARRAYROWS \ + 262144 // Each row predecode block produces a max of 2^9 outputs. So +// the maximum number of row decode outputs will be 2^9*2^9 +#define MINSUBARRAYCOLS 2 +#define MAXSUBARRAYCOLS 262144 + +#define INV 0 +#define NOR 1 +#define NAND 2 + +#define NUMBER_TECH_FLAVORS 4 + +#define NUMBER_INTERCONNECT_PROJECTION_TYPES 2 // aggressive and conservative +// 0 = Aggressive projections, 1 = Conservative projections +#define NUMBER_WIRE_TYPES 4 // local, semi-global and global +// 1 = 'Semi-global' wire type, 2 = 'Global' wire type + +const int dram_cell_tech_flavor = 3; + +#define VBITSENSEMIN \ + 0.08 // minimum bitline sense voltage is fixed to be 80 + // mV. + +#define fopt 4.0 + +#define INPUT_WIRE_TO_INPUT_GATE_CAP_RATIO 0 +#define BUFFER_SEPARATION_LENGTH_MULTIPLIER 1 +#define NUMBER_MATS_PER_REDUNDANT_MAT 8 + +#define NUMBER_STACKED_DIE_LAYERS 1 + +// this variable can be set to carry out solution optimization for +// a maximum area allocation. +#define STACKED_DIE_LAYER_ALLOTED_AREA_mm2 0 // 6.24 //6.21//71.5 + +// this variable can also be employed when solution optimization +// with maximum area allocation is carried out. +#define MAX_PERCENT_AWAY_FROM_ALLOTED_AREA 50 + +// this variable can also be employed when solution optimization +// with maximum area allocation is carried out. +#define MIN_AREA_EFFICIENCY 20 + +// this variable can be employed when solution with a desired +// aspect ratio is required. +#define STACKED_DIE_LAYER_ASPECT_RATIO 1 + +// this variable can be employed when solution with a desired +// aspect ratio is required. +#define MAX_PERCENT_AWAY_FROM_ASPECT_RATIO 101 + +// this variable can be employed to carry out solution optimization +// for a certain target random cycle time. +#define TARGET_CYCLE_TIME_ns 1000000000 + +#define NUMBER_PIPELINE_STAGES 4 + +// this can be used to model the length of interconnect +// between a bank and a crossbar +#define LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR 0 // 3791 // 2880//micron + +#define IS_CROSSBAR 0 +#define NUMBER_INPUT_PORTS_CROSSBAR 8 +#define NUMBER_OUTPUT_PORTS_CROSSBAR 8 +#define NUMBER_SIGNALS_PER_PORT_CROSSBAR 256 + +#define MAT_LEAKAGE_REDUCTION_DUE_TO_SLEEP_TRANSISTORS_FACTOR 1 +#define LEAKAGE_REDUCTION_DUE_TO_LONG_CHANNEL_HP_TRANSISTORS_FACTOR 1 + +#define PAGE_MODE 0 + +#define MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA 60 +// We are actually not using this variable in the CACTI code. We just want to +// acknowledge that this current should be multiplied by the DDR(n) system VDD +// value to compute the standby power consumed during precharge. + +const double VDD_STORAGE_LOSS_FRACTION_WORST = 0.125; +const double CU_RESISTIVITY = 0.022; // ohm-micron +const double BULK_CU_RESISTIVITY = 0.018; // ohm-micron +const double PERMITTIVITY_FREE_SPACE = 8.854e-18; // F/micron + +const static uint32_t sram_num_cells_wl_stitching_ = 16; +const static uint32_t dram_num_cells_wl_stitching_ = 64; +const static uint32_t comm_dram_num_cells_wl_stitching_ = 256; +const static double num_bits_per_ecc_b_ = 8.0; + +const double bit_to_byte = 8.0; + +#define MAX_NUMBER_GATES_STAGE 20 +#define MAX_NUMBER_HTREE_NODES 20 +#define NAND2_LEAK_STACK_FACTOR 0.2 +#define NAND3_LEAK_STACK_FACTOR 0.2 +#define NOR2_LEAK_STACK_FACTOR 0.2 +#define INV_LEAK_STACK_FACTOR 0.5 +#define MAX_NUMBER_ARRAY_PARTITIONS 1000000 + +// abbreviations used in this project +// ---------------------------------- +// +// num : number +// rw : read/write +// rd : read +// wr : write +// se : single-ended +// sz : size +// F : feature +// w : width +// h : height or horizontal +// v : vertical or velocity + +enum ram_cell_tech_type_num { + itrs_hp = 0, + itrs_lstp = 1, + itrs_lop = 2, + lp_dram = 3, + comm_dram = 4 +}; + +const double pppm[4] = {1, 1, 1, 1}; +const double pppm_lkg[4] = {0, 1, 1, 0}; +const double pppm_dyn[4] = {1, 0, 0, 0}; +const double pppm_Isub[4] = {0, 1, 0, 0}; +const double pppm_Ig[4] = {0, 0, 1, 0}; +const double pppm_sc[4] = {0, 0, 0, 1}; + +const double Ilinear_to_Isat_ratio = 2.0; + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/crossbar.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/crossbar.cc new file mode 100644 index 0000000000..e8566672ca --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/crossbar.cc @@ -0,0 +1,183 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "crossbar.h" + +#define ASPECT_THRESHOLD .8 +#define ADJ 1 +using namespace cacti; + +Crossbar::Crossbar(double n_inp_, double n_out_, double flit_size_, + TechnologyParameter::DeviceType *dt) + : n_inp(n_inp_), n_out(n_out_), flit_size(flit_size_), deviceType(dt) { + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + Vdd = dt->Vdd; + CB_ADJ = 1; +} + +Crossbar::~Crossbar() {} + +double Crossbar::output_buffer() { + // Wire winit(4, 4); + double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; + Wire w1(g_ip->wt, l_eff); + // double s1 = w1.repeater_size *l_eff*ADJ/w1.repeater_spacing; + double s1 = + w1.repeater_size * + (l_eff < w1.repeater_spacing ? l_eff * ADJ / w1.repeater_spacing : ADJ); + double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; + // the model assumes input capacitance of the wire driver = input capacitance + // of nand + nor = input cap of the driver transistor + TriS1 = s1 * (1 + pton_size) / (2 + pton_size + 1 + 2 * pton_size); + TriS2 = s1; // driver transistor + + if (TriS1 < 1) + TriS1 = 1; + + double input_cap = gate_C(TriS1 * (2 * min_w_pmos + g_tp.min_w_nmos_), 0) + + gate_C(TriS1 * (min_w_pmos + 2 * g_tp.min_w_nmos_), 0); + // input_cap += drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + // + + // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 + + // gate_C(TriS2*g_tp.min_w_nmos_, 0)+ + // drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 + + // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + // gate_C(TriS2*min_w_pmos, 0); + tri_int_cap = drain_C_(TriS1 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 + + gate_C(TriS2 * g_tp.min_w_nmos_, 0) + + drain_C_(TriS1 * min_w_pmos, NCH, 1, 1, g_tp.cell_h_def) * 2 + + drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(TriS2 * min_w_pmos, 0); + double output_cap = + drain_C_(TriS2 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(TriS2 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def); + double ctr_cap = gate_C(TriS2 * (min_w_pmos + g_tp.min_w_nmos_), 0); + + tri_inp_cap = input_cap; + tri_out_cap = output_cap; + tri_ctr_cap = ctr_cap; + return input_cap + output_cap + ctr_cap; +} + +void Crossbar::compute_power() { + Wire winit(4, 4); + double tri_cap = output_buffer(); + assert(tri_cap > 0); + // area of a tristate logic + double g_area = compute_gate_area(INV, 1, TriS2 * g_tp.min_w_nmos_, + TriS2 * min_w_pmos, g_tp.cell_h_def); + g_area *= 2; // to model area of output transistors + g_area += compute_gate_area(NAND, 2, TriS1 * 2 * g_tp.min_w_nmos_, + TriS1 * min_w_pmos, g_tp.cell_h_def); + g_area += compute_gate_area(NOR, 2, TriS1 * g_tp.min_w_nmos_, + TriS1 * 2 * min_w_pmos, g_tp.cell_h_def); + double width /*per tristate*/ = g_area / (CB_ADJ * g_tp.cell_h_def); + // effective no. of tristate buffers that need to be laid side by side + int ntri = (int)ceil(g_tp.cell_h_def / (g_tp.wire_outside_mat.pitch)); + double wire_len = MAX(width * ntri * n_out, + flit_size * g_tp.wire_outside_mat.pitch * n_out); + Wire w1(g_ip->wt, wire_len); + + area.w = wire_len; + area.h = g_tp.wire_outside_mat.pitch * n_inp * flit_size * CB_ADJ; + Wire w2(g_ip->wt, area.h); + + double aspect_ratio_cb = (area.h / area.w) * (n_out / n_inp); + if (aspect_ratio_cb > 1) + aspect_ratio_cb = 1 / aspect_ratio_cb; + + if (aspect_ratio_cb < ASPECT_THRESHOLD) { + if (n_out > 2 && n_inp > 2) { + CB_ADJ += 0.2; + // cout << "CB ADJ " << CB_ADJ << endl; + if (CB_ADJ < 4) { + this->compute_power(); + } + } + } + + power.readOp.dynamic = + (w1.power.readOp.dynamic + w2.power.readOp.dynamic + + (tri_inp_cap * n_out + tri_out_cap * n_inp + tri_ctr_cap + tri_int_cap) * + Vdd * Vdd) * + flit_size; + power.readOp.leakage = n_inp * n_out * flit_size * + (cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS2 * 2, + min_w_pmos * TriS2 * 2, 1, inv) * + Vdd + + cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, + min_w_pmos * TriS1 * 3, 2, nand) * + Vdd + + cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, + min_w_pmos * TriS1 * 3, 2, nor) * + Vdd + + w1.power.readOp.leakage + w2.power.readOp.leakage); + power.readOp.gate_leakage = + n_inp * n_out * flit_size * + (cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2, 1, + inv) * + Vdd + + cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 2, + nand) * + Vdd + + cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 2, + nor) * + Vdd + + w1.power.readOp.gate_leakage + w2.power.readOp.gate_leakage); + + // delay calculation + double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; + Wire wdriver(g_ip->wt, l_eff); + double res = g_tp.wire_outside_mat.R_per_um * (area.w + area.h) + + tr_R_on(g_tp.min_w_nmos_ * wdriver.repeater_size, NCH, 1); + double cap = g_tp.wire_outside_mat.C_per_um * (area.w + area.h) + + n_out * tri_inp_cap + n_inp * tri_out_cap; + delay = horowitz(w1.signal_rise_time(), res * cap, + deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + + // Wire wreset(); +} + +void Crossbar::print_crossbar() { + cout << "\nCrossbar Stats (" << n_inp << "x" << n_out << ")\n\n"; + cout << "Flit size : " << flit_size << " bits" << endl; + cout << "Width : " << area.w << " u" << endl; + cout << "Height : " << area.h << " u" << endl; + cout << "Dynamic Power : " + << power.readOp.dynamic * 1e9 * MIN(n_inp, n_out) << " (nJ)" << endl; + cout << "Leakage Power : " << power.readOp.leakage * 1e3 << " (mW)" + << endl; + cout << "Gate Leakage Power : " << power.readOp.gate_leakage * 1e3 + << " (mW)" << endl; + cout << "Crossbar Delay : " << delay * 1e12 << " ps\n"; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/crossbar.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/crossbar.h new file mode 100644 index 0000000000..db4b342377 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/crossbar.h @@ -0,0 +1,80 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __CROSSBAR__ +#define __CROSSBAR__ + +#include +#include +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "mat.h" +#include "parameter.h" +#include "wire.h" + +namespace cacti { + +class Crossbar : public Component { + public: + Crossbar(double in, double out, double flit_sz, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + ~Crossbar(); + + void print_crossbar(); + double output_buffer(); + void compute_power(); + + double n_inp, n_out; + double flit_size; + double tri_inp_cap, tri_out_cap, tri_ctr_cap, tri_int_cap; + + private: + double CB_ADJ; + /* + * Adjust factor of the height of the cross-point (tri-state buffer) cell + * (layout) in crossbar buffer is adjusted to get an aspect ratio of whole + * cross bar close to one; when adjust the ratio, the number of wires route + * over the tri-state buffers does not change, however, the effective wiring + * pitch changes. Specifically, since CB_ADJ will increase during the adjust, + * the tri-state buffer will become taller and thiner, and the effective + * wiring pitch will increase. As a result, the height of the crossbar + * (area.h) will increase. + */ + + TechnologyParameter::DeviceType *deviceType; + double TriS1, TriS2; + double min_w_pmos, Vdd; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/decoder.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/decoder.cc new file mode 100644 index 0000000000..7cd202a8d2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/decoder.cc @@ -0,0 +1,1646 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "decoder.h" +#include +#include +#include +#include "area.h" +#include "parameter.h" + +using namespace std; +using namespace cacti; + +Decoder::Decoder(int _num_dec_signals, bool flag_way_select, + double _C_ld_dec_out, double _R_wire_dec_out, + bool fully_assoc_, bool is_dram_, bool is_wl_tr_, + const Area &cell_, bool power_gating_, int nodes_DSTN_) + : exist(false), + C_ld_dec_out(_C_ld_dec_out), + R_wire_dec_out(_R_wire_dec_out), + num_gates(0), + num_gates_min(2), + delay(0), + // power(), + fully_assoc(fully_assoc_), + is_dram(is_dram_), + is_wl_tr(is_wl_tr_), + total_driver_nwidth(0), + total_driver_pwidth(0), + sleeptx(NULL), + cell(cell_), + nodes_DSTN(nodes_DSTN_), + power_gating(power_gating_) { + for (int i = 0; i < MAX_NUMBER_GATES_STAGE; i++) { + w_dec_n[i] = 0; + w_dec_p[i] = 0; + } + + /* + * _num_dec_signals is the number of decoded signal as output + * num_addr_bits_dec is the number of signal to be decoded + * as the decoders input. + */ + int num_addr_bits_dec = _log2(_num_dec_signals); + + if (num_addr_bits_dec < 4) { + if (flag_way_select) { + exist = true; + num_in_signals = 2; + } + else { + num_in_signals = 0; + } + } + else { + exist = true; + + if (flag_way_select) { + num_in_signals = 3; + } + else { + num_in_signals = 2; + } + } + + assert(cell.h > 0); + assert(cell.w > 0); + // the height of a row-decoder-driver cell is fixed to be 4 * cell.h; + // area.h = 4 * cell.h; + area.h = g_tp.h_dec * cell.h; + + compute_widths(); + compute_area(); +} + +void Decoder::compute_widths() { + double F; + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram, is_wl_tr); + double gnand2 = (2 + p_to_n_sz_ratio) / (1 + p_to_n_sz_ratio); + double gnand3 = (3 + p_to_n_sz_ratio) / (1 + p_to_n_sz_ratio); + + if (exist) { + if (num_in_signals == 2 || fully_assoc) { + w_dec_n[0] = 2 * g_tp.min_w_nmos_; + w_dec_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_; + F = gnand2; + } + else { + w_dec_n[0] = 3 * g_tp.min_w_nmos_; + w_dec_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_; + F = gnand3; + } + + F *= C_ld_dec_out / (gate_C(w_dec_n[0], 0, is_dram, false, is_wl_tr) + + gate_C(w_dec_p[0], 0, is_dram, false, is_wl_tr)); + num_gates = + logical_effort(num_gates_min, num_in_signals == 2 ? gnand2 : gnand3, F, + w_dec_n, w_dec_p, C_ld_dec_out, p_to_n_sz_ratio, is_dram, + is_wl_tr, g_tp.max_w_nmos_dec); + } +} + +void Decoder::compute_area() { + double cumulative_area = 0; + double cumulative_curr = 0; // cumulative leakage current + double cumulative_curr_Ig = 0; // cumulative leakage current + + if (exist) { // First check if this decoder exists + if (num_in_signals == 2) { + cumulative_area = + compute_gate_area(NAND, 2, w_dec_p[0], w_dec_n[0], area.h); + cumulative_curr = + cmos_Isub_leakage(w_dec_n[0], w_dec_p[0], 2, nand, is_dram); + cumulative_curr_Ig = + cmos_Ig_leakage(w_dec_n[0], w_dec_p[0], 2, nand, is_dram); + } + else if (num_in_signals == 3) { + cumulative_area = + compute_gate_area(NAND, 3, w_dec_p[0], w_dec_n[0], area.h); + cumulative_curr = + cmos_Isub_leakage(w_dec_n[0], w_dec_p[0], 3, nand, is_dram); + ; + cumulative_curr_Ig = + cmos_Ig_leakage(w_dec_n[0], w_dec_p[0], 3, nand, is_dram); + } + + for (int i = 1; i < num_gates; i++) { + cumulative_area += + compute_gate_area(INV, 1, w_dec_p[i], w_dec_n[i], area.h); + cumulative_curr += + cmos_Isub_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram); + cumulative_curr_Ig = + cmos_Ig_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram); + } + power.readOp.leakage = cumulative_curr * g_tp.peri_global.Vdd; + power.readOp.power_gated_leakage = + cumulative_curr * g_tp.peri_global.Vcc_min; + power.readOp.gate_leakage = cumulative_curr_Ig * g_tp.peri_global.Vdd; + + area.w = (cumulative_area / area.h); + if (power_gating) { + compute_power_gating(); + cumulative_area += sleeptx->area.get_area(); + area.w = (cumulative_area / area.h); + } + } +} + +void Decoder::compute_power_gating() { + // For all driver chains there is only one sleep transistors to save area + // Total transistor width for sleep tx calculation + for (int i = 0; i < num_gates; i++) { + total_driver_nwidth += w_dec_n[i]; + total_driver_pwidth += w_dec_p[i]; + } + + // compute sleep tx + bool is_footer = false; + double Isat_subarray = simplified_nmos_Isat(total_driver_nwidth); + double detalV; + double c_wakeup; + + c_wakeup = drain_C_(total_driver_pwidth, PCH, 1, 1, cell.h); // Psleep tx + detalV = g_tp.peri_global.Vdd - g_tp.peri_global.Vcc_min; + // if (g_ip->power_gating) + sleeptx = new Sleep_tx(g_ip->perfloss, Isat_subarray, is_footer, c_wakeup, + detalV, nodes_DSTN, area); +} + +double Decoder::compute_delays(double inrisetime) { + if (exist) { + double ret_val = 0; // outrisetime + int i; + double rd, tf, this_delay, c_load, c_intrinsic, Vpp; + double Vdd = g_tp.peri_global.Vdd; + + if ((is_wl_tr) && (is_dram)) { + Vpp = g_tp.vpp; + } + else if (is_wl_tr) { + Vpp = g_tp.sram_cell.Vdd; + } + else { + Vpp = g_tp.peri_global.Vdd; + } + + // first check whether a decoder is required at all + rd = tr_R_on(w_dec_n[0], NCH, num_in_signals, is_dram, false, is_wl_tr); + c_load = gate_C(w_dec_n[1] + w_dec_p[1], 0.0, is_dram, false, is_wl_tr); + c_intrinsic = + drain_C_(w_dec_p[0], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) * + num_in_signals + + drain_C_(w_dec_n[0], NCH, num_in_signals, 1, area.h, is_dram, false, + is_wl_tr); + tf = rd * (c_intrinsic + c_load); + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay += this_delay; + inrisetime = this_delay / (1.0 - 0.5); + power.readOp.dynamic += (c_load + c_intrinsic) * Vdd * Vdd; + // cout<<"w_dec_n["<<0<<"] = "<blk), blk2(drv2_->blk), drv1(drv1_), drv2(drv2_) { + driver_power.readOp.leakage = drv1->power_nand2_path.readOp.leakage + + drv1->power_nand3_path.readOp.leakage + + drv2->power_nand2_path.readOp.leakage + + drv2->power_nand3_path.readOp.leakage; + block_power.readOp.leakage = + blk1->power_nand2_path.readOp.leakage + + blk1->power_nand3_path.readOp.leakage + blk1->power_L2.readOp.leakage + + blk2->power_nand2_path.readOp.leakage + + blk2->power_nand3_path.readOp.leakage + blk2->power_L2.readOp.leakage; + + driver_power.readOp.power_gated_leakage = + drv1->power_nand2_path.readOp.power_gated_leakage + + drv1->power_nand3_path.readOp.power_gated_leakage + + drv2->power_nand2_path.readOp.power_gated_leakage + + drv2->power_nand3_path.readOp.power_gated_leakage; + block_power.readOp.power_gated_leakage = + blk1->power_nand2_path.readOp.power_gated_leakage + + blk1->power_nand3_path.readOp.power_gated_leakage + + blk1->power_L2.readOp.power_gated_leakage + + blk2->power_nand2_path.readOp.power_gated_leakage + + blk2->power_nand3_path.readOp.power_gated_leakage + + blk2->power_L2.readOp.power_gated_leakage; + + power.readOp.leakage = + driver_power.readOp.leakage + block_power.readOp.leakage; + + power.readOp.power_gated_leakage = driver_power.readOp.power_gated_leakage + + block_power.readOp.power_gated_leakage; + + driver_power.readOp.gate_leakage = + drv1->power_nand2_path.readOp.gate_leakage + + drv1->power_nand3_path.readOp.gate_leakage + + drv2->power_nand2_path.readOp.gate_leakage + + drv2->power_nand3_path.readOp.gate_leakage; + block_power.readOp.gate_leakage = blk1->power_nand2_path.readOp.gate_leakage + + blk1->power_nand3_path.readOp.gate_leakage + + blk1->power_L2.readOp.gate_leakage + + blk2->power_nand2_path.readOp.gate_leakage + + blk2->power_nand3_path.readOp.gate_leakage + + blk2->power_L2.readOp.gate_leakage; + power.readOp.gate_leakage = + driver_power.readOp.gate_leakage + block_power.readOp.gate_leakage; +} + +void PredecBlkDrv::leakage_feedback(double temperature) { + double leak_nand2_path = 0; + double leak_nand3_path = 0; + double gate_leak_nand2_path = 0; + double gate_leak_nand3_path = 0; + + if (flag_driver_exists) { // first check whether a predecoder block driver is + // needed + for (int i = 0; i < number_gates_nand2_path; ++i) { + leak_nand2_path += cmos_Isub_leakage( + width_nand2_path_n[i], width_nand2_path_p[i], 1, inv, is_dram_); + gate_leak_nand2_path += cmos_Ig_leakage( + width_nand2_path_n[i], width_nand2_path_p[i], 1, inv, is_dram_); + } + leak_nand2_path *= + (num_buffers_driving_1_nand2_load + num_buffers_driving_2_nand2_load + + num_buffers_driving_4_nand2_load); + gate_leak_nand2_path *= + (num_buffers_driving_1_nand2_load + num_buffers_driving_2_nand2_load + + num_buffers_driving_4_nand2_load); + + for (int i = 0; i < number_gates_nand3_path; ++i) { + leak_nand3_path += cmos_Isub_leakage( + width_nand3_path_n[i], width_nand3_path_p[i], 1, inv, is_dram_); + gate_leak_nand3_path += cmos_Ig_leakage( + width_nand3_path_n[i], width_nand3_path_p[i], 1, inv, is_dram_); + } + leak_nand3_path *= + (num_buffers_driving_2_nand3_load + num_buffers_driving_8_nand3_load); + gate_leak_nand3_path *= + (num_buffers_driving_2_nand3_load + num_buffers_driving_8_nand3_load); + + power_nand2_path.readOp.leakage = leak_nand2_path * g_tp.peri_global.Vdd; + power_nand3_path.readOp.leakage = leak_nand3_path * g_tp.peri_global.Vdd; + power_nand2_path.readOp.gate_leakage = + gate_leak_nand2_path * g_tp.peri_global.Vdd; + power_nand3_path.readOp.gate_leakage = + gate_leak_nand3_path * g_tp.peri_global.Vdd; + } +} + +double Predec::compute_delays(double inrisetime) { + // TODO: Jung Ho thinks that predecoder block driver locates between decoder + // and predecoder block. + pair tmp_pair1, tmp_pair2; + tmp_pair1 = drv1->compute_delays(inrisetime, inrisetime); + tmp_pair1 = blk1->compute_delays(tmp_pair1); + tmp_pair2 = drv2->compute_delays(inrisetime, inrisetime); + tmp_pair2 = blk2->compute_delays(tmp_pair2); + tmp_pair1 = get_max_delay_before_decoder(tmp_pair1, tmp_pair2); + + driver_power.readOp.dynamic = + drv1->num_addr_bits_nand2_path() * drv1->power_nand2_path.readOp.dynamic + + drv1->num_addr_bits_nand3_path() * drv1->power_nand3_path.readOp.dynamic + + drv2->num_addr_bits_nand2_path() * drv2->power_nand2_path.readOp.dynamic + + drv2->num_addr_bits_nand3_path() * drv2->power_nand3_path.readOp.dynamic; + + block_power.readOp.dynamic = + blk1->power_nand2_path.readOp.dynamic * blk1->num_L1_active_nand2_path + + blk1->power_nand3_path.readOp.dynamic * blk1->num_L1_active_nand3_path + + blk1->power_L2.readOp.dynamic + + blk2->power_nand2_path.readOp.dynamic * blk1->num_L1_active_nand2_path + + blk2->power_nand3_path.readOp.dynamic * blk1->num_L1_active_nand3_path + + blk2->power_L2.readOp.dynamic; + + power.readOp.dynamic = + driver_power.readOp.dynamic + block_power.readOp.dynamic; + + delay = tmp_pair1.first; + return tmp_pair1.second; +} + +void Predec::leakage_feedback(double temperature) { + drv1->leakage_feedback(temperature); + drv2->leakage_feedback(temperature); + blk1->leakage_feedback(temperature); + blk2->leakage_feedback(temperature); + + driver_power.readOp.leakage = drv1->power_nand2_path.readOp.leakage + + drv1->power_nand3_path.readOp.leakage + + drv2->power_nand2_path.readOp.leakage + + drv2->power_nand3_path.readOp.leakage; + block_power.readOp.leakage = + blk1->power_nand2_path.readOp.leakage + + blk1->power_nand3_path.readOp.leakage + blk1->power_L2.readOp.leakage + + blk2->power_nand2_path.readOp.leakage + + blk2->power_nand3_path.readOp.leakage + blk2->power_L2.readOp.leakage; + power.readOp.leakage = + driver_power.readOp.leakage + block_power.readOp.leakage; + + driver_power.readOp.gate_leakage = + drv1->power_nand2_path.readOp.gate_leakage + + drv1->power_nand3_path.readOp.gate_leakage + + drv2->power_nand2_path.readOp.gate_leakage + + drv2->power_nand3_path.readOp.gate_leakage; + block_power.readOp.gate_leakage = blk1->power_nand2_path.readOp.gate_leakage + + blk1->power_nand3_path.readOp.gate_leakage + + blk1->power_L2.readOp.gate_leakage + + blk2->power_nand2_path.readOp.gate_leakage + + blk2->power_nand3_path.readOp.gate_leakage + + blk2->power_L2.readOp.gate_leakage; + power.readOp.gate_leakage = + driver_power.readOp.gate_leakage + block_power.readOp.gate_leakage; +} + +// returns +pair Predec::get_max_delay_before_decoder( + pair input_pair1, pair input_pair2) { + pair ret_val; + double delay; + + delay = drv1->delay_nand2_path + blk1->delay_nand2_path; + ret_val.first = delay; + ret_val.second = input_pair1.first; + delay = drv1->delay_nand3_path + blk1->delay_nand3_path; + if (ret_val.first < delay) { + ret_val.first = delay; + ret_val.second = input_pair1.second; + } + delay = drv2->delay_nand2_path + blk2->delay_nand2_path; + if (ret_val.first < delay) { + ret_val.first = delay; + ret_val.second = input_pair2.first; + } + delay = drv2->delay_nand3_path + blk2->delay_nand3_path; + if (ret_val.first < delay) { + ret_val.first = delay; + ret_val.second = input_pair2.second; + } + + return ret_val; +} + +Driver::Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, + bool is_dram, bool power_gating_, int nodes_DSTN_) + : number_gates(0), + min_number_gates(2), + c_gate_load(c_gate_load_), + c_wire_load(c_wire_load_), + r_wire_load(r_wire_load_), + delay(0), + // power(), + is_dram_(is_dram), + total_driver_nwidth(0), + total_driver_pwidth(0), + sleeptx(NULL), + nodes_DSTN(nodes_DSTN_), + power_gating(power_gating_) { + for (int i = 0; i < MAX_NUMBER_GATES_STAGE; i++) { + width_n[i] = 0; + width_p[i] = 0; + } + + compute_widths(); + compute_area(); +} + +void Driver::compute_widths() { + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram_); + double c_load = c_gate_load + c_wire_load; + width_n[0] = g_tp.min_w_nmos_; + width_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_; + + double F = c_load / gate_C(width_n[0] + width_p[0], 0, is_dram_); + number_gates = + logical_effort(min_number_gates, 1, F, width_n, width_p, c_load, + p_to_n_sz_ratio, is_dram_, false, g_tp.max_w_nmos_); +} + +void Driver::compute_area() { + double cumulative_area = 0; + + area.h = g_tp.cell_h_def; + for (int i = 0; i < number_gates; i++) { + cumulative_area += + compute_gate_area(INV, 1, width_p[i], width_n[i], area.h); + } + area.w = (cumulative_area / area.h); + if (power_gating) { + compute_power_gating(); + cumulative_area += sleeptx->area.get_area(); + area.w = (cumulative_area / area.h); + } +} + +void Driver::compute_power_gating() { + // For all driver chains there is only one sleep transistors to save area + // Total transistor width for sleep tx calculation + for (int i = 0; i < number_gates; i++) { + total_driver_nwidth += width_n[i]; + total_driver_pwidth += width_p[i]; + } + + // compute sleep tx + bool is_footer = false; + double Isat_subarray = simplified_nmos_Isat(total_driver_nwidth); + double detalV; + double c_wakeup; + + c_wakeup = drain_C_(total_driver_pwidth, PCH, 1, 1, area.h); // Psleep tx + detalV = g_tp.peri_global.Vdd - g_tp.peri_global.Vcc_min; + // if (g_ip->power_gating) + sleeptx = + new Sleep_tx(g_ip->perfloss, Isat_subarray, is_footer, c_wakeup, detalV, + nodes_DSTN, // default is 1 for drivers + area); +} + +double Driver::compute_delay(double inrisetime) { + int i; + double rd, c_load, c_intrinsic, tf; + double this_delay = 0; + + for (i = 0; i < number_gates - 1; ++i) { + rd = tr_R_on(width_n[i], NCH, 1, is_dram_); + c_load = gate_C(width_n[i + 1] + width_p[i + 1], 0.0, is_dram_); + c_intrinsic = drain_C_(width_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) + + drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_); + tf = rd * (c_intrinsic + c_load); + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay += this_delay; + inrisetime = this_delay / (1.0 - 0.5); + power.readOp.dynamic += + (c_intrinsic + c_load) * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + power.readOp.leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + power.readOp.power_gated_leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vcc_min; + power.readOp.gate_leakage += + cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + } + + i = number_gates - 1; + c_load = c_gate_load + c_wire_load; + rd = tr_R_on(width_n[i], NCH, 1, is_dram_); + c_intrinsic = drain_C_(width_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) + + drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_); + tf = rd * (c_intrinsic + c_load) + + r_wire_load * (c_wire_load / 2 + c_gate_load); + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay += this_delay; + power.readOp.dynamic += + (c_intrinsic + c_load) * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + power.readOp.leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + power.readOp.power_gated_leakage += + cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vcc_min; + power.readOp.gate_leakage += + cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) * + g_tp.peri_global.Vdd; + + return this_delay / (1.0 - 0.5); +} + +// TODO: add sleep tx in predec/predecblk/predecdriver diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/decoder.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/decoder.h new file mode 100644 index 0000000000..ff3265dc45 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/decoder.h @@ -0,0 +1,244 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __DECODER_H__ +#define __DECODER_H__ + +#include +#include "area.h" +#include "component.h" +#include "parameter.h" +#include "powergating.h" + +using namespace std; + +namespace cacti { + +class Decoder : public Component { + public: + Decoder(int _num_dec_signals, bool flag_way_select, double _C_ld_dec_out, + double _R_wire_dec_out, bool fully_assoc_, bool is_dram_, + bool is_wl_tr_, const Area &cell_, bool power_gating_ = false, + int nodes_DSTN_ = 1); + + bool exist; + int num_in_signals; + double C_ld_dec_out; + double R_wire_dec_out; + int num_gates; + int num_gates_min; + double w_dec_n[MAX_NUMBER_GATES_STAGE]; + double w_dec_p[MAX_NUMBER_GATES_STAGE]; + double delay; + // powerDef power; + bool fully_assoc; + bool is_dram; + bool is_wl_tr; + + double total_driver_nwidth; + double total_driver_pwidth; + Sleep_tx *sleeptx; + + const Area &cell; + int nodes_DSTN; + bool power_gating; + + void compute_widths(); + void compute_area(); + double compute_delays(double inrisetime); // return outrisetime + void compute_power_gating(); + + void leakage_feedback(double temperature); + + ~Decoder() { + if (sleeptx != 0) + delete sleeptx; + }; +}; + +class PredecBlk : public Component { + public: + PredecBlk(int num_dec_signals, Decoder *dec, double C_wire_predec_blk_out, + double R_wire_predec_blk_out, int num_dec_per_predec, bool is_dram_, + bool is_blk1); + + Decoder *dec; + bool exist; + int number_input_addr_bits; + double C_ld_predec_blk_out; + double R_wire_predec_blk_out; + int branch_effort_nand2_gate_output; + int branch_effort_nand3_gate_output; + bool flag_two_unique_paths; + int flag_L2_gate; + int number_inputs_L1_gate; + int number_gates_L1_nand2_path; + int number_gates_L1_nand3_path; + int number_gates_L2; + int min_number_gates_L1; + int min_number_gates_L2; + int num_L1_active_nand2_path; + int num_L1_active_nand3_path; + double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE]; + double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE]; + double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE]; + double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE]; + double w_L2_n[MAX_NUMBER_GATES_STAGE]; + double w_L2_p[MAX_NUMBER_GATES_STAGE]; + double delay_nand2_path; + double delay_nand3_path; + powerDef power_nand2_path; + powerDef power_nand3_path; + powerDef power_L2; + + bool is_dram_; + + void compute_widths(); + void compute_area(); + + void leakage_feedback(double temperature); + + pair compute_delays( + pair inrisetime); // + // return +}; + +class PredecBlkDrv : public Component { + public: + PredecBlkDrv(int way_select, PredecBlk *blk_, bool is_dram); + + int flag_driver_exists; + int number_input_addr_bits; + int number_gates_nand2_path; + int number_gates_nand3_path; + int min_number_gates; + int num_buffers_driving_1_nand2_load; + int num_buffers_driving_2_nand2_load; + int num_buffers_driving_4_nand2_load; + int num_buffers_driving_2_nand3_load; + int num_buffers_driving_8_nand3_load; + int num_buffers_nand3_path; + double c_load_nand2_path_out; + double c_load_nand3_path_out; + double r_load_nand2_path_out; + double r_load_nand3_path_out; + double width_nand2_path_n[MAX_NUMBER_GATES_STAGE]; + double width_nand2_path_p[MAX_NUMBER_GATES_STAGE]; + double width_nand3_path_n[MAX_NUMBER_GATES_STAGE]; + double width_nand3_path_p[MAX_NUMBER_GATES_STAGE]; + double delay_nand2_path; + double delay_nand3_path; + powerDef power_nand2_path; + powerDef power_nand3_path; + + PredecBlk *blk; + Decoder *dec; + bool is_dram_; + int way_select; + + void compute_widths(); + void compute_area(); + + void leakage_feedback(double temperature); + + pair compute_delays( + double inrisetime_nand2_path, + double inrisetime_nand3_path); // return + + inline int num_addr_bits_nand2_path() { + return num_buffers_driving_1_nand2_load + num_buffers_driving_2_nand2_load + + num_buffers_driving_4_nand2_load; + } + inline int num_addr_bits_nand3_path() { + return num_buffers_driving_2_nand3_load + num_buffers_driving_8_nand3_load; + } + double get_rdOp_dynamic_E(int num_act_mats_hor_dir); +}; + +class Predec : public Component { + public: + Predec(PredecBlkDrv *drv1, PredecBlkDrv *drv2); + + double compute_delays(double inrisetime); // return outrisetime + + void leakage_feedback(double temperature); + PredecBlk *blk1; + PredecBlk *blk2; + PredecBlkDrv *drv1; + PredecBlkDrv *drv2; + + powerDef block_power; + powerDef driver_power; + + private: + // returns + pair get_max_delay_before_decoder( + pair input_pair1, pair input_pair2); +}; + +class Driver : public Component { + public: + Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, + bool is_dram, bool power_gating_ = false, int nodes_DSTN_ = 1); + + int number_gates; + int min_number_gates; + double width_n[MAX_NUMBER_GATES_STAGE]; + double width_p[MAX_NUMBER_GATES_STAGE]; + double c_gate_load; + double c_wire_load; + double r_wire_load; + double delay; + // powerDef power; + bool is_dram_; + + double total_driver_nwidth; + double total_driver_pwidth; + Sleep_tx *sleeptx; + + int nodes_DSTN; + bool power_gating; + + void compute_widths(); + void compute_area(); + double compute_delay(double inrisetime); + + void compute_power_gating(); + + ~Driver() { + if (sleeptx != 0) + delete sleeptx; + }; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/htree2.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/htree2.cc new file mode 100644 index 0000000000..ab45c501d2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/htree2.cc @@ -0,0 +1,758 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "htree2.h" +#include +#include +#include "wire.h" +using namespace cacti; + +Htree2::Htree2(enum Wire_type wire_model, double mat_w, double mat_h, + int a_bits, int d_inbits, int search_data_in, int d_outbits, + int search_data_out, int bl, int wl, enum Htree_type htree_type, + bool uca_tree_, bool search_tree_, + TechnologyParameter::DeviceType *dt) + : in_rise_time(0), + out_rise_time(0), + tree_type(htree_type), + mat_width(mat_w), + mat_height(mat_h), + add_bits(a_bits), + data_in_bits(d_inbits), + search_data_in_bits(search_data_in), + data_out_bits(d_outbits), + search_data_out_bits(search_data_out), + ndbl(bl), + ndwl(wl), + uca_tree(uca_tree_), + search_tree(search_tree_), + wt(wire_model), + deviceType(dt) { + assert(ndbl >= 2 && ndwl >= 2); + + // if (ndbl == 1 && ndwl == 1) + // { + // delay = 0; + // power.readOp.dynamic = 0; + // power.readOp.leakage = 0; + // area.w = mat_w; + // area.h = mat_h; + // return; + // } + // if (ndwl == 1) ndwl++; + // if (ndbl == 1) ndbl++; + + max_unpipelined_link_delay = 0; // TODO + min_w_nmos = g_tp.min_w_nmos_; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos; + + switch (htree_type) { + case Add_htree: + wire_bw = init_wire_bw = add_bits; + in_htree(); + break; + case Data_in_htree: + wire_bw = init_wire_bw = data_in_bits; + in_htree(); + break; + case Data_out_htree: + wire_bw = init_wire_bw = data_out_bits; + out_htree(); + break; + case Search_in_htree: + wire_bw = init_wire_bw = search_data_in_bits; // in_search_tree is broad + // cast, out_htree is not. + in_htree(); + break; + case Search_out_htree: + wire_bw = init_wire_bw = search_data_out_bits; + out_htree(); + break; + default: + assert(0); + break; + } + + power_bit = power; + power.readOp.dynamic *= init_wire_bw; + + assert(power.readOp.dynamic >= 0); + assert(power.readOp.leakage >= 0); +} + +// nand gate sizing calculation +void Htree2::input_nand(double s1, double s2, double l_eff) { + Wire w1(wt, l_eff); + double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; + // input capacitance of a repeater = input capacitance of nand. + double nsize = s1 * (1 + pton_size) / (2 + pton_size); + nsize = (nsize < 1) ? 1 : nsize; + + double tc = 2 * tr_R_on(nsize * min_w_nmos, NCH, 1) * + (drain_C_(nsize * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) * 2 + + 2 * gate_C(s2 * (min_w_nmos + min_w_pmos), 0)); + delay += horowitz(w1.out_rise_time, tc, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + power.readOp.dynamic += + 0.5 * + (2 * drain_C_(pton_size * nsize * min_w_pmos, PCH, 1, 1, + g_tp.cell_h_def) + + drain_C_(nsize * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + 2 * gate_C(s2 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (2 * drain_C_(pton_size * nsize * min_w_pmos, PCH, 1, 1, + g_tp.cell_h_def) + + drain_C_(nsize * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + 2 * gate_C(s2 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * wire_bw; + power.readOp.leakage += + (wire_bw * cmos_Isub_leakage(min_w_nmos * (nsize * 2), + min_w_pmos * nsize * 2, 2, nand)) * + deviceType->Vdd; + power.readOp.power_gated_leakage += + (wire_bw * cmos_Isub_leakage(min_w_nmos * (nsize * 2), + min_w_pmos * nsize * 2, 2, nand)) * + deviceType->Vcc_min; + power.readOp.gate_leakage += + (wire_bw * cmos_Ig_leakage(min_w_nmos * (nsize * 2), + min_w_pmos * nsize * 2, 2, nand)) * + deviceType->Vdd; +} + +// tristate buffer model consisting of not, nand, nor, and driver transistors +void Htree2::output_buffer(double s1, double s2, double l_eff) { + Wire w1(wt, l_eff); + double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; + // input capacitance of repeater = input capacitance of nand + nor. + double size = s1 * (1 + pton_size) / (2 + pton_size + 1 + 2 * pton_size); + double s_eff = // stage eff of a repeater in a wire + (gate_C(s2 * (min_w_nmos + min_w_pmos), 0) + + w1.wire_cap(l_eff * 1e-6, true)) / + gate_C(s2 * (min_w_nmos + min_w_pmos), 0); + double tr_size = gate_C(s1 * (min_w_nmos + min_w_pmos), 0) * 1 / 2 / + (s_eff * gate_C(min_w_pmos, 0)); + size = (size < 1) ? 1 : size; + + double res_nor = 2 * tr_R_on(size * min_w_pmos, PCH, 1); + double res_ptrans = tr_R_on(tr_size * min_w_nmos, NCH, 1); + double cap_nand_out = + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 + + gate_C(tr_size * min_w_pmos, 0); + double cap_ptrans_out = + 2 * (drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(tr_size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) + + gate_C(s1 * (min_w_nmos + min_w_pmos), 0); + + double tc = res_nor * cap_nand_out + (res_nor + res_ptrans) * cap_ptrans_out; + + delay += horowitz(w1.out_rise_time, tc, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + + // nand + power.readOp.dynamic += + 0.5 * + (2 * drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (2 * drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + // not + power.readOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + // nor + power.readOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + 2 * drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + (drain_C_(size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + 2 * drain_C_(size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(tr_size * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + // output transistor + power.readOp.dynamic += + 0.5 * + ((drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(tr_size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) * + 2 + + gate_C(s1 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd; + + power.searchOp.dynamic += + 0.5 * + ((drain_C_(tr_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(tr_size * min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) * + 2 + + gate_C(s1 * (min_w_nmos + min_w_pmos), 0)) * + deviceType->Vdd * deviceType->Vdd * init_wire_bw; + + if (uca_tree) { + power.readOp.leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vcc_min * wire_bw; /*inverter + output tr*/ + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nand) * + deviceType->Vcc_min * wire_bw; // nand + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nor) * + deviceType->Vcc_min * wire_bw; // nor + + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + // power.readOp.gate_leakage *=; + } + else { + power.readOp.leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.leakage += cmos_Isub_leakage(min_w_nmos * size * 3, + min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vcc_min * wire_bw; /*inverter + output tr*/ + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nand) * + deviceType->Vcc_min * wire_bw; // nand + power.readOp.power_gated_leakage += + cmos_Isub_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, + nor) * + deviceType->Vcc_min * wire_bw; // nor + + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * tr_size * 2, min_w_pmos * tr_size * 2, 1, + inv) * + deviceType->Vdd * wire_bw; /*inverter + output tr*/ + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nand) * + deviceType->Vdd * wire_bw; // nand + power.readOp.gate_leakage += + cmos_Ig_leakage(min_w_nmos * size * 3, min_w_pmos * size * 3, 2, nor) * + deviceType->Vdd * wire_bw; // nor + // power.readOp.gate_leakage *=deviceType->Vdd*wire_bw; + } +} + +/* calculates the input h-tree delay/power + * A nand gate is used at each node to + * limit the signal + * The area of an unbalanced htree (rows != columns) + * depends on how data is traversed. + * In the following function, if ( no. of rows < no. of columns), + * then data first traverse in excess hor. links until vertical + * and horizontal nodes are same. + * If no. of rows is bigger, then data traverse in + * a hor. link followed by a ver. link in a repeated + * fashion (similar to a balanced tree) until there are no + * hor. links left. After this it goes through the remaining vertical + * links. + */ +void Htree2::in_htree() { + // temp var + double s1 = 0, s2 = 0, s3 = 0; + double l_eff = 0; + Wire *wtemp1 = 0, *wtemp2 = 0, *wtemp3 = 0; + double len = 0, ht = 0; + int option = 0; + + int h = (int)_log2(ndwl / 2); // horizontal nodes + int v = (int)_log2(ndbl / 2); // vertical nodes + double len_temp; + double ht_temp; + if (uca_tree) { // Sheng: this computation do not consider the wires that + // route from edge to middle. + ht_temp = (mat_height * ndbl / 2 + /* since uca_tree models interbank tree, + mat_height => bank height */ + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, h)))) / + 2; + len_temp = (mat_width * ndwl / 2 + + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, v)))) / + 2; + } + else { + if (ndwl == ndbl) { + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndbl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else if (ndwl > ndbl) { + double excess_part = (_log2(ndwl / 2) - _log2(ndbl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + +(search_data_in_bits + search_data_out_bits)) * + ((ndbl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (2 * (1 - pow(0.5, h - v)) + pow(0.5, v - h) * v)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else { + double excess_part = (_log2(ndbl / 2) - _log2(ndwl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (h + 2 * (1 - pow(0.5, v - h)))) / + 2; + } + } + + area.h = ht_temp * 2; + area.w = len_temp * 2; + delay = 0; + power.readOp.dynamic = 0; + power.readOp.leakage = 0; + power.readOp.power_gated_leakage = 0; + power.searchOp.dynamic = 0; + len = len_temp; + ht = ht_temp / 2; + + while (v > 0 || h > 0) { + if (wtemp1) + delete wtemp1; + if (wtemp2) + delete wtemp2; + if (wtemp3) + delete wtemp3; + + if (h > v) { + // the iteration considers only one horizontal link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, len / 2); // ver + len_temp = len; + len /= 2; + wtemp3 = 0; + h--; + option = 0; + } + else if (v > 0 && h > 0) { + // considers one horizontal link and one vertical link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, ht); // ver + wtemp3 = new Wire(wt, len / 2); // next hor + len_temp = len; + ht_temp = ht; + len /= 2; + ht /= 2; + v--; + h--; + option = 1; + } + else { + // considers only one vertical link + assert(h == 0); + wtemp1 = new Wire(wt, ht); // ver + wtemp2 = new Wire(wt, ht / 2); // hor + ht_temp = ht; + ht /= 2; + wtemp3 = 0; + v--; + option = 2; + } + + delay += wtemp1->delay; + power.readOp.dynamic += wtemp1->power.readOp.dynamic; + power.searchOp.dynamic += wtemp1->power.readOp.dynamic * wire_bw; + power.readOp.leakage += wtemp1->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp1->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp1->power.readOp.gate_leakage * wire_bw; + if ((uca_tree == false && option == 2) || search_tree == true) { + wire_bw *= 2; // wire bandwidth doubles only for vertical branches + } + + if (uca_tree == false) { + if (len_temp > wtemp1->repeater_spacing) { + s1 = wtemp1->repeater_size; + l_eff = wtemp1->repeater_spacing; + } + else { + s1 = (len_temp / wtemp1->repeater_spacing) * wtemp1->repeater_size; + l_eff = len_temp; + } + + if (ht_temp > wtemp2->repeater_spacing) { + s2 = wtemp2->repeater_size; + } + else { + s2 = (len_temp / wtemp2->repeater_spacing) * wtemp2->repeater_size; + } + // first level + input_nand(s1, s2, l_eff); + } + + if (option != 1) { + continue; + } + + // second level + delay += wtemp2->delay; + power.readOp.dynamic += wtemp2->power.readOp.dynamic; + power.searchOp.dynamic += wtemp2->power.readOp.dynamic * wire_bw; + power.readOp.leakage += wtemp2->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp2->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + + if (uca_tree) { + power.readOp.leakage += (wtemp2->power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + } + else { + power.readOp.leakage += (wtemp2->power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + wire_bw *= 2; + + if (ht_temp > wtemp3->repeater_spacing) { + s3 = wtemp3->repeater_size; + l_eff = wtemp3->repeater_spacing; + } + else { + s3 = (len_temp / wtemp3->repeater_spacing) * wtemp3->repeater_size; + l_eff = ht_temp; + } + + input_nand(s2, s3, l_eff); + } + } + + if (wtemp1) + delete wtemp1; + if (wtemp2) + delete wtemp2; + if (wtemp3) + delete wtemp3; +} + +/* a tristate buffer is used to handle fan-ins + * The area of an unbalanced htree (rows != columns) + * depends on how data is traversed. + * In the following function, if ( no. of rows < no. of columns), + * then data first traverse in excess hor. links until vertical + * and horizontal nodes are same. + * If no. of rows is bigger, then data traverse in + * a hor. link followed by a ver. link in a repeated + * fashion (similar to a balanced tree) until there are no + * hor. links left. After this it goes through the remaining vertical + * links. + */ +void Htree2::out_htree() { + // temp var + double s1 = 0, s2 = 0, s3 = 0; + double l_eff = 0; + Wire *wtemp1 = 0, *wtemp2 = 0, *wtemp3 = 0; + double len = 0, ht = 0; + int option = 0; + + int h = (int)_log2(ndwl / 2); + int v = (int)_log2(ndbl / 2); + double len_temp; + double ht_temp; + if (uca_tree) { + ht_temp = (mat_height * ndbl / 2 + /* since uca_tree models interbank tree, + mat_height => bank height */ + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, h)))) / + 2; + len_temp = (mat_width * ndwl / 2 + + ((add_bits + data_in_bits + data_out_bits + + (search_data_in_bits + search_data_out_bits)) * + g_tp.wire_outside_mat.pitch * 2 * (1 - pow(0.5, v)))) / + 2; + } + else { + if (ndwl == ndbl) { + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndbl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else if (ndwl > ndbl) { + double excess_part = (_log2(ndwl / 2) - _log2(ndbl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndbl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (2 * (1 - pow(0.5, h - v)) + pow(0.5, v - h) * v)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v)) / + 2; + } + else { + double excess_part = (_log2(ndbl / 2) - _log2(ndwl / 2)); + ht_temp = + ((mat_height * ndbl / 2) + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + ((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)) / + 2; + len_temp = + (mat_width * ndwl / 2 + + ((add_bits + (search_data_in_bits + search_data_out_bits)) * + ((ndwl / 2 - 1) + excess_part) * g_tp.wire_outside_mat.pitch) + + (data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * + (h + 2 * (1 - pow(0.5, v - h)))) / + 2; + } + } + area.h = ht_temp * 2; + area.w = len_temp * 2; + delay = 0; + power.readOp.dynamic = 0; + power.readOp.leakage = 0; + power.readOp.power_gated_leakage = 0; + power.readOp.gate_leakage = 0; + // cout<<"power.readOp.gate_leakage"< 0 || h > 0) { // finds delay/power of each link in the tree + if (wtemp1) + delete wtemp1; + if (wtemp2) + delete wtemp2; + if (wtemp3) + delete wtemp3; + + if (h > v) { + // the iteration considers only one horizontal link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, len / 2); // ver + len_temp = len; + len /= 2; + wtemp3 = 0; + h--; + option = 0; + } + else if (v > 0 && h > 0) { + // considers one horizontal link and one vertical link + wtemp1 = new Wire(wt, len); // hor + wtemp2 = new Wire(wt, ht); // ver + wtemp3 = new Wire(wt, len / 2); // next hor + len_temp = len; + ht_temp = ht; + len /= 2; + ht /= 2; + v--; + h--; + option = 1; + } + else { + // considers only one vertical link + assert(h == 0); + wtemp1 = new Wire(wt, ht); // hor + wtemp2 = new Wire(wt, ht / 2); // ver + ht_temp = ht; + ht /= 2; + wtemp3 = 0; + v--; + option = 2; + } + delay += wtemp1->delay; + power.readOp.dynamic += wtemp1->power.readOp.dynamic; + power.searchOp.dynamic += wtemp1->power.readOp.dynamic * init_wire_bw; + power.readOp.leakage += wtemp1->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp1->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp1->power.readOp.gate_leakage * wire_bw; + // cout<<"power.readOp.gate_leakage"< wtemp1->repeater_spacing) { + s1 = wtemp1->repeater_size; + l_eff = wtemp1->repeater_spacing; + } + else { + s1 = (len_temp / wtemp1->repeater_spacing) * wtemp1->repeater_size; + l_eff = len_temp; + } + if (ht_temp > wtemp2->repeater_spacing) { + s2 = wtemp2->repeater_size; + } + else { + s2 = (len_temp / wtemp2->repeater_spacing) * wtemp2->repeater_size; + } + // first level + output_buffer(s1, s2, l_eff); + } + + if (option != 1) { + continue; + } + + // second level + delay += wtemp2->delay; + power.readOp.dynamic += wtemp2->power.readOp.dynamic; + power.searchOp.dynamic += wtemp2->power.readOp.dynamic * init_wire_bw; + power.readOp.leakage += wtemp2->power.readOp.leakage * wire_bw; + power.readOp.power_gated_leakage += + wtemp2->power.readOp.power_gated_leakage * wire_bw; + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + // cout<<"power.readOp.gate_leakage"<power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + } + else { + power.readOp.leakage += (wtemp2->power.readOp.leakage * wire_bw); + power.readOp.power_gated_leakage += + (wtemp2->power.readOp.power_gated_leakage * wire_bw); + power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage * wire_bw; + wire_bw *= 2; + + if (ht_temp > wtemp3->repeater_spacing) { + s3 = wtemp3->repeater_size; + l_eff = wtemp3->repeater_spacing; + } + else { + s3 = (len_temp / wtemp3->repeater_spacing) * wtemp3->repeater_size; + l_eff = ht_temp; + } + + output_buffer(s2, s3, l_eff); + } + // cout<<"power.readOp.leakage"<power.readOp.gate_leakage"<power.readOp.gate_leakage< +#include +#include +#include + +#include "Ucache.h" +#include "arbiter.h" +#include "area.h" +#include "basic_circuit.h" +#include "crossbar.h" +#include "io.h" +#include "nuca.h" +#include "parameter.h" +#include "version_cacti.h" +//#include "highradix.h" + +using namespace std; + +namespace cacti { + +InputParameter::InputParameter() + : array_power_gated(false), + bitline_floating(false), + wl_power_gated(false), + cl_power_gated(false), + interconect_power_gated(false), + power_gating(false), + perfloss(0.01), + cl_vertical(true), + long_channel_device(false) { + dvs_voltage = std::vector(0); +} + +/* Parses "cache.cfg" file */ +void InputParameter::parse_cfg(const string &in_file) { + FILE *fp = fopen(in_file.c_str(), "r"); + char line[5000]; + char jk[5000]; + char temp_var[5000]; + double temp_double; + char *data = line; + int offset = 0; + + if (!fp) { + cout << in_file << " is missing!\n"; + exit(-1); + } + + while (fscanf(fp, "%[^\n]\n", line) != EOF) { + if (!strncmp("-size", line, strlen("-size"))) { + sscanf(line, "-size %[(:-~)*]%u", jk, &(cache_sz)); + continue; + } + + if (!strncmp("-page size", line, strlen("-page size"))) { + sscanf(line, "-page size %[(:-~)*]%u", jk, &(page_sz_bits)); + continue; + } + + if (!strncmp("-burst length", line, strlen("-burst length"))) { + sscanf(line, "-burst %[(:-~)*]%u", jk, &(burst_len)); + continue; + } + + if (!strncmp("-internal prefetch width", line, + strlen("-internal prefetch width"))) { + sscanf(line, "-internal prefetch %[(:-~)*]%u", jk, &(int_prefetch_w)); + continue; + } + + if (!strncmp("-block", line, strlen("-block"))) { + sscanf(line, "-block size (bytes) %d", &(line_sz)); + continue; + } + + if (!strncmp("-associativity", line, strlen("-associativity"))) { + sscanf(line, "-associativity %d", &(assoc)); + continue; + } + + if (!strncmp("-read-write", line, strlen("-read-write"))) { + sscanf(line, "-read-write port %d", &(num_rw_ports)); + continue; + } + + if (!strncmp("-exclusive read", line, strlen("exclusive read"))) { + sscanf(line, "-exclusive read port %d", &(num_rd_ports)); + continue; + } + + if (!strncmp("-exclusive write", line, strlen("-exclusive write"))) { + sscanf(line, "-exclusive write port %d", &(num_wr_ports)); + continue; + } + + if (!strncmp("-single ended", line, strlen("-single ended"))) { + sscanf(line, "-single %[(:-~)*]%d", jk, &(num_se_rd_ports)); + continue; + } + + if (!strncmp("-search", line, strlen("-search"))) { + sscanf(line, "-search port %d", &(num_search_ports)); + continue; + } + + if (!strncmp("-UCA bank", line, strlen("-UCA bank"))) { + sscanf(line, "-UCA bank%[((:-~)| )*]%d", jk, &(nbanks)); + continue; + } + + if (!strncmp("-technology", line, strlen("-technology"))) { + sscanf(line, "-technology (u) %lf", &(F_sz_um)); + F_sz_nm = F_sz_um * 1000; + continue; + } + + if (!strncmp("-hp Vdd", line, strlen("-hp Vdd"))) { + sscanf(line, "-hp Vdd%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_hp_vdd = false; + hp_Vdd = 1.0; /* + * if this is by default, then the vdd value in g_ip here + * does not matter + */ + } + else { + specific_hp_vdd = true; + sscanf(line, "-hp Vdd (V) %lf", &(hp_Vdd)); + } + continue; + } + + if (!strncmp("-lstp Vdd", line, strlen("-lstp Vdd"))) { + sscanf(line, "-lstp Vdd%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_lstp_vdd = false; + lstp_Vdd = 1.0; /* + * if this is by default, then the vdd value in g_ip + * here does not matter + */ + } + else { + specific_lstp_vdd = true; + sscanf(line, "-lstp Vdd (V) %lf", &(lstp_Vdd)); + } + continue; + } + + if (!strncmp("-lop Vdd", line, strlen("-lop Vdd"))) { + sscanf(line, "-lop Vdd%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_lop_vdd = false; + lop_Vdd = 1.0; /* + * if this is by default, then the vdd value in g_ip here + * does not matter + */ + } + else { + specific_lop_vdd = true; + sscanf(line, "-lop Vdd (V) %lf", &(lop_Vdd)); + } + continue; + } + + if (!strncmp("-DVS(V):", line, strlen("-DVS(V):"))) { + memmove(line, line + 9, strlen(line)); + while (1 == sscanf(data, "%lf%n", &temp_double, &offset)) { + data += offset; + dvs_voltage.push_back(temp_double); + } + // dvs_levels = dvs_voltage.size(); + continue; + } + + if (!strncmp("-Powergating voltage", line, + strlen("-Powergating voltage"))) { + sscanf(line, "-Powergating voltage%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_vcc_min = false; + user_defined_vcc_min = 1.0; /* + * if this is by default, then the vdd value + * in g_ip here does not matter + */ + } + else { + specific_vcc_min = true; + sscanf(line, "-Powergating voltage (V) %lf", &(user_defined_vcc_min)); + } + continue; + } + + if (!strncmp("-output/input", line, strlen("-output/input"))) { + sscanf(line, "-output/input bus %[(:-~)*]%d", jk, &(out_w)); + continue; + } + + if (!strncmp("-operating temperature", line, + strlen("-operating temperature"))) { + sscanf(line, "-operating temperature %[(:-~)*]%d", jk, &(temp)); + continue; + } + + if (!strncmp("-cache type", line, strlen("-cache type"))) { + sscanf(line, "-cache type%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("cache", temp_var, sizeof("cache"))) { + is_cache = true; + } + else { + is_cache = false; + } + + if (!strncmp("main memory", temp_var, sizeof("main memory"))) { + is_main_mem = true; + } + else { + is_main_mem = false; + } + + if (!strncmp("cam", temp_var, sizeof("cam"))) { + pure_cam = true; + } + else { + pure_cam = false; + } + + if (!strncmp("ram", temp_var, sizeof("ram"))) { + pure_ram = true; + } + else { + if (!is_main_mem) + pure_ram = false; + else + pure_ram = true; + } + + continue; + } + + if (!strncmp("-tag size", line, strlen("-tag size"))) { + sscanf(line, "-tag size%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("default", temp_var, sizeof("default"))) { + specific_tag = false; + tag_w = + 42; /* the acutal value is calculated + * later based on the cache size, bank count, and associativity + */ + } + else { + specific_tag = true; + sscanf(line, "-tag size (b) %d", &(tag_w)); + } + continue; + } + + if (!strncmp("-access mode", line, strlen("-access mode"))) { + sscanf(line, "-access %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("fast", temp_var, strlen("fast"))) { + access_mode = 2; + } + else if (!strncmp("sequential", temp_var, strlen("sequential"))) { + access_mode = 1; + } + else if (!strncmp("normal", temp_var, strlen("normal"))) { + access_mode = 0; + } + else { + cout << "ERROR: Invalid access mode!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Data array cell type", line, + strlen("-Data array cell type"))) { + sscanf(line, "-Data array cell type %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + data_arr_ram_cell_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + data_arr_ram_cell_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + data_arr_ram_cell_tech_type = 2; + } + else if (!strncmp("lp-dram", temp_var, strlen("lp-dram"))) { + data_arr_ram_cell_tech_type = 3; + } + else if (!strncmp("comm-dram", temp_var, strlen("comm-dram"))) { + data_arr_ram_cell_tech_type = 4; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Data array peripheral type", line, + strlen("-Data array peripheral type"))) { + sscanf(line, "-Data array peripheral type %[^\"]\"%[^\"]\"", jk, + temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + data_arr_peri_global_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + data_arr_peri_global_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + data_arr_peri_global_tech_type = 2; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Tag array cell type", line, + strlen("-Tag array cell type"))) { + sscanf(line, "-Tag array cell type %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + tag_arr_ram_cell_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + tag_arr_ram_cell_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + tag_arr_ram_cell_tech_type = 2; + } + else if (!strncmp("lp-dram", temp_var, strlen("lp-dram"))) { + tag_arr_ram_cell_tech_type = 3; + } + else if (!strncmp("comm-dram", temp_var, strlen("comm-dram"))) { + tag_arr_ram_cell_tech_type = 4; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + + if (!strncmp("-Tag array peripheral type", line, + strlen("-Tag array peripheral type"))) { + sscanf(line, "-Tag array peripheral type %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { + tag_arr_peri_global_tech_type = 0; + } + else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { + tag_arr_peri_global_tech_type = 1; + } + else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { + tag_arr_peri_global_tech_type = 2; + } + else { + cout << "ERROR: Invalid type!\n"; + exit(0); + } + continue; + } + if (!strncmp("-design", line, strlen("-design"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_wt), + &(dynamic_power_wt), &(leakage_power_wt), &(cycle_time_wt), + &(area_wt)); + continue; + } + + if (!strncmp("-deviate", line, strlen("-deviate"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_dev), + &(dynamic_power_dev), &(leakage_power_dev), &(cycle_time_dev), + &(area_dev)); + continue; + } + + if (!strncmp("-Optimize", line, strlen("-Optimize"))) { + sscanf(line, "-Optimize %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("ED^2", temp_var, strlen("ED^2"))) { + ed = 2; + } + else if (!strncmp("ED", temp_var, strlen("ED"))) { + ed = 1; + } + else { + ed = 0; + } + } + + if (!strncmp("-NUCAdesign", line, strlen("-NUCAdesign"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_wt_nuca), + &(dynamic_power_wt_nuca), &(leakage_power_wt_nuca), + &(cycle_time_wt_nuca), &(area_wt_nuca)); + continue; + } + + if (!strncmp("-NUCAdeviate", line, strlen("-NUCAdeviate"))) { + sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, &(delay_dev_nuca), + &(dynamic_power_dev_nuca), &(leakage_power_dev_nuca), + &(cycle_time_dev_nuca), &(area_dev_nuca)); + continue; + } + + if (!strncmp("-Cache model", line, strlen("-cache model"))) { + sscanf(line, "-Cache model %[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("UCA", temp_var, strlen("UCA"))) { + nuca = 0; + } + else { + nuca = 1; + } + continue; + } + + if (!strncmp("-NUCA bank", line, strlen("-NUCA bank"))) { + sscanf(line, "-NUCA bank count %d", &(nuca_bank_count)); + + if (nuca_bank_count != 0) { + force_nuca_bank = 1; + } + continue; + } + + if (!strncmp("-Wire inside mat", line, strlen("-Wire inside mat"))) { + sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("global", temp_var, strlen("global"))) { + wire_is_mat_type = 2; + continue; + } + else if (!strncmp("local", temp_var, strlen("local"))) { + wire_is_mat_type = 0; + continue; + } + else { + wire_is_mat_type = 1; + continue; + } + } + + if (!strncmp("-Wire outside mat", line, strlen("-Wire outside mat"))) { + sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("global", temp_var, strlen("global"))) { + wire_os_mat_type = 2; + } + else { + wire_os_mat_type = 1; + } + continue; + } + + if (!strncmp("-Interconnect projection", line, + strlen("-Interconnect projection"))) { + sscanf(line, "-Interconnect projection%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("aggressive", temp_var, strlen("aggressive"))) { + ic_proj_type = 0; + } + else { + ic_proj_type = 1; + } + continue; + } + + if (!strncmp("-Wire signalling", line, strlen("-wire signalling"))) { + sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); + + if (!strncmp("default", temp_var, strlen("default"))) { + force_wiretype = 0; + wt = Global; + } + else if (!(strncmp("Global_10", temp_var, strlen("Global_10")))) { + force_wiretype = 1; + wt = Global_10; + } + else if (!(strncmp("Global_20", temp_var, strlen("Global_20")))) { + force_wiretype = 1; + wt = Global_20; + } + else if (!(strncmp("Global_30", temp_var, strlen("Global_30")))) { + force_wiretype = 1; + wt = Global_30; + } + else if (!(strncmp("Global_5", temp_var, strlen("Global_5")))) { + force_wiretype = 1; + wt = Global_5; + } + else if (!(strncmp("Global", temp_var, strlen("Global")))) { + force_wiretype = 1; + wt = Global; + } + else { + wt = Low_swing; + force_wiretype = 1; + } + continue; + } + + if (!strncmp("-Core", line, strlen("-Core"))) { + sscanf(line, "-Core count %d\n", &(cores)); + if (cores > 16) { + printf("No. of cores should be less than 16!\n"); + } + continue; + } + + if (!strncmp("-Cache level", line, strlen("-Cache level"))) { + sscanf(line, "-Cache l%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("L2", temp_var, strlen("L2"))) { + cache_level = 0; + } + else { + cache_level = 1; + } + } + + if (!strncmp("-Print level", line, strlen("-Print level"))) { + sscanf(line, "-Print l%[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("DETAILED", temp_var, strlen("DETAILED"))) { + print_detail = 1; + } + else { + print_detail = 0; + } + } + if (!strncmp("-Add ECC", line, strlen("-Add ECC"))) { + sscanf(line, "-Add ECC %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + add_ecc_b_ = true; + } + else { + add_ecc_b_ = false; + } + } + + if (!strncmp("-CLDriver vertical", line, strlen("-CLDriver vertical"))) { + sscanf(line, "-CLDriver vertical %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + cl_vertical = true; + } + else { + cl_vertical = false; + } + } + + if (!strncmp("-Array Power Gating", line, strlen("-Array Power Gating"))) { + sscanf(line, "-Array Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + array_power_gated = true; + } + else { + array_power_gated = false; + } + } + + if (!strncmp("-Bitline floating", line, strlen("-Bitline floating"))) { + sscanf(line, "-Bitline floating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + bitline_floating = true; + } + else { + bitline_floating = false; + } + } + + if (!strncmp("-WL Power Gating", line, strlen("-WL Power Gating"))) { + sscanf(line, "-WL Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + wl_power_gated = true; + } + else { + wl_power_gated = false; + } + } + + if (!strncmp("-CL Power Gating", line, strlen("-CL Power Gating"))) { + sscanf(line, "-CL Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + cl_power_gated = true; + } + else { + cl_power_gated = false; + } + } + + if (!strncmp("-Interconnect Power Gating", line, + strlen("-Interconnect Power Gating"))) { + sscanf(line, "-Interconnect Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + interconect_power_gated = true; + } + else { + interconect_power_gated = false; + } + } + + if (!strncmp("-Power Gating Performance Loss", line, + strlen("-Power Gating Performance Loss"))) { + sscanf(line, "-Power Gating Performance Loss %lf", &(perfloss)); + continue; + } + + if (!strncmp("-Power Gating", line, strlen("-Power Gating"))) { + sscanf(line, "-Power Gating %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + power_gating = true; + } + else { + power_gating = false; + } + } + + if (!strncmp("-Long channel devices", line, + strlen("-Long channel devices"))) { + sscanf(line, "-Long channel devices %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + long_channel_device = true; + } + else { + long_channel_device = false; + } + } + + if (!strncmp("-Print input parameters", line, + strlen("-Print input parameters"))) { + sscanf(line, "-Print input %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + print_input_args = true; + } + else { + print_input_args = false; + } + } + + if (!strncmp("-Force cache config", line, strlen("-Force cache config"))) { + sscanf(line, "-Force cache %[^\"]\"%[^\"]\"", jk, temp_var); + if (!strncmp("true", temp_var, strlen("true"))) { + force_cache_config = true; + } + else { + force_cache_config = false; + } + } + + if (!strncmp("-Ndbl", line, strlen("-Ndbl"))) { + sscanf(line, "-Ndbl %d\n", &(ndbl)); + continue; + } + if (!strncmp("-Ndwl", line, strlen("-Ndwl"))) { + sscanf(line, "-Ndwl %d\n", &(ndwl)); + continue; + } + if (!strncmp("-Nspd", line, strlen("-Nspd"))) { + sscanf(line, "-Nspd %d\n", &(nspd)); + continue; + } + if (!strncmp("-Ndsam1", line, strlen("-Ndsam1"))) { + sscanf(line, "-Ndsam1 %d\n", &(ndsam1)); + continue; + } + if (!strncmp("-Ndsam2", line, strlen("-Ndsam2"))) { + sscanf(line, "-Ndsam2 %d\n", &(ndsam2)); + continue; + } + if (!strncmp("-Ndcm", line, strlen("-Ndcm"))) { + sscanf(line, "-Ndcm %d\n", &(ndcm)); + continue; + } + } + rpters_in_htree = true; + fclose(fp); +} + +void InputParameter::display_ip() { + cout << "Cache size : " << cache_sz << endl; + cout << "Block size : " << line_sz << endl; + cout << "Associativity : " << assoc << endl; + cout << "Read only ports : " << num_rd_ports << endl; + cout << "Write only ports : " << num_wr_ports << endl; + cout << "Read write ports : " << num_rw_ports << endl; + cout << "Single ended read ports : " << num_se_rd_ports << endl; + if (fully_assoc || pure_cam) { + cout << "Search ports : " << num_search_ports << endl; + } + cout << "Cache banks (UCA) : " << nbanks << endl; + cout << "Technology : " << F_sz_um << endl; + cout << "User specified HP Vdd (v)? : " << std::boolalpha + << specific_hp_vdd << endl; + if (specific_hp_vdd) { + cout << "User defined HP Vdd (v) : " << hp_Vdd << endl; + } + cout << "User specified LSTP Vdd (v)? : " << std::boolalpha + << specific_lstp_vdd << endl; + if (specific_lstp_vdd) { + cout << "User defined HP Vdd (v) : " << lstp_Vdd << endl; + } + cout << "User specified LOP Vdd (v)? : " << std::boolalpha + << specific_lop_vdd << endl; + if (specific_lop_vdd) { + cout << "User defined HP Vdd (v) : " << lop_Vdd << endl; + } + cout << "Temperature : " << temp << endl; + cout << "Tag size : " << tag_w << endl; + if (is_cache) { + cout << "array type : " + << "Cache" << endl; + } + if (pure_ram) { + cout << "array type : " + << "Scratch RAM" << endl; + } + if (pure_cam) { + cout << "array type : " + << "CAM" << endl; + } + cout << "Model as memory : " << is_main_mem << endl; + cout << "Access mode : " << access_mode << endl; + cout << "Data array cell type : " << data_arr_ram_cell_tech_type + << endl; + cout << "Data array peripheral type : " << data_arr_peri_global_tech_type + << endl; + cout << "Tag array cell type : " << tag_arr_ram_cell_tech_type + << endl; + cout << "Tag array peripheral type : " << tag_arr_peri_global_tech_type + << endl; + cout << "Optimization target : " << ed << endl; + cout << "Design objective (UCA wt) : " << delay_wt << " " + << dynamic_power_wt << " " << leakage_power_wt << " " << cycle_time_wt + << " " << area_wt << endl; + cout << "Design objective (UCA dev) : " << delay_dev << " " + << dynamic_power_dev << " " << leakage_power_dev << " " << cycle_time_dev + << " " << area_dev << endl; + if (nuca) { + cout << "Cores : " << cores << endl; + + cout << "Design objective (NUCA wt) : " << delay_wt_nuca << " " + << dynamic_power_wt_nuca << " " << leakage_power_wt_nuca << " " + << cycle_time_wt_nuca << " " << area_wt_nuca << endl; + cout << "Design objective (NUCA dev) : " << delay_dev_nuca << " " + << dynamic_power_dev_nuca << " " << leakage_power_dev_nuca << " " + << cycle_time_dev_nuca << " " << area_dev_nuca << endl; + } + cout << "Cache model : " << nuca << endl; + cout << "Nuca bank : " << nuca_bank_count << endl; + cout << "Wire inside mat : " << wire_is_mat_type << endl; + cout << "Wire outside mat : " << wire_os_mat_type << endl; + cout << "Interconnect projection : " << ic_proj_type << endl; + cout << "Wire signalling : " << force_wiretype << endl; + cout << "Print level : " << print_detail << endl; + cout << "ECC overhead : " << add_ecc_b_ << endl; + cout << "Page size : " << page_sz_bits << endl; + cout << "Burst length : " << burst_len << endl; + cout << "Internal prefetch width : " << int_prefetch_w << endl; + cout << "Force cache config : " << g_ip->force_cache_config + << endl; + if (g_ip->force_cache_config) { + cout << "Ndwl : " << g_ip->ndwl << endl; + cout << "Ndbl : " << g_ip->ndbl << endl; + cout << "Nspd : " << g_ip->nspd << endl; + cout << "Ndcm : " << g_ip->ndcm << endl; + cout << "Ndsam1 : " << g_ip->ndsam1 << endl; + cout << "Ndsam2 : " << g_ip->ndsam2 << endl; + } + // cout << "Placing subarray out driver vertical? : " << g_ip->cl_vertical + // << endl; +} + +powerComponents operator+(const powerComponents &x, const powerComponents &y) { + powerComponents z; + + z.dynamic = x.dynamic + y.dynamic; + z.leakage = x.leakage + y.leakage; + z.gate_leakage = x.gate_leakage + y.gate_leakage; + z.short_circuit = x.short_circuit + y.short_circuit; + z.longer_channel_leakage = + x.longer_channel_leakage + y.longer_channel_leakage; + z.power_gated_leakage = x.power_gated_leakage + y.power_gated_leakage; + z.power_gated_with_long_channel_leakage = + x.power_gated_with_long_channel_leakage + + y.power_gated_with_long_channel_leakage; + + return z; +} + +powerComponents operator*(const powerComponents &x, double const *const y) { + powerComponents z; + + z.dynamic = x.dynamic * y[0]; + z.leakage = x.leakage * y[1]; + z.gate_leakage = x.gate_leakage * y[2]; + z.short_circuit = x.short_circuit * y[3]; + z.longer_channel_leakage = + x.longer_channel_leakage * + y[1]; // longer channel leakage has the same behavior as normal leakage + z.power_gated_leakage = + x.power_gated_leakage * + y[1]; // power_gated_leakage has the same behavior as normal leakage + z.power_gated_with_long_channel_leakage = + x.power_gated_with_long_channel_leakage * + y[1]; // power_gated_with_long_channel_leakage has the same behavior as + // normal leakage + return z; +} + +powerDef operator+(const powerDef &x, const powerDef &y) { + powerDef z; + + z.readOp = x.readOp + y.readOp; + z.writeOp = x.writeOp + y.writeOp; + z.searchOp = x.searchOp + y.searchOp; + return z; +} + +powerDef operator*(const powerDef &x, double const *const y) { + powerDef z; + + z.readOp = x.readOp * y; + z.writeOp = x.writeOp * y; + z.searchOp = x.searchOp * y; + return z; +} + +uca_org_t cacti_interface(const string &infile_name) { + uca_org_t fin_res; + // uca_org_t result; + fin_res.valid = false; + + g_ip = new InputParameter(); + g_ip->parse_cfg(infile_name); + if (!g_ip->error_checking()) + exit(0); + if (g_ip->print_input_args) + g_ip->display_ip(); + + init_tech_params(g_ip->F_sz_um, false); // this init is for initializing + // wires + Wire winit; // Do not delete this line. It initializes wires. + // g_tp.peri_global.display(); + // g_tp.sram_cell.display(); + + // For HighRadix Only + // //// Wire wirea(g_ip->wt, 1000); + // //// wirea.print_wire(); + // //// cout << "Wire Area " << wirea.area.get_area() << " sq. u" << endl; + // // winit.print_wire(); + // // + // HighRadix *hr; + // hr = new HighRadix(); + // hr->compute_power(); + // hr->print_router(); + // exit(0); + // + // double sub_switch_sz = 2; + // double rows = 32; + // for (int i=0; i<6; i++) { + // sub_switch_sz = pow(2, i); + // rows = 64/sub_switch_sz; + // hr = new HighRadix(sub_switch_sz, rows, .8/* freq */, 64, 2, 64, 0.7); + // hr->compute_power(); + // hr->print_router(); + // delete hr; + // } + // // HighRadix yarc; + // // yarc.compute_power(); + // // yarc.print_router(); + // winit.print_wire(); + // exit(0); + // For HighRadix Only End + + if (g_ip->nuca == 1) { + Nuca n(&g_tp.peri_global); + n.sim_nuca(); + } + + // g_ip->display_ip(); + + solve(&fin_res); + // output_UCA(&fin_res); + // Wire::print_wire(); + output_data_csv(fin_res); + + if (!g_ip->dvs_voltage.empty()) { + update_dvs(&fin_res); + } + if (g_ip->power_gating) { + update_pg(&fin_res); // this is needed for compute area overhead of + // power-gating, even the gated power is calculated + // together un-gated leakage + } + output_UCA(&fin_res); + + Wire wprint; // reset wires to original configuration as in *.cfg file (dvs + // level 0) + Wire::print_wire(); + + delete (g_ip); + return fin_res; +} + +// cacti6.5's plain interface, please keep !!! +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, int excl_write_ports, int single_ended_read_ports, + int banks, + double tech_node, // in nm + int page_sz, int burst_length, int pre_width, int output_width, + int specific_tag, int tag_width, + int access_mode, // 0 normal, 1 seq, 2 fast + int cache, // scratch ram or cache + int main_mem, int obj_func_delay, int obj_func_dynamic_power, + int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, + int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, + int dev_func_area, int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, // 0-4 + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, // 0 - aggressive, 1 - normal + int wire_inside_mat_type_in, int wire_outside_mat_type_in, + int is_nuca, // 0 - UCA, 1 - NUCA + int core_count, + int cache_level, // 0 - L2, 1 - L3 + int nuca_bank_count, int nuca_obj_func_delay, + int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, + int nuca_obj_func_area, int nuca_obj_func_cycle_time, + int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, + int nuca_dev_func_leakage_power, int nuca_dev_func_area, + int nuca_dev_func_cycle_time, + int REPEATERS_IN_HTREE_SEGMENTS_in, // TODO for now only wires with + // repeaters are supported + int p_input) { + g_ip = new InputParameter(); + g_ip->add_ecc_b_ = true; + + g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in; + g_ip->tag_arr_ram_cell_tech_type = tag_arr_ram_cell_tech_flavor_in; + g_ip->tag_arr_peri_global_tech_type = tag_arr_peri_global_tech_flavor_in; + + g_ip->ic_proj_type = interconnect_projection_type_in; + g_ip->wire_is_mat_type = wire_inside_mat_type_in; + g_ip->wire_os_mat_type = wire_outside_mat_type_in; + g_ip->burst_len = burst_length; + g_ip->int_prefetch_w = pre_width; + g_ip->page_sz_bits = page_sz; + + g_ip->cache_sz = cache_size; + g_ip->line_sz = line_size; + g_ip->assoc = associativity; + g_ip->nbanks = banks; + g_ip->out_w = output_width; + g_ip->specific_tag = specific_tag; + if (tag_width == 0) { + g_ip->tag_w = 42; + } + else { + g_ip->tag_w = tag_width; + } + + g_ip->access_mode = access_mode; + g_ip->delay_wt = obj_func_delay; + g_ip->dynamic_power_wt = obj_func_dynamic_power; + g_ip->leakage_power_wt = obj_func_leakage_power; + g_ip->area_wt = obj_func_area; + g_ip->cycle_time_wt = obj_func_cycle_time; + g_ip->delay_dev = dev_func_delay; + g_ip->dynamic_power_dev = dev_func_dynamic_power; + g_ip->leakage_power_dev = dev_func_leakage_power; + g_ip->area_dev = dev_func_area; + g_ip->cycle_time_dev = dev_func_cycle_time; + g_ip->ed = ed_ed2_none; + + switch (wt) { + case (0): + g_ip->force_wiretype = 0; + g_ip->wt = Global; + break; + case (1): + g_ip->force_wiretype = 1; + g_ip->wt = Global; + break; + case (2): + g_ip->force_wiretype = 1; + g_ip->wt = Global_5; + break; + case (3): + g_ip->force_wiretype = 1; + g_ip->wt = Global_10; + break; + case (4): + g_ip->force_wiretype = 1; + g_ip->wt = Global_20; + break; + case (5): + g_ip->force_wiretype = 1; + g_ip->wt = Global_30; + break; + case (6): + g_ip->force_wiretype = 1; + g_ip->wt = Low_swing; + break; + default: + cout << "Unknown wire type!\n"; + exit(0); + } + + g_ip->delay_wt_nuca = nuca_obj_func_delay; + g_ip->dynamic_power_wt_nuca = nuca_obj_func_dynamic_power; + g_ip->leakage_power_wt_nuca = nuca_obj_func_leakage_power; + g_ip->area_wt_nuca = nuca_obj_func_area; + g_ip->cycle_time_wt_nuca = nuca_obj_func_cycle_time; + g_ip->delay_dev_nuca = dev_func_delay; + g_ip->dynamic_power_dev_nuca = nuca_dev_func_dynamic_power; + g_ip->leakage_power_dev_nuca = nuca_dev_func_leakage_power; + g_ip->area_dev_nuca = nuca_dev_func_area; + g_ip->cycle_time_dev_nuca = nuca_dev_func_cycle_time; + g_ip->nuca = is_nuca; + g_ip->nuca_bank_count = nuca_bank_count; + if (nuca_bank_count > 0) { + g_ip->force_nuca_bank = 1; + } + g_ip->cores = core_count; + g_ip->cache_level = cache_level; + + g_ip->temp = temp; + + g_ip->F_sz_nm = tech_node; + g_ip->F_sz_um = tech_node / 1000; + g_ip->is_main_mem = (main_mem != 0) ? true : false; + g_ip->is_cache = (cache != 0) ? true : false; + g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false; + + g_ip->num_rw_ports = rw_ports; + g_ip->num_rd_ports = excl_read_ports; + g_ip->num_wr_ports = excl_write_ports; + g_ip->num_se_rd_ports = single_ended_read_ports; + g_ip->print_detail = 1; + g_ip->nuca = 0; + + g_ip->wt = Global_5; + g_ip->force_cache_config = false; + g_ip->force_wiretype = false; + g_ip->print_input_args = p_input; + + uca_org_t fin_res; + fin_res.valid = false; + + if (g_ip->error_checking() == false) + exit(0); + if (g_ip->print_input_args) + g_ip->display_ip(); + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + + if (g_ip->nuca == 1) { + Nuca n(&g_tp.peri_global); + n.sim_nuca(); + } + solve(&fin_res); + + output_UCA(&fin_res); + + delete (g_ip); + return fin_res; +} + +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface( + int cache_size, int line_size, int associativity, int rw_ports, + int excl_read_ports, // para5 + int excl_write_ports, int single_ended_read_ports, int search_ports, + int banks, + double tech_node, // para10 + int output_width, int specific_tag, int tag_width, int access_mode, + int cache, // para15 + int main_mem, int obj_func_delay, int obj_func_dynamic_power, + int obj_func_leakage_power, + int obj_func_cycle_time, // para20 + int obj_func_area, int dev_func_delay, int dev_func_dynamic_power, + int dev_func_leakage_power, + int dev_func_area, // para25 + int dev_func_cycle_time, + int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate + int temp, + int wt, // 0 - default(search across everything), 1 - global, 2 - 5% delay + // penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing + int data_arr_ram_cell_tech_flavor_in, // para30 + int data_arr_peri_global_tech_flavor_in, + int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, + int interconnect_projection_type_in, + int wire_inside_mat_type_in, // para35 + int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, + int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, + int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, + int PAGE_SIZE_BITS_in, // para40 + int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, + int wiretype, + int force_config, // para45 + int ndwl, int ndbl, int nspd, int ndcm, + int ndsam1, // para50 + int ndsam2, int ecc) { + g_ip = new InputParameter(); + + uca_org_t fin_res; + fin_res.valid = false; + + g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in; + g_ip->tag_arr_ram_cell_tech_type = tag_arr_ram_cell_tech_flavor_in; + g_ip->tag_arr_peri_global_tech_type = tag_arr_peri_global_tech_flavor_in; + + g_ip->ic_proj_type = interconnect_projection_type_in; + g_ip->wire_is_mat_type = wire_inside_mat_type_in; + g_ip->wire_os_mat_type = wire_outside_mat_type_in; + g_ip->burst_len = BURST_LENGTH_in; + g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; + g_ip->page_sz_bits = PAGE_SIZE_BITS_in; + + g_ip->cache_sz = cache_size; + g_ip->line_sz = line_size; + g_ip->assoc = associativity; + g_ip->nbanks = banks; + g_ip->out_w = output_width; + g_ip->specific_tag = specific_tag; + if (specific_tag == 0) { + g_ip->tag_w = 42; + } + else { + g_ip->tag_w = tag_width; + } + + g_ip->access_mode = access_mode; + g_ip->delay_wt = obj_func_delay; + g_ip->dynamic_power_wt = obj_func_dynamic_power; + g_ip->leakage_power_wt = obj_func_leakage_power; + g_ip->area_wt = obj_func_area; + g_ip->cycle_time_wt = obj_func_cycle_time; + g_ip->delay_dev = dev_func_delay; + g_ip->dynamic_power_dev = dev_func_dynamic_power; + g_ip->leakage_power_dev = dev_func_leakage_power; + g_ip->area_dev = dev_func_area; + g_ip->cycle_time_dev = dev_func_cycle_time; + g_ip->temp = temp; + g_ip->ed = ed_ed2_none; + + g_ip->F_sz_nm = tech_node; + g_ip->F_sz_um = tech_node / 1000; + g_ip->is_main_mem = (main_mem != 0) ? true : false; + g_ip->is_cache = (cache == 1) ? true : false; + g_ip->pure_ram = (cache == 0) ? true : false; + g_ip->pure_cam = (cache == 2) ? true : false; + g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false; + g_ip->ver_htree_wires_over_array = VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; + g_ip->broadcast_addr_din_over_ver_htrees = + BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; + + g_ip->num_rw_ports = rw_ports; + g_ip->num_rd_ports = excl_read_ports; + g_ip->num_wr_ports = excl_write_ports; + g_ip->num_se_rd_ports = single_ended_read_ports; + g_ip->num_search_ports = search_ports; + + g_ip->print_detail = 1; + g_ip->nuca = 0; + + if (force_wiretype == 0) { + g_ip->wt = Global; + g_ip->force_wiretype = false; + } + else { + g_ip->force_wiretype = true; + if (wiretype == 10) { + g_ip->wt = Global_10; + } + if (wiretype == 20) { + g_ip->wt = Global_20; + } + if (wiretype == 30) { + g_ip->wt = Global_30; + } + if (wiretype == 5) { + g_ip->wt = Global_5; + } + if (wiretype == 0) { + g_ip->wt = Low_swing; + } + } + // g_ip->wt = Global_5; + if (force_config == 0) { + g_ip->force_cache_config = false; + } + else { + g_ip->force_cache_config = true; + g_ip->ndbl = ndbl; + g_ip->ndwl = ndwl; + g_ip->nspd = nspd; + g_ip->ndcm = ndcm; + g_ip->ndsam1 = ndsam1; + g_ip->ndsam2 = ndsam2; + } + + if (ecc == 0) { + g_ip->add_ecc_b_ = false; + } + else { + g_ip->add_ecc_b_ = true; + } + + if (!g_ip->error_checking()) + exit(0); + + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + + g_ip->display_ip(); + solve(&fin_res); + output_UCA(&fin_res); + output_data_csv(fin_res); + delete (g_ip); + + return fin_res; +} + +bool InputParameter::error_checking() { + int A; + bool seq_access = false; + fast_access = true; + fully_assoc = false; + + switch (access_mode) { + case 0: + seq_access = false; + fast_access = false; + break; + case 1: + seq_access = true; + fast_access = false; + break; + case 2: + seq_access = false; + fast_access = true; + break; + } + + if (is_main_mem) { + if (ic_proj_type == 0) { + cerr << "DRAM model supports only conservative interconnect " + "projection!\n\n"; + return false; + } + } + + uint32_t B = line_sz; + + if (B < 1) { + cerr << "Block size must >= 1" << endl; + return false; + } + else if (B * 8 < out_w) { + cerr << "Block size must be at least " << out_w / 8 << endl; + return false; + } + + if (F_sz_um <= 0) { + cerr << "Feature size must be > 0" << endl; + return false; + } + else if (F_sz_um > 0.181) { + cerr << "Feature size must be <= 180 nm" << endl; + return false; + } + else if (F_sz_um > 0.091 && (data_arr_ram_cell_tech_type != itrs_hp || + tag_arr_ram_cell_tech_type != itrs_hp || + data_arr_peri_global_tech_type != itrs_hp || + tag_arr_peri_global_tech_type != itrs_hp)) { + cerr << "Feature size from 90nm to 180 nm only support the ITRS HP device " + "type" + << endl; + return false; + } + + uint32_t RWP = num_rw_ports; + uint32_t ERP = num_rd_ports; + uint32_t EWP = num_wr_ports; + uint32_t NSER = num_se_rd_ports; + uint32_t SCHP = num_search_ports; + + // TODO: revisit this. This is an important feature. Sheng thought this should + // be used + // // If multiple banks and multiple ports are specified, then if number of + // ports is less than or equal to + // // the number of banks, we assume that the multiple ports are implemented + // via the multiple banks. + // // In such a case we assume that each bank has 1 RWP port. + // if ((RWP + ERP + EWP) <= nbanks && nbanks>1) + // { + // RWP = 1; + // ERP = 0; + // EWP = 0; + // NSER = 0; + // } + // else if ((RWP < 0) || (EWP < 0) || (ERP < 0)) + // { + // cerr << "Ports must >=0" << endl; + // return false; + // } + // else if (RWP > 2) + // { + // cerr << "Maximum of 2 read/write ports" << endl; + // return false; + // } + // else if ((RWP+ERP+EWP) < 1) + // Changed to new implementation: + // The number of ports specified at input is per bank + if ((RWP + ERP + EWP) < 1) { + cerr << "Must have at least one port" << endl; + return false; + } + + if (is_pow2(nbanks) == false) { + cerr << "Number of subbanks should be greater than or equal to 1 and " + "should be a power of 2" + << endl; + return false; + } + + int C = cache_sz / nbanks; + if (C < 64) { + cerr << "Cache size must >=64" << endl; + return false; + } + + // TODO: revisit this + // if (pure_ram==true && assoc!=1) + // { + // cerr << "Pure RAM must have assoc as 1" << endl; + // return false; + // } + + // fully assoc and cam check + if (is_cache && assoc == 0) + fully_assoc = true; + else + fully_assoc = false; + + if (pure_cam == true && assoc != 0) { + cerr << "Pure CAM must have associativity as 0" << endl; + return false; + } + + if (assoc == 0 && (pure_cam == false && is_cache == false)) { + cerr << "Only CAM or Fully associative cache can have associativity as 0" + << endl; + return false; + } + + if ((fully_assoc == true || pure_cam == true) && + (data_arr_ram_cell_tech_type != tag_arr_ram_cell_tech_type || + data_arr_peri_global_tech_type != tag_arr_peri_global_tech_type)) { + cerr << "CAM and fully associative cache must have same device type for " + "both data and tag array" + << endl; + return false; + } + + if ((fully_assoc == true || pure_cam == true) && + (data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram)) { + cerr << "DRAM based CAM and fully associative cache are not supported" + << endl; + return false; + } + + if ((fully_assoc == true || pure_cam == true) && (is_main_mem == true)) { + cerr << "CAM and fully associative cache cannot be as main memory" << endl; + return false; + } + + if ((fully_assoc || pure_cam) && SCHP < 1) { + cerr << "CAM and fully associative must have at least 1 search port" + << endl; + return false; + } + + if (RWP == 0 && ERP == 0 && SCHP > 0 && ((fully_assoc || pure_cam))) { + ERP = SCHP; + } + + // if ((!(fully_assoc || pure_cam)) && SCHP>=1) + // { + // cerr << "None CAM and fully associative cannot have search ports" << + // endl; return false; + // } + + if (assoc == 0) { + A = C / B; + // fully_assoc = true; + } + else { + if (assoc == 1) { + A = 1; + // fully_assoc = false; + } + else { + // fully_assoc = false; + A = assoc; + if (is_pow2(A) == false) { + cerr << "Associativity must be a power of 2" << endl; + return false; + } + } + } + + if (C / (B * A) <= 1 && assoc != 0) { + cerr << "Number of sets is too small: " << endl; + cerr << " Need to either increase cache size, or decrease associativity or " + "block size" + << endl; + cerr << " (or use fully associative cache)" << endl; + return false; + } + + block_sz = B; + + /*dt: testing sequential access mode*/ + if (seq_access) { + tag_assoc = A; + data_assoc = 1; + is_seq_acc = true; + } + else { + tag_assoc = A; + data_assoc = A; + is_seq_acc = false; + } + + if (assoc == 0) { + data_assoc = 1; + } + num_rw_ports = RWP; + num_rd_ports = ERP; + num_wr_ports = EWP; + num_se_rd_ports = NSER; + if (!(fully_assoc || pure_cam)) + num_search_ports = 0; + nsets = C / (B * A); + + if (temp < 300 || temp > 400 || temp % 10 != 0) { + cerr + << temp + << " Temperature must be between 300 and 400 Kelvin and multiple of 10." + << endl; + return false; + } + + if (nsets < 1) { + cerr << "Less than one set..." << endl; + return false; + } + + // power_gating = (array_power_gated + // || bitline_floating + // || wl_power_gated + // || cl_power_gated + // || interconect_power_gated)?true:false; + + if (power_gating) { + array_power_gated = true; + bitline_floating = true; + wl_power_gated = true; + cl_power_gated = true; + interconect_power_gated = true; + } + else { + array_power_gated = false; + bitline_floating = false; + wl_power_gated = false; + cl_power_gated = false; + interconect_power_gated = false; + } + + // if (power_gating && (!dvs_voltage.empty())) + // { + // cerr << "Power gating and DVS cannot be active simultaneously, please + // model them in two runs.\n\n"; return false; + // } + + if (power_gating && (pure_cam || fully_assoc)) { + cerr << "Power gating in CAM is not supported yet.\n\n" << endl; + return false; + } + + if (power_gating && (is_main_mem || data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram || + tag_arr_ram_cell_tech_type == lp_dram || + tag_arr_ram_cell_tech_type == comm_dram || + data_arr_peri_global_tech_type == lp_dram || + data_arr_peri_global_tech_type == comm_dram || + tag_arr_peri_global_tech_type == lp_dram || + tag_arr_peri_global_tech_type == comm_dram)) { + cerr << "Power gating in DRAM is not supported. \n\n" << endl; + return false; + } + + if (long_channel_device && + (is_main_mem || data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram || + tag_arr_ram_cell_tech_type == lp_dram || + tag_arr_ram_cell_tech_type == comm_dram || + data_arr_peri_global_tech_type == lp_dram || + data_arr_peri_global_tech_type == comm_dram || + tag_arr_peri_global_tech_type == lp_dram || + tag_arr_peri_global_tech_type == comm_dram)) { + cerr << "Long Channel Device in DRAM is not supported. \n\n" << endl; + return false; + } + + if ((!dvs_voltage.empty()) && + (is_main_mem || data_arr_ram_cell_tech_type == lp_dram || + data_arr_ram_cell_tech_type == comm_dram || + tag_arr_ram_cell_tech_type == lp_dram || + tag_arr_ram_cell_tech_type == comm_dram || + data_arr_peri_global_tech_type == lp_dram || + data_arr_peri_global_tech_type == comm_dram || + tag_arr_peri_global_tech_type == lp_dram || + tag_arr_peri_global_tech_type == comm_dram)) { + cerr << "DVS in DRAM is not supported. \n\n" << endl; + return false; + } + + // if (power_gating && (specific_hp_vdd + // || specific_lstp_vdd + // || specific_lop_vdd)) + // { + // cerr << "Default Vdd is recommended when enabling power gating.\n\n"<< + // endl; return false; + // } + + if ((!dvs_voltage.empty()) && + ((data_arr_ram_cell_tech_type != data_arr_peri_global_tech_type) || + (tag_arr_peri_global_tech_type != tag_arr_ram_cell_tech_type) || + (data_arr_ram_cell_tech_type != tag_arr_ram_cell_tech_type))) { + cerr << "Same device types is recommended for tag/data/cell/peripheral for " + "DVS. Same DVS voltage will be applied to different device " + "types\n\n"; + return false; + } + + return true; +} + +void output_data_csv(const uca_org_t &fin_res) { + // TODO: the csv output should remain + fstream file("out.csv", ios::in); + bool print_index = file.fail(); + file.close(); + + file.open("out.csv", ios::out | ios::app); + if (file.fail() == true) { + cerr << "File out.csv could not be opened successfully" << endl; + } + else { + if (print_index == true) { + file << "Tech node (nm), "; + file << "Capacity (bytes), "; + file << "Number of banks, "; + file << "Associativity, "; + file << "Output width (bits), "; + file << "Access time (ns), "; + file << "Random cycle time (ns), "; + // file << "Multisubbank interleave cycle time (ns), "; + + // file << "Delay request network (ns), "; + // file << "Delay inside mat (ns), "; + // file << "Delay reply network (ns), "; + // file << "Tag array access time (ns), "; + // file << "Data array access time (ns), "; + // file << "Refresh period (microsec), "; + // file << "DRAM array availability (%), "; + file << "Dynamic search energy (nJ), "; + file << "Dynamic read energy (nJ), "; + file << "Dynamic write energy (nJ), "; + // file << "Tag Dynamic read energy (nJ), "; + // file << "Data Dynamic read energy (nJ), "; + // file << "Dynamic read power (mW), "; + file << "Standby leakage per bank(mW), "; + // file << "Leakage per bank with leak power management (mW), "; + // file << "Leakage per bank with leak power management (mW), "; + // file << "Refresh power as percentage of standby leakage, "; + file << "Area (mm2), "; + file << "Ndwl, "; + file << "Ndbl, "; + file << "Nspd, "; + file << "Ndcm, "; + file << "Ndsam_level_1, "; + file << "Ndsam_level_2, "; + file << "Data arrary area efficiency %, "; + file << "Ntwl, "; + file << "Ntbl, "; + file << "Ntspd, "; + file << "Ntcm, "; + file << "Ntsam_level_1, "; + file << "Ntsam_level_2, "; + file << "Tag arrary area efficiency %, "; + + // file << "Resistance per unit micron (ohm-micron), "; + // file << "Capacitance per unit micron (fF per micron), "; + // file << "Unit-length wire delay (ps), "; + // file << "FO4 delay (ps), "; + // file << "delay route to bank (including crossb delay) (ps), "; + // file << "Crossbar delay (ps), "; + // file << "Dyn read energy per access from closed page (nJ), "; + // file << "Dyn read energy per access from open page (nJ), "; + // file << "Leak power of an subbank with page closed (mW), "; + // file << "Leak power of a subbank with page open (mW), "; + // file << "Leak power of request and reply networks (mW), "; + // file << "Number of subbanks, "; + // file << "Page size in bits, "; + // file << "Activate power, "; + // file << "Read power, "; + // file << "Write power, "; + // file << "Precharge power, "; + // file << "tRCD, "; + // file << "CAS latency, "; + // file << "Precharge delay, "; + // file << "Perc dyn energy bitlines, "; + // file << "perc dyn energy wordlines, "; + // file << "perc dyn energy outside mat, "; + // file << "Area opt (perc), "; + // file << "Delay opt (perc), "; + // file << "Repeater opt (perc), "; + // file << "Aspect ratio"; + file << endl; + } + file << g_ip->F_sz_nm << ", "; + file << g_ip->cache_sz << ", "; + file << g_ip->nbanks << ", "; + file << g_ip->tag_assoc << ", "; + file << g_ip->out_w << ", "; + file << fin_res.access_time * 1e+9 << ", "; + file << fin_res.cycle_time * 1e+9 << ", "; + // file << fin_res.data_array2->multisubbank_interleave_cycle_time*1e+9 + // << ", "; file << fin_res.data_array2->delay_request_network*1e+9 << ", + // "; file << fin_res.data_array2->delay_inside_mat*1e+9 << ", "; file + // << fin_res.data_array2.delay_reply_network*1e+9 << ", "; + + // if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) + // { + // file << fin_res.tag_array2->access_time*1e+9 << ", "; + // } + // else + // { + // file << 0 << ", "; + // } + // file << fin_res.data_array2->access_time*1e+9 << ", "; + // file << fin_res.data_array2->dram_refresh_period*1e+6 << ", "; + // file << fin_res.data_array2->dram_array_availability << ", "; + if (g_ip->fully_assoc || g_ip->pure_cam) { + file << fin_res.power.searchOp.dynamic * 1e+9 << ", "; + } + else { + file << "N/A" + << ", "; + } + file << fin_res.power.readOp.dynamic * 1e+9 << ", "; + file << fin_res.power.writeOp.dynamic * 1e+9 << ", "; + // if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) + // { + // file << fin_res.tag_array2->power.readOp.dynamic*1e+9 << ", "; + // } + // else + // { + // file << "NA" << ", "; + // } + // file << fin_res.data_array2->power.readOp.dynamic*1e+9 << ", "; + // if (g_ip->fully_assoc || g_ip->pure_cam) + // { + // file << + // fin_res.power.searchOp.dynamic*1000/fin_res.cycle_time << ", "; + // } + // else + // { + // file << fin_res.power.readOp.dynamic*1000/fin_res.cycle_time << + // ", "; + // } + + file << (fin_res.power.readOp.leakage + fin_res.power.readOp.gate_leakage) * + 1000 + << ", "; + // file << fin_res.leak_power_with_sleep_transistors_in_mats*1000 << ", + // "; file << fin_res.data_array.refresh_power / + // fin_res.data_array.total_power.readOp.leakage << ", "; + file << fin_res.area * 1e-6 << ", "; + + file << fin_res.data_array2->Ndwl << ", "; + file << fin_res.data_array2->Ndbl << ", "; + file << fin_res.data_array2->Nspd << ", "; + file << fin_res.data_array2->deg_bl_muxing << ", "; + file << fin_res.data_array2->Ndsam_lev_1 << ", "; + file << fin_res.data_array2->Ndsam_lev_2 << ", "; + file << fin_res.data_array2->area_efficiency << ", "; + if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) { + file << fin_res.tag_array2->Ndwl << ", "; + file << fin_res.tag_array2->Ndbl << ", "; + file << fin_res.tag_array2->Nspd << ", "; + file << fin_res.tag_array2->deg_bl_muxing << ", "; + file << fin_res.tag_array2->Ndsam_lev_1 << ", "; + file << fin_res.tag_array2->Ndsam_lev_2 << ", "; + file << fin_res.tag_array2->area_efficiency << ", "; + } + else { + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + file << "N/A" + << ", "; + } + + // file << g_tp.wire_inside_mat.R_per_um << ", "; + // file << g_tp.wire_inside_mat.C_per_um / 1e-15 << ", "; + // file << g_tp.unit_len_wire_del / 1e-12 << ", "; + // file << g_tp.FO4 / 1e-12 << ", "; + // file << fin_res.data_array.delay_route_to_bank / 1e-9 << ", "; + // file << fin_res.data_array.delay_crossbar / 1e-9 << ", "; + // file << fin_res.data_array.dyn_read_energy_from_closed_page / 1e-9 << + // ", "; file << fin_res.data_array.dyn_read_energy_from_open_page / 1e-9 + // << ", "; file << fin_res.data_array.leak_power_subbank_closed_page / + // 1e-3 << ", "; file << fin_res.data_array.leak_power_subbank_open_page + // / 1e-3 << ", "; file << + // fin_res.data_array.leak_power_request_and_reply_networks / 1e-3 << ", + // "; file << fin_res.data_array.number_subbanks << ", " ; file << + // fin_res.data_array.page_size_in_bits << ", " ; file << + // fin_res.data_array.activate_energy * 1e9 << ", " ; file << + // fin_res.data_array.read_energy * 1e9 << ", " ; file << + // fin_res.data_array.write_energy * 1e9 << ", " ; file << + // fin_res.data_array.precharge_energy * 1e9 << ", " ; file << + // fin_res.data_array.trcd * 1e9 << ", " ; file << + // fin_res.data_array.cas_latency * 1e9 << ", " ; file << + // fin_res.data_array.precharge_delay * 1e9 << ", " ; file << + // fin_res.data_array.all_banks_height / + // fin_res.data_array.all_banks_width; + file << endl; + } + file.close(); +} + +void output_UCA(uca_org_t *fr) { + double long_channel_leakage_reduction = + 0.1 + + 0.9 * (0.8 * fr->data_array2->long_channel_leakage_reduction_memcell + + 0.2 * fr->data_array2 + ->long_channel_leakage_reduction_periperal); // TODO + double areaoverhead, overhead_data, overhead_tag; + double wakeup_E, wakeup_T, wakeup_E_data, wakeup_T_data = 0., wakeup_E_tag, + wakeup_T_tag = 0.; + int dvs_levels = g_ip->dvs_voltage.size(); + int i; + bool dvs = !g_ip->dvs_voltage.empty(); + // if (NUCA) + if (0) { + cout << "\n\n Detailed Bank Stats:\n"; + cout << " Bank Size (bytes): %d\n" << (int)(g_ip->cache_sz); + } + else { + if (g_ip->data_arr_ram_cell_tech_type == 3) { + cout << "\n---------- CACTI-P, with new features: " << VER_COMMENT_CACTI + << " of " << VER_UPDATE_CACTI << "), Uniform Cache Access " + << "Logic Process Based DRAM Model ----------\n"; + } + else if (g_ip->data_arr_ram_cell_tech_type == 4) { + cout << "\n---------- CACTI-P, with new features: " << VER_COMMENT_CACTI + << " of " << VER_UPDATE_CACTI << "), Uniform" + << "Cache Access Commodity DRAM Model ----------\n"; + } + else { + cout << "\n---------- CACTI-P, with new features: " << VER_COMMENT_CACTI + << " of " << VER_UPDATE_CACTI + << "), Uniform Cache Access " + "SRAM Model ----------\n"; + } + // (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<< + // VER_postfix_CACTI<<"; (version "<< VER_MAJOR_CACTI <<"."<< + // VER_MINOR_CACTI<<"."VER_COMMENT_CACTI << VER_postfix_CACTI + // << " of + // " + // << VER_UPDATE_CACTI << ") + cout << "\nCache Parameters:\n"; + cout << " Total cache size (bytes): " << (int)(g_ip->cache_sz) << endl; + } + + cout << " Number of banks: " << (int)g_ip->nbanks << endl; + if (g_ip->fully_assoc || g_ip->pure_cam) + cout << " Associativity: fully associative\n"; + else { + if (g_ip->tag_assoc == 1) + cout << " Associativity: direct mapped\n"; + else + cout << " Associativity: " << g_ip->tag_assoc << endl; + } + + cout << " Block size (bytes): " << g_ip->line_sz << endl; + cout << " Read/write Ports: " << g_ip->num_rw_ports << endl; + cout << " Read ports: " << g_ip->num_rd_ports << endl; + cout << " Write ports: " << g_ip->num_wr_ports << endl; + if (g_ip->fully_assoc || g_ip->pure_cam) + cout << " search ports: " << g_ip->num_search_ports << endl; + cout << " Technology size (nm): " << g_ip->F_sz_nm << endl << endl; + + cout << " Access time (ns): " << fr->access_time * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->access_time * 1e9 << " (@DVS_Level" << i + 1 + << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + + cout << " Cycle time (ns): " << fr->cycle_time * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->cycle_time * 1e9 << " (@DVS_Level" << i + 1 + << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + if (g_ip->data_arr_ram_cell_tech_type >= 4) { + cout << " Precharge Delay (ns): " + << fr->data_array2->precharge_delay * 1e9 << endl; + cout << " Activate Energy (nJ): " + << fr->data_array2->activate_energy * 1e9 << endl; + cout << " Read Energy (nJ): " << fr->data_array2->read_energy * 1e9 + << endl; + cout << " Write Energy (nJ): " << fr->data_array2->write_energy * 1e9 + << endl; + cout << " Precharge Energy (nJ): " + << fr->data_array2->precharge_energy * 1e9 << endl; + cout << " Leakage Power Closed Page (mW): " + << fr->data_array2->leak_power_subbank_closed_page * 1e3 << endl; + cout << " Leakage Power Open Page (mW): " + << fr->data_array2->leak_power_subbank_open_page * 1e3 << endl; + cout << " Leakage Power I/O (mW): " + << fr->data_array2->leak_power_request_and_reply_networks * 1e3 + << endl; + cout << " Refresh power (mW): " << fr->data_array2->refresh_power * 1e3 + << endl; + } + else { + if ((g_ip->fully_assoc || g_ip->pure_cam)) { + cout << " Total dynamic associative search energy per access (nJ): " + << fr->power.searchOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->power.searchOp.dynamic * 1e9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + // cout << " Total dynamic read energy per access + //(nJ): " << fr->power.readOp.dynamic*1e9 << endl; + // cout << " Total dynamic write energy per access + //(nJ): " << fr->power.writeOp.dynamic*1e9 << endl; + } + // else + // { + cout << " Total dynamic read energy per access (nJ): " + << fr->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->power.readOp.dynamic * 1e9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + cout << " Total dynamic write energy per access (nJ): " + << fr->power.writeOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->power.writeOp.dynamic * 1e9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + // } + if (g_ip->power_gating) { + cout << " Total leakage power of a bank, with power-gating "; + if (!g_ip->user_defined_vcc_underflow) { + cout << "(state retained)"; + } + else { + cout << "(non state retained)"; + } + + cout << ", including its network outside" // power gated with retaining + // memory content + " (mW): " + << (g_ip->long_channel_device + ? fr->power.readOp.power_gated_leakage * + long_channel_leakage_reduction + : fr->power.readOp.power_gated_leakage) * + 1e3 + << endl; + } + cout << " Total leakage power of a bank without power gating, including " + "its network outside" + " (mW): " + << (g_ip->long_channel_device + ? fr->power.readOp.leakage * long_channel_leakage_reduction + : fr->power.readOp.leakage) * + 1e3; + + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + if (g_ip->data_arr_ram_cell_tech_type == 3 || + g_ip->data_arr_ram_cell_tech_type == 4) { + } + cout << " Cache height x width (mm): " << fr->cache_ht * 1e-3 << " x " + << fr->cache_len * 1e-3 << endl; + cout << endl; + + if (g_ip->power_gating) { + /* Energy/Power stats */ + cout << " Power-gating results (The virtual power supply for gated " + "circuit can only retain the state of idle circuit, not for " + "operating the circuit):" + << endl; + /* Data array power-gating stats */ + if (g_ip->user_defined_vcc_underflow) { + cout << " Warning: user defined power gating voltage is too low to " + "retain state; Please understand the implications of deep sleep " + "state on non state retaining and cold start effects when waking " + "up the structure." + << endl; + } + else { + cout << " Power-gating results when retaining state" << endl; + } + areaoverhead = + (fr->cache_ht * fr->cache_len / fr->uca_pg_reference->cache_ht / + fr->uca_pg_reference->cache_len - + 1) * + 100; //% + cout << " \tPower gating circuits (sleep transistors) induced area " + "overhead: " + << areaoverhead << " % " << endl; + wakeup_E = wakeup_E_data = fr->data_array2->sram_sleep_wakeup_energy + + fr->data_array2->wl_sleep_wakeup_energy + + fr->data_array2->bl_floating_wakeup_energy; + wakeup_T = wakeup_T_data = + MAX(fr->data_array2->sram_sleep_wakeup_latency, + MAX(fr->data_array2->wl_sleep_wakeup_latency, + fr->data_array2->bl_floating_wakeup_latency)); + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + wakeup_E_tag = fr->tag_array2->sram_sleep_wakeup_energy + + fr->tag_array2->wl_sleep_wakeup_energy + + fr->tag_array2->bl_floating_wakeup_energy; + wakeup_T_tag = MAX(fr->tag_array2->sram_sleep_wakeup_latency, + MAX(fr->tag_array2->wl_sleep_wakeup_latency, + fr->tag_array2->bl_floating_wakeup_latency)); + + wakeup_E += wakeup_E_tag; + wakeup_T = MAX(wakeup_T_tag, wakeup_T_data); + } + cout << " \tPower gating Wakeup Latency (ns): " << wakeup_T * 1e9 + << endl; + cout << " \tPower gating Wakeup Energy (nJ): " << wakeup_E * 1e9 << endl; + } + cout << endl << endl; + cout << " Best Ndwl : " << fr->data_array2->Ndwl << endl; + cout << " Best Ndbl : " << fr->data_array2->Ndbl << endl; + cout << " Best Nspd : " << fr->data_array2->Nspd << endl; + cout << " Best Ndcm : " << fr->data_array2->deg_bl_muxing << endl; + cout << " Best Ndsam L1 : " << fr->data_array2->Ndsam_lev_1 << endl; + cout << " Best Ndsam L2 : " << fr->data_array2->Ndsam_lev_2 << endl + << endl; + + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << " Best Ntwl : " << fr->tag_array2->Ndwl << endl; + cout << " Best Ntbl : " << fr->tag_array2->Ndbl << endl; + cout << " Best Ntspd : " << fr->tag_array2->Nspd << endl; + cout << " Best Ntcm : " << fr->tag_array2->deg_bl_muxing << endl; + cout << " Best Ntsam L1 : " << fr->tag_array2->Ndsam_lev_1 << endl; + cout << " Best Ntsam L2 : " << fr->tag_array2->Ndsam_lev_2 << endl; + } + + switch (fr->data_array2->wt) { + case (0): + cout + << " Data array, H-tree wire type: Delay optimized global wires\n"; + break; + case (1): + cout << " Data array, H-tree wire type: Global wires with 5\% delay " + "penalty\n"; + break; + case (2): + cout << " Data array, H-tree wire type: Global wires with 10\% delay " + "penalty\n"; + break; + case (3): + cout << " Data array, H-tree wire type: Global wires with 20\% delay " + "penalty\n"; + break; + case (4): + cout << " Data array, H-tree wire type: Global wires with 30\% delay " + "penalty\n"; + break; + case (5): + cout << " Data array, wire type: Low swing wires\n"; + break; + default: + cout << "ERROR - Unknown wire type " << (int)fr->data_array2->wt << endl; + exit(0); + } + + if (!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) { + switch (fr->tag_array2->wt) { + case (0): + cout << " Tag array, H-tree wire type: Delay optimized global " + "wires\n"; + break; + case (1): + cout << " Tag array, H-tree wire type: Global wires with 5\% delay " + "penalty\n"; + break; + case (2): + cout << " Tag array, H-tree wire type: Global wires with 10\% delay " + "penalty\n"; + break; + case (3): + cout << " Tag array, H-tree wire type: Global wires with 20\% delay " + "penalty\n"; + break; + case (4): + cout << " Tag array, H-tree wire type: Global wires with 30\% delay " + "penalty\n"; + break; + case (5): + cout << " Tag array, wire type: Low swing wires\n"; + break; + default: + cout << "ERROR - Unknown wire type " << (int)fr->tag_array2->wt << endl; + exit(-1); + } + } + + if (g_ip->print_detail) { + // if(g_ip->fully_assoc) return; + if (0) { // detailed power-gating output + if (g_ip->power_gating) { + /* Energy/Power stats */ + cout << endl << endl << "Power-gating Components:" << endl << endl; + /* Data array power-gating stats */ + areaoverhead = fr->cache_ht * fr->cache_len / + fr->uca_pg_reference->cache_ht / + fr->uca_pg_reference->cache_len - + 1; + cout << " Power gating circuits (sleep transistors) induced area " + "overhead: " + << areaoverhead << " % " << endl; + wakeup_E = wakeup_E_data = fr->data_array2->sram_sleep_wakeup_energy + + fr->data_array2->wl_sleep_wakeup_energy + + fr->data_array2->bl_floating_wakeup_energy; + wakeup_T = wakeup_T_data = + MAX(fr->data_array2->sram_sleep_wakeup_latency, + MAX(fr->data_array2->wl_sleep_wakeup_latency, + fr->data_array2->bl_floating_wakeup_latency)); + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + wakeup_E_tag = fr->tag_array2->sram_sleep_wakeup_energy + + fr->tag_array2->wl_sleep_wakeup_energy + + fr->tag_array2->bl_floating_wakeup_energy; + wakeup_T_tag = MAX(fr->tag_array2->sram_sleep_wakeup_latency, + MAX(fr->tag_array2->wl_sleep_wakeup_latency, + fr->tag_array2->bl_floating_wakeup_latency)); + + wakeup_E += wakeup_E_tag; + wakeup_T = MAX(wakeup_T_tag, wakeup_T_data); + } + cout << " Power gating Wakeup Latency (ns): " << wakeup_T * 1e9 + << endl; + cout << " Power gating Wakeup Energy (nJ): " << wakeup_E * 1e9 + << endl; + + // extra power gating details + if (!(g_ip->pure_cam || g_ip->fully_assoc)) + cout << " Data array: " << endl; + else if (g_ip->pure_cam) + cout << " CAM array: " << endl; + else + cout << " Fully associative cache array: " << endl; + + cout << "\t Sub-array Sleep Tx size (um) - " + << fr->data_array2->sram_sleep_tx_width << endl; + + // cout << "\t Sub-array Sleep Tx total size (um) - " << + // fr->data_array2->sram_sleep_tx_width << endl; + + cout << "\t Sub-array Sleep Tx total area (mm^2) - " + << fr->data_array2->sram_sleep_tx_area * 1e-6 << endl; + + cout << "\t Sub-array wakeup time (ns) - " + << fr->data_array2->sram_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t Sub-array Tx energy (nJ) - " + << fr->data_array2->sram_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t WL Sleep Tx size (um) - " + << fr->data_array2->wl_sleep_tx_width << endl; + + // cout << "\t WL Sleep total Tx size (um) - " << + // fr->data_array2->wl_sleep_tx_width << endl; + + cout << "\t WL Sleep Tx total area (mm^2) - " + << fr->data_array2->wl_sleep_tx_area * 1e-6 << endl; + + cout << "\t WL wakeup time (ns) - " + << fr->data_array2->wl_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t WL Tx energy (nJ) - " + << fr->data_array2->wl_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t BL floating wakeup time (ns) - " + << fr->data_array2->bl_floating_wakeup_latency * 1e9 << endl; + + cout << "\t BL floating Tx energy (nJ) - " + << fr->data_array2->bl_floating_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + cout << endl; + + cout << "\t Active mats per access - " + << fr->data_array2->num_active_mats << endl; + cout << "\t Active subarrays per mat - " + << fr->data_array2->num_submarray_mats << endl; + cout << endl; + /* Tag array area stats */ + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << " Tag array: " << endl; + cout << "\t Sub-array Sleep Tx size (um) - " + << fr->tag_array2->sram_sleep_tx_width << endl; + + // cout << "\t Sub-array Sleep Tx total size (um) - " << + // fr->tag_array2->sram_sleep_tx_width << endl; + + cout << "\t Sub-array Sleep Tx total area (mm^2) - " + << fr->tag_array2->sram_sleep_tx_area * 1e-6 << endl; + + cout << "\t Sub-array wakeup time (ns) - " + << fr->tag_array2->sram_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t Sub-array Tx energy (nJ) - " + << fr->tag_array2->sram_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t WL Sleep Tx size (um) - " + << fr->tag_array2->wl_sleep_tx_width << endl; + + // cout << "\t WL Sleep total Tx size (um) - " << + // fr->tag_array2->wl_sleep_tx_width << endl; + + cout << "\t WL Sleep Tx total area (mm^2) - " + << fr->tag_array2->wl_sleep_tx_area * 1e-6 << endl; + + cout << "\t WL wakeup time (ns) - " + << fr->tag_array2->wl_sleep_wakeup_latency * 1e9 << endl; + + cout << "\t WL Tx energy (nJ) - " + << fr->tag_array2->wl_sleep_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + cout << "\t BL floating wakeup time (ns) - " + << fr->tag_array2->bl_floating_wakeup_latency * 1e9 << endl; + + cout << "\t BL floating Tx energy (nJ) - " + << fr->tag_array2->bl_floating_wakeup_energy * 1e9 << endl; + //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + cout << endl; + + cout << "\t Active mats per access - " + << fr->tag_array2->num_active_mats << endl; + cout << "\t Active subarrays per mat - " + << fr->tag_array2->num_submarray_mats << endl; + cout << endl; + } + } + } + /* Delay stats */ + /* data array stats */ + cout << endl << "Time Components:" << endl << endl; + + cout << " Data side (with Output driver) (ns): " + << fr->data_array2->access_time / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->access_time / 1e-9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + + cout << "\tH-tree delay outside banks (ns): " + << fr->data_array2->delay_route_to_bank * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_route_to_bank * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree input delay (inside a bank) (ns): " + << fr->data_array2->delay_input_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_input_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (!(g_ip->pure_cam || g_ip->fully_assoc)) { + cout << "\tDecoder + wordline delay (ns): " + << fr->data_array2->delay_row_predecode_driver_and_block * 1e9 + + fr->data_array2->delay_row_decoder * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2 + ->delay_row_predecode_driver_and_block * + 1e9 + + fr->uca_q[i]->data_array2->delay_row_decoder * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + else { + cout << "\tCAM search delay (ns): " + << fr->data_array2->delay_matchlines * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_matchlines * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + cout << "\tBitline delay (ns): " << fr->data_array2->delay_bitlines / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_bitlines / 1e-9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense Amplifier delay (ns): " + << fr->data_array2->delay_sense_amp * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_sense_amp * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree output delay (inside a bank) (ns): " + << fr->data_array2->delay_subarray_output_driver * 1e9 + + fr->data_array2->delay_dout_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->delay_subarray_output_driver * 1e9 + + fr->uca_q[i]->data_array2->delay_dout_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + if (g_ip->power_gating) { + cout << "\tPower gating wakeup time (ns) - " << wakeup_T_data * 1e9 + << endl; + } + + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + /* tag array stats */ + cout << endl + << " Tag side (with Output driver) (ns): " + << fr->tag_array2->access_time / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->access_time / 1e-9 << " (@DVS_Level" + << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] << "); "; + } + cout << endl; + cout << "\tH-tree delay outside banks (ns): " + << fr->tag_array2->delay_route_to_bank * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_route_to_bank * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree input delay (inside a bank) (ns): " + << fr->tag_array2->delay_input_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_input_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder + wordline delay (ns): " + << fr->tag_array2->delay_row_predecode_driver_and_block * 1e9 + + fr->tag_array2->delay_row_decoder * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2 + ->delay_row_predecode_driver_and_block * + 1e9 + + fr->uca_q[i]->tag_array2->delay_row_decoder * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline delay (ns): " << fr->tag_array2->delay_bitlines / 1e-9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_bitlines * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense Amplifier delay (ns): " + << fr->tag_array2->delay_sense_amp * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_sense_amp * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tComparator delay (ns): " + << fr->tag_array2->delay_comparator * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_comparator * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tH-tree output delay (inside a bank) (ns): " + << fr->tag_array2->delay_subarray_output_driver * 1e9 + + fr->tag_array2->delay_dout_htree * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->delay_subarray_output_driver * 1e9 + + fr->uca_q[i]->tag_array2->delay_dout_htree * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + if (g_ip->power_gating) { + cout << "\tPower gating wakeup time (ns) - " << wakeup_T_tag * 1e9 + << endl; + } + } + + /* Energy/Power stats */ + cout << endl << endl << "Power Components:" << endl << endl; + + if (!(g_ip->pure_cam || g_ip->fully_assoc)) { + cout << " Data array: Total dynamic read energy/access (nJ): " + << fr->data_array2->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power of a bank, power gated "; + + if (!g_ip->user_defined_vcc_underflow) { + cout << "with "; + } + else { + cout << "without "; + } + cout << "retaining memory content, including its network outside (mW): " + << (g_ip->long_channel_device + ? fr->data_array2->power.readOp.power_gated_leakage * + long_channel_leakage_reduction + : fr->data_array2->power.readOp.power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power of a bank without power gating, including " + "its network outside (mW): " + << (g_ip->long_channel_device + ? fr->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->data_array2->power.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->data_array2->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + // } + + cout << "\tTotal energy in H-tree outside banks (that includes both " + "address and data transfer) (nJ): " + << (fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tInput H-tree inside bank Energy (nJ): " + << (fr->data_array2->power_addr_input_htree.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_addr_input_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tOutput Htree inside bank Energy (nJ): " + << fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_data_output_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder (nJ): " + << fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2->power_row_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_row_predecoder_blocks.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tWordline (nJ): " + << fr->data_array2->power_row_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_row_decoders.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline mux & associated drivers (nJ): " + << fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << (fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_decoders.readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amp mux & associated drivers (nJ): " + << fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp + .dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_1_decoders + .readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_2_decoders + .readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines precharge and equalization circuit (nJ): " + << fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_prechg_eq_drivers.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines (nJ): " + << fr->data_array2->power_bitlines.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_bitlines.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->data_array2->power_sense_amps.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_sense_amps.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSub-array output driver (nJ): " + << fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_output_drivers_at_subarray.readOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power in H-tree outside a bank when power " + "gated (that includes both " + "address and data network) ((mW)): " + << (g_ip->long_channel_device + ? fr->data_array2->power_routing_to_bank.readOp + .power_gated_leakage * + long_channel_leakage_reduction + : fr->data_array2->power_routing_to_bank.readOp + .power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power in H-tree outside a bank (that includes " + "both " + "address and data network) ((mW)): " + << (g_ip->long_channel_device + ? fr->data_array2->power_routing_to_bank.readOp.leakage * + long_channel_leakage_reduction + : fr->data_array2->power_routing_to_bank.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp + .leakage * + long_channel_leakage_reduction + : fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp + .leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + // } + // cout << "\tTotal leakage power in H-tree (that includes both " + // "address and data network) ((mW)): " << + // (fr->data_array2->power_addr_input_htree.readOp.leakage + // + fr->data_array2->power_data_output_htree.readOp.leakage + // + fr->data_array2->power_routing_to_bank.readOp.leakage) + // * 1e3 << endl; + + // cout << "\tTotal leakage power in cells (mW): " << + // (fr->data_array2->array_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in row logic(mW): " << + // (fr->data_array2->wl_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in column logic(mW): " << + // (fr->data_array2->cl_leakage) * 1e3 << endl; + // + // cout << "\tTotal gate leakage power in H-tree (that includes + // both " "address and data network) ((mW)): " << + // (fr->data_array2->power_addr_input_htree.readOp.gate_leakage + // + + // fr->data_array2->power_data_output_htree.readOp.gate_leakage + // + + // fr->data_array2->power_routing_to_bank.readOp.gate_leakage) + // * 1e3 << endl; + } + + if (g_ip->pure_cam || g_ip->fully_assoc) { + if (g_ip->pure_cam) + cout << " CAM array:" << endl; + // cout << " Total dynamic associative search + // energy/access (nJ): " << + // fr->data_array2->power.searchOp.dynamic * 1e9 << + // endl; + // cout << "\tTotal energy in H-tree (that includes both " + // "match key and data transfer) (nJ): " << + // (fr->data_array2->power_htree_in_search.searchOp.dynamic + // + + // fr->data_array2->power_htree_out_search.searchOp.dynamic + // + + // fr->data_array2->power_routing_to_bank.searchOp.dynamic) + // * 1e9 << endl; cout << "\tKeyword input and result + // output Htrees inside bank Energy (nJ): " << + // (fr->data_array2->power_htree_in_search.searchOp.dynamic + // + + // fr->data_array2->power_htree_out_search.searchOp.dynamic) + // * 1e9 << endl; cout << "\tSearchlines (nJ): " << + // fr->data_array2->power_searchline.searchOp.dynamic + // * 1e9 + + // fr->data_array2->power_searchline_precharge.searchOp.dynamic + // * 1e9 << endl; cout << "\tMatchlines (nJ): " << + // fr->data_array2->power_matchlines.searchOp.dynamic + // * 1e9 + + // fr->data_array2->power_matchline_precharge.searchOp.dynamic + // * 1e9 << endl; cout << "\tSub-array output driver + // (nJ): " << + // fr->data_array2->power_output_drivers_at_subarray.searchOp.dynamic + // * 1e9 << endl; + // + // + // cout <data_array2->power.readOp.dynamic * + // 1e9 << endl; + // cout << "\tTotal energy in H-tree (that includes both " + // "address and data transfer) (nJ): " << + // (fr->data_array2->power_addr_input_htree.readOp.dynamic + // + + // fr->data_array2->power_data_output_htree.readOp.dynamic + // + + // fr->data_array2->power_routing_to_bank.readOp.dynamic) + // * 1e9 << endl; cout << "\tOutput Htree inside bank + // Energy (nJ): " << + // fr->data_array2->power_data_output_htree.readOp.dynamic + // * 1e9 << endl; cout << "\tDecoder (nJ): " << + // fr->data_array2->power_row_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_row_predecoder_blocks.readOp.dynamic + // * 1e9 << endl; cout << "\tWordline (nJ): " << + // fr->data_array2->power_row_decoders.readOp.dynamic + // * 1e9 << endl; cout << "\tBitline mux & associated + // drivers (nJ): " << + // fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_bit_mux_decoders.readOp.dynamic + // * 1e9 << endl; cout << "\tSense amp mux & associated + // drivers (nJ): " << + // fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic + // * 1e9 << endl; cout << "\tBitlines (nJ): " << + // fr->data_array2->power_bitlines.readOp.dynamic + // * 1e9 + + // fr->data_array2->power_prechg_eq_drivers.readOp.dynamic + // * 1e9<< endl; cout << "\tSense amplifier energy (nJ): + // " << + // fr->data_array2->power_sense_amps.readOp.dynamic + // * 1e9 << endl; cout << "\tSub-array output driver + // (nJ): " << + // fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic + // * 1e9 << endl; + // + // cout << endl <<" Total leakage power of a bank (mW): " + // << + // fr->data_array2->power.readOp.leakage * 1e3 << + // endl; + // } + // else + // { + if (g_ip->fully_assoc) + cout << " Fully associative array:" << endl; + + cout << " Total dynamic associative search energy/access (nJ): " + << fr->data_array2->power.searchOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power.searchOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tTotal energy in H-tree outside banks(that includes both " + "match key and data transfer) (nJ): " + << (fr->data_array2->power_routing_to_bank.searchOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_routing_to_bank.searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tMatch Key input Htrees inside bank Energy (nJ): " + << (fr->data_array2->power_htree_in_search.searchOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_htree_in_search.searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tResult output Htrees inside bank Energy (nJ): " + << (fr->data_array2->power_htree_out_search.searchOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_htree_out_search.searchOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSearchlines (nJ): " + << fr->data_array2->power_searchline.searchOp.dynamic * 1e9 + + fr->data_array2->power_searchline_precharge.searchOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_searchline.searchOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_searchline_precharge.searchOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tMatchlines (nJ): " + << fr->data_array2->power_matchlines.searchOp.dynamic * 1e9 + + fr->data_array2->power_matchline_precharge.searchOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_matchlines.searchOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_matchline_precharge.searchOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->fully_assoc) { + cout << "\tData portion wordline (nJ): " + << fr->data_array2->power_matchline_to_wordline_drv.searchOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_matchline_to_wordline_drv + .searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tData Bitlines (nJ): " + << fr->data_array2->power_bitlines.searchOp.dynamic * 1e9 + + fr->data_array2->power_prechg_eq_drivers.searchOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << (fr->uca_q[i]->data_array2->power_bitlines.searchOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_prechg_eq_drivers.searchOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->data_array2->power_sense_amps.searchOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_sense_amps.searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + cout << "\tSub-array output driver (nJ): " + << fr->data_array2->power_output_drivers_at_subarray.searchOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_output_drivers_at_subarray + .searchOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << endl + << " Total dynamic read energy/access (nJ): " + << fr->data_array2->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tTotal energy in H-tree outside banks(that includes both " + "address and data transfer) (nJ): " + << (fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_routing_to_bank.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tInput Htree inside bank Energy (nJ): " + << (fr->data_array2->power_addr_input_htree.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_addr_input_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tOutput Htree inside bank Energy (nJ): " + << fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << fr->uca_q[i] + ->data_array2->power_data_output_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder (nJ): " + << fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2->power_row_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_row_predecoder_blocks.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tWordline (nJ): " + << fr->data_array2->power_row_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_row_decoders.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline mux & associated drivers (nJ): " + << fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout + << (fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_bit_mux_decoders.readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amp mux & associated drivers (nJ): " + << fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp + .dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_1_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_1_decoders + .readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2 + ->power_senseamp_mux_lev_2_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_senseamp_mux_lev_2_decoders + .readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines (nJ): " + << fr->data_array2->power_bitlines.readOp.dynamic * 1e9 + + fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i]->data_array2->power_bitlines.readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->data_array2->power_prechg_eq_drivers.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->data_array2->power_sense_amps.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->data_array2->power_sense_amps.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSub-array output driver (nJ): " + << fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->data_array2->power_output_drivers_at_subarray.readOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << endl + << " Total leakage power of a bank, including its network outside " + "(mW): " + << (g_ip->long_channel_device + ? fr->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->data_array2->power.readOp.leakage) * + 1e3; // CAM/FA does not support PG yet + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->data_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->data_array2->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + } + + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << endl + << " Tag array: Total dynamic read energy/access (nJ): " + << fr->tag_array2->power.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power of a bank, power gated "; + if (!g_ip->user_defined_vcc_underflow) { + cout << "with "; + } + else { + cout << "without "; + } + cout << "retaining memory content, including its network outside (mW): " + << (g_ip->long_channel_device + ? fr->tag_array2->power.readOp.power_gated_leakage * + long_channel_leakage_reduction + : fr->tag_array2->power.readOp.power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power of a bank without power gating, including " + "its network outside (mW): " + << (g_ip->long_channel_device + ? fr->tag_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->tag_array2->power.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i]->tag_array2->power.readOp.leakage * + long_channel_leakage_reduction + : fr->uca_q[i]->tag_array2->power.readOp.leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + // } + // cout << "\tTotal leakage read/write power of a bank (mW): " << + // fr->tag_array2->power.readOp.leakage * 1e3 << endl; + cout << "\tTotal energy in H-tree outside banks (that includes both " + "address and data transfer) (nJ): " + << (fr->tag_array2->power_routing_to_bank.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_routing_to_bank.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tInput H-tree inside banks Energy (nJ): " + << (fr->tag_array2->power_addr_input_htree.readOp.dynamic) * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_addr_input_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tOutput Htree inside a bank Energy (nJ): " + << fr->tag_array2->power_data_output_htree.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_data_output_htree.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tDecoder (nJ): " + << fr->tag_array2->power_row_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->tag_array2->power_row_predecoder_blocks.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->tag_array2->power_row_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_row_predecoder_blocks.readOp + .dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tWordline (nJ): " + << fr->tag_array2->power_row_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power_row_decoders.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitline mux & associated drivers (nJ): " + << fr->tag_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * + 1e9 + + fr->tag_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->tag_array2->power_bit_mux_decoders.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->tag_array2->power_bit_mux_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_bit_mux_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_bit_mux_decoders.readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amp mux & associated drivers (nJ): " + << fr->tag_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_1_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_1_decoders.readOp + .dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_2_predecoder_drivers + .readOp.dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_2_predecoder_blocks + .readOp.dynamic * + 1e9 + + fr->tag_array2->power_senseamp_mux_lev_2_decoders.readOp + .dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_1_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_1_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_senseamp_mux_lev_1_decoders + .readOp.dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_2_predecoder_drivers.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2 + ->power_senseamp_mux_lev_2_predecoder_blocks.readOp + .dynamic * + 1e9 + + fr->uca_q[i] + ->tag_array2->power_senseamp_mux_lev_2_decoders + .readOp.dynamic * + 1e9) + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tBitlines precharge and equalization circuit (nJ): " + << fr->tag_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_prechg_eq_drivers.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + cout << "\tBitlines (nJ): " + << fr->tag_array2->power_bitlines.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power_bitlines.readOp.dynamic * 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSense amplifier energy (nJ): " + << fr->tag_array2->power_sense_amps.readOp.dynamic * 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i]->tag_array2->power_sense_amps.readOp.dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + cout << "\tSub-array output driver (nJ): " + << fr->tag_array2->power_output_drivers_at_subarray.readOp.dynamic * + 1e9; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << fr->uca_q[i] + ->tag_array2->power_output_drivers_at_subarray.readOp + .dynamic * + 1e9 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + + if (g_ip->power_gating) { + cout << "\tTotal leakage power in H-tree outside a bank when power " + "gated (that includes both " + "address and data network) ((mW)): " + << (g_ip->long_channel_device + ? fr->tag_array2->power_routing_to_bank.readOp + .power_gated_leakage * + long_channel_leakage_reduction + : fr->tag_array2->power_routing_to_bank.readOp + .power_gated_leakage) * + 1e3 + << endl; + } + // else + // { + cout << "\tTotal leakage power in H-tree outside a bank (that includes " + "both " + "address and data network) without power gating((mW)): " + << (g_ip->long_channel_device + ? fr->tag_array2->power_routing_to_bank.readOp.leakage * + long_channel_leakage_reduction + : fr->tag_array2->power_routing_to_bank.readOp.leakage) * + 1e3; + if (dvs) { + cout << " (@DVS_Level0); "; + for (i = 0; i < dvs_levels; i++) + cout << (g_ip->long_channel_device + ? fr->uca_q[i] + ->tag_array2->power_routing_to_bank.readOp + .leakage * + long_channel_leakage_reduction + : fr->uca_q[i] + ->tag_array2->power_routing_to_bank.readOp + .leakage) * + 1e3 + << " (@DVS_Level" << i + 1 << "_Vdd=" << g_ip->dvs_voltage[i] + << "); "; + } + cout << endl; + // } + + // cout << "\tTotal leakage power of a bank (mW): " << + // fr->tag_array2->power.readOp.leakage * 1e3 << endl; + // cout << "\tTotal leakage power in H-tree (that includes both " + // "address and data network) ((mW)): " << + // (fr->tag_array2->power_addr_input_htree.readOp.leakage + + // fr->tag_array2->power_data_output_htree.readOp.leakage + // + fr->tag_array2->power_routing_to_bank.readOp.leakage) * + // 1e3 << endl; + // + // cout << "\tTotal leakage power in cells (mW): " << + // (fr->tag_array2->array_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in row logic(mW): " << + // (fr->tag_array2->wl_leakage) * 1e3 << endl; + // cout << "\tTotal leakage power in column logic(mW): " << + // (fr->tag_array2->cl_leakage) * 1e3 << endl; + // cout << "\tTotal gate leakage power in H-tree (that includes + // both " "address and data network) ((mW)): " << + // (fr->tag_array2->power_addr_input_htree.readOp.gate_leakage + // + + // fr->tag_array2->power_data_output_htree.readOp.gate_leakage + // + + // fr->tag_array2->power_routing_to_bank.readOp.gate_leakage) + // * 1e3 << endl; + } + + cout << endl << endl << "Area Components:" << endl << endl; + /* Data array area stats */ + if (!(g_ip->pure_cam || g_ip->fully_assoc)) + cout << " Data array: Area (mm2): " << fr->data_array2->area * 1e-6 + << endl; + else if (g_ip->pure_cam) + cout << " CAM array: Area (mm2): " << fr->data_array2->area * 1e-6 + << endl; + else + cout << " Fully associative cache array: Area (mm2): " + << fr->data_array2->area * 1e-6 << endl; + + cout << "\tHeight (mm): " << fr->data_array2->all_banks_height * 1e-3 + << endl; + cout << "\tWidth (mm): " << fr->data_array2->all_banks_width * 1e-3 << endl; + if (g_ip->print_detail) { + cout << "\tArea efficiency (Memory cell area/Total area) - " + << fr->data_array2->area_efficiency << " %" << endl; + cout << "\t\tMAT Height (mm): " << fr->data_array2->mat_height * 1e-3 + << endl; + cout << "\t\tMAT Length (mm): " << fr->data_array2->mat_length * 1e-3 + << endl; + cout << "\t\tSubarray Height (mm): " + << fr->data_array2->subarray_height * 1e-3 << endl; + cout << "\t\tSubarray Length (mm): " + << fr->data_array2->subarray_length * 1e-3 << endl; + if (g_ip->power_gating) { + overhead_data = + (fr->data_array2->area / fr->uca_pg_reference->data_array2->area - + 1) * + 100; //%; + cout << " Power gating circuits (sleep transistors) induced area " + "overhead: " + << overhead_data << "%" << endl; + } + } + + /* Tag array area stats */ + if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && + !g_ip->is_main_mem) { + cout << endl + << " Tag array: Area (mm2): " << fr->tag_array2->area * 1e-6 + << endl; + cout << "\tHeight (mm): " << fr->tag_array2->all_banks_height * 1e-3 + << endl; + cout << "\tWidth (mm): " << fr->tag_array2->all_banks_width * 1e-3 + << endl; + + if (g_ip->print_detail) { + cout << "\tArea efficiency (Memory cell area/Total area) - " + << fr->tag_array2->area_efficiency << " %" << endl; + cout << "\t\tMAT Height (mm): " << fr->tag_array2->mat_height * 1e-3 + << endl; + cout << "\t\tMAT Length (mm): " << fr->tag_array2->mat_length * 1e-3 + << endl; + cout << "\t\tSubarray Height (mm): " + << fr->tag_array2->subarray_height * 1e-3 << endl; + cout << "\t\tSubarray Length (mm): " + << fr->tag_array2->subarray_length * 1e-3 << endl; + } + + if (g_ip->power_gating) { + overhead_tag = + (fr->tag_array2->area / fr->uca_pg_reference->tag_array2->area - + 1) * + 100; //%; + cout << " Power gating circuits (sleep transistors) induced area " + "overhead: " + << overhead_tag << "%" << endl + << endl; + } + } + + // Wire wpr; //TODO: this must change, since this changes the wire value + // during dvs loop. Wire::print_wire();//move outside output UCA + + // cout << "FO4 = " << g_tp.FO4 << endl; + } +} + +// McPAT's plain interface, please keep !!! +uca_org_t cacti_interface(InputParameter *const local_interface) { + // g_ip = new InputParameter(); + // g_ip->add_ecc_b_ = true; + + uca_org_t fin_res; + fin_res.valid = false; + + g_ip = local_interface; + + // g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + // g_ip->data_arr_peri_global_tech_type = + // data_arr_peri_global_tech_flavor_in; g_ip->tag_arr_ram_cell_tech_type + // = tag_arr_ram_cell_tech_flavor_in; g_ip->tag_arr_peri_global_tech_type = + // tag_arr_peri_global_tech_flavor_in; + // + // g_ip->ic_proj_type = interconnect_projection_type_in; + // g_ip->wire_is_mat_type = wire_inside_mat_type_in; + // g_ip->wire_os_mat_type = wire_outside_mat_type_in; + // g_ip->burst_len = BURST_LENGTH_in; + // g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; + // g_ip->page_sz_bits = PAGE_SIZE_BITS_in; + // + // g_ip->cache_sz = cache_size; + // g_ip->line_sz = line_size; + // g_ip->assoc = associativity; + // g_ip->nbanks = banks; + // g_ip->out_w = output_width; + // g_ip->specific_tag = specific_tag; + // if (tag_width == 0) { + // g_ip->tag_w = 42; + // } + // else { + // g_ip->tag_w = tag_width; + // } + // + // g_ip->access_mode = access_mode; + // g_ip->delay_wt = obj_func_delay; + // g_ip->dynamic_power_wt = obj_func_dynamic_power; + // g_ip->leakage_power_wt = obj_func_leakage_power; + // g_ip->area_wt = obj_func_area; + // g_ip->cycle_time_wt = obj_func_cycle_time; + // g_ip->delay_dev = dev_func_delay; + // g_ip->dynamic_power_dev = dev_func_dynamic_power; + // g_ip->leakage_power_dev = dev_func_leakage_power; + // g_ip->area_dev = dev_func_area; + // g_ip->cycle_time_dev = dev_func_cycle_time; + // g_ip->temp = temp; + // + // g_ip->F_sz_nm = tech_node; + // g_ip->F_sz_um = tech_node / 1000; + // g_ip->is_main_mem = (main_mem != 0) ? true : false; + // g_ip->is_cache = (cache ==1) ? true : false; + // g_ip->pure_ram = (cache ==0) ? true : false; + // g_ip->pure_cam = (cache ==2) ? true : false; + // g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : + // false; g_ip->ver_htree_wires_over_array = + // VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; + // g_ip->broadcast_addr_din_over_ver_htrees = + // BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; + // + // g_ip->num_rw_ports = rw_ports; + // g_ip->num_rd_ports = excl_read_ports; + // g_ip->num_wr_ports = excl_write_ports; + // g_ip->num_se_rd_ports = single_ended_read_ports; + // g_ip->num_search_ports = search_ports; + // + // g_ip->print_detail = 1; + // g_ip->nuca = 0; + // g_ip->is_cache=true; + // + // if (force_wiretype == 0) + // { + // g_ip->wt = Global; + // g_ip->force_wiretype = false; + // } + // else + // { g_ip->force_wiretype = true; + // if (wiretype==10) { + // g_ip->wt = Global_10; + // } + // if (wiretype==20) { + // g_ip->wt = Global_20; + // } + // if (wiretype==30) { + // g_ip->wt = Global_30; + // } + // if (wiretype==5) { + // g_ip->wt = Global_5; + // } + // if (wiretype==0) { + // g_ip->wt = Low_swing; + // } + // } + // //g_ip->wt = Global_5; + // if (force_config == 0) + // { + // g_ip->force_cache_config = false; + // } + // else + // { + // g_ip->force_cache_config = true; + // g_ip->ndbl=ndbl; + // g_ip->ndwl=ndwl; + // g_ip->nspd=nspd; + // g_ip->ndcm=ndcm; + // g_ip->ndsam1=ndsam1; + // g_ip->ndsam2=ndsam2; + // + // + // } + // + // if (ecc==0){ + // g_ip->add_ecc_b_=false; + // } + // else + // { + // g_ip->add_ecc_b_=true; + // } + + if (!g_ip->error_checking()) + exit(0); + + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + + solve(&fin_res); + + if (!g_ip->dvs_voltage.empty()) { + update_dvs(&fin_res); + } + if (g_ip->power_gating) { + update_pg(&fin_res); // this is needed for compute area overhead of + // power-gating, even the gated power is calculated + // together un-gated leakage + } + + // g_ip->display_ip(); + // output_UCA(&fin_res); + // output_data_csv(fin_res); + // Wire wprint;//reset wires to original configuration as in *.cfg file (dvs + // level 0) Wire::print_wire(); + // delete (g_ip); + + return fin_res; +} + +// McPAT's plain interface, please keep !!! +uca_org_t init_interface(InputParameter *const local_interface) { + // g_ip = new InputParameter(); + // g_ip->add_ecc_b_ = true; + + uca_org_t fin_res; + fin_res.valid = false; + + g_ip = local_interface; + + // g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; + // g_ip->data_arr_peri_global_tech_type = + // data_arr_peri_global_tech_flavor_in; g_ip->tag_arr_ram_cell_tech_type + // = tag_arr_ram_cell_tech_flavor_in; g_ip->tag_arr_peri_global_tech_type = + // tag_arr_peri_global_tech_flavor_in; + // + // g_ip->ic_proj_type = interconnect_projection_type_in; + // g_ip->wire_is_mat_type = wire_inside_mat_type_in; + // g_ip->wire_os_mat_type = wire_outside_mat_type_in; + // g_ip->burst_len = BURST_LENGTH_in; + // g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; + // g_ip->page_sz_bits = PAGE_SIZE_BITS_in; + // + // g_ip->cache_sz = cache_size; + // g_ip->line_sz = line_size; + // g_ip->assoc = associativity; + // g_ip->nbanks = banks; + // g_ip->out_w = output_width; + // g_ip->specific_tag = specific_tag; + // if (tag_width == 0) { + // g_ip->tag_w = 42; + // } + // else { + // g_ip->tag_w = tag_width; + // } + // + // g_ip->access_mode = access_mode; + // g_ip->delay_wt = obj_func_delay; + // g_ip->dynamic_power_wt = obj_func_dynamic_power; + // g_ip->leakage_power_wt = obj_func_leakage_power; + // g_ip->area_wt = obj_func_area; + // g_ip->cycle_time_wt = obj_func_cycle_time; + // g_ip->delay_dev = dev_func_delay; + // g_ip->dynamic_power_dev = dev_func_dynamic_power; + // g_ip->leakage_power_dev = dev_func_leakage_power; + // g_ip->area_dev = dev_func_area; + // g_ip->cycle_time_dev = dev_func_cycle_time; + // g_ip->temp = temp; + // + // g_ip->F_sz_nm = tech_node; + // g_ip->F_sz_um = tech_node / 1000; + // g_ip->is_main_mem = (main_mem != 0) ? true : false; + // g_ip->is_cache = (cache ==1) ? true : false; + // g_ip->pure_ram = (cache ==0) ? true : false; + // g_ip->pure_cam = (cache ==2) ? true : false; + // g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : + // false; g_ip->ver_htree_wires_over_array = + // VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; + // g_ip->broadcast_addr_din_over_ver_htrees = + // BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; + // + // g_ip->num_rw_ports = rw_ports; + // g_ip->num_rd_ports = excl_read_ports; + // g_ip->num_wr_ports = excl_write_ports; + // g_ip->num_se_rd_ports = single_ended_read_ports; + // g_ip->num_search_ports = search_ports; + // + // g_ip->print_detail = 1; + // g_ip->nuca = 0; + // + // if (force_wiretype == 0) + // { + // g_ip->wt = Global; + // g_ip->force_wiretype = false; + // } + // else + // { g_ip->force_wiretype = true; + // if (wiretype==10) { + // g_ip->wt = Global_10; + // } + // if (wiretype==20) { + // g_ip->wt = Global_20; + // } + // if (wiretype==30) { + // g_ip->wt = Global_30; + // } + // if (wiretype==5) { + // g_ip->wt = Global_5; + // } + // if (wiretype==0) { + // g_ip->wt = Low_swing; + // } + // } + // //g_ip->wt = Global_5; + // if (force_config == 0) + // { + // g_ip->force_cache_config = false; + // } + // else + // { + // g_ip->force_cache_config = true; + // g_ip->ndbl=ndbl; + // g_ip->ndwl=ndwl; + // g_ip->nspd=nspd; + // g_ip->ndcm=ndcm; + // g_ip->ndsam1=ndsam1; + // g_ip->ndsam2=ndsam2; + // + // + // } + // + // if (ecc==0){ + // g_ip->add_ecc_b_=false; + // } + // else + // { + // g_ip->add_ecc_b_=true; + // } + + g_ip->error_checking(); + + init_tech_params(g_ip->F_sz_um, false); + Wire winit; // Do not delete this line. It initializes wires. + // solve(&fin_res); + // g_ip->display_ip(); + + // solve(&fin_res); + // output_UCA(&fin_res); + // output_data_csv(fin_res); + // delete (g_ip); + + return fin_res; +} + +void reconfigure(InputParameter *local_interface, uca_org_t *fin_res) { + // Copy the InputParameter to global interface (g_ip) and do error checking. + g_ip = local_interface; + g_ip->error_checking(); + + // Initialize technology parameters + init_tech_params(g_ip->F_sz_um, false); + + Wire winit; // Do not delete this line. It initializes wires. + + // This corresponds to solve() in the initialization process. + update_dvs(fin_res); +} + +} // namespace cacti diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/io.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/io.h new file mode 100644 index 0000000000..601e92d99a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/io.h @@ -0,0 +1,45 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __IO_H__ +#define __IO_H__ + +#include "cacti_interface.h" +#include "const.h" + +namespace cacti { + +void output_data_csv(const cacti::uca_org_t &fin_res); +void output_UCA(cacti::uca_org_t *fin_res); + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/main.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/main.cc new file mode 100644 index 0000000000..8a9ed400e3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/main.cc @@ -0,0 +1,115 @@ +/*------------------------------------------------------------ + * CACTI 6.5 + * Copyright 2008 Hewlett-Packard Development Corporation + * All Rights Reserved + * + * Permission to use, copy, and modify this software and its documentation is + * hereby granted only under the following terms and conditions. Both the + * above copyright notice and this permission notice must appear in all copies + * of the software, derivative works or modified versions, and any portions + * thereof, and both notices must appear in supporting documentation. + * + * Users of this software agree to the terms and conditions set forth herein, + *and hereby grant back to Hewlett-Packard Company and its affiliated companies + *("HP") a non-exclusive, unrestricted, royalty-free right and license under + *any changes, enhancements or extensions made to the core functions of the + *software, including but not limited to those affording compatibility with + *other hardware or software environments, but excluding applications which + *incorporate this software. Users further agree to use their best efforts to + *return to HP any such changes, enhancements or extensions that they make and + *inform HP of noteworthy uses of this software. Correspondence should be + *provided to HP at: + * + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * This software may be distributed (but not offered for sale or transferred + * for compensation) to third parties, provided such third parties agree to + * abide by the terms and conditions of this notice. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL HP + * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS + * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + *------------------------------------------------------------*/ + +#include +#include "io.h" + +using namespace std; +using namespace cacti; + +int main(int argc, char *argv[]) { + uca_org_t result; + if (argc != 53 && argc != 55) { + bool infile_specified = false; + string infile_name(""); + + for (int32_t i = 0; i < argc; i++) { + if (argv[i] == string("-infile")) { + infile_specified = true; + i++; + infile_name = argv[i]; + } + } + + if (infile_specified == false) { + cerr << " Invalid arguments -- how to use CACTI:" << endl; + cerr << " 1) cacti -infile " << endl; + cerr << " 2) cacti arg1 ... arg52 -- please refer to the README file" + << endl; + cerr << " No. of arguments input - " << argc << endl; + exit(1); + } + else { + result = cacti_interface(infile_name); + } + } + else if (argc == 53) { + result = cacti_interface( + atoi(argv[1]), atoi(argv[2]), atoi(argv[3]), atoi(argv[4]), + atoi(argv[5]), atoi(argv[6]), atoi(argv[7]), atoi(argv[8]), + atoi(argv[9]), atof(argv[10]), atoi(argv[11]), atoi(argv[12]), + atoi(argv[13]), atoi(argv[14]), atoi(argv[15]), atoi(argv[16]), + atoi(argv[17]), atoi(argv[18]), atoi(argv[19]), atoi(argv[20]), + atoi(argv[21]), atoi(argv[22]), atoi(argv[23]), atoi(argv[24]), + atoi(argv[25]), atoi(argv[26]), atoi(argv[27]), atoi(argv[28]), + atoi(argv[29]), atoi(argv[30]), atoi(argv[31]), atoi(argv[32]), + atoi(argv[33]), atoi(argv[34]), atoi(argv[35]), atoi(argv[36]), + atoi(argv[37]), atoi(argv[38]), atoi(argv[39]), atoi(argv[40]), + atoi(argv[41]), atoi(argv[42]), atoi(argv[43]), atoi(argv[44]), + atoi(argv[45]), atoi(argv[46]), atoi(argv[47]), atoi(argv[48]), + atoi(argv[49]), atoi(argv[50]), atoi(argv[51]), atoi(argv[52])); + } + else { + result = cacti_interface( + atoi(argv[1]), atoi(argv[2]), atoi(argv[3]), atoi(argv[4]), + atoi(argv[5]), atoi(argv[6]), atoi(argv[7]), atoi(argv[8]), + atof(argv[9]), atoi(argv[10]), atoi(argv[11]), atoi(argv[12]), + atoi(argv[13]), atoi(argv[14]), atoi(argv[15]), atoi(argv[16]), + atoi(argv[17]), atoi(argv[18]), atoi(argv[19]), atoi(argv[20]), + atoi(argv[21]), atoi(argv[22]), atoi(argv[23]), atoi(argv[24]), + atoi(argv[25]), atoi(argv[26]), atoi(argv[27]), atoi(argv[28]), + atoi(argv[29]), atoi(argv[30]), atoi(argv[31]), atoi(argv[32]), + atoi(argv[33]), atoi(argv[34]), atoi(argv[35]), atoi(argv[36]), + atoi(argv[37]), atoi(argv[38]), atoi(argv[39]), atoi(argv[40]), + atoi(argv[41]), atoi(argv[42]), atoi(argv[43]), atoi(argv[44]), + atoi(argv[45]), atoi(argv[46]), atoi(argv[47]), atoi(argv[48]), + atoi(argv[49]), atoi(argv[50]), atoi(argv[51]), atoi(argv[52]), + atoi(argv[53]), atoi(argv[54])); + } + + result.cleanup(); + // delete result.data_array2; + // if (result.tag_array2!=NULL) + // delete result.tag_array2; + + return 0; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/mat.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/mat.cc new file mode 100644 index 0000000000..48eae4d292 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/mat.cc @@ -0,0 +1,2427 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "mat.h" +#include +using namespace cacti; + +Mat::Mat(const DynamicParameter &dyn_p) + : dp(dyn_p), + power_subarray_out_drv(), + delay_fa_tag(0), + delay_cam(0), + delay_before_decoder(0), + delay_bitline(0), + delay_wl_reset(0), + delay_bl_restore(0), + delay_searchline(0), + delay_matchchline(0), + delay_cam_sl_restore(0), + delay_cam_ml_reset(0), + delay_fa_ram_wl(0), + delay_hit_miss_reset(0), + delay_hit_miss(0), + subarray(dp, dp.fully_assoc), + power_bitline(), + per_bitline_read_energy(0), + deg_bl_muxing(dp.deg_bl_muxing), + num_act_mats_hor_dir(dyn_p.num_act_mats_hor_dir), + delay_writeback(0), + cell(subarray.cell), + cam_cell(subarray.cam_cell), + is_dram(dyn_p.is_dram), + pure_cam(dyn_p.pure_cam), + num_mats(dp.num_mats), + power_sa(), + delay_sa(0), + leak_power_sense_amps_closed_page_state(0), + leak_power_sense_amps_open_page_state(0), + delay_subarray_out_drv(0), + delay_comparator(0), + power_comparator(), + num_do_b_mat(dyn_p.num_do_b_mat), + num_so_b_mat(dyn_p.num_so_b_mat), + num_subarrays_per_mat(dp.num_subarrays / dp.num_mats), + num_subarrays_per_row(dp.Ndwl / dp.num_mats_h_dir), + array_leakage(0), + wl_leakage(0), + cl_leakage(0), + sram_sleep_tx(0) { + assert(num_subarrays_per_mat <= 4); + assert(num_subarrays_per_row <= 2); + is_fa = (dp.fully_assoc) ? true : false; + camFlag = (is_fa || pure_cam); // although cam_cell.w = cell.w for fa, we + // still differentiate them. + + if (is_fa || pure_cam) + num_subarrays_per_row = num_subarrays_per_mat > 2 + ? num_subarrays_per_mat / 2 + : num_subarrays_per_mat; + + if (dp.use_inp_params == 1) { + RWP = dp.num_rw_ports; + ERP = dp.num_rd_ports; + EWP = dp.num_wr_ports; + SCHP = dp.num_search_ports; + } + else { + RWP = g_ip->num_rw_ports; + ERP = g_ip->num_rd_ports; + EWP = g_ip->num_wr_ports; + SCHP = g_ip->num_search_ports; + } + + double number_sa_subarray; + + if (!is_fa && !pure_cam) { + number_sa_subarray = subarray.num_cols / deg_bl_muxing; + } + else if (is_fa && !pure_cam) { + number_sa_subarray = + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram) / deg_bl_muxing; + } + + else { + number_sa_subarray = (subarray.num_cols_fa_cam) / deg_bl_muxing; + } + + int num_dec_signals = subarray.num_rows; + double C_ld_bit_mux_dec_out = 0; + double C_ld_sa_mux_lev_1_dec_out = 0; + double C_ld_sa_mux_lev_2_dec_out = 0; + double R_wire_wl_drv_out; + + if (!is_fa && !pure_cam) { + R_wire_wl_drv_out = subarray.num_cols * cell.w * g_tp.wire_local.R_per_um; + } + else if (is_fa && !pure_cam) { + R_wire_wl_drv_out = (subarray.num_cols_fa_cam * cam_cell.w + + subarray.num_cols_fa_ram * cell.w) * + g_tp.wire_local.R_per_um; + } + else { + R_wire_wl_drv_out = + (subarray.num_cols_fa_cam * cam_cell.w) * g_tp.wire_local.R_per_um; + } + + double R_wire_bit_mux_dec_out = num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.R_per_um * + cell.w; // TODO:revisit for FA + double R_wire_sa_mux_dec_out = num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.R_per_um * cell.w; + + if (deg_bl_muxing > 1) { + C_ld_bit_mux_dec_out = + (2 * num_subarrays_per_mat * subarray.num_cols / deg_bl_muxing) * + gate_C(g_tp.w_nmos_b_mux, 0, is_dram) + // 2 transistor per cell + num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.C_per_um * cell.get_w(); + } + + if (dp.Ndsam_lev_1 > 1) { + C_ld_sa_mux_lev_1_dec_out = + (num_subarrays_per_mat * number_sa_subarray / dp.Ndsam_lev_1) * + gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) + + num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.C_per_um * cell.get_w(); + } + if (dp.Ndsam_lev_2 > 1) { + C_ld_sa_mux_lev_2_dec_out = (num_subarrays_per_mat * number_sa_subarray / + (dp.Ndsam_lev_1 * dp.Ndsam_lev_2)) * + gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) + + num_subarrays_per_row * subarray.num_cols * + g_tp.wire_inside_mat.C_per_um * + cell.get_w(); + } + + if (num_subarrays_per_row >= 2) { + // wire heads for both right and left side of a mat, so half the resistance + R_wire_bit_mux_dec_out /= 2.0; + R_wire_sa_mux_dec_out /= 2.0; + } + + row_dec = + new Decoder(num_dec_signals, false, subarray.C_wl, R_wire_wl_drv_out, + false /*is_fa*/, is_dram, true, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false, subarray.num_rows); + + // row_dec->nodes_DSTN = subarray.num_rows;//TODO: this is not a good way for + // OOO programming if (is_fa && (!dp.is_tag)) + // { + // row_dec->exist = true; + // } + bit_mux_dec = + new Decoder(deg_bl_muxing, // This number is 1 for FA or CAM + false, C_ld_bit_mux_dec_out, R_wire_bit_mux_dec_out, + false /*is_fa*/, is_dram, false, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false); + sa_mux_lev_1_dec = + new Decoder(dp.deg_senseamp_muxing_non_associativity, // This number is 1 + // for FA or CAM + dp.number_way_select_signals_mat + ? true + : false, // only sa_mux_lev_1_dec needs way select signal + C_ld_sa_mux_lev_1_dec_out, R_wire_sa_mux_dec_out, + false /*is_fa*/, is_dram, false, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false); + sa_mux_lev_2_dec = + new Decoder(dp.Ndsam_lev_2, // This number is 1 for FA or CAM + false, C_ld_sa_mux_lev_2_dec_out, R_wire_sa_mux_dec_out, + false /*is_fa*/, is_dram, false, camFlag ? cam_cell : cell, + g_ip->power_gating ? true : false); + + double C_wire_predec_blk_out; + double R_wire_predec_blk_out; + + if (!is_fa && !pure_cam) { + C_wire_predec_blk_out = num_subarrays_per_row * subarray.num_rows * + g_tp.wire_inside_mat.C_per_um * cell.h; + R_wire_predec_blk_out = num_subarrays_per_row * subarray.num_rows * + g_tp.wire_inside_mat.R_per_um * cell.h; + } + else // for pre-decode block's load is same for both FA and CAM + { + C_wire_predec_blk_out = + subarray.num_rows * g_tp.wire_inside_mat.C_per_um * cam_cell.h; + R_wire_predec_blk_out = + subarray.num_rows * g_tp.wire_inside_mat.R_per_um * cam_cell.h; + } + + if (is_fa || pure_cam) + num_dec_signals += _log2(num_subarrays_per_mat); + + PredecBlk *r_predec_blk1 = new PredecBlk( + num_dec_signals, row_dec, C_wire_predec_blk_out, R_wire_predec_blk_out, + num_subarrays_per_mat, is_dram, true); + PredecBlk *r_predec_blk2 = new PredecBlk( + num_dec_signals, row_dec, C_wire_predec_blk_out, R_wire_predec_blk_out, + num_subarrays_per_mat, is_dram, false); + PredecBlk *b_mux_predec_blk1 = + new PredecBlk(deg_bl_muxing, bit_mux_dec, 0, 0, 1, is_dram, true); + PredecBlk *b_mux_predec_blk2 = + new PredecBlk(deg_bl_muxing, bit_mux_dec, 0, 0, 1, is_dram, false); + PredecBlk *sa_mux_lev_1_predec_blk1 = + new PredecBlk(dyn_p.deg_senseamp_muxing_non_associativity, + sa_mux_lev_1_dec, 0, 0, 1, is_dram, true); + PredecBlk *sa_mux_lev_1_predec_blk2 = + new PredecBlk(dyn_p.deg_senseamp_muxing_non_associativity, + sa_mux_lev_1_dec, 0, 0, 1, is_dram, false); + PredecBlk *sa_mux_lev_2_predec_blk1 = + new PredecBlk(dp.Ndsam_lev_2, sa_mux_lev_2_dec, 0, 0, 1, is_dram, true); + PredecBlk *sa_mux_lev_2_predec_blk2 = + new PredecBlk(dp.Ndsam_lev_2, sa_mux_lev_2_dec, 0, 0, 1, is_dram, false); + dummy_way_sel_predec_blk1 = + new PredecBlk(1, sa_mux_lev_1_dec, 0, 0, 0, is_dram, true); + dummy_way_sel_predec_blk2 = + new PredecBlk(1, sa_mux_lev_1_dec, 0, 0, 0, is_dram, false); + + PredecBlkDrv *r_predec_blk_drv1 = new PredecBlkDrv(0, r_predec_blk1, is_dram); + PredecBlkDrv *r_predec_blk_drv2 = new PredecBlkDrv(0, r_predec_blk2, is_dram); + PredecBlkDrv *b_mux_predec_blk_drv1 = + new PredecBlkDrv(0, b_mux_predec_blk1, is_dram); + PredecBlkDrv *b_mux_predec_blk_drv2 = + new PredecBlkDrv(0, b_mux_predec_blk2, is_dram); + PredecBlkDrv *sa_mux_lev_1_predec_blk_drv1 = + new PredecBlkDrv(0, sa_mux_lev_1_predec_blk1, is_dram); + PredecBlkDrv *sa_mux_lev_1_predec_blk_drv2 = + new PredecBlkDrv(0, sa_mux_lev_1_predec_blk2, is_dram); + PredecBlkDrv *sa_mux_lev_2_predec_blk_drv1 = + new PredecBlkDrv(0, sa_mux_lev_2_predec_blk1, is_dram); + PredecBlkDrv *sa_mux_lev_2_predec_blk_drv2 = + new PredecBlkDrv(0, sa_mux_lev_2_predec_blk2, is_dram); + way_sel_drv1 = new PredecBlkDrv(dyn_p.number_way_select_signals_mat, + dummy_way_sel_predec_blk1, is_dram); + dummy_way_sel_predec_blk_drv2 = + new PredecBlkDrv(1, dummy_way_sel_predec_blk2, is_dram); + + r_predec = new Predec(r_predec_blk_drv1, r_predec_blk_drv2); + b_mux_predec = new Predec(b_mux_predec_blk_drv1, b_mux_predec_blk_drv2); + sa_mux_lev_1_predec = + new Predec(sa_mux_lev_1_predec_blk_drv1, sa_mux_lev_1_predec_blk_drv2); + sa_mux_lev_2_predec = + new Predec(sa_mux_lev_2_predec_blk_drv1, sa_mux_lev_2_predec_blk_drv2); + + subarray_out_wire = + new Wire(Global, (g_ip->cl_vertical ? subarray.area.w : subarray.area.h), + 1, 1, inside_mat); // should be subarray.area.w; if with /2 + // means average length + + double driver_c_gate_load; + double driver_c_wire_load; + double driver_r_wire_load; + + if (is_fa || pure_cam) + + { // Although CAM and RAM use different bl pre-charge driver, assuming the + // precharge p size is the same + driver_c_gate_load = + (subarray.num_cols_fa_cam) * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, + false, false); + driver_c_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.R_per_um; + cam_bl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + if (!pure_cam) { + // This is only used for fully asso not pure CAM + driver_c_gate_load = + (subarray.num_cols_fa_ram) * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, + false, false); + driver_c_wire_load = + subarray.num_cols_fa_ram * cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols_fa_ram * cell.w * g_tp.wire_outside_mat.R_per_um; + bl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + } + } + + else { + driver_c_gate_load = + subarray.num_cols * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, + false, false); + driver_c_wire_load = + subarray.num_cols * cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols * cell.w * g_tp.wire_outside_mat.R_per_um; + bl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + } + double area_row_decoder = + row_dec->area.get_area() * subarray.num_rows * (RWP + ERP + EWP); + double w_row_decoder = area_row_decoder / subarray.area.get_h(); + + double h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux = + compute_bit_mux_sa_precharge_sa_mux_wr_drv_wr_mux_h(); + + /* This means the subarray drivers are along the vertical (y) direction since + * / subarray.area.get_w() is used; so the subarray_out_wire (actually the + * drivers) under the subarray and along the horizontal (x) direction So as + * mentioned above @ line 271 subarray_out_wire = new Wire(g_ip->wt, + * subarray.area.h);//should be subarray.area.w change the out_wire (driver to + * along y direction need carefully rethinking rather than just simply switch + * w with h ) + * */ + double h_subarray_out_drv = + subarray_out_wire->area.get_area() * + (subarray.num_cols / (deg_bl_muxing * dp.Ndsam_lev_1 * dp.Ndsam_lev_2)) / + subarray.area.get_w(); + + h_subarray_out_drv *= (RWP + ERP + SCHP); + + double h_comparators = 0.0; + double w_row_predecode_output_wires = 0.0; + double h_bit_mux_dec_out_wires = 0.0; + double h_senseamp_mux_dec_out_wires = 0.0; + + if ((!is_fa) && (dp.is_tag)) { + // tagbits = (4 * num_cols_subarray / (deg_bl_muxing * dp.Ndsam_lev_1 * + // dp.Ndsam_lev_2)) / num_do_b_mat; + h_comparators = compute_comparators_height(dp.tagbits, dyn_p.num_do_b_mat, + subarray.area.get_w()); + h_comparators *= (RWP + ERP); + } + + // power-gating circuit + bool is_footer = false; + double Isat_subarray = + 2 * simplified_nmos_Isat(g_tp.sram.cell_nmos_w, is_dram, + true); // only one wordline active in a subarray + // 2 means two inverters in an SRAM cell + double detalV_array; //, deltaV_wl, deltaV_floatingBL; + double c_wakeup_array; + + if (!(is_fa || pure_cam) && + g_ip->power_gating) { // for SRAM only at this moment + c_wakeup_array = drain_C_(g_tp.sram.cell_pmos_w, PCH, 1, 1, cell.h, is_dram, + true); // 1 inv + c_wakeup_array += + 2 * drain_C_(g_tp.sram.cell_pmos_w, PCH, 1, 1, cell.h, is_dram, true) + + drain_C_(g_tp.sram.cell_nmos_w, NCH, 1, 1, cell.h, is_dram, + true); // 1 inv + c_wakeup_array *= subarray.num_rows; // all the SRAM cells in a bitline is + // connected to the sleep tx to + // provide Vcc_min + detalV_array = g_tp.sram_cell.Vdd - g_tp.sram_cell.Vcc_min; + + sram_sleep_tx = new Sleep_tx(g_ip->perfloss, Isat_subarray, is_footer, + c_wakeup_array, detalV_array, 1, cell); + + subarray.area.set_h(subarray.area.h + sram_sleep_tx->area.h); + + // TODO: add the sleep tx in the wl driver and + } + + int branch_effort_predec_blk1_out = + (1 << r_predec_blk2->number_input_addr_bits); + int branch_effort_predec_blk2_out = + (1 << r_predec_blk1->number_input_addr_bits); + w_row_predecode_output_wires = + (branch_effort_predec_blk1_out + branch_effort_predec_blk2_out) * + g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP); + + double h_non_cell_area = + (num_subarrays_per_mat / num_subarrays_per_row) * + (h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux + + h_subarray_out_drv + h_comparators); + + double w_non_cell_area = + MAX(w_row_predecode_output_wires, num_subarrays_per_row * w_row_decoder); + + if (deg_bl_muxing > 1) { + h_bit_mux_dec_out_wires = + deg_bl_muxing * g_tp.wire_inside_mat.pitch * (RWP + ERP); + } + if (dp.Ndsam_lev_1 > 1) { + h_senseamp_mux_dec_out_wires = + dp.Ndsam_lev_1 * g_tp.wire_inside_mat.pitch * (RWP + ERP); + } + if (dp.Ndsam_lev_2 > 1) { + h_senseamp_mux_dec_out_wires += + dp.Ndsam_lev_2 * g_tp.wire_inside_mat.pitch * (RWP + ERP); + } + + double h_addr_datain_wires; + if (!g_ip->ver_htree_wires_over_array) { + h_addr_datain_wires = + (dp.number_addr_bits_mat + dp.number_way_select_signals_mat + + (dp.num_di_b_mat + dp.num_do_b_mat) / num_subarrays_per_row) * + g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP); + + if (is_fa || pure_cam) { + h_addr_datain_wires = + (dp.number_addr_bits_mat + + dp.number_way_select_signals_mat + // TODO: revisit + (dp.num_di_b_mat + dp.num_do_b_mat) / num_subarrays_per_row) * + g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP) + + (dp.num_si_b_mat + dp.num_so_b_mat) / num_subarrays_per_row * + g_tp.wire_inside_mat.pitch * SCHP; + } + // h_non_cell_area = 2 * h_bit_mux_sense_amp_precharge_sa_mux + + // MAX(h_addr_datain_wires, 2 * h_subarray_out_drv); + h_non_cell_area = + (h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux + + h_comparators + h_subarray_out_drv) * + (num_subarrays_per_mat / num_subarrays_per_row) + + h_addr_datain_wires + h_bit_mux_dec_out_wires + + h_senseamp_mux_dec_out_wires; + } + + // double area_rectangle_center_mat = h_non_cell_area * w_non_cell_area; + double area_mat_center_circuitry = + (r_predec_blk_drv1->area.get_area() + + b_mux_predec_blk_drv1->area.get_area() + + sa_mux_lev_1_predec_blk_drv1->area.get_area() + + sa_mux_lev_2_predec_blk_drv1->area.get_area() + + way_sel_drv1->area.get_area() + r_predec_blk_drv2->area.get_area() + + b_mux_predec_blk_drv2->area.get_area() + + sa_mux_lev_1_predec_blk_drv2->area.get_area() + + sa_mux_lev_2_predec_blk_drv2->area.get_area() + + r_predec_blk1->area.get_area() + b_mux_predec_blk1->area.get_area() + + sa_mux_lev_1_predec_blk1->area.get_area() + + sa_mux_lev_2_predec_blk1->area.get_area() + + r_predec_blk2->area.get_area() + b_mux_predec_blk2->area.get_area() + + sa_mux_lev_1_predec_blk2->area.get_area() + + sa_mux_lev_2_predec_blk2->area.get_area() + + bit_mux_dec->area.get_area() + sa_mux_lev_1_dec->area.get_area() + + sa_mux_lev_2_dec->area.get_area()) * + (RWP + ERP + EWP); + + // double area_efficiency_mat; + + // if (!is_fa) + // { + assert(num_subarrays_per_mat / num_subarrays_per_row > 0); + area.h = (num_subarrays_per_mat / num_subarrays_per_row) * subarray.area.h + + h_non_cell_area; + area.w = num_subarrays_per_row * subarray.area.get_w() + w_non_cell_area; + area.w = (area.h * area.w + area_mat_center_circuitry) / area.h; + // area_efficiency_mat = subarray.area.get_area() * num_subarrays_per_mat * + // 100.0 / area.get_area(); + + // cout<<"h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux"< 0); + assert(area.w > 0); + // } + // else + // { + // area.h = (num_subarrays_per_mat / num_subarrays_per_row) * + // subarray.area.get_h() + h_non_cell_area; area.w = num_subarrays_per_row + // * subarray.area.get_w() + w_non_cell_area; area.w = (area.h*area.w + + // area_mat_center_circuitry) / area.h; area_efficiency_mat = + // subarray.area.get_area() * num_subarrays_per_row * 100.0 / + // area.get_area(); + // } +} + +Mat::~Mat() { + delete row_dec; + delete bit_mux_dec; + delete sa_mux_lev_1_dec; + delete sa_mux_lev_2_dec; + + delete r_predec->blk1; + delete r_predec->blk2; + delete b_mux_predec->blk1; + delete b_mux_predec->blk2; + delete sa_mux_lev_1_predec->blk1; + delete sa_mux_lev_1_predec->blk2; + delete sa_mux_lev_2_predec->blk1; + delete sa_mux_lev_2_predec->blk2; + delete dummy_way_sel_predec_blk1; + delete dummy_way_sel_predec_blk2; + + delete r_predec->drv1; + delete r_predec->drv2; + delete b_mux_predec->drv1; + delete b_mux_predec->drv2; + delete sa_mux_lev_1_predec->drv1; + delete sa_mux_lev_1_predec->drv2; + delete sa_mux_lev_2_predec->drv1; + delete sa_mux_lev_2_predec->drv2; + delete way_sel_drv1; + delete dummy_way_sel_predec_blk_drv2; + + delete r_predec; + delete b_mux_predec; + delete sa_mux_lev_1_predec; + delete sa_mux_lev_2_predec; + + delete subarray_out_wire; + if (!pure_cam) + delete bl_precharge_eq_drv; + + if (is_fa || pure_cam) { + delete sl_precharge_eq_drv; + delete sl_data_drv; + delete cam_bl_precharge_eq_drv; + delete ml_precharge_drv; + delete ml_to_ram_wl_drv; + } + if (sram_sleep_tx != 0) { + delete sram_sleep_tx; + } +} + +double Mat::compute_delays(double inrisetime) { + int k; + double rd, C_intrinsic, C_ld, tf, R_bl_precharge, r_b_metal, R_bl, C_bl; + double outrisetime_search, outrisetime, row_dec_outrisetime; + // delay calculation for tags of fully associative cache + if (is_fa || pure_cam) { + // Compute search access time + outrisetime_search = compute_cam_delay(inrisetime); + if (is_fa) { + bl_precharge_eq_drv->compute_delay(0); + k = ml_to_ram_wl_drv->number_gates - 1; + rd = tr_R_on(ml_to_ram_wl_drv->width_n[k], NCH, 1, is_dram, false, true); + C_intrinsic = drain_C_(ml_to_ram_wl_drv->width_n[k], PCH, 1, 1, + 4 * cell.h, is_dram, false, true) + + drain_C_(ml_to_ram_wl_drv->width_n[k], NCH, 1, 1, + 4 * cell.h, is_dram, false, true); + C_ld = ml_to_ram_wl_drv->c_gate_load + ml_to_ram_wl_drv->c_wire_load; + tf = rd * (C_intrinsic + C_ld) + ml_to_ram_wl_drv->r_wire_load * C_ld / 2; + delay_wl_reset = horowitz(0, tf, 0.5, 0.5, RISE); + + R_bl_precharge = + tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false); + r_b_metal = cam_cell.h * + g_tp.wire_local.R_per_um; // dummy rows in sram are filled in + R_bl = subarray.num_rows * r_b_metal; + C_bl = subarray.C_bl; + delay_bl_restore = bl_precharge_eq_drv->delay + + log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) / + (g_tp.sram.Vbitpre - dp.V_b_sense)) * + (R_bl_precharge * C_bl + R_bl * C_bl / 2); + + outrisetime_search = compute_bitline_delay(outrisetime_search); + outrisetime_search = compute_sa_delay(outrisetime_search); + } + outrisetime_search = compute_subarray_out_drv(outrisetime_search); + subarray_out_wire->set_in_rise_time(outrisetime_search); + outrisetime_search = subarray_out_wire->signal_rise_time(); + delay_subarray_out_drv_htree = + delay_subarray_out_drv + subarray_out_wire->delay; + + // TODO: this is just for compute plain read/write energy for fa and cam, + // plain read/write access timing need to be revisited. + outrisetime = r_predec->compute_delays(inrisetime); + row_dec_outrisetime = row_dec->compute_delays(outrisetime); + + outrisetime = b_mux_predec->compute_delays(inrisetime); + bit_mux_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_1_predec->compute_delays(inrisetime); + sa_mux_lev_1_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_2_predec->compute_delays(inrisetime); + sa_mux_lev_2_dec->compute_delays(outrisetime); + + if (pure_cam) { + outrisetime = compute_bitline_delay(row_dec_outrisetime); + outrisetime = compute_sa_delay(outrisetime); + } + return outrisetime_search; + } + else { + bl_precharge_eq_drv->compute_delay(0); + if (row_dec->exist == true) { + int k = row_dec->num_gates - 1; + double rd = tr_R_on(row_dec->w_dec_n[k], NCH, 1, is_dram, false, true); + // TODO: this 4*cell.h number must be revisited + double C_intrinsic = drain_C_(row_dec->w_dec_p[k], PCH, 1, 1, 4 * cell.h, + is_dram, false, true) + + drain_C_(row_dec->w_dec_n[k], NCH, 1, 1, 4 * cell.h, + is_dram, false, true); + double C_ld = row_dec->C_ld_dec_out; + double tf = + rd * (C_intrinsic + C_ld) + row_dec->R_wire_dec_out * C_ld / 2; + delay_wl_reset = horowitz(0, tf, 0.5, 0.5, RISE); + } + double R_bl_precharge = + tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false); + double r_b_metal = cell.h * g_tp.wire_local.R_per_um; + double R_bl = subarray.num_rows * r_b_metal; + double C_bl = subarray.C_bl; + + if (is_dram) { + delay_bl_restore = bl_precharge_eq_drv->delay + + 2.3 * (R_bl_precharge * C_bl + R_bl * C_bl / 2); + } + else { + delay_bl_restore = bl_precharge_eq_drv->delay + + log((g_tp.sram.Vbitpre - 0.1 * dp.V_b_sense) / + (g_tp.sram.Vbitpre - dp.V_b_sense)) * + (R_bl_precharge * C_bl + R_bl * C_bl / 2); + } + } + + outrisetime = r_predec->compute_delays(inrisetime); + row_dec_outrisetime = row_dec->compute_delays(outrisetime); + + outrisetime = b_mux_predec->compute_delays(inrisetime); + bit_mux_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_1_predec->compute_delays(inrisetime); + sa_mux_lev_1_dec->compute_delays(outrisetime); + + outrisetime = sa_mux_lev_2_predec->compute_delays(inrisetime); + sa_mux_lev_2_dec->compute_delays(outrisetime); + + outrisetime = compute_bitline_delay(row_dec_outrisetime); + outrisetime = compute_sa_delay(outrisetime); + outrisetime = compute_subarray_out_drv(outrisetime); + subarray_out_wire->set_in_rise_time(outrisetime); + outrisetime = subarray_out_wire->signal_rise_time(); + + delay_subarray_out_drv_htree = + delay_subarray_out_drv + subarray_out_wire->delay; + + if (dp.is_tag == true && dp.fully_assoc == false) { + compute_comparator_delay(0); + } + + if (row_dec->exist == false) { + delay_wl_reset = MAX(r_predec->blk1->delay, r_predec->blk2->delay); + } + + // cout<<"r_predec delay=" <delay<<" row_dec delay = " + // <delay< 1) { + height += compute_tr_width_after_folding( + g_tp.w_nmos_b_mux, cell.w / (2 * (RWP + ERP))); // col mux tr height + // height += deg_bl_muxing * g_tp.wire_inside_mat.pitch * (RWP + ERP); // + // bit mux dec out wires height + } + + height += + height_sense_amplifier(/*camFlag? sram_cell.w:*/ cell.w * deg_bl_muxing / + (RWP + ERP)); // sense_amp_height + + if (dp.Ndsam_lev_1 > 1) { + height += compute_tr_width_after_folding( + g_tp.w_nmos_sa_mux, + cell.w * dp.Ndsam_lev_1 / (RWP + ERP)); // sense_amp_mux_height + // height_senseamp_mux_decode_output_wires = Ndsam * wire_inside_mat_pitch + // * (RWP + ERP); + } + + if (dp.Ndsam_lev_2 > 1) { + height += compute_tr_width_after_folding( + g_tp.w_nmos_sa_mux, cell.w * deg_bl_muxing * dp.Ndsam_lev_1 / + (RWP + ERP)); // sense_amp_mux_height + // height_senseamp_mux_decode_output_wires = Ndsam * wire_inside_mat_pitch + // * (RWP + ERP); + + // add height of inverter-buffers between the two levels (pass-transistors) + // of sense-amp mux + height += 2 * compute_tr_width_after_folding( + pmos_to_nmos_sz_ratio(is_dram) * g_tp.min_w_nmos_, + cell.w * dp.Ndsam_lev_2 / (RWP + ERP)); + height += 2 * compute_tr_width_after_folding( + g_tp.min_w_nmos_, cell.w * dp.Ndsam_lev_2 / (RWP + ERP)); + } + + // TODO: this should be uncommented... + /*if (deg_bl_muxing * dp.Ndsam_lev_1 * dp.Ndsam_lev_2 > 1) + { + //height_write_mux_decode_output_wires = deg_bl_muxing * Ndsam * + g_tp.wire_inside_mat.pitch * (RWP + EWP); double width_write_driver_write_mux + = width_write_driver_or_write_mux(); double height_write_driver_write_mux = + compute_tr_width_after_folding(2 * width_write_driver_write_mux, cell.w * + // deg_bl_muxing * + dp.Ndsam_lev_1 * dp.Ndsam_lev_2 / (RWP + EWP)); + height += height_write_driver_write_mux; + }*/ + + return height; +} + +double Mat::compute_cam_delay(double inrisetime) { + double out_time_ramp, this_delay; + double Rwire, tf, c_intrinsic, rd, Cwire, c_gate_load; + + double // Wdecdrivep, Wdecdriven, Wfadriven, Wfadrivep, Wfadrive2n, + // Wfadrive2p, Wfadecdrive1n, Wfadecdrive1p, Wfadecdrive2n, + // Wfadecdrive2p, Wfadecdriven, Wfadecdrivep, Wfaprechn, + Wfaprechp, + Wdummyn, Wdummyinvn, Wdummyinvp, + // Wfainvn, Wfainvp, + Waddrnandn, Waddrnandp, + // Wfanandn, Wfanandp, + Wfanorn, Wfanorp, + // Wdecnandn, Wdecnandp, + W_hit_miss_n, W_hit_miss_p; + + double c_matchline_metal, r_matchline_metal, c_searchline_metal, + r_searchline_metal, dynSearchEng; + int Htagbits; + + double driver_c_gate_load; + double driver_c_wire_load; + double driver_r_wire_load; + // double searchline_precharge_time; + + double leak_power_cc_inverters_sram_cell = 0; + double leak_power_acc_tr_RW_or_WR_port_sram_cell = 0; + double leak_power_RD_port_sram_cell = 0; + double leak_power_SCHP_port_sram_cell = 0; + double leak_comparator_cam_cell = 0; + + double gate_leak_comparator_cam_cell = 0; + double gate_leak_power_cc_inverters_sram_cell = 0; + double gate_leak_power_RD_port_sram_cell = 0; + double gate_leak_power_SCHP_port_sram_cell = 0; + + c_matchline_metal = cam_cell.get_w() * g_tp.wire_local.C_per_um; + c_searchline_metal = cam_cell.get_h() * g_tp.wire_local.C_per_um; + r_matchline_metal = cam_cell.get_w() * g_tp.wire_local.R_per_um; + r_searchline_metal = cam_cell.get_h() * g_tp.wire_local.R_per_um; + + dynSearchEng = 0.0; + delay_matchchline = 0.0; + double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(is_dram); + bool linear_scaling = false; + + if (linear_scaling) { + // Wdecdrivep = + // 450 * g_ip->F_sz_um; // this was 360 micron for the 0.8 micron + // process + // Wdecdriven = + // 300 * g_ip->F_sz_um; // this was 240 micron for the 0.8 micron + // process + // Wfadriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfadrive2n = + // 250 * g_ip->F_sz_um; // this was 200 micron for the 0.8 micron + // process + // Wfadrive2p = + // 500 * g_ip->F_sz_um; // this was 400 micron for the 0.8 micron + // process + // Wfadecdrive1n = + // 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron + // process + // Wfadecdrive1p = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfadecdrive2n = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfadecdrive2p = + // 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron + // process + // Wfadecdriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadecdrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfaprechn = + // 7.5 * g_ip->F_sz_um; // this was 6 micron for the 0.8 micron + // process + // Wfainvn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfainvp = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandn = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + // Wdecnandn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wdecnandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + + Wfaprechp = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + Wdummyn = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + Wdummyinvn = + 75 * g_ip->F_sz_um; // this was 60 micron for the 0.8 micron process + Wdummyinvp = + 100 * g_ip->F_sz_um; // this was 80 micron for the 0.8 micron process + Waddrnandn = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Waddrnandp = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Wfanorn = + 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron process + Wfanorp = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + W_hit_miss_n = Wdummyn; + W_hit_miss_p = g_tp.min_w_nmos_ * p_to_n_sizing_r; + // TODO: this number should updated using new layout; from the NAND to + // output NOR should be computed using logical effort + } + else { + // Wdecdrivep = + // 450 * g_ip->F_sz_um; // this was 360 micron for the 0.8 micron + // process + // Wdecdriven = + // 300 * g_ip->F_sz_um; // this was 240 micron for the 0.8 micron + // process + // Wfadriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfadrive2n = + // 250 * g_ip->F_sz_um; // this was 200 micron for the 0.8 micron + // process + // Wfadrive2p = + // 500 * g_ip->F_sz_um; // this was 400 micron for the 0.8 micron + // process + // Wfadecdrive1n = + // 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron + // process + // Wfadecdrive1p = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfadecdrive2n = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfadecdrive2p = + // 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron + // process + // Wfadecdriven = + // 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron + // process + // Wfadecdrivep = + // 125 * g_ip->F_sz_um; // this was 100 micron for the 0.8 micron + // process + // Wfaprechn = + // 7.5 * g_ip->F_sz_um; // this was 6 micron for the 0.8 micron + // process + // Wfainvn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wfainvp = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandn = + // 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron + // process + // Wfanandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + // Wdecnandn = + // 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron + // process + // Wdecnandp = + // 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron + // process + + Wfaprechp = g_tp.w_pmos_bl_precharge; // this was 10 micron for the 0.8 + // micron process + Wdummyn = g_tp.cam.cell_nmos_w; + Wdummyinvn = + 75 * g_ip->F_sz_um; // this was 60 micron for the 0.8 micron process + Wdummyinvp = + 100 * g_ip->F_sz_um; // this was 80 micron for the 0.8 micron process + Waddrnandn = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Waddrnandp = + 62.5 * g_ip->F_sz_um; // this was 50 micron for the 0.8 micron process + Wfanorn = + 6.25 * g_ip->F_sz_um; // this was 5 micron for the 0.8 micron process + Wfanorp = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + W_hit_miss_n = Wdummyn; + W_hit_miss_p = g_tp.min_w_nmos_ * p_to_n_sizing_r; + } + + Htagbits = (int)(ceil((double)(subarray.num_cols_fa_cam) / 2.0)); + + /* First stage, searchline is precharged. searchline data driver drives the + searchline to open (if miss) the comparators. search_line_delay, + search_line_power, search_line_restore_delay for cycle time computation. + From the driver(am and an) to the comparators in all the rows including the + dummy row, Assuming that comparators in both the normal matching line and + the dummy matching line have the same sizing */ + + // Searchline precharge circuitry is same as that of bitline. However, no + // sharing between search ports and r/w ports Searchline precharge routes + // horizontally + driver_c_gate_load = subarray.num_cols_fa_cam * + gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, + 0, is_dram, false, false); + driver_c_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.C_per_um; + driver_r_wire_load = + subarray.num_cols_fa_cam * cam_cell.w * g_tp.wire_outside_mat.R_per_um; + + sl_precharge_eq_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + // searchline data driver ; subarray.num_rows + 1 is because of the dummy row + // data drv should only have gate_C not 2*gate_C since the two searchlines are + // differential--same as bitlines + driver_c_gate_load = + (subarray.num_rows + 1) * gate_C(Wdummyn, 0, is_dram, false, false); + driver_c_wire_load = (subarray.num_rows + 1) * c_searchline_metal; + driver_r_wire_load = (subarray.num_rows + 1) * r_searchline_metal; + sl_data_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + sl_precharge_eq_drv->compute_delay(0); + double R_bl_precharge = + tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, + false); // Assuming CAM and SRAM have same Pre_eq_dr + double r_b_metal = cam_cell.h * g_tp.wire_local.R_per_um; + double R_bl = (subarray.num_rows + 1) * r_b_metal; + double C_bl = subarray.C_bl_cam; + delay_cam_sl_restore = + sl_precharge_eq_drv->delay + + log(g_tp.cam.Vbitpre) * (R_bl_precharge * C_bl + R_bl * C_bl / 2); + + out_time_ramp = sl_data_drv->compute_delay( + inrisetime); // After entering one mat, start + // to consider the inrisetime from + // 0(0 is passed from outside) + + // matchline ops delay + delay_matchchline += sl_data_drv->delay; + + /* second stage, from the trasistors in the comparators(both normal row and + * dummy row) to the NAND gates that combins both half*/ + // matchline delay, matchline power, matchline_reset for cycle time + // computation, + + ////matchline precharge circuitry routes vertically + // There are two matchline precharge driver chains per subarray. + driver_c_gate_load = (subarray.num_rows + 1) * gate_C(Wfaprechp, 0, is_dram); + driver_c_wire_load = (subarray.num_rows + 1) * c_searchline_metal; + driver_r_wire_load = (subarray.num_rows + 1) * r_searchline_metal; + + ml_precharge_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + ml_precharge_drv->compute_delay(0); + + rd = tr_R_on(Wdummyn, NCH, 2, is_dram); + c_intrinsic = + Htagbits * + (2 * drain_C_(Wdummyn, NCH, 2, 1, g_tp.cell_h_def, + is_dram) // TODO: the cell_h_def should be revisit + + drain_C_(Wfaprechp, PCH, 1, 1, g_tp.cell_h_def, is_dram) / + Htagbits); // since each halve only has one precharge tx per + // matchline + + Cwire = c_matchline_metal * Htagbits; + Rwire = r_matchline_metal * Htagbits; + c_gate_load = gate_C(Waddrnandn + Waddrnandp, 0, is_dram); + + double R_ml_precharge = tr_R_on(Wfaprechp, PCH, 1, is_dram); + // double r_ml_metal = cam_cell.w * g_tp.wire_local.R_per_um; + double R_ml = Rwire; + double C_ml = Cwire + c_intrinsic; + delay_cam_ml_reset = + ml_precharge_drv->delay + + log(g_tp.cam.Vbitpre) * + (R_ml_precharge * C_ml + + R_ml * C_ml / + 2); // TODO: latest CAM has sense amps on matchlines too + + // matchline ops delay + tf = rd * (c_intrinsic + Cwire / 2 + c_gate_load) + + Rwire * (Cwire / 2 + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, VTHFA2, VTHFA3, FALL); + delay_matchchline += this_delay; + out_time_ramp = this_delay / VTHFA3; + + dynSearchEng += + ((c_intrinsic + Cwire + c_gate_load) * + (subarray.num_rows + 1)) //+ 2*drain_C_(Wdummyn, NCH, 2, 1, + // g_tp.cell_h_def, is_dram))//TODO: + // need to be precise + * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * + 2; //* Ntbl;//each subarry has two halves + + /* third stage, from the NAND2 gates to the drivers in the dummy row */ + rd = tr_R_on(Waddrnandn, NCH, 2, is_dram); + c_intrinsic = drain_C_(Waddrnandn, NCH, 2, 1, g_tp.cell_h_def, is_dram) + + drain_C_(Waddrnandp, PCH, 1, 1, g_tp.cell_h_def, is_dram) * 2; + c_gate_load = gate_C(Wdummyinvn + Wdummyinvp, 0, is_dram); + tf = rd * (c_intrinsic + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, VTHFA3, VTHFA4, RISE); + out_time_ramp = this_delay / (1 - VTHFA4); + delay_matchchline += this_delay; + + // only the dummy row has the extra inverter between NAND and NOR gates + dynSearchEng += (c_intrinsic * (subarray.num_rows + 1) + c_gate_load * 2) * + g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; // * Ntbl; + + /* fourth stage, from the driver in dummy matchline to the NOR2 gate which + * drives the wordline of the data portion */ + rd = tr_R_on(Wdummyinvn, NCH, 1, is_dram); + c_intrinsic = drain_C_(Wdummyinvn, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(Wdummyinvp, NCH, 1, 1, g_tp.cell_h_def, is_dram); + Cwire = c_matchline_metal * Htagbits + + c_searchline_metal * (subarray.num_rows + 1) / 2; + Rwire = r_matchline_metal * Htagbits + + r_searchline_metal * (subarray.num_rows + 1) / 2; + c_gate_load = gate_C(Wfanorn + Wfanorp, 0, is_dram); + tf = rd * (c_intrinsic + Cwire + c_gate_load) + + Rwire * (Cwire / 2 + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, VTHFA4, VTHFA5, FALL); + out_time_ramp = this_delay / VTHFA5; + delay_matchchline += this_delay; + + dynSearchEng += (c_intrinsic + Cwire + subarray.num_rows * c_gate_load) * + g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; //* Ntbl; + + /*final statge from the NOR gate to drive the wordline of the data portion */ + + // searchline data driver There are two matchline precharge driver chains per + // subarray. + driver_c_gate_load = gate_C(W_hit_miss_n, 0, is_dram, false, + false); // nmos of the pull down logic + driver_c_wire_load = subarray.C_wl_ram; + driver_r_wire_load = subarray.R_wl_ram; + + ml_to_ram_wl_drv = new Driver(driver_c_gate_load, driver_c_wire_load, + driver_r_wire_load, is_dram); + + rd = tr_R_on(Wfanorn, NCH, 1, is_dram); + c_intrinsic = 2 * drain_C_(Wfanorn, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(Wfanorp, NCH, 1, 1, g_tp.cell_h_def, is_dram); + c_gate_load = gate_C( + ml_to_ram_wl_drv->width_n[0] + ml_to_ram_wl_drv->width_p[0], 0, is_dram); + tf = rd * (c_intrinsic + c_gate_load); + this_delay = horowitz(out_time_ramp, tf, 0.5, 0.5, RISE); + out_time_ramp = this_delay / (1 - 0.5); + delay_matchchline += this_delay; + + out_time_ramp = ml_to_ram_wl_drv->compute_delay(out_time_ramp); + + // c_gate_load energy is computed in ml_to_ram_wl_drv + dynSearchEng += + (c_intrinsic)*g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; //* Ntbl; + + /* peripheral-- hitting logic "CMOS VLSI Design Fig11.51*/ + /*Precharge the hitting logic */ + c_intrinsic = 2 * drain_C_(W_hit_miss_p, NCH, 2, 1, g_tp.cell_h_def, is_dram); + Cwire = c_searchline_metal * subarray.num_rows; + Rwire = r_searchline_metal * subarray.num_rows; + c_gate_load = drain_C_(W_hit_miss_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) * + subarray.num_rows; + + rd = tr_R_on(W_hit_miss_p, PCH, 1, is_dram, false, false); + // double r_ml_metal = cam_cell.w * g_tp.wire_local.R_per_um; + double R_hit_miss = Rwire; + double C_hit_miss = Cwire + c_intrinsic; + delay_hit_miss_reset = + log(g_tp.cam.Vbitpre) * (rd * C_hit_miss + R_hit_miss * C_hit_miss / 2); + dynSearchEng += (c_intrinsic + Cwire + c_gate_load) * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd; + + /*hitting logic evaluation */ + c_intrinsic = 2 * drain_C_(W_hit_miss_n, NCH, 2, 1, g_tp.cell_h_def, is_dram); + Cwire = c_searchline_metal * subarray.num_rows; + Rwire = r_searchline_metal * subarray.num_rows; + c_gate_load = drain_C_(W_hit_miss_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) * + subarray.num_rows; + + rd = tr_R_on(W_hit_miss_n, PCH, 1, is_dram, false, false); + tf = rd * (c_intrinsic + Cwire / 2 + c_gate_load) + + Rwire * (Cwire / 2 + c_gate_load); + + delay_hit_miss = horowitz(0, tf, 0.5, 0.5, FALL); + + if (is_fa) + delay_matchchline += MAX(ml_to_ram_wl_drv->delay, delay_hit_miss); + + dynSearchEng += (c_intrinsic + Cwire + c_gate_load) * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd; + + /* TODO: peripheral-- Priority Encoder, usually this is not necessary in + * processor components*/ + + power_matchline.searchOp.dynamic = dynSearchEng; + + // leakage in one subarray + double Iport = + cmos_Isub_leakage(g_tp.cam.cell_a_w, 0, 1, nmos, false, + true); // TODO: how much is the idle time? just by *2? + double Iport_erp = + cmos_Isub_leakage(g_tp.cam.cell_a_w, 0, 2, nmos, false, true); + double Icell = cmos_Isub_leakage(g_tp.cam.cell_nmos_w, g_tp.cam.cell_pmos_w, + 1, inv, false, true) * + 2; + double Icell_comparator = + cmos_Isub_leakage(Wdummyn, Wdummyn, 1, inv, false, true) * + 2; // approx XOR with Inv + + leak_power_cc_inverters_sram_cell = Icell * g_tp.cam_cell.Vdd; + leak_comparator_cam_cell = Icell_comparator * g_tp.cam_cell.Vdd; + leak_power_acc_tr_RW_or_WR_port_sram_cell = Iport * g_tp.cam_cell.Vdd; + leak_power_RD_port_sram_cell = Iport_erp * g_tp.cam_cell.Vdd; + leak_power_SCHP_port_sram_cell = + 0; // search port and r/w port are sperate, + // therefore no access txs in search ports + + power_matchline.searchOp.leakage += + leak_power_cc_inverters_sram_cell + leak_comparator_cam_cell + + leak_power_acc_tr_RW_or_WR_port_sram_cell + + leak_power_acc_tr_RW_or_WR_port_sram_cell * (RWP + EWP - 1) + + leak_power_RD_port_sram_cell * ERP + + leak_power_SCHP_port_sram_cell * SCHP; + // power_matchline.searchOp.leakage += leak_comparator_cam_cell; + power_matchline.searchOp.leakage *= + (subarray.num_rows + 1) * + subarray.num_cols_fa_cam; // TODO:dumy line precise + power_matchline.searchOp.leakage += (subarray.num_rows + 1) * + cmos_Isub_leakage(0, Wfaprechp, 1, pmos) * + g_tp.cam_cell.Vdd; + power_matchline.searchOp.leakage += + (subarray.num_rows + 1) * + cmos_Isub_leakage(Waddrnandn, Waddrnandp, 2, nand) * g_tp.cam_cell.Vdd; + power_matchline.searchOp.leakage += + (subarray.num_rows + 1) * cmos_Isub_leakage(Wfanorn, Wfanorp, 2, nor) * + g_tp.cam_cell.Vdd; + // In idle states, the hit/miss txs are closed (on) therefore no Isub + power_matchline.searchOp.leakage += + 0; // subarray.num_rows * cmos_Isub_leakage(W_hit_miss_n, 0,1, nmos) * + // g_tp.cam_cell.Vdd+ + // + cmos_Isub_leakage(0, W_hit_miss_p,1, pmos) * g_tp.cam_cell.Vdd; + + // in idle state, Ig_on only possibly exist in access transistors of read only + // ports + double Ig_port_erp = + cmos_Ig_leakage(g_tp.cam.cell_a_w, 0, 1, nmos, false, true); + double Ig_cell = cmos_Ig_leakage(g_tp.cam.cell_nmos_w, g_tp.cam.cell_pmos_w, + 1, inv, false, true) * + 2; + double Ig_cell_comparator = + cmos_Ig_leakage(Wdummyn, Wdummyn, 1, inv, false, true) * + 2; // cmos_Ig_leakage(Wdummyn, 0, 2, nmos)*2; + + gate_leak_comparator_cam_cell = Ig_cell_comparator * g_tp.cam_cell.Vdd; + gate_leak_power_cc_inverters_sram_cell = Ig_cell * g_tp.cam_cell.Vdd; + gate_leak_power_RD_port_sram_cell = Ig_port_erp * g_tp.sram_cell.Vdd; + gate_leak_power_SCHP_port_sram_cell = 0; + + // cout<<"power_matchline.searchOp.leakage"<array_power_gated? g_tp.sram_cell.Vcc_min : + // g_tp.sram_cell.Vdd); leak_power_acc_tr_RW_or_WR_port_sram_cell = Iport + // * (g_ip->bitline_floating? g_tp.sram.Vbitfloating : + // g_tp.sram_cell.Vdd); leak_power_RD_port_sram_cell = + // Iport_erp * (g_ip->bitline_floating? g_tp.sram.Vbitfloating : + // g_tp.sram_cell.Vdd); + + leak_power_cc_inverters_sram_cell_gated = Icell * g_tp.sram_cell.Vcc_min; + leak_power_acc_tr_RW_or_WR_port_sram_cell_gated = + Iport * g_tp.sram.Vbitfloating; + leak_power_RD_port_sram_cell_gated = Iport_erp * g_tp.sram.Vbitfloating; + // + // leak_power_cc_inverters_sram_cell_gated = + // leak_power_cc_inverters_sram_cell/g_tp.sram_cell.Vdd*g_tp.sram_cell.Vcc_min; + // leak_power_acc_tr_RW_or_WR_port_sram_cell_floating = + // leak_power_acc_tr_RW_or_WR_port_sram_cell/g_tp.sram_cell.Vdd*g_tp.sram.Vbitfloating; + // leak_power_RD_port_sram_cell_floating = + // leak_power_RD_port_sram_cell_floating/g_tp.sram_cell.Vdd*g_tp.sram.Vbitfloating; + // + + // in idle state, Ig_on only possibly exist in access transistors of read + // only ports + double Ig_port_erp = + cmos_Ig_leakage(g_tp.sram.cell_a_w, 0, 1, nmos, false, true); + double Ig_cell = cmos_Ig_leakage( + g_tp.sram.cell_nmos_w, g_tp.sram.cell_pmos_w, 1, inv, false, true); + + gate_leak_power_cc_inverters_sram_cell = Ig_cell * g_tp.sram_cell.Vdd; + gate_leak_power_RD_port_sram_cell = Ig_port_erp * g_tp.sram_cell.Vdd; + } + + double C_drain_bit_mux = drain_C_( + g_tp.w_nmos_b_mux, NCH, 1, 0, + camFlag ? cam_cell.w : cell.w / (2 * (RWP + ERP + SCHP)), is_dram); + double R_bit_mux = tr_R_on(g_tp.w_nmos_b_mux, NCH, 1, is_dram); + double C_drain_sense_amp_iso = drain_C_( + g_tp.w_iso, PCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram); + double R_sense_amp_iso = tr_R_on(g_tp.w_iso, PCH, 1, is_dram); + double C_sense_amp_latch = + gate_C(g_tp.w_sense_p + g_tp.w_sense_n, 0, is_dram) + + drain_C_( + g_tp.w_sense_n, NCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram) + + drain_C_( + g_tp.w_sense_p, PCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram); + double C_drain_sense_amp_mux = drain_C_( + g_tp.w_nmos_sa_mux, NCH, 1, 0, + camFlag ? cam_cell.w : cell.w * deg_bl_muxing / (RWP + ERP + SCHP), + is_dram); + + if (is_dram) { + double fraction = + dp.V_b_sense / ((g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_C / + (g_tp.dram_cell_C + C_bl)); + tstep = 2.3 * fraction * r_dev * + (g_tp.dram_cell_C * (C_bl + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux)) / + (g_tp.dram_cell_C + (C_bl + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux)); + delay_writeback = tstep; + dynRdEnergy += + (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + (g_tp.dram_cell_Vdd / 2) * + g_tp.dram_cell_Vdd /* subarray.num_cols * num_subarrays_per_mat*/; + dynWriteEnergy += + (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch) * + (g_tp.dram_cell_Vdd / 2) * + g_tp.dram_cell_Vdd /* subarray.num_cols * num_subarrays_per_mat*/ * + num_act_mats_hor_dir * 100; + per_bitline_read_energy = (C_bl + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) * + (g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_Vdd; + } + else { + double tau; + + if (deg_bl_muxing > 1) { + tau = (R_cell_pull_down + R_cell_acc) * + (C_bl + 2 * C_drain_bit_mux + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) + + R_bl * (C_bl / 2 + 2 * C_drain_bit_mux + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) + + R_bit_mux * (C_drain_bit_mux + 2 * C_drain_sense_amp_iso + + C_sense_amp_latch + C_drain_sense_amp_mux) + + R_sense_amp_iso * (C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux); + dynRdEnergy += (C_bl + 2 * C_drain_bit_mux) * 2 * dp.V_b_sense * + g_tp.sram_cell.Vdd /* + subarray.num_cols * num_subarrays_per_mat*/ + ; + blfloating_c += (C_bl + 2 * C_drain_bit_mux) * 2; + dynRdEnergy += + (2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2 * dp.V_b_sense * g_tp.sram_cell.Vdd * + (1.0 /*subarray.num_cols * num_subarrays_per_mat*/ / deg_bl_muxing); + blfloating_c += (2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2; + dynWriteEnergy += + ((1.0 /*subarray.num_cols *num_subarrays_per_mat*/ / deg_bl_muxing) / + deg_senseamp_muxing) * + num_act_mats_hor_dir * (C_bl + 2 * C_drain_bit_mux) * + g_tp.sram_cell.Vdd * g_tp.sram_cell.Vdd * 2; + // Write Ops are differential for SRAM + } + else { + tau = (R_cell_pull_down + R_cell_acc) * + (C_bl + C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) + + R_bl * C_bl / 2 + + R_sense_amp_iso * (C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux); + dynRdEnergy += + (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2 * dp.V_b_sense * + g_tp.sram_cell.Vdd /* subarray.num_cols * num_subarrays_per_mat*/; + + blfloating_c += (C_bl + 2 * C_drain_sense_amp_iso + C_sense_amp_latch + + C_drain_sense_amp_mux) * + 2; + dynWriteEnergy += (((1.0 /*subarray.num_cols * num_subarrays_per_mat*/ / + deg_bl_muxing) / + deg_senseamp_muxing) * + num_act_mats_hor_dir * C_bl) * + g_tp.sram_cell.Vdd * g_tp.sram_cell.Vdd * 2; + } + tstep = tau * log(V_b_pre / (V_b_pre - dp.V_b_sense)); + // cout<<"R_cell_pull_down ="<repeater_size * g_tp.min_w_nmos_ * (1 + + // p_to_n_sz_r), 0.0, is_dram); + gate_C(subarray_out_wire->repeater_size * + (subarray_out_wire->wire_length / + subarray_out_wire->repeater_spacing) * + g_tp.min_w_nmos_ * (1 + p_to_n_sz_r), + 0.0, is_dram); + tf = rd * C_ld; + this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE); + delay_subarray_out_drv += this_delay; + inrisetime = this_delay / (1.0 - 0.5); + power_subarray_out_drv.readOp.dynamic += + C_ld * 0.5 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + power_subarray_out_drv.readOp.leakage += + 0; // for now, let leakage of the pass transistor be 0 + power_subarray_out_drv.readOp.power_gated_leakage += 0; + power_subarray_out_drv.readOp.gate_leakage += + cmos_Ig_leakage(g_tp.w_nmos_sa_mux, 0, 1, nmos) * g_tp.peri_global.Vdd; + + return inrisetime; +} + +double Mat::compute_comparator_delay(double inrisetime) { + int A = g_ip->tag_assoc; + + int tagbits_ = + dp.tagbits / + 4; // Assuming there are 4 quarter comparators. input tagbits is already + // a multiple of 4. + + /* First Inverter */ + double Ceq = + gate_C(g_tp.w_comp_inv_n2 + g_tp.w_comp_inv_p2, 0, is_dram) + + drain_C_(g_tp.w_comp_inv_p1, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_inv_n1, NCH, 1, 1, g_tp.cell_h_def, is_dram); + double Req = tr_R_on(g_tp.w_comp_inv_p1, PCH, 1, is_dram); + double tf = Req * Ceq; + double st1del = horowitz(inrisetime, tf, VTHCOMPINV, VTHCOMPINV, FALL); + double nextinputtime = st1del / VTHCOMPINV; + power_comparator.readOp.dynamic += + 0.5 * Ceq * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + + // For each degree of associativity + // there are 4 such quarter comparators + double lkgCurrent = cmos_Isub_leakage(g_tp.w_comp_inv_n1, g_tp.w_comp_inv_p1, + 1, inv, is_dram) * + 4 * A; + double gatelkgCurrent = + cmos_Ig_leakage(g_tp.w_comp_inv_n1, g_tp.w_comp_inv_p1, 1, inv, is_dram) * + 4 * A; + /* Second Inverter */ + Ceq = gate_C(g_tp.w_comp_inv_n3 + g_tp.w_comp_inv_p3, 0, is_dram) + + drain_C_(g_tp.w_comp_inv_p2, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_inv_n2, NCH, 1, 1, g_tp.cell_h_def, is_dram); + Req = tr_R_on(g_tp.w_comp_inv_n2, NCH, 1, is_dram); + tf = Req * Ceq; + double st2del = horowitz(nextinputtime, tf, VTHCOMPINV, VTHCOMPINV, RISE); + nextinputtime = st2del / (1.0 - VTHCOMPINV); + power_comparator.readOp.dynamic += + 0.5 * Ceq * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + lkgCurrent += cmos_Isub_leakage(g_tp.w_comp_inv_n2, g_tp.w_comp_inv_p2, 1, + inv, is_dram) * + 4 * A; + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_comp_inv_n2, g_tp.w_comp_inv_p2, 1, inv, is_dram) * + 4 * A; + + /* Third Inverter */ + Ceq = gate_C(g_tp.w_eval_inv_n + g_tp.w_eval_inv_p, 0, is_dram) + + drain_C_(g_tp.w_comp_inv_p3, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_inv_n3, NCH, 1, 1, g_tp.cell_h_def, is_dram); + Req = tr_R_on(g_tp.w_comp_inv_p3, PCH, 1, is_dram); + tf = Req * Ceq; + double st3del = horowitz(nextinputtime, tf, VTHCOMPINV, VTHEVALINV, FALL); + nextinputtime = st3del / (VTHEVALINV); + power_comparator.readOp.dynamic += + 0.5 * Ceq * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + lkgCurrent += cmos_Isub_leakage(g_tp.w_comp_inv_n3, g_tp.w_comp_inv_p3, 1, + inv, is_dram) * + 4 * A; + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_comp_inv_n3, g_tp.w_comp_inv_p3, 1, inv, is_dram) * + 4 * A; + + /* Final Inverter (virtual ground driver) discharging compare part */ + double r1 = tr_R_on(g_tp.w_comp_n, NCH, 2, is_dram); + double r2 = tr_R_on(g_tp.w_eval_inv_n, NCH, 1, is_dram); /* was switch */ + double c2 = + (tagbits_) * + (drain_C_(g_tp.w_comp_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_n, NCH, 2, 1, g_tp.cell_h_def, is_dram)) + + drain_C_(g_tp.w_eval_inv_p, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_eval_inv_n, NCH, 1, 1, g_tp.cell_h_def, is_dram); + double c1 = + (tagbits_) * + (drain_C_(g_tp.w_comp_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) + + drain_C_(g_tp.w_comp_n, NCH, 2, 1, g_tp.cell_h_def, is_dram)) + + drain_C_(g_tp.w_comp_p, PCH, 1, 1, g_tp.cell_h_def, is_dram) + + gate_C(WmuxdrvNANDn + WmuxdrvNANDp, 0, is_dram); + power_comparator.readOp.dynamic += + 0.5 * c2 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * 4 * A; + power_comparator.readOp.dynamic += + c1 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * (A - 1); + lkgCurrent += + cmos_Isub_leakage(g_tp.w_eval_inv_n, g_tp.w_eval_inv_p, 1, inv, is_dram) * + 4 * A; + lkgCurrent += + cmos_Isub_leakage(g_tp.w_comp_n, g_tp.w_comp_n, 1, inv, is_dram) * 4 * + A; // stack factor of 0.2 + + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_eval_inv_n, g_tp.w_eval_inv_p, 1, inv, is_dram) * + 4 * A; + gatelkgCurrent += + cmos_Ig_leakage(g_tp.w_comp_n, g_tp.w_comp_n, 1, inv, is_dram) * 4 * + A; // for gate leakage this equals to a inverter + + /* time to go to threshold of mux driver */ + double tstep = (r2 * c2 + (r1 + r2) * c1) * log(1.0 / VTHMUXNAND); + /* take into account non-zero input rise time */ + double m = g_tp.peri_global.Vdd / nextinputtime; + double Tcomparatorni; + + if ((tstep) <= (0.5 * (g_tp.peri_global.Vdd - g_tp.peri_global.Vth) / m)) { + double a = m; + double b = 2 * ((g_tp.peri_global.Vdd * VTHEVALINV) - g_tp.peri_global.Vth); + double c = + -2 * (tstep) * (g_tp.peri_global.Vdd - g_tp.peri_global.Vth) + + 1 / m * ((g_tp.peri_global.Vdd * VTHEVALINV) - g_tp.peri_global.Vth) * + ((g_tp.peri_global.Vdd * VTHEVALINV) - g_tp.peri_global.Vth); + Tcomparatorni = (-b + sqrt(b * b - 4 * a * c)) / (2 * a); + } + else { + Tcomparatorni = (tstep) + + (g_tp.peri_global.Vdd + g_tp.peri_global.Vth) / (2 * m) - + (g_tp.peri_global.Vdd * VTHEVALINV) / m; + } + delay_comparator = Tcomparatorni + st1del + st2del + st3del; + power_comparator.readOp.leakage = lkgCurrent * g_tp.peri_global.Vdd; + power_comparator.readOp.power_gated_leakage = + lkgCurrent * g_tp.peri_global.Vcc_min; + power_comparator.readOp.gate_leakage = gatelkgCurrent * g_tp.peri_global.Vdd; + + return Tcomparatorni / (1.0 - VTHMUXNAND); + ; +} + +void Mat::compute_power_energy() { + // for cam and FA, power.readOp is the plain read power, power.searchOp is the + // associative search related power + // when search all subarrays and all mats are fully active + // when plain read/write only one subarray in a single mat is active. + + // add energy consumed in predecoder drivers. This unit is shared by all + // subarrays in a mat. + power.readOp.dynamic += r_predec->power.readOp.dynamic + + b_mux_predec->power.readOp.dynamic + + sa_mux_lev_1_predec->power.readOp.dynamic + + sa_mux_lev_2_predec->power.readOp.dynamic; + + // add energy consumed in decoders + power_row_decoders.readOp.dynamic = row_dec->power.readOp.dynamic; + if (!(is_fa || pure_cam)) + power_row_decoders.readOp.dynamic *= num_subarrays_per_mat; + + // add energy consumed in bitline prechagers, SAs, and bitlines + if (!(is_fa || pure_cam)) { + // add energy consumed in bitline prechagers + power_bl_precharge_eq_drv.readOp.dynamic = + bl_precharge_eq_drv->power.readOp.dynamic; + power_bl_precharge_eq_drv.readOp.dynamic *= num_subarrays_per_mat; + + // Add sense amps energy + num_sa_subarray = subarray.num_cols / deg_bl_muxing; + power_sa.readOp.dynamic *= num_sa_subarray * num_subarrays_per_mat; + + // add energy consumed in bitlines + // cout<<"bitline power"<power.readOp.dynamic) * + num_do_b_mat; + + power.readOp.dynamic += + power_bl_precharge_eq_drv.readOp.dynamic + power_sa.readOp.dynamic + + power_bitline.readOp.dynamic + power_subarray_out_drv.readOp.dynamic; + + power.readOp.dynamic += power_row_decoders.readOp.dynamic + + bit_mux_dec->power.readOp.dynamic + + sa_mux_lev_1_dec->power.readOp.dynamic + + sa_mux_lev_2_dec->power.readOp.dynamic + + power_comparator.readOp.dynamic; + } + + else if (is_fa) { + // for plain read/write only one subarray in a mat is active + // add energy consumed in bitline prechagers + power_bl_precharge_eq_drv.readOp.dynamic = + bl_precharge_eq_drv->power.readOp.dynamic + + cam_bl_precharge_eq_drv->power.readOp.dynamic; + power_bl_precharge_eq_drv.searchOp.dynamic = + bl_precharge_eq_drv->power.readOp.dynamic; + + // Add sense amps energy + num_sa_subarray = + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram) / deg_bl_muxing; + num_sa_subarray_search = subarray.num_cols_fa_ram / deg_bl_muxing; + power_sa.searchOp.dynamic = + power_sa.readOp.dynamic * num_sa_subarray_search; + power_sa.readOp.dynamic *= num_sa_subarray; + + // add energy consumed in bitlines + power_bitline.searchOp.dynamic = power_bitline.readOp.dynamic; + power_bitline.readOp.dynamic *= + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram); + power_bitline.writeOp.dynamic *= + (subarray.num_cols_fa_cam + subarray.num_cols_fa_ram); + power_bitline.searchOp.dynamic *= subarray.num_cols_fa_ram; + + // Add subarray output energy + power_subarray_out_drv.searchOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_so_b_mat; + power_subarray_out_drv.readOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_do_b_mat; + + power.readOp.dynamic += + power_bl_precharge_eq_drv.readOp.dynamic + power_sa.readOp.dynamic + + power_bitline.readOp.dynamic + power_subarray_out_drv.readOp.dynamic; + + power.readOp.dynamic += power_row_decoders.readOp.dynamic + + bit_mux_dec->power.readOp.dynamic + + sa_mux_lev_1_dec->power.readOp.dynamic + + sa_mux_lev_2_dec->power.readOp.dynamic + + power_comparator.readOp.dynamic; + + // add energy consumed inside cam + power_matchline.searchOp.dynamic *= num_subarrays_per_mat; + power_searchline_precharge = sl_precharge_eq_drv->power; + power_searchline_precharge.searchOp.dynamic = + power_searchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_searchline = sl_data_drv->power; + power_searchline.searchOp.dynamic = power_searchline.readOp.dynamic * + subarray.num_cols_fa_cam * + num_subarrays_per_mat; + ; + power_matchline_precharge = ml_precharge_drv->power; + power_matchline_precharge.searchOp.dynamic = + power_matchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_ml_to_ram_wl_drv = ml_to_ram_wl_drv->power; + power_ml_to_ram_wl_drv.searchOp.dynamic = + ml_to_ram_wl_drv->power.readOp.dynamic; + + power_cam_all_active.searchOp.dynamic = power_matchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_searchline_precharge.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += power_searchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_matchline_precharge.searchOp.dynamic; + + power.searchOp.dynamic += power_cam_all_active.searchOp.dynamic; + // power.searchOp.dynamic += ml_to_ram_wl_drv->power.readOp.dynamic; + } + else { + // add energy consumed in bitline prechagers + power_bl_precharge_eq_drv.readOp.dynamic = + cam_bl_precharge_eq_drv->power.readOp.dynamic; + // power_bl_precharge_eq_drv.readOp.dynamic *= num_subarrays_per_mat; + // power_bl_precharge_eq_drv.searchOp.dynamic = + // cam_bl_precharge_eq_drv->power.readOp.dynamic; + // power_bl_precharge_eq_drv.searchOp.dynamic *= num_subarrays_per_mat; + + // Add sense amps energy + num_sa_subarray = subarray.num_cols_fa_cam / deg_bl_muxing; + power_sa.readOp.dynamic *= num_sa_subarray; //*num_subarrays_per_mat; + power_sa.searchOp.dynamic = 0; + + power_bitline.readOp.dynamic *= subarray.num_cols_fa_cam; + power_bitline.searchOp.dynamic = 0; + power_bitline.writeOp.dynamic *= subarray.num_cols_fa_cam; + + power_subarray_out_drv.searchOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_so_b_mat; + power_subarray_out_drv.readOp.dynamic = + (power_subarray_out_drv.readOp.dynamic + + subarray_out_wire->power.readOp.dynamic) * + num_do_b_mat; + + power.readOp.dynamic += + power_bl_precharge_eq_drv.readOp.dynamic + power_sa.readOp.dynamic + + power_bitline.readOp.dynamic + power_subarray_out_drv.readOp.dynamic; + + power.readOp.dynamic += power_row_decoders.readOp.dynamic + + bit_mux_dec->power.readOp.dynamic + + sa_mux_lev_1_dec->power.readOp.dynamic + + sa_mux_lev_2_dec->power.readOp.dynamic + + power_comparator.readOp.dynamic; + + ////add energy consumed inside cam + power_matchline.searchOp.dynamic *= num_subarrays_per_mat; + power_searchline_precharge = sl_precharge_eq_drv->power; + power_searchline_precharge.searchOp.dynamic = + power_searchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_searchline = sl_data_drv->power; + power_searchline.searchOp.dynamic = power_searchline.readOp.dynamic * + subarray.num_cols_fa_cam * + num_subarrays_per_mat; + ; + power_matchline_precharge = ml_precharge_drv->power; + power_matchline_precharge.searchOp.dynamic = + power_matchline_precharge.readOp.dynamic * num_subarrays_per_mat; + power_ml_to_ram_wl_drv = ml_to_ram_wl_drv->power; + power_ml_to_ram_wl_drv.searchOp.dynamic = + ml_to_ram_wl_drv->power.readOp.dynamic; + + power_cam_all_active.searchOp.dynamic = power_matchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_searchline_precharge.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += power_searchline.searchOp.dynamic; + power_cam_all_active.searchOp.dynamic += + power_matchline_precharge.searchOp.dynamic; + + power.searchOp.dynamic += power_cam_all_active.searchOp.dynamic; + // power.searchOp.dynamic += ml_to_ram_wl_drv->power.readOp.dynamic; + } + + int number_output_drivers_subarray; + // // calculate leakage power + if (!(is_fa || pure_cam)) { + number_output_drivers_subarray = + num_sa_subarray / (dp.Ndsam_lev_1 * dp.Ndsam_lev_2); + + power_bitline.readOp.leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bitline.readOp.power_gated_leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bl_precharge_eq_drv.readOp.leakage = + bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + // bl precharge drv is not power gated to turn off the precharge and + // equalization circuit (PMOS, thus turn-off signal is "1") for bitline + // floating + power_bl_precharge_eq_drv.readOp.power_gated_leakage = + bl_precharge_eq_drv->power.readOp.power_gated_leakage * + num_subarrays_per_mat; + power_sa.readOp.leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP); + + // num_sa_subarray = subarray.num_cols / deg_bl_muxing; + power_subarray_out_drv.readOp.leakage = + (power_subarray_out_drv.readOp.leakage + + subarray_out_wire->power.readOp.leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * (RWP + ERP); + + power_subarray_out_drv.readOp.power_gated_leakage = + (power_subarray_out_drv.readOp.power_gated_leakage + + subarray_out_wire->power.readOp.power_gated_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * (RWP + ERP); + + power.readOp.leakage += power_bitline.readOp.leakage + + power_bl_precharge_eq_drv.readOp.leakage + + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage; + + power.readOp.power_gated_leakage += + power_bitline.readOp.power_gated_leakage + + power_bl_precharge_eq_drv.readOp.power_gated_leakage + + power_sa.readOp.power_gated_leakage + + power_subarray_out_drv.readOp.power_gated_leakage; + + power_comparator.readOp.leakage *= num_do_b_mat * (RWP + ERP); + power.readOp.leakage += power_comparator.readOp.leakage; + + power_comparator.readOp.power_gated_leakage *= num_do_b_mat * (RWP + ERP); + power.readOp.power_gated_leakage += + power_comparator.readOp.power_gated_leakage; + + array_leakage = power_bitline.readOp.leakage; + + cl_leakage = + power_bl_precharge_eq_drv.readOp.leakage + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage + power_comparator.readOp.leakage; + + // Decoder blocks + power_row_decoders.readOp.leakage = row_dec->power.readOp.leakage * + subarray.num_rows * + num_subarrays_per_mat; + power_bit_mux_decoders.readOp.leakage = + bit_mux_dec->power.readOp.leakage * deg_bl_muxing; + power_sa_mux_lev_1_decoders.readOp.leakage = + sa_mux_lev_1_dec->power.readOp.leakage * dp.Ndsam_lev_1; + power_sa_mux_lev_2_decoders.readOp.leakage = + sa_mux_lev_2_dec->power.readOp.leakage * dp.Ndsam_lev_2; + + power_row_decoders.readOp.power_gated_leakage = + row_dec->power.readOp.power_gated_leakage * subarray.num_rows * + num_subarrays_per_mat; + power_bit_mux_decoders.readOp.power_gated_leakage = + bit_mux_dec->power.readOp.power_gated_leakage * deg_bl_muxing; + power_sa_mux_lev_1_decoders.readOp.power_gated_leakage = + sa_mux_lev_1_dec->power.readOp.power_gated_leakage * dp.Ndsam_lev_1; + power_sa_mux_lev_2_decoders.readOp.power_gated_leakage = + sa_mux_lev_2_dec->power.readOp.power_gated_leakage * dp.Ndsam_lev_2; + + // if (!g_ip->wl_power_gated) + // { + power.readOp.leakage += r_predec->power.readOp.leakage + + b_mux_predec->power.readOp.leakage + + sa_mux_lev_1_predec->power.readOp.leakage + + sa_mux_lev_2_predec->power.readOp.leakage + + power_row_decoders.readOp.leakage + + power_bit_mux_decoders.readOp.leakage + + power_sa_mux_lev_1_decoders.readOp.leakage + + power_sa_mux_lev_2_decoders.readOp.leakage; + + power.readOp.power_gated_leakage += + r_predec->power.readOp.power_gated_leakage + + b_mux_predec->power.readOp.power_gated_leakage + + sa_mux_lev_1_predec->power.readOp.power_gated_leakage + + sa_mux_lev_2_predec->power.readOp.power_gated_leakage + + power_row_decoders.readOp.power_gated_leakage + + power_bit_mux_decoders.readOp.power_gated_leakage + + power_sa_mux_lev_1_decoders.readOp.power_gated_leakage + + power_sa_mux_lev_2_decoders.readOp.power_gated_leakage; + + // } + // else + // { + // power.readOp.power_gated_leakage += + // (r_predec->power.readOp.leakage + + // + // b_mux_predec->power.readOp.leakage + + // sa_mux_lev_1_predec->power.readOp.leakage + + // sa_mux_lev_2_predec->power.readOp.leakage + + // power_row_decoders.readOp.leakage + + // power_bit_mux_decoders.readOp.leakage + + // power_sa_mux_lev_1_decoders.readOp.leakage + + // power_sa_mux_lev_2_decoders.readOp.leakage)/g_tp.peri_global.Vdd*g_tp.peri_global.Vcc_min; + + // } + + wl_leakage = r_predec->power.readOp.leakage + + b_mux_predec->power.readOp.leakage + + sa_mux_lev_1_predec->power.readOp.leakage + + sa_mux_lev_2_predec->power.readOp.leakage + + power_row_decoders.readOp.leakage + + power_bit_mux_decoders.readOp.leakage + + power_sa_mux_lev_1_decoders.readOp.leakage + + power_sa_mux_lev_2_decoders.readOp.leakage; + + //++++Below is gate leakage + power_bitline.readOp.gate_leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bl_precharge_eq_drv.readOp.gate_leakage = + bl_precharge_eq_drv->power.readOp.gate_leakage * num_subarrays_per_mat; + power_sa.readOp.gate_leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP); + + // num_sa_subarray = subarray.num_cols / deg_bl_muxing; + power_subarray_out_drv.readOp.gate_leakage = + (power_subarray_out_drv.readOp.gate_leakage + + subarray_out_wire->power.readOp.gate_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * (RWP + ERP); + + power.readOp.gate_leakage += power_bitline.readOp.gate_leakage + + power_bl_precharge_eq_drv.readOp.gate_leakage + + power_sa.readOp.gate_leakage + + power_subarray_out_drv.readOp.gate_leakage; + // cout<<"leakage"<power_gating) { + // cout<<"leakage1"<area.get_area() * subarray.num_cols * + num_subarrays_per_mat * dp.num_mats; + array_wakeup_e.readOp.dynamic = + sram_sleep_tx->wakeup_power.readOp.dynamic * num_subarrays_per_mat * + subarray.num_cols * dp.num_act_mats_hor_dir; + array_wakeup_t = sram_sleep_tx->wakeup_delay; + + wl_sleep_tx_area = + (row_dec->exist ? row_dec->sleeptx->area.get_area() : 0) * + subarray.num_rows * num_subarrays_per_mat * dp.num_mats + + (bit_mux_dec->exist ? bit_mux_dec->sleeptx->area.get_area() : 0) * + dp.num_mats + + (sa_mux_lev_1_dec->exist ? sa_mux_lev_1_dec->sleeptx->area.get_area() + : 0) * + dp.num_mats + + (sa_mux_lev_2_dec->exist ? sa_mux_lev_2_dec->sleeptx->area.get_area() + : 0) * + dp.num_mats; + wl_wakeup_e.readOp.dynamic = + (row_dec->exist ? row_dec->sleeptx->wakeup_power.readOp.dynamic : 0) * + num_subarrays_per_mat * subarray.num_rows * + dp.num_act_mats_hor_dir + + (bit_mux_dec->exist + ? bit_mux_dec->sleeptx->wakeup_power.readOp.dynamic + : 0) * + dp.num_mats + + (sa_mux_lev_1_dec->exist + ? sa_mux_lev_1_dec->sleeptx->wakeup_power.readOp.dynamic + : 0) * + dp.num_mats + + (sa_mux_lev_2_dec->exist + ? sa_mux_lev_2_dec->sleeptx->wakeup_power.readOp.dynamic + : 0) * + dp.num_mats; + wl_wakeup_t = + (row_dec->exist ? row_dec->sleeptx->wakeup_delay : 0) + + (bit_mux_dec->exist ? bit_mux_dec->sleeptx->wakeup_delay : 0) * + dp.num_mats + + (sa_mux_lev_1_dec->exist ? sa_mux_lev_1_dec->sleeptx->wakeup_delay + : 0) * + dp.num_mats + + (sa_mux_lev_2_dec->exist ? sa_mux_lev_2_dec->sleeptx->wakeup_delay + : 0) * + dp.num_mats; + ; + } + + // gate_leakage power + power_row_decoders.readOp.gate_leakage = + row_dec->power.readOp.gate_leakage * subarray.num_rows * + num_subarrays_per_mat; + power_bit_mux_decoders.readOp.gate_leakage = + bit_mux_dec->power.readOp.gate_leakage * deg_bl_muxing; + power_sa_mux_lev_1_decoders.readOp.gate_leakage = + sa_mux_lev_1_dec->power.readOp.gate_leakage * dp.Ndsam_lev_1; + power_sa_mux_lev_2_decoders.readOp.gate_leakage = + sa_mux_lev_2_dec->power.readOp.gate_leakage * dp.Ndsam_lev_2; + + power.readOp.gate_leakage += + r_predec->power.readOp.gate_leakage + + b_mux_predec->power.readOp.gate_leakage + + sa_mux_lev_1_predec->power.readOp.gate_leakage + + sa_mux_lev_2_predec->power.readOp.gate_leakage + + power_row_decoders.readOp.gate_leakage + + power_bit_mux_decoders.readOp.gate_leakage + + power_sa_mux_lev_1_decoders.readOp.gate_leakage + + power_sa_mux_lev_2_decoders.readOp.gate_leakage; + } + else if (is_fa) // fully assoc + { + int number_output_drivers_subarray = + num_sa_subarray; // / (dp.Ndsam_lev_1 * dp.Ndsam_lev_2); + + power_bitline.readOp.leakage *= + subarray.num_rows * subarray.num_cols * num_subarrays_per_mat; + power_bl_precharge_eq_drv.readOp.leakage = + bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_bl_precharge_eq_drv.searchOp.leakage = + cam_bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_sa.readOp.leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + // cout<<"leakage3"<power.readOp.leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp.leakage += power_bitline.readOp.leakage + + power_bl_precharge_eq_drv.readOp.leakage + + power_bl_precharge_eq_drv.searchOp.leakage + + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage; + + // cout<<"leakage4"<power.readOp.leakage * + subarray.num_rows * + num_subarrays_per_mat; + power.readOp.leakage += + r_predec->power.readOp.leakage + power_row_decoders.readOp.leakage; + + // cout<<"leakage5"<power.readOp.leakage; + power_cam_all_active.searchOp.leakage += + sl_data_drv->power.readOp.leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.leakage *= num_subarrays_per_mat; + + power.readOp.leakage += power_cam_all_active.searchOp.leakage; + + // cout<<"leakage6"<power.readOp.gate_leakage * num_subarrays_per_mat; + power_bl_precharge_eq_drv.searchOp.gate_leakage = + cam_bl_precharge_eq_drv->power.readOp.gate_leakage * + num_subarrays_per_mat; + power_sa.readOp.gate_leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + // cout<<"leakage3"<power.readOp.gate_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp.gate_leakage += + power_bitline.readOp.gate_leakage + + power_bl_precharge_eq_drv.readOp.gate_leakage + + power_bl_precharge_eq_drv.searchOp.gate_leakage + + power_sa.readOp.gate_leakage + + power_subarray_out_drv.readOp.gate_leakage; + + // cout<<"leakage4"<power.readOp.gate_leakage * subarray.num_rows * + num_subarrays_per_mat; + power.readOp.gate_leakage += r_predec->power.readOp.gate_leakage + + power_row_decoders.readOp.gate_leakage; + + // cout<<"leakage5"<power.readOp.gate_leakage; + power_cam_all_active.searchOp.gate_leakage += + sl_data_drv->power.readOp.gate_leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.gate_leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.gate_leakage *= num_subarrays_per_mat; + + power.readOp.gate_leakage += power_cam_all_active.searchOp.gate_leakage; + } + else // pure CAM + { + int number_output_drivers_subarray = + num_sa_subarray; // / (dp.Ndsam_lev_1 * dp.Ndsam_lev_2); + + // power_bitline.readOp.leakage *= subarray.num_rows * + // subarray.num_cols * num_subarrays_per_mat; + // power_bl_precharge_eq_drv.readOp.leakage = + // bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_bl_precharge_eq_drv.searchOp.leakage = + cam_bl_precharge_eq_drv->power.readOp.leakage * num_subarrays_per_mat; + power_sa.readOp.leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + power_subarray_out_drv.readOp.leakage = + (power_subarray_out_drv.readOp.leakage + + subarray_out_wire->power.readOp.leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp.leakage += // power_bitline.readOp.leakage + + // power_bl_precharge_eq_drv.readOp.leakage + + power_bl_precharge_eq_drv.searchOp.leakage + power_sa.readOp.leakage + + power_subarray_out_drv.readOp.leakage; + + // leakage power + power_row_decoders.readOp.leakage = + row_dec->power.readOp.leakage * subarray.num_rows * + num_subarrays_per_mat * (RWP + ERP + EWP); + power.readOp.leakage += + r_predec->power.readOp.leakage + power_row_decoders.readOp.leakage; + + // inside cam + power_cam_all_active.searchOp.leakage = power_matchline.searchOp.leakage; + power_cam_all_active.searchOp.leakage += + sl_precharge_eq_drv->power.readOp.leakage; + power_cam_all_active.searchOp.leakage += + sl_data_drv->power.readOp.leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.leakage *= num_subarrays_per_mat; + + power.readOp.leakage += power_cam_all_active.searchOp.leakage; + + //+++Below is gate leakage + power_bl_precharge_eq_drv.searchOp.gate_leakage = + cam_bl_precharge_eq_drv->power.readOp.gate_leakage * + num_subarrays_per_mat; + power_sa.readOp.gate_leakage *= + num_sa_subarray * num_subarrays_per_mat * (RWP + ERP + SCHP); + + power_subarray_out_drv.readOp.gate_leakage = + (power_subarray_out_drv.readOp.gate_leakage + + subarray_out_wire->power.readOp.gate_leakage) * + number_output_drivers_subarray * num_subarrays_per_mat * + (RWP + ERP + SCHP); + + power.readOp + .gate_leakage += // power_bitline.readOp.gate_leakage + + // power_bl_precharge_eq_drv.readOp.gate_leakage + + power_bl_precharge_eq_drv.searchOp.gate_leakage + + power_sa.readOp.gate_leakage + + power_subarray_out_drv.readOp.gate_leakage; + + // gate_leakage power + power_row_decoders.readOp.gate_leakage = + row_dec->power.readOp.gate_leakage * subarray.num_rows * + num_subarrays_per_mat * (RWP + ERP + EWP); + power.readOp.gate_leakage += r_predec->power.readOp.gate_leakage + + power_row_decoders.readOp.gate_leakage; + + // inside cam + power_cam_all_active.searchOp.gate_leakage = + power_matchline.searchOp.gate_leakage; + power_cam_all_active.searchOp.gate_leakage += + sl_precharge_eq_drv->power.readOp.gate_leakage; + power_cam_all_active.searchOp.gate_leakage += + sl_data_drv->power.readOp.gate_leakage * subarray.num_cols_fa_cam; + power_cam_all_active.searchOp.gate_leakage += + ml_precharge_drv->power.readOp.dynamic; + power_cam_all_active.searchOp.gate_leakage *= num_subarrays_per_mat; + + power.readOp.gate_leakage += power_cam_all_active.searchOp.gate_leakage; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/mat.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/mat.h new file mode 100644 index 0000000000..e8886bca55 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/mat.h @@ -0,0 +1,173 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __MAT_H__ +#define __MAT_H__ + +#include "component.h" +#include "decoder.h" +#include "powergating.h" +#include "subarray.h" +#include "wire.h" + +namespace cacti { + +class Mat : public Component { + public: + Mat(const DynamicParameter &dyn_p); + ~Mat(); + double compute_delays(double inrisetime); // return outrisetime + void compute_power_energy(); + + const DynamicParameter &dp; + + // TODO: clean up pointers and powerDefs below + Decoder *row_dec; + Decoder *bit_mux_dec; + Decoder *sa_mux_lev_1_dec; + Decoder *sa_mux_lev_2_dec; + PredecBlk *dummy_way_sel_predec_blk1; + PredecBlk *dummy_way_sel_predec_blk2; + PredecBlkDrv *way_sel_drv1; + PredecBlkDrv *dummy_way_sel_predec_blk_drv2; + + Predec *r_predec; + Predec *b_mux_predec; + Predec *sa_mux_lev_1_predec; + Predec *sa_mux_lev_2_predec; + + Wire *subarray_out_wire; + Driver *bl_precharge_eq_drv; + Driver *cam_bl_precharge_eq_drv; // bitline pre-charge circuit is separated + // for CAM and RAM arrays. + Driver *ml_precharge_drv; // matchline prechange driver + Driver *sl_precharge_eq_drv; // searchline prechage driver + Driver *sl_data_drv; // search line data driver + Driver *ml_to_ram_wl_drv; // search line data driver + + powerDef power_row_decoders; + powerDef power_bit_mux_decoders; + powerDef power_sa_mux_lev_1_decoders; + powerDef power_sa_mux_lev_2_decoders; + powerDef power_fa_cam; // TODO: leakage power is not computed yet + powerDef power_bl_precharge_eq_drv; + powerDef power_subarray_out_drv; + powerDef power_cam_all_active; + powerDef power_searchline_precharge; + powerDef power_matchline_precharge; + powerDef power_ml_to_ram_wl_drv; + + double delay_fa_tag, delay_cam; + double delay_before_decoder; + double delay_bitline; + double delay_wl_reset; + double delay_bl_restore; + + double delay_searchline; + double delay_matchchline; + double delay_cam_sl_restore; + double delay_cam_ml_reset; + double delay_fa_ram_wl; + + double delay_hit_miss_reset; + double delay_hit_miss; + + Subarray subarray; + powerDef power_bitline, power_searchline, power_matchline, + power_bitline_gated; + double per_bitline_read_energy; + int deg_bl_muxing; + int num_act_mats_hor_dir; + double delay_writeback; + Area cell, cam_cell; + bool is_dram, is_fa, pure_cam, camFlag; + int num_mats; + powerDef power_sa; + double delay_sa; + double leak_power_sense_amps_closed_page_state; + double leak_power_sense_amps_open_page_state; + double delay_subarray_out_drv; + double delay_subarray_out_drv_htree; + double delay_comparator; + powerDef power_comparator; + int num_do_b_mat; + int num_so_b_mat; + int num_sa_subarray; + int num_sa_subarray_search; + double C_bl; + + uint32_t num_subarrays_per_mat; // the number of subarrays in a mat + uint32_t num_subarrays_per_row; // the number of subarrays in a row of a mat + + double array_leakage; + double wl_leakage; + double cl_leakage; + + Sleep_tx *sram_sleep_tx; + Sleep_tx *wl_sleep_tx; + Sleep_tx *cl_sleep_tx; + + powerDef array_wakeup_e; + double array_wakeup_t; + double array_sleep_tx_area; + + powerDef blfloating_wakeup_e; + double blfloating_wakeup_t; + double blfloating_sleep_tx_area; + + powerDef wl_wakeup_e; + double wl_wakeup_t; + double wl_sleep_tx_area; + + powerDef cl_wakeup_e; + double cl_wakeup_t; + double cl_sleep_tx_area; + + private: + double compute_bit_mux_sa_precharge_sa_mux_wr_drv_wr_mux_h(); + double width_write_driver_or_write_mux(); + double compute_comparators_height(int tagbits, int number_ways_in_mat, + double subarray_mem_cell_area_w); + double compute_cam_delay(double inrisetime); + double compute_bitline_delay(double inrisetime); + double compute_sa_delay(double inrisetime); + double compute_subarray_out_drv(double inrisetime); + double compute_comparator_delay(double inrisetime); + + int RWP; + int ERP; + int EWP; + int SCHP; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/nuca.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/nuca.cc new file mode 100644 index 0000000000..e946bc2cfa --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/nuca.cc @@ -0,0 +1,596 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "nuca.h" +#include +#include "Ucache.h" +using namespace cacti; + +unsigned int MIN_BANKSIZE = 65536; +#define FIXED_OVERHEAD \ + 55e-12 /* clock skew and jitter in s. Ref: Hrishikesh et al ISCA 01 */ +#define LATCH_DELAY 28e-12 /* latch delay in s (later should use FO4 TODO) */ +#define CONTR_2_BANK_LAT 0 + +int cont_stats[2 /*l2 or l3*/][5 /* cores */][ROUTER_TYPES][8 /*banks*/] + [8 /* cycle time */]; + +Nuca::Nuca(TechnologyParameter::DeviceType *dt) + : deviceType(dt) { + init_cont(); +} + +void Nuca::init_cont() { + FILE *cont; + char line[5000]; + char jk[5000]; + cont = fopen("contention.dat", "r"); + if (!cont) { + cout << "contention.dat file is missing!\n"; + exit(0); + } + + for (int i = 0; i < 2; i++) { + for (int j = 2; j < 5; j++) { + for (int k = 0; k < ROUTER_TYPES; k++) { + for (int l = 0; l < 7; l++) { + int *temp = + cont_stats[i /*l2 or l3*/][j /*core*/] + [k /*64 or 128 or 256 link bw*/][l /* no banks*/]; + assert(fscanf(cont, "%[^\n]\n", line) != EOF); + sscanf(line, "%[^:]: %d %d %d %d %d %d %d %d", jk, &temp[0], &temp[1], + &temp[2], &temp[3], &temp[4], &temp[5], &temp[6], &temp[7]); + } + } + } + } + fclose(cont); +} + +void Nuca::print_cont_stats() { + for (int i = 0; i < 2; i++) { + for (int j = 2; j < 5; j++) { + for (int k = 0; k < ROUTER_TYPES; k++) { + for (int l = 0; l < 7; l++) { + for (int m = 0; l < 7; l++) { + cout << cont_stats[i][j][k][l][m] << " "; + } + cout << endl; + } + } + } + } + cout << endl; +} + +Nuca::~Nuca() { + for (int i = wt_min; i <= wt_max; i++) { + delete wire_vertical[i]; + delete wire_horizontal[i]; + } +} + +/* converts latency (in s) to cycles depending upon the FREQUENCY (in GHz) */ +int Nuca::calc_cycles(double lat, double oper_freq) { + // TODO: convert latch delay to FO4 */ + double cycle_time = (1.0 / (oper_freq * 1e9)); /*s*/ + cycle_time -= LATCH_DELAY; + cycle_time -= FIXED_OVERHEAD; + + return (int)ceil(lat / cycle_time); +} + +nuca_org_t::~nuca_org_t() { + // if(h_wire) delete h_wire; + // if(v_wire) delete v_wire; + // if(router) delete router; +} + +/* + * Version - 6.0 + * + * Perform exhaustive search across different bank organizatons, + * router configurations, grid organizations, and wire models and + * find an optimal NUCA organization + * For different bank count values + * 1. Optimal bank organization is calculated + * 2. For each bank organization, find different NUCA organizations + * using various router configurations, grid organizations, + * and wire models. + * 3. NUCA model with the least cost is picked for + * this particular bank count + * Finally include contention statistics and find the optimal + * NUCA configuration + */ +void Nuca::sim_nuca() { + /* temp variables */ + int it, ro, wr; + int num_cyc; + unsigned int i, j; + unsigned int r, c; + int l2_c; + int bank_count = 0; + uca_org_t ures; + nuca_org_t *opt_n; + mem_array tag, data; + list nuca_list; + Router *router_s[ROUTER_TYPES]; + router_s[0] = new Router(64.0, 8, 4, &(g_tp.peri_global)); + router_s[0]->print_router(); + router_s[1] = new Router(128.0, 8, 4, &(g_tp.peri_global)); + router_s[1]->print_router(); + router_s[2] = new Router(256.0, 8, 4, &(g_tp.peri_global)); + router_s[2]->print_router(); + + int core_in; // to store no. of cores + + /* to search diff grid organizations */ + double curr_hop, totno_hops, totno_hhops, totno_vhops, tot_lat, curr_acclat; + double avg_lat, avg_hop, avg_hhop, avg_vhop, avg_dyn_power, avg_leakage_power; + + double opt_acclat = INF; //, opt_avg_lat = INF, opt_tot_lat = INF; + int opt_rows = 0; + int opt_columns = 0; + // double opt_totno_hops = 0; + double opt_avg_hop = 0; + double opt_dyn_power = 0, opt_leakage_power = 0; + min_values_t minval; + + int bank_start = 0; + + int flit_width = 0; + + /* vertical and horizontal hop latency values */ + int ver_hop_lat, hor_hop_lat; /* in cycles */ + + /* no. of different bank sizes to consider */ + int iterations; + + g_ip->nuca_cache_sz = g_ip->cache_sz; + nuca_list.push_back(new nuca_org_t()); + + if (g_ip->cache_level == 0) + l2_c = 1; + else + l2_c = 0; + + if (g_ip->cores <= 4) + core_in = 2; + else if (g_ip->cores <= 8) + core_in = 3; + else if (g_ip->cores <= 16) + core_in = 4; + else { + cout << "Number of cores should be <= 16!\n"; + exit(0); + } + + // set the lower bound to an appropriate value. this depends on cache + // associativity + if (g_ip->assoc > 2) { + i = 2; + while (i != g_ip->assoc) { + MIN_BANKSIZE *= 2; + i *= 2; + } + } + + iterations = (int)logtwo((int)g_ip->cache_sz / MIN_BANKSIZE); + + if (g_ip->force_wiretype) { + if (g_ip->wt == Low_swing) { + wt_min = Low_swing; + wt_max = Low_swing; + } + else { + wt_min = Global; + wt_max = Low_swing - 1; + } + } + else { + wt_min = Global; + wt_max = Low_swing; + } + if (g_ip->nuca_bank_count != 0) { // simulate just one bank + if (g_ip->nuca_bank_count != 2 && g_ip->nuca_bank_count != 4 && + g_ip->nuca_bank_count != 8 && g_ip->nuca_bank_count != 16 && + g_ip->nuca_bank_count != 32 && g_ip->nuca_bank_count != 64) { + fprintf( + stderr, + "Incorrect bank count value! Please fix the value in cache.cfg\n"); + } + bank_start = (int)logtwo((double)g_ip->nuca_bank_count); + iterations = bank_start + 1; + g_ip->cache_sz = g_ip->cache_sz / g_ip->nuca_bank_count; + } + cout << "Simulating various NUCA configurations\n"; + for (it = bank_start; it < iterations; + it++) { /* different bank count values */ + ures.tag_array2 = &tag; + ures.data_array2 = &data; + /* + * find the optimal bank organization + */ + solve(&ures); + // output_UCA(&ures); + bank_count = g_ip->nuca_cache_sz / g_ip->cache_sz; + cout << "====" << g_ip->cache_sz << "\n"; + + for (wr = wt_min; wr <= wt_max; wr++) { + for (ro = 0; ro < ROUTER_TYPES; ro++) { + flit_width = (int)router_s[ro]->flit_size; // initialize router + nuca_list.back()->nuca_pda.cycle_time = router_s[ro]->cycle_time; + + /* calculate router and wire parameters */ + + double vlength = ures.cache_ht; /* length of the wire (u)*/ + double hlength = ures.cache_len; // u + + /* find delay, area, and power for wires */ + wire_vertical[wr] = new Wire((enum Wire_type)wr, vlength); + wire_horizontal[wr] = new Wire((enum Wire_type)wr, hlength); + + hor_hop_lat = + calc_cycles(wire_horizontal[wr]->delay, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001)); + ver_hop_lat = + calc_cycles(wire_vertical[wr]->delay, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001)); + + /* + * assume a grid like topology and explore for optimal network + * configuration using different row and column count values. + */ + for (c = 1; c <= (unsigned int)bank_count; c++) { + while (bank_count % c != 0) + c++; + r = bank_count / c; + + /* + * to find the avg access latency of a NUCA cache, uncontended + * access time to each bank from the + * cache controller is calculated. + * avg latency = + * sum of the access latencies to individual banks)/bank + * count value. + */ + totno_hops = totno_hhops = totno_vhops = tot_lat = 0; + for (i = 0; i < r; i++) { + for (j = 0; j < c; j++) { + /* + * vertical hops including the + * first hop from the cache controller + */ + curr_hop = i + 1; + curr_hop += j; /* horizontal hops */ + totno_hhops += j; + totno_vhops += (i + 1); + curr_acclat = + (i * ver_hop_lat + CONTR_2_BANK_LAT + j * hor_hop_lat); + + tot_lat += curr_acclat; + totno_hops += curr_hop; + } + } + avg_lat = tot_lat / bank_count; + avg_hop = totno_hops / bank_count; + avg_hhop = totno_hhops / bank_count; + avg_vhop = totno_vhops / bank_count; + + /* net access latency */ + curr_acclat = + 2 * avg_lat + 2 * (router_s[ro]->delay * avg_hop) + + calc_cycles(ures.access_time, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001)); + + /* avg access lat of nuca */ + avg_dyn_power = avg_hop * (router_s[ro]->power.readOp.dynamic) + + avg_hhop * + (wire_horizontal[wr]->power.readOp.dynamic) * + (g_ip->block_sz * 8 + 64) + + avg_vhop * (wire_vertical[wr]->power.readOp.dynamic) * + (g_ip->block_sz * 8 + 64) + + ures.power.readOp.dynamic; + + avg_leakage_power = + bank_count * router_s[ro]->power.readOp.leakage + + avg_hhop * + (wire_horizontal[wr]->power.readOp.leakage * + wire_horizontal[wr]->delay) * + flit_width + + avg_vhop * (wire_vertical[wr]->power.readOp.leakage * + wire_horizontal[wr]->delay); + + if (curr_acclat < opt_acclat) { + opt_acclat = curr_acclat; + // opt_tot_lat = tot_lat; + // opt_avg_lat = avg_lat; + // opt_totno_hops = totno_hops; + opt_avg_hop = avg_hop; + opt_rows = r; + opt_columns = c; + opt_dyn_power = avg_dyn_power; + opt_leakage_power = avg_leakage_power; + } + totno_hops = 0; + tot_lat = 0; + totno_hhops = 0; + totno_vhops = 0; + } + nuca_list.back()->wire_pda.power.readOp.dynamic = + opt_avg_hop * flit_width * + (wire_horizontal[wr]->power.readOp.dynamic + + wire_vertical[wr]->power.readOp.dynamic); + nuca_list.back()->avg_hops = opt_avg_hop; + /* network delay/power */ + nuca_list.back()->h_wire = wire_horizontal[wr]; + nuca_list.back()->v_wire = wire_vertical[wr]; + nuca_list.back()->router = router_s[ro]; + /* bank delay/power */ + + nuca_list.back()->bank_pda.delay = ures.access_time; + nuca_list.back()->bank_pda.power = ures.power; + nuca_list.back()->bank_pda.area.h = ures.cache_ht; + nuca_list.back()->bank_pda.area.w = ures.cache_len; + nuca_list.back()->bank_pda.cycle_time = ures.cycle_time; + + num_cyc = calc_cycles( + nuca_list.back()->bank_pda.delay /*s*/, + 1 / (nuca_list.back()->nuca_pda.cycle_time * .001 /*GHz*/)); + if (num_cyc % 2 != 0) + num_cyc++; + if (num_cyc > 16) + num_cyc = 16; // we have data only up to 16 cycles + + if (it < 7) { + nuca_list.back()->nuca_pda.delay = + opt_acclat + cont_stats[l2_c][core_in][ro][it][num_cyc / 2 - 1]; + nuca_list.back()->contention = + cont_stats[l2_c][core_in][ro][it][num_cyc / 2 - 1]; + } + else { + nuca_list.back()->nuca_pda.delay = + opt_acclat + cont_stats[l2_c][core_in][ro][7][num_cyc / 2 - 1]; + nuca_list.back()->contention = + cont_stats[l2_c][core_in][ro][7][num_cyc / 2 - 1]; + } + nuca_list.back()->nuca_pda.power.readOp.dynamic = opt_dyn_power; + nuca_list.back()->nuca_pda.power.readOp.leakage = opt_leakage_power; + + /* array organization */ + nuca_list.back()->bank_count = bank_count; + nuca_list.back()->rows = opt_rows; + nuca_list.back()->columns = opt_columns; + calculate_nuca_area(nuca_list.back()); + + minval.update_min_values(nuca_list.back()); + nuca_list.push_back(new nuca_org_t()); + opt_acclat = BIGNUM; + } + } + g_ip->cache_sz /= 2; + } + + delete (nuca_list.back()); + nuca_list.pop_back(); + opt_n = find_optimal_nuca(&nuca_list, &minval); + print_nuca(opt_n); + g_ip->cache_sz = g_ip->nuca_cache_sz / opt_n->bank_count; + + list::iterator niter; + for (niter = nuca_list.begin(); niter != nuca_list.end(); ++niter) { + delete *niter; + } + nuca_list.clear(); + + for (int i = 0; i < ROUTER_TYPES; i++) { + delete router_s[i]; + } + g_ip->display_ip(); + // g_ip->force_cache_config = true; + // g_ip->ndwl = 8; + // g_ip->ndbl = 16; + // g_ip->nspd = 4; + // g_ip->ndcm = 1; + // g_ip->ndsam1 = 8; + // g_ip->ndsam2 = 32; +} + +void Nuca::print_nuca(nuca_org_t *fr) { + printf("\n---------- CACTI version 6.5, Non-uniform Cache Access " + "----------\n\n"); + printf("Optimal number of banks - %d\n", fr->bank_count); + printf("Grid organization rows x columns - %d x %d\n", fr->rows, fr->columns); + printf("Network frequency - %g GHz\n", (1 / fr->nuca_pda.cycle_time) * 1e3); + printf("Cache dimension (mm x mm) - %g x %g\n", fr->nuca_pda.area.h * 1e-3, + fr->nuca_pda.area.w * 1e-3); + + fr->router->print_router(); + + printf("\n\nWire stats:\n"); + if (fr->h_wire->wt == Global) { + printf("\tWire type - Full swing global wires with least " + "possible delay\n"); + } + else if (fr->h_wire->wt == Global_5) { + printf("\tWire type - Full swing global wires with " + "5%% delay penalty\n"); + } + else if (fr->h_wire->wt == Global_10) { + printf("\tWire type - Full swing global wires with " + "10%% delay penalty\n"); + } + else if (fr->h_wire->wt == Global_20) { + printf("\tWire type - Full swing global wires with " + "20%% delay penalty\n"); + } + else if (fr->h_wire->wt == Global_30) { + printf("\tWire type - Full swing global wires with " + "30%% delay penalty\n"); + } + else if (fr->h_wire->wt == Low_swing) { + printf("\tWire type - Low swing wires\n"); + } + + printf("\tHorizontal link delay - %g (ns)\n", fr->h_wire->delay * 1e9); + printf("\tVertical link delay - %g (ns)\n", fr->v_wire->delay * 1e9); + printf("\tDelay/length - %g (ns/mm)\n", + fr->h_wire->delay * 1e9 / fr->bank_pda.area.w); + printf("\tHorizontal link energy -dynamic/access %g (nJ)\n" + "\t -leakage %g (nW)\n\n", + fr->h_wire->power.readOp.dynamic * 1e9, + fr->h_wire->power.readOp.leakage * 1e9); + printf("\tVertical link energy -dynamic/access %g (nJ)\n" + "\t -leakage %g (nW)\n\n", + fr->v_wire->power.readOp.dynamic * 1e9, + fr->v_wire->power.readOp.leakage * 1e9); + printf("\n\n"); + fr->v_wire->print_wire(); + printf("\n\nBank stats:\n"); +} + +nuca_org_t *Nuca::find_optimal_nuca(list *n, + min_values_t *minval) { + double cost = 0; + double min_cost = BIGNUM; + nuca_org_t *res = NULL; + float d, a, dp, lp, c; + int v; + dp = g_ip->dynamic_power_wt_nuca; + lp = g_ip->leakage_power_wt_nuca; + a = g_ip->area_wt_nuca; + d = g_ip->delay_wt_nuca; + c = g_ip->cycle_time_wt_nuca; + + list::iterator niter; + + for (niter = n->begin(); niter != n->end(); niter++) { + fprintf(stderr, "\n-----------------------------" + "---------------\n"); + + printf("NUCA___stats %d \tbankcount: lat = %g \tdynP = %g \twt = %d\t " + "bank_dpower = %g \tleak = %g \tcycle = %g\n", + (*niter)->bank_count, (*niter)->nuca_pda.delay, + (*niter)->nuca_pda.power.readOp.dynamic, (*niter)->h_wire->wt, + (*niter)->bank_pda.power.readOp.dynamic, + (*niter)->nuca_pda.power.readOp.leakage, + (*niter)->nuca_pda.cycle_time); + + if (g_ip->ed == 1) { + cost = ((*niter)->nuca_pda.delay / minval->min_delay) * + ((*niter)->nuca_pda.power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + res = ((*niter)); + } + } + else if (g_ip->ed == 2) { + cost = ((*niter)->nuca_pda.delay / minval->min_delay) * + ((*niter)->nuca_pda.delay / minval->min_delay) * + ((*niter)->nuca_pda.power.readOp.dynamic / minval->min_dyn); + if (min_cost > cost) { + min_cost = cost; + res = ((*niter)); + } + } + else { + /* + * check whether the current organization + * meets the input deviation constraints + */ + v = check_nuca_org((*niter), minval); + if (minval->min_leakage == 0) + minval->min_leakage = 0.1; // FIXME remove this after leakage modeling + + if (v) { + cost = + (d * ((*niter)->nuca_pda.delay / minval->min_delay) + + c * ((*niter)->nuca_pda.cycle_time / minval->min_cyc) + + dp * ((*niter)->nuca_pda.power.readOp.dynamic / minval->min_dyn) + + lp * ((*niter)->nuca_pda.power.readOp.leakage / + minval->min_leakage) + + a * ((*niter)->nuca_pda.area.get_area() / minval->min_area)); + fprintf(stderr, "cost = %g\n", cost); + + if (min_cost > cost) { + min_cost = cost; + res = ((*niter)); + } + } + else { + niter = n->erase(niter); + if (niter != n->begin()) + niter--; + } + } + } + return res; +} + +int Nuca::check_nuca_org(nuca_org_t *n, min_values_t *minval) { + if (((n->nuca_pda.delay - minval->min_delay) * 100 / minval->min_delay) > + g_ip->delay_dev_nuca) { + return 0; + } + if (((n->nuca_pda.power.readOp.dynamic - minval->min_dyn) / minval->min_dyn) * + 100 > + g_ip->dynamic_power_dev_nuca) { + return 0; + } + if (((n->nuca_pda.power.readOp.leakage - minval->min_leakage) / + minval->min_leakage) * + 100 > + g_ip->leakage_power_dev_nuca) { + return 0; + } + if (((n->nuca_pda.cycle_time - minval->min_cyc) / minval->min_cyc) * 100 > + g_ip->cycle_time_dev_nuca) { + return 0; + } + if (((n->nuca_pda.area.get_area() - minval->min_area) / minval->min_area) * + 100 > + g_ip->area_dev_nuca) { + return 0; + } + return 1; +} + +void Nuca::calculate_nuca_area(nuca_org_t *nuca) { + nuca->nuca_pda.area.h = + nuca->rows * ((nuca->h_wire->wire_width + nuca->h_wire->wire_spacing) * + nuca->router->flit_size + + nuca->bank_pda.area.h); + + nuca->nuca_pda.area.w = + nuca->columns * ((nuca->v_wire->wire_width + nuca->v_wire->wire_spacing) * + nuca->router->flit_size + + nuca->bank_pda.area.w); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/nuca.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/nuca.h new file mode 100644 index 0000000000..a065f5b931 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/nuca.h @@ -0,0 +1,94 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __NUCA_H__ +#define __NUCA_H__ + +#include +#include "assert.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "io.h" +#include "mat.h" +#include "parameter.h" +#include "router.h" +#include "wire.h" + +namespace cacti { + +class nuca_org_t { + public: + ~nuca_org_t(); + // int size; + /* area, power, access time, and cycle time stats */ + Component nuca_pda; + Component bank_pda; + Component wire_pda; + Wire *h_wire; + Wire *v_wire; + Router *router; + /* for particular network configuration + * calculated based on a cycle accurate + * simulation Ref: CACTI 6 - Tech report + */ + double contention; + + /* grid network stats */ + double avg_hops; + int rows; + int columns; + int bank_count; +}; + +class Nuca : public Component { + public: + Nuca(TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + void print_router(); + ~Nuca(); + void sim_nuca(); + void init_cont(); + int calc_cycles(double lat, double oper_freq); + void calculate_nuca_area(nuca_org_t *nuca); + int check_nuca_org(nuca_org_t *n, min_values_t *minval); + nuca_org_t *find_optimal_nuca(list *n, min_values_t *minval); + void print_nuca(nuca_org_t *n); + void print_cont_stats(); + + private: + TechnologyParameter::DeviceType *deviceType; + int wt_min, wt_max; + Wire *wire_vertical[WIRE_TYPES], *wire_horizontal[WIRE_TYPES]; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/parameter.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/parameter.cc new file mode 100644 index 0000000000..1fb3993a92 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/parameter.cc @@ -0,0 +1,781 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include +#include + +#include "area.h" +#include "parameter.h" + +using namespace std; +using namespace cacti; + +namespace cacti { +InputParameter *g_ip; +TechnologyParameter g_tp; +} // namespace cacti + +void TechnologyParameter::DeviceType::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "C_g_ideal = " << setw(12) << C_g_ideal << " F/um" + << endl; + cout << indent_str << "C_fringe = " << setw(12) << C_fringe << " F/um" + << endl; + cout << indent_str << "C_overlap = " << setw(12) << C_overlap << " F/um" + << endl; + cout << indent_str << "C_junc = " << setw(12) << C_junc << " F/um^2" + << endl; + cout << indent_str << "l_phy = " << setw(12) << l_phy << " um" << endl; + cout << indent_str << "l_elec = " << setw(12) << l_elec << " um" << endl; + cout << indent_str << "R_nch_on = " << setw(12) << R_nch_on << " ohm-um" + << endl; + cout << indent_str << "R_pch_on = " << setw(12) << R_pch_on << " ohm-um" + << endl; + cout << indent_str << "Vdd = " << setw(12) << Vdd << " V" << endl; + cout << indent_str << "Vth = " << setw(12) << Vth << " V" << endl; + cout << indent_str << "Vdd_default = " << setw(12) << Vdd_default << " V" + << endl; + cout << indent_str << "I_on_n = " << setw(12) << I_on_n << " A/um" << endl; + cout << indent_str << "I_on_p = " << setw(12) << I_on_p << " A/um" << endl; + cout << indent_str << "I_off_n = " << setw(12) << I_off_n << " A/um" + << endl; + cout << indent_str << "I_off_p = " << setw(12) << I_off_p << " A/um" + << endl; + cout << indent_str << "C_ox = " << setw(12) << C_ox << " F/um^2" << endl; + cout << indent_str << "t_ox = " << setw(12) << t_ox << " um" << endl; + cout << indent_str + << "n_to_p_eff_curr_drv_ratio = " << n_to_p_eff_curr_drv_ratio << endl; +} + +void TechnologyParameter::InterconnectType::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "pitch = " << setw(12) << pitch << " um" << endl; + cout << indent_str << "R_per_um = " << setw(12) << R_per_um << " ohm/um" + << endl; + cout << indent_str << "C_per_um = " << setw(12) << C_per_um << " F/um" + << endl; +} + +void TechnologyParameter::ScalingFactor::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "logic_scaling_co_eff = " << setw(12) + << logic_scaling_co_eff << endl; + cout << indent_str << "curr_core_tx_density = " << setw(12) << core_tx_density + << " # of tx/um^2" << endl; +} + +void TechnologyParameter::MemoryType::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "b_w = " << setw(12) << b_w << " um" << endl; + cout << indent_str << "b_h = " << setw(12) << b_h << " um" << endl; + cout << indent_str << "cell_a_w = " << setw(12) << cell_a_w << " um" + << endl; + cout << indent_str << "cell_pmos_w = " << setw(12) << cell_pmos_w << " um" + << endl; + cout << indent_str << "cell_nmos_w = " << setw(12) << cell_nmos_w << " um" + << endl; + cout << indent_str << "Vbitpre = " << setw(12) << Vbitpre << " V" << endl; +} + +void TechnologyParameter::display(uint32_t indent) { + string indent_str(indent, ' '); + + cout << indent_str << "ram_wl_stitching_overhead_ = " << setw(12) + << ram_wl_stitching_overhead_ << " um" << endl; + cout << indent_str << "min_w_nmos_ = " << setw(12) + << min_w_nmos_ << " um" << endl; + cout << indent_str << "max_w_nmos_ = " << setw(12) + << max_w_nmos_ << " um" << endl; + cout << indent_str << "unit_len_wire_del = " << setw(12) + << unit_len_wire_del << " s/um^2" << endl; + cout << indent_str << "FO4 = " << setw(12) << FO4 + << " s" << endl; + cout << indent_str << "kinv = " << setw(12) << kinv + << " s" << endl; + cout << indent_str << "vpp = " << setw(12) << vpp + << " V" << endl; + cout << indent_str << "w_sense_en = " << setw(12) + << w_sense_en << " um" << endl; + cout << indent_str << "w_sense_n = " << setw(12) << w_sense_n + << " um" << endl; + cout << indent_str << "w_sense_p = " << setw(12) << w_sense_p + << " um" << endl; + cout << indent_str << "w_iso = " << setw(12) << w_iso + << " um" << endl; + cout << indent_str << "w_poly_contact = " << setw(12) + << w_poly_contact << " um" << endl; + cout << indent_str << "spacing_poly_to_poly = " << setw(12) + << spacing_poly_to_poly << " um" << endl; + cout << indent_str << "spacing_poly_to_contact = " << setw(12) + << spacing_poly_to_contact << " um" << endl; + cout << endl; + cout << indent_str << "w_comp_inv_p1 = " << setw(12) + << w_comp_inv_p1 << " um" << endl; + cout << indent_str << "w_comp_inv_p2 = " << setw(12) + << w_comp_inv_p2 << " um" << endl; + cout << indent_str << "w_comp_inv_p3 = " << setw(12) + << w_comp_inv_p3 << " um" << endl; + cout << indent_str << "w_comp_inv_n1 = " << setw(12) + << w_comp_inv_n1 << " um" << endl; + cout << indent_str << "w_comp_inv_n2 = " << setw(12) + << w_comp_inv_n2 << " um" << endl; + cout << indent_str << "w_comp_inv_n3 = " << setw(12) + << w_comp_inv_n3 << " um" << endl; + cout << indent_str << "w_eval_inv_p = " << setw(12) + << w_eval_inv_p << " um" << endl; + cout << indent_str << "w_eval_inv_n = " << setw(12) + << w_eval_inv_n << " um" << endl; + cout << indent_str << "w_comp_n = " << setw(12) << w_comp_n + << " um" << endl; + cout << indent_str << "w_comp_p = " << setw(12) << w_comp_p + << " um" << endl; + cout << endl; + cout << indent_str << "dram_cell_I_on = " << setw(12) + << dram_cell_I_on << " A/um" << endl; + cout << indent_str << "dram_cell_Vdd = " << setw(12) + << dram_cell_Vdd << " V" << endl; + cout << indent_str << "dram_cell_I_off_worst_case_len_temp = " << setw(12) + << dram_cell_I_off_worst_case_len_temp << " A/um" << endl; + cout << indent_str << "dram_cell_C = " << setw(12) + << dram_cell_C << " F" << endl; + cout << indent_str << "gm_sense_amp_latch = " << setw(12) + << gm_sense_amp_latch << " F/s" << endl; + cout << endl; + cout << indent_str << "w_nmos_b_mux = " << setw(12) + << w_nmos_b_mux << " um" << endl; + cout << indent_str << "w_nmos_sa_mux = " << setw(12) + << w_nmos_sa_mux << " um" << endl; + cout << indent_str << "w_pmos_bl_precharge = " << setw(12) + << w_pmos_bl_precharge << " um" << endl; + cout << indent_str << "w_pmos_bl_eq = " << setw(12) + << w_pmos_bl_eq << " um" << endl; + cout << indent_str << "MIN_GAP_BET_P_AND_N_DIFFS = " << setw(12) + << MIN_GAP_BET_P_AND_N_DIFFS << " um" << endl; + cout << indent_str << "HPOWERRAIL = " << setw(12) + << HPOWERRAIL << " um" << endl; + cout << indent_str << "cell_h_def = " << setw(12) + << cell_h_def << " um" << endl; + + cout << endl; + cout << indent_str << "SRAM cell transistor: " << endl; + sram_cell.display(indent + 2); + + cout << endl; + cout << indent_str << "DRAM access transistor: " << endl; + dram_acc.display(indent + 2); + + cout << endl; + cout << indent_str << "DRAM wordline transistor: " << endl; + dram_wl.display(indent + 2); + + cout << endl; + cout << indent_str << "peripheral global transistor: " << endl; + peri_global.display(indent + 2); + + cout << endl; + cout << indent_str << "wire local" << endl; + wire_local.display(indent + 2); + + cout << endl; + cout << indent_str << "wire inside mat" << endl; + wire_inside_mat.display(indent + 2); + + cout << endl; + cout << indent_str << "wire outside mat" << endl; + wire_outside_mat.display(indent + 2); + + cout << endl; + cout << indent_str << "SRAM" << endl; + sram.display(indent + 2); + + cout << endl; + cout << indent_str << "DRAM" << endl; + dram.display(indent + 2); +} + +DynamicParameter::DynamicParameter() + : use_inp_params(0), cell(), is_valid(true) {} + +DynamicParameter::DynamicParameter(bool is_tag_, int pure_ram_, int pure_cam_, + double Nspd_, unsigned int Ndwl_, + unsigned int Ndbl_, unsigned int Ndcm_, + unsigned int Ndsam_lev_1_, + unsigned int Ndsam_lev_2_, bool is_main_mem_) + : is_tag(is_tag_), + pure_ram(pure_ram_), + pure_cam(pure_cam_), + tagbits(0), + Nspd(Nspd_), + Ndwl(Ndwl_), + Ndbl(Ndbl_), + Ndcm(Ndcm_), + Ndsam_lev_1(Ndsam_lev_1_), + Ndsam_lev_2(Ndsam_lev_2_), + number_way_select_signals_mat(0), + V_b_sense(0), + use_inp_params(0), + is_main_mem(is_main_mem_), + cell(), + is_valid(false) { + ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type + : g_ip->data_arr_ram_cell_tech_type; + is_dram = + ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram)); + + unsigned int capacity_per_die = + g_ip->cache_sz / + NUMBER_STACKED_DIE_LAYERS; // capacity per stacked die layer + const TechnologyParameter::InterconnectType &wire_local = g_tp.wire_local; + fully_assoc = (g_ip->fully_assoc) ? true : false; + + if (fully_assoc || + pure_cam) { // fully-assocative cache -- ref: CACTi 2.0 report + if (Ndwl != 1 || // Ndwl is fixed to 1 for FA + Ndcm != 1 || // Ndcm is fixed to 1 for FA + Nspd < 1 || Nspd > 1 || // Nspd is fixed to 1 for FA + Ndsam_lev_1 != 1 || // Ndsam_lev_1 is fixed to one + Ndsam_lev_2 != 1 || // Ndsam_lev_2 is fixed to one + Ndbl < 2) { + return; + } + } + + if ((is_dram) && (!is_tag) && (Ndcm > 1)) { + return; // For a DRAM array, each bitline has its own sense-amp + } + + // If it's not an FA tag/data array, Ndwl should be at least two and Ndbl + // should be at least two because an array is assumed to have at least one + // mat. And a mat is formed out of two horizontal subarrays and two vertical + // subarrays + if (fully_assoc == false && (Ndwl < 1 || Ndbl < 1)) { + return; + } + + //***********compute row, col of an subarray + if (!(fully_assoc || pure_cam)) // Not fully_asso nor cam + { + // if data array, let tagbits = 0 + if (is_tag) { + if (g_ip->specific_tag) { + tagbits = g_ip->tag_w; + } + else { + tagbits = ADDRESS_BITS + EXTRA_TAG_BITS - _log2(capacity_per_die) + + _log2(g_ip->tag_assoc * 2 - 1) - _log2(g_ip->nbanks); + } + tagbits = (((tagbits + 3) >> 2) << 2); + + num_r_subarray = (int)ceil( + capacity_per_die / (g_ip->nbanks * g_ip->block_sz * g_ip->tag_assoc * + Ndbl * Nspd)); // + EPSILON); + num_c_subarray = + (int)ceil((tagbits * g_ip->tag_assoc * Nspd / Ndwl)); // + EPSILON); + // burst_length = 1; + } + else { + num_r_subarray = (int)ceil( + capacity_per_die / (g_ip->nbanks * g_ip->block_sz * g_ip->data_assoc * + Ndbl * Nspd)); // + EPSILON); + num_c_subarray = (int)ceil((8 * g_ip->block_sz * g_ip->data_assoc * Nspd / + Ndwl)); // + EPSILON); + EPSILON); + // burst_length = g_ip->block_sz * 8 / g_ip->out_w; + } + + if (num_r_subarray < MINSUBARRAYROWS) + return; + if (num_r_subarray == 0) + return; + if (num_r_subarray > MAXSUBARRAYROWS) + return; + if (num_c_subarray < MINSUBARRAYCOLS) + return; + if (num_c_subarray > MAXSUBARRAYCOLS) + return; + } + + else { // either fully-asso or cam + if (pure_cam) { + if (g_ip->specific_tag) { + tagbits = int(ceil(g_ip->tag_w / 8.0) * 8); + } + else { + tagbits = int(ceil((ADDRESS_BITS + EXTRA_TAG_BITS) / 8.0) * 8); + // cout<<"Pure CAM needs tag width to be + // specified"<> 2) << 2); + + tag_num_r_subarray = (int)ceil(capacity_per_die / + (g_ip->nbanks * tagbits / 8.0 * + Ndbl)); // TODO: error check input of + // tagbits and blocksize //TODO: + // for pure CAM, g_ip->block + // should be number of entries. + // tag_num_c_subarray = (int)(tagbits + EPSILON); + tag_num_c_subarray = tagbits; + if (tag_num_r_subarray == 0) + return; + if (tag_num_r_subarray > MAXSUBARRAYROWS) + return; + if (tag_num_c_subarray < MINSUBARRAYCOLS) + return; + if (tag_num_c_subarray > MAXSUBARRAYCOLS) + return; + num_r_subarray = tag_num_r_subarray; + } + else // fully associative + { + if (g_ip->specific_tag) { + tagbits = g_ip->tag_w; + } + else { + tagbits = ADDRESS_BITS + EXTRA_TAG_BITS - + _log2(g_ip->block_sz); // TODO: should be the + // page_offset=log2(page size), but + // this info is not avail with CACTI, + // for McPAT this is no problem. + } + tagbits = (((tagbits + 3) >> 2) << 2); + + tag_num_r_subarray = + (int)(capacity_per_die / (g_ip->nbanks * g_ip->block_sz * Ndbl)); + tag_num_c_subarray = (int)ceil((tagbits * Nspd / Ndwl)); // + EPSILON); + if (tag_num_r_subarray == 0) + return; + if (tag_num_r_subarray > MAXSUBARRAYROWS) + return; + if (tag_num_c_subarray < MINSUBARRAYCOLS) + return; + if (tag_num_c_subarray > MAXSUBARRAYCOLS) + return; + + data_num_r_subarray = tag_num_r_subarray; + data_num_c_subarray = 8 * g_ip->block_sz; + if (data_num_r_subarray == 0) + return; + if (data_num_r_subarray > MAXSUBARRAYROWS) + return; + if (data_num_c_subarray < MINSUBARRAYCOLS) + return; + if (data_num_c_subarray > MAXSUBARRAYCOLS) + return; + num_r_subarray = tag_num_r_subarray; + } + } + + num_subarrays = Ndwl * Ndbl; + //****************end of computation of row, col of an subarray + + // calculate wire parameters + if (fully_assoc || pure_cam) { + cam_cell.h = + g_tp.cam.b_h + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + g_ip->num_rd_ports + g_ip->num_wr_ports) + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) + + wire_local.pitch * g_ip->num_se_rd_ports; + cam_cell.w = + g_tp.cam.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + g_ip->num_rd_ports + g_ip->num_wr_ports) + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) + + wire_local.pitch * g_ip->num_se_rd_ports; + + cell.h = + g_tp.sram.b_h + + 2 * wire_local.pitch * + (g_ip->num_wr_ports + g_ip->num_rw_ports - 1 + g_ip->num_rd_ports) + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1); + cell.w = g_tp.sram.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + + (g_ip->num_rd_ports - g_ip->num_se_rd_ports) + + g_ip->num_wr_ports) + + g_tp.wire_local.pitch * g_ip->num_se_rd_ports + + 2 * wire_local.pitch * (g_ip->num_search_ports - 1); + } + else { + if (is_tag) { + cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + + g_ip->num_rd_ports + g_ip->num_wr_ports); + cell.w = g_tp.sram.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + g_ip->num_wr_ports + + (g_ip->num_rd_ports - g_ip->num_se_rd_ports)) + + wire_local.pitch * g_ip->num_se_rd_ports; + } + else { + if (is_dram) { + cell.h = g_tp.dram.b_h; + cell.w = g_tp.dram.b_w; + } + else { + cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * + (g_ip->num_wr_ports + g_ip->num_rw_ports - + 1 + g_ip->num_rd_ports); + cell.w = g_tp.sram.b_w + + 2 * wire_local.pitch * + (g_ip->num_rw_ports - 1 + + (g_ip->num_rd_ports - g_ip->num_se_rd_ports) + + g_ip->num_wr_ports) + + g_tp.wire_local.pitch * g_ip->num_se_rd_ports; + } + } + } + + double c_b_metal = cell.h * wire_local.C_per_um; + double C_bl; + + if (!(fully_assoc || pure_cam)) { + if (is_dram) { + deg_bl_muxing = 1; + if (ram_cell_tech_type == comm_dram) { + C_bl = num_r_subarray * c_b_metal; + V_b_sense = (g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_C / + (g_tp.dram_cell_C + C_bl); + if (V_b_sense < VBITSENSEMIN) { + return; + } + V_b_sense = VBITSENSEMIN; // in any case, we fix sense amp input signal + // to a constant value + dram_refresh_period = 64e-3; + } + else { + double Cbitrow_drain_cap = + drain_C_(g_tp.dram.cell_a_w, NCH, 1, 0, cell.w, true, true) / 2.0; + C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); + V_b_sense = (g_tp.dram_cell_Vdd / 2) * g_tp.dram_cell_C / + (g_tp.dram_cell_C + C_bl); + + if (V_b_sense < VBITSENSEMIN) { + return; // Sense amp input signal is smaller that minimum allowable + // sense amp input signal + } + V_b_sense = VBITSENSEMIN; // in any case, we fix sense amp input signal + // to a constant value + // v_storage_worst = g_tp.dram_cell_Vdd / 2 - VBITSENSEMIN * + // (g_tp.dram_cell_C + C_bl) / g_tp.dram_cell_C; dram_refresh_period + // = 1.1 * g_tp.dram_cell_C * v_storage_worst / + // g_tp.dram_cell_I_off_worst_case_len_temp; + dram_refresh_period = + 0.9 * g_tp.dram_cell_C * VDD_STORAGE_LOSS_FRACTION_WORST * + g_tp.dram_cell_Vdd / g_tp.dram_cell_I_off_worst_case_len_temp; + } + } + else { // SRAM + V_b_sense = (0.05 * g_tp.sram_cell.Vdd > VBITSENSEMIN) + ? 0.05 * g_tp.sram_cell.Vdd + : VBITSENSEMIN; + deg_bl_muxing = Ndcm; + // "/ 2.0" below is due to the fact that two adjacent access transistors + // share drain contacts in a physical layout + double Cbitrow_drain_cap = + drain_C_(g_tp.sram.cell_a_w, NCH, 1, 0, cell.w, false, true) / 2.0; + C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); + dram_refresh_period = 0; + } + } + else { + c_b_metal = cam_cell.h * wire_local.C_per_um; // IBM and SUN design, SRAM + // array uses dummy cells to + // fill the blank space due + // to mismatch on CAM-RAM + V_b_sense = (0.05 * g_tp.sram_cell.Vdd > VBITSENSEMIN) + ? 0.05 * g_tp.sram_cell.Vdd + : VBITSENSEMIN; + deg_bl_muxing = 1; // FA fix as 1 + // "/ 2.0" below is due to the fact that two adjacent access transistors + // share drain contacts in a physical layout + double Cbitrow_drain_cap = + drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / + 2.0; // TODO: comment out these two lines + C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); + dram_refresh_period = 0; + } + + // do/di: data in/out, for fully associative they are the data width for + // normal read and write so/si: search data in/out, for fully associative they + // are the data width for the search ops for CAM, si=di, but so = matching + // address. do = data out = di (for normal read/write) so/si needs broadcase + // while do/di do not + + if (fully_assoc || pure_cam) { + switch (Ndbl) { + case (0): + cout << " Invalid Ndbl \n" << endl; + exit(0); + break; + case (1): + num_mats_h_dir = 1; // one subarray per mat + num_mats_v_dir = 1; + break; + case (2): + num_mats_h_dir = 1; // two subarrays per mat + num_mats_v_dir = 1; + break; + default: + num_mats_h_dir = int(floor(sqrt(Ndbl / 4.0))); // 4 subbarrys per mat + num_mats_v_dir = int(Ndbl / 4.0 / num_mats_h_dir); + } + num_mats = num_mats_h_dir * num_mats_v_dir; + + if (fully_assoc) { + num_so_b_mat = data_num_c_subarray; + num_do_b_mat = data_num_c_subarray + tagbits; + } + else { + num_so_b_mat = int( + ceil(log2(num_r_subarray)) + + ceil(log2(num_subarrays))); // the address contains the matched data + num_do_b_mat = tagbits; + } + } + else { + num_mats_h_dir = MAX(Ndwl / 2, 1); + num_mats_v_dir = MAX(Ndbl / 2, 1); + num_mats = num_mats_h_dir * num_mats_v_dir; + num_do_b_mat = MAX((num_subarrays / num_mats) * num_c_subarray / + (deg_bl_muxing * Ndsam_lev_1 * Ndsam_lev_2), + 1); + } + + if (!(fully_assoc || pure_cam) && + (num_do_b_mat < (num_subarrays / num_mats))) { + return; + } + + int deg_sa_mux_l1_non_assoc; + // TODO:the i/o for subbank is not necessary and should be removed. + if (!(fully_assoc || pure_cam)) { + if (!is_tag) { + if (is_main_mem == true) { + num_do_b_subbank = g_ip->int_prefetch_w * g_ip->out_w; + deg_sa_mux_l1_non_assoc = Ndsam_lev_1; + } + else { + if (g_ip->fast_access == true) { + num_do_b_subbank = g_ip->out_w * g_ip->data_assoc; + deg_sa_mux_l1_non_assoc = Ndsam_lev_1; + } + else { + num_do_b_subbank = g_ip->out_w; + deg_sa_mux_l1_non_assoc = Ndsam_lev_1 / g_ip->data_assoc; + if (deg_sa_mux_l1_non_assoc < 1) { + return; + } + } + } + } + else { + num_do_b_subbank = tagbits * g_ip->tag_assoc; + if (num_do_b_mat < tagbits) { + return; + } + deg_sa_mux_l1_non_assoc = Ndsam_lev_1; + // num_do_b_mat = g_ip->tag_assoc / num_mats_h_dir; + } + } + else { + if (fully_assoc) { + num_so_b_subbank = 8 * g_ip->block_sz; // TODO:internal perfetch should + // be considered also for fa + num_do_b_subbank = num_so_b_subbank + tag_num_c_subarray; + } + else { + num_so_b_subbank = int( + ceil(log2(num_r_subarray)) + + ceil(log2(num_subarrays))); // the address contains the matched data + num_do_b_subbank = tag_num_c_subarray; + } + + deg_sa_mux_l1_non_assoc = 1; + } + + deg_senseamp_muxing_non_associativity = deg_sa_mux_l1_non_assoc; + + if (fully_assoc || pure_cam) { + num_act_mats_hor_dir = 1; + num_act_mats_hor_dir_sl = num_mats_h_dir; // TODO: this is unnecessary, + // since search op, num_mats is + // used + } + else { + num_act_mats_hor_dir = num_do_b_subbank / num_do_b_mat; + if (num_act_mats_hor_dir == 0) { + return; + } + } + + // compute num_do_mat for tag + if (is_tag) { + if (!(fully_assoc || pure_cam)) { + num_do_b_mat = g_ip->tag_assoc / num_act_mats_hor_dir; + num_do_b_subbank = num_act_mats_hor_dir * num_do_b_mat; + } + } + + if ((g_ip->is_cache == false && is_main_mem == true) || + (PAGE_MODE == 1 && is_dram)) { + if (num_act_mats_hor_dir * num_do_b_mat * Ndsam_lev_1 * Ndsam_lev_2 != + (int)g_ip->page_sz_bits) { + return; + } + } + + // if (is_tag == false && g_ip->is_cache == true && !fully_assoc && !pure_cam + // && //TODO: TODO burst transfer should also apply to RAM arrays + if (is_tag == false && g_ip->is_main_mem == true && + num_act_mats_hor_dir * num_do_b_mat * Ndsam_lev_1 * Ndsam_lev_2 < + ((int)g_ip->out_w * (int)g_ip->burst_len * (int)g_ip->data_assoc)) { + return; + } + + if (num_act_mats_hor_dir > num_mats_h_dir) { + return; + } + + // compute di for mat subbank and bank + if (!(fully_assoc || pure_cam)) { + if (!is_tag) { + if (g_ip->fast_access == true) { + num_di_b_mat = num_do_b_mat / g_ip->data_assoc; + } + else { + num_di_b_mat = num_do_b_mat; + } + } + else { + num_di_b_mat = tagbits; + } + } + else { + if (fully_assoc) { + num_di_b_mat = num_do_b_mat; + //*num_subarrays/num_mats; bits per mat of CAM/FA is as same as cache, + // but inside the mat wire tracks need to be reserved for search data bus + num_si_b_mat = tagbits; + } + else { + num_di_b_mat = tagbits; + num_si_b_mat = tagbits; //*num_subarrays/num_mats; + } + } + + num_di_b_subbank = + num_di_b_mat * num_act_mats_hor_dir; // normal cache or normal r/w for FA + num_si_b_subbank = + num_si_b_mat; //* num_act_mats_hor_dir_sl; inside the data is broadcast + + int num_addr_b_row_dec = _log2(num_r_subarray); + if ((fully_assoc || pure_cam)) + num_addr_b_row_dec += _log2(num_subarrays / num_mats); + int number_subbanks = num_mats / num_act_mats_hor_dir; + number_subbanks_decode = _log2( + number_subbanks); // TODO: add log2(num_subarray_per_bank) to FA/CAM + + num_rw_ports = g_ip->num_rw_ports; + num_rd_ports = g_ip->num_rd_ports; + num_wr_ports = g_ip->num_wr_ports; + num_se_rd_ports = g_ip->num_se_rd_ports; + num_search_ports = g_ip->num_search_ports; + + if (is_dram && is_main_mem) { + number_addr_bits_mat = + MAX((unsigned int)num_addr_b_row_dec, + _log2(deg_bl_muxing) + _log2(deg_sa_mux_l1_non_assoc) + + _log2(Ndsam_lev_2)); + } + else { + number_addr_bits_mat = num_addr_b_row_dec + _log2(deg_bl_muxing) + + _log2(deg_sa_mux_l1_non_assoc) + _log2(Ndsam_lev_2); + } + + if (!(fully_assoc || pure_cam)) { + if (is_tag) { + num_di_b_bank_per_port = tagbits; + num_do_b_bank_per_port = g_ip->data_assoc; + } + else { + num_di_b_bank_per_port = g_ip->out_w + g_ip->data_assoc; + num_do_b_bank_per_port = g_ip->out_w; + } + } + else { + if (fully_assoc) { + num_di_b_bank_per_port = + g_ip->out_w + tagbits; // TODO: out_w or block_sz? + num_si_b_bank_per_port = tagbits; + num_do_b_bank_per_port = g_ip->out_w + tagbits; + num_so_b_bank_per_port = g_ip->out_w; + } + else { + num_di_b_bank_per_port = tagbits; + num_si_b_bank_per_port = tagbits; + num_do_b_bank_per_port = tagbits; + num_so_b_bank_per_port = + int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays))); + } + } + + if ((!is_tag) && (g_ip->data_assoc > 1) && (!g_ip->fast_access)) { + number_way_select_signals_mat = g_ip->data_assoc; + } + + // add ECC adjustment to all data signals that traverse on H-trees. + if (g_ip->add_ecc_b_ == true) { + num_do_b_mat += (int)(ceil(num_do_b_mat / num_bits_per_ecc_b_)); + num_di_b_mat += (int)(ceil(num_di_b_mat / num_bits_per_ecc_b_)); + num_di_b_subbank += (int)(ceil(num_di_b_subbank / num_bits_per_ecc_b_)); + num_do_b_subbank += (int)(ceil(num_do_b_subbank / num_bits_per_ecc_b_)); + num_di_b_bank_per_port += + (int)(ceil(num_di_b_bank_per_port / num_bits_per_ecc_b_)); + num_do_b_bank_per_port += + (int)(ceil(num_do_b_bank_per_port / num_bits_per_ecc_b_)); + + num_so_b_mat += (int)(ceil(num_so_b_mat / num_bits_per_ecc_b_)); + num_si_b_mat += (int)(ceil(num_si_b_mat / num_bits_per_ecc_b_)); + num_si_b_subbank += (int)(ceil(num_si_b_subbank / num_bits_per_ecc_b_)); + num_so_b_subbank += (int)(ceil(num_so_b_subbank / num_bits_per_ecc_b_)); + num_si_b_bank_per_port += + (int)(ceil(num_si_b_bank_per_port / num_bits_per_ecc_b_)); + num_so_b_bank_per_port += + (int)(ceil(num_so_b_bank_per_port / num_bits_per_ecc_b_)); + } + + is_valid = true; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/parameter.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/parameter.h new file mode 100644 index 0000000000..4d0b426bab --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/parameter.h @@ -0,0 +1,391 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __PARAMETER_H__ +#define __PARAMETER_H__ + +#include "area.h" +#include "cacti_interface.h" +#include "const.h" +#include "io.h" + +namespace cacti { + +// parameters which are functions of certain device technology +class TechnologyParameter { + public: + class DeviceType { + public: + double C_g_ideal; + double C_fringe; + double C_overlap; + double C_junc; // C_junc_area + double C_junc_sidewall; + double l_phy; + double l_elec; + double R_nch_on; + double R_pch_on; + double Vdd; + double Vdd_default; + double Vth; + double Vcc_min_default; // allowed min vcc; for memory cell it is the + // lowest vcc for data retention. for logic it is + // the vcc to balance the leakage reduction and + // wakeup latency; This is the value constrained by + // the IC technology and cannot by changed by + // external/user voltage supply + double Vcc_min; // same meaning as Vcc_min_default, however, this value is + // set by user, once it is lower than Vcc_min_default; + // circuit (e.g. SRAM cells) cannot retain state. + double I_on_n; + double I_on_p; + double I_off_n; + double I_off_p; + double I_g_on_n; + double I_g_on_p; + double C_ox; + double t_ox; + double n_to_p_eff_curr_drv_ratio; + double long_channel_leakage_reduction; + double Mobility_n; + + DeviceType() + : C_g_ideal(0), + C_fringe(0), + C_overlap(0), + C_junc(0), + C_junc_sidewall(0), + l_phy(0), + l_elec(0), + R_nch_on(0), + R_pch_on(0), + Vdd(0), + Vdd_default(0), + Vth(0), + Vcc_min(0), + I_on_n(0), + I_on_p(0), + I_off_n(0), + I_off_p(0), + I_g_on_n(0), + I_g_on_p(0), + C_ox(0), + t_ox(0), + n_to_p_eff_curr_drv_ratio(0), + long_channel_leakage_reduction(0), + Mobility_n(0){}; + void reset() { + C_g_ideal = 0; + C_fringe = 0; + C_overlap = 0; + C_junc = 0; + l_phy = 0; + l_elec = 0; + R_nch_on = 0; + R_pch_on = 0; + Vdd = 0; + Vdd_default = 0; + Vth = 0; + Vcc_min_default = 0; + Vcc_min = 0; + I_on_n = 0; + I_on_p = 0; + I_off_n = 0; + I_off_p = 0; + I_g_on_n = 0; + I_g_on_p = 0; + C_ox = 0; + t_ox = 0; + n_to_p_eff_curr_drv_ratio = 0; + long_channel_leakage_reduction = 0; + Mobility_n = 0; + } + + void display(uint32_t indent = 0); + }; + class InterconnectType { + public: + double pitch; + double R_per_um; + double C_per_um; + double horiz_dielectric_constant; + double vert_dielectric_constant; + double aspect_ratio; + double miller_value; + double ild_thickness; + + InterconnectType() : pitch(0), R_per_um(0), C_per_um(0){}; + + void reset() { + pitch = 0; + R_per_um = 0; + C_per_um = 0; + horiz_dielectric_constant = 0; + vert_dielectric_constant = 0; + aspect_ratio = 0; + miller_value = 0; + ild_thickness = 0; + } + + void display(uint32_t indent = 0); + }; + class MemoryType { + public: + double b_w; + double b_h; + double cell_a_w; + double cell_pmos_w; + double cell_nmos_w; + double Vbitpre; + double Vbitfloating; // voltage when floating bitline is supported + + void reset() { + b_w = 0; + b_h = 0; + cell_a_w = 0; + cell_pmos_w = 0; + cell_nmos_w = 0; + Vbitpre = 0; + Vbitfloating = 0; + } + + void display(uint32_t indent = 0); + }; + + class ScalingFactor { + public: + double logic_scaling_co_eff; + double core_tx_density; + double long_channel_leakage_reduction; + + ScalingFactor() + : logic_scaling_co_eff(0), + core_tx_density(0), + long_channel_leakage_reduction(0){}; + + void reset() { + logic_scaling_co_eff = 0; + core_tx_density = 0; + long_channel_leakage_reduction = 0; + } + + void display(uint32_t indent = 0); + }; + + double ram_wl_stitching_overhead_; + double min_w_nmos_; + double max_w_nmos_; + double max_w_nmos_dec; + double unit_len_wire_del; + double FO4; + double kinv; + double vpp; + double w_sense_en; + double w_sense_n; + double w_sense_p; + double sense_delay; + double sense_dy_power; + double w_iso; + double w_poly_contact; + double spacing_poly_to_poly; + double spacing_poly_to_contact; + + double w_comp_inv_p1; + double w_comp_inv_p2; + double w_comp_inv_p3; + double w_comp_inv_n1; + double w_comp_inv_n2; + double w_comp_inv_n3; + double w_eval_inv_p; + double w_eval_inv_n; + double w_comp_n; + double w_comp_p; + + double dram_cell_I_on; + double dram_cell_Vdd; + double dram_cell_I_off_worst_case_len_temp; + double dram_cell_C; + double gm_sense_amp_latch; + + double w_nmos_b_mux; + double w_nmos_sa_mux; + double w_pmos_bl_precharge; + double w_pmos_bl_eq; + double MIN_GAP_BET_P_AND_N_DIFFS; + double MIN_GAP_BET_SAME_TYPE_DIFFS; + double HPOWERRAIL; + double cell_h_def; + + double chip_layout_overhead; + double macro_layout_overhead; + double sckt_co_eff; + + double fringe_cap; + + uint64_t h_dec; + + DeviceType sram_cell; // SRAM cell transistor + DeviceType dram_acc; // DRAM access transistor + DeviceType dram_wl; // DRAM wordline transistor + DeviceType peri_global; // peripheral global + DeviceType cam_cell; // SRAM cell transistor + + DeviceType sleep_tx; // Sleep transistor cell transistor + + InterconnectType wire_local; + InterconnectType wire_inside_mat; + InterconnectType wire_outside_mat; + + ScalingFactor scaling_factor; + + MemoryType sram; + MemoryType dram; + MemoryType cam; + + void display(uint32_t indent = 0); + + void reset() { + dram_cell_Vdd = 0; + dram_cell_I_on = 0; + dram_cell_C = 0; + vpp = 0; + + sense_delay = 0; + sense_dy_power = 0; + fringe_cap = 0; + // horiz_dielectric_constant = 0; + // vert_dielectric_constant = 0; + // aspect_ratio = 0; + // miller_value = 0; + // ild_thickness = 0; + + dram_cell_I_off_worst_case_len_temp = 0; + + sram_cell.reset(); + dram_acc.reset(); + dram_wl.reset(); + peri_global.reset(); + cam_cell.reset(); + sleep_tx.reset(); + + scaling_factor.reset(); + + wire_local.reset(); + wire_inside_mat.reset(); + wire_outside_mat.reset(); + + sram.reset(); + dram.reset(); + cam.reset(); + + chip_layout_overhead = 0; + macro_layout_overhead = 0; + sckt_co_eff = 0; + } +}; + +class DynamicParameter { + public: + bool is_tag; + bool pure_ram; + bool pure_cam; + bool fully_assoc; + int tagbits; + int num_subarrays; // only for leakage computation -- the number of + // subarrays per bank + int num_mats; // only for leakage computation -- the number of mats per bank + double Nspd; + int Ndwl; + int Ndbl; + int Ndcm; + int deg_bl_muxing; + int deg_senseamp_muxing_non_associativity; + int Ndsam_lev_1; + int Ndsam_lev_2; + int number_addr_bits_mat; // per port + int number_subbanks_decode; // per_port + int num_di_b_bank_per_port; + int num_do_b_bank_per_port; + int num_di_b_mat; + int num_do_b_mat; + int num_di_b_subbank; + int num_do_b_subbank; + + int num_si_b_mat; + int num_so_b_mat; + int num_si_b_subbank; + int num_so_b_subbank; + int num_si_b_bank_per_port; + int num_so_b_bank_per_port; + + int number_way_select_signals_mat; + int num_act_mats_hor_dir; + + int num_act_mats_hor_dir_sl; + bool is_dram; + double V_b_sense; + unsigned int num_r_subarray; + unsigned int num_c_subarray; + int tag_num_r_subarray; // sheng: fully associative cache tag and data must + // be computed together, data and tag must be + // separate + int tag_num_c_subarray; + int data_num_r_subarray; + int data_num_c_subarray; + int num_mats_h_dir; + int num_mats_v_dir; + uint32_t ram_cell_tech_type; + double dram_refresh_period; + + DynamicParameter(); + DynamicParameter(bool is_tag_, int pure_ram_, int pure_cam_, double Nspd_, + unsigned int Ndwl_, unsigned int Ndbl_, unsigned int Ndcm_, + unsigned int Ndsam_lev_1_, unsigned int Ndsam_lev_2_, + bool is_main_mem_); + + int use_inp_params; + unsigned int num_rw_ports; + unsigned int num_rd_ports; + unsigned int num_wr_ports; + unsigned int num_se_rd_ports; // number of single ended read ports + unsigned int num_search_ports; + unsigned int out_w; // == nr_bits_out + bool is_main_mem; + Area cell, cam_cell; // cell is the sram_cell in both nomal cache/ram and FA. + bool is_valid; +}; + +extern InputParameter *g_ip; +extern TechnologyParameter g_tp; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/powergating.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/powergating.cc new file mode 100644 index 0000000000..de39bf37d3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/powergating.cc @@ -0,0 +1,163 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "powergating.h" +#include +#include +#include +#include "area.h" +#include "parameter.h" + +using namespace std; +using namespace cacti; + +/* + * Sizing of sleep tx is independent of sleep/power-saving supply voltage, + * sleep/power-saving supply voltage only affects wake-up energy and time + * + * While using DSTN (Distributed sleep tx network), worst case sizing is used. + * For DSTN, the network can help to reduce the runtime latency (or achieve the + * same latency with smaller transistor size) For example, during write access, + * if not all bits are toggled, the sleep tx in the non-toggled path can work as + * the extra discharge paths of all the toggled bits, in addition to the sleep + * tx in the bitlines with the toggled bits. Since CACTI itself assumes worst + * case with all bits toggled, sleep txs are assumed to work all the time with + * all bits toggled, Therefore, although DTSN is used, for memory array, the + * number of sleep txs is related to the number of rows and cols., and all + * calculations are still base on single sleep tx for each discharge case. Of + * couse in each discharge path, the sleep tx is the charge path of all the + * devices in the same path (row or col). + * + * Even in the worse case sizing, the wakeup time will not change + * since all paths need to charge/discharge---each sleep tx is just do its own + * portion of the work during wakeup or entering sleep state. + * + * Power-gating and DVS cannot happen at the same time! Because power-gating + * happens when circuit is idle, while DVS happens when circuit is active. When + * waking up from power-gating status, it is assumed that the system will first + * wakeup to DVS0 (full speed) state, if DVS is enabled in the system. + * + * + * + */ +Sleep_tx::Sleep_tx(double _perf_with_sleep_tx, + double _active_Isat, // of circuit block, not sleep tx + bool _is_footer, double _c_circuit_wakeup, double _V_delta, + int _num_sleep_tx, + // double _vt_circuit, + // double _vt_sleep_tx, + // double _mobility,//of sleep tx + // double _c_ox,//of sleep tx + const Area &cell_) + : perf_with_sleep_tx(_perf_with_sleep_tx), + active_Isat(_active_Isat), + is_footer(_is_footer), + num_sleep_tx(_num_sleep_tx), + c_circuit_wakeup(_c_circuit_wakeup), + // vt_circuit(_vt_circuit), + // vt_sleep_tx(_vt_sleep_tx), + // mobility(_mobility), + // c_ox(_c_ox) + cell(cell_), + is_sleep_tx(true), + V_delta(_V_delta) { + // a single sleep tx in a network + double raw_area, raw_width, raw_hight; + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(false, false, true); + vdd = g_tp.peri_global.Vdd; + vt_circuit = g_tp.peri_global.Vth; + vt_sleep_tx = g_tp.sleep_tx.Vth; + mobility = g_tp.sleep_tx.Mobility_n; + c_ox = g_tp.sleep_tx.C_ox; + + width = active_Isat / + (perf_with_sleep_tx * mobility * c_ox * (vdd - vt_circuit) * + (vdd - vt_sleep_tx)) * + g_ip->F_sz_um; // W/L uses physical numbers + width /= num_sleep_tx; + + // double cell_hight = MAX(cell.w*2, g_tp.cell_h_def); + raw_area = compute_gate_area(INV, 1, width, p_to_n_sz_ratio * width, cell.h) / + 2; // Only single device, assuming device is laid on the side of + // the circuit block without changing the height of the + // standard library cells (using the standard cell approach). + raw_width = cell.w; + raw_hight = raw_area / cell.w; + area.set_h(raw_hight); + area.set_w(raw_width); + + compute_penalty(); +} + +double Sleep_tx::compute_penalty() { + // V_delta = VDD - VCCmin nothing to do with threshold of sleep tx. Although + // it might be OK to use sleep tx to control the V_delta + // double c_load; + double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(false, false, true); + + if (is_footer) { + c_intrinsic_sleep = + drain_C_(width, NCH, 1, 1, area.h, false, false, false, is_sleep_tx); + // V_delta = _V_delta; + wakeup_delay = + (c_circuit_wakeup + c_intrinsic_sleep) * V_delta / + (simplified_nmos_Isat(width, false, false, false, is_sleep_tx) / + Ilinear_to_Isat_ratio); + wakeup_power.readOp.dynamic = + (c_circuit_wakeup + c_intrinsic_sleep) * g_tp.sram_cell.Vdd * V_delta; + // no 0.5 because the half of the energy spend in entering sleep and half of + // the energy will be spent in waking up. And they are pairs + } + else { + c_intrinsic_sleep = drain_C_(width * p_to_n_sz_ratio, PCH, 1, 1, area.h, + false, false, false, is_sleep_tx); + // V_delta = _V_delta; + wakeup_delay = + (c_circuit_wakeup + c_intrinsic_sleep) * V_delta / + (simplified_pmos_Isat(width, false, false, false, is_sleep_tx) / + Ilinear_to_Isat_ratio); + wakeup_power.readOp.dynamic = + (c_circuit_wakeup + c_intrinsic_sleep) * g_tp.sram_cell.Vdd * V_delta; + } + + /* + The number of cycles in the wake-up latency set the constraint on the + minimum number of idle clock cycles needed before a processor + can enter in the corresponding sleep mode without any wakeup + overhead. + + If the circuit is half way to sleep then waken up, it is still OK + just the wakeup latency will be shorter than the wakeup time from full + asleep. So, the sleep time and energy does not matter + */ + + return 0.; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/powergating.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/powergating.h new file mode 100644 index 0000000000..c4709c1c01 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/powergating.h @@ -0,0 +1,81 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef POWERGATING_H_ +#define POWERGATING_H_ + +#include "component.h" + +namespace cacti { + +class Sleep_tx : public Component { + public: + Sleep_tx(double _perf_with_sleep_tx, + double _active_Isat, // of circuit block, not sleep tx + bool _is_footer, double _c_circuit_wakeup, double _V_delta, + int _num_sleep_tx, + // double _vt_circuit, + // double _vt_sleep_tx, + // double _mobility,//of sleep tx + // double _c_ox,//of sleep tx + const Area &cell_); + + double perf_with_sleep_tx; + double active_Isat; + bool is_footer; + int num_sleep_tx; + double vt_circuit; + double vt_sleep_tx; + double vdd; // of circuit block not sleep tx + double mobility; // of sleep tx + double c_ox; + double width; + double c_circuit_wakeup; + double c_intrinsic_sleep; + double delay, wakeup_delay; + powerDef power, wakeup_power; + // double c_circuit_sleep; + // double sleep_delay; + // powerDef sleep_power; + const Area &cell; + bool is_sleep_tx; + double V_delta; + + // void compute_area(); + double compute_penalty(); // return outrisetime + + void leakage_feedback(double){}; + ~Sleep_tx(){}; +}; + +} // namespace cacti + +#endif /* POWERGATING_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/router.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/router.cc new file mode 100644 index 0000000000..7949ee6fc8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/router.cc @@ -0,0 +1,291 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "router.h" +using namespace cacti; + +Router::Router(double flit_size_, + double vc_buf, /* vc size = vc_buffer_size * flit_size */ + double vc_c, TechnologyParameter::DeviceType *dt, double I_, + double O_, double M_) + : flit_size(flit_size_), deviceType(dt), I(I_), O(O_), M(M_) { + vc_buffer_size = vc_buf; + vc_count = vc_c; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + double technology = g_ip->F_sz_um; + + Vdd = dt->Vdd; + + /*Crossbar parameters. Transmisson gate is employed for connector*/ + NTtr = 10 * technology * 1e-6 / 2; /*Transmission gate's nmos tr. length*/ + PTtr = 20 * technology * 1e-6 / 2; /* pmos tr. length*/ + wt = 15 * technology * 1e-6 / 2; /*track width*/ + ht = 15 * technology * 1e-6 / 2; /*track height*/ + // I = 5; /*Number of crossbar input ports*/ + // O = 5; /*Number of crossbar output ports*/ + NTi = 12.5 * technology * 1e-6 / 2; + PTi = 25 * technology * 1e-6 / 2; + + NTid = 60 * technology * 1e-6 / 2; // m + PTid = 120 * technology * 1e-6 / 2; // m + NTod = 60 * technology * 1e-6 / 2; // m + PTod = 120 * technology * 1e-6 / 2; // m + + calc_router_parameters(); +} + +Router::~Router() {} + +double // wire cap with triple spacing +Router::Cw3(double length) { + Wire wc(g_ip->wt, length, 1, 3, 3); + return (wc.wire_cap(length)); +} + +/*Function to calculate the gate capacitance*/ +double Router::gate_cap(double w) { + return (double)gate_C(w * 1e6 /*u*/, 0); +} + +/*Function to calculate the diffusion capacitance*/ +double Router::diff_cap(double w, int type /*0 for n-mos and 1 for p-mos*/, + double s /*number of stacking transistors*/) { + return (double)drain_C_(w * 1e6 /*u*/, type, (int)s, 1, g_tp.cell_h_def); +} + +/*crossbar related functions */ + +// Model for simple transmission gate +double Router::transmission_buf_inpcap() { + return diff_cap(NTtr, 0, 1) + diff_cap(PTtr, 1, 1); +} + +double Router::transmission_buf_outcap() { + return diff_cap(NTtr, 0, 1) + diff_cap(PTtr, 1, 1); +} + +double Router::transmission_buf_ctrcap() { + return gate_cap(NTtr) + gate_cap(PTtr); +} + +double Router::crossbar_inpline() { + return (Cw3(O * flit_size * wt) + O * transmission_buf_inpcap() + + gate_cap(NTid) + gate_cap(PTid) + diff_cap(NTid, 0, 1) + + diff_cap(PTid, 1, 1)); +} + +double Router::crossbar_outline() { + return (Cw3(I * flit_size * ht) + I * transmission_buf_outcap() + + gate_cap(NTod) + gate_cap(PTod) + diff_cap(NTod, 0, 1) + + diff_cap(PTod, 1, 1)); +} + +double Router::crossbar_ctrline() { + return (Cw3(0.5 * O * flit_size * wt) + + flit_size * transmission_buf_ctrcap() + diff_cap(NTi, 0, 1) + + diff_cap(PTi, 1, 1) + gate_cap(NTi) + gate_cap(PTi)); +} + +double Router::tr_crossbar_power() { + return (crossbar_inpline() * Vdd * Vdd * flit_size / 2 + + crossbar_outline() * Vdd * Vdd * flit_size / 2) * + 2; +} + +void Router::buffer_stats() { + DynamicParameter dyn_p; + dyn_p.is_tag = false; + dyn_p.pure_cam = false; + dyn_p.fully_assoc = false; + dyn_p.pure_ram = true; + dyn_p.is_dram = false; + dyn_p.is_main_mem = false; + dyn_p.num_subarrays = 1; + dyn_p.num_mats = 1; + dyn_p.Ndbl = 1; + dyn_p.Ndwl = 1; + dyn_p.Nspd = 1; + dyn_p.deg_bl_muxing = 1; + dyn_p.deg_senseamp_muxing_non_associativity = 1; + dyn_p.Ndsam_lev_1 = 1; + dyn_p.Ndsam_lev_2 = 1; + dyn_p.Ndcm = 1; + dyn_p.number_addr_bits_mat = 8; + dyn_p.number_way_select_signals_mat = 1; + dyn_p.number_subbanks_decode = 0; + dyn_p.num_act_mats_hor_dir = 1; + dyn_p.V_b_sense = Vdd; // FIXME check power calc. + dyn_p.ram_cell_tech_type = 0; + dyn_p.num_r_subarray = (int)vc_buffer_size; + dyn_p.num_c_subarray = (int)flit_size * (int)vc_count; + dyn_p.num_mats_h_dir = 1; + dyn_p.num_mats_v_dir = 1; + dyn_p.num_do_b_subbank = (int)flit_size; + dyn_p.num_di_b_subbank = (int)flit_size; + dyn_p.num_do_b_mat = (int)flit_size; + dyn_p.num_di_b_mat = (int)flit_size; + dyn_p.num_do_b_mat = (int)flit_size; + dyn_p.num_di_b_mat = (int)flit_size; + dyn_p.num_do_b_bank_per_port = (int)flit_size; + dyn_p.num_di_b_bank_per_port = (int)flit_size; + dyn_p.out_w = (int)flit_size; + + dyn_p.use_inp_params = 1; + dyn_p.num_wr_ports = (unsigned int)vc_count; + dyn_p.num_rd_ports = + 1; //(unsigned int) vc_count;//based on Bill Dally's book + dyn_p.num_rw_ports = 0; + dyn_p.num_se_rd_ports = 0; + dyn_p.num_search_ports = 0; + + dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * + (dyn_p.num_wr_ports + dyn_p.num_rw_ports - + 1 + dyn_p.num_rd_ports); + dyn_p.cell.w = + g_tp.sram.b_w + + 2 * g_tp.wire_outside_mat.pitch * + (dyn_p.num_rw_ports - 1 + + (dyn_p.num_rd_ports - dyn_p.num_se_rd_ports) + dyn_p.num_wr_ports) + + g_tp.wire_outside_mat.pitch * dyn_p.num_se_rd_ports; + + Mat buff(dyn_p); + buff.compute_delays(0); + buff.compute_power_energy(); + buffer.power.readOp = buff.power.readOp; + buffer.power.writeOp = buffer.power.readOp; // FIXME + buffer.area = buff.area; +} + +void Router::cb_stats() { + if (1) { + Crossbar c_b(I, O, flit_size); + c_b.compute_power(); + crossbar.delay = c_b.delay; + crossbar.power.readOp.dynamic = c_b.power.readOp.dynamic; + crossbar.power.readOp.leakage = c_b.power.readOp.leakage; + crossbar.power.readOp.gate_leakage = c_b.power.readOp.gate_leakage; + crossbar.area = c_b.area; + // c_b.print_crossbar(); + } + else { + crossbar.power.readOp.dynamic = tr_crossbar_power(); + crossbar.power.readOp.leakage = + flit_size * I * O * + cmos_Isub_leakage(NTtr * g_tp.min_w_nmos_, PTtr * min_w_pmos, 1, tg); + crossbar.power.readOp.gate_leakage = + flit_size * I * O * + cmos_Ig_leakage(NTtr * g_tp.min_w_nmos_, PTtr * min_w_pmos, 1, tg); + } +} + +void Router::get_router_power() { + /* calculate buffer stats */ + buffer_stats(); + + /* calculate cross-bar stats */ + cb_stats(); + + /* calculate arbiter stats */ + Arbiter vcarb(vc_count, flit_size, buffer.area.w); + Arbiter cbarb(I, flit_size, crossbar.area.w); + vcarb.compute_power(); + cbarb.compute_power(); + arbiter.power.readOp.dynamic = + vcarb.power.readOp.dynamic * I + cbarb.power.readOp.dynamic * O; + arbiter.power.readOp.leakage = + vcarb.power.readOp.leakage * I + cbarb.power.readOp.leakage * O; + arbiter.power.readOp.gate_leakage = + vcarb.power.readOp.gate_leakage * I + cbarb.power.readOp.gate_leakage * O; + + // arb_stats(); + power.readOp.dynamic = + ((buffer.power.readOp.dynamic + buffer.power.writeOp.dynamic) + + crossbar.power.readOp.dynamic + arbiter.power.readOp.dynamic) * + MIN(I, O) * M; + double pppm_t[4] = {1, I, I, 1}; + power = power + + (buffer.power * pppm_t + crossbar.power + arbiter.power) * pppm_lkg; +} + +void Router::get_router_delay() { + FREQUENCY = 5; // move this to config file --TODO + cycle_time = (1 / (double)FREQUENCY) * 1e3; // ps + delay = 4; + max_cyc = 17 * g_tp.FO4; // s + max_cyc *= 1e12; // ps + if (cycle_time < max_cyc) { + FREQUENCY = (1 / max_cyc) * 1e3; // GHz + } +} + +void Router::get_router_area() { + area.h = I * buffer.area.h; + area.w = buffer.area.w + crossbar.area.w; +} + +void Router::calc_router_parameters() { + /* calculate router frequency and pipeline cycles */ + get_router_delay(); + + /* router power stats */ + get_router_power(); + + /* area stats */ + get_router_area(); +} + +void Router::print_router() { + cout << "\n\nRouter stats:\n"; + cout << "\tRouter Area - " << area.get_area() * 1e-6 << "(mm^2)\n"; + cout << "\tMaximum possible network frequency - " << (1 / max_cyc) * 1e3 + << "GHz\n"; + cout << "\tNetwork frequency - " << FREQUENCY << " GHz\n"; + cout << "\tNo. of Virtual channels - " << vc_count << "\n"; + cout << "\tNo. of pipeline stages - " << delay << endl; + cout << "\tLink bandwidth - " << flit_size << " (bits)\n"; + cout << "\tNo. of buffer entries per virtual channel - " << vc_buffer_size + << "\n"; + cout << "\tSimple buffer Area - " << buffer.area.get_area() * 1e-6 + << "(mm^2)\n"; + cout << "\tSimple buffer access (Read) - " + << buffer.power.readOp.dynamic * 1e9 << " (nJ)\n"; + cout << "\tSimple buffer leakage - " << buffer.power.readOp.leakage * 1e3 + << " (mW)\n"; + cout << "\tCrossbar Area - " << crossbar.area.get_area() * 1e-6 << "(mm^2)\n"; + cout << "\tCross bar access energy - " << crossbar.power.readOp.dynamic * 1e9 + << " (nJ)\n"; + cout << "\tCross bar leakage power - " << crossbar.power.readOp.leakage * 1e3 + << " (mW)\n"; + cout << "\tArbiter access energy (VC arb + Crossbar arb) - " + << arbiter.power.readOp.dynamic * 1e9 << " (nJ)\n"; + cout << "\tArbiter leakage (VC arb + Crossbar arb) - " + << arbiter.power.readOp.leakage * 1e3 << " (mW)\n"; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/router.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/router.h new file mode 100644 index 0000000000..feed61fe94 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/router.h @@ -0,0 +1,109 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __ROUTER_H__ +#define __ROUTER_H__ + +#include +#include +#include "arbiter.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "crossbar.h" +#include "mat.h" +#include "parameter.h" +#include "wire.h" + +namespace cacti { + +class Router : public Component { + public: + Router(double flit_size_, + double vc_buf, /* vc size = vc_buffer_size * flit_size */ + double vc_count, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global), + double I_ = 5, double O_ = 5, double M_ = 0.6); + ~Router(); + + void print_router(); + + Component arbiter, crossbar, buffer; + + double cycle_time, max_cyc; + double flit_size; + double vc_count; + double vc_buffer_size; /* vc size = vc_buffer_size * flit_size */ + + private: + TechnologyParameter::DeviceType *deviceType; + double FREQUENCY; // move this to config file --TODO + double Cw3(double len); + double gate_cap(double w); + double diff_cap(double w, int type /*0 for n-mos and 1 for p-mos*/, + double stack); + enum Wire_type wtype; + enum Wire_placement wire_placement; + // corssbar + double NTtr, PTtr, wt, ht, I, O, NTi, PTi, NTid, PTid, NTod, PTod, TriS1, + TriS2; + double M; // network load + double transmission_buf_inpcap(); + double transmission_buf_outcap(); + double transmission_buf_ctrcap(); + double crossbar_inpline(); + double crossbar_outline(); + double crossbar_ctrline(); + double tr_crossbar_power(); + void cb_stats(); + double arb_power(); + void arb_stats(); + double buffer_params(); + void buffer_stats(); + + // arbiter + + // buffer + + // router params + double Vdd; + + void calc_router_parameters(); + void get_router_area(); + void get_router_power(); + void get_router_delay(); + + double min_w_pmos; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/subarray.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/subarray.cc new file mode 100644 index 0000000000..41ba1db5e8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/subarray.cc @@ -0,0 +1,222 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include +#include + +#include "subarray.h" +using namespace cacti; + +Subarray::Subarray(const DynamicParameter &dp_, bool is_fa_) + : dp(dp_), + num_rows(dp.num_r_subarray), + num_cols(dp.num_c_subarray), + num_cols_fa_cam(dp.tag_num_c_subarray), + num_cols_fa_ram(dp.data_num_c_subarray), + cell(dp.cell), + cam_cell(dp.cam_cell), + is_fa(is_fa_) { + // num_cols=7; + // cout<<"num_cols ="<< num_cols <add_ecc_b_ ? (int)ceil(num_cols / num_bits_per_ecc_b_) + : 0); // ECC overhead + uint32_t ram_num_cells_wl_stitching = + (dp.ram_cell_tech_type == lp_dram) + ? dram_num_cells_wl_stitching_ + : (dp.ram_cell_tech_type == comm_dram) + ? comm_dram_num_cells_wl_stitching_ + : sram_num_cells_wl_stitching_; + + area.h = cell.h * num_rows; + + area.w = cell.w * num_cols + + ceil(num_cols / ram_num_cells_wl_stitching) * + g_tp.ram_wl_stitching_overhead_; // stitching overhead + } + else // cam fa + { + // should not add dummy row here since the dummy row do not need decoder + if (is_fa) // fully associative cache + { + num_cols_fa_cam += g_ip->add_ecc_b_ + ? (int)ceil(num_cols_fa_cam / num_bits_per_ecc_b_) + : 0; + num_cols_fa_ram += + (g_ip->add_ecc_b_ ? (int)ceil(num_cols_fa_ram / num_bits_per_ecc_b_) + : 0); + num_cols = num_cols_fa_cam + num_cols_fa_ram; + } + else { + num_cols_fa_cam += g_ip->add_ecc_b_ + ? (int)ceil(num_cols_fa_cam / num_bits_per_ecc_b_) + : 0; + num_cols_fa_ram = 0; + num_cols = num_cols_fa_cam; + } + + area.h = cam_cell.h * (num_rows + 1); // height of subarray is decided by + // CAM array. blank space in sram + // array are filled with dummy cells + area.w = cam_cell.w * num_cols_fa_cam + cell.w * num_cols_fa_ram + + ceil((num_cols_fa_cam + num_cols_fa_ram) / + sram_num_cells_wl_stitching_) * + g_tp.ram_wl_stitching_overhead_ + + 16 * g_tp.wire_local.pitch // the overhead for the NAND gate to + // connect the two halves + + + 128 * g_tp.wire_local.pitch; // the overhead for the drivers + // from matchline to wordline of RAM + } + + assert(area.h > 0); + assert(area.w > 0); + compute_C(); +} + +Subarray::~Subarray() {} + +double Subarray::get_total_cell_area() { + // return (is_fa==false? cell.get_area() * num_rows * num_cols + // //: cam_cell.h*(num_rows+1)*(num_cols_fa_cam + + // sram_cell.get_area()*num_cols_fa_ram)); : + // cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + num_cols_fa_ram)); + // //: cam_cell.get_area()*(num_rows+1)*num_cols_fa_cam + + // sram_cell.get_area()*(num_rows+1)*num_cols_fa_ram);//for FA, this area does + // not include the dummy cells in SRAM arrays. + + if (!(is_fa || dp.pure_cam)) + return (cell.get_area() * num_rows * num_cols); + else if (is_fa) { // for FA, this area includes the dummy cells in SRAM + // arrays. + // return (cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + + // num_cols_fa_ram)); cout<<"diff" + // < +#include "basic_circuit.h" + +#include "parameter.h" + +namespace cacti { + +double wire_resistance(double resistivity, double wire_width, + double wire_thickness, double barrier_thickness, + double dishing_thickness, double alpha_scatter) { + double resistance; + resistance = alpha_scatter * resistivity / + ((wire_thickness - barrier_thickness - dishing_thickness) * + (wire_width - 2 * barrier_thickness)); + return (resistance); +} + +double wire_capacitance(double wire_width, double wire_thickness, + double wire_spacing, double ild_thickness, + double miller_value, double horiz_dielectric_constant, + double vert_dielectric_constant, double fringe_cap) { + double vertical_cap, sidewall_cap, total_cap; + vertical_cap = 2 * PERMITTIVITY_FREE_SPACE * vert_dielectric_constant * + wire_width / ild_thickness; + sidewall_cap = 2 * PERMITTIVITY_FREE_SPACE * miller_value * + horiz_dielectric_constant * wire_thickness / wire_spacing; + total_cap = vertical_cap + sidewall_cap + fringe_cap; + return (total_cap); +} + +void init_tech_params(double technology, bool is_tag) { + int iter, tech, tech_lo, tech_hi; + double curr_alpha, curr_vpp = 0.; + double wire_width, wire_thickness, wire_spacing, fringe_cap, + pmos_to_nmos_sizing_r; + // double aspect_ratio,ild_thickness, miller_value = 1.5, + // horiz_dielectric_constant, vert_dielectric_constant; + double barrier_thickness, dishing_thickness, alpha_scatter; + double curr_vdd_dram_cell = 0.; + double curr_v_th_dram_access_transistor = 0.; + double curr_I_on_dram_cell = 0.; + double curr_c_dram_cell = 0.; + + uint32_t ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type + : g_ip->data_arr_ram_cell_tech_type; + uint32_t peri_global_tech_type = (is_tag) + ? g_ip->tag_arr_peri_global_tech_type + : g_ip->data_arr_peri_global_tech_type; + + technology = technology * 1000.0; // in the unit of nm + + // initialize parameters + g_tp.reset(); + double gmp_to_gmn_multiplier_periph_global = 0; + + double curr_Wmemcella_dram = 0.; + double curr_Wmemcellpmos_dram = 0.; + double curr_Wmemcellnmos_dram = 0.; + double curr_area_cell_dram = 0.; + double curr_asp_ratio_cell_dram = 0.; + double curr_Wmemcella_sram = 0.; + double curr_Wmemcellpmos_sram = 0.; + double curr_Wmemcellnmos_sram = 0.; + double curr_area_cell_sram = 0.; + double curr_asp_ratio_cell_sram = 0.; + double curr_I_off_dram_cell_worst_case_length_temp = 0.; + double curr_Wmemcella_cam = 0.; + double curr_Wmemcellpmos_cam = 0.; + double curr_Wmemcellnmos_cam = 0.; + double curr_area_cell_cam = 0.; + double curr_asp_ratio_cell_cam = 0.; + double SENSE_AMP_D = 0.; + double SENSE_AMP_P = 0.; + double area_cell_dram = 0; + double asp_ratio_cell_dram = 0; + double area_cell_sram = 0; + double asp_ratio_cell_sram = 0; + double area_cell_cam = 0; + double asp_ratio_cell_cam = 0; + double mobility_eff_periph_global = 0; + double Vdsat_periph_global = 0; + double nmos_effective_resistance_multiplier; + double width_dram_access_transistor; + + double curr_logic_scaling_co_eff = + 0; // This is based on the reported + // numbers of Intel Merom 65nm, + // Penryn45nm and IBM cell 90/65/45 date + double curr_core_tx_density = + 0; // this is density per um^2; 90, ...22nm based on Intel Penryn + double curr_chip_layout_overhead = 0; + double curr_macro_layout_overhead = 0; + double curr_sckt_co_eff = 0; + + if (technology < 181 && technology > 179) { + tech_lo = 180; + tech_hi = 180; + } + else if (technology < 91 && technology > 89) { + tech_lo = 90; + tech_hi = 90; + } + else if (technology < 66 && technology > 64) { + tech_lo = 65; + tech_hi = 65; + } + else if (technology < 46 && technology > 44) { + tech_lo = 45; + tech_hi = 45; + } + else if (technology < 33 && technology > 31) { + tech_lo = 32; + tech_hi = 32; + } + else if (technology < 23 && technology > 21) { + tech_lo = 22; + tech_hi = 22; + if (ram_cell_tech_type == 3) { + cout << "current version does not support eDRAM technologies at 22nm" + << endl; + exit(0); + } + } + // else if (technology < 17 && technology > 15) + // { + // tech_lo = 16; + // tech_hi = 16; + // } + else if (technology < 180 && technology > 90) { + tech_lo = 180; + tech_hi = 90; + } + else if (technology < 90 && technology > 65) { + tech_lo = 90; + tech_hi = 65; + } + else if (technology < 65 && technology > 45) { + tech_lo = 65; + tech_hi = 45; + } + else if (technology < 45 && technology > 32) { + tech_lo = 45; + tech_hi = 32; + } + else if (technology < 32 && technology > 22) { + tech_lo = 32; + tech_hi = 22; + } + // else if (technology < 22 && technology > 16) + // { + // tech_lo = 22; + // tech_hi = 16; + // } + else { + cout << "Invalid technology nodes" << endl; + exit(0); + } + + double vdd[NUMBER_TECH_FLAVORS]; // default vdd from itrs + double vdd_real[NUMBER_TECH_FLAVORS]; // real vdd defined by user, this is + // for changing vdd from itrs; it + // actually does not dependent on + // technology node since it is user + // defined + double alpha_power_law[NUMBER_TECH_FLAVORS]; // co-efficient for ap-law + double Lphy[NUMBER_TECH_FLAVORS]; + double Lelec[NUMBER_TECH_FLAVORS]; + double t_ox[NUMBER_TECH_FLAVORS]; + double v_th[NUMBER_TECH_FLAVORS]; + double c_ox[NUMBER_TECH_FLAVORS]; + double mobility_eff[NUMBER_TECH_FLAVORS]; + double Vdsat[NUMBER_TECH_FLAVORS]; + double c_g_ideal[NUMBER_TECH_FLAVORS]; + double c_fringe[NUMBER_TECH_FLAVORS]; + double c_junc[NUMBER_TECH_FLAVORS]; + double I_on_n[NUMBER_TECH_FLAVORS]; + // double I_on_p[NUMBER_TECH_FLAVORS]; + double Rnchannelon[NUMBER_TECH_FLAVORS]; + double Rpchannelon[NUMBER_TECH_FLAVORS]; + double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS]; + double I_off_n[NUMBER_TECH_FLAVORS][101]; + double I_g_on_n[NUMBER_TECH_FLAVORS][101]; + // double I_off_p[NUMBER_TECH_FLAVORS][101]; + double gmp_to_gmn_multiplier[NUMBER_TECH_FLAVORS]; + // double curr_sckt_co_eff[NUMBER_TECH_FLAVORS]; + double long_channel_leakage_reduction[NUMBER_TECH_FLAVORS]; + + for (iter = 0; iter <= 1; ++iter) { + // linear interpolation + if (iter == 0) { + tech = tech_lo; + if (tech_lo == tech_hi) { + curr_alpha = 1; + } + else { + curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); + } + } + else { + tech = tech_hi; + if (tech_lo == tech_hi) { + break; + } + else { + curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); + } + } + + if (tech == 180) { + // 180nm technology-node. Corresponds to year 1999 in ITRS + // Only HP transistor was of interest that 180nm since leakage power was + // not a big issue. Performance was the king MASTAR does not contain data + // for 0.18um process. The following parameters are projected based on + // ITRS 2000 update and IBM 0.18 Cu Spice input 180nm does not support + // DVS + bool Aggre_proj = false; + SENSE_AMP_D = .28e-9; // s + SENSE_AMP_P = 14.7e-15; // J + vdd[0] = 1.5; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.4; + Lphy[0] = 0.12; // Lphy is the physical gate-length. micron + Lelec[0] = 0.10; // Lelec is the electrical gate-length. micron + t_ox[0] = 1.2e-3 * (Aggre_proj ? 1.9 / 1.2 : 2); // micron + v_th[0] = Aggre_proj ? 0.36 : 0.4407; // V + c_ox[0] = 1.79e-14 * (Aggre_proj ? 1.9 / 1.2 : 2); // F/micron2 + mobility_eff[0] = 302.16 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 0.128 * 2; // V + c_g_ideal[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 6.64e-16; // F/micron + c_fringe[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 0.08e-15; // F/micron + c_junc[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 1e-15; // F/micron2 + I_on_n[0] = 750e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); // A/micron + // I_on_p[0] = 350e-6; // A/micron + // Note that nmos_effective_resistance_multiplier, + // n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are + // calculated offline + nmos_effective_resistance_multiplier = 1.54; + n_to_p_eff_curr_drv_ratio[0] = 2.45; + gmp_to_gmn_multiplier[0] = 1.22; + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1; + I_off_n[0][0] = 7e-10; // A/micron + I_off_n[0][10] = 8.26e-10; + I_off_n[0][20] = 9.74e-10; + I_off_n[0][30] = 1.15e-9; + I_off_n[0][40] = 1.35e-9; + I_off_n[0][50] = 1.60e-9; + I_off_n[0][60] = 1.88e-9; + I_off_n[0][70] = 2.29e-9; + I_off_n[0][80] = 2.70e-9; + I_off_n[0][90] = 3.19e-9; + I_off_n[0][100] = 3.76e-9; + + I_g_on_n[0][0] = 1.65e-10; // A/micron + I_g_on_n[0][10] = 1.65e-10; + I_g_on_n[0][20] = 1.65e-10; + I_g_on_n[0][30] = 1.65e-10; + I_g_on_n[0][40] = 1.65e-10; + I_g_on_n[0][50] = 1.65e-10; + I_g_on_n[0][60] = 1.65e-10; + I_g_on_n[0][70] = 1.65e-10; + I_g_on_n[0][80] = 1.65e-10; + I_g_on_n[0][90] = 1.65e-10; + I_g_on_n[0][100] = 1.65e-10; + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; // 360 + curr_asp_ratio_cell_cam = 2.92; // 2.5 + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 1.5; // linear scaling from 90nm + curr_core_tx_density = 1.25 * 0.7 * 0.7 * 0.4; + curr_sckt_co_eff = 1.11; + curr_chip_layout_overhead = + 1.0; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.0; // EDA placement and routing tool rule of thumb + } + + if (tech == 90) { + SENSE_AMP_D = .28e-9; // s + SENSE_AMP_P = 14.7e-15; // J + // 90nm technology-node. Corresponds to year 2004 in ITRS + // ITRS HP device type + vdd[0] = 1.2; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.34; + Lphy[0] = 0.037; // Lphy is the physical gate-length. micron + Lelec[0] = 0.0266; // Lelec is the electrical gate-length. micron + t_ox[0] = 1.2e-3; // micron + v_th[0] = 0.23707; // V + c_ox[0] = 1.79e-14; // F/micron2 + mobility_eff[0] = 342.16 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 0.128; // V + c_g_ideal[0] = 6.64e-16; // F/micron + c_fringe[0] = 0.08e-15; // F/micron + c_junc[0] = 1e-15; // F/micron2 + I_on_n[0] = 1076.9e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); // A/micron with ap-law + // applied for dvs and + // arbitrary vdd + // I_on_p[0] = 712.6e-6; // A/micron + // Note that nmos_effective_resistance_multiplier, + // n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are + // calculated offline + nmos_effective_resistance_multiplier = 1.54; + n_to_p_eff_curr_drv_ratio[0] = 2.45; + gmp_to_gmn_multiplier[0] = 1.22; + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd_real[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1; + I_off_n[0][0] = 3.24e-8 * pow(vdd_real[0] / (vdd[0]), 4); // A/micron + I_off_n[0][10] = 4.01e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][20] = 4.90e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][30] = 5.92e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][40] = 7.08e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][50] = 8.38e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][60] = 9.82e-8 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][70] = 1.14e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][80] = 1.29e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][90] = 1.43e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][100] = 1.54e-7 * pow(vdd_real[0] / (vdd[0]), 4); + + I_g_on_n[0][0] = 1.65e-8; // A/micron + I_g_on_n[0][10] = 1.65e-8; + I_g_on_n[0][20] = 1.65e-8; + I_g_on_n[0][30] = 1.65e-8; + I_g_on_n[0][40] = 1.65e-8; + I_g_on_n[0][50] = 1.65e-8; + I_g_on_n[0][60] = 1.65e-8; + I_g_on_n[0][70] = 1.65e-8; + I_g_on_n[0][80] = 1.65e-8; + I_g_on_n[0][90] = 1.65e-8; + I_g_on_n[0][100] = 1.65e-8; + + // ITRS LSTP device type + vdd[1] = 1.3; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; + alpha_power_law[1] = 1.47; + Lphy[1] = 0.075; + Lelec[1] = 0.0486; + t_ox[1] = 2.2e-3; + v_th[1] = 0.48203; + c_ox[1] = 1.22e-14; + mobility_eff[1] = 356.76 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 0.373; + c_g_ideal[1] = 9.15e-16; + c_fringe[1] = 0.08e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 503.6e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = 235.1e-6; + nmos_effective_resistance_multiplier = 1.92; + n_to_p_eff_curr_drv_ratio[1] = 2.44; + gmp_to_gmn_multiplier[1] = 0.88; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1; + I_off_n[1][0] = 2.81e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][10] = 4.76e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][20] = 7.82e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][30] = 1.25e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][40] = 1.94e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][50] = 2.94e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][60] = 4.36e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][70] = 6.32e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][80] = 8.95e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][90] = 1.25e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][100] = 1.7e-10 * pow(vdd_real[1] / (vdd[1]), 4); + + I_g_on_n[1][0] = 3.87e-11; // A/micron + I_g_on_n[1][10] = 3.87e-11; + I_g_on_n[1][20] = 3.87e-11; + I_g_on_n[1][30] = 3.87e-11; + I_g_on_n[1][40] = 3.87e-11; + I_g_on_n[1][50] = 3.87e-11; + I_g_on_n[1][60] = 3.87e-11; + I_g_on_n[1][70] = 3.87e-11; + I_g_on_n[1][80] = 3.87e-11; + I_g_on_n[1][90] = 3.87e-11; + I_g_on_n[1][100] = 3.87e-11; + + // ITRS LOP device type + vdd[2] = 0.9; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; + alpha_power_law[2] = 1.55; + Lphy[2] = 0.053; + Lelec[2] = 0.0354; + t_ox[2] = 1.5e-3; + v_th[2] = 0.30764; + c_ox[2] = 1.59e-14; + mobility_eff[2] = 460.39 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 0.113; + c_g_ideal[2] = 8.45e-16; + c_fringe[2] = 0.08e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 386.6e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = 209.7e-6; + nmos_effective_resistance_multiplier = 1.77; + n_to_p_eff_curr_drv_ratio[2] = 2.54; + gmp_to_gmn_multiplier[2] = 0.98; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1; + I_off_n[2][0] = 2.14e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 2.9e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 3.87e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 5.07e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 6.54e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 8.27e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 1.02e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.20e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 1.36e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 1.52e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 1.73e-8 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 4.31e-8; // A/micron + I_g_on_n[2][10] = 4.31e-8; + I_g_on_n[2][20] = 4.31e-8; + I_g_on_n[2][30] = 4.31e-8; + I_g_on_n[2][40] = 4.31e-8; + I_g_on_n[2][50] = 4.31e-8; + I_g_on_n[2][60] = 4.31e-8; + I_g_on_n[2][70] = 4.31e-8; + I_g_on_n[2][80] = 4.31e-8; + I_g_on_n[2][90] = 4.31e-8; + I_g_on_n[2][100] = 4.31e-8; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.2; + Lphy[3] = 0.12; + Lelec[3] = 0.0756; + curr_v_th_dram_access_transistor = 0.4545; + width_dram_access_transistor = 0.14; + curr_I_on_dram_cell = 45e-6; + curr_I_off_dram_cell_worst_case_length_temp = 21.1e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 0.168; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.6; + t_ox[3] = 2.2e-3; + v_th[3] = 0.4545; + c_ox[3] = 1.22e-14; + mobility_eff[3] = 323.95 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.3; + c_g_ideal[3] = 1.47e-15; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 321.6e-6; + // I_on_p[3] = 203.3e-6; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 1.95; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.42e-11; + I_off_n[3][10] = 2.25e-11; + I_off_n[3][20] = 3.46e-11; + I_off_n[3][30] = 5.18e-11; + I_off_n[3][40] = 7.58e-11; + I_off_n[3][50] = 1.08e-10; + I_off_n[3][60] = 1.51e-10; + I_off_n[3][70] = 2.02e-10; + I_off_n[3][80] = 2.57e-10; + I_off_n[3][90] = 3.14e-10; + I_off_n[3][100] = 3.85e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.6; + Lphy[3] = 0.09; + Lelec[3] = 0.0576; + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.09; + curr_I_on_dram_cell = 20e-6; + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.09 * 0.09; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 3.7; + t_ox[3] = 5.5e-3; + v_th[3] = 1.0; + c_ox[3] = 5.65e-15; + mobility_eff[3] = 302.2 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.32; + c_g_ideal[3] = 5.08e-16; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1094.3e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.62; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 5.80e-15; + I_off_n[3][10] = 1.21e-14; + I_off_n[3][20] = 2.42e-14; + I_off_n[3][30] = 4.65e-14; + I_off_n[3][40] = 8.60e-14; + I_off_n[3][50] = 1.54e-13; + I_off_n[3][60] = 2.66e-13; + I_off_n[3][70] = 4.45e-13; + I_off_n[3][80] = 7.17e-13; + I_off_n[3][90] = 1.11e-12; + I_off_n[3][100] = 1.67e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; // 360 + curr_asp_ratio_cell_cam = 2.92; // 2.5 + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 1; + curr_core_tx_density = 1.25 * 0.7 * 0.7; + curr_sckt_co_eff = 1.1539; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 65) { // 65nm technology-node. Corresponds to year 2007 in ITRS + // ITRS HP device type + SENSE_AMP_D = .2e-9; // s + SENSE_AMP_P = 5.7e-15; // J + vdd[0] = 1.1; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.27; + Lphy[0] = 0.025; + Lelec[0] = 0.019; + t_ox[0] = 1.1e-3; + v_th[0] = .19491; + c_ox[0] = 1.88e-14; + mobility_eff[0] = 436.24 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[0] = 7.71e-2; + c_g_ideal[0] = 4.69e-16; + c_fringe[0] = 0.077e-15; + c_junc[0] = 1e-15; + I_on_n[0] = 1197.2e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); + // I_on_p[0] = 870.8e-6; + nmos_effective_resistance_multiplier = 1.50; + n_to_p_eff_curr_drv_ratio[0] = 2.41; + gmp_to_gmn_multiplier[0] = 1.38; + Rnchannelon[0] = + nmos_effective_resistance_multiplier * vdd_real[0] / I_on_n[0]; + Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; + long_channel_leakage_reduction[0] = 1 / 3.74; + // Using MASTAR, @380K, increase Lgate until Ion reduces to 90% or Lgate + // increase by 10%, whichever comes first Ioff(Lgate normal)/Ioff(Lgate + // long)= 3.74. + I_off_n[0][0] = 1.96e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][10] = 2.29e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][20] = 2.66e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][30] = 3.05e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][40] = 3.49e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][50] = 3.95e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][60] = 4.45e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][70] = 4.97e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][80] = 5.48e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][90] = 5.94e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][100] = 6.3e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_g_on_n[0][0] = 4.09e-8; // A/micron + I_g_on_n[0][10] = 4.09e-8; + I_g_on_n[0][20] = 4.09e-8; + I_g_on_n[0][30] = 4.09e-8; + I_g_on_n[0][40] = 4.09e-8; + I_g_on_n[0][50] = 4.09e-8; + I_g_on_n[0][60] = 4.09e-8; + I_g_on_n[0][70] = 4.09e-8; + I_g_on_n[0][80] = 4.09e-8; + I_g_on_n[0][90] = 4.09e-8; + I_g_on_n[0][100] = 4.09e-8; + + // ITRS LSTP device type + vdd[1] = 1.2; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; // TODO + alpha_power_law[1] = 1.40; + Lphy[1] = 0.045; + Lelec[1] = 0.0298; + t_ox[1] = 1.9e-3; + v_th[1] = 0.52354; + c_ox[1] = 1.36e-14; + mobility_eff[1] = 341.21 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 0.128; + c_g_ideal[1] = 6.14e-16; + c_fringe[1] = 0.08e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 519.2e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = 266e-6; + nmos_effective_resistance_multiplier = 1.96; + n_to_p_eff_curr_drv_ratio[1] = 2.23; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1 / 2.82; + I_off_n[1][0] = 9.12e-12 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][10] = 1.49e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][20] = 2.36e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][30] = 3.64e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][40] = 5.48e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][50] = 8.05e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][60] = 1.15e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][70] = 1.59e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][80] = 2.1e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][90] = 2.62e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][100] = 3.21e-10 * pow(vdd_real[1] / (vdd[1]), 4); + + I_g_on_n[1][0] = 1.09e-10; // A/micron + I_g_on_n[1][10] = 1.09e-10; + I_g_on_n[1][20] = 1.09e-10; + I_g_on_n[1][30] = 1.09e-10; + I_g_on_n[1][40] = 1.09e-10; + I_g_on_n[1][50] = 1.09e-10; + I_g_on_n[1][60] = 1.09e-10; + I_g_on_n[1][70] = 1.09e-10; + I_g_on_n[1][80] = 1.09e-10; + I_g_on_n[1][90] = 1.09e-10; + I_g_on_n[1][100] = 1.09e-10; + + // ITRS LOP device type + vdd[2] = 0.8; + alpha_power_law[2] = 1.43; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; + Lphy[2] = 0.032; + Lelec[2] = 0.0216; + t_ox[2] = 1.2e-3; + v_th[2] = 0.28512; + c_ox[2] = 1.87e-14; + mobility_eff[2] = 495.19 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 0.292; + c_g_ideal[2] = 6e-16; + c_fringe[2] = 0.08e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 573.1e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = 340.6e-6; + nmos_effective_resistance_multiplier = 1.82; + n_to_p_eff_curr_drv_ratio[2] = 2.28; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1 / 2.05; + I_off_n[2][0] = 4.9e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 6.49e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 8.45e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 1.08e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 1.37e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 1.71e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 2.09e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 2.48e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 2.84e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 3.13e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 3.42e-8 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 9.61e-9; // A/micron + I_g_on_n[2][10] = 9.61e-9; + I_g_on_n[2][20] = 9.61e-9; + I_g_on_n[2][30] = 9.61e-9; + I_g_on_n[2][40] = 9.61e-9; + I_g_on_n[2][50] = 9.61e-9; + I_g_on_n[2][60] = 9.61e-9; + I_g_on_n[2][70] = 9.61e-9; + I_g_on_n[2][80] = 9.61e-9; + I_g_on_n[2][90] = 9.61e-9; + I_g_on_n[2][100] = 9.61e-9; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.2; + Lphy[3] = 0.12; + Lelec[3] = 0.0756; + curr_v_th_dram_access_transistor = 0.43806; + width_dram_access_transistor = 0.09; + curr_I_on_dram_cell = 36e-6; + curr_I_off_dram_cell_worst_case_length_temp = 19.6e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 0.11; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.6; + t_ox[3] = 2.2e-3; + v_th[3] = 0.43806; + c_ox[3] = 1.22e-14; + mobility_eff[3] = 328.32 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.43806; + c_g_ideal[3] = 1.46e-15; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 399.8e-6; + // I_on_p[3] = 243.4e-6; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 2.23e-11; + I_off_n[3][10] = 3.46e-11; + I_off_n[3][20] = 5.24e-11; + I_off_n[3][30] = 7.75e-11; + I_off_n[3][40] = 1.12e-10; + I_off_n[3][50] = 1.58e-10; + I_off_n[3][60] = 2.18e-10; + I_off_n[3][70] = 2.88e-10; + I_off_n[3][80] = 3.63e-10; + I_off_n[3][90] = 4.41e-10; + I_off_n[3][100] = 5.36e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.3; + Lphy[3] = 0.065; + Lelec[3] = 0.0426; + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.065; + curr_I_on_dram_cell = 20e-6; + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.065 * 0.065; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 3.3; + t_ox[3] = 5e-3; + v_th[3] = 1.0; + c_ox[3] = 6.16e-15; + mobility_eff[3] = 303.44 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.385; + c_g_ideal[3] = 4e-16; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1031e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.69; + n_to_p_eff_curr_drv_ratio[3] = 2.39; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.80e-14; + I_off_n[3][10] = 3.64e-14; + I_off_n[3][20] = 7.03e-14; + I_off_n[3][30] = 1.31e-13; + I_off_n[3][40] = 2.35e-13; + I_off_n[3][50] = 4.09e-13; + I_off_n[3][60] = 6.89e-13; + I_off_n[3][70] = 1.13e-12; + I_off_n[3][80] = 1.78e-12; + I_off_n[3][90] = 2.71e-12; + I_off_n[3][100] = 3.99e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = + 0.7; // Rather than scale proportionally to square of feature size, + // only scale linearly according to IBM cell processor + curr_core_tx_density = 1.25 * 0.7; + curr_sckt_co_eff = 1.1359; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 45) { // 45nm technology-node. Corresponds to year 2010 in ITRS + // ITRS HP device type + SENSE_AMP_D = .04e-9; // s + SENSE_AMP_P = 2.7e-15; // J + vdd[0] = 1.0; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; // TODO + alpha_power_law[0] = 1.21; + Lphy[0] = 0.018; + Lelec[0] = 0.01345; + t_ox[0] = 0.65e-3; + v_th[0] = .18035; + c_ox[0] = 3.77e-14; + mobility_eff[0] = 266.68 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[0] = 9.38E-2; + c_g_ideal[0] = 6.78e-16; + c_fringe[0] = 0.05e-15; + c_junc[0] = 1e-15; + I_on_n[0] = 2046.6e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); + // There are certain problems with the ITRS PMOS numbers in MASTAR for + // 45nm. So we are using 65nm values of n_to_p_eff_curr_drv_ratio and + // gmp_to_gmn_multiplier for 45nm + // I_on_p[0] = I_on_n[0] / 2; // This value is fixed arbitrarily + // but I_on_p + // is not being used in CACTI + nmos_effective_resistance_multiplier = 1.51; + n_to_p_eff_curr_drv_ratio[0] = 2.41; + gmp_to_gmn_multiplier[0] = 1.38; + Rnchannelon[0] = + nmos_effective_resistance_multiplier * vdd_real[0] / I_on_n[0]; + Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; + long_channel_leakage_reduction[0] = + 1 / 3.546; // Using MASTAR, @380K, increase Lgate until Ion reduces + // to 90%, Ioff(Lgate normal)/Ioff(Lgate long)= 3.74 + I_off_n[0][0] = 2.8e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][10] = 3.28e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][20] = 3.81e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][30] = 4.39e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][40] = 5.02e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][50] = 5.69e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][60] = 6.42e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][70] = 7.2e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][80] = 8.03e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][90] = 8.91e-7 * pow(vdd_real[0] / (vdd[0]), 4); + I_off_n[0][100] = 9.84e-7 * pow(vdd_real[0] / (vdd[0]), 4); + + I_g_on_n[0][0] = 3.59e-8; // A/micron + I_g_on_n[0][10] = 3.59e-8; + I_g_on_n[0][20] = 3.59e-8; + I_g_on_n[0][30] = 3.59e-8; + I_g_on_n[0][40] = 3.59e-8; + I_g_on_n[0][50] = 3.59e-8; + I_g_on_n[0][60] = 3.59e-8; + I_g_on_n[0][70] = 3.59e-8; + I_g_on_n[0][80] = 3.59e-8; + I_g_on_n[0][90] = 3.59e-8; + I_g_on_n[0][100] = 3.59e-8; + + // ITRS LSTP device type + vdd[1] = 1.1; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; + alpha_power_law[1] = 1.33; + Lphy[1] = 0.028; + Lelec[1] = 0.0212; + t_ox[1] = 1.4e-3; + v_th[1] = 0.50245; + c_ox[1] = 2.01e-14; + mobility_eff[1] = 363.96 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 9.12e-2; + c_g_ideal[1] = 5.18e-16; + c_fringe[1] = 0.08e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 666.2e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = I_on_n[1] / 2; + nmos_effective_resistance_multiplier = 1.99; + n_to_p_eff_curr_drv_ratio[1] = 2.23; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1 / 2.08; + I_off_n[1][0] = 1.01e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][10] = 1.65e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][20] = 2.62e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][30] = 4.06e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][40] = 6.12e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][50] = 9.02e-11 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][60] = 1.3e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][70] = 1.83e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][80] = 2.51e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][90] = 3.29e-10 * pow(vdd_real[1] / (vdd[1]), 4); + I_off_n[1][100] = 4.1e-10 * pow(vdd_real[1] / (vdd[1]), 4); + + I_g_on_n[1][0] = 9.47e-12; // A/micron + I_g_on_n[1][10] = 9.47e-12; + I_g_on_n[1][20] = 9.47e-12; + I_g_on_n[1][30] = 9.47e-12; + I_g_on_n[1][40] = 9.47e-12; + I_g_on_n[1][50] = 9.47e-12; + I_g_on_n[1][60] = 9.47e-12; + I_g_on_n[1][70] = 9.47e-12; + I_g_on_n[1][80] = 9.47e-12; + I_g_on_n[1][90] = 9.47e-12; + I_g_on_n[1][100] = 9.47e-12; + + // ITRS LOP device type + vdd[2] = 0.7; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; // TODO + alpha_power_law[2] = 1.39; + Lphy[2] = 0.022; + Lelec[2] = 0.016; + t_ox[2] = 0.9e-3; + v_th[2] = 0.22599; + c_ox[2] = 2.82e-14; // F/micron2 + mobility_eff[2] = 508.9 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 5.71e-2; + c_g_ideal[2] = 6.2e-16; + c_fringe[2] = 0.073e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 748.9e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = I_on_n[2] / 2; + nmos_effective_resistance_multiplier = 1.76; + n_to_p_eff_curr_drv_ratio[2] = 2.28; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1 / 1.92; + I_off_n[2][0] = 4.03e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 5.02e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 6.18e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 7.51e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 9.04e-9 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 1.08e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 1.27e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.47e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 1.66e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 1.84e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 2.03e-8 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 3.24e-8; // A/micron + I_g_on_n[2][10] = 4.01e-8; + I_g_on_n[2][20] = 4.90e-8; + I_g_on_n[2][30] = 5.92e-8; + I_g_on_n[2][40] = 7.08e-8; + I_g_on_n[2][50] = 8.38e-8; + I_g_on_n[2][60] = 9.82e-8; + I_g_on_n[2][70] = 1.14e-7; + I_g_on_n[2][80] = 1.29e-7; + I_g_on_n[2][90] = 1.43e-7; + I_g_on_n[2][100] = 1.54e-7; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.1; + Lphy[3] = 0.078; + Lelec[3] = 0.0504; // Assume Lelec is 30% lesser than Lphy for DRAM + // access and wordline transistors. + curr_v_th_dram_access_transistor = 0.44559; + width_dram_access_transistor = 0.079; + curr_I_on_dram_cell = 36e-6; // A + curr_I_off_dram_cell_worst_case_length_temp = 19.5e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.5; + t_ox[3] = 2.1e-3; + v_th[3] = 0.44559; + c_ox[3] = 1.41e-14; + mobility_eff[3] = 426.30 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.181; + c_g_ideal[3] = 1.10e-15; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 456e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 2.54e-11; + I_off_n[3][10] = 3.94e-11; + I_off_n[3][20] = 5.95e-11; + I_off_n[3][30] = 8.79e-11; + I_off_n[3][40] = 1.27e-10; + I_off_n[3][50] = 1.79e-10; + I_off_n[3][60] = 2.47e-10; + I_off_n[3][70] = 3.31e-10; + I_off_n[3][80] = 4.26e-10; + I_off_n[3][90] = 5.27e-10; + I_off_n[3][100] = 6.46e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.1; + Lphy[3] = 0.045; + Lelec[3] = 0.0298; + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.045; + curr_I_on_dram_cell = 20e-6; // A + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.045 * 0.045; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 2.7; + t_ox[3] = 4e-3; + v_th[3] = 1.0; + c_ox[3] = 7.98e-15; + mobility_eff[3] = 368.58 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.147; + c_g_ideal[3] = 3.59e-16; + c_fringe[3] = 0.08e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 999.4e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.69; + n_to_p_eff_curr_drv_ratio[3] = 1.95; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.31e-14; + I_off_n[3][10] = 2.68e-14; + I_off_n[3][20] = 5.25e-14; + I_off_n[3][30] = 9.88e-14; + I_off_n[3][40] = 1.79e-13; + I_off_n[3][50] = 3.15e-13; + I_off_n[3][60] = 5.36e-13; + I_off_n[3][70] = 8.86e-13; + I_off_n[3][80] = 1.42e-12; + I_off_n[3][90] = 2.20e-12; + I_off_n[3][100] = 3.29e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7; + curr_core_tx_density = 1.25; + curr_sckt_co_eff = 1.1387; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 32) { + SENSE_AMP_D = .03e-9; // s + SENSE_AMP_P = 2.16e-15; // J + // For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is + // 32 nm technology i.e. FEATURESIZE = 0.032). Using the SOI process + // numbers for HP and LSTP. + vdd[0] = 0.9; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; + alpha_power_law[0] = 1.19; + Lphy[0] = 0.013; + Lelec[0] = 0.01013; + t_ox[0] = 0.5e-3; + v_th[0] = 0.21835; + c_ox[0] = 4.11e-14; + mobility_eff[0] = 361.84 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[0] = 5.09E-2; + c_g_ideal[0] = 5.34e-16; + c_fringe[0] = 0.04e-15; + c_junc[0] = 1e-15; + I_on_n[0] = 2211.7e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); + // I_on_p[0] = I_on_n[0] / 2; + nmos_effective_resistance_multiplier = 1.49; + n_to_p_eff_curr_drv_ratio[0] = 2.41; + gmp_to_gmn_multiplier[0] = 1.38; + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd_real[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1 / 3.706; + // Using MASTAR, @300K (380K does not work in MASTAR), increase Lgate + // until Ion reduces to 95% or Lgate increase by 5% (DG device can only + // increase by 5%), whichever comes first + I_off_n[0][0] = 1.52e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][10] = 1.55e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][20] = 1.59e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][30] = 1.68e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][40] = 1.90e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][50] = 2.69e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][60] = 5.32e-7 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][70] = 1.02e-6 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][80] = 1.62e-6 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][90] = 2.73e-6 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][100] = 6.1e-6 * pow(vdd_real[0] / (vdd[0]), 2); + + I_g_on_n[0][0] = 6.55e-8; // A/micron + I_g_on_n[0][10] = 6.55e-8; + I_g_on_n[0][20] = 6.55e-8; + I_g_on_n[0][30] = 6.55e-8; + I_g_on_n[0][40] = 6.55e-8; + I_g_on_n[0][50] = 6.55e-8; + I_g_on_n[0][60] = 6.55e-8; + I_g_on_n[0][70] = 6.55e-8; + I_g_on_n[0][80] = 6.55e-8; + I_g_on_n[0][90] = 6.55e-8; + I_g_on_n[0][100] = 6.55e-8; + + // 32 DG + // I_g_on_n[0][0] = 2.71e-9;//A/micron + // I_g_on_n[0][10] = 2.71e-9; + // I_g_on_n[0][20] = 2.71e-9; + // I_g_on_n[0][30] = 2.71e-9; + // I_g_on_n[0][40] = 2.71e-9; + // I_g_on_n[0][50] = 2.71e-9; + // I_g_on_n[0][60] = 2.71e-9; + // I_g_on_n[0][70] = 2.71e-9; + // I_g_on_n[0][80] = 2.71e-9; + // I_g_on_n[0][90] = 2.71e-9; + // I_g_on_n[0][100] = 2.71e-9; + + // LSTP device type + vdd[1] = 1; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; + alpha_power_law[1] = 1.27; + Lphy[1] = 0.020; + Lelec[1] = 0.0173; + t_ox[1] = 1.2e-3; + v_th[1] = 0.513; + c_ox[1] = 2.29e-14; + mobility_eff[1] = 347.46 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[1] = 8.64e-2; + c_g_ideal[1] = 4.58e-16; + c_fringe[1] = 0.053e-15; + c_junc[1] = 1e-15; + I_on_n[1] = 683.6e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); + // I_on_p[1] = I_on_n[1] / 2; + nmos_effective_resistance_multiplier = 1.99; + n_to_p_eff_curr_drv_ratio[1] = 2.23; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = + nmos_effective_resistance_multiplier * vdd_real[1] / I_on_n[1]; + Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; + long_channel_leakage_reduction[1] = 1 / 1.93; + I_off_n[1][0] = 2.06e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][10] = 3.30e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][20] = 5.15e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][30] = 7.83e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][40] = 1.16e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][50] = 1.69e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][60] = 2.40e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][70] = 3.34e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][80] = 4.54e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][90] = 5.96e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][100] = 7.44e-10 * pow(vdd_real[1] / (vdd[1]), 1); + + I_g_on_n[1][0] = 3.73e-11; // A/micron + I_g_on_n[1][10] = 3.73e-11; + I_g_on_n[1][20] = 3.73e-11; + I_g_on_n[1][30] = 3.73e-11; + I_g_on_n[1][40] = 3.73e-11; + I_g_on_n[1][50] = 3.73e-11; + I_g_on_n[1][60] = 3.73e-11; + I_g_on_n[1][70] = 3.73e-11; + I_g_on_n[1][80] = 3.73e-11; + I_g_on_n[1][90] = 3.73e-11; + I_g_on_n[1][100] = 3.73e-11; + + // LOP device type + vdd[2] = 0.6; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; // TODO + alpha_power_law[2] = 1.26; + Lphy[2] = 0.016; + Lelec[2] = 0.01232; + t_ox[2] = 0.9e-3; + v_th[2] = 0.24227; + c_ox[2] = 2.84e-14; + mobility_eff[2] = 513.52 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[2] = 4.64e-2; + c_g_ideal[2] = 4.54e-16; + c_fringe[2] = 0.057e-15; + c_junc[2] = 1e-15; + I_on_n[2] = 827.8e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); + // I_on_p[2] = I_on_n[2] / 2; + nmos_effective_resistance_multiplier = 1.73; + n_to_p_eff_curr_drv_ratio[2] = 2.28; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = + nmos_effective_resistance_multiplier * vdd_real[2] / I_on_n[2]; + Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; + long_channel_leakage_reduction[2] = 1 / 1.89; + I_off_n[2][0] = 5.94e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 7.23e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 8.7e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 1.04e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 1.22e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 1.43e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 1.65e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.90e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 2.15e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 2.39e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 2.63e-7 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 2.93e-9; // A/micron + I_g_on_n[2][10] = 2.93e-9; + I_g_on_n[2][20] = 2.93e-9; + I_g_on_n[2][30] = 2.93e-9; + I_g_on_n[2][40] = 2.93e-9; + I_g_on_n[2][50] = 2.93e-9; + I_g_on_n[2][60] = 2.93e-9; + I_g_on_n[2][70] = 2.93e-9; + I_g_on_n[2][80] = 2.93e-9; + I_g_on_n[2][90] = 2.93e-9; + I_g_on_n[2][100] = 2.93e-9; + + if (ram_cell_tech_type == lp_dram) { + // LP-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.0; + Lphy[3] = 0.056; + Lelec[3] = 0.0419; // Assume Lelec is 30% lesser than Lphy for DRAM + // access and wordline transistors. + curr_v_th_dram_access_transistor = 0.44129; + width_dram_access_transistor = 0.056; + curr_I_on_dram_cell = 36e-6; + curr_I_off_dram_cell_worst_case_length_temp = 18.9e-12; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; + curr_asp_ratio_cell_dram = 1.46; + curr_c_dram_cell = 20e-15; + + // LP-DRAM wordline transistor parameters + curr_vpp = 1.5; + t_ox[3] = 2e-3; + v_th[3] = 0.44467; + c_ox[3] = 1.48e-14; + mobility_eff[3] = 408.12 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.174; + c_g_ideal[3] = 7.45e-16; + c_fringe[3] = 0.053e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1055.4e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.65; + n_to_p_eff_curr_drv_ratio[3] = 2.05; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 3.57e-11; + I_off_n[3][10] = 5.51e-11; + I_off_n[3][20] = 8.27e-11; + I_off_n[3][30] = 1.21e-10; + I_off_n[3][40] = 1.74e-10; + I_off_n[3][50] = 2.45e-10; + I_off_n[3][60] = 3.38e-10; + I_off_n[3][70] = 4.53e-10; + I_off_n[3][80] = 5.87e-10; + I_off_n[3][90] = 7.29e-10; + I_off_n[3][100] = 8.87e-10; + } + else if (ram_cell_tech_type == comm_dram) { + // COMM-DRAM cell access transistor technology parameters + curr_vdd_dram_cell = 1.0; + Lphy[3] = 0.032; + Lelec[3] = 0.0205; // Assume Lelec is 30% lesser than Lphy for DRAM + // access and wordline transistors. + curr_v_th_dram_access_transistor = 1; + width_dram_access_transistor = 0.032; + curr_I_on_dram_cell = 20e-6; + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.032 * 0.032; + curr_asp_ratio_cell_dram = 1.5; + curr_c_dram_cell = 30e-15; + + // COMM-DRAM wordline transistor parameters + curr_vpp = 2.6; + t_ox[3] = 4e-3; + v_th[3] = 1.0; + c_ox[3] = 7.99e-15; + mobility_eff[3] = 380.76 * (1e-2 * 1e6 * 1e-2 * 1e6); + Vdsat[3] = 0.129; + c_g_ideal[3] = 2.56e-16; + c_fringe[3] = 0.053e-15; + c_junc[3] = 1e-15; + I_on_n[3] = 1024.5e-6; + // I_on_p[3] = I_on_n[3] / 2; + nmos_effective_resistance_multiplier = 1.69; + n_to_p_eff_curr_drv_ratio[3] = 1.95; + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = + nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; + Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 3.63e-14; + I_off_n[3][10] = 7.18e-14; + I_off_n[3][20] = 1.36e-13; + I_off_n[3][30] = 2.49e-13; + I_off_n[3][40] = 4.41e-13; + I_off_n[3][50] = 7.55e-13; + I_off_n[3][60] = 1.26e-12; + I_off_n[3][70] = 2.03e-12; + I_off_n[3][80] = 3.19e-12; + I_off_n[3][90] = 4.87e-12; + I_off_n[3][100] = 7.16e-12; + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7; + curr_core_tx_density = 1.25 / 0.7; + curr_sckt_co_eff = 1.1111; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 22) { + SENSE_AMP_D = .03e-9; // s + SENSE_AMP_P = 2.16e-15; // J + // For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is + // 22 nm technology i.e. FEATURESIZE = 0.022). Using the DG process + // numbers for HP. 22 nm HP + vdd[0] = 0.8; + vdd_real[0] = g_ip->specific_hp_vdd ? g_ip->hp_Vdd : vdd[0]; // TODO + alpha_power_law[0] = 1.2; // 1.3//1.15; + Lphy[0] = 0.009; // Lphy is the physical gate-length. + Lelec[0] = 0.00468; // Lelec is the electrical gate-length. + t_ox[0] = 0.55e-3; // micron + v_th[0] = 0.1395; // V + c_ox[0] = 3.63e-14; // F/micron2 + mobility_eff[0] = 426.07 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 2.33e-2; // V/micron + c_g_ideal[0] = 3.27e-16; // F/micron + c_fringe[0] = 0.06e-15; // F/micron + c_junc[0] = 0; // F/micron2 + I_on_n[0] = 2626.4e-6 * pow((vdd_real[0] - v_th[0]) / (vdd[0] - v_th[0]), + alpha_power_law[0]); // A/micron + // I_on_p[0] = I_on_n[0] / + // 2; // A/micron //This value for I_on_p is not really + // used. + nmos_effective_resistance_multiplier = 1.45; + n_to_p_eff_curr_drv_ratio[0] = + 2; // Wpmos/Wnmos = 2 in 2007 MASTAR. Look in + //"Dynamic" tab of Device workspace. + gmp_to_gmn_multiplier[0] = 1.38; // Just using the 32nm SOI value. + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd_real[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1 / 3.274; + I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2 * + pow(vdd_real[0] / (vdd[0]), + 2); // From 22nm, leakage current are directly from + // ITRS report rather than MASTAR, since MASTAR + // has serious bugs there. + I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2 * pow(vdd_real[0] / (vdd[0]), 2); + // for 22nm DG HP + I_g_on_n[0][0] = 1.81e-9; // A/micron + I_g_on_n[0][10] = 1.81e-9; + I_g_on_n[0][20] = 1.81e-9; + I_g_on_n[0][30] = 1.81e-9; + I_g_on_n[0][40] = 1.81e-9; + I_g_on_n[0][50] = 1.81e-9; + I_g_on_n[0][60] = 1.81e-9; + I_g_on_n[0][70] = 1.81e-9; + I_g_on_n[0][80] = 1.81e-9; + I_g_on_n[0][90] = 1.81e-9; + I_g_on_n[0][100] = 1.81e-9; + + // 22 nm LSTP DG + vdd[1] = 0.8; + vdd_real[1] = g_ip->specific_lstp_vdd ? g_ip->lstp_Vdd : vdd[1]; // TODO + alpha_power_law[1] = 1.23; + Lphy[1] = 0.014; + Lelec[1] = 0.008; // Lelec is the electrical gate-length. + t_ox[1] = 1.1e-3; // micron + v_th[1] = 0.40126; // V + c_ox[1] = 2.30e-14; // F/micron2 + mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[1] = 6.64e-2; // V/micron + c_g_ideal[1] = 3.22e-16; // F/micron + c_fringe[1] = 0.08e-15; + c_junc[1] = 0; // F/micron2 + I_on_n[1] = 727.6e-6 * pow((vdd_real[1] - v_th[1]) / (vdd[1] - v_th[1]), + alpha_power_law[1]); // A/micron + // I_on_p[1] = I_on_n[1] / 2; + nmos_effective_resistance_multiplier = 1.99; + n_to_p_eff_curr_drv_ratio[1] = 2; + gmp_to_gmn_multiplier[1] = 0.99; + Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd_real[1] / + I_on_n[1]; // ohm-micron + Rpchannelon[1] = + n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; // ohm-micron + long_channel_leakage_reduction[1] = 1 / 1.89; + I_off_n[1][0] = 2.43e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][10] = 4.85e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][20] = 9.68e-11 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][30] = 1.94e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][40] = 3.87e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][50] = 7.73e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][60] = 3.55e-10 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][70] = 3.09e-9 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][80] = 6.19e-9 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][90] = 1.24e-8 * pow(vdd_real[1] / (vdd[1]), 1); + I_off_n[1][100] = 2.48e-8 * pow(vdd_real[1] / (vdd[1]), 1); + + I_g_on_n[1][0] = 4.51e-10; // A/micron + I_g_on_n[1][10] = 4.51e-10; + I_g_on_n[1][20] = 4.51e-10; + I_g_on_n[1][30] = 4.51e-10; + I_g_on_n[1][40] = 4.51e-10; + I_g_on_n[1][50] = 4.51e-10; + I_g_on_n[1][60] = 4.51e-10; + I_g_on_n[1][70] = 4.51e-10; + I_g_on_n[1][80] = 4.51e-10; + I_g_on_n[1][90] = 4.51e-10; + I_g_on_n[1][100] = 4.51e-10; + + // 22 nm LOP + vdd[2] = 0.6; + vdd_real[2] = g_ip->specific_lop_vdd ? g_ip->lop_Vdd : vdd[2]; // TODO + alpha_power_law[2] = 1.21; + Lphy[2] = 0.011; + Lelec[2] = 0.00604; // Lelec is the electrical gate-length. + t_ox[2] = 0.8e-3; // micron + v_th[2] = 0.2315; // V + c_ox[2] = 2.87e-14; // F/micron2 + mobility_eff[2] = 698.37 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[2] = 1.81e-2; // V/micron + c_g_ideal[2] = 3.16e-16; // F/micron + c_fringe[2] = 0.08e-15; + c_junc[2] = + 0; // F/micron2 This is Cj0 not Cjunc in MASTAR results->Dynamic Tab + I_on_n[2] = 916.1e-6 * pow((vdd_real[2] - v_th[2]) / (vdd[2] - v_th[2]), + alpha_power_law[2]); // A/micron + // I_on_p[2] = I_on_n[2] / 2; + nmos_effective_resistance_multiplier = 1.73; + n_to_p_eff_curr_drv_ratio[2] = 2; + gmp_to_gmn_multiplier[2] = 1.11; + Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd_real[2] / + I_on_n[2]; // ohm-micron + Rpchannelon[2] = + n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; // ohm-micron + long_channel_leakage_reduction[2] = 1 / 2.38; + + I_off_n[2][0] = 1.31e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][10] = 2.60e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][20] = 5.14e-8 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][30] = 1.02e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][40] = 2.02e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][50] = 3.99e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][60] = 7.91e-7 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][70] = 1.09e-6 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][80] = 2.09e-6 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][90] = 4.04e-6 * pow(vdd_real[2] / (vdd[2]), 5); + I_off_n[2][100] = 4.48e-6 * pow(vdd_real[2] / (vdd[2]), 5); + + I_g_on_n[2][0] = 2.74e-9; // A/micron + I_g_on_n[2][10] = 2.74e-9; + I_g_on_n[2][20] = 2.74e-9; + I_g_on_n[2][30] = 2.74e-9; + I_g_on_n[2][40] = 2.74e-9; + I_g_on_n[2][50] = 2.74e-9; + I_g_on_n[2][60] = 2.74e-9; + I_g_on_n[2][70] = 2.74e-9; + I_g_on_n[2][80] = 2.74e-9; + I_g_on_n[2][90] = 2.74e-9; + I_g_on_n[2][100] = 2.74e-9; + + if (ram_cell_tech_type == 3) { + } + else if (ram_cell_tech_type == 4) { + // 22 nm commodity DRAM cell access transistor technology parameters. + // parameters + curr_vdd_dram_cell = 0.9; // 0.45;//This value has reduced greatly in + // 2007 ITRS for all technology nodes. In + // 2005 ITRS, the value was about twice the value in 2007 ITRS + Lphy[3] = 0.022; // micron + Lelec[3] = 0.0181; // micron. + curr_v_th_dram_access_transistor = 1; // V + width_dram_access_transistor = 0.022; // micron + curr_I_on_dram_cell = + 20e-6; // This is a typical value that I have always + // kept constant. In reality this could perhaps be lower + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; // A + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.022 * 0.022; // micron2. + curr_asp_ratio_cell_dram = 0.667; + curr_c_dram_cell = 30e-15; // This is a typical value that I have + // alwaus + // kept constant. + + // 22 nm commodity DRAM wordline transistor parameters obtained using + // MASTAR. + curr_vpp = 2.3; // vpp. V + t_ox[3] = 3.5e-3; // micron + v_th[3] = 1.0; // V + c_ox[3] = 9.06e-15; // F/micron2 + mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[3] = 0.0972; // V/micron + c_g_ideal[3] = 1.99e-16; // F/micron + c_fringe[3] = 0.053e-15; // F/micron + c_junc[3] = 1e-15; // F/micron2 + I_on_n[3] = 910.5e-6; // A/micron + // I_on_p[3] = I_on_n[3] / 2; // This value for I_on_p is not + // really used. + nmos_effective_resistance_multiplier = + 1.69; // Using the value from 32nm. + // + n_to_p_eff_curr_drv_ratio[3] = 1.95; // Using the value from 32nm + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / + I_on_n[3]; // ohm-micron + Rpchannelon[3] = + n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; // ohm-micron + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.1e-13; // A/micron + I_off_n[3][10] = 2.11e-13; + I_off_n[3][20] = 3.88e-13; + I_off_n[3][30] = 6.9e-13; + I_off_n[3][40] = 1.19e-12; + I_off_n[3][50] = 1.98e-12; + I_off_n[3][60] = 3.22e-12; + I_off_n[3][70] = 5.09e-12; + I_off_n[3][80] = 7.85e-12; + I_off_n[3][90] = 1.18e-11; + I_off_n[3][100] = 1.72e-11; + } + else { + // some error handler + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7; + curr_core_tx_density = 1.25 / 0.7 / 0.7; + curr_sckt_co_eff = 1.1296; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + if (tech == 16) { + // For 2019, MPU/ASIC stagger-contacted M1 half-pitch is 16 nm (so this is + // 16 nm technology i.e. FEATURESIZE = 0.016). Using the DG process + // numbers for HP. 16 nm HP + vdd[0] = 0.7; + Lphy[0] = 0.006; // Lphy is the physical gate-length. + Lelec[0] = 0.00315; // Lelec is the electrical gate-length. + t_ox[0] = 0.5e-3; // micron + v_th[0] = 0.1489; // V + c_ox[0] = 3.83e-14; // F/micron2 Cox_elec in MASTAR + mobility_eff[0] = 476.15 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[0] = 1.42e-2; // V/micron calculated in spreadsheet + c_g_ideal[0] = 2.30e-16; // F/micron + c_fringe[0] = 0.06e-15; // F/micron MASTAR inputdynamic/3 + c_junc[0] = 0; // F/micron2 MASTAR result dynamic + I_on_n[0] = 2768.4e-6; // A/micron + // I_on_p[0] = I_on_n[0] / + // 2; // A/micron //This value for I_on_p is not really + // used. + nmos_effective_resistance_multiplier = + 1.48; // nmos_effective_resistance_multiplier is the ratio of Ieff + // to Idsat where Ieff is the effective NMOS current and Idsat + // is the saturation current. + n_to_p_eff_curr_drv_ratio[0] = + 2; // Wpmos/Wnmos = 2 in 2007 MASTAR. Look in + //"Dynamic" tab of Device workspace. + gmp_to_gmn_multiplier[0] = 1.38; // Just using the 32nm SOI value. + Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / + I_on_n[0]; // ohm-micron + Rpchannelon[0] = + n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; // ohm-micron + long_channel_leakage_reduction[0] = 1 / 2.655; + I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2 * 1.07; + I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2 * 1.07; + I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2 * 1.07; + I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2 * 1.07; + I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2 * 1.07; + // for 16nm DG HP + I_g_on_n[0][0] = 1.07e-9; // A/micron + I_g_on_n[0][10] = 1.07e-9; + I_g_on_n[0][20] = 1.07e-9; + I_g_on_n[0][30] = 1.07e-9; + I_g_on_n[0][40] = 1.07e-9; + I_g_on_n[0][50] = 1.07e-9; + I_g_on_n[0][60] = 1.07e-9; + I_g_on_n[0][70] = 1.07e-9; + I_g_on_n[0][80] = 1.07e-9; + I_g_on_n[0][90] = 1.07e-9; + I_g_on_n[0][100] = 1.07e-9; + + // //16 nm LSTP DG + // vdd[1] = 0.8; + // Lphy[1] = 0.014; + // Lelec[1] = 0.008;//Lelec is the electrical gate-length. + // t_ox[1] = 1.1e-3;//micron + // v_th[1] = 0.40126;//V + // c_ox[1] = 2.30e-14;//F/micron2 + // mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 + // / Vs Vdsat[1] = 6.64e-2; //V/micron c_g_ideal[1] + // = 3.22e-16;//F/micron c_fringe[1] = 0.008e-15; + // c_junc[1] = 0;//F/micron2 + // I_on_n[1] = 727.6e-6;//A/micron + // // I_on_p[1] = I_on_n[1] / 2; + // nmos_effective_resistance_multiplier = 1.99; + // n_to_p_eff_curr_drv_ratio[1] = 2; + // gmp_to_gmn_multiplier[1] = 0.99; + // Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / + // I_on_n[1];//ohm-micron Rpchannelon[1] = + // n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];//ohm-micron + // I_off_n[1][0] = 2.43e-11; + // I_off_n[1][10] = 4.85e-11; + // I_off_n[1][20] = 9.68e-11; + // I_off_n[1][30] = 1.94e-10; + // I_off_n[1][40] = 3.87e-10; + // I_off_n[1][50] = 7.73e-10; + // I_off_n[1][60] = 3.55e-10; + // I_off_n[1][70] = 3.09e-9; + // I_off_n[1][80] = 6.19e-9; + // I_off_n[1][90] = 1.24e-8; + // I_off_n[1][100]= 2.48e-8; + // + // // for 22nm LSTP HP + // I_g_on_n[1][0] = 4.51e-10;//A/micron + // I_g_on_n[1][10] = 4.51e-10; + // I_g_on_n[1][20] = 4.51e-10; + // I_g_on_n[1][30] = 4.51e-10; + // I_g_on_n[1][40] = 4.51e-10; + // I_g_on_n[1][50] = 4.51e-10; + // I_g_on_n[1][60] = 4.51e-10; + // I_g_on_n[1][70] = 4.51e-10; + // I_g_on_n[1][80] = 4.51e-10; + // I_g_on_n[1][90] = 4.51e-10; + // I_g_on_n[1][100] = 4.51e-10; + + if (ram_cell_tech_type == 3) { + } + else if (ram_cell_tech_type == 4) { + // 22 nm commodity DRAM cell access transistor technology parameters. + // parameters + curr_vdd_dram_cell = 0.9; // 0.45;//This value has reduced greatly in + // 2007 ITRS for all technology nodes. In + // 2005 ITRS, the value was about twice the value in 2007 ITRS + Lphy[3] = 0.022; // micron + Lelec[3] = 0.0181; // micron. + curr_v_th_dram_access_transistor = 1; // V + width_dram_access_transistor = 0.022; // micron + curr_I_on_dram_cell = + 20e-6; // This is a typical value that I have always + // kept constant. In reality this could perhaps be lower + curr_I_off_dram_cell_worst_case_length_temp = 1e-15; // A + curr_Wmemcella_dram = width_dram_access_transistor; + curr_Wmemcellpmos_dram = 0; + curr_Wmemcellnmos_dram = 0; + curr_area_cell_dram = 6 * 0.022 * 0.022; // micron2. + curr_asp_ratio_cell_dram = 0.667; + curr_c_dram_cell = 30e-15; // This is a typical value that I have + // alwaus + // kept constant. + + // 22 nm commodity DRAM wordline transistor parameters obtained using + // MASTAR. + curr_vpp = 2.3; // vpp. V + t_ox[3] = 3.5e-3; // micron + v_th[3] = 1.0; // V + c_ox[3] = 9.06e-15; // F/micron2 + mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6); // micron2 / Vs + Vdsat[3] = 0.0972; // V/micron + c_g_ideal[3] = 1.99e-16; // F/micron + c_fringe[3] = 0.053e-15; // F/micron + c_junc[3] = 1e-15; // F/micron2 + I_on_n[3] = 910.5e-6; // A/micron + // I_on_p[3] = I_on_n[3] / 2; // This value for I_on_p is not + // really used. + nmos_effective_resistance_multiplier = + 1.69; // Using the value from 32nm. + // + n_to_p_eff_curr_drv_ratio[3] = 1.95; // Using the value from 32nm + gmp_to_gmn_multiplier[3] = 0.90; + Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / + I_on_n[3]; // ohm-micron + Rpchannelon[3] = + n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; // ohm-micron + long_channel_leakage_reduction[3] = 1; + I_off_n[3][0] = 1.1e-13; // A/micron + I_off_n[3][10] = 2.11e-13; + I_off_n[3][20] = 3.88e-13; + I_off_n[3][30] = 6.9e-13; + I_off_n[3][40] = 1.19e-12; + I_off_n[3][50] = 1.98e-12; + I_off_n[3][60] = 3.22e-12; + I_off_n[3][70] = 5.09e-12; + I_off_n[3][80] = 7.85e-12; + I_off_n[3][90] = 1.18e-11; + I_off_n[3][100] = 1.72e-11; + } + else { + // some error handler + } + + // SRAM cell properties + curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; + curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_sram = 1.46; + // CAM cell properties //TODO: data need to be revisited + curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; + curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; + curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; + curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; + curr_asp_ratio_cell_cam = 2.92; + // Empirical undifferetiated core/FU coefficient + curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7 * 0.7; + curr_core_tx_density = 1.25 / 0.7 / 0.7 / 0.7; + curr_sckt_co_eff = 1.1296; + curr_chip_layout_overhead = + 1.2; // die measurement results based on Niagara 1 and 2 + curr_macro_layout_overhead = + 1.1; // EDA placement and routing tool rule of thumb + } + + /* + * TODO:WL_Vcc does not need to retain data as long as the wordline enable + * signal is not active (of course enable signal will not be active since it + * is idle) So, the WL_Vcc only need to balance the leakage reduction and + * the required waking up restore time (as mentioned in the 4.0Ghz 291 Mb + * SRAM Intel Paper) + */ + g_tp.peri_global.Vdd += + curr_alpha * + vdd_real[peri_global_tech_type]; // real vdd, user defined or itrs + g_tp.peri_global.Vdd_default += + curr_alpha * vdd[peri_global_tech_type]; // itrs vdd this does not have + // to do within line + // interpolation loop, can be + // assigned directly + g_tp.peri_global.Vth += curr_alpha * v_th[peri_global_tech_type]; + g_tp.peri_global.Vcc_min_default += + g_tp.peri_global.Vdd_default * + 0.45; // Use minimal voltage to keep the device + // conducted.//g_tp.peri_global.Vth; + g_tp.peri_global.t_ox += curr_alpha * t_ox[peri_global_tech_type]; + g_tp.peri_global.C_ox += curr_alpha * c_ox[peri_global_tech_type]; + g_tp.peri_global.C_g_ideal += curr_alpha * c_g_ideal[peri_global_tech_type]; + g_tp.peri_global.C_fringe += curr_alpha * c_fringe[peri_global_tech_type]; + g_tp.peri_global.C_junc += curr_alpha * c_junc[peri_global_tech_type]; + g_tp.peri_global.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.peri_global.l_phy += curr_alpha * Lphy[peri_global_tech_type]; + g_tp.peri_global.l_elec += curr_alpha * Lelec[peri_global_tech_type]; + g_tp.peri_global.I_on_n += curr_alpha * I_on_n[peri_global_tech_type]; + g_tp.peri_global.R_nch_on += + curr_alpha * Rnchannelon[peri_global_tech_type]; + g_tp.peri_global.R_pch_on += + curr_alpha * Rpchannelon[peri_global_tech_type]; + g_tp.peri_global.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[peri_global_tech_type]; + g_tp.peri_global.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[peri_global_tech_type]; + g_tp.peri_global.I_off_n += + curr_alpha * + I_off_n + [peri_global_tech_type] + [g_ip->temp - + 300]; //*pow(g_tp.peri_global.Vdd/g_tp.peri_global.Vdd_default,3);//Consider + // the voltage change may affect the current density as + // well. + // TODO: polynomial curve-fitting based on MASTAR may not be + // accurate enough + g_tp.peri_global.I_off_p += + curr_alpha * + I_off_n + [peri_global_tech_type] + [g_ip->temp - + 300]; //*pow(g_tp.peri_global.Vdd/g_tp.peri_global.Vdd_default,3);//To + // mimic the Vdd effect on Ioff (for the same device, dvs + // should not change default Ioff---only changes if device + // is different?? but MASTAR shows different results) + g_tp.peri_global.I_g_on_n += + curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; + g_tp.peri_global.I_g_on_p += + curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; + gmp_to_gmn_multiplier_periph_global += + curr_alpha * gmp_to_gmn_multiplier[peri_global_tech_type]; + g_tp.peri_global.Mobility_n += + curr_alpha * mobility_eff[peri_global_tech_type]; + + // Sleep tx uses LSTP devices + g_tp.sleep_tx.Vdd += curr_alpha * vdd_real[1]; + g_tp.sleep_tx.Vdd_default += curr_alpha * vdd[1]; + g_tp.sleep_tx.Vth += curr_alpha * v_th[1]; + g_tp.sleep_tx.Vcc_min_default += g_tp.sleep_tx.Vdd; + g_tp.sleep_tx.Vcc_min = + g_tp.sleep_tx.Vcc_min_default; // user cannot change this, has to be + // decided by technology + g_tp.sleep_tx.t_ox += curr_alpha * t_ox[1]; + g_tp.sleep_tx.C_ox += curr_alpha * c_ox[1]; + g_tp.sleep_tx.C_g_ideal += curr_alpha * c_g_ideal[1]; + g_tp.sleep_tx.C_fringe += curr_alpha * c_fringe[1]; + g_tp.sleep_tx.C_junc += curr_alpha * c_junc[1]; + g_tp.sleep_tx.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.sleep_tx.l_phy += curr_alpha * Lphy[1]; + g_tp.sleep_tx.l_elec += curr_alpha * Lelec[1]; + g_tp.sleep_tx.I_on_n += curr_alpha * I_on_n[1]; + g_tp.sleep_tx.R_nch_on += curr_alpha * Rnchannelon[1]; + g_tp.sleep_tx.R_pch_on += curr_alpha * Rpchannelon[1]; + g_tp.sleep_tx.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[1]; + g_tp.sleep_tx.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[1]; + g_tp.sleep_tx.I_off_n += + curr_alpha * + I_off_n[1] + [g_ip->temp - + 300]; //**pow(g_tp.sleep_tx.Vdd/g_tp.sleep_tx.Vdd_default,4); + g_tp.sleep_tx.I_off_p += + curr_alpha * + I_off_n[1] + [g_ip->temp - + 300]; //**pow(g_tp.sleep_tx.Vdd/g_tp.sleep_tx.Vdd_default,4); + g_tp.sleep_tx.I_g_on_n += curr_alpha * I_g_on_n[1][g_ip->temp - 300]; + g_tp.sleep_tx.I_g_on_p += curr_alpha * I_g_on_n[1][g_ip->temp - 300]; + g_tp.sleep_tx.Mobility_n += curr_alpha * mobility_eff[1]; + // gmp_to_gmn_multiplier_periph_global += curr_alpha * + // gmp_to_gmn_multiplier[1]; + + g_tp.sram_cell.Vdd += curr_alpha * vdd_real[ram_cell_tech_type]; + g_tp.sram_cell.Vdd_default += curr_alpha * vdd[ram_cell_tech_type]; + g_tp.sram_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; + g_tp.sram_cell.Vcc_min_default += g_tp.sram_cell.Vdd_default * 0.6; + g_tp.sram_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; + g_tp.sram_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; + g_tp.sram_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; + g_tp.sram_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; + g_tp.sram_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; + g_tp.sram_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; + g_tp.sram_cell.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.sram_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; + g_tp.sram_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; + g_tp.sram_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; + g_tp.sram_cell.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; + g_tp.sram_cell.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; + g_tp.sram_cell.I_off_n += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //**pow(g_tp.sram_cell.Vdd/g_tp.sram_cell.Vdd_default,4); + g_tp.sram_cell.I_off_p += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //**pow(g_tp.sram_cell.Vdd/g_tp.sram_cell.Vdd_default,4); + g_tp.sram_cell.I_g_on_n += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + g_tp.sram_cell.I_g_on_p += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + + g_tp.dram_cell_Vdd += curr_alpha * curr_vdd_dram_cell; + g_tp.dram_acc.Vth += curr_alpha * curr_v_th_dram_access_transistor; + g_tp.dram_acc.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; + g_tp.dram_acc.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; + g_tp.dram_acc.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; + g_tp.dram_acc.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; + g_tp.dram_acc.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; + g_tp.dram_acc.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.dram_cell_I_on += curr_alpha * curr_I_on_dram_cell; + g_tp.dram_cell_I_off_worst_case_len_temp += + curr_alpha * curr_I_off_dram_cell_worst_case_length_temp; + g_tp.dram_acc.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; + g_tp.dram_cell_C += curr_alpha * curr_c_dram_cell; + g_tp.vpp += curr_alpha * curr_vpp; + g_tp.dram_wl.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; + g_tp.dram_wl.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; + g_tp.dram_wl.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; + g_tp.dram_wl.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; + g_tp.dram_wl.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; + g_tp.dram_wl.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.dram_wl.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; + g_tp.dram_wl.R_nch_on += curr_alpha * Rnchannelon[dram_cell_tech_flavor]; + g_tp.dram_wl.R_pch_on += curr_alpha * Rpchannelon[dram_cell_tech_flavor]; + g_tp.dram_wl.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[dram_cell_tech_flavor]; + g_tp.dram_wl.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[dram_cell_tech_flavor]; + g_tp.dram_wl.I_off_n += + curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; + g_tp.dram_wl.I_off_p += + curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; + + g_tp.cam_cell.Vdd += curr_alpha * vdd_real[ram_cell_tech_type]; + g_tp.cam_cell.Vdd_default += curr_alpha * vdd[ram_cell_tech_type]; + g_tp.cam_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; + g_tp.cam_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; + g_tp.cam_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; + g_tp.cam_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; + g_tp.cam_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; + g_tp.cam_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; + g_tp.cam_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; + g_tp.cam_cell.C_junc_sidewall = 0.25e-15; // F/micron + g_tp.cam_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; + g_tp.cam_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; + g_tp.cam_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; + g_tp.cam_cell.n_to_p_eff_curr_drv_ratio += + curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; + g_tp.cam_cell.long_channel_leakage_reduction += + curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; + g_tp.cam_cell.I_off_n += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //*pow(g_tp.cam_cell.Vdd/g_tp.cam_cell.Vdd_default,4); + g_tp.cam_cell.I_off_p += + curr_alpha * + I_off_n[ram_cell_tech_type] + [g_ip->temp - + 300]; //**pow(g_tp.cam_cell.Vdd/g_tp.cam_cell.Vdd_default,4); + g_tp.cam_cell.I_g_on_n += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + g_tp.cam_cell.I_g_on_p += + curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; + + g_tp.dram.cell_a_w += curr_alpha * curr_Wmemcella_dram; + g_tp.dram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_dram; + g_tp.dram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_dram; + area_cell_dram += curr_alpha * curr_area_cell_dram; + asp_ratio_cell_dram += curr_alpha * curr_asp_ratio_cell_dram; + + g_tp.sram.cell_a_w += curr_alpha * curr_Wmemcella_sram; + g_tp.sram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_sram; + g_tp.sram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_sram; + area_cell_sram += curr_alpha * curr_area_cell_sram; + asp_ratio_cell_sram += curr_alpha * curr_asp_ratio_cell_sram; + + g_tp.cam.cell_a_w += curr_alpha * curr_Wmemcella_cam; // sheng + g_tp.cam.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_cam; + g_tp.cam.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_cam; + area_cell_cam += curr_alpha * curr_area_cell_cam; + asp_ratio_cell_cam += curr_alpha * curr_asp_ratio_cell_cam; + + // Sense amplifier latch Gm calculation + mobility_eff_periph_global += + curr_alpha * mobility_eff[peri_global_tech_type]; + Vdsat_periph_global += curr_alpha * Vdsat[peri_global_tech_type]; + + // Empirical undifferetiated core/FU coefficient + g_tp.scaling_factor.logic_scaling_co_eff += + curr_alpha * curr_logic_scaling_co_eff; + g_tp.scaling_factor.core_tx_density += curr_alpha * curr_core_tx_density; + g_tp.chip_layout_overhead += curr_alpha * curr_chip_layout_overhead; + g_tp.macro_layout_overhead += curr_alpha * curr_macro_layout_overhead; + g_tp.sckt_co_eff += curr_alpha * curr_sckt_co_eff; + } + + // Currently we are not modeling the resistance/capacitance of poly anywhere. + // following data are continuous function (or data have been processed) does + // not need linear interpolation + g_tp.w_comp_inv_p1 = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + g_tp.w_comp_inv_n1 = + 7.5 * g_ip->F_sz_um; // this was 6 micron for the 0.8 micron process + g_tp.w_comp_inv_p2 = + 25 * g_ip->F_sz_um; // this was 20 micron for the 0.8 micron process + g_tp.w_comp_inv_n2 = + 15 * g_ip->F_sz_um; // this was 12 micron for the 0.8 micron process + g_tp.w_comp_inv_p3 = + 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron process + g_tp.w_comp_inv_n3 = + 30 * g_ip->F_sz_um; // this was 24 micron for the 0.8 micron process + g_tp.w_eval_inv_p = + 100 * g_ip->F_sz_um; // this was 80 micron for the 0.8 micron process + g_tp.w_eval_inv_n = + 50 * g_ip->F_sz_um; // this was 40 micron for the 0.8 micron process + g_tp.w_comp_n = + 12.5 * g_ip->F_sz_um; // this was 10 micron for the 0.8 micron process + g_tp.w_comp_p = + 37.5 * g_ip->F_sz_um; // this was 30 micron for the 0.8 micron process + + g_tp.MIN_GAP_BET_P_AND_N_DIFFS = 5 * g_ip->F_sz_um; + g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS = 1.5 * g_ip->F_sz_um; + g_tp.HPOWERRAIL = 2 * g_ip->F_sz_um; + g_tp.cell_h_def = 50 * g_ip->F_sz_um; + g_tp.w_poly_contact = g_ip->F_sz_um; + g_tp.spacing_poly_to_contact = g_ip->F_sz_um; + g_tp.spacing_poly_to_poly = 1.5 * g_ip->F_sz_um; + g_tp.ram_wl_stitching_overhead_ = 7.5 * g_ip->F_sz_um; + + g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2; + g_tp.max_w_nmos_ = 100 * g_ip->F_sz_um; + g_tp.w_iso = 12.5 * g_ip->F_sz_um; // was 10 micron for the 0.8 micron + // process + g_tp.w_sense_n = 3.75 * g_ip->F_sz_um; // sense amplifier N-trans; was 3 + // micron for the 0.8 micron process + g_tp.w_sense_p = 7.5 * g_ip->F_sz_um; // sense amplifier P-trans; was 6 + // micron for the 0.8 micron process + g_tp.w_sense_en = 5 * g_ip->F_sz_um; // Sense enable transistor of the sense + // amplifier; was 4 micron for the 0.8 + // micron process + g_tp.w_nmos_b_mux = 6 * g_tp.min_w_nmos_; + g_tp.w_nmos_sa_mux = 6 * g_tp.min_w_nmos_; + + if (ram_cell_tech_type == comm_dram) { + g_tp.max_w_nmos_dec = 8 * g_ip->F_sz_um; + g_tp.h_dec = 8; // in the unit of memory cell height + } + else { + g_tp.max_w_nmos_dec = g_tp.max_w_nmos_; + g_tp.h_dec = 4; // in the unit of memory cell height + } + + g_tp.peri_global.C_overlap = 0.2 * g_tp.peri_global.C_g_ideal; + g_tp.sram_cell.C_overlap = 0.2 * g_tp.sram_cell.C_g_ideal; + g_tp.cam_cell.C_overlap = 0.2 * g_tp.cam_cell.C_g_ideal; + + g_tp.dram_acc.C_overlap = 0.2 * g_tp.dram_acc.C_g_ideal; + g_tp.dram_acc.R_nch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_n; + // // g_tp.dram_acc.R_pch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_p; + + g_tp.dram_wl.C_overlap = 0.2 * g_tp.dram_wl.C_g_ideal; + + double gmn_sense_amp_latch = + (mobility_eff_periph_global / 2) * g_tp.peri_global.C_ox * + (g_tp.w_sense_n / g_tp.peri_global.l_elec) * Vdsat_periph_global; + double gmp_sense_amp_latch = + gmp_to_gmn_multiplier_periph_global * gmn_sense_amp_latch; + g_tp.gm_sense_amp_latch = + gmn_sense_amp_latch + + gmp_sense_amp_latch * + pow((g_tp.peri_global.Vdd - g_tp.peri_global.Vth) / + (g_tp.peri_global.Vdd_default - g_tp.peri_global.Vth), + 1.3) / + (g_tp.peri_global.Vdd / g_tp.peri_global.Vdd_default); + + g_tp.dram.b_w = sqrt(area_cell_dram / (asp_ratio_cell_dram)); + g_tp.dram.b_h = asp_ratio_cell_dram * g_tp.dram.b_w; + g_tp.sram.b_w = sqrt(area_cell_sram / (asp_ratio_cell_sram)); + g_tp.sram.b_h = asp_ratio_cell_sram * g_tp.sram.b_w; + g_tp.cam.b_w = sqrt(area_cell_cam / (asp_ratio_cell_cam)); // Sheng + g_tp.cam.b_h = asp_ratio_cell_cam * g_tp.cam.b_w; + + g_tp.dram.Vbitpre = g_tp.dram_cell_Vdd; + g_tp.sram.Vbitpre = g_tp.sram_cell.Vdd; // vdd[ram_cell_tech_type]; + g_tp.cam.Vbitpre = g_tp.cam_cell.Vdd; // vdd[ram_cell_tech_type];//Sheng + pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + g_tp.w_pmos_bl_precharge = 6 * pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; + g_tp.w_pmos_bl_eq = pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; + + // DVS and power-gating voltage finalization + if ((g_tp.sram_cell.Vcc_min_default > g_tp.sram_cell.Vdd || + g_tp.peri_global.Vdd < g_tp.peri_global.Vdd_default * 0.75 || + g_tp.sram_cell.Vdd < g_tp.sram_cell.Vdd_default * 0.75) && + (!g_ip->is_main_mem)) { + cerr << "User defined Vdd is too low.\n\n" << endl; + exit(0); + } + + if (g_ip->specific_vcc_min) { + g_tp.sram_cell.Vcc_min = g_ip->user_defined_vcc_min; + g_tp.peri_global.Vcc_min = g_ip->user_defined_vcc_min; + g_tp.sram.Vbitfloating = + g_tp.sram.Vbitpre * 0.7 * + (g_tp.sram_cell.Vcc_min / g_tp.peri_global.Vcc_min_default); + // if (g_ip->user_defined_vcc_min < g_tp.peri_global.Vcc_min_default) + // { + // g_tp.peri_global.Vcc_min = g_ip->user_defined_vcc_min; + // } + // else { + // + // } + } + else { + g_tp.sram_cell.Vcc_min = g_tp.sram_cell.Vcc_min_default; + g_tp.peri_global.Vcc_min = g_tp.peri_global.Vcc_min_default; + g_tp.sram.Vbitfloating = g_tp.sram.Vbitpre * 0.7; + } + + if (g_tp.sram_cell.Vcc_min < + g_tp.sram_cell.Vcc_min_default) // if want to compute multiple + // power-gating vdd settings in one run, + // should have multiple results copies + // (each copy containing such flag) in + // update_pg () + { + g_ip->user_defined_vcc_underflow = true; + } + else { + g_ip->user_defined_vcc_underflow = false; + } + + if ((g_tp.sram_cell.Vcc_min > g_tp.sram_cell.Vdd || + g_tp.peri_global.Vcc_min > g_tp.peri_global.Vdd) && + (!g_ip->is_main_mem)) { + cerr << "User defined power-saving supply voltage cannot be lower than Vdd " + "(DVS0).\n\n" + << endl; + exit(0); + } + double wire_pitch[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], + wire_r_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + wire_c_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + horiz_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + vert_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES] + [NUMBER_WIRE_TYPES], + aspect_ratio[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], + miller_value[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], + ild_thickness[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES]; + + for (iter = 0; iter <= 1; ++iter) { + // linear interpolation + if (iter == 0) { + tech = tech_lo; + if (tech_lo == tech_hi) { + curr_alpha = 1; + } + else { + curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); + } + } + else { + tech = tech_hi; + if (tech_lo == tech_hi) { + break; + } + else { + curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); + } + } + + if (tech == 180) { + // Aggressive projections + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // micron + aspect_ratio[0][0] = 2.0; + wire_width = wire_pitch[0][0] / 2; // micron + wire_thickness = aspect_ratio[0][0] * wire_width; // micron + wire_spacing = wire_pitch[0][0] - wire_width; // micron + barrier_thickness = 0.017; // micron + dishing_thickness = 0; // micron + alpha_scatter = 1; + wire_r_per_micron[0][0] = wire_resistance( + CU_RESISTIVITY, wire_width, wire_thickness, barrier_thickness, + dishing_thickness, alpha_scatter); // ohm/micron + ild_thickness[0][0] = 0.75; // micron + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 2.709; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; // F/micron + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], + fringe_cap); // F/micron. + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 2.4; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.75; // micron + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 2.709; + vert_dielectric_constant[0][1] = 3.9; + fringe_cap = 0.115e-15; // F/micron + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 2.2; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 1.5; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 2.709; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.017; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.75; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 3.038; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.75; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 3.038; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 1.98; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 3.038; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.18; + wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.18); + wire_r_per_micron[1][3] = 12 / 0.18; + } + else if (tech == 90) { + // Aggressive projections + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // micron + aspect_ratio[0][0] = 2.4; + wire_width = wire_pitch[0][0] / 2; // micron + wire_thickness = aspect_ratio[0][0] * wire_width; // micron + wire_spacing = wire_pitch[0][0] - wire_width; // micron + barrier_thickness = 0.01; // micron + dishing_thickness = 0; // micron + alpha_scatter = 1; + wire_r_per_micron[0][0] = wire_resistance( + CU_RESISTIVITY, wire_width, wire_thickness, barrier_thickness, + dishing_thickness, alpha_scatter); // ohm/micron + ild_thickness[0][0] = 0.48; // micron + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 2.709; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; // F/micron + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], + fringe_cap); // F/micron. + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 2.4; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.48; // micron + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 2.709; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 2.7; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.96; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 2.709; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.008; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.48; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 3.038; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.48; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 3.038; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 1.1; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 3.038; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.09; + wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.09); + wire_r_per_micron[1][3] = 12 / 0.09; + } + else if (tech == 65) { + // Aggressive projections + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[0][0] = 2.7; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.405; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 2.303; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 2.7; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.405; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 2.303; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 2.8; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.81; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 2.303; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.006; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.405; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.734; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.405; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.734; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.77; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.734; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.065; + wire_c_per_micron[1][3] = 52.5e-15 / (256 * 2 * 0.065); + wire_r_per_micron[1][3] = 12 / 0.065; + } + else if (tech == 45) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.315; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.958; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 3.0; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.315; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.958; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.63; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.958; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.004; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.315; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.46; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.315; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.46; + vert_dielectric_constant[1][1] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.55; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.46; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.045; + wire_c_per_micron[1][3] = 37.5e-15 / (256 * 2 * 0.045); + wire_r_per_micron[1][3] = 12 / 0.045; + } + else if (tech == 32) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.21; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.664; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 3.0; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.21; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.664; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.42; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.664; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.003; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.21; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.214; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + aspect_ratio[1][1] = 2.0; + wire_width = wire_pitch[1][1] / 2; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.21; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.214; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.385; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.214; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.032; // micron + wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.032); // F/micron + wire_r_per_micron[1][3] = 12 / 0.032; // ohm/micron + } + else if (tech == 22) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // local + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.15; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.414; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; // semi-global + wire_width = wire_pitch[0][1] / 2; + aspect_ratio[0][1] = 3.0; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.15; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.414; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; // global + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.3; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.414; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // //************************* + // wire_pitch[0][4] = 16 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][4] - wire_width; + // wire_r_per_micron[0][4] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][5] = 24 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][5] - wire_width; + // wire_r_per_micron[0][5] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][6] = 32 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][6] - wire_width; + // wire_r_per_micron[0][6] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + //************************* + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.003; + dishing_thickness = 0; + alpha_scatter = 1.05; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.15; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 2.104; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.15; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 2.104; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.275; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 2.104; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.022; // micron + wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.022); // F/micron + wire_r_per_micron[1][3] = 12 / 0.022; // ohm/micron + + //****************** + // wire_pitch[1][4] = 16 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][4] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][4] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][5] = 24 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][5] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][5] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][6] = 32 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][6] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][6] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + } + + else if (tech == 16) { + // Aggressive projections. + wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; // local + aspect_ratio[0][0] = 3.0; + wire_width = wire_pitch[0][0] / 2; + wire_thickness = aspect_ratio[0][0] * wire_width; + wire_spacing = wire_pitch[0][0] - wire_width; + barrier_thickness = 0; + dishing_thickness = 0; + alpha_scatter = 1; + wire_r_per_micron[0][0] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][0] = 0.108; + miller_value[0][0] = 1.5; + horiz_dielectric_constant[0][0] = 1.202; + vert_dielectric_constant[0][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[0][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][0], + miller_value[0][0], horiz_dielectric_constant[0][0], + vert_dielectric_constant[0][0], fringe_cap); + + wire_pitch[0][1] = 4 * g_ip->F_sz_um; // semi-global + aspect_ratio[0][1] = 3.0; + wire_width = wire_pitch[0][1] / 2; + wire_thickness = aspect_ratio[0][1] * wire_width; + wire_spacing = wire_pitch[0][1] - wire_width; + wire_r_per_micron[0][1] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][1] = 0.108; + miller_value[0][1] = 1.5; + horiz_dielectric_constant[0][1] = 1.202; + vert_dielectric_constant[0][1] = 3.9; + wire_c_per_micron[0][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][1], + miller_value[0][1], horiz_dielectric_constant[0][1], + vert_dielectric_constant[0][1], fringe_cap); + + wire_pitch[0][2] = 8 * g_ip->F_sz_um; // global + aspect_ratio[0][2] = 3.0; + wire_width = wire_pitch[0][2] / 2; + wire_thickness = aspect_ratio[0][2] * wire_width; + wire_spacing = wire_pitch[0][2] - wire_width; + wire_r_per_micron[0][2] = + wire_resistance(BULK_CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[0][2] = 0.216; + miller_value[0][2] = 1.5; + horiz_dielectric_constant[0][2] = 1.202; + vert_dielectric_constant[0][2] = 3.9; + wire_c_per_micron[0][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[0][2], + miller_value[0][2], horiz_dielectric_constant[0][2], + vert_dielectric_constant[0][2], fringe_cap); + + // //************************* + // wire_pitch[0][4] = 16 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][4] - wire_width; + // wire_r_per_micron[0][4] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][5] = 24 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][5] - wire_width; + // wire_r_per_micron[0][5] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + // + // wire_pitch[0][6] = 32 * g_ip.F_sz_um;//global + // aspect_ratio = 3.0; + // wire_width = wire_pitch[0][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[0][6] - wire_width; + // wire_r_per_micron[0][6] = wire_resistance(BULK_CU_RESISTIVITY, + // wire_width, + // wire_thickness, barrier_thickness, + // dishing_thickness, alpha_scatter); + // ild_thickness = 0.3; + // wire_c_per_micron[0][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, + // ild_thickness, miller_value, + // horiz_dielectric_constant, vert_dielectric_constant, + // fringe_cap); + //************************* + + // Conservative projections + wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; + aspect_ratio[1][0] = 2.0; + wire_width = wire_pitch[1][0] / 2; + wire_thickness = aspect_ratio[1][0] * wire_width; + wire_spacing = wire_pitch[1][0] - wire_width; + barrier_thickness = 0.002; + dishing_thickness = 0; + alpha_scatter = 1.05; + wire_r_per_micron[1][0] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][0] = 0.108; + miller_value[1][0] = 1.5; + horiz_dielectric_constant[1][0] = 1.998; + vert_dielectric_constant[1][0] = 3.9; + fringe_cap = 0.115e-15; + wire_c_per_micron[1][0] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][0], + miller_value[1][0], horiz_dielectric_constant[1][0], + vert_dielectric_constant[1][0], fringe_cap); + + wire_pitch[1][1] = 4 * g_ip->F_sz_um; + wire_width = wire_pitch[1][1] / 2; + aspect_ratio[1][1] = 2.0; + wire_thickness = aspect_ratio[1][1] * wire_width; + wire_spacing = wire_pitch[1][1] - wire_width; + wire_r_per_micron[1][1] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][1] = 0.108; + miller_value[1][1] = 1.5; + horiz_dielectric_constant[1][1] = 1.998; + vert_dielectric_constant[1][1] = 3.9; + wire_c_per_micron[1][1] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][1], + miller_value[1][1], horiz_dielectric_constant[1][1], + vert_dielectric_constant[1][1], fringe_cap); + + wire_pitch[1][2] = 8 * g_ip->F_sz_um; + aspect_ratio[1][2] = 2.2; + wire_width = wire_pitch[1][2] / 2; + wire_thickness = aspect_ratio[1][2] * wire_width; + wire_spacing = wire_pitch[1][2] - wire_width; + dishing_thickness = 0.1 * wire_thickness; + wire_r_per_micron[1][2] = + wire_resistance(CU_RESISTIVITY, wire_width, wire_thickness, + barrier_thickness, dishing_thickness, alpha_scatter); + ild_thickness[1][2] = 0.198; + miller_value[1][2] = 1.5; + horiz_dielectric_constant[1][2] = 1.998; + vert_dielectric_constant[1][2] = 3.9; + wire_c_per_micron[1][2] = wire_capacitance( + wire_width, wire_thickness, wire_spacing, ild_thickness[1][2], + miller_value[1][2], horiz_dielectric_constant[1][2], + vert_dielectric_constant[1][2], fringe_cap); + // Nominal projections for commodity DRAM wordline/bitline + wire_pitch[1][3] = 2 * 0.016; // micron + wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.016); // F/micron + wire_r_per_micron[1][3] = 12 / 0.016; // ohm/micron + + //****************** + // wire_pitch[1][4] = 16 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][4] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][4] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][4] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][4] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][5] = 24 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][5] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][5] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][5] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][5] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + // + // wire_pitch[1][6] = 32 * g_ip.F_sz_um; + // aspect_ratio = 2.2; + // wire_width = wire_pitch[1][6] / 2; + // wire_thickness = aspect_ratio * wire_width; + // wire_spacing = wire_pitch[1][6] - wire_width; + // dishing_thickness = 0.1 * wire_thickness; + // wire_r_per_micron[1][6] = wire_resistance(CU_RESISTIVITY, + // wire_width, wire_thickness, + // barrier_thickness, dishing_thickness, alpha_scatter); + // ild_thickness = 0.275; + // wire_c_per_micron[1][6] = wire_capacitance(wire_width, + // wire_thickness, wire_spacing, ild_thickness, + // miller_value, horiz_dielectric_constant, + // vert_dielectric_constant, fringe_cap); + } + g_tp.wire_local.pitch += + curr_alpha * wire_pitch[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.R_per_um += + curr_alpha * + wire_r_per_micron[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.C_per_um += + curr_alpha * + wire_c_per_micron[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.aspect_ratio += + curr_alpha * aspect_ratio[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.ild_thickness += + curr_alpha * ild_thickness[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.miller_value += + curr_alpha * miller_value[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.horiz_dielectric_constant += + curr_alpha * + horiz_dielectric_constant[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + g_tp.wire_local.vert_dielectric_constant += + curr_alpha * + vert_dielectric_constant[g_ip->ic_proj_type] + [(ram_cell_tech_type == comm_dram) ? 3 : 0]; + + g_tp.wire_inside_mat.pitch += + curr_alpha * wire_pitch[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.R_per_um += + curr_alpha * + wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.C_per_um += + curr_alpha * + wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.aspect_ratio += + curr_alpha * aspect_ratio[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.ild_thickness += + curr_alpha * ild_thickness[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.miller_value += + curr_alpha * miller_value[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.horiz_dielectric_constant += + curr_alpha * + horiz_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + g_tp.wire_inside_mat.vert_dielectric_constant += + curr_alpha * + vert_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; + + g_tp.wire_outside_mat.pitch += + curr_alpha * wire_pitch[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.R_per_um += + curr_alpha * + wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.C_per_um += + curr_alpha * + wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.aspect_ratio += + curr_alpha * aspect_ratio[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.ild_thickness += + curr_alpha * ild_thickness[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.miller_value += + curr_alpha * miller_value[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.horiz_dielectric_constant += + curr_alpha * + horiz_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + g_tp.wire_outside_mat.vert_dielectric_constant += + curr_alpha * + vert_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; + + g_tp.unit_len_wire_del = + g_tp.wire_inside_mat.R_per_um * g_tp.wire_inside_mat.C_per_um / 2; + + g_tp.sense_delay += curr_alpha * SENSE_AMP_D; + g_tp.sense_dy_power += curr_alpha * SENSE_AMP_P; + // g_tp.horiz_dielectric_constant += horiz_dielectric_constant; + // g_tp.vert_dielectric_constant += vert_dielectric_constant; + // g_tp.aspect_ratio += aspect_ratio; + // g_tp.miller_value += miller_value; + // g_tp.ild_thickness += ild_thickness; + } + g_tp.fringe_cap = fringe_cap; + + double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1); + double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(); + double c_load = gate_C(g_tp.min_w_nmos_ * (1 + p_to_n_sizing_r), 0.0); + double tf = rd * c_load; + g_tp.kinv = horowitz(0, tf, 0.5, 0.5, RISE); + double KLOAD = 1; + c_load = KLOAD * (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, + g_tp.cell_h_def) + + gate_C(g_tp.min_w_nmos_ * 4 * (1 + p_to_n_sizing_r), 0.0)); + tf = rd * c_load; + g_tp.FO4 = horowitz(0, tf, 0.5, 0.5, RISE); +} + +} // namespace cacti diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/uca.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/uca.cc new file mode 100644 index 0000000000..b7922b0202 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/uca.cc @@ -0,0 +1,478 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include +#include + +#include "uca.h" +using namespace cacti; + +UCA::UCA(const DynamicParameter &dyn_p) + : dp(dyn_p), bank(dp), nbanks(g_ip->nbanks), refresh_power(0) { + int num_banks_ver_dir = + 1 << ((bank.area.h > bank.area.w) ? _log2(nbanks) / 2 + : (_log2(nbanks) - _log2(nbanks) / 2)); + int num_banks_hor_dir = nbanks / num_banks_ver_dir; + + if (dp.use_inp_params) { + RWP = dp.num_rw_ports; + ERP = dp.num_rd_ports; + EWP = dp.num_wr_ports; + SCHP = dp.num_search_ports; + } + else { + RWP = g_ip->num_rw_ports; + ERP = g_ip->num_rd_ports; + EWP = g_ip->num_wr_ports; + SCHP = g_ip->num_search_ports; + } + + num_addr_b_bank = + (dp.number_addr_bits_mat + dp.number_subbanks_decode) * (RWP + ERP + EWP); + num_di_b_bank = dp.num_di_b_bank_per_port * (RWP + EWP); + num_do_b_bank = dp.num_do_b_bank_per_port * (RWP + ERP); + num_si_b_bank = dp.num_si_b_bank_per_port * SCHP; + num_so_b_bank = dp.num_so_b_bank_per_port * SCHP; + + if (!dp.fully_assoc && !dp.pure_cam) { + if (g_ip->fast_access && dp.is_tag == false) { + num_do_b_bank *= g_ip->data_assoc; + } + + htree_in_add = + new Htree2(g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, + num_di_b_bank, 0, num_do_b_bank, 0, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Add_htree, true); + htree_in_data = + new Htree2(g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, + num_di_b_bank, 0, num_do_b_bank, 0, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_in_htree, true); + htree_out_data = + new Htree2(g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, + num_di_b_bank, 0, num_do_b_bank, 0, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_out_htree, true); + } + + else { + htree_in_add = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Add_htree, true); + htree_in_data = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_in_htree, true); + htree_out_data = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_out_htree, true); + htree_in_search = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_in_htree, true); + htree_out_search = new Htree2( + g_ip->wt, bank.area.w, bank.area.h, num_addr_b_bank, num_di_b_bank, + num_si_b_bank, num_do_b_bank, num_so_b_bank, num_banks_ver_dir * 2, + num_banks_hor_dir * 2, Data_out_htree, true); + } + + area.w = htree_in_data->area.w; + area.h = htree_in_data->area.h; + + area_all_dataramcells = + bank.mat.subarray.get_total_cell_area() * dp.num_subarrays * g_ip->nbanks; + // cout<<"area cell"<delay + bank.htree_in_add->delay; + double max_delay_before_row_decoder = + delay_array_to_mat + bank.mat.r_predec->delay; + delay_array_to_sa_mux_lev_1_decoder = delay_array_to_mat + + bank.mat.sa_mux_lev_1_predec->delay + + bank.mat.sa_mux_lev_1_dec->delay; + delay_array_to_sa_mux_lev_2_decoder = delay_array_to_mat + + bank.mat.sa_mux_lev_2_predec->delay + + bank.mat.sa_mux_lev_2_dec->delay; + double delay_inside_mat = + bank.mat.row_dec->delay + bank.mat.delay_bitline + bank.mat.delay_sa; + + delay_before_subarray_output_driver = + MAX(MAX(max_delay_before_row_decoder + delay_inside_mat, // row_path + delay_array_to_mat + bank.mat.b_mux_predec->delay + + bank.mat.bit_mux_dec->delay + bank.mat.delay_sa), // col_path + MAX(delay_array_to_sa_mux_lev_1_decoder, // sa_mux_lev_1_path + delay_array_to_sa_mux_lev_2_decoder)); // sa_mux_lev_2_path + delay_from_subarray_out_drv_to_out = bank.mat.delay_subarray_out_drv_htree + + bank.htree_out_data->delay + + htree_out_data->delay; + access_time = bank.mat.delay_comparator; + + double ram_delay_inside_mat; + if (dp.fully_assoc) { + // delay of FA contains both CAM tag and RAM data + { // delay of CAM + ram_delay_inside_mat = + bank.mat.delay_bitline + bank.mat.delay_matchchline; + access_time = htree_in_add->delay + bank.htree_in_add->delay; + // delay of fully-associative data array + access_time += ram_delay_inside_mat + delay_from_subarray_out_drv_to_out; + } + } + else { + access_time = delay_before_subarray_output_driver + + delay_from_subarray_out_drv_to_out; // data_acc_path + } + + if (dp.is_main_mem) { + double t_rcd = max_delay_before_row_decoder + delay_inside_mat; + double cas_latency = MAX(delay_array_to_sa_mux_lev_1_decoder, + delay_array_to_sa_mux_lev_2_decoder) + + delay_from_subarray_out_drv_to_out; + access_time = t_rcd + cas_latency; + } + + double temp; + + if (!dp.fully_assoc) { + temp = delay_inside_mat + bank.mat.delay_wl_reset + + bank.mat.delay_bl_restore; // TODO: Sheng: revisit + if (dp.is_dram) { + temp += bank.mat.delay_writeback; // temp stores random cycle time + } + + temp = MAX(temp, bank.mat.r_predec->delay); + temp = MAX(temp, bank.mat.b_mux_predec->delay); + temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay); + temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay); + } + else { + ram_delay_inside_mat = bank.mat.delay_bitline + bank.mat.delay_matchchline; + temp = ram_delay_inside_mat + bank.mat.delay_cam_sl_restore + + bank.mat.delay_cam_ml_reset + bank.mat.delay_bl_restore + + bank.mat.delay_hit_miss_reset + bank.mat.delay_wl_reset; + + temp = MAX(temp, bank.mat.b_mux_predec->delay); // TODO: Sheng revisit + // whether distinguish cam + // and ram bitline etc. + temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay); + temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay); + } + + // The following is true only if the input parameter "repeaters_in_htree" is + // set to false --Nav + if (g_ip->rpters_in_htree == false) { + temp = MAX(temp, bank.htree_in_add->max_unpipelined_link_delay); + } + cycle_time = temp; + + double delay_req_network = max_delay_before_row_decoder; + double delay_rep_network = delay_from_subarray_out_drv_to_out; + multisubbank_interleave_cycle_time = + MAX(delay_req_network, delay_rep_network); + + if (dp.is_main_mem) { + multisubbank_interleave_cycle_time = htree_in_add->delay; + precharge_delay = htree_in_add->delay + bank.htree_in_add->delay + + bank.mat.delay_writeback + bank.mat.delay_wl_reset + + bank.mat.delay_bl_restore; + cycle_time = access_time + precharge_delay; + } + else { + precharge_delay = 0; + } + + // double dram_array_availability = 0; + // if (dp.is_dram) { + // dram_array_availability = + // (1 - dp.num_r_subarray * cycle_time / dp.dram_refresh_period) * 100; + // } + + return outrisetime; +} + +// note: currently, power numbers are for a bank of an array +void UCA::compute_power_energy() { + bank.compute_power_energy(); + power = bank.power; + + power_routing_to_bank.readOp.dynamic = + htree_in_add->power.readOp.dynamic + htree_out_data->power.readOp.dynamic; + power_routing_to_bank.writeOp.dynamic = + htree_in_add->power.readOp.dynamic + htree_in_data->power.readOp.dynamic; + if (dp.fully_assoc || dp.pure_cam) { + power_routing_to_bank.searchOp.dynamic = + htree_in_search->power.searchOp.dynamic + + htree_out_search->power.searchOp.dynamic; + } + power_routing_to_bank.readOp.leakage += htree_in_add->power.readOp.leakage + + htree_in_data->power.readOp.leakage + + htree_out_data->power.readOp.leakage; + + power_routing_to_bank.readOp.power_gated_leakage += + htree_in_add->power.readOp.power_gated_leakage + + htree_in_data->power.readOp.power_gated_leakage + + htree_out_data->power.readOp.power_gated_leakage; + + power_routing_to_bank.readOp.gate_leakage += + htree_in_add->power.readOp.gate_leakage + + htree_in_data->power.readOp.gate_leakage + + htree_out_data->power.readOp.gate_leakage; + if (dp.fully_assoc || dp.pure_cam) { + power_routing_to_bank.readOp.leakage += + htree_in_search->power.readOp.leakage + + htree_out_search->power.readOp.leakage; + power_routing_to_bank.readOp.gate_leakage += + htree_in_search->power.readOp.gate_leakage + + htree_out_search->power.readOp.gate_leakage; + } + + power.searchOp.dynamic += power_routing_to_bank.searchOp.dynamic; + power.readOp.dynamic += power_routing_to_bank.readOp.dynamic; + power.readOp.leakage += power_routing_to_bank.readOp.leakage; + power.readOp.power_gated_leakage += + power_routing_to_bank.readOp.power_gated_leakage; + power.readOp.gate_leakage += power_routing_to_bank.readOp.gate_leakage; + + // calculate total write energy per access + power.writeOp.dynamic = + power.readOp.dynamic - + bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir + + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir - + power_routing_to_bank.readOp.dynamic + + power_routing_to_bank.writeOp.dynamic + + bank.htree_in_data->power.readOp.dynamic - + bank.htree_out_data->power.readOp.dynamic; + + if (dp.is_dram == false) { + power.writeOp.dynamic -= + bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; + } + + dyn_read_energy_from_closed_page = power.readOp.dynamic; + dyn_read_energy_from_open_page = + power.readOp.dynamic - + (bank.mat.r_predec->power.readOp.dynamic + + bank.mat.power_row_decoders.readOp.dynamic + + bank.mat.power_bl_precharge_eq_drv.readOp.dynamic + + bank.mat.power_sa.readOp.dynamic + + bank.mat.power_bitline.readOp.dynamic) * + dp.num_act_mats_hor_dir; + + dyn_read_energy_remaining_words_in_burst = + (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1) * + ((bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + + bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + + bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + + bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic + + bank.mat.power_subarray_out_drv.readOp.dynamic) * + dp.num_act_mats_hor_dir + + bank.htree_out_data->power.readOp.dynamic + + power_routing_to_bank.readOp.dynamic); + dyn_read_energy_from_closed_page += dyn_read_energy_remaining_words_in_burst; + dyn_read_energy_from_open_page += dyn_read_energy_remaining_words_in_burst; + + activate_energy = htree_in_add->power.readOp.dynamic + + bank.htree_in_add->power_bit.readOp.dynamic * + bank.num_addr_b_routed_to_mat_for_act + + (bank.mat.r_predec->power.readOp.dynamic + + bank.mat.power_row_decoders.readOp.dynamic + + bank.mat.power_sa.readOp.dynamic) * + dp.num_act_mats_hor_dir; + read_energy = (htree_in_add->power.readOp.dynamic + + bank.htree_in_add->power_bit.readOp.dynamic * + bank.num_addr_b_routed_to_mat_for_rd_or_wr + + (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + + bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + + bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + + bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic + + bank.mat.power_subarray_out_drv.readOp.dynamic) * + dp.num_act_mats_hor_dir + + bank.htree_out_data->power.readOp.dynamic + + htree_in_data->power.readOp.dynamic) * + g_ip->burst_len; + write_energy = (htree_in_add->power.readOp.dynamic + + bank.htree_in_add->power_bit.readOp.dynamic * + bank.num_addr_b_routed_to_mat_for_rd_or_wr + + htree_in_data->power.readOp.dynamic + + bank.htree_in_data->power.readOp.dynamic + + (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + + bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + + bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + + bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic) * + dp.num_act_mats_hor_dir) * + g_ip->burst_len; + precharge_energy = (bank.mat.power_bitline.readOp.dynamic + + bank.mat.power_bl_precharge_eq_drv.readOp.dynamic) * + dp.num_act_mats_hor_dir; + + // The follow 6 parameters are only used in DRAM/eDRAM output for now + leak_power_subbank_closed_page = + (bank.mat.r_predec->power.readOp.leakage + + bank.mat.b_mux_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.leakage + + bank.mat.power_row_decoders.readOp.leakage + + bank.mat.power_bit_mux_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage + + bank.mat.leak_power_sense_amps_closed_page_state) * + dp.num_act_mats_hor_dir; + + leak_power_subbank_closed_page += + (bank.mat.r_predec->power.readOp.gate_leakage + + bank.mat.b_mux_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage + + bank.mat.power_row_decoders.readOp.gate_leakage + + bank.mat.power_bit_mux_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * + dp.num_act_mats_hor_dir; //+ + // bank.mat.leak_power_sense_amps_closed_page_state) * + // dp.num_act_mats_hor_dir; + + leak_power_subbank_open_page = + (bank.mat.r_predec->power.readOp.leakage + + bank.mat.b_mux_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.leakage + + bank.mat.power_row_decoders.readOp.leakage + + bank.mat.power_bit_mux_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage + + bank.mat.leak_power_sense_amps_open_page_state) * + dp.num_act_mats_hor_dir; + + leak_power_subbank_open_page += + (bank.mat.r_predec->power.readOp.gate_leakage + + bank.mat.b_mux_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage + + bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage + + bank.mat.power_row_decoders.readOp.gate_leakage + + bank.mat.power_bit_mux_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage + + bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * + dp.num_act_mats_hor_dir; + // bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir; + + leak_power_request_and_reply_networks = + power_routing_to_bank.readOp.leakage + + bank.htree_in_add->power.readOp.leakage + + bank.htree_in_data->power.readOp.leakage + + bank.htree_out_data->power.readOp.leakage; + + leak_power_request_and_reply_networks += + power_routing_to_bank.readOp.gate_leakage + + bank.htree_in_add->power.readOp.gate_leakage + + bank.htree_in_data->power.readOp.gate_leakage + + bank.htree_out_data->power.readOp.gate_leakage; + + if (dp.fully_assoc || dp.pure_cam) { + leak_power_request_and_reply_networks += + htree_in_search->power.readOp.leakage + + htree_out_search->power.readOp.leakage; + leak_power_request_and_reply_networks += + htree_in_search->power.readOp.gate_leakage + + htree_out_search->power.readOp.gate_leakage; + } + + if (dp.is_dram) { // if DRAM, add contribution of power spent in row + // predecoder drivers, blocks and decoders to refresh power + refresh_power = + (bank.mat.r_predec->power.readOp.dynamic * dp.num_act_mats_hor_dir + + bank.mat.row_dec->power.readOp.dynamic) * + dp.num_r_subarray * dp.num_subarrays; + refresh_power += bank.mat.per_bitline_read_energy * dp.num_c_subarray * + dp.num_r_subarray * dp.num_subarrays; + refresh_power += bank.mat.power_bl_precharge_eq_drv.readOp.dynamic * + dp.num_act_mats_hor_dir; + refresh_power += bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; + refresh_power /= dp.dram_refresh_period; + } + // The follow 6 parameters are only used in DRAM/eDRAM output for now + + if (dp.is_tag == false) { + power.readOp.dynamic = dyn_read_energy_from_closed_page; + power.writeOp.dynamic = + dyn_read_energy_from_closed_page - + dyn_read_energy_remaining_words_in_burst - + bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir + + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir + + (power_routing_to_bank.writeOp.dynamic - + power_routing_to_bank.readOp.dynamic - + bank.htree_out_data->power.readOp.dynamic + + bank.htree_in_data->power.readOp.dynamic) * + (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1); // FIXME + + if (dp.is_dram == false) { + power.writeOp.dynamic -= + bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; + } + } + + // if DRAM, add refresh power to total leakage + if (dp.is_dram) { + power.readOp.leakage += refresh_power; + } + + // TODO: below should be avoided. + /*if (dp.is_main_mem) + { + power.readOp.leakage += MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA * 1e-3 * + g_tp.peri_global.Vdd / g_ip->nbanks; + }*/ + + assert(power.readOp.dynamic > 0); + assert(power.writeOp.dynamic > 0); + assert(power.readOp.leakage > 0); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/uca.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/uca.h new file mode 100644 index 0000000000..4201479923 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/uca.h @@ -0,0 +1,97 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __UCA_H__ +#define __UCA_H__ + +#include "area.h" +#include "bank.h" +#include "component.h" +#include "htree2.h" +#include "parameter.h" + +namespace cacti { + +class UCA : public Component { + public: + UCA(const DynamicParameter &dyn_p); + ~UCA(); + double compute_delays(double inrisetime); // returns outrisetime + void compute_power_energy(); + + DynamicParameter dp; + Bank bank; + + Htree2 *htree_in_add; + Htree2 *htree_in_data; + Htree2 *htree_out_data; + Htree2 *htree_in_search; + Htree2 *htree_out_search; + + powerDef power_routing_to_bank; + + uint32_t nbanks; + + int num_addr_b_bank; + int num_di_b_bank; + int num_do_b_bank; + int num_si_b_bank; + int num_so_b_bank; + int RWP, ERP, EWP, SCHP; + double area_all_dataramcells; + + double dyn_read_energy_from_closed_page; + double dyn_read_energy_from_open_page; + double dyn_read_energy_remaining_words_in_burst; + + double refresh_power; // only for DRAM + double activate_energy; + double read_energy; + double write_energy; + double precharge_energy; + double leak_power_subbank_closed_page; + double leak_power_subbank_open_page; + double leak_power_request_and_reply_networks; + + double delay_array_to_sa_mux_lev_1_decoder; + double delay_array_to_sa_mux_lev_2_decoder; + double delay_before_subarray_output_driver; + double delay_from_subarray_out_drv_to_out; + double access_time; + double precharge_delay; + double multisubbank_interleave_cycle_time; + double long_channel_leakage_reduction_periperal; + double long_channel_leakage_reduction_memcell; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/version_cacti.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/version_cacti.h new file mode 100644 index 0000000000..6af534e3c5 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/version_cacti.h @@ -0,0 +1,44 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef VERSION_H_ +#define VERSION_H_ + +#include + +#define VER_MAJOR_CACTI 6 /* CACTI-P and DVS */ +#define VER_MINOR_CACTI 5 +const std::string VER_postfix_CACTI = "-P"; +#define VER_COMMENT_CACTI \ + "CAM and fully associative cache, power gating, and DVS" +#define VER_UPDATE_CACTI "June, 2014" + +#endif /* VERSION_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/wire.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/wire.cc new file mode 100644 index 0000000000..9b58c9aa32 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/wire.cc @@ -0,0 +1,919 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "wire.h" +#include "cmath" +using namespace cacti; +// use this constructor to calculate wire stats +Wire::Wire(enum Wire_type wire_model, double wl, int n, double w_s, double s_s, + enum Wire_placement wp, double resistivity, + TechnologyParameter::DeviceType *dt) + : wt(wire_model), + wire_length(wl * 1e-6), + nsense(n), + w_scale(w_s), + s_scale(s_s), + resistivity(resistivity), + deviceType(dt) { + wire_placement = wp; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + in_rise_time = 0; + out_rise_time = 0; + if (initialized != 1) { + cout << "Wire not initialized. Initializing it with default values\n"; + Wire winit; + } + calculate_wire_stats(); + // change everything back to seconds, microns, and Joules + repeater_spacing *= 1e6; + wire_length *= 1e6; + wire_width *= 1e6; + wire_spacing *= 1e6; + assert(wire_length > 0); + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); +} + +// the following values are for peripheral global technology +// specified in the input config file +Component Wire::global; +Component Wire::global_5; +Component Wire::global_10; +Component Wire::global_20; +Component Wire::global_30; +Component Wire::low_swing; + +int Wire::initialized; +double Wire::wire_width_init; +double Wire::wire_spacing_init; +double Wire::repeater_size_init; // value used in initialization should not be + // reused in final output +double Wire::repeater_spacing_init; + +Wire::Wire(double w_s, double s_s, + /*bool reset_repeater_sizing,*/ enum Wire_placement wp, double resis, + TechnologyParameter::DeviceType *dt) { + w_scale = w_s; + s_scale = s_s; + deviceType = dt; + wire_placement = wp; + resistivity = resis; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; + in_rise_time = 0; + out_rise_time = 0; + + switch (wire_placement) { + case outside_mat: + wire_width = g_tp.wire_outside_mat.pitch; + break; + case inside_mat: + wire_width = g_tp.wire_inside_mat.pitch; + break; + default: + wire_width = g_tp.wire_local.pitch; + break; + } + + wire_spacing = wire_width; + + wire_width *= (w_scale * 1e-6 / 2) /* (m) */; + wire_spacing *= (s_scale * 1e-6 / 2) /* (m) */; + + initialized = 1; + init_wire(); + // init_wire(reset_repeater_sizing); + wire_width_init = wire_width; + wire_spacing_init = wire_spacing; + + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); +} + +Wire::~Wire() {} + +void Wire::calculate_wire_stats() { + if (wire_placement == outside_mat) { + wire_width = g_tp.wire_outside_mat.pitch; + } + else if (wire_placement == inside_mat) { + wire_width = g_tp.wire_inside_mat.pitch; + } + else { + wire_width = g_tp.wire_local.pitch; + } + + wire_spacing = wire_width; + + wire_width *= (w_scale * 1e-6 / 2) /* (m) */; + wire_spacing *= (s_scale * 1e-6 / 2) /* (m) */; + + if (wt != Low_swing) { + // delay_optimal_wire(); + + if (wt == Global) { + delay = global.delay * wire_length; + power.readOp.dynamic = global.power.readOp.dynamic * wire_length; + power.readOp.leakage = global.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global.power.readOp.gate_leakage * wire_length; + repeater_spacing = global.area.w; + repeater_size = global.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_5) { + delay = global_5.delay * wire_length; + power.readOp.dynamic = global_5.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_5.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_5.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_5.area.w; + repeater_size = global_5.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_10) { + delay = global_10.delay * wire_length; + power.readOp.dynamic = global_10.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_10.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_10.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_10.area.w; + repeater_size = global_10.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_20) { + delay = global_20.delay * wire_length; + power.readOp.dynamic = global_20.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_20.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_20.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_20.area.w; + repeater_size = global_20.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + else if (wt == Global_30) { + delay = global_30.delay * wire_length; + power.readOp.dynamic = global_30.power.readOp.dynamic * wire_length; + power.readOp.leakage = global_30.power.readOp.leakage * wire_length; + power.readOp.gate_leakage = + global_30.power.readOp.gate_leakage * wire_length; + repeater_spacing = global_30.area.w; + repeater_size = global_30.area.h; + area.set_area((wire_length / repeater_spacing) * + compute_gate_area(INV, 1, min_w_pmos * repeater_size, + g_tp.min_w_nmos_ * repeater_size, + g_tp.cell_h_def)); + } + out_rise_time = delay * repeater_spacing / deviceType->Vth; + } + else if (wt == Low_swing) { + low_swing_model(); + repeater_spacing = wire_length; + repeater_size = 1; + } + else { + assert(0); + } + + // if (g_ip->interconect_power_gated)//TODO:actual sleep txs need to be added + // as in the wordline drivers, + // //but since wires have enough space underneath for placement and + // routing of the sleep tx, the area overhead should be very small. + // //performance loss and energy overhead is also very small + // because of the property of sleep tx. + // { + // power.readOp.leakage = + // power.readOp.leakage/deviceType->Vdd*deviceType->Vcc_min; + // } + power.readOp.power_gated_leakage = + power.readOp.leakage / deviceType->Vdd * deviceType->Vcc_min; // TODO: +} + +/* + * The fall time of an input signal to the first stage of a circuit is + * assumed to be same as the fall time of the output signal of two + * inverters connected in series (refer: CACTI 1 Technical report, + * section 6.1.3) + */ +double Wire::signal_fall_time() { + /* rise time of inverter 1's output */ + double rt; + /* fall time of inverter 2's output */ + double ft; + double timeconst; + + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(min_w_pmos, PCH, 1); + rt = horowitz(0, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, FALL) / + (deviceType->Vdd - deviceType->Vth); + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(g_tp.min_w_nmos_, NCH, 1); + ft = horowitz(rt, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE) / + deviceType->Vth; + return ft; +} + +double Wire::signal_rise_time() { + /* rise time of inverter 1's output */ + double ft; + /* fall time of inverter 2's output */ + double rt; + double timeconst; + + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(g_tp.min_w_nmos_, NCH, 1); + rt = horowitz(0, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE) / + deviceType->Vth; + timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) * + tr_R_on(min_w_pmos, PCH, 1); + ft = horowitz(rt, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, FALL) / + (deviceType->Vdd - deviceType->Vth); + return ft; // sec +} + +/* Wire resistance and capacitance calculations + * wire width + * + * /__/ + * | | + * | | height = ASPECT_RATIO*wire width (ASPECT_RATIO = 2.2, ref: ITRS) + * |__|/ + * + * spacing between wires in same level = wire width + * spacing between wires in adjacent levels = wire width---this is incorrect, + * according to R.Ho's paper and thesis. ILD != wire width + * + */ + +double Wire::wire_cap(double len /* in m */, bool call_from_outside) { + // TODO: this should be consistent with the wire_res in technology file + double sidewall, adj, tot_cap; + double wire_height; + double epsilon0 = 8.8542e-12; + double aspect_ratio, horiz_dielectric_constant, vert_dielectric_constant, + miller_value, ild_thickness; + + switch (wire_placement) { + case outside_mat: { + aspect_ratio = g_tp.wire_outside_mat.aspect_ratio; + horiz_dielectric_constant = + g_tp.wire_outside_mat.horiz_dielectric_constant; + vert_dielectric_constant = g_tp.wire_outside_mat.vert_dielectric_constant; + miller_value = g_tp.wire_outside_mat.miller_value; + ild_thickness = g_tp.wire_outside_mat.ild_thickness; + break; + } + case inside_mat: { + aspect_ratio = g_tp.wire_inside_mat.aspect_ratio; + horiz_dielectric_constant = + g_tp.wire_inside_mat.horiz_dielectric_constant; + vert_dielectric_constant = g_tp.wire_inside_mat.vert_dielectric_constant; + miller_value = g_tp.wire_inside_mat.miller_value; + ild_thickness = g_tp.wire_inside_mat.ild_thickness; + break; + } + default: { + aspect_ratio = g_tp.wire_local.aspect_ratio; + horiz_dielectric_constant = g_tp.wire_local.horiz_dielectric_constant; + vert_dielectric_constant = g_tp.wire_local.vert_dielectric_constant; + miller_value = g_tp.wire_local.miller_value; + ild_thickness = g_tp.wire_local.ild_thickness; + break; + } + } + + if (call_from_outside) { + wire_width *= 1e-6; + wire_spacing *= 1e-6; + } + wire_height = wire_width / w_scale * aspect_ratio; + /* + * assuming height does not change. wire_width = width_original*w_scale + * So wire_height does not change as wire width increases + */ + + // capacitance between wires in the same level + // sidewall = 2*miller_value * horiz_dielectric_constant * + // (wire_height/wire_spacing) + // * epsilon0; + + sidewall = miller_value * horiz_dielectric_constant * + (wire_height / wire_spacing) * epsilon0; + + // capacitance between wires in adjacent levels + // adj = miller_value * vert_dielectric_constant *w_scale * epsilon0; + // adj = 2*vert_dielectric_constant *wire_width/(ild_thickness*1e-6) * + // epsilon0; + + adj = miller_value * vert_dielectric_constant * wire_width / + (ild_thickness * 1e-6) * epsilon0; + // Change ild_thickness from micron to M + + // tot_cap = (sidewall + adj + (deviceType->C_fringe * 1e6)); //F/m + tot_cap = (sidewall + adj + (g_tp.fringe_cap * 1e6)); // F/m + + if (call_from_outside) { + wire_width *= 1e6; + wire_spacing *= 1e6; + } + return (tot_cap * len); // (F) +} + +double Wire::wire_res(double len /*(in m)*/) { + double aspect_ratio, alpha_scatter = 1.05, dishing_thickness = 0, + barrier_thickness = 0; + // TODO: this should be consistent with the wire_res in technology file + // The whole computation should be consistent with the wire_res in + // technology.cc too! + + switch (wire_placement) { + case outside_mat: { + aspect_ratio = g_tp.wire_outside_mat.aspect_ratio; + break; + } + case inside_mat: { + aspect_ratio = g_tp.wire_inside_mat.aspect_ratio; + break; + } + default: { + aspect_ratio = g_tp.wire_local.aspect_ratio; + break; + } + } + return (alpha_scatter * resistivity * 1e-6 * len / + ((aspect_ratio * wire_width / w_scale - dishing_thickness - + barrier_thickness) * + (wire_width - 2 * barrier_thickness))); +} + +/* + * Calculates the delay, power and area of the transmitter circuit. + * + * The transmitter delay is the sum of nand gate delay, inverter delay + * low swing nmos delay, and the wire delay + * (ref: Technical report 6) + */ +void Wire::low_swing_model() { + double len = wire_length; + double beta = pmos_to_nmos_sz_ratio(); + + double inputrise = (in_rise_time == 0) ? signal_rise_time() : in_rise_time; + + /* Final nmos low swing driver size calculation: + * Try to size the driver such that the delay + * is less than 8FO4. + * If the driver size is greater than + * the max allowable size, assume max size for the driver. + * In either case, recalculate the delay using + * the final driver size assuming slow input with + * finite rise time instead of ideal step input + * + * (ref: Technical report 6) + */ + double cwire = wire_cap(len); /* load capacitance */ + double rwire = wire_res(len); + +#define RES_ADJ (8.6) // Increase in resistance due to low driving vol. + + double driver_res = (-8 * g_tp.FO4 / (log(0.5) * cwire)) / RES_ADJ; + double nsize = R_to_w(driver_res, NCH); + + nsize = MIN(nsize, g_tp.max_w_nmos_); + nsize = MAX(nsize, g_tp.min_w_nmos_); + + if (rwire * cwire > 8 * g_tp.FO4) { + nsize = g_tp.max_w_nmos_; + } + + // size the inverter appropriately to minimize the transmitter delay + // Note - In order to minimize leakage, we are not adding a set of inverters + // to bring down delay. Instead, we are sizing the single gate based on the + // logical effort. + double st_eff = + sqrt((2 + beta / 1 + beta) * gate_C(nsize, 0) / + (gate_C(2 * g_tp.min_w_nmos_, 0) + gate_C(2 * min_w_pmos, 0))); + double req_cin = ((2 + beta / 1 + beta) * gate_C(nsize, 0)) / st_eff; + double inv_size = + req_cin / (gate_C(min_w_pmos, 0) + gate_C(g_tp.min_w_nmos_, 0)); + inv_size = MAX(inv_size, 1); + + /* nand gate delay */ + double res_eq = (2 * tr_R_on(g_tp.min_w_nmos_, NCH, 1)); + double cap_eq = 2 * drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(2 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(inv_size * g_tp.min_w_nmos_, 0) + + gate_C(inv_size * min_w_pmos, 0); + + double timeconst = res_eq * cap_eq; + + delay = horowitz(inputrise, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, RISE); + double temp_power = cap_eq * deviceType->Vdd * deviceType->Vdd; + + inputrise = + delay / (deviceType->Vdd - deviceType->Vth); /* for the next stage */ + + /* Inverter delay: + * The load capacitance of this inv depends on + * the gate capacitance of the final stage nmos + * transistor which in turn depends on nsize + */ + res_eq = tr_R_on(inv_size * min_w_pmos, PCH, 1); + cap_eq = drain_C_(inv_size * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(inv_size * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + + gate_C(nsize, 0); + timeconst = res_eq * cap_eq; + + delay += horowitz(inputrise, timeconst, deviceType->Vth / deviceType->Vdd, + deviceType->Vth / deviceType->Vdd, FALL); + temp_power += cap_eq * deviceType->Vdd * deviceType->Vdd; + + transmitter.delay = delay; + transmitter.power.readOp.dynamic = + temp_power * 2; /* since it is a diff. model*/ + transmitter.power.readOp.leakage = + deviceType->Vdd * + (4 * cmos_Isub_leakage(g_tp.min_w_nmos_, min_w_pmos, 2, nand) + + 4 * cmos_Isub_leakage(g_tp.min_w_nmos_, min_w_pmos, 1, inv)); + + transmitter.power.readOp.gate_leakage = + deviceType->Vdd * + (4 * cmos_Ig_leakage(g_tp.min_w_nmos_, min_w_pmos, 2, nand) + + 4 * cmos_Ig_leakage(g_tp.min_w_nmos_, min_w_pmos, 1, inv)); + + inputrise = delay / deviceType->Vth; + + /* nmos delay + wire delay */ + cap_eq = cwire + drain_C_(nsize, NCH, 1, 1, g_tp.cell_h_def) * 2 + + nsense * sense_amp_input_cap(); //+receiver cap + /* + * NOTE: nmos is used as both pull up and pull down transistor + * in the transmitter. This is because for low voltage swing, drive + * resistance of nmos is less than pmos + * (for a detailed graph ref: On-Chip Wires: Scaling and Efficiency) + */ + timeconst = (tr_R_on(nsize, NCH, 1) * RES_ADJ) * + (cwire + drain_C_(nsize, NCH, 1, 1, g_tp.cell_h_def) * 2) + + rwire * cwire / 2 + + (tr_R_on(nsize, NCH, 1) * RES_ADJ + rwire) * nsense * + sense_amp_input_cap(); + + /* + * since we are pre-equalizing and overdriving the low + * swing wires, the net time constant is less + * than the actual value + */ + delay += + horowitz(inputrise, timeconst, deviceType->Vth / deviceType->Vdd, .25, 0); +#define VOL_SWING .1 + temp_power += cap_eq * VOL_SWING * .400; /* .4v is the over drive voltage */ + temp_power *= 2; /* differential wire */ + + l_wire.delay = delay - transmitter.delay; + l_wire.power.readOp.dynamic = temp_power - transmitter.power.readOp.dynamic; + l_wire.power.readOp.leakage = + deviceType->Vdd * (4 * cmos_Isub_leakage(nsize, 0, 1, nmos)); + + l_wire.power.readOp.gate_leakage = + deviceType->Vdd * (4 * cmos_Ig_leakage(nsize, 0, 1, nmos)); + + // double rt = horowitz(inputrise, timeconst, deviceType->Vth/deviceType->Vdd, + // deviceType->Vth/deviceType->Vdd, RISE)/deviceType->Vth; + + delay += g_tp.sense_delay; + + sense_amp.delay = g_tp.sense_delay; + out_rise_time = g_tp.sense_delay / (deviceType->Vth); + sense_amp.power.readOp.dynamic = g_tp.sense_dy_power; + sense_amp.power.readOp.leakage = 0; // FIXME + sense_amp.power.readOp.gate_leakage = 0; + + power.readOp.dynamic = temp_power + sense_amp.power.readOp.dynamic; + power.readOp.leakage = transmitter.power.readOp.leakage + + l_wire.power.readOp.leakage + + sense_amp.power.readOp.leakage; + power.readOp.gate_leakage = transmitter.power.readOp.gate_leakage + + l_wire.power.readOp.gate_leakage + + sense_amp.power.readOp.gate_leakage; +} + +double Wire::sense_amp_input_cap() { + return drain_C_(g_tp.w_iso, PCH, 1, 1, g_tp.cell_h_def) + + gate_C(g_tp.w_sense_en + g_tp.w_sense_n, 0) + + drain_C_(g_tp.w_sense_n, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.w_sense_p, PCH, 1, 1, g_tp.cell_h_def); +} + +void Wire::delay_optimal_wire(/*bool reset_repeater_sizing*/) { + double len = wire_length; + // double min_wire_width = wire_width; //m + double beta = pmos_to_nmos_sz_ratio(); + double switching = 0; // switching energy + double short_ckt = 0; // short-circuit energy + double tc = 0; // time constant + // input cap of min sized driver + double input_cap = gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0); + + // output parasitic capacitance of + // the min. sized driver + double out_cap = drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def); + // drive resistance + double out_res = + (tr_R_on(g_tp.min_w_nmos_, NCH, 1) + tr_R_on(min_w_pmos, PCH, 1)) / 2; + double wr = wire_res(len); // ohm + + // wire cap /m + double wc = wire_cap(len); + + // size the repeater such that the delay of the wire is minimum + double repeater_scaling = + sqrt(out_res * wc / (wr * input_cap)); // len will cancel + + // calc the optimum spacing between the repeaters (m) + + // if (reset_repeater_sizing==true) { + + repeater_spacing_init = + sqrt(2 * out_res * (out_cap + input_cap) / ((wr / len) * (wc / len))); + repeater_size_init = repeater_scaling; + // } + + switching = (repeater_scaling * (input_cap + out_cap) + + repeater_spacing_init * (wc / len)) * + deviceType->Vdd * deviceType->Vdd; + + tc = out_res * (input_cap + out_cap) + + out_res * wc / len * repeater_spacing_init / repeater_scaling + + wr / len * repeater_spacing_init * input_cap * repeater_scaling + + 0.5 * (wr / len) * (wc / len) * repeater_spacing_init * + repeater_spacing_init; + + delay = 0.693 * tc * len / repeater_spacing_init; + +#define Ishort_ckt 65e-6 /* across all tech Ref:Banerjee et al. {IEEE TED} */ + short_ckt = deviceType->Vdd * g_tp.min_w_nmos_ * Ishort_ckt * 1.0986 * + repeater_scaling * tc; + + area.set_area((len / repeater_spacing_init) * + compute_gate_area(INV, 1, min_w_pmos * repeater_scaling, + g_tp.min_w_nmos_ * repeater_scaling, + g_tp.cell_h_def)); + power.readOp.dynamic = + ((len / repeater_spacing_init) * (switching + short_ckt)); + power.readOp.leakage = + ((len / repeater_spacing_init) * deviceType->Vdd * + cmos_Isub_leakage(g_tp.min_w_nmos_ * repeater_scaling, + beta * g_tp.min_w_nmos_ * repeater_scaling, 1, inv)); + power.readOp.gate_leakage = + ((len / repeater_spacing_init) * deviceType->Vdd * + cmos_Ig_leakage(g_tp.min_w_nmos_ * repeater_scaling, + beta * g_tp.min_w_nmos_ * repeater_scaling, 1, inv)); +} + +// calculate power/delay values for wires with suboptimal repeater +// sizing/spacing +void Wire::init_wire(/*bool reset_repeater_sizing*/) { + wire_length = 1; + delay_optimal_wire(/*reset_repeater_sizing*/); + double sp, si; + powerDef pow; + si = repeater_size_init; + sp = repeater_spacing_init; + sp *= 1e6; // in microns + + double i, j, del; + repeated_wire.push_back(Component()); + for (j = sp; j < 4 * sp; j += 100) { + for (i = si; i > 1; i--) { + pow = wire_model(j * 1e-6, i, &del); + if (j == sp && i == si) { + global.delay = del; + global.power = pow; + global.area.h = si; + global.area.w = sp * 1e-6; // m + } + // cout << "Repeater size - "<< i << + // " Repeater spacing - " << j << + // " Delay - " << del << + // " PowerD - " << pow.readOp.dynamic << + // " PowerL - " << pow.readOp.leakage <delay; + low_swing.power = l_wire->power; + delete l_wire; +} + +void Wire::update_fullswing() { + list::iterator citer; + double del[4]; + del[3] = this->global.delay + this->global.delay * .3; + del[2] = global.delay + global.delay * .2; + del[1] = global.delay + global.delay * .1; + del[0] = global.delay + global.delay * .05; + double threshold; + double ncost; + double cost; + int i = 4; + while (i > 0) { + threshold = del[i - 1]; + cost = BIGNUM; + for (citer = repeated_wire.begin(); citer != repeated_wire.end(); citer++) { + if (citer->delay > threshold) { + citer = repeated_wire.erase(citer); + citer--; + } + else { + ncost = citer->power.readOp.dynamic / global.power.readOp.dynamic + + citer->power.readOp.leakage / global.power.readOp.leakage; + if (ncost < cost) { + cost = ncost; + if (i == 4) { + global_30.delay = citer->delay; + global_30.power = citer->power; + global_30.area = citer->area; + } + else if (i == 3) { + global_20.delay = citer->delay; + global_20.power = citer->power; + global_20.area = citer->area; + } + else if (i == 2) { + global_10.delay = citer->delay; + global_10.power = citer->power; + global_10.area = citer->area; + } + else if (i == 1) { + global_5.delay = citer->delay; + global_5.power = citer->power; + global_5.area = citer->area; + } + } + } + } + i--; + } + citer = repeated_wire.begin(); + while (!repeated_wire.empty()) // TODO: code optimize + { + citer = repeated_wire.erase(citer); + } +} + +powerDef Wire::wire_model(double space, double size, double *delay) { + powerDef ptemp; + double len = 1; + // double min_wire_width = wire_width; //m + double beta = pmos_to_nmos_sz_ratio(); + // switching energy + double switching = 0; + // short-circuit energy + double short_ckt = 0; + // time constant + double tc = 0; + // input cap of min sized driver + double input_cap = gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0); + + // output parasitic capacitance of + // the min. sized driver + double out_cap = drain_C_(min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def); + // drive resistance + double out_res = + (tr_R_on(g_tp.min_w_nmos_, NCH, 1) + tr_R_on(min_w_pmos, PCH, 1)) / 2; + double wr = wire_res(len); // ohm + + // wire cap /m + double wc = wire_cap(len); + + repeater_spacing = space; + repeater_size = size; + + switching = + (repeater_size * (input_cap + out_cap) + repeater_spacing * (wc / len)) * + deviceType->Vdd * deviceType->Vdd; + + tc = out_res * (input_cap + out_cap) + + out_res * wc / len * repeater_spacing / repeater_size + + wr / len * repeater_spacing * out_cap * repeater_size + + 0.5 * (wr / len) * (wc / len) * repeater_spacing * repeater_spacing; + + *delay = 0.693 * tc * len / repeater_spacing; + +#define Ishort_ckt 65e-6 /* across all tech Ref:Banerjee et al. {IEEE TED} */ + short_ckt = deviceType->Vdd * g_tp.min_w_nmos_ * Ishort_ckt * 1.0986 * + repeater_size * tc; + + ptemp.readOp.dynamic = ((len / repeater_spacing) * (switching + short_ckt)); + ptemp.readOp.leakage = + ((len / repeater_spacing) * deviceType->Vdd * + cmos_Isub_leakage(g_tp.min_w_nmos_ * repeater_size, + beta * g_tp.min_w_nmos_ * repeater_size, 1, inv)); + + ptemp.readOp.gate_leakage = + ((len / repeater_spacing) * deviceType->Vdd * + cmos_Ig_leakage(g_tp.min_w_nmos_ * repeater_size, + beta * g_tp.min_w_nmos_ * repeater_size, 1, inv)); + + return ptemp; +} + +void Wire::print_wire() { + cout << "\nWire Properties at DVS level 0:\n\n"; + cout << " Delay Optimal\n\tRepeater size - " << global.area.h + << " \n\tRepeater spacing - " << global.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + + cout << " 5% Overhead\n\tRepeater size - " << global_5.area.h + << " \n\tRepeater spacing - " << global_5.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_5.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_5.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_5.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_5.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " 10% Overhead\n\tRepeater size - " << global_10.area.h + << " \n\tRepeater spacing - " << global_10.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_10.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_10.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_10.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_10.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " 20% Overhead\n\tRepeater size - " << global_20.area.h + << " \n\tRepeater spacing - " << global_20.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_20.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_20.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_20.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_20.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " 30% Overhead\n\tRepeater size - " << global_30.area.h + << " \n\tRepeater spacing - " << global_30.area.w * 1e3 + << " (mm)" + " \n\tDelay - " + << global_30.delay * 1e6 + << " (ns/mm)" + " \n\tPowerD - " + << global_30.power.readOp.dynamic * 1e6 + << " (nJ/mm)" + " \n\tPowerL - " + << global_30.power.readOp.leakage + << " (mW/mm)" + " \n\tPowerLgate - " + << global_30.power.readOp.gate_leakage << " (mW/mm)\n"; + cout << "\tWire width - " << wire_width_init * 1e6 << " microns\n"; + cout << "\tWire spacing - " << wire_spacing_init * 1e6 << " microns\n"; + cout << endl; + cout << " Low-swing wire (1 mm) - Note: Unlike repeated wires, \n\tdelay " + "and power " + "values of low-swing wires do not\n\thave a linear relationship with " + "length." + << " \n\tdelay - " << low_swing.delay * 1e9 + << " (ns)" + " \n\tpowerD - " + << low_swing.power.readOp.dynamic * 1e9 + << " (nJ)" + " \n\tPowerL - " + << low_swing.power.readOp.leakage + << " (mW)" + " \n\tPowerLgate - " + << low_swing.power.readOp.gate_leakage << " (mW)\n"; + cout << "\tWire width - " + << wire_width_init * 2 /* differential */ << " microns\n"; + cout << "\tWire spacing - " + << wire_spacing_init * 2 /* differential */ << " microns\n"; + cout << endl; + cout << endl; + + // cout<<"repeater_size_init"<delay; + low_swing.power = l_wire->power; + delete l_wire; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/wire.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/wire.h new file mode 100644 index 0000000000..c652e9f36a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/cacti/wire.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * McPAT/CACTI + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __WIRE_H__ +#define __WIRE_H__ + +#include +#include +#include "assert.h" +#include "basic_circuit.h" +#include "cacti_interface.h" +#include "component.h" +#include "parameter.h" + +namespace cacti { + +class Wire : public Component { + public: + Wire(enum Wire_type wire_model, double len /* in u*/, + int nsense = 1 /* no. of sense amps connected to the low-swing wire */, + double width_scaling = 1, double spacing_scaling = 1, + enum Wire_placement wire_placement = outside_mat, + double resistivity = CU_RESISTIVITY, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + ~Wire(); + + Wire(double width_scaling = 1, double spacing_scaling = 1, + // bool reset_repeater_sizing = true, + enum Wire_placement wire_placement = outside_mat, + double resistivity = CU_RESISTIVITY, + TechnologyParameter::DeviceType *dt = + &(g_tp.peri_global)); // should be used only once for initializing + // static members + void init_wire(/*bool reset_repeater_sizing = true*/); + + void calculate_wire_stats(); + void delay_optimal_wire(/*bool reset_repeater_sizing = true*/); + double wire_cap(double len, bool call_from_outside = false); + double wire_res(double len); + void low_swing_model(); + double signal_fall_time(); + double signal_rise_time(); + double sense_amp_input_cap(); + + enum Wire_type wt; + double wire_spacing; + double wire_width; + enum Wire_placement wire_placement; + double repeater_size; + double repeater_spacing; + static double repeater_size_init; // value used in initialization should not + // be reused in final output + static double repeater_spacing_init; + double wire_length; + double in_rise_time, out_rise_time; + + void set_in_rise_time(double rt) { in_rise_time = rt; } + static Component global; + static Component global_5; + static Component global_10; + static Component global_20; + static Component global_30; + static Component low_swing; + static double wire_width_init; + static double wire_spacing_init; + static void print_wire(); + void wire_dvs_update(); + + private: + int nsense; // no. of sense amps connected to a low-swing wire if it + // is broadcasting data to multiple destinations + // width and spacing scaling factor can be used + // to model low level wires or special + // fat wires + double w_scale, s_scale; + double resistivity; + powerDef wire_model(double space, double size, double *delay); + list repeated_wire; + void update_fullswing(); + static int initialized; + + // low-swing + Component transmitter; + Component l_wire; + Component sense_amp; + + double min_w_pmos; + + TechnologyParameter::DeviceType *deviceType; +}; + +} // namespace cacti + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/core.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/core.cc new file mode 100644 index 0000000000..79c43e0b61 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/core.cc @@ -0,0 +1,5893 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "core.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +//#include "globalvar.h" + +InstFetchU::InstFetchU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + IB(0), + BTB(0), + ID_inst(0), + ID_operand(0), + ID_misc(0), + exist(exist_) { + if (!exist) + return; + int idx, tag, data, size, line, assoc, banks; + bool debug = false, is_default = true; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + cache_p = (Cache_policy)(int)XML->sys.core[ithCore].icache.icache_config[7]; + // Assuming all L1 caches are virtually idxed physically tagged. + // cache + + size = (int)XML->sys.core[ithCore].icache.icache_config[0]; + line = (int)XML->sys.core[ithCore].icache.icache_config[1]; + assoc = (int)XML->sys.core[ithCore].icache.icache_config[2]; + banks = (int)XML->sys.core[ithCore].icache.icache_config[3]; + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + tag = debug ? 51 + : (int)XML->sys.physical_address_width - idx - + int(ceil(log2(line))) + EXTRA_TAG_BITS; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + debug ? 32768 : (int)XML->sys.core[ithCore].icache.icache_config[0]; + interface_ip.line_sz = + debug ? 64 : (int)XML->sys.core[ithCore].icache.icache_config[1]; + interface_ip.assoc = + debug ? 8 : (int)XML->sys.core[ithCore].icache.icache_config[2]; + interface_ip.nbanks = + debug ? 1 : (int)XML->sys.core[ithCore].icache.icache_config[3]; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = + 0; // debug?0:XML->sys.core[ithCore].icache.icache_config[5]; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 3.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + // interface_ip.obj_func_dyn_energy = 0; + // interface_ip.obj_func_dyn_power = 0; + // interface_ip.obj_func_leak_power = 0; + // interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + icache.caches = new ArrayST(&interface_ip, "icache", Core_device, + coredynp.opt_local, coredynp.core_ty); + scktRatio = g_tp.sckt_co_eff; + chip_PR_overhead = g_tp.chip_layout_overhead; + macro_PR_overhead = g_tp.macro_layout_overhead; + icache.area.set_area(icache.area.get_area() + + icache.caches->local_result.area); + area.set_area(area.get_area() + icache.caches->local_result.area); + // output_data_csv(icache.caches.local_result); + + /* + *iCache controllers + *miss buffer Each MSHR contains enough state + *to handle one or more accesses of any type to a single memory line. + *Due to the generality of the MSHR mechanism, + *the amount of state involved is non-trivial: + *including the address, pointers to the cache entry and destination register, + *written data, and various other pieces of state. + */ + interface_ip.num_search_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = (XML->sys.physical_address_width) + int(ceil(log2(size / line))) + + icache.caches->l_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].icache.buffer_sizes[0] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / + clockRate; // means cycle time + interface_ip.latency = debug + ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / + clockRate; // means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + XML->sys.core[ithCore].number_instruction_fetch_ports; + icache.missb = new ArrayST(&interface_ip, "icacheMissBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + icache.area.set_area(icache.area.get_area() + + icache.missb->local_result.area); + area.set_area(area.get_area() + icache.missb->local_result.area); + // output_data_csv(icache.missb.local_result); + + // fill buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = icache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data * XML->sys.core[ithCore].icache.buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + XML->sys.core[ithCore].number_instruction_fetch_ports; + icache.ifb = new ArrayST(&interface_ip, "icacheFillBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + icache.area.set_area(icache.area.get_area() + icache.ifb->local_result.area); + area.set_area(area.get_area() + icache.ifb->local_result.area); + // output_data_csv(icache.ifb.local_result); + + // prefetch buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; // check with + // previous entries + // to decide wthether + // to merge. + data = icache.caches->l_ip + .line_sz; // separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = + XML->sys.core[ithCore].icache.buffer_sizes[2] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + XML->sys.core[ithCore].number_instruction_fetch_ports; + icache.prefetchb = + new ArrayST(&interface_ip, "icacheprefetchBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + icache.area.set_area(icache.area.get_area() + + icache.prefetchb->local_result.area); + area.set_area(area.get_area() + icache.prefetchb->local_result.area); + // output_data_csv(icache.prefetchb.local_result); + + // Instruction buffer + data = + XML->sys.core[ithCore].instruction_length * + XML->sys.core[ithCore].peak_issue_width; // icache.caches.l_ip.line_sz; + // //multiple threads timing + // sharing the instruction + // buffer. + interface_ip.is_cache = false; + interface_ip.pure_ram = true; + interface_ip.pure_cam = false; + interface_ip.line_sz = int(ceil(data / 8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].number_hardware_threads * + XML->sys.core[ithCore].instruction_buffer_size * + interface_ip.line_sz > + 64 + ? XML->sys.core[ithCore].number_hardware_threads * + XML->sys.core[ithCore].instruction_buffer_size * + interface_ip.line_sz + : 64; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + // NOTE: Assuming IB is time slice shared among threads, every fetch op will + // at least fetch "fetch width" instructions. + interface_ip.num_rw_ports = + debug + ? 1 + : XML->sys.core[ithCore] + .number_instruction_fetch_ports; // XML->sys.core[ithCore].fetch_width; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + IB = new ArrayST(&interface_ip, "InstBuffer", Core_device, coredynp.opt_local, + coredynp.core_ty); + IB->area.set_area(IB->area.get_area() + IB->local_result.area); + area.set_area(area.get_area() + IB->local_result.area); + // output_data_csv(IB.IB.local_result); + + // inst_decoder.opcode_length = XML->sys.core[ithCore].opcode_width; + // inst_decoder.init_decoder(is_default, &interface_ip); + // inst_decoder.full_decoder_power(); + + if (coredynp.predictionW > 0) { + /* + * BTB branch target buffer, accessed during IF stage. Virtually indexed and + * virtually tagged It is only a cache without all the buffers in the cache + * controller since it is more like a look up table than a cache with cache + * controller. When access miss, no load from other places such as main + * memory (not actively fill the misses), it is passively updated under two + * circumstances: 1) when BPT@ID stage finds out current is a taken branch + * while BTB missed 2) When BPT@ID stage predicts differently than BTB 3) + * When ID stage finds out current instruction is not a branch while BTB had + * a hit.(mark as invalid) 4) when EXEU find out wrong target has been + * provided from BTB. + * + */ + size = XML->sys.core[ithCore].BTB.BTB_config[0]; + line = XML->sys.core[ithCore].BTB.BTB_config[1]; + assoc = XML->sys.core[ithCore].BTB.BTB_config[2]; + banks = XML->sys.core[ithCore].BTB.BTB_config[3]; + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + // tag = + // debug?51:XML->sys.virtual_address_width-idx-int(ceil(log2(line))) + + // int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + // +EXTRA_TAG_BITS; + tag = debug ? 51 + : XML->sys.virtual_address_width + + int(ceil(log2( + XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = debug ? 32768 : size; + interface_ip.line_sz = debug ? 64 : line; + interface_ip.assoc = debug ? 8 : assoc; + interface_ip.nbanks = debug ? 1 : banks; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = + 0; // debug?0:XML->sys.core[ithCore].dcache.dcache_config[5]; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].BTB.BTB_config[4] / clockRate; + interface_ip.latency = + debug ? 3.0 / clockRate + : XML->sys.core[ithCore].BTB.BTB_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + BTB = new ArrayST(&interface_ip, "Branch Target Buffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + BTB->area.set_area(BTB->area.get_area() + BTB->local_result.area); + area.set_area(area.get_area() + BTB->local_result.area); + /// cout<<"area="<area.get_area()); + } + + ID_inst = new inst_decoder(is_default, &interface_ip, coredynp.opcode_length, + 1 /*Decoder should not know how many by itself*/, + coredynp.x86, Core_device, coredynp.core_ty); + + ID_operand = + new inst_decoder(is_default, &interface_ip, coredynp.arch_ireg_width, 1, + coredynp.x86, Core_device, coredynp.core_ty); + + ID_misc = new inst_decoder(is_default, &interface_ip, + 8 /* Prefix field etc upto 14B*/, 1, coredynp.x86, + Core_device, coredynp.core_ty); + // TODO: X86 decoder should decode the inst in cyclic mode under the control + // of squencer. So the dynamic power should be multiplied by a few times. + area.set_area(area.get_area() + + (ID_inst->area.get_area() + ID_operand->area.get_area() + + ID_misc->area.get_area()) * + coredynp.decodeW); +} + +BranchPredictor::BranchPredictor(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + globalBPT(0), + localBPT(0), + L1_localBPT(0), + L2_localBPT(0), + chooser(0), + RAS(0), + exist(exist_) { + /* + * Branch Predictor, accessed during ID stage. + * McPAT's branch predictor model is the tournament branch predictor used in + * Alpha 21264, including global predictor, local two level predictor, and + * Chooser. The Branch predictor also includes a RAS (return address stack) + * for function calls Branch predictors are tagged by thread ID and modeled as + * 1-way associative cache. However RAS return address stacks are duplicated + * for each thread. + * TODO:Data Width need to be computed more precisely * + */ + if (!exist) + return; + int tag, data; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + interface_ip.assoc = 1; + interface_ip.pure_cam = false; + if (coredynp.multithreaded) { + tag = int(log2(coredynp.num_hthreads) + EXTRA_TAG_BITS); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + } + else { + interface_ip.is_cache = false; + interface_ip.pure_ram = true; + } + // Global predictor + data = + int(ceil(XML->sys.core[ithCore].predictor.global_predictor_bits / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.global_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + globalBPT = new ArrayST(&interface_ip, "Global Predictor", Core_device, + coredynp.opt_local, coredynp.core_ty); + globalBPT->area.set_area(globalBPT->area.get_area() + + globalBPT->local_result.area); + area.set_area(area.get_area() + globalBPT->local_result.area); + + // Local BPT (Level 1) + data = + int(ceil(XML->sys.core[ithCore].predictor.local_predictor_size[0] / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.local_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + L1_localBPT = new ArrayST(&interface_ip, "L1 local Predictor", Core_device, + coredynp.opt_local, coredynp.core_ty); + L1_localBPT->area.set_area(L1_localBPT->area.get_area() + + L1_localBPT->local_result.area); + area.set_area(area.get_area() + L1_localBPT->local_result.area); + + // Local BPT (Level 2) + data = + int(ceil(XML->sys.core[ithCore].predictor.local_predictor_size[1] / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.local_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + L2_localBPT = new ArrayST(&interface_ip, "L2 local Predictor", Core_device, + coredynp.opt_local, coredynp.core_ty); + L2_localBPT->area.set_area(L2_localBPT->area.get_area() + + L2_localBPT->local_result.area); + area.set_area(area.get_area() + L2_localBPT->local_result.area); + + // Chooser + data = + int(ceil(XML->sys.core[ithCore].predictor.chooser_predictor_bits / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].predictor.chooser_predictor_entries; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + chooser = new ArrayST(&interface_ip, "Predictor Chooser", Core_device, + coredynp.opt_local, coredynp.core_ty); + chooser->area.set_area(chooser->area.get_area() + chooser->local_result.area); + area.set_area(area.get_area() + chooser->local_result.area); + + // RAS return address stacks are Duplicated for each thread. + interface_ip.is_cache = false; + interface_ip.pure_ram = true; + data = int(ceil(coredynp.pc_width / 8.0)); + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].RAS_size; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.predictionW; + interface_ip.num_wr_ports = coredynp.predictionW; + interface_ip.num_se_rd_ports = 0; + RAS = new ArrayST(&interface_ip, "RAS", Core_device, coredynp.opt_local, + coredynp.core_ty); + RAS->area.set_area(RAS->area.get_area() + + RAS->local_result.area * coredynp.num_hthreads); + area.set_area(area.get_area() + + RAS->local_result.area * coredynp.num_hthreads); +} + +SchedulerU::SchedulerU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + int_inst_window(0), + fp_inst_window(0), + ROB(0), + instruction_selection(0), + exist(exist_) { + if (!exist) + return; + int tag, data; + bool is_default = true; + string tmp_name; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + if (coredynp.core_ty == Inorder && coredynp.multithreaded) { + // Instruction issue queue, in-order multi-issue or multithreaded processor + // also has this structure. Unified window for Inorder processors + tag = int(log2(XML->sys.core[ithCore].number_hardware_threads) * + coredynp.perThreadState); // This is the normal thread state bits + // based on Niagara Design + data = XML->sys.core[ithCore].instruction_length; + // NOTE: x86 inst can be very lengthy, up to 15B. Source: Intel® 64 and + // IA-32 Architectures Software Developer’s Manual + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = int(ceil(data / 8.0)); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + XML->sys.core[ithCore].instruction_window_size * interface_ip.line_sz > + 64 + ? XML->sys.core[ithCore].instruction_window_size * + interface_ip.line_sz + : 64; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.peak_issueW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = coredynp.peak_issueW; + int_inst_window = new ArrayST(&interface_ip, "InstFetchQueue", Core_device, + coredynp.opt_local, coredynp.core_ty); + int_inst_window->area.set_area(int_inst_window->area.get_area() + + int_inst_window->local_result.area * + coredynp.num_pipelines); + area.set_area(area.get_area() + + int_inst_window->local_result.area * coredynp.num_pipelines); + // output_data_csv(iRS.RS.local_result); + Iw_height = int_inst_window->local_result.cache_ht; + + /* + * selection logic + * In a single-issue Inorder multithreaded processor like Niagara, issue + * width=1*number_of_threads since the processor does need to pick up + * instructions from multiple ready ones(although these ready ones are from + * different threads).While SMT processors do not distinguish which thread + * belongs to who at the issue stage. + */ + interface_ip.assoc = + 1; // reset to prevent unnecessary warning messages when init_interface + instruction_selection = new selection_logic( + is_default, XML->sys.core[ithCore].instruction_window_size, + coredynp.peak_issueW * XML->sys.core[ithCore].number_hardware_threads, + &interface_ip, Core_device, coredynp.core_ty); + } + + if (coredynp.core_ty == OOO) { + /* + * CAM based instruction window + * For physicalRegFilebased OOO it is the instruction issue queue, where + * only tags of phy regs are stored For RS based OOO it is the Reservation + * station, where both tags and values of phy regs are stored It is written + * once and read twice(two operands) before an instruction can be issued. + * X86 instruction can be very long up to 15B. add instruction length in XML + */ + if (coredynp.scheu_ty == PhysicalRegFile) { + tag = coredynp.phy_ireg_width; + // Each time only half of the tag is compared, but two tag should be + // stored. This underestimate the search power + data = + int((ceil((coredynp.instruction_length + + 2 * (coredynp.phy_ireg_width - coredynp.arch_ireg_width)) / + 2.0) / + 8.0)); + // Data width being divided by 2 means only after both operands available + // the whole data will be read out. This is modeled using two equivalent + // readouts with half of the data width + tmp_name = "InstIssueQueue"; + } + else { + tag = coredynp.phy_ireg_width; + // Each time only half of the tag is compared, but two tag should be + // stored. This underestimate the search power + data = + int(ceil(((coredynp.instruction_length + + 2 * (coredynp.phy_ireg_width - coredynp.arch_ireg_width) + + 2 * coredynp.int_data_width) / + 2.0) / + 8.0)); + // Data width being divided by 2 means only after both operands available + // the whole data will be read out. This is modeled using two equivalent + // readouts with half of the data width + + tmp_name = "IntReservationStation"; + } + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].instruction_window_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 0; + interface_ip.throughput = 2 * 1.0 / clockRate; + interface_ip.latency = 2 * 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.peak_issueW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = coredynp.peak_issueW; + int_inst_window = new ArrayST(&interface_ip, tmp_name, Core_device, + coredynp.opt_local, coredynp.core_ty); + int_inst_window->area.set_area(int_inst_window->area.get_area() + + int_inst_window->local_result.area * + coredynp.num_pipelines); + area.set_area(area.get_area() + + int_inst_window->local_result.area * coredynp.num_pipelines); + Iw_height = int_inst_window->local_result.cache_ht; + // FU inst window + if (coredynp.scheu_ty == PhysicalRegFile) { + tag = 2 * coredynp.phy_freg_width; // TODO: each time only half of the + // tag is compared + data = + int(ceil((coredynp.instruction_length + + 2 * (coredynp.phy_freg_width - coredynp.arch_freg_width)) / + 8.0)); + tmp_name = "FPIssueQueue"; + } + else { + tag = 2 * coredynp.phy_ireg_width; + data = + int(ceil((coredynp.instruction_length + + 2 * (coredynp.phy_freg_width - coredynp.arch_freg_width) + + 2 * coredynp.fp_data_width) / + 8.0)); + tmp_name = "FPReservationStation"; + } + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].fp_instruction_window_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.fp_issueW; + interface_ip.num_wr_ports = coredynp.fp_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = coredynp.fp_issueW; + fp_inst_window = new ArrayST(&interface_ip, tmp_name, Core_device, + coredynp.opt_local, coredynp.core_ty); + fp_inst_window->area.set_area(fp_inst_window->area.get_area() + + fp_inst_window->local_result.area * + coredynp.num_fp_pipelines); + area.set_area(area.get_area() + fp_inst_window->local_result.area * + coredynp.num_fp_pipelines); + fp_Iw_height = fp_inst_window->local_result.cache_ht; + + if (XML->sys.core[ithCore].ROB_size > 0) { + /* + * if ROB_size = 0, then the target processor does not support + *hardware-based speculation, i.e. , the processor allow OOO issue as well + *as OOO completion, which means branch must be resolved before + *instruction issued into instruction window, since there is no change + *to flush miss-predict branch path after instructions are issued in + *this situation. + * + * ROB.ROB size = inflight inst. ROB is unified for int and fp inst. + * One old approach is to combine the RAT and ROB as a huge CAM structure + *as in AMD K7. However, this approach is abandoned due to its high power + *and poor scalability. McPAT uses current implementation of ROB as + *circular buffer. ROB is written once when instruction is issued and + *read once when the instruction is committed. * + */ + + int robExtra = int(ceil(5 + log2(coredynp.num_hthreads))); + data = int(ceil( + (robExtra + coredynp.pc_width + + ((coredynp.rm_ty == RAMbased) + ? (coredynp.phy_ireg_width + coredynp.phy_freg_width) + : fmax(coredynp.phy_ireg_width, coredynp.phy_freg_width)) + + ((coredynp.scheu_ty == PhysicalRegFile) ? 0 + : coredynp.fp_data_width)) / + 8.0)); + /* + * 5 bits are: busy, Issued, Finished, speculative, valid; + * PC is to id the instruction for recover + * exception/mis-prediction. When using RAM-based RAT, ROB needs to + * contain the ARF-PRF mapping to index the correct entry in the RAT, so + * that the correct architecture register (and freelist) can be found and + * the RAT can be appropriately updated; otherwise, the RAM-based RAT + * needs to support search ops to identify the target architecture + * register that needs to be updated, or the physical resigner that needs + * to be recycled; When using CAM-based RAT, ROB only needs to contain + * destination physical register since the CAM-base RAT can search for + * the corresponding ARF-PRF mapping to find the correct entry in the RAT, + * so that the correct architecture register (and freelist/bits) can be + * found and the RAT can be appropriately updated. ROB phy_reg entry + * should use the larger one from phy_ireg and phy_freg; fdata_width is + * always larger. Latest Intel Processors may have different ROB/RS + * designs. + */ + + /* + if(coredynp.scheu_ty==PhysicalRegFile) + { + //PC is to id the instruction for recover + exception. + //inst is used to map the renamed dest. + registers.so that commit stage can know which reg/RRAT to update + // data = + int(ceil((robExtra+coredynp.pc_width + + + // coredynp.instruction_length + + 2*coredynp.phy_ireg_width)/8.0)); + + if (coredynp.rm_ty ==RAMbased) + { + data = int(ceil((robExtra + + coredynp.pc_width + (coredynp.phy_ireg_width, + coredynp.phy_freg_width))/8.0)); + //When using RAM-based RAT, ROB + needs to contain the ARF-PRF mapping to index the correct entry in the + RAT, + //so that the correct architecture + register (and freelist) can be found and the RAT can be appropriately + updated. + } + else if (coredynp.rm_ty ==CAMbased) + { + data = + int(ceil((robExtra+coredynp.pc_width + fmax(coredynp.phy_ireg_width, + coredynp.phy_freg_width))/8.0)); + //When using CAM-based RAT, ROB + needs to contain the ARF-PRF mapping to index the correct entry in the + RAT, + //so that the correct architecture register (and freelist) can be found and the RAT can be appropriately updated. + } + } + else + { + //in RS based OOO, ROB also contains value + of destination reg + // data = + int(ceil((robExtra+coredynp.pc_width + + + // coredynp.instruction_length + + 2*coredynp.phy_ireg_width + + coredynp.fp_data_width)/8.0)); + + //using phy_reg number to search in the + RAT, the correct architecture register can be found and the RAT can be + appropriately updated. + //ROB phy_reg entry should use the larger + one from ireg and freg; fdata_width is always larger; Latest Intel + Processors may have different ROB/RS designs. data = int(ceil((robExtra + + coredynp.pc_width + fmax(coredynp.phy_ireg_width, coredynp.phy_freg_width) + + coredynp.fp_data_width)/8.0)); + } + */ + + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore] + .ROB_size; // The XML ROB size is for all threads + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.peak_commitW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 0; + ROB = new ArrayST(&interface_ip, "ReorderBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + ROB->area.set_area(ROB->area.get_area() + + ROB->local_result.area * coredynp.num_pipelines); + area.set_area(area.get_area() + + ROB->local_result.area * coredynp.num_pipelines); + ROB_height = ROB->local_result.cache_ht; + } + + instruction_selection = new selection_logic( + is_default, XML->sys.core[ithCore].instruction_window_size, + coredynp.peak_issueW, &interface_ip, Core_device, coredynp.core_ty); + } +} + +LoadStoreU::LoadStoreU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + LSQ(0), + LoadQ(0), + exist(exist_) { + if (!exist) + return; + int idx, tag, data, size, line, assoc; + bool debug = false; + int ldst_opcode = XML->sys.core[ithCore].opcode_width; // 16; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + cache_p = (Cache_policy)(int)XML->sys.core[ithCore].dcache.dcache_config[7]; + + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + // Dcache + size = (int)XML->sys.core[ithCore].dcache.dcache_config[0]; + line = (int)XML->sys.core[ithCore].dcache.dcache_config[1]; + assoc = (int)XML->sys.core[ithCore].dcache.dcache_config[2]; + // banks = (int)XML->sys.core[ithCore].dcache.dcache_config[3]; + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + tag = debug ? 51 + : XML->sys.physical_address_width - idx - int(ceil(log2(line))) + + EXTRA_TAG_BITS; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + debug ? 32768 : (int)XML->sys.core[ithCore].dcache.dcache_config[0]; + interface_ip.line_sz = + debug ? 64 : (int)XML->sys.core[ithCore].dcache.dcache_config[1]; + interface_ip.assoc = + debug ? 8 : (int)XML->sys.core[ithCore].dcache.dcache_config[2]; + interface_ip.nbanks = + debug ? 1 : (int)XML->sys.core[ithCore].dcache.dcache_config[3]; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = + 0; // debug?0:XML->sys.core[ithCore].dcache.dcache_config[5]; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 3.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.is_cache = true; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + debug ? 1 : XML->sys.core[ithCore].memory_ports; // usually In-order has + // 1 and OOO has 2 at + // least. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.caches = new ArrayST(&interface_ip, "dcache", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.caches->local_result.area); + area.set_area(area.get_area() + dcache.caches->local_result.area); + // output_data_csv(dcache.caches.local_result); + + // dCache controllers + // miss buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = (XML->sys.physical_address_width) + int(ceil(log2(size / line))) + + dcache.caches->l_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].dcache.buffer_sizes[0] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = debug ? 1 : XML->sys.core[ithCore].memory_ports; + ; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.missb = new ArrayST(&interface_ip, "dcacheMissBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.missb->local_result.area); + area.set_area(area.get_area() + dcache.missb->local_result.area); + // output_data_csv(dcache.missb.local_result); + + // fill buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = dcache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data * XML->sys.core[ithCore].dcache.buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = debug ? 1 : XML->sys.core[ithCore].memory_ports; + ; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.ifb = new ArrayST(&interface_ip, "dcacheFillBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + dcache.ifb->local_result.area); + area.set_area(area.get_area() + dcache.ifb->local_result.area); + // output_data_csv(dcache.ifb.local_result); + + // prefetch buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; // check with + // previous entries + // to decide wthether + // to merge. + data = dcache.caches->l_ip + .line_sz; // separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = + XML->sys.core[ithCore].dcache.buffer_sizes[2] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = debug ? 1 : XML->sys.core[ithCore].memory_ports; + ; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.prefetchb = + new ArrayST(&interface_ip, "dcacheprefetchBuffer", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.prefetchb->local_result.area); + area.set_area(area.get_area() + dcache.prefetchb->local_result.area); + // output_data_csv(dcache.prefetchb.local_result); + + // WBB + + if (cache_p == Write_back) { + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = dcache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.core[ithCore].dcache.buffer_sizes[3] * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + dcache.wbb = new ArrayST(&interface_ip, "dcacheWBB", Core_device, + coredynp.opt_local, coredynp.core_ty); + dcache.area.set_area(dcache.area.get_area() + + dcache.wbb->local_result.area); + area.set_area(area.get_area() + dcache.wbb->local_result.area); + // output_data_csv(dcache.wbb.local_result); + } + + /* + * LSU--in-order processors do not have separate load queue: unified lsq + * partitioned among threads + * it is actually the store queue but for inorder processors it serves as both + * loadQ and StoreQ + */ + tag = ldst_opcode + XML->sys.virtual_address_width + + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + data = XML->sys.machine_bits; + interface_ip.is_cache = true; + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + XML->sys.core[ithCore].store_buffer_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + LSQ = new ArrayST(&interface_ip, "Load(Store)Queue", Core_device, + coredynp.opt_local, coredynp.core_ty); + LSQ->area.set_area(LSQ->area.get_area() + LSQ->local_result.area); + area.set_area(area.get_area() + LSQ->local_result.area); + // output_data_csv(LSQ.LSQ.local_result); + lsq_height = + LSQ->local_result.cache_ht * + sqrt(cdb_overhead); /*XML->sys.core[ithCore].number_hardware_threads*/ + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = + XML->sys.core[ithCore].load_buffer_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + LoadQ = new ArrayST(&interface_ip, "LoadQueue", Core_device, + coredynp.opt_local, coredynp.core_ty); + LoadQ->area.set_area(LoadQ->area.get_area() + LoadQ->local_result.area); + area.set_area(area.get_area() + LoadQ->local_result.area); + // output_data_csv(LoadQ.LoadQ.local_result); + lsq_height = + (LSQ->local_result.cache_ht + LoadQ->local_result.cache_ht) * + sqrt(cdb_overhead); /*XML->sys.core[ithCore].number_hardware_threads*/ + } + area.set_area(area.get_area() * cdb_overhead); +} + +MemManU::MemManU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + itlb(0), + dtlb(0), + exist(exist_) { + if (!exist) + return; + int tag, data; + bool debug = false; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.specific_tag = 1; + // Itlb TLBs are partioned among threads according to Nigara and Nehalem + tag = XML->sys.virtual_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))) + + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + data = XML->sys.physical_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))); + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].itlb.number_entries * + interface_ip.line_sz; //*XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].icache.icache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = + debug ? 1 : XML->sys.core[ithCore].number_instruction_fetch_ports; + itlb = new ArrayST(&interface_ip, "ITLB", Core_device, coredynp.opt_local, + coredynp.core_ty); + itlb->area.set_area(itlb->area.get_area() + itlb->local_result.area); + area.set_area(area.get_area() + itlb->local_result.area); + // output_data_csv(itlb.tlb.local_result); + + // dtlb + tag = XML->sys.virtual_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))) + + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + + EXTRA_TAG_BITS; + data = XML->sys.physical_address_width - + int(floor(log2(XML->sys.virtual_memory_page_size))); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.core[ithCore].dtlb.number_entries * + interface_ip.line_sz; //*XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[4] / clockRate; + interface_ip.latency = + debug ? 1.0 / clockRate + : XML->sys.core[ithCore].dcache.dcache_config[5] / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports; + dtlb = new ArrayST(&interface_ip, "DTLB", Core_device, coredynp.opt_local, + coredynp.core_ty); + dtlb->area.set_area(dtlb->area.get_area() + dtlb->local_result.area); + area.set_area(area.get_area() + dtlb->local_result.area); + // output_data_csv(dtlb.tlb.local_result); +} + +RegFU::RegFU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + IRF(0), + FRF(0), + RFWIN(0), + exist(exist_) { + /* + * processors have separate architectural register files for each thread. + * therefore, the bypass buses need to travel across all the register files. + */ + + if (!exist) + return; + int data; + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + //**********************************IRF*************************************** + data = coredynp.int_data_width; + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.cache_sz = coredynp.num_IRF_entry * interface_ip.line_sz; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // this is the transfer port for + // saving/restoring states when exceptions + // happen. + interface_ip.num_rd_ports = 2 * coredynp.peak_issueW; + interface_ip.num_wr_ports = coredynp.peak_issueW; + interface_ip.num_se_rd_ports = 0; + IRF = new ArrayST(&interface_ip, "Integer Register File", Core_device, + coredynp.opt_local, coredynp.core_ty); + IRF->area.set_area(IRF->area.get_area() + + IRF->local_result.area * coredynp.num_pipelines * + cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + area.set_area(area.get_area() + + IRF->local_result.area * coredynp.num_pipelines * cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + // area.set_area(area.get_area()*cdb_overhead); + // output_data_csv(IRF.RF.local_result); + + //**********************************FRF*************************************** + data = coredynp.fp_data_width; + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = int(ceil(data / 32.0)) * 4; + interface_ip.cache_sz = coredynp.num_FRF_entry * interface_ip.line_sz; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // this is the transfer port for + // saving/restoring states when exceptions + // happen. + interface_ip.num_rd_ports = 2 * XML->sys.core[ithCore].issue_width; + interface_ip.num_wr_ports = XML->sys.core[ithCore].issue_width; + interface_ip.num_se_rd_ports = 0; + FRF = new ArrayST(&interface_ip, "Floating point Register File", Core_device, + coredynp.opt_local, coredynp.core_ty); + FRF->area.set_area(FRF->area.get_area() + + FRF->local_result.area * coredynp.num_fp_pipelines * + cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + area.set_area(area.get_area() + + FRF->local_result.area * coredynp.num_fp_pipelines * + cdb_overhead * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1)); + // area.set_area(area.get_area()*cdb_overhead); + // output_data_csv(FRF.RF.local_result); + int_regfile_height = IRF->local_result.cache_ht * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1) * + sqrt(cdb_overhead); + fp_regfile_height = FRF->local_result.cache_ht * + ((coredynp.scheu_ty == ReservationStation) + ? XML->sys.core[ithCore].number_hardware_threads + : 1) * + sqrt(cdb_overhead); + // since a EXU is associated with each pipeline, the cdb should not have + // longer length. + if (coredynp.regWindowing) { + //*********************************REG_WIN************************************ + data = coredynp.int_data_width; // ECC, and usually 2 regs are transfered + // together during window shifting.Niagara + // Mega cell + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = int(ceil(data / 8.0)); + interface_ip.cache_sz = XML->sys.core[ithCore].register_windows_size * + IRF->l_ip.cache_sz * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 4.0 / clockRate; + interface_ip.latency = 4.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // this is the transfer port for + // saving/restoring states when exceptions + // happen. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + RFWIN = new ArrayST(&interface_ip, "RegWindow", Core_device, + coredynp.opt_local, coredynp.core_ty); + RFWIN->area.set_area(RFWIN->area.get_area() + + RFWIN->local_result.area * coredynp.num_pipelines); + area.set_area(area.get_area() + + RFWIN->local_result.area * coredynp.num_pipelines); + // output_data_csv(RFWIN.RF.local_result); + } +} + +EXECU::EXECU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, double lsq_height_, + const CoreDynParam &dyn_p_, bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + lsq_height(lsq_height_), + coredynp(dyn_p_), + rfu(0), + scheu(0), + fp_u(0), + exeu(0), + mul(0), + int_bypass(0), + intTagBypass(0), + int_mul_bypass(0), + intTag_mul_Bypass(0), + fp_bypass(0), + fpTagBypass(0), + exist(exist_) { + // bool exist_flag = true; + if (!exist) + return; + double fu_height = 0.0; + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + rfu = new RegFU(XML, ithCore, &interface_ip, coredynp); + scheu = new SchedulerU(XML, ithCore, &interface_ip, coredynp); + exeu = new FunctionalUnit(XML, ithCore, &interface_ip, coredynp, ALU); + area.set_area(area.get_area() + exeu->area.get_area() + rfu->area.get_area() + + scheu->area.get_area()); + fu_height = exeu->FU_height; + if (coredynp.num_fpus > 0) { + fp_u = new FunctionalUnit(XML, ithCore, &interface_ip, coredynp, FPU); + area.set_area(area.get_area() + fp_u->area.get_area()); + } + if (coredynp.num_muls > 0) { + mul = new FunctionalUnit(XML, ithCore, &interface_ip, coredynp, MUL); + area.set_area(area.get_area() + mul->area.get_area()); + fu_height += mul->FU_height; + } + /* + * broadcast logic, including int-broadcast; int_tag-broadcast; fp-broadcast; + * fp_tag-broadcast integer by pass has two paths and fp has 3 paths. on the + * same bus there are multiple tri-state drivers and muxes that go to + * different components on the same bus + */ + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 0; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = + 2; // start from semi-global since local wires are already used + interface_ip.wire_os_mat_type = 2; + interface_ip.throughput = 10.0 / clockRate; // Do not care + interface_ip.latency = 10.0 / clockRate; + } + + if (coredynp.core_ty == Inorder) { + int_bypass = new interconnect( + "Int Bypass Data", Core_device, 1, 1, + int(ceil(XML->sys.machine_bits / 32.0) * 32), + rfu->int_regfile_height + exeu->FU_height + lsq_height, &interface_ip, + 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + int_bypass->area.get_area()); + intTagBypass = new interconnect( + "Int Bypass tag", Core_device, 1, 1, coredynp.perThreadState, + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + intTagBypass->area.get_area()); + + if (coredynp.num_muls > 0) { + int_mul_bypass = new interconnect( + "Mul Bypass Data", Core_device, 1, 1, + int(ceil(XML->sys.machine_bits / 32.0) * 32 * 1.5), + rfu->fp_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_mul_bypass->area.get_area()); + intTag_mul_Bypass = new interconnect( + "Mul Bypass tag", Core_device, 1, 1, coredynp.perThreadState, + rfu->fp_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + intTag_mul_Bypass->area.get_area()); + } + + if (coredynp.num_fpus > 0) { + fp_bypass = new interconnect( + "FP Bypass Data", Core_device, 1, 1, + int(ceil(XML->sys.machine_bits / 32.0) * 32 * 1.5), + rfu->fp_regfile_height + fp_u->FU_height, &interface_ip, 3, false, + 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + fp_bypass->area.get_area()); + fpTagBypass = new interconnect( + "FP Bypass tag", Core_device, 1, 1, coredynp.perThreadState, + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->Iw_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + fpTagBypass->area.get_area()); + } + } + else { // OOO + if (coredynp.scheu_ty == PhysicalRegFile) { + /* For physical register based OOO, + * data broadcast interconnects cover across functional units, lsq, inst + * windows and register files, while tag broadcast interconnects also + * cover across ROB + */ + int_bypass = new interconnect( + "Int Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + lsq_height, &interface_ip, + 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_bypass->area.get_area()); + intTagBypass = new interconnect( + "Int Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + intTagBypass->area.get_area()); + + if (coredynp.num_muls > 0) { + int_mul_bypass = new interconnect( + "Mul Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + intTag_mul_Bypass = new interconnect( + "Mul Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_mul_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + intTag_mul_Bypass->area.get_area()); + } + + if (coredynp.num_fpus > 0) { + fp_bypass = new interconnect("FP Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.fp_data_width)), + rfu->fp_regfile_height + fp_u->FU_height, + &interface_ip, 3, false, 1.0, + coredynp.opt_local, coredynp.core_ty); + fpTagBypass = new interconnect( + "FP Bypass tag", Core_device, 1, 1, coredynp.phy_freg_width, + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->fp_Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + fp_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + fpTagBypass->area.get_area()); + } + } + else { + /* + * In RS based processor both data and tag are broadcast together, + * covering functional units, lsq, nst windows, register files, and ROBs + */ + int_bypass = new interconnect( + "Int Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + intTagBypass = new interconnect( + "Int Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + lsq_height + + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + intTagBypass->area.get_area()); + if (coredynp.num_muls > 0) { + int_mul_bypass = new interconnect( + "Mul Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.int_data_width)), + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + intTag_mul_Bypass = new interconnect( + "Mul Bypass tag", Core_device, 1, 1, coredynp.phy_ireg_width, + rfu->int_regfile_height + exeu->FU_height + mul->FU_height + + lsq_height + scheu->Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + int_mul_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + intTag_mul_Bypass->area.get_area()); + } + + if (coredynp.num_fpus > 0) { + fp_bypass = new interconnect( + "FP Bypass Data", Core_device, 1, 1, + int(ceil(coredynp.fp_data_width)), + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->fp_Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + fpTagBypass = new interconnect( + "FP Bypass tag", Core_device, 1, 1, coredynp.phy_freg_width, + rfu->fp_regfile_height + fp_u->FU_height + lsq_height + + scheu->fp_Iw_height + scheu->ROB_height, + &interface_ip, 3, false, 1.0, coredynp.opt_local, coredynp.core_ty); + bypass.area.set_area(bypass.area.get_area() + + fp_bypass->area.get_area()); + bypass.area.set_area(bypass.area.get_area() + + fpTagBypass->area.get_area()); + } + } + } + area.set_area(area.get_area() + bypass.area.get_area()); +} + +RENAMINGU::RENAMINGU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + iFRAT(0), + fFRAT(0), + iRRAT(0), + fRRAT(0), + ifreeL(0), + ffreeL(0), + idcl(0), + fdcl(0), + RAHT(0), + exist(exist_) { + /* + * Although renaming logic maybe be used in in-order processors, +* McPAT assumes no renaming logic is used since the performance gain is very +limited and +* the only major inorder processor with renaming logic is Itainium +* that is a VLIW processor and different from current McPAT's model. + * physical register base OOO must have Dual-RAT architecture or equivalent +structure.FRAT:FrontRAT, RRAT:RetireRAT; + * i,f prefix mean int and fp + * RAT for all Renaming logic, random accessible checkpointing is used, but +only update when instruction retires. + * FRAT will be read twice and written once per instruction; + * RRAT will be write once per instruction when committing and reads out all +when context switch + * + * RAM scheme has # ARchi Reg entry with each entry hold phy reg tag, + * CAM scheme has # Phy Reg entry with each entry hold ARchi reg tag, + * + * RAM-based RAT is duplicated/partitioned for each different hardware threads + * CAM-based RAT is shared for all hardware threads + * With SMT, RAT is partitioned and tagged. RAM-based RAT needs to have N +(N-way SMT) sets of entries, with each set for a thread. + * The RAT control logic will determine different sets to use for different +threads. But it does not need extra tag bits in the entries. + * However, CAM-based RAT need extra tag bits to distinguish the architecture +register ids for different threads. + + * + * checkpointing of RAT and RRAT are both for architecture state recovery with +events including mis-speculation; + * Checkpointing is easier to implement in CAM than in RAM based RAT, despite +of the inferior scalabilty of the CAM-based RATs. + * McPAT assumes at least 1 checkpoint for CAM-based RATs, and no more than 4 +checkpoints (based on MIPS designs) for RAM based RATs, + * thus CAM-based RAT does not need RRAT + * Although no Dual-RAT is needed in RS-based OOO processors, since archi +RegFile contains the committed register values, + * a RRAT or GC (not both) will speedup the mis-speculation recovery. Thus, +when RAM-RAT does not have any GC, McPAT assumes the existence of a RRAT. + * + * RAM-base RAT does not need to scan/search all contents during instruction +commit, since the ROB for RAM-based RAT contains the ARF-PRF mapping that is +used for index the RAT entry to be updated. + * + * Both RAM and CAM have same DCL + * + + * + */ + if (!exist) + return; + int tag, data, out_w; + // interface_ip.wire_is_mat_type = 0; + // interface_ip.wire_os_mat_type = 0; + // interface_ip.wt = Global_30; + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + if (coredynp.core_ty == OOO) { + // integer pipeline + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { // FRAT with global checkpointing (GCs) + // please see paper tech report for + // detailed explanation. + data = int(ceil(coredynp.phy_ireg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); // 33; + out_w = int(ceil(coredynp.phy_ireg_width / 8.0)); // bytes + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_IRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FRAT floating point + data = int(ceil(coredynp.phy_freg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_FRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + else if (coredynp.rm_ty == CAMbased) { + // FRAT + tag = coredynp.arch_ireg_width + coredynp.hthread_width; + data = int( + ceil((coredynp.arch_ireg_width + 1 * coredynp.globalCheckpoint) / + 8.0)); // each checkpoint in the CAM-based RAT design needs + // only 1 bit, see "a power-aware hybrid ram-cam + // renaming mechanism for fast recovery" + out_w = int(ceil(coredynp.arch_ireg_width / 8.0)); + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_IRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.decodeW; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FRAT for FP + tag = coredynp.arch_freg_width + coredynp.hthread_width; + data = int( + ceil((coredynp.arch_freg_width + 1 * coredynp.globalCheckpoint) / + 8.0)); // each checkpoint in the CAM-based RAT design needs + // only 1 bit, see "a power-aware hybrid ram-cam + // renaming mechanism for fast recovery" + out_w = int(ceil(coredynp.arch_freg_width / 8.0)); + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_FRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.fp_decodeW; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + + // RRAT is always RAM based, does not have GCs, and is used only for + // record latest non-speculative mapping RRAT is not needed for CAM-based + // RAT (McPAT assumes CAM-based RAT to have at least 1 checkpoint), it is + // not needed for RAM-based RAT with checkpoints McPAT assumes renaming + // unit to have RRAT when there is no checkpoints in FRAT, while MIPS + // R1000 has 4 GCs, according to Intel Netburst Archi, combine GC with + // FRAT is very costly, especially for high issue width and high clock + // rate. + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_IRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_wr_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + iRRAT = new ArrayST(&interface_ip, "Int RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iRRAT->area.set_area(iRRAT->area.get_area() + iRRAT->local_result.area); + area.set_area(area.get_area() + iRRAT->area.get_area()); + + // RRAT for FP + data = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_FRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fRRAT = new ArrayST(&interface_ip, "FP RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fRRAT->area.set_area(fRRAT->area.get_area() + fRRAT->local_result.area); + area.set_area(area.get_area() + fRRAT->area.get_area()); + } + // Freelist of renaming unit always RAM based and needed for RAM-based + // RATs. Although it can be implemented within the CAM-based RAT, Current + // McPAT does not have the free bits in the CAM but use the same external + // free list as a close approximation for CAM RAT. Recycle happens at two + // places: 1)when DCL check there are WAW, the Phy-registers/ROB directly + // recycles into freelist + // 2)When instruction commits the Phyregisters/ROB needed to be recycled. + // therefore num_wr port = decode-1(-1 means at least one phy reg will be + // used for the current renaming group) + commit width + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * coredynp.num_ifreelist_entries; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // TODO + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = + coredynp.decodeW - 1 + XML->sys.core[ithCore].commit_width; + // every cycle, (coredynp.decodeW -1) inst may need to send back it dest + // tags, committW insts needs to update freelist buffers + interface_ip.num_se_rd_ports = 0; + ifreeL = new ArrayST(&interface_ip, "Int Free List", Core_device, + coredynp.opt_local, coredynp.core_ty); + ifreeL->area.set_area(ifreeL->area.get_area() + + ifreeL->local_result.area); + area.set_area(area.get_area() + ifreeL->area.get_area()); + + // freelist for FP + data = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * coredynp.num_ffreelist_entries; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = + coredynp.fp_decodeW - 1 + XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + ffreeL = new ArrayST(&interface_ip, "FP Free List", Core_device, + coredynp.opt_local, coredynp.core_ty); + ffreeL->area.set_area(ffreeL->area.get_area() + + ffreeL->local_result.area); + area.set_area(area.get_area() + ffreeL->area.get_area()); + + idcl = new dep_resource_conflict_check( + &interface_ip, coredynp, + coredynp.phy_ireg_width); // TODO:Separate 2 sections See TR + fdcl = new dep_resource_conflict_check(&interface_ip, coredynp, + coredynp.phy_freg_width); + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + data = int(ceil(coredynp.phy_ireg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.phy_ireg_width / + 8.0)); // GC does not need to be readout + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_IRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->local_result.adjust_area(); + // iFRAT->local_result.power.readOp.dynamic *= + // 1+0.2*0.05;//1+mis-speculation% TODO + // iFRAT->local_result.power.writeOp.dynamic + //*=1+0.2*0.05;//compensate for GC + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FP + data = int(ceil(coredynp.phy_freg_width * + (1 + coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * + XML->sys.core[ithCore].archi_Regs_FRF_size * + XML->sys.core[ithCore].number_hardware_threads; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // the extra one port is for GCs + interface_ip.num_rd_ports = 2 * coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->local_result.adjust_area(); + // fFRAT->local_result.power.readOp.dynamic *= + // 1+0.2*0.05;//1+mis-speculation% TODO + // fFRAT->local_result.power.writeOp.dynamic + //*=1+0.2*0.05;//compensate for GC + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + else if (coredynp.rm_ty == CAMbased) { + // FRAT + tag = coredynp.arch_ireg_width + coredynp.hthread_width; + data = int(ceil( + (coredynp.arch_ireg_width + 1 * coredynp.globalCheckpoint) / 8.0)); + out_w = int(ceil(coredynp.arch_ireg_width / + 8.0)); // GC bits does not need to be sent out + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_IRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = coredynp.decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.decodeW; + iFRAT = new ArrayST(&interface_ip, "Int FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iFRAT->area.set_area(iFRAT->area.get_area() + iFRAT->local_result.area); + area.set_area(area.get_area() + iFRAT->area.get_area()); + + // FRAT + tag = coredynp.arch_freg_width + coredynp.hthread_width; + data = int( + ceil((coredynp.arch_freg_width + 1 * coredynp.globalCheckpoint) / + 8.0)); // the address of CAM needed to be sent out + out_w = int(ceil(coredynp.arch_freg_width / 8.0)); + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * XML->sys.core[ithCore].phy_Regs_FRF_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = out_w * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 2; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // for GCs + interface_ip.num_rd_ports = + XML->sys.core[ithCore].decode_width; // 0;TODO; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 2 * coredynp.fp_decodeW; + fFRAT = new ArrayST(&interface_ip, "FP FrontRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fFRAT->area.set_area(fFRAT->area.get_area() + fFRAT->local_result.area); + area.set_area(area.get_area() + fFRAT->area.get_area()); + } + // Although no RRAT for RS based OOO is really needed since the archiRF + // always holds the non-speculative data, having the RRAT or GC (not both) + // can help the recovery of mis-speculations. + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_IRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_wr_ports = XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + iRRAT = new ArrayST(&interface_ip, "Int RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + iRRAT->area.set_area(iRRAT->area.get_area() + iRRAT->local_result.area); + area.set_area(area.get_area() + iRRAT->area.get_area()); + + // RRAT for FP + data = int(ceil(coredynp.phy_freg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = + data * XML->sys.core[ithCore].archi_Regs_FRF_size * 2 * + XML->sys.core[ithCore] + .number_hardware_threads; // HACK--2 to make it as least 64B + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = coredynp.fp_decodeW; + interface_ip.num_wr_ports = coredynp.fp_decodeW; + interface_ip.num_se_rd_ports = 0; + fRRAT = new ArrayST(&interface_ip, "FP RetireRAT", Core_device, + coredynp.opt_local, coredynp.core_ty); + fRRAT->area.set_area(fRRAT->area.get_area() + fRRAT->local_result.area); + area.set_area(area.get_area() + fRRAT->area.get_area()); + } + + // Freelist of renaming unit of RS based OOO is unifed for both int and fp + // renaming unit since the ROB is unified + data = int(ceil(coredynp.phy_ireg_width / 8.0)); + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.line_sz = data; + interface_ip.cache_sz = data * coredynp.num_ifreelist_entries; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / clockRate; + interface_ip.latency = 1.0 / clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // TODO + interface_ip.num_rd_ports = coredynp.decodeW; + interface_ip.num_wr_ports = + coredynp.decodeW - 1 + XML->sys.core[ithCore].commit_width; + interface_ip.num_se_rd_ports = 0; + ifreeL = new ArrayST(&interface_ip, "Unified Free List", Core_device, + coredynp.opt_local, coredynp.core_ty); + // ifreeL->area.set_area(ifreeL->area.get_area()+ + // ifreeL->local_result.area*XML->sys.core[ithCore].number_hardware_threads); + area.set_area(area.get_area() + ifreeL->area.get_area()); + + idcl = new dep_resource_conflict_check( + &interface_ip, coredynp, + coredynp.phy_ireg_width); // TODO:Separate 2 sections See TR + fdcl = new dep_resource_conflict_check(&interface_ip, coredynp, + coredynp.phy_freg_width); + } + } + if (coredynp.core_ty == Inorder && coredynp.issueW > 1) { + /* Dependency check logic will only present when decode(issue) width>1. + * Multiple issue in order processor can do without renaming, but dcl is a + * must. + */ + idcl = new dep_resource_conflict_check( + &interface_ip, coredynp, + coredynp.phy_ireg_width); // TODO:Separate 2 sections See TR + fdcl = new dep_resource_conflict_check(&interface_ip, coredynp, + coredynp.phy_freg_width); + } +} + +Core::Core(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + ifu(0), + lsu(0), + mmu(0), + exu(0), + rnu(0), + corepipe(0), + undiffCore(0), + l2cache(0) { + /* + * initialize, compute and optimize individual components. + */ + + bool exit_flag = true; + + double pipeline_area_per_unit; + // interface_ip.wire_is_mat_type = 2; + // interface_ip.wire_os_mat_type = 2; + // interface_ip.wt =Global_30; + set_core_param(); + + if (XML->sys.Private_L2) { + l2cache = new SharedCache(XML, ithCore, &interface_ip); + } + + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + ifu = new InstFetchU(XML, ithCore, &interface_ip, coredynp, exit_flag); + lsu = new LoadStoreU(XML, ithCore, &interface_ip, coredynp, exit_flag); + mmu = new MemManU(XML, ithCore, &interface_ip, coredynp, exit_flag); + exu = new EXECU(XML, ithCore, &interface_ip, lsu->lsq_height, coredynp, + exit_flag); + undiffCore = new UndiffCore(XML, ithCore, &interface_ip, coredynp, exit_flag); + if (coredynp.core_ty == OOO) { + rnu = new RENAMINGU(XML, ithCore, &interface_ip, coredynp); + } + corepipe = new Pipeline(&interface_ip, coredynp); + + if (coredynp.core_ty == OOO) { + pipeline_area_per_unit = + (corepipe->area.get_area() * coredynp.num_pipelines) / 5.0; + if (rnu->exist) { + rnu->area.set_area(rnu->area.get_area() + pipeline_area_per_unit); + } + } + else { + pipeline_area_per_unit = + (corepipe->area.get_area() * coredynp.num_pipelines) / 4.0; + } + + // area.set_area(area.get_area()+ corepipe->area.get_area()); + if (ifu->exist) { + ifu->area.set_area(ifu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + ifu->area.get_area()); + } + if (lsu->exist) { + lsu->area.set_area(lsu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + lsu->area.get_area()); + } + if (exu->exist) { + exu->area.set_area(exu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + exu->area.get_area()); + } + if (mmu->exist) { + mmu->area.set_area(mmu->area.get_area() + pipeline_area_per_unit); + area.set_area(area.get_area() + mmu->area.get_area()); + } + + if (coredynp.core_ty == OOO) { + if (rnu->exist) { + area.set_area(area.get_area() + rnu->area.get_area()); + } + } + + if (undiffCore->exist) { + area.set_area(area.get_area() + undiffCore->area.get_area()); + } + + if (XML->sys.Private_L2) { + area.set_area(area.get_area() + l2cache->area.get_area()); + } + // //clock power + // clockNetwork.init_wire_external(is_default, &interface_ip); + // clockNetwork.clk_area =area*1.1;//10% of placement overhead. + // rule of thumb clockNetwork.end_wiring_level =5;//toplevel metal + // clockNetwork.start_wiring_level =5;//toplevel metal + // clockNetwork.num_regs = corepipe.tot_stage_vector; + // clockNetwork.optimize_wire(); +} + +void BranchPredictor::computeEnergy(bool is_tdp) { + if (!exist) + return; + double r_access; + double w_access; + if (is_tdp) { + r_access = coredynp.predictionW * coredynp.BR_duty_cycle; + w_access = 0 * coredynp.BR_duty_cycle; + globalBPT->stats_t.readAc.access = r_access; + globalBPT->stats_t.writeAc.access = w_access; + globalBPT->tdp_stats = globalBPT->stats_t; + + L1_localBPT->stats_t.readAc.access = r_access; + L1_localBPT->stats_t.writeAc.access = w_access; + L1_localBPT->tdp_stats = L1_localBPT->stats_t; + + L2_localBPT->stats_t.readAc.access = r_access; + L2_localBPT->stats_t.writeAc.access = w_access; + L2_localBPT->tdp_stats = L2_localBPT->stats_t; + + chooser->stats_t.readAc.access = r_access; + chooser->stats_t.writeAc.access = w_access; + chooser->tdp_stats = chooser->stats_t; + + RAS->stats_t.readAc.access = r_access; + RAS->stats_t.writeAc.access = w_access; + RAS->tdp_stats = RAS->stats_t; + } + else { + // The resolution of BPT accesses is coarse, but this is + // because most simulators cannot track finer grained details + r_access = XML->sys.core[ithCore].branch_instructions; + w_access = + XML->sys.core[ithCore].branch_mispredictions + + 0.1 * XML->sys.core[ithCore] + .branch_instructions; // 10% of BR will flip internal bits//0 + globalBPT->stats_t.readAc.access = r_access; + globalBPT->stats_t.writeAc.access = w_access; + globalBPT->rtp_stats = globalBPT->stats_t; + + L1_localBPT->stats_t.readAc.access = r_access; + L1_localBPT->stats_t.writeAc.access = w_access; + L1_localBPT->rtp_stats = L1_localBPT->stats_t; + + L2_localBPT->stats_t.readAc.access = r_access; + L2_localBPT->stats_t.writeAc.access = w_access; + L2_localBPT->rtp_stats = L2_localBPT->stats_t; + + chooser->stats_t.readAc.access = r_access; + chooser->stats_t.writeAc.access = w_access; + chooser->rtp_stats = chooser->stats_t; + + RAS->stats_t.readAc.access = XML->sys.core[ithCore].function_calls; + RAS->stats_t.writeAc.access = XML->sys.core[ithCore].function_calls; + RAS->rtp_stats = RAS->stats_t; + } + + globalBPT->power_t.reset(); + L1_localBPT->power_t.reset(); + L2_localBPT->power_t.reset(); + chooser->power_t.reset(); + RAS->power_t.reset(); + + globalBPT->power_t.readOp.dynamic += + globalBPT->local_result.power.readOp.dynamic * + globalBPT->stats_t.readAc.access + + globalBPT->stats_t.writeAc.access * + globalBPT->local_result.power.writeOp.dynamic; + L1_localBPT->power_t.readOp.dynamic += + L1_localBPT->local_result.power.readOp.dynamic * + L1_localBPT->stats_t.readAc.access + + L1_localBPT->stats_t.writeAc.access * + L1_localBPT->local_result.power.writeOp.dynamic; + + L2_localBPT->power_t.readOp.dynamic += + L2_localBPT->local_result.power.readOp.dynamic * + L2_localBPT->stats_t.readAc.access + + L2_localBPT->stats_t.writeAc.access * + L2_localBPT->local_result.power.writeOp.dynamic; + + chooser->power_t.readOp.dynamic += + chooser->local_result.power.readOp.dynamic * + chooser->stats_t.readAc.access + + chooser->stats_t.writeAc.access * + chooser->local_result.power.writeOp.dynamic; + RAS->power_t.readOp.dynamic += + RAS->local_result.power.readOp.dynamic * RAS->stats_t.readAc.access + + RAS->stats_t.writeAc.access * RAS->local_result.power.writeOp.dynamic; + + if (is_tdp) { + globalBPT->power = + globalBPT->power_t + globalBPT->local_result.power * pppm_lkg; + L1_localBPT->power = + L1_localBPT->power_t + L1_localBPT->local_result.power * pppm_lkg; + L2_localBPT->power = + L2_localBPT->power_t + L2_localBPT->local_result.power * pppm_lkg; + chooser->power = chooser->power_t + chooser->local_result.power * pppm_lkg; + RAS->power = + RAS->power_t + RAS->local_result.power * coredynp.pppm_lkg_multhread; + + power = power + globalBPT->power + L1_localBPT->power + L2_localBPT->power + + chooser->power + RAS->power; + } + else { + globalBPT->rt_power = + globalBPT->power_t + globalBPT->local_result.power * pppm_lkg; + L1_localBPT->rt_power = + L1_localBPT->power_t + L1_localBPT->local_result.power * pppm_lkg; + L2_localBPT->rt_power = + L2_localBPT->power_t + L2_localBPT->local_result.power * pppm_lkg; + chooser->rt_power = + chooser->power_t + chooser->local_result.power * pppm_lkg; + RAS->rt_power = + RAS->power_t + RAS->local_result.power * coredynp.pppm_lkg_multhread; + rt_power = rt_power + globalBPT->rt_power + L1_localBPT->rt_power + + L2_localBPT->rt_power + chooser->rt_power + RAS->rt_power; + } +} + +void BranchPredictor::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + if (is_tdp) { + cout << indent_str << "Global Predictor:" << endl; + cout << indent_str_next << "Area = " << globalBPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << globalBPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? globalBPT->power.readOp.longer_channel_leakage + : globalBPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? globalBPT->power.readOp + .power_gated_with_long_channel_leakage + : globalBPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << globalBPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << globalBPT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "Local Predictor:" << endl; + cout << indent_str << "L1_Local Predictor:" << endl; + cout << indent_str_next << "Area = " << L1_localBPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << L1_localBPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? L1_localBPT->power.readOp.longer_channel_leakage + : L1_localBPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? L1_localBPT->power.readOp + .power_gated_with_long_channel_leakage + : L1_localBPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << L1_localBPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << L1_localBPT->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + cout << indent_str << "L2_Local Predictor:" << endl; + cout << indent_str_next << "Area = " << L2_localBPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << L2_localBPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? L2_localBPT->power.readOp.longer_channel_leakage + : L2_localBPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? L2_localBPT->power.readOp + .power_gated_with_long_channel_leakage + : L2_localBPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << L2_localBPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << L2_localBPT->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + + cout << indent_str << "Chooser:" << endl; + cout << indent_str_next << "Area = " << chooser->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << chooser->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? chooser->power.readOp.longer_channel_leakage + : chooser->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? chooser->power.readOp.power_gated_with_long_channel_leakage + : chooser->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << chooser->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << chooser->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "RAS:" << endl; + cout << indent_str_next << "Area = " << RAS->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << RAS->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? RAS->power.readOp.longer_channel_leakage + : RAS->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? RAS->power.readOp.power_gated_with_long_channel_leakage + : RAS->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << RAS->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << RAS->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + else { + // cout << indent_str_next << "Global Predictor Peak Dynamic = " + //<< globalBPT->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Global Predictor Subthreshold + // Leakage = " << globalBPT->rt_power.readOp.leakage <<" W" << endl; cout + // << + // indent_str_next << "Global Predictor Gate Leakage = " << + // globalBPT->rt_power.readOp.gate_leakage << " W" << endl; + // cout + // << indent_str_next << "Local Predictor Peak Dynamic = " << + // L1_localBPT->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Local Predictor Subthreshold + // Leakage + //= + //" + //<< L1_localBPT->rt_power.readOp.leakage << " W" << endl; + // cout << indent_str_next << "Local Predictor Gate Leakage = " + //<< L1_localBPT->rt_power.readOp.gate_leakage << " W" << endl; + // cout << indent_str_next << "Chooser Peak Dynamic = " << + // chooser->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Chooser Subthreshold Leakage = " + //<< chooser->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Chooser Gate Leakage = " << + // chooser->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "RAS Peak Dynamic = " << + // RAS->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "RAS Subthreshold Leakage = " << + // RAS->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "RAS Gate Leakage = " << + // RAS->rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void InstFetchU::computeEnergy(bool is_tdp) { + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + icache.caches->stats_t.readAc.access = + icache.caches->l_ip.num_rw_ports * coredynp.IFU_duty_cycle; + icache.caches->stats_t.readAc.miss = 0; + icache.caches->stats_t.readAc.hit = icache.caches->stats_t.readAc.access - + icache.caches->stats_t.readAc.miss; + icache.caches->tdp_stats = icache.caches->stats_t; + + icache.missb->stats_t.readAc.access = icache.missb->stats_t.readAc.hit = + icache.missb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.missb->stats_t.writeAc.access = icache.missb->stats_t.writeAc.hit = + icache.missb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.missb->tdp_stats = icache.missb->stats_t; + + icache.ifb->stats_t.readAc.access = icache.ifb->stats_t.readAc.hit = + icache.ifb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.ifb->stats_t.writeAc.access = icache.ifb->stats_t.writeAc.hit = + icache.ifb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.ifb->tdp_stats = icache.ifb->stats_t; + + icache.prefetchb->stats_t.readAc.access = + icache.prefetchb->stats_t.readAc.hit = + icache.prefetchb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.prefetchb->stats_t.writeAc.access = icache.ifb->stats_t.writeAc.hit = + icache.ifb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + icache.prefetchb->tdp_stats = icache.prefetchb->stats_t; + + IB->stats_t.readAc.access = IB->stats_t.writeAc.access = + XML->sys.core[ithCore].peak_issue_width; + IB->tdp_stats = IB->stats_t; + + if (coredynp.predictionW > 0) { + BTB->stats_t.readAc.access = + coredynp.predictionW; // XML->sys.core[ithCore].BTB.read_accesses; + BTB->stats_t.writeAc.access = + 0; // XML->sys.core[ithCore].BTB.write_accesses; + } + + ID_inst->stats_t.readAc.access = coredynp.decodeW; + ID_operand->stats_t.readAc.access = coredynp.decodeW; + ID_misc->stats_t.readAc.access = coredynp.decodeW; + ID_inst->tdp_stats = ID_inst->stats_t; + ID_operand->tdp_stats = ID_operand->stats_t; + ID_misc->tdp_stats = ID_misc->stats_t; + } + else { + // init stats for Runtime Dynamic (RTP) + icache.caches->stats_t.readAc.access = + XML->sys.core[ithCore].icache.read_accesses; + icache.caches->stats_t.readAc.miss = + XML->sys.core[ithCore].icache.read_misses; + icache.caches->stats_t.readAc.hit = icache.caches->stats_t.readAc.access - + icache.caches->stats_t.readAc.miss; + icache.caches->rtp_stats = icache.caches->stats_t; + + icache.missb->stats_t.readAc.access = icache.caches->stats_t.readAc.miss; + icache.missb->stats_t.writeAc.access = icache.caches->stats_t.readAc.miss; + icache.missb->rtp_stats = icache.missb->stats_t; + + icache.ifb->stats_t.readAc.access = icache.caches->stats_t.readAc.miss; + icache.ifb->stats_t.writeAc.access = icache.caches->stats_t.readAc.miss; + icache.ifb->rtp_stats = icache.ifb->stats_t; + + icache.prefetchb->stats_t.readAc.access = + icache.caches->stats_t.readAc.miss; + icache.prefetchb->stats_t.writeAc.access = + icache.caches->stats_t.readAc.miss; + icache.prefetchb->rtp_stats = icache.prefetchb->stats_t; + + IB->stats_t.readAc.access = IB->stats_t.writeAc.access = + XML->sys.core[ithCore].total_instructions; + IB->rtp_stats = IB->stats_t; + + if (coredynp.predictionW > 0) { + BTB->stats_t.readAc.access = + XML->sys.core[ithCore] + .BTB + .read_accesses; // XML->sys.core[ithCore].branch_instructions; + BTB->stats_t.writeAc.access = + XML->sys.core[ithCore] + .BTB + .write_accesses; // XML->sys.core[ithCore].branch_mispredictions; + BTB->rtp_stats = BTB->stats_t; + } + + ID_inst->stats_t.readAc.access = XML->sys.core[ithCore].total_instructions; + ID_operand->stats_t.readAc.access = + XML->sys.core[ithCore].total_instructions; + ID_misc->stats_t.readAc.access = XML->sys.core[ithCore].total_instructions; + ID_inst->rtp_stats = ID_inst->stats_t; + ID_operand->rtp_stats = ID_operand->stats_t; + ID_misc->rtp_stats = ID_misc->stats_t; + } + + icache.power_t.reset(); + IB->power_t.reset(); + // ID_inst->power_t.reset(); + // ID_operand->power_t.reset(); + // ID_misc->power_t.reset(); + if (coredynp.predictionW > 0) { + BTB->power_t.reset(); + } + + icache.power_t.readOp.dynamic += + (icache.caches->stats_t.readAc.hit * + icache.caches->local_result.power.readOp.dynamic + + // icache.caches->stats_t.readAc.miss*icache.caches->local_result.tag_array2->power.readOp.dynamic+ + icache.caches->stats_t.readAc.miss * + icache.caches->local_result.power.readOp + .dynamic + // assume tag data accessed in parallel + icache.caches->stats_t.readAc.miss * + icache.caches->local_result.power.writeOp + .dynamic); // read miss in Icache cause a write to Icache + icache.power_t.readOp.dynamic += + icache.missb->stats_t.readAc.access * + icache.missb->local_result.power.searchOp.dynamic + + icache.missb->stats_t.writeAc.access * + icache.missb->local_result.power.writeOp + .dynamic; // each access to missb involves a CAM and a write + icache.power_t.readOp.dynamic += + icache.ifb->stats_t.readAc.access * + icache.ifb->local_result.power.searchOp.dynamic + + icache.ifb->stats_t.writeAc.access * + icache.ifb->local_result.power.writeOp.dynamic; + icache.power_t.readOp.dynamic += + icache.prefetchb->stats_t.readAc.access * + icache.prefetchb->local_result.power.searchOp.dynamic + + icache.prefetchb->stats_t.writeAc.access * + icache.prefetchb->local_result.power.writeOp.dynamic; + + IB->power_t.readOp.dynamic += + IB->local_result.power.readOp.dynamic * IB->stats_t.readAc.access + + IB->stats_t.writeAc.access * IB->local_result.power.writeOp.dynamic; + + if (coredynp.predictionW > 0) { + BTB->power_t.readOp.dynamic += + BTB->local_result.power.readOp.dynamic * BTB->stats_t.readAc.access + + BTB->stats_t.writeAc.access * BTB->local_result.power.writeOp.dynamic; + + BPT->computeEnergy(is_tdp); + } + + if (is_tdp) { + // icache.power = icache.power_t + + // (icache.caches->local_result.power)*pppm_lkg + + // (icache.missb->local_result.power + + // icache.ifb->local_result.power + + // icache.prefetchb->local_result.power)*pppm_Isub; + icache.power = icache.power_t + (icache.caches->local_result.power + + icache.missb->local_result.power + + icache.ifb->local_result.power + + icache.prefetchb->local_result.power) * + pppm_lkg; + + IB->power = IB->power_t + IB->local_result.power * pppm_lkg; + power = power + icache.power + IB->power; + if (coredynp.predictionW > 0) { + BTB->power = BTB->power_t + BTB->local_result.power * pppm_lkg; + power = power + BTB->power + BPT->power; + } + + ID_inst->power_t.readOp.dynamic = ID_inst->power.readOp.dynamic; + ID_operand->power_t.readOp.dynamic = ID_operand->power.readOp.dynamic; + ID_misc->power_t.readOp.dynamic = ID_misc->power.readOp.dynamic; + + ID_inst->power.readOp.dynamic *= ID_inst->tdp_stats.readAc.access; + ID_operand->power.readOp.dynamic *= ID_operand->tdp_stats.readAc.access; + ID_misc->power.readOp.dynamic *= ID_misc->tdp_stats.readAc.access; + + power = power + (ID_inst->power + ID_operand->power + ID_misc->power); + } + else { + // icache.rt_power = icache.power_t + + // (icache.caches->local_result.power)*pppm_lkg + + // (icache.missb->local_result.power + + // icache.ifb->local_result.power + + // icache.prefetchb->local_result.power)*pppm_Isub; + + icache.rt_power = icache.power_t + (icache.caches->local_result.power + + icache.missb->local_result.power + + icache.ifb->local_result.power + + icache.prefetchb->local_result.power) * + pppm_lkg; + + IB->rt_power = IB->power_t + IB->local_result.power * pppm_lkg; + rt_power = rt_power + icache.rt_power + IB->rt_power; + if (coredynp.predictionW > 0) { + BTB->rt_power = BTB->power_t + BTB->local_result.power * pppm_lkg; + rt_power = rt_power + BTB->rt_power + BPT->rt_power; + } + + ID_inst->rt_power.readOp.dynamic = + ID_inst->power_t.readOp.dynamic * ID_inst->rtp_stats.readAc.access; + ID_operand->rt_power.readOp.dynamic = ID_operand->power_t.readOp.dynamic * + ID_operand->rtp_stats.readAc.access; + ID_misc->rt_power.readOp.dynamic = + ID_misc->power_t.readOp.dynamic * ID_misc->rtp_stats.readAc.access; + + rt_power = rt_power + + (ID_inst->rt_power + ID_operand->rt_power + ID_misc->rt_power); + } +} + +void InstFetchU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Instruction Cache:" << endl; + cout << indent_str_next << "Area = " << icache.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << icache.power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? icache.power.readOp.longer_channel_leakage + : icache.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? icache.power.readOp.power_gated_with_long_channel_leakage + : icache.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << icache.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << icache.rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (coredynp.predictionW > 0) { + cout << indent_str << "Branch Target Buffer:" << endl; + cout << indent_str_next << "Area = " << BTB->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << BTB->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? BTB->power.readOp.longer_channel_leakage + : BTB->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? BTB->power.readOp.power_gated_with_long_channel_leakage + : BTB->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << BTB->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << BTB->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (BPT->exist) { + cout << indent_str << "Branch Predictor:" << endl; + cout << indent_str_next << "Area = " << BPT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << BPT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? BPT->power.readOp.longer_channel_leakage + : BPT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? BPT->power.readOp.power_gated_with_long_channel_leakage + : BPT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << BPT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << BPT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 3) { + BPT->displayEnergy(indent + 4, plevel, is_tdp); + } + } + } + cout << indent_str << "Instruction Buffer:" << endl; + cout << indent_str_next << "Area = " << IB->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << IB->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? IB->power.readOp.longer_channel_leakage + : IB->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? IB->power.readOp.power_gated_with_long_channel_leakage + : IB->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << IB->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << IB->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + cout << indent_str << "Instruction Decoder:" << endl; + cout << indent_str_next << "Area = " + << (ID_inst->area.get_area() + ID_operand->area.get_area() + + ID_misc->area.get_area()) * + coredynp.decodeW * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << (ID_inst->power.readOp.dynamic + ID_operand->power.readOp.dynamic + + ID_misc->power.readOp.dynamic) * + clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? (ID_inst->power.readOp.longer_channel_leakage + + ID_operand->power.readOp.longer_channel_leakage + + ID_misc->power.readOp.longer_channel_leakage) + : (ID_inst->power.readOp.leakage + + ID_operand->power.readOp.leakage + + ID_misc->power.readOp.leakage)) + << " W" << endl; + + // double tot_leakage = + // (ID_inst->power.readOp.leakage + ID_operand->power.readOp.leakage + + // ID_misc->power.readOp.leakage); + // double tot_leakage_longchannel = + // (ID_inst->power.readOp.longer_channel_leakage + + // ID_operand->power.readOp.longer_channel_leakage + + // ID_misc->power.readOp.longer_channel_leakage); + double tot_leakage_pg = (ID_inst->power.readOp.power_gated_leakage + + ID_operand->power.readOp.power_gated_leakage + + ID_misc->power.readOp.power_gated_leakage); + double tot_leakage_pg_with_long_channel = + (ID_inst->power.readOp.power_gated_with_long_channel_leakage + + ID_operand->power.readOp.power_gated_with_long_channel_leakage + + ID_misc->power.readOp.power_gated_with_long_channel_leakage); + + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? tot_leakage_pg_with_long_channel : tot_leakage_pg) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " + << (ID_inst->power.readOp.gate_leakage + + ID_operand->power.readOp.gate_leakage + + ID_misc->power.readOp.gate_leakage) + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << (ID_inst->rt_power.readOp.dynamic + + ID_operand->rt_power.readOp.dynamic + + ID_misc->rt_power.readOp.dynamic) / + executionTime + << " W" << endl; + cout << endl; + } + else { + // cout << indent_str_next << "Instruction Cache Peak Dynamic = + //" + //<< icache.rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Instruction Cache Subthreshold + // Leakage + //= " << icache.rt_power.readOp.leakage <<" W" << endl; cout << + // indent_str_next << "Instruction Cache Gate Leakage = " << + // icache.rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Instruction Buffer Peak Dynamic = " << + // IB->rt_power.readOp.dynamic*clockRate << " W" << endl; cout << + // indent_str_next << "Instruction Buffer Subthreshold Leakage = " << + // IB->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Instruction Buffer Gate Leakage = " << + // IB->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Branch Target Buffer Peak Dynamic = " << + // BTB->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Branch Target Buffer Subthreshold Leakage = " + // << BTB->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Branch Target Buffer Gate Leakage = " << + // BTB->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Branch Predictor Peak Dynamic = " << + // BPT->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Branch Predictor Subthreshold Leakage = " << + // BPT->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Branch Predictor Gate Leakage = " << + // BPT->rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void RENAMINGU::computeEnergy(bool is_tdp) { + if (!exist) + return; + double pppm_t[4] = {1, 1, 1, 1}; + if (is_tdp) { // init stats for Peak + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_rd_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_rd_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_search_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_search_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = iRRAT->l_ip.num_rd_ports; + iRRAT->stats_t.writeAc.access = iRRAT->l_ip.num_wr_ports; + iRRAT->tdp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = fRRAT->l_ip.num_rd_ports; + fRRAT->stats_t.writeAc.access = fRRAT->l_ip.num_wr_ports; + fRRAT->tdp_stats = fRRAT->stats_t; + } + ifreeL->stats_t.readAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_rd_ports;; + ifreeL->stats_t.writeAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_wr_ports; + ifreeL->tdp_stats = ifreeL->stats_t; + + ffreeL->stats_t.readAc.access = + coredynp.decodeW; // ffreeL->l_ip.num_rd_ports; + ffreeL->stats_t.writeAc.access = + coredynp.decodeW; // ffreeL->l_ip.num_wr_ports; + ffreeL->tdp_stats = ffreeL->stats_t; + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_rd_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_rd_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = iFRAT->l_ip.num_search_ports; + iFRAT->stats_t.writeAc.access = iFRAT->l_ip.num_wr_ports; + iFRAT->tdp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = fFRAT->l_ip.num_search_ports; + fFRAT->stats_t.writeAc.access = fFRAT->l_ip.num_wr_ports; + fFRAT->tdp_stats = fFRAT->stats_t; + } + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = iRRAT->l_ip.num_rd_ports; + iRRAT->stats_t.writeAc.access = iRRAT->l_ip.num_wr_ports; + iRRAT->tdp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = fRRAT->l_ip.num_rd_ports; + fRRAT->stats_t.writeAc.access = fRRAT->l_ip.num_wr_ports; + fRRAT->tdp_stats = fRRAT->stats_t; + } + // Unified free list for both int and fp + ifreeL->stats_t.readAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_rd_ports; + ifreeL->stats_t.writeAc.access = + coredynp.decodeW; // ifreeL->l_ip.num_wr_ports; + ifreeL->tdp_stats = ifreeL->stats_t; + } + idcl->stats_t.readAc.access = coredynp.decodeW; + fdcl->stats_t.readAc.access = coredynp.decodeW; + idcl->tdp_stats = idcl->stats_t; + fdcl->tdp_stats = fdcl->stats_t; + } + else { + if (coredynp.issueW > 1) { + idcl->stats_t.readAc.access = coredynp.decodeW; + fdcl->stats_t.readAc.access = coredynp.decodeW; + idcl->tdp_stats = idcl->stats_t; + fdcl->tdp_stats = fdcl->stats_t; + } + } + } + else { // init stats for Runtime Dynamic (RTP) + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fFRAT->rtp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fFRAT->rtp_stats = fFRAT->stats_t; + } + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].rename_writes; // Hack, should be (context + // switch + branch + // mispredictions)*16 + iRRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iRRAT->rtp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].fp_rename_writes; // Hack, should be + // (context switch + + // branch + // mispredictions)*16 + fRRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fRRAT->rtp_stats = fRRAT->stats_t; + } + ifreeL->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + ifreeL->stats_t.writeAc.access = + 2 * XML->sys.core[ithCore].rename_writes; + ifreeL->rtp_stats = ifreeL->stats_t; + + ffreeL->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + ffreeL->stats_t.writeAc.access = + 2 * XML->sys.core[ithCore].fp_rename_writes; + ffreeL->rtp_stats = ffreeL->stats_t; + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + // iFRAT->stats_t.searchAc.access = + // XML->sys.core[ithCore].committed_int_instructions;//hack: not all + // committed instructions use regs. + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + // fFRAT->stats_t.searchAc.access = + // XML->sys.core[ithCore].committed_fp_instructions; + fFRAT->rtp_stats = fFRAT->stats_t; + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads; + iFRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iFRAT->rtp_stats = iFRAT->stats_t; + + fFRAT->stats_t.readAc.access = XML->sys.core[ithCore].fp_rename_reads; + fFRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fFRAT->rtp_stats = fFRAT->stats_t; + } + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].rename_writes; // Hack, should be (context + // switch + branch + // mispredictions)*16 + iRRAT->stats_t.writeAc.access = XML->sys.core[ithCore].rename_writes; + iRRAT->rtp_stats = iRRAT->stats_t; + + fRRAT->stats_t.readAc.access = + XML->sys.core[ithCore].fp_rename_writes; // Hack, should be + // (context switch + + // branch + // mispredictions)*16 + fRRAT->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_rename_writes; + fRRAT->rtp_stats = fRRAT->stats_t; + } + // Unified free list for both int and fp since the ROB act as physcial + // registers + ifreeL->stats_t.readAc.access = XML->sys.core[ithCore].rename_reads + + XML->sys.core[ithCore].fp_rename_reads; + ifreeL->stats_t.writeAc.access = + 2 * (XML->sys.core[ithCore].rename_writes + + XML->sys.core[ithCore].fp_rename_writes); // HACK: 2-> since + // some of renaming + // in the same group + // are terminated + // early + ifreeL->rtp_stats = ifreeL->stats_t; + } + idcl->stats_t.readAc.access = 3 * coredynp.decodeW * coredynp.decodeW * + XML->sys.core[ithCore].rename_reads; + fdcl->stats_t.readAc.access = 3 * coredynp.fp_issueW * + coredynp.fp_issueW * + XML->sys.core[ithCore].fp_rename_writes; + idcl->rtp_stats = idcl->stats_t; + fdcl->rtp_stats = fdcl->stats_t; + } + else { + if (coredynp.issueW > 1) { + idcl->stats_t.readAc.access = + 2 * XML->sys.core[ithCore].int_instructions; + fdcl->stats_t.readAc.access = XML->sys.core[ithCore].fp_instructions; + idcl->rtp_stats = idcl->stats_t; + fdcl->rtp_stats = fdcl->stats_t; + } + } + } + /* Compute engine */ + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.readOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.readOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.searchOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.searchOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power_t.reset(); + fRRAT->power_t.reset(); + + iRRAT->power_t.readOp.dynamic += + (iRRAT->stats_t.readAc.access * + iRRAT->local_result.power.readOp.dynamic + + iRRAT->stats_t.writeAc.access * + iRRAT->local_result.power.writeOp.dynamic); + fRRAT->power_t.readOp.dynamic += + (fRRAT->stats_t.readAc.access * + fRRAT->local_result.power.readOp.dynamic + + fRRAT->stats_t.writeAc.access * + fRRAT->local_result.power.writeOp.dynamic); + } + + ifreeL->power_t.reset(); + ffreeL->power_t.reset(); + ifreeL->power_t.readOp.dynamic += + (ifreeL->stats_t.readAc.access * + ifreeL->local_result.power.readOp.dynamic + + ifreeL->stats_t.writeAc.access * + ifreeL->local_result.power.writeOp.dynamic); + ffreeL->power_t.readOp.dynamic += + (ffreeL->stats_t.readAc.access * + ffreeL->local_result.power.readOp.dynamic + + ffreeL->stats_t.writeAc.access * + ffreeL->local_result.power.writeOp.dynamic); + } + else if (coredynp.scheu_ty == ReservationStation) { + if (coredynp.rm_ty == RAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.readOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.readOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + else if (coredynp.rm_ty == CAMbased) { + iFRAT->power_t.reset(); + fFRAT->power_t.reset(); + iFRAT->power_t.readOp.dynamic += + (iFRAT->stats_t.readAc.access * + (iFRAT->local_result.power.searchOp.dynamic + + idcl->power.readOp.dynamic) + + iFRAT->stats_t.writeAc.access * + iFRAT->local_result.power.writeOp.dynamic); + fFRAT->power_t.readOp.dynamic += + (fFRAT->stats_t.readAc.access * + (fFRAT->local_result.power.searchOp.dynamic + + fdcl->power.readOp.dynamic) + + fFRAT->stats_t.writeAc.access * + fFRAT->local_result.power.writeOp.dynamic); + } + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power_t.reset(); + fRRAT->power_t.reset(); + + iRRAT->power_t.readOp.dynamic += + (iRRAT->stats_t.readAc.access * + iRRAT->local_result.power.readOp.dynamic + + iRRAT->stats_t.writeAc.access * + iRRAT->local_result.power.writeOp.dynamic); + fRRAT->power_t.readOp.dynamic += + (fRRAT->stats_t.readAc.access * + fRRAT->local_result.power.readOp.dynamic + + fRRAT->stats_t.writeAc.access * + fRRAT->local_result.power.writeOp.dynamic); + } + + ifreeL->power_t.reset(); + ifreeL->power_t.readOp.dynamic += + (ifreeL->stats_t.readAc.access * + ifreeL->local_result.power.readOp.dynamic + + ifreeL->stats_t.writeAc.access * + ifreeL->local_result.power.writeOp.dynamic); + } + } + else { + if (coredynp.issueW > 1) { + idcl->power_t.reset(); + fdcl->power_t.reset(); + set_pppm(pppm_t, idcl->stats_t.readAc.access, coredynp.num_hthreads, + coredynp.num_hthreads, idcl->stats_t.readAc.access); + idcl->power_t = idcl->power * pppm_t; + set_pppm(pppm_t, fdcl->stats_t.readAc.access, coredynp.num_hthreads, + coredynp.num_hthreads, idcl->stats_t.readAc.access); + fdcl->power_t = fdcl->power * pppm_t; + } + } + + // assign value to tpd and rtp + if (is_tdp) { + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + iFRAT->power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + ifreeL->power = ifreeL->power_t + ifreeL->local_result.power; + ffreeL->power = ffreeL->power_t + ffreeL->local_result.power; + power = power + + (iFRAT->power + fFRAT->power) + //+ (iRRAT->power + fRRAT->power) + + (ifreeL->power + ffreeL->power); + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->power = fRRAT->power_t + fRRAT->local_result.power; + power = power + (iRRAT->power + fRRAT->power); + } + } + else if (coredynp.scheu_ty == ReservationStation) { + iFRAT->power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + ifreeL->power = ifreeL->power_t + ifreeL->local_result.power; + power = power + (iFRAT->power + fFRAT->power) + ifreeL->power; + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->power = fRRAT->power_t + fRRAT->local_result.power; + power = power + (iRRAT->power + fRRAT->power); + } + } + } + else { + power = power + idcl->power_t + fdcl->power_t; + } + } + else { + if (coredynp.core_ty == OOO) { + if (coredynp.scheu_ty == PhysicalRegFile) { + iFRAT->rt_power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->rt_power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + + ifreeL->rt_power = ifreeL->power_t + ifreeL->local_result.power; + ffreeL->rt_power = ffreeL->power_t + ffreeL->local_result.power; + rt_power = rt_power + + (iFRAT->rt_power + fFRAT->rt_power) + // + (iRRAT->rt_power + + // fRRAT->rt_power) + + (ifreeL->rt_power + ffreeL->rt_power); + + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->rt_power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->rt_power = fRRAT->power_t + fRRAT->local_result.power; + rt_power = rt_power + (iRRAT->rt_power + fRRAT->rt_power); + } + } + else if (coredynp.scheu_ty == ReservationStation) { + iFRAT->rt_power = + iFRAT->power_t + (iFRAT->local_result.power) + idcl->power_t; + fFRAT->rt_power = + fFRAT->power_t + (fFRAT->local_result.power) + fdcl->power_t; + ifreeL->rt_power = ifreeL->power_t + ifreeL->local_result.power; + rt_power = + rt_power + (iFRAT->rt_power + fFRAT->rt_power) + ifreeL->rt_power; + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + iRRAT->rt_power = iRRAT->power_t + iRRAT->local_result.power; + fRRAT->rt_power = fRRAT->power_t + fRRAT->local_result.power; + rt_power = rt_power + (iRRAT->rt_power + fRRAT->rt_power); + } + } + } + else { + rt_power = rt_power + idcl->power_t + fdcl->power_t; + } + } +} + +void RENAMINGU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + if (coredynp.core_ty == OOO) { + cout << indent_str << "Int Front End RAT with " + << coredynp.globalCheckpoint << " internal checkpoints:" << endl; + cout << indent_str_next << "Area = " << iFRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << iFRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? iFRAT->power.readOp.longer_channel_leakage + : iFRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? iFRAT->power.readOp.power_gated_with_long_channel_leakage + : iFRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << iFRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << iFRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "FP Front End RAT with " + << coredynp.globalCheckpoint << " internal checkpoints:" << endl; + cout << indent_str_next << "Area = " << fFRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << fFRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? fFRAT->power.readOp.longer_channel_leakage + : fFRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? fFRAT->power.readOp.power_gated_with_long_channel_leakage + : fFRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fFRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fFRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "Free List:" << endl; + cout << indent_str_next << "Area = " << ifreeL->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ifreeL->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ifreeL->power.readOp.longer_channel_leakage + : ifreeL->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout + << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? ifreeL->power.readOp.power_gated_with_long_channel_leakage + : ifreeL->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ifreeL->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ifreeL->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + cout << indent_str << "Int Retire RAT: " << endl; + cout << indent_str_next << "Area = " << iRRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << iRRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? iRRAT->power.readOp.longer_channel_leakage + : iRRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? iRRAT->power.readOp + .power_gated_with_long_channel_leakage + : iRRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << iRRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << iRRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "FP Retire RAT:" << endl; + cout << indent_str_next << "Area = " << fRRAT->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << fRRAT->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? fRRAT->power.readOp.longer_channel_leakage + : fRRAT->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? fRRAT->power.readOp + .power_gated_with_long_channel_leakage + : fRRAT->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fRRAT->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fRRAT->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + if (coredynp.scheu_ty == PhysicalRegFile) { + cout << indent_str << "FP Free List:" << endl; + cout << indent_str_next << "Area = " << ffreeL->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ffreeL->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ffreeL->power.readOp.longer_channel_leakage + : ffreeL->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? ffreeL->power.readOp + .power_gated_with_long_channel_leakage + : ffreeL->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ffreeL->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ffreeL->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << indent_str << "Int DCL:" << endl; + cout << indent_str_next + << "Peak Dynamic = " << idcl->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? idcl->power.readOp.longer_channel_leakage + : idcl->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? idcl->power.readOp.power_gated_with_long_channel_leakage + : idcl->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << idcl->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << idcl->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << indent_str << "FP DCL:" << endl; + cout << indent_str_next + << "Peak Dynamic = " << fdcl->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? fdcl->power.readOp.longer_channel_leakage + : fdcl->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? fdcl->power.readOp.power_gated_with_long_channel_leakage + : fdcl->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fdcl->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fdcl->rt_power.readOp.dynamic / executionTime << " W" << endl; + } + } + else { + if (coredynp.core_ty == OOO) { + cout << indent_str_next << "Int Front End RAT Peak Dynamic = " + << iFRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Int Front End RAT Subthreshold Leakage = " + << iFRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Int Front End RAT Gate Leakage = " + << iFRAT->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "FP Front End RAT Peak Dynamic = " + << fFRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP Front End RAT Subthreshold Leakage = " + << fFRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Front End RAT Gate Leakage = " + << fFRAT->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Free List Peak Dynamic = " + << ifreeL->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Free List Subthreshold Leakage = " + << ifreeL->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Free List Gate Leakage = " + << fFRAT->rt_power.readOp.gate_leakage << " W" << endl; + if (coredynp.scheu_ty == PhysicalRegFile) { + if ((coredynp.rm_ty == RAMbased) && (coredynp.globalCheckpoint < 1)) { + cout << indent_str_next << "Int Retire RAT Peak Dynamic = " + << iRRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Int Retire RAT Subthreshold Leakage = " + << iRRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Int Retire RAT Gate Leakage = " + << iRRAT->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "FP Retire RAT Peak Dynamic = " + << fRRAT->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP Retire RAT Subthreshold Leakage = " + << fRRAT->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Retire RAT Gate Leakage = " + << fRRAT->rt_power.readOp.gate_leakage << " W" << endl; + } + cout << indent_str_next << "FP Free List Peak Dynamic = " + << ffreeL->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP Free List Subthreshold Leakage = " + << ffreeL->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Free List Gate Leakage = " + << fFRAT->rt_power.readOp.gate_leakage << " W" << endl; + } + } + else { + cout << indent_str_next << "Int DCL Peak Dynamic = " + << idcl->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Int DCL Subthreshold Leakage = " + << idcl->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "Int DCL Gate Leakage = " << idcl->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "FP DCL Peak Dynamic = " + << fdcl->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "FP DCL Subthreshold Leakage = " + << fdcl->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "FP DCL Gate Leakage = " << fdcl->rt_power.readOp.gate_leakage + << " W" << endl; + } + } +} + +void SchedulerU::computeEnergy(bool is_tdp) { + if (!exist) + return; + double ROB_duty_cycle; + // ROB_duty_cycle = ((coredynp.ALU_duty_cycle + + // coredynp.num_muls>0?coredynp.MUL_duty_cycle:0 + // + coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0))*1.1<1 + //? (coredynp.ALU_duty_cycle + coredynp.num_muls>0?coredynp.MUL_duty_cycle:0 + // + + // coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0)*1.1:1; + ROB_duty_cycle = 1; + // init stats + if (is_tdp) { + if (coredynp.core_ty == OOO) { + int_inst_window->stats_t.readAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_search_ports; + int_inst_window->stats_t.writeAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_wr_ports; + int_inst_window->stats_t.searchAc.access = + coredynp.issueW * coredynp.num_pipelines; + int_inst_window->tdp_stats = int_inst_window->stats_t; + fp_inst_window->stats_t.readAc.access = + fp_inst_window->l_ip.num_rd_ports * coredynp.num_fp_pipelines; + fp_inst_window->stats_t.writeAc.access = + fp_inst_window->l_ip.num_wr_ports * coredynp.num_fp_pipelines; + fp_inst_window->stats_t.searchAc.access = + fp_inst_window->l_ip.num_search_ports * coredynp.num_fp_pipelines; + fp_inst_window->tdp_stats = fp_inst_window->stats_t; + + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->stats_t.readAc.access = + coredynp.commitW * coredynp.num_pipelines * ROB_duty_cycle; + ROB->stats_t.writeAc.access = + coredynp.issueW * coredynp.num_pipelines * ROB_duty_cycle; + ROB->tdp_stats = ROB->stats_t; + + /* + * When inst commits, ROB must be read. + * Because for Physcial register based cores, physical register tag in + * ROB need to be read out and write into RRAT/CAM based RAT. For RS + * based cores, register content that stored in ROB must be read out and + * stored in architectural registers. + * + * if no-register is involved, the ROB read out operation when + * instruction commits can be ignored. assuming 20% insts. belong this + * type. + * TODO: ROB duty_cycle need to be revisited + */ + } + } + else if (coredynp.multithreaded) { + int_inst_window->stats_t.readAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_search_ports; + int_inst_window->stats_t.writeAc.access = + coredynp.issueW * + coredynp.num_pipelines; // int_inst_window->l_ip.num_wr_ports; + int_inst_window->stats_t.searchAc.access = + coredynp.issueW * coredynp.num_pipelines; + int_inst_window->tdp_stats = int_inst_window->stats_t; + } + } + else { // rtp + if (coredynp.core_ty == OOO) { + int_inst_window->stats_t.readAc.access = + XML->sys.core[ithCore].inst_window_reads; + int_inst_window->stats_t.writeAc.access = + XML->sys.core[ithCore].inst_window_writes; + int_inst_window->stats_t.searchAc.access = + XML->sys.core[ithCore].inst_window_wakeup_accesses; + int_inst_window->rtp_stats = int_inst_window->stats_t; + fp_inst_window->stats_t.readAc.access = + XML->sys.core[ithCore].fp_inst_window_reads; + fp_inst_window->stats_t.writeAc.access = + XML->sys.core[ithCore].fp_inst_window_writes; + fp_inst_window->stats_t.searchAc.access = + XML->sys.core[ithCore].fp_inst_window_wakeup_accesses; + fp_inst_window->rtp_stats = fp_inst_window->stats_t; + + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->stats_t.readAc.access = XML->sys.core[ithCore].ROB_reads; + ROB->stats_t.writeAc.access = XML->sys.core[ithCore].ROB_writes; + /* ROB need to be updated in RS based OOO when new values are produced, + * this update may happen before the commit stage when ROB entry is + * released + * 1. ROB write at instruction inserted in + * 2. ROB write as results produced (for RS based OOO only) + * 3. ROB read as instruction committed. For RS based OOO, data values + * are read out and sent to ARF For Physical reg based OOO, no data + * stored in ROB, but register tags need to be read out and used to set + * the RRAT and to recycle the register tag to free list buffer + */ + ROB->rtp_stats = ROB->stats_t; + } + } + else if (coredynp.multithreaded) { + int_inst_window->stats_t.readAc.access = + XML->sys.core[ithCore].int_instructions + + XML->sys.core[ithCore].fp_instructions; + int_inst_window->stats_t.writeAc.access = + XML->sys.core[ithCore].int_instructions + + XML->sys.core[ithCore].fp_instructions; + int_inst_window->stats_t.searchAc.access = + 2 * (XML->sys.core[ithCore].int_instructions + + XML->sys.core[ithCore].fp_instructions); + int_inst_window->rtp_stats = int_inst_window->stats_t; + } + } + + // computation engine + if (coredynp.core_ty == OOO) { + int_inst_window->power_t.reset(); + fp_inst_window->power_t.reset(); + + /* each instruction needs to write to scheduler, read out when all resources + * and source operands are ready two search ops with one for each source + * operand + * + */ + int_inst_window->power_t.readOp.dynamic += + int_inst_window->local_result.power.readOp.dynamic * + int_inst_window->stats_t.readAc.access + + int_inst_window->local_result.power.searchOp.dynamic * + int_inst_window->stats_t.searchAc.access + + int_inst_window->local_result.power.writeOp.dynamic * + int_inst_window->stats_t.writeAc.access + + int_inst_window->stats_t.readAc.access * + instruction_selection->power.readOp.dynamic; + + fp_inst_window->power_t.readOp.dynamic += + fp_inst_window->local_result.power.readOp.dynamic * + fp_inst_window->stats_t.readAc.access + + fp_inst_window->local_result.power.searchOp.dynamic * + fp_inst_window->stats_t.searchAc.access + + fp_inst_window->local_result.power.writeOp.dynamic * + fp_inst_window->stats_t.writeAc.access + + fp_inst_window->stats_t.writeAc.access * + instruction_selection->power.readOp.dynamic; + + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->power_t.reset(); + ROB->power_t.readOp.dynamic += + ROB->local_result.power.readOp.dynamic * ROB->stats_t.readAc.access + + ROB->stats_t.writeAc.access * ROB->local_result.power.writeOp.dynamic; + } + } + else if (coredynp.multithreaded) { + int_inst_window->power_t.reset(); + int_inst_window->power_t.readOp.dynamic += + int_inst_window->local_result.power.readOp.dynamic * + int_inst_window->stats_t.readAc.access + + int_inst_window->local_result.power.searchOp.dynamic * + int_inst_window->stats_t.searchAc.access + + int_inst_window->local_result.power.writeOp.dynamic * + int_inst_window->stats_t.writeAc.access + + int_inst_window->stats_t.writeAc.access * + instruction_selection->power.readOp.dynamic; + } + + // assign values + if (is_tdp) { + if (coredynp.core_ty == OOO) { + int_inst_window->power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + fp_inst_window->power = + fp_inst_window->power_t + + (fp_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + power = power + int_inst_window->power + fp_inst_window->power; + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->power = ROB->power_t + ROB->local_result.power * pppm_lkg; + power = power + ROB->power; + } + } + else if (coredynp.multithreaded) { + // set_pppm(pppm_t, + // XML->sys.core[ithCore].issue_width,1, 1, 1); + int_inst_window->power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + power = power + int_inst_window->power; + } + } + else { // rtp + if (coredynp.core_ty == OOO) { + int_inst_window->rt_power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + fp_inst_window->rt_power = + fp_inst_window->power_t + + (fp_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + rt_power = + rt_power + int_inst_window->rt_power + fp_inst_window->rt_power; + if (XML->sys.core[ithCore].ROB_size > 0) { + ROB->rt_power = ROB->power_t + ROB->local_result.power * pppm_lkg; + rt_power = rt_power + ROB->rt_power; + } + } + else if (coredynp.multithreaded) { + // set_pppm(pppm_t, + // XML->sys.core[ithCore].issue_width,1, 1, 1); + int_inst_window->rt_power = + int_inst_window->power_t + + (int_inst_window->local_result.power + instruction_selection->power) * + pppm_lkg; + rt_power = rt_power + int_inst_window->rt_power; + } + } + // set_pppm(pppm_t, XML->sys.core[ithCore].issue_width,1, 1, 1); + // cout<<"Scheduler + // power="<power.readOp.dynamic<<"leakage"<power.readOp.leakage<sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + if (coredynp.core_ty == OOO) { + cout << indent_str << "Instruction Window:" << endl; + cout << indent_str_next + << "Area = " << int_inst_window->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << int_inst_window->power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? int_inst_window->power.readOp.longer_channel_leakage + : int_inst_window->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? int_inst_window->power.readOp + .power_gated_with_long_channel_leakage + : int_inst_window->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << int_inst_window->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << int_inst_window->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + cout << indent_str << "FP Instruction Window:" << endl; + cout << indent_str_next + << "Area = " << fp_inst_window->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << fp_inst_window->power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? fp_inst_window->power.readOp.longer_channel_leakage + : fp_inst_window->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? fp_inst_window->power.readOp + .power_gated_with_long_channel_leakage + : fp_inst_window->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << fp_inst_window->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << fp_inst_window->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + if (XML->sys.core[ithCore].ROB_size > 0) { + cout << indent_str << "ROB:" << endl; + cout << indent_str_next << "Area = " << ROB->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ROB->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ROB->power.readOp.longer_channel_leakage + : ROB->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? ROB->power.readOp.power_gated_with_long_channel_leakage + : ROB->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ROB->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ROB->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else if (coredynp.multithreaded) { + cout << indent_str << "Instruction Window:" << endl; + cout << indent_str_next + << "Area = " << int_inst_window->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << int_inst_window->power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? int_inst_window->power.readOp.longer_channel_leakage + : int_inst_window->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? int_inst_window->power.readOp + .power_gated_with_long_channel_leakage + : int_inst_window->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << int_inst_window->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << int_inst_window->rt_power.readOp.dynamic / executionTime << " W" + << endl; + cout << endl; + } + } + else { + if (coredynp.core_ty == OOO) { + cout << indent_str_next << "Instruction Window Peak Dynamic = " + << int_inst_window->rt_power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Instruction Window Subthreshold Leakage = " + << int_inst_window->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Instruction Window Gate Leakage = " + << int_inst_window->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "FP Instruction Window Peak Dynamic = " + << fp_inst_window->rt_power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next + << "FP Instruction Window Subthreshold Leakage = " + << fp_inst_window->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "FP Instruction Window Gate Leakage = " + << fp_inst_window->rt_power.readOp.gate_leakage << " W" << endl; + if (XML->sys.core[ithCore].ROB_size > 0) { + cout << indent_str_next << "ROB Peak Dynamic = " + << ROB->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "ROB Subthreshold Leakage = " << ROB->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "ROB Gate Leakage = " << ROB->rt_power.readOp.gate_leakage + << " W" << endl; + } + } + else if (coredynp.multithreaded) { + cout << indent_str_next << "Instruction Window Peak Dynamic = " + << int_inst_window->rt_power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Instruction Window Subthreshold Leakage = " + << int_inst_window->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Instruction Window Gate Leakage = " + << int_inst_window->rt_power.readOp.gate_leakage << " W" << endl; + } + } +} + +void LoadStoreU::computeEnergy(bool is_tdp) { + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + dcache.caches->stats_t.readAc.access = + 0.67 * dcache.caches->l_ip.num_rw_ports * coredynp.LSU_duty_cycle; + dcache.caches->stats_t.readAc.miss = 0; + dcache.caches->stats_t.readAc.hit = dcache.caches->stats_t.readAc.access - + dcache.caches->stats_t.readAc.miss; + dcache.caches->stats_t.writeAc.access = + 0.33 * dcache.caches->l_ip.num_rw_ports * coredynp.LSU_duty_cycle; + dcache.caches->stats_t.writeAc.miss = 0; + dcache.caches->stats_t.writeAc.hit = dcache.caches->stats_t.writeAc.access - + dcache.caches->stats_t.writeAc.miss; + dcache.caches->tdp_stats = dcache.caches->stats_t; + + dcache.missb->stats_t.readAc.access = + dcache.missb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.missb->stats_t.writeAc.access = + dcache.missb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.missb->tdp_stats = dcache.missb->stats_t; + + dcache.ifb->stats_t.readAc.access = + dcache.ifb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.ifb->stats_t.writeAc.access = + dcache.ifb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.ifb->tdp_stats = dcache.ifb->stats_t; + + dcache.prefetchb->stats_t.readAc.access = + dcache.prefetchb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.prefetchb->stats_t.writeAc.access = + dcache.ifb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dcache.prefetchb->tdp_stats = dcache.prefetchb->stats_t; + if (cache_p == Write_back) { + dcache.wbb->stats_t.readAc.access = dcache.wbb->l_ip.num_search_ports; + dcache.wbb->stats_t.writeAc.access = dcache.wbb->l_ip.num_search_ports; + dcache.wbb->tdp_stats = dcache.wbb->stats_t; + } + + LSQ->stats_t.readAc.access = LSQ->stats_t.writeAc.access = + LSQ->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + LSQ->tdp_stats = LSQ->stats_t; + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->stats_t.readAc.access = LoadQ->stats_t.writeAc.access = + LoadQ->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + LoadQ->tdp_stats = LoadQ->stats_t; + } + } + else { + // init stats for Runtime Dynamic (RTP) + dcache.caches->stats_t.readAc.access = + XML->sys.core[ithCore].dcache.read_accesses; + dcache.caches->stats_t.readAc.miss = + XML->sys.core[ithCore].dcache.read_misses; + dcache.caches->stats_t.readAc.hit = dcache.caches->stats_t.readAc.access - + dcache.caches->stats_t.readAc.miss; + dcache.caches->stats_t.writeAc.access = + XML->sys.core[ithCore].dcache.write_accesses; + dcache.caches->stats_t.writeAc.miss = + XML->sys.core[ithCore].dcache.write_misses; + dcache.caches->stats_t.writeAc.hit = dcache.caches->stats_t.writeAc.access - + dcache.caches->stats_t.writeAc.miss; + dcache.caches->rtp_stats = dcache.caches->stats_t; + + if (cache_p == Write_back) { + dcache.missb->stats_t.readAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.missb->stats_t.writeAc.access = + dcache.caches->stats_t.writeAc.miss; + dcache.missb->rtp_stats = dcache.missb->stats_t; + + dcache.ifb->stats_t.readAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.ifb->stats_t.writeAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.ifb->rtp_stats = dcache.ifb->stats_t; + + dcache.prefetchb->stats_t.readAc.access = + dcache.caches->stats_t.writeAc.miss; + dcache.prefetchb->stats_t.writeAc.access = + dcache.caches->stats_t.writeAc.miss; + dcache.prefetchb->rtp_stats = dcache.prefetchb->stats_t; + + dcache.wbb->stats_t.readAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.wbb->stats_t.writeAc.access = dcache.caches->stats_t.writeAc.miss; + dcache.wbb->rtp_stats = dcache.wbb->stats_t; + } + else { + dcache.missb->stats_t.readAc.access = dcache.caches->stats_t.readAc.miss; + dcache.missb->stats_t.writeAc.access = dcache.caches->stats_t.readAc.miss; + dcache.missb->rtp_stats = dcache.missb->stats_t; + + dcache.ifb->stats_t.readAc.access = dcache.caches->stats_t.readAc.miss; + dcache.ifb->stats_t.writeAc.access = dcache.caches->stats_t.readAc.miss; + dcache.ifb->rtp_stats = dcache.ifb->stats_t; + + dcache.prefetchb->stats_t.readAc.access = + dcache.caches->stats_t.readAc.miss; + dcache.prefetchb->stats_t.writeAc.access = + dcache.caches->stats_t.readAc.miss; + dcache.prefetchb->rtp_stats = dcache.prefetchb->stats_t; + } + + LSQ->stats_t.readAc.access = (XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions) * + 2; // flush overhead considered + LSQ->stats_t.writeAc.access = (XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions) * + 2; + LSQ->rtp_stats = LSQ->stats_t; + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->stats_t.readAc.access = XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions; + LoadQ->stats_t.writeAc.access = XML->sys.core[ithCore].load_instructions + + XML->sys.core[ithCore].store_instructions; + LoadQ->rtp_stats = LoadQ->stats_t; + } + } + + dcache.power_t.reset(); + LSQ->power_t.reset(); + dcache.power_t.readOp.dynamic += + (dcache.caches->stats_t.readAc.hit * + dcache.caches->local_result.power.readOp.dynamic + + dcache.caches->stats_t.readAc.miss * + dcache.caches->local_result.power.readOp + .dynamic + // assuming D cache is in the fast model which read + // tag and data together + dcache.caches->stats_t.writeAc.miss * + dcache.caches->local_result.tag_array2->power.readOp.dynamic + + dcache.caches->stats_t.writeAc.access * + dcache.caches->local_result.power.writeOp.dynamic); + + if (cache_p == Write_back) { // write miss will generate a write later + dcache.power_t.readOp.dynamic += + dcache.caches->stats_t.writeAc.miss * + dcache.caches->local_result.power.writeOp.dynamic; + } + + dcache.power_t.readOp.dynamic += + dcache.missb->stats_t.readAc.access * + dcache.missb->local_result.power.searchOp.dynamic + + dcache.missb->stats_t.writeAc.access * + dcache.missb->local_result.power.writeOp + .dynamic; // each access to missb involves a CAM and a write + dcache.power_t.readOp.dynamic += + dcache.ifb->stats_t.readAc.access * + dcache.ifb->local_result.power.searchOp.dynamic + + dcache.ifb->stats_t.writeAc.access * + dcache.ifb->local_result.power.writeOp.dynamic; + dcache.power_t.readOp.dynamic += + dcache.prefetchb->stats_t.readAc.access * + dcache.prefetchb->local_result.power.searchOp.dynamic + + dcache.prefetchb->stats_t.writeAc.access * + dcache.prefetchb->local_result.power.writeOp.dynamic; + if (cache_p == Write_back) { + dcache.power_t.readOp.dynamic += + dcache.wbb->stats_t.readAc.access * + dcache.wbb->local_result.power.searchOp.dynamic + + dcache.wbb->stats_t.writeAc.access * + dcache.wbb->local_result.power.writeOp.dynamic; + } + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->power_t.reset(); + LoadQ->power_t.readOp.dynamic += + LoadQ->stats_t.readAc.access * + (LoadQ->local_result.power.searchOp.dynamic + + LoadQ->local_result.power.readOp.dynamic) + + LoadQ->stats_t.writeAc.access * + LoadQ->local_result.power.writeOp.dynamic; // every memory access + // invloves at least two + // operations on LoadQ + + LSQ->power_t.readOp.dynamic += + LSQ->stats_t.readAc.access * (LSQ->local_result.power.searchOp.dynamic + + LSQ->local_result.power.readOp.dynamic) + + LSQ->stats_t.writeAc.access * + LSQ->local_result.power.writeOp.dynamic; // every memory access + // invloves at least two + // operations on LSQ + } + else { + LSQ->power_t.readOp.dynamic += + LSQ->stats_t.readAc.access * (LSQ->local_result.power.searchOp.dynamic + + LSQ->local_result.power.readOp.dynamic) + + LSQ->stats_t.writeAc.access * + LSQ->local_result.power.writeOp.dynamic; // every memory access + // invloves at least two + // operations on LSQ + } + + if (is_tdp) { + // dcache.power = dcache.power_t + + // (dcache.caches->local_result.power)*pppm_lkg + + // (dcache.missb->local_result.power + + // dcache.ifb->local_result.power + + // dcache.prefetchb->local_result.power + + // dcache.wbb->local_result.power)*pppm_Isub; + dcache.power = dcache.power_t + (dcache.caches->local_result.power + + dcache.missb->local_result.power + + dcache.ifb->local_result.power + + dcache.prefetchb->local_result.power) * + pppm_lkg; + if (cache_p == Write_back) { + dcache.power = dcache.power + dcache.wbb->local_result.power * pppm_lkg; + } + + LSQ->power = LSQ->power_t + LSQ->local_result.power * pppm_lkg; + power = power + dcache.power + LSQ->power; + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->power = LoadQ->power_t + LoadQ->local_result.power * pppm_lkg; + power = power + LoadQ->power; + } + } + else { + // dcache.rt_power = dcache.power_t + + // (dcache.caches->local_result.power + + // dcache.missb->local_result.power + + // dcache.ifb->local_result.power + + // dcache.prefetchb->local_result.power + + // dcache.wbb->local_result.power)*pppm_lkg; + dcache.rt_power = dcache.power_t + (dcache.caches->local_result.power + + dcache.missb->local_result.power + + dcache.ifb->local_result.power + + dcache.prefetchb->local_result.power) * + pppm_lkg; + + if (cache_p == Write_back) { + dcache.rt_power = + dcache.rt_power + dcache.wbb->local_result.power * pppm_lkg; + } + + LSQ->rt_power = LSQ->power_t + LSQ->local_result.power * pppm_lkg; + rt_power = rt_power + dcache.rt_power + LSQ->rt_power; + + if ((coredynp.core_ty == OOO) && + (XML->sys.core[ithCore].load_buffer_size > 0)) { + LoadQ->rt_power = LoadQ->power_t + LoadQ->local_result.power * pppm_lkg; + rt_power = rt_power + LoadQ->rt_power; + } + } +} + +void LoadStoreU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Data Cache:" << endl; + cout << indent_str_next << "Area = " << dcache.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << dcache.power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? dcache.power.readOp.longer_channel_leakage + : dcache.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? dcache.power.readOp.power_gated_with_long_channel_leakage + : dcache.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << dcache.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << dcache.rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (coredynp.core_ty == Inorder) { + cout << indent_str << "Load/Store Queue:" << endl; + cout << indent_str_next << "Area = " << LSQ->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << LSQ->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? LSQ->power.readOp.longer_channel_leakage + : LSQ->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? LSQ->power.readOp.power_gated_with_long_channel_leakage + : LSQ->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << LSQ->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << LSQ->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + else + + { + if (XML->sys.core[ithCore].load_buffer_size > 0) { + cout << indent_str << "LoadQ:" << endl; + cout << indent_str_next << "Area = " << LoadQ->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << LoadQ->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? LoadQ->power.readOp.longer_channel_leakage + : LoadQ->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? LoadQ->power.readOp + .power_gated_with_long_channel_leakage + : LoadQ->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << LoadQ->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << LoadQ->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + cout << indent_str << "StoreQ:" << endl; + cout << indent_str_next << "Area = " << LSQ->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << LSQ->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? LSQ->power.readOp.longer_channel_leakage + : LSQ->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? LSQ->power.readOp.power_gated_with_long_channel_leakage + : LSQ->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << LSQ->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << LSQ->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << indent_str_next << "Data Cache Peak Dynamic = " + << dcache.rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Data Cache Subthreshold Leakage = " + << dcache.rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Data Cache Gate Leakage = " + << dcache.rt_power.readOp.gate_leakage << " W" << endl; + if (coredynp.core_ty == Inorder) { + cout << indent_str_next << "Load/Store Queue Peak Dynamic = " + << LSQ->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Load/Store Queue Subthreshold Leakage = " + << LSQ->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Load/Store Queue Gate Leakage = " + << LSQ->rt_power.readOp.gate_leakage << " W" << endl; + } + else { + cout << indent_str_next << "LoadQ Peak Dynamic = " + << LoadQ->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "LoadQ Subthreshold Leakage = " + << LoadQ->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "LoadQ Gate Leakage = " << LoadQ->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "StoreQ Peak Dynamic = " + << LSQ->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "StoreQ Subthreshold Leakage = " << LSQ->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "StoreQ Gate Leakage = " << LSQ->rt_power.readOp.gate_leakage + << " W" << endl; + } + } +} + +void MemManU::computeEnergy(bool is_tdp) { + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + itlb->stats_t.readAc.access = + itlb->l_ip.num_search_ports * coredynp.IFU_duty_cycle; + itlb->stats_t.readAc.miss = 0; + itlb->stats_t.readAc.hit = + itlb->stats_t.readAc.access - itlb->stats_t.readAc.miss; + itlb->tdp_stats = itlb->stats_t; + + dtlb->stats_t.readAc.access = + dtlb->l_ip.num_search_ports * coredynp.LSU_duty_cycle; + dtlb->stats_t.readAc.miss = 0; + dtlb->stats_t.readAc.hit = + dtlb->stats_t.readAc.access - dtlb->stats_t.readAc.miss; + dtlb->tdp_stats = dtlb->stats_t; + } + else { + // init stats for Runtime Dynamic (RTP) + itlb->stats_t.readAc.access = XML->sys.core[ithCore].itlb.total_accesses; + itlb->stats_t.readAc.miss = XML->sys.core[ithCore].itlb.total_misses; + itlb->stats_t.readAc.hit = + itlb->stats_t.readAc.access - itlb->stats_t.readAc.miss; + itlb->rtp_stats = itlb->stats_t; + + dtlb->stats_t.readAc.access = XML->sys.core[ithCore].dtlb.total_accesses; + dtlb->stats_t.readAc.miss = XML->sys.core[ithCore].dtlb.total_misses; + dtlb->stats_t.readAc.hit = + dtlb->stats_t.readAc.access - dtlb->stats_t.readAc.miss; + dtlb->rtp_stats = dtlb->stats_t; + } + + itlb->power_t.reset(); + dtlb->power_t.reset(); + itlb->power_t.readOp.dynamic += + itlb->stats_t.readAc.access * + itlb->local_result.power.searchOp.dynamic // FA spent most power in + // tag, so use total access + // not hits + + itlb->stats_t.readAc.miss * itlb->local_result.power.writeOp.dynamic; + dtlb->power_t.readOp.dynamic += + dtlb->stats_t.readAc.access * + dtlb->local_result.power.searchOp.dynamic // FA spent most power in + // tag, so use total access + // not hits + + dtlb->stats_t.readAc.miss * dtlb->local_result.power.writeOp.dynamic; + + if (is_tdp) { + itlb->power = itlb->power_t + itlb->local_result.power * pppm_lkg; + dtlb->power = dtlb->power_t + dtlb->local_result.power * pppm_lkg; + power = power + itlb->power + dtlb->power; + } + else { + itlb->rt_power = itlb->power_t + itlb->local_result.power * pppm_lkg; + dtlb->rt_power = dtlb->power_t + dtlb->local_result.power * pppm_lkg; + rt_power = rt_power + itlb->rt_power + dtlb->rt_power; + } +} + +void MemManU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Itlb:" << endl; + cout << indent_str_next << "Area = " << itlb->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << itlb->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? itlb->power.readOp.longer_channel_leakage + : itlb->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? itlb->power.readOp.power_gated_with_long_channel_leakage + : itlb->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << itlb->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << itlb->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + cout << indent_str << "Dtlb:" << endl; + cout << indent_str_next << "Area = " << dtlb->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << dtlb->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? dtlb->power.readOp.longer_channel_leakage + : dtlb->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? dtlb->power.readOp.power_gated_with_long_channel_leakage + : dtlb->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << dtlb->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << dtlb->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + else { + cout << indent_str_next << "Itlb Peak Dynamic = " + << itlb->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "Itlb Subthreshold Leakage = " << itlb->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Itlb Gate Leakage = " << itlb->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Dtlb Peak Dynamic = " + << dtlb->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next + << "Dtlb Subthreshold Leakage = " << dtlb->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Dtlb Gate Leakage = " << dtlb->rt_power.readOp.gate_leakage + << " W" << endl; + } +} + +void RegFU::computeEnergy(bool is_tdp) { + /* + * Architecture RF and physical RF cannot be present at the same time. + * Therefore, the RF stats can only refer to either ARF or PRF; + * And the same stats can be used for both. + */ + if (!exist) + return; + if (is_tdp) { + // init stats for Peak + IRF->stats_t.readAc.access = + coredynp.issueW * 2 * + (coredynp.ALU_duty_cycle * 1.1 + + (coredynp.num_muls > 0 ? coredynp.MUL_duty_cycle : 0)) * + coredynp.num_pipelines; + IRF->stats_t.writeAc.access = + coredynp.issueW * + (coredynp.ALU_duty_cycle * 1.1 + + (coredynp.num_muls > 0 ? coredynp.MUL_duty_cycle : 0)) * + coredynp.num_pipelines; + // Rule of Thumb: about 10% RF related instructions do not need to access + // ALUs + IRF->tdp_stats = IRF->stats_t; + + FRF->stats_t.readAc.access = FRF->l_ip.num_rd_ports * + coredynp.FPU_duty_cycle * 1.05 * + coredynp.num_fp_pipelines; + FRF->stats_t.writeAc.access = FRF->l_ip.num_wr_ports * + coredynp.FPU_duty_cycle * 1.05 * + coredynp.num_fp_pipelines; + FRF->tdp_stats = FRF->stats_t; + if (coredynp.regWindowing) { + RFWIN->stats_t.readAc.access = 0; // 0.5*RFWIN->l_ip.num_rw_ports; + RFWIN->stats_t.writeAc.access = 0; // 0.5*RFWIN->l_ip.num_rw_ports; + RFWIN->tdp_stats = RFWIN->stats_t; + } + } + else { + // init stats for Runtime Dynamic (RTP) + IRF->stats_t.readAc.access = + XML->sys.core[ithCore] + .int_regfile_reads; // TODO: no diff on archi and phy + IRF->stats_t.writeAc.access = XML->sys.core[ithCore].int_regfile_writes; + IRF->rtp_stats = IRF->stats_t; + + FRF->stats_t.readAc.access = XML->sys.core[ithCore].float_regfile_reads; + FRF->stats_t.writeAc.access = XML->sys.core[ithCore].float_regfile_writes; + FRF->rtp_stats = FRF->stats_t; + if (coredynp.regWindowing) { + RFWIN->stats_t.readAc.access = XML->sys.core[ithCore].function_calls * 16; + RFWIN->stats_t.writeAc.access = + XML->sys.core[ithCore].function_calls * 16; + RFWIN->rtp_stats = RFWIN->stats_t; + + IRF->stats_t.readAc.access = XML->sys.core[ithCore].int_regfile_reads + + XML->sys.core[ithCore].function_calls * 16; + IRF->stats_t.writeAc.access = XML->sys.core[ithCore].int_regfile_writes + + XML->sys.core[ithCore].function_calls * 16; + IRF->rtp_stats = IRF->stats_t; + + FRF->stats_t.readAc.access = XML->sys.core[ithCore].float_regfile_reads + + XML->sys.core[ithCore].function_calls * 16; + ; + FRF->stats_t.writeAc.access = + XML->sys.core[ithCore].float_regfile_writes + + XML->sys.core[ithCore].function_calls * 16; + ; + FRF->rtp_stats = FRF->stats_t; + } + } + IRF->power_t.reset(); + FRF->power_t.reset(); + IRF->power_t.readOp.dynamic += + (IRF->stats_t.readAc.access * IRF->local_result.power.readOp.dynamic + + IRF->stats_t.writeAc.access * IRF->local_result.power.writeOp.dynamic); + FRF->power_t.readOp.dynamic += + (FRF->stats_t.readAc.access * FRF->local_result.power.readOp.dynamic + + FRF->stats_t.writeAc.access * FRF->local_result.power.writeOp.dynamic); + if (coredynp.regWindowing) { + RFWIN->power_t.reset(); + RFWIN->power_t.readOp.dynamic += + (RFWIN->stats_t.readAc.access * + RFWIN->local_result.power.readOp.dynamic + + RFWIN->stats_t.writeAc.access * + RFWIN->local_result.power.writeOp.dynamic); + } + + if (is_tdp) { + IRF->power = IRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (IRF->local_result.power * coredynp.pppm_lkg_multhread) + : IRF->local_result.power); + FRF->power = FRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (FRF->local_result.power * coredynp.pppm_lkg_multhread) + : FRF->local_result.power); + power = power + (IRF->power + FRF->power); + if (coredynp.regWindowing) { + RFWIN->power = RFWIN->power_t + RFWIN->local_result.power * pppm_lkg; + power = power + RFWIN->power; + } + } + else { + IRF->rt_power = + IRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (IRF->local_result.power * coredynp.pppm_lkg_multhread) + : IRF->local_result.power); + FRF->rt_power = + FRF->power_t + + ((coredynp.scheu_ty == ReservationStation) + ? (FRF->local_result.power * coredynp.pppm_lkg_multhread) + : FRF->local_result.power); + rt_power = rt_power + (IRF->power_t + FRF->power_t); + if (coredynp.regWindowing) { + RFWIN->rt_power = RFWIN->power_t + RFWIN->local_result.power * pppm_lkg; + rt_power = rt_power + RFWIN->rt_power; + } + } +} + +void RegFU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Integer RF:" << endl; + cout << indent_str_next << "Area = " << IRF->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << IRF->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? IRF->power.readOp.longer_channel_leakage + : IRF->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? IRF->power.readOp.power_gated_with_long_channel_leakage + : IRF->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << IRF->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << IRF->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + cout << indent_str << "Floating Point RF:" << endl; + cout << indent_str_next << "Area = " << FRF->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << FRF->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? FRF->power.readOp.longer_channel_leakage + : FRF->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? FRF->power.readOp.power_gated_with_long_channel_leakage + : FRF->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << FRF->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << FRF->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + if (coredynp.regWindowing) { + cout << indent_str << "Register Windows:" << endl; + cout << indent_str_next << "Area = " << RFWIN->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << RFWIN->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? RFWIN->power.readOp.longer_channel_leakage + : RFWIN->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? RFWIN->power.readOp.power_gated_with_long_channel_leakage + : RFWIN->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << RFWIN->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << RFWIN->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << indent_str_next << "Integer RF Peak Dynamic = " + << IRF->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Integer RF Subthreshold Leakage = " + << IRF->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next + << "Integer RF Gate Leakage = " << IRF->rt_power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Floating Point RF Peak Dynamic = " + << FRF->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Floating Point RF Subthreshold Leakage = " + << FRF->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Floating Point RF Gate Leakage = " + << FRF->rt_power.readOp.gate_leakage << " W" << endl; + if (coredynp.regWindowing) { + cout << indent_str_next << "Register Windows Peak Dynamic = " + << RFWIN->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Register Windows Subthreshold Leakage = " + << RFWIN->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Register Windows Gate Leakage = " + << RFWIN->rt_power.readOp.gate_leakage << " W" << endl; + } + } +} + +void EXECU::computeEnergy(bool is_tdp) { + if (!exist) + return; + double pppm_t[4] = {1, 1, 1, 1}; + // rfu->power.reset(); + // rfu->rt_power.reset(); + // scheu->power.reset(); + // scheu->rt_power.reset(); + // exeu->power.reset(); + // exeu->rt_power.reset(); + + rfu->computeEnergy(is_tdp); + scheu->computeEnergy(is_tdp); + exeu->computeEnergy(is_tdp); + if (coredynp.num_fpus > 0) { + fp_u->computeEnergy(is_tdp); + } + if (coredynp.num_muls > 0) { + mul->computeEnergy(is_tdp); + } + + if (is_tdp) { + set_pppm(pppm_t, 2 * coredynp.ALU_cdb_duty_cycle, 2, 2, + 2 * coredynp.ALU_cdb_duty_cycle); // 2 means two source operands + // needs to be passed for each + // int instruction. + bypass.power = bypass.power + intTagBypass->power * pppm_t + + int_bypass->power * pppm_t; + if (coredynp.num_muls > 0) { + set_pppm(pppm_t, 2 * coredynp.MUL_cdb_duty_cycle, 2, 2, + 2 * coredynp.MUL_cdb_duty_cycle); // 2 means two source operands + // needs to be passed for each + // int instruction. + bypass.power = bypass.power + intTag_mul_Bypass->power * pppm_t + + int_mul_bypass->power * pppm_t; + power = power + mul->power; + } + if (coredynp.num_fpus > 0) { + set_pppm(pppm_t, 3 * coredynp.FPU_cdb_duty_cycle, 3, 3, + 3 * coredynp.FPU_cdb_duty_cycle); // 3 means three source + // operands needs to be passed + // for each fp instruction. + bypass.power = bypass.power + fp_bypass->power * pppm_t + + fpTagBypass->power * pppm_t; + power = power + fp_u->power; + } + + power = power + rfu->power + exeu->power + bypass.power + scheu->power; + } + else { + set_pppm(pppm_t, XML->sys.core[ithCore].cdb_alu_accesses, 2, 2, + XML->sys.core[ithCore].cdb_alu_accesses); + bypass.rt_power = bypass.rt_power + intTagBypass->power * pppm_t; + bypass.rt_power = bypass.rt_power + int_bypass->power * pppm_t; + + if (coredynp.num_muls > 0) { + set_pppm(pppm_t, XML->sys.core[ithCore].cdb_mul_accesses, 2, 2, + XML->sys.core[ithCore].cdb_mul_accesses); // 2 means two source + // operands needs to + // be passed for each + // int instruction. + bypass.rt_power = bypass.rt_power + intTag_mul_Bypass->power * pppm_t + + int_mul_bypass->power * pppm_t; + rt_power = rt_power + mul->rt_power; + } + + if (coredynp.num_fpus > 0) { + set_pppm(pppm_t, XML->sys.core[ithCore].cdb_fpu_accesses, 3, 3, + XML->sys.core[ithCore].cdb_fpu_accesses); + bypass.rt_power = bypass.rt_power + fp_bypass->power * pppm_t; + bypass.rt_power = bypass.rt_power + fpTagBypass->power * pppm_t; + rt_power = rt_power + fp_u->rt_power; + } + rt_power = rt_power + rfu->rt_power + exeu->rt_power + bypass.rt_power + + scheu->rt_power; + } +} + +void EXECU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + if (!exist) + return; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + // cout << indent_str_next << "Results Broadcast Bus Area = " << + // bypass->area.get_area() *1e-6 << " mm^2" << endl; + if (is_tdp) { + cout << indent_str << "Register Files:" << endl; + cout << indent_str_next << "Area = " << rfu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << rfu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? rfu->power.readOp.longer_channel_leakage + : rfu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? rfu->power.readOp.power_gated_with_long_channel_leakage + : rfu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << rfu->power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rfu->rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + if (plevel > 3) { + rfu->displayEnergy(indent + 4, is_tdp); + } + cout << indent_str << "Instruction Scheduler:" << endl; + cout << indent_str_next << "Area = " << scheu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << scheu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? scheu->power.readOp.longer_channel_leakage + : scheu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? scheu->power.readOp.power_gated_with_long_channel_leakage + : scheu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << scheu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << scheu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 3) { + scheu->displayEnergy(indent + 4, is_tdp); + } + exeu->displayEnergy(indent, is_tdp); + if (coredynp.num_fpus > 0) { + fp_u->displayEnergy(indent, is_tdp); + } + if (coredynp.num_muls > 0) { + mul->displayEnergy(indent, is_tdp); + } + cout << indent_str << "Results Broadcast Bus:" << endl; + cout << indent_str_next + << "Area Overhead = " << bypass.area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << bypass.power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? bypass.power.readOp.longer_channel_leakage + : bypass.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? bypass.power.readOp.power_gated_with_long_channel_leakage + : bypass.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << bypass.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << bypass.rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + } + else { + cout << indent_str_next << "Register Files Peak Dynamic = " + << rfu->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Register Files Subthreshold Leakage = " + << rfu->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Register Files Gate Leakage = " + << rfu->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Instruction Sheduler Peak Dynamic = " + << scheu->rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Instruction Sheduler Subthreshold Leakage = " + << scheu->rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Instruction Sheduler Gate Leakage = " + << scheu->rt_power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Results Broadcast Bus Peak Dynamic = " + << bypass.rt_power.readOp.dynamic * clockRate << " W" << endl; + cout << indent_str_next << "Results Broadcast Bus Subthreshold Leakage = " + << bypass.rt_power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Results Broadcast Bus Gate Leakage = " + << bypass.rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void Core::computeEnergy(bool is_tdp) { + /* + * When computing TDP, power = energy_per_cycle (the value computed in this + * function) * clock_rate (in the display_energy function) When computing + * dyn_power; power = total energy (the value computed in this function) / + * Total execution time (cycle count / clock rate) + */ + // power_point_product_masks + double pppm_t[4] = {1, 1, 1, 1}; + double rtp_pipeline_coe; + double num_units = 4.0; + if (is_tdp) { + ifu->computeEnergy(is_tdp); + lsu->computeEnergy(is_tdp); + mmu->computeEnergy(is_tdp); + exu->computeEnergy(is_tdp); + + if (coredynp.core_ty == OOO) { + num_units = 5.0; + rnu->computeEnergy(is_tdp); + set_pppm( + pppm_t, coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / + num_units); // User need to feed a duty cycle to improve accuracy + if (rnu->exist) { + rnu->power = rnu->power + corepipe->power * pppm_t; + power = power + rnu->power; + } + } + + if (ifu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * coredynp.IFU_duty_cycle, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + // cout << "IFU = " << + // ifu->power.readOp.dynamic*clockRate << " W" << endl; + ifu->power = ifu->power + corepipe->power * pppm_t; + // cout << "IFU = " << + // ifu->power.readOp.dynamic*clockRate << " W" << endl; + // cout << "1/4 pipe = " << + // corepipe->power.readOp.dynamic*clockRate/num_units << " W" << endl; + power = power + ifu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + if (lsu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * coredynp.LSU_duty_cycle, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + lsu->power = lsu->power + corepipe->power * pppm_t; + // cout << "LSU = " << + // lsu->power.readOp.dynamic*clockRate << " W" << endl; + power = power + lsu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + if (exu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * coredynp.ALU_duty_cycle, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + exu->power = exu->power + corepipe->power * pppm_t; + // cout << "EXE = " << + // exu->power.readOp.dynamic*clockRate << " W" << endl; + power = power + exu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + if (mmu->exist) { + set_pppm(pppm_t, + coredynp.num_pipelines / num_units * + (0.5 + 0.5 * coredynp.LSU_duty_cycle), + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + mmu->power = mmu->power + corepipe->power * pppm_t; + // cout << "MMU = " << + // mmu->power.readOp.dynamic*clockRate << " W" << endl; + power = power + mmu->power; + // cout << "core = " << + // power.readOp.dynamic*clockRate << " W" << endl; + } + + power = power + undiffCore->power; + + if (XML->sys.Private_L2) { + l2cache->computeEnergy(is_tdp); + set_pppm(pppm_t, l2cache->cachep.clockRate / clockRate, 1, 1, 1); + // l2cache->power = l2cache->power*pppm_t; + power = power + l2cache->power * pppm_t; + } + } + else { + ifu->computeEnergy(is_tdp); + lsu->computeEnergy(is_tdp); + mmu->computeEnergy(is_tdp); + exu->computeEnergy(is_tdp); + + if (coredynp.core_ty == OOO) { + num_units = 5.0; + rnu->computeEnergy(is_tdp); + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + XML->sys.total_cycles * XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + if (rnu->exist) { + rnu->rt_power = rnu->rt_power + corepipe->power * pppm_t; + + rt_power = rt_power + rnu->rt_power; + } + } + else { + num_units = 4.0; + } + + if (ifu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.IFU_duty_cycle * XML->sys.total_cycles * + XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.IFU_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + ifu->rt_power = ifu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + ifu->rt_power; + } + if (lsu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.LSU_duty_cycle * XML->sys.total_cycles * + XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.LSU_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + + lsu->rt_power = lsu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + lsu->rt_power; + } + if (exu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.ALU_duty_cycle * XML->sys.total_cycles * + XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + coredynp.ALU_duty_cycle * coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + exu->rt_power = exu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + exu->rt_power; + } + if (mmu->exist) { + if (XML->sys.homogeneous_cores == 1) { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + (0.5 + 0.5 * coredynp.LSU_duty_cycle) * + XML->sys.total_cycles * XML->sys.number_of_cores; + } + else { + rtp_pipeline_coe = coredynp.pipeline_duty_cycle * + (0.5 + 0.5 * coredynp.LSU_duty_cycle) * + coredynp.total_cycles; + } + set_pppm(pppm_t, coredynp.num_pipelines * rtp_pipeline_coe / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units, + coredynp.num_pipelines / num_units); + mmu->rt_power = mmu->rt_power + corepipe->power * pppm_t; + rt_power = rt_power + mmu->rt_power; + } + + rt_power = rt_power + undiffCore->power; + // cout << "EXE = " << exu->power.readOp.dynamic*clockRate << " W" + //<< endl; + if (XML->sys.Private_L2) { + l2cache->computeEnergy(is_tdp); + // set_pppm(pppm_t,1/l2cache->cachep.executionTime, 1,1,1); + // l2cache->rt_power = l2cache->rt_power*pppm_t; + rt_power = rt_power + l2cache->rt_power; + } + } +} + +void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "Core:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + if (ifu->exist) { + cout << indent_str << "Instruction Fetch Unit:" << endl; + cout << indent_str_next << "Area = " << ifu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << ifu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? ifu->power.readOp.longer_channel_leakage + : ifu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? ifu->power.readOp.power_gated_with_long_channel_leakage + : ifu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << ifu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << ifu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + ifu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + if (coredynp.core_ty == OOO) { + if (rnu->exist) { + cout << indent_str << "Renaming Unit:" << endl; + cout << indent_str_next << "Area = " << rnu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << rnu->power.readOp.dynamic * clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? rnu->power.readOp.longer_channel_leakage + : rnu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? rnu->power.readOp.power_gated_with_long_channel_leakage + : rnu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << rnu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << rnu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + rnu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + } + if (lsu->exist) { + cout << indent_str << "Load Store Unit:" << endl; + cout << indent_str_next << "Area = " << lsu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << lsu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? lsu->power.readOp.longer_channel_leakage + : lsu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? lsu->power.readOp.power_gated_with_long_channel_leakage + : lsu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << lsu->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << lsu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + lsu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + if (mmu->exist) { + cout << indent_str << "Memory Management Unit:" << endl; + cout << indent_str_next << "Area = " << mmu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << mmu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? mmu->power.readOp.longer_channel_leakage + : mmu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? mmu->power.readOp.power_gated_with_long_channel_leakage + : mmu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << mmu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + mmu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + if (exu->exist) { + cout << indent_str << "Execution Unit:" << endl; + cout << indent_str_next << "Area = " << exu->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << exu->power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? exu->power.readOp.longer_channel_leakage + : exu->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? exu->power.readOp.power_gated_with_long_channel_leakage + : exu->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << exu->rt_power.readOp.dynamic / executionTime << " W" << endl; + cout << endl; + if (plevel > 2) { + exu->displayEnergy(indent + 4, plevel, is_tdp); + } + } + // if (plevel >2) + // { + // if (undiffCore->exist) + // { + // cout << indent_str << "Undifferentiated Core" << + // endl; cout << indent_str_next << "Area = " << + // undiffCore->area.get_area()*1e-6<< " mm^2" << endl; + // cout << indent_str_next << "Peak Dynamic = " << + // undiffCore->power.readOp.dynamic*clockRate << " W" << endl; + //// cout << indent_str_next << "Subthreshold + /// Leakage + ///= + ///" + ///<< undiffCore->power.readOp.leakage <<" W" << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= + //" + // << + //(long_channel? + // undiffCore->power.readOp.longer_channel_leakage:undiffCore->power.readOp.leakage) + //<< " W" << endl; + // cout << indent_str_next << "Gate Leakage = " << + // undiffCore->power.readOp.gate_leakage << " W" << endl; + // // cout << indent_str_next << + //"Runtime Dynamic + //= + //" + //<< undiffCore->rt_power.readOp.dynamic/executionTime << " W" << endl; + // cout <sys.Private_L2) { + l2cache->displayEnergy(4, is_tdp); + } + } + else { + // cout << indent_str_next << "Instruction Fetch Unit Peak + // Dynamic + //= + //" + //<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Subthreshold + // Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Gate + // Leakage + //= + //" + //<< ifu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Peak Dynamic = " << + // lsu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Load Store Unit Subthreshold Leakage = " << + // lsu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Gate Leakage = " << + // lsu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Peak Dynamic = " << + // mmu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Memory Management Unit Subthreshold Leakage = " + // << mmu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Gate Leakage = " << + // mmu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Peak Dynamic = " << + // exu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Execution Unit Subthreshold Leakage = " << + // exu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Gate Leakage = " << + // exu->rt_power.readOp.gate_leakage << " W" << endl; + } +} +InstFetchU ::~InstFetchU() { + if (!exist) + return; + if (IB) { + delete IB; + IB = 0; + } + if (ID_inst) { + delete ID_inst; + ID_inst = 0; + } + if (ID_operand) { + delete ID_operand; + ID_operand = 0; + } + if (ID_misc) { + delete ID_misc; + ID_misc = 0; + } + if (coredynp.predictionW > 0) { + if (BTB) { + delete BTB; + BTB = 0; + } + if (BPT) { + delete BPT; + BPT = 0; + } + } +} + +BranchPredictor ::~BranchPredictor() { + if (!exist) + return; + if (globalBPT) { + delete globalBPT; + globalBPT = 0; + } + if (localBPT) { + delete localBPT; + localBPT = 0; + } + if (L1_localBPT) { + delete L1_localBPT; + L1_localBPT = 0; + } + if (L2_localBPT) { + delete L2_localBPT; + L2_localBPT = 0; + } + if (chooser) { + delete chooser; + chooser = 0; + } + if (RAS) { + delete RAS; + RAS = 0; + } +} + +RENAMINGU ::~RENAMINGU() { + if (!exist) + return; + if (iFRAT) { + delete iFRAT; + iFRAT = 0; + } + if (iRRAT) { + delete iRRAT; + iRRAT = 0; + } + if (iFRAT) { + delete iFRAT; + iFRAT = 0; + } + if (ifreeL) { + delete ifreeL; + ifreeL = 0; + } + if (idcl) { + delete idcl; + idcl = 0; + } + if (fFRAT) { + delete fFRAT; + fFRAT = 0; + } + if (fRRAT) { + delete fRRAT; + fRRAT = 0; + } + if (fdcl) { + delete fdcl; + fdcl = 0; + } + if (ffreeL) { + delete ffreeL; + ffreeL = 0; + } + if (RAHT) { + delete RAHT; + RAHT = 0; + } +} + +LoadStoreU ::~LoadStoreU() { + if (!exist) + return; + if (LSQ) { + delete LSQ; + LSQ = 0; + } + if (LoadQ) { + delete LoadQ; + LoadQ = 0; + } +} + +MemManU ::~MemManU() { + if (!exist) + return; + if (itlb) { + delete itlb; + itlb = 0; + } + if (dtlb) { + delete dtlb; + dtlb = 0; + } +} + +RegFU ::~RegFU() { + if (!exist) + return; + if (IRF) { + delete IRF; + IRF = 0; + } + if (FRF) { + delete FRF; + FRF = 0; + } + if (RFWIN) { + delete RFWIN; + RFWIN = 0; + } +} + +SchedulerU ::~SchedulerU() { + if (!exist) + return; + if (int_inst_window) { + delete int_inst_window; + int_inst_window = 0; + } + if (fp_inst_window) { + delete fp_inst_window; + fp_inst_window = 0; + } + if (ROB) { + delete ROB; + ROB = 0; + } + if (instruction_selection) { + delete instruction_selection; + instruction_selection = 0; + } +} + +EXECU ::~EXECU() { + if (!exist) + return; + if (int_bypass) { + delete int_bypass; + int_bypass = 0; + } + if (intTagBypass) { + delete intTagBypass; + intTagBypass = 0; + } + if (int_mul_bypass) { + delete int_mul_bypass; + int_mul_bypass = 0; + } + if (intTag_mul_Bypass) { + delete intTag_mul_Bypass; + intTag_mul_Bypass = 0; + } + if (fp_bypass) { + delete fp_bypass; + fp_bypass = 0; + } + if (fpTagBypass) { + delete fpTagBypass; + fpTagBypass = 0; + } + if (fp_u) { + delete fp_u; + fp_u = 0; + } + if (exeu) { + delete exeu; + exeu = 0; + } + if (mul) { + delete mul; + mul = 0; + } + if (rfu) { + delete rfu; + rfu = 0; + } + if (scheu) { + delete scheu; + scheu = 0; + } +} + +Core ::~Core() { + if (ifu) { + delete ifu; + ifu = 0; + } + if (lsu) { + delete lsu; + lsu = 0; + } + if (rnu) { + delete rnu; + rnu = 0; + } + if (mmu) { + delete mmu; + mmu = 0; + } + if (exu) { + delete exu; + exu = 0; + } + if (corepipe) { + delete corepipe; + corepipe = 0; + } + if (undiffCore) { + delete undiffCore; + undiffCore = 0; + } + if (l2cache) { + delete l2cache; + l2cache = 0; + } +} + +void Core::set_core_param() { + coredynp.opt_local = XML->sys.core[ithCore].opt_local; + coredynp.x86 = XML->sys.core[ithCore].x86; + coredynp.Embedded = XML->sys.Embedded; + coredynp.core_ty = (enum Core_type)XML->sys.core[ithCore].machine_type; + coredynp.rm_ty = (enum Renaming_type)XML->sys.core[ithCore].rename_scheme; + coredynp.fetchW = XML->sys.core[ithCore].fetch_width; + coredynp.decodeW = XML->sys.core[ithCore].decode_width; + coredynp.issueW = XML->sys.core[ithCore].issue_width; + coredynp.peak_issueW = XML->sys.core[ithCore].peak_issue_width; + coredynp.commitW = XML->sys.core[ithCore].commit_width; + coredynp.peak_commitW = XML->sys.core[ithCore].peak_issue_width; + coredynp.predictionW = XML->sys.core[ithCore].prediction_width; + coredynp.fp_issueW = XML->sys.core[ithCore].fp_issue_width; + coredynp.fp_decodeW = XML->sys.core[ithCore].fp_issue_width; + coredynp.num_alus = XML->sys.core[ithCore].ALU_per_core; + coredynp.num_fpus = XML->sys.core[ithCore].FPU_per_core; + coredynp.num_muls = XML->sys.core[ithCore].MUL_per_core; + coredynp.vdd = XML->sys.core[ithCore].vdd; + coredynp.power_gating_vcc = XML->sys.core[ithCore].power_gating_vcc; + + coredynp.num_hthreads = XML->sys.core[ithCore].number_hardware_threads; + coredynp.multithreaded = coredynp.num_hthreads > 1 ? true : false; + coredynp.hthread_width = + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))); + coredynp.instruction_length = XML->sys.core[ithCore].instruction_length; + coredynp.pc_width = XML->sys.virtual_address_width; + + coredynp.opcode_length = XML->sys.core[ithCore].opcode_width; + coredynp.micro_opcode_length = XML->sys.core[ithCore].micro_opcode_width; + coredynp.num_pipelines = XML->sys.core[ithCore].pipelines_per_core[0]; + coredynp.pipeline_stages = XML->sys.core[ithCore].pipeline_depth[0]; + coredynp.num_fp_pipelines = XML->sys.core[ithCore].pipelines_per_core[1]; + coredynp.fp_pipeline_stages = XML->sys.core[ithCore].pipeline_depth[1]; + coredynp.int_data_width = int(ceil(XML->sys.machine_bits / 32.0)) * 32; + coredynp.fp_data_width = coredynp.int_data_width; + coredynp.v_address_width = XML->sys.virtual_address_width; + coredynp.p_address_width = XML->sys.physical_address_width; + + coredynp.scheu_ty = + (enum Scheduler_type)XML->sys.core[ithCore].instruction_window_scheme; + coredynp.arch_ireg_width = + int(ceil(log2(XML->sys.core[ithCore].archi_Regs_IRF_size))); + coredynp.arch_freg_width = + int(ceil(log2(XML->sys.core[ithCore].archi_Regs_FRF_size))); + coredynp.num_IRF_entry = XML->sys.core[ithCore].archi_Regs_IRF_size; + coredynp.num_FRF_entry = XML->sys.core[ithCore].archi_Regs_FRF_size; + coredynp.pipeline_duty_cycle = XML->sys.core[ithCore].pipeline_duty_cycle; + coredynp.total_cycles = XML->sys.core[ithCore].total_cycles; + coredynp.busy_cycles = XML->sys.core[ithCore].busy_cycles; + coredynp.idle_cycles = XML->sys.core[ithCore].idle_cycles; + + // Max power duty cycle for peak power estimation + // if (coredynp.core_ty==OOO) + // { + // coredynp.IFU_duty_cycle = 1; + // coredynp.LSU_duty_cycle = 1; + // coredynp.MemManU_I_duty_cycle =1; + // coredynp.MemManU_D_duty_cycle =1; + // coredynp.ALU_duty_cycle =1; + // coredynp.MUL_duty_cycle =1; + // coredynp.FPU_duty_cycle =1; + // coredynp.ALU_cdb_duty_cycle =1; + // coredynp.MUL_cdb_duty_cycle =1; + // coredynp.FPU_cdb_duty_cycle =1; + // } + // else + // { + coredynp.IFU_duty_cycle = XML->sys.core[ithCore].IFU_duty_cycle; + coredynp.BR_duty_cycle = XML->sys.core[ithCore].BR_duty_cycle; + coredynp.LSU_duty_cycle = XML->sys.core[ithCore].LSU_duty_cycle; + coredynp.MemManU_I_duty_cycle = XML->sys.core[ithCore].MemManU_I_duty_cycle; + coredynp.MemManU_D_duty_cycle = XML->sys.core[ithCore].MemManU_D_duty_cycle; + coredynp.ALU_duty_cycle = XML->sys.core[ithCore].ALU_duty_cycle; + coredynp.MUL_duty_cycle = XML->sys.core[ithCore].MUL_duty_cycle; + coredynp.FPU_duty_cycle = XML->sys.core[ithCore].FPU_duty_cycle; + coredynp.ALU_cdb_duty_cycle = XML->sys.core[ithCore].ALU_cdb_duty_cycle; + coredynp.MUL_cdb_duty_cycle = XML->sys.core[ithCore].MUL_cdb_duty_cycle; + coredynp.FPU_cdb_duty_cycle = XML->sys.core[ithCore].FPU_cdb_duty_cycle; + // } + + if (!(coredynp.core_ty == OOO) || (coredynp.core_ty == Inorder)) { + cout << "Invalid Core Type" << endl; + exit(0); + } + // if (coredynp.core_ty==OOO) + // { + // cout<<"OOO processor models are being updated and will be + // available in next release"<sys.core[ithCore].phy_Regs_IRF_size))); + coredynp.phy_freg_width = + int(ceil(log2(XML->sys.core[ithCore].phy_Regs_FRF_size))); + coredynp.num_ifreelist_entries = coredynp.num_IRF_entry = + XML->sys.core[ithCore].phy_Regs_IRF_size; + coredynp.num_ffreelist_entries = coredynp.num_FRF_entry = + XML->sys.core[ithCore].phy_Regs_FRF_size; + } + else if (coredynp.scheu_ty == + ReservationStation) { // ROB serves as Phy RF in RS based OOO + coredynp.phy_ireg_width = + int(ceil(log2(XML->sys.core[ithCore].ROB_size))); + coredynp.phy_freg_width = + int(ceil(log2(XML->sys.core[ithCore].ROB_size))); + coredynp.num_ifreelist_entries = XML->sys.core[ithCore].ROB_size; + coredynp.num_ffreelist_entries = XML->sys.core[ithCore].ROB_size; + } + } + + int GC_count = + XML->sys.core[ithCore].checkpoint_depth; // best check pointing entries + // for a 4~8 issue OOO should be + // 8~48;See TR for reference. + if (coredynp.rm_ty == RAMbased) { + coredynp.globalCheckpoint = + GC_count > 4 ? 4 : GC_count; // RAM-based RAT cannot have more than 4 + // GCs; see "a power-aware hybrid ram-cam + // renaming mechanism for fast recovery" + } + else if (coredynp.rm_ty == CAMbased) { + coredynp.globalCheckpoint = GC_count < 1 ? 1 : GC_count; + } + + coredynp.perThreadState = 8; + coredynp.instruction_length = 32; + coredynp.clockRate = XML->sys.core[ithCore].clock_rate; + coredynp.clockRate *= 1e6; + coredynp.regWindowing = (XML->sys.core[ithCore].register_windows_size > 0 && + coredynp.core_ty == Inorder) + ? true + : false; + coredynp.executionTime = XML->sys.total_cycles / coredynp.clockRate; + set_pppm(coredynp.pppm_lkg_multhread, 0, coredynp.num_hthreads, + coredynp.num_hthreads, 0); + + // does not care device types, since all core device types are set at sys. + // level + if (coredynp.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = coredynp.vdd; + interface_ip.lop_Vdd = coredynp.vdd; + interface_ip.lstp_Vdd = coredynp.vdd; + } + + if (coredynp.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = coredynp.power_gating_vcc; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/core.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/core.h new file mode 100644 index 0000000000..eea0b173fe --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/core.h @@ -0,0 +1,264 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef CORE_H_ +#define CORE_H_ + +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/parameter.h" +#include "interconnect.h" +#include "logic.h" +#include "sharedcache.h" + +using namespace cacti; + +class BranchPredictor : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + ArrayST *globalBPT; + ArrayST *localBPT; + ArrayST *L1_localBPT; + ArrayST *L2_localBPT; + ArrayST *chooser; + ArrayST *RAS; + bool exist; + + BranchPredictor(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exsit = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~BranchPredictor(); +}; + +class InstFetchU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + enum Cache_policy cache_p; + InstCache icache; + ArrayST *IB; + ArrayST *BTB; + BranchPredictor *BPT; + inst_decoder *ID_inst; + inst_decoder *ID_operand; + inst_decoder *ID_misc; + bool exist; + + InstFetchU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exsit = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~InstFetchU(); +}; + +class SchedulerU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double Iw_height, fp_Iw_height, ROB_height; + ArrayST *int_inst_window; + ArrayST *fp_inst_window; + ArrayST *ROB; + selection_logic *instruction_selection; + bool exist; + + SchedulerU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~SchedulerU(); +}; + +class RENAMINGU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + double clockRate, executionTime; + CoreDynParam coredynp; + ArrayST *iFRAT; + ArrayST *fFRAT; + ArrayST *iRRAT; + ArrayST *fRRAT; + ArrayST *ifreeL; + ArrayST *ffreeL; + dep_resource_conflict_check *idcl; + dep_resource_conflict_check *fdcl; + ArrayST *RAHT; // register alias history table Used to store GC + bool exist; + + RENAMINGU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~RENAMINGU(); +}; + +class LoadStoreU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + enum Cache_policy cache_p; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double lsq_height; + DataCache dcache; + ArrayST *LSQ; // it is actually the store queue but for inorder processors it + // serves as both loadQ and StoreQ + ArrayST *LoadQ; + bool exist; + + LoadStoreU(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~LoadStoreU(); +}; + +class MemManU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + ArrayST *itlb; + ArrayST *dtlb; + bool exist; + + MemManU(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MemManU(); +}; + +class RegFU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double int_regfile_height, fp_regfile_height; + ArrayST *IRF; + ArrayST *FRF; + ArrayST *RFWIN; + bool exist; + + RegFU(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~RegFU(); +}; + +class EXECU : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + double lsq_height; + CoreDynParam coredynp; + RegFU *rfu; + SchedulerU *scheu; + FunctionalUnit *fp_u; + FunctionalUnit *exeu; + FunctionalUnit *mul; + interconnect *int_bypass; + interconnect *intTagBypass; + interconnect *int_mul_bypass; + interconnect *intTag_mul_Bypass; + interconnect *fp_bypass; + interconnect *fpTagBypass; + + Component bypass; + bool exist; + + EXECU(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, + double lsq_height_, const CoreDynParam &dyn_p_, bool exist_ = true); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~EXECU(); +}; + +class Core : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + InstFetchU *ifu; + LoadStoreU *lsu; + MemManU *mmu; + EXECU *exu; + RENAMINGU *rnu; + Pipeline *corepipe; + UndiffCore *undiffCore; + SharedCache *l2cache; + CoreDynParam coredynp; + // full_decoder inst_decoder; + // clock_network clockNetwork; + Core(ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_); + void set_core_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~Core(); +}; + +#endif /* CORE_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/globalvar.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/globalvar.h new file mode 100644 index 0000000000..e0b76c2c6e --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/globalvar.h @@ -0,0 +1,43 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef GLOBALVAR_H_ +#define GLOBALVAR_H_ + +#ifdef GLOBALVAR +#define EXTERN +#else +#define EXTERN extern +#endif + +EXTERN bool opt_for_clk; + +#endif /* GLOBALVAR_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/interconnect.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/interconnect.cc new file mode 100644 index 0000000000..82d2a49689 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/interconnect.cc @@ -0,0 +1,209 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "interconnect.h" +#include +#include +#include "cacti/wire.h" +#include "globalvar.h" + +interconnect::interconnect(string name_, enum Device_ty device_ty_, + double base_w, double base_h, int data_w, double len, + const InputParameter *configure_interface, + int start_wiring_level_, bool pipelinable_, + double route_over_perc_, bool opt_local_, + enum Core_type core_ty_, enum Wire_type wire_model, + double width_s, double space_s, + TechnologyParameter::DeviceType *dt) + : name(name_), + device_ty(device_ty_), + in_rise_time(0), + out_rise_time(0), + base_width(base_w), + base_height(base_h), + data_width(data_w), + wt(wire_model), + width_scaling(width_s), + space_scaling(space_s), + start_wiring_level(start_wiring_level_), + length(len), + // interconnect_latency(1e-12), + // interconnect_throughput(1e-12), + opt_local(opt_local_), + core_ty(core_ty_), + pipelinable(pipelinable_), + route_over_perc(route_over_perc_), + deviceType(dt) { + wt = Global; + l_ip = *configure_interface; + local_result = init_interface(&l_ip); + + max_unpipelined_link_delay = 0; // TODO + min_w_nmos = g_tp.min_w_nmos_; + min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos; + + latency = l_ip.latency; + throughput = l_ip.throughput; + latency_overflow = false; + throughput_overflow = false; + + /* + * TODO: Add wiring option from semi-global to global automatically + * And directly jump to global if semi-global cannot satisfy timing + * Fat wires only available for global wires, thus + * if signal wiring layer starts from semi-global, + * the next layer up will be global, i.e., semi-global does + * not have fat wires. + */ + if (pipelinable == false) + // Non-pipelinable wires, such as bypass logic, care latency + { + compute(); + if (opt_for_clk && opt_local) { + while (delay > latency && width_scaling < 3.0) { + width_scaling *= 2; + space_scaling *= 2; + Wire winit(width_scaling, space_scaling); + compute(); + } + if (delay > latency) { + latency_overflow = true; + } + } + } + else // Pipelinable wires, such as bus, does not care latency but throughput + { + /* + * TODO: Add pipe regs power, area, and timing; + * Pipelinable wires optimize latency first. + */ + compute(); + if (opt_for_clk && opt_local) { + while (delay > throughput && width_scaling < 3.0) { + width_scaling *= 2; + space_scaling *= 2; + Wire winit(width_scaling, space_scaling); + compute(); + } + if (delay > throughput) + // insert pipeline stages + { + num_pipe_stages = (int)ceil(delay / throughput); + assert(num_pipe_stages > 0); + delay = delay / num_pipe_stages + num_pipe_stages * 0.05 * delay; + } + } + } + + power_bit = power; + power.readOp.dynamic *= data_width; + power.readOp.leakage *= data_width; + power.readOp.gate_leakage *= data_width; + area.set_area(area.get_area() * data_width); + no_device_under_wire_area.h *= data_width; + + if (latency_overflow == true) + cout << "Warning: " << name + << " wire structure cannot satisfy latency constraint." << endl; + + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + double pg_reduction = power_gating_leakage_reduction(false); // + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + + if (pipelinable) // Only global wires has the option to choose whether + // routing over or not + area.set_area(area.get_area() * route_over_perc + + no_device_under_wire_area.get_area() * (1 - route_over_perc)); + + // Wire wreset(); +} + +void interconnect::compute() { + Wire *wtemp1 = 0; + wtemp1 = new Wire(wt, length, 1, width_scaling, space_scaling); + delay = wtemp1->delay; + power.readOp.dynamic = wtemp1->power.readOp.dynamic; + power.readOp.leakage = wtemp1->power.readOp.leakage; + power.readOp.gate_leakage = wtemp1->power.readOp.gate_leakage; + + area.set_area(wtemp1->area.get_area()); + no_device_under_wire_area.h = (wtemp1->wire_width + wtemp1->wire_spacing); + no_device_under_wire_area.w = length; + + if (wtemp1) + delete wtemp1; +} + +void interconnect::leakage_feedback( + double temperature) // TODO: add code for processing power gating +{ + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + uca_org_t init_result = init_interface(&l_ip); // init_result is dummy + + compute(); + + power_bit = power; + power.readOp.dynamic *= data_width; + power.readOp.leakage *= data_width; + power.readOp.gate_leakage *= data_width; + + assert(power.readOp.dynamic > 0); + assert(power.readOp.leakage > 0); + assert(power.readOp.gate_leakage > 0); + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/interconnect.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/interconnect.h new file mode 100644 index 0000000000..9f3d14f3f7 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/interconnect.h @@ -0,0 +1,101 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef __INTERCONNECT_H__ +#define __INTERCONNECT_H__ + +#include "assert.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/cacti_interface.h" +#include "cacti/component.h" +#include "cacti/parameter.h" +#include "cacti/subarray.h" +#include "cacti/wire.h" + +// leakge power includes entire htree in a bank (when uca_tree == false) +// leakge power includes only part to one bank when uca_tree == true +using namespace cacti; + +class interconnect : public Component { + public: + interconnect(string name_, enum Device_ty device_ty_, double base_w, + double base_h, int data_w, double len, + const InputParameter *configure_interface, + int start_wiring_level_, bool pipelinable_ = false, + double route_over_perc_ = 0.5, bool opt_local_ = true, + enum Core_type core_ty_ = Inorder, + enum Wire_type wire_model = Global, double width_s = 1.0, + double space_s = 1.0, + TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)); + + ~interconnect(){}; + + void compute(); + string name; + enum Device_ty device_ty; + double in_rise_time, out_rise_time; + InputParameter l_ip; + uca_org_t local_result; + Area no_device_under_wire_area; + void set_in_rise_time(double rt) { in_rise_time = rt; } + + void leakage_feedback(double temperature); + double max_unpipelined_link_delay; + powerDef power_bit; + + double wire_bw; + double init_wire_bw; // bus width at root + double base_width; + double base_height; + int data_width; + enum Wire_type wt; + double width_scaling, space_scaling; + int start_wiring_level; + double length; + double min_w_nmos; + double min_w_pmos; + double latency, throughput; + bool latency_overflow; + bool throughput_overflow; + double interconnect_latency; + double interconnect_throughput; + bool opt_local; + enum Core_type core_ty; + bool pipelinable; + double route_over_perc; + int num_pipe_stages; + + private: + TechnologyParameter::DeviceType *deviceType; +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/iocontrollers.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/iocontrollers.cc new file mode 100644 index 0000000000..e1e98a7d21 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/iocontrollers.cc @@ -0,0 +1,602 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#include "iocontrollers.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +#include "logic.h" + +/* +SUN Niagara 2 I/O power analysis: +total signal bits: 711 +Total FBDIMM bits: (14+10)*2*8= 384 +PCIe bits: (8 + 8)*2 = 32 +10Gb NIC: (4*2+4*2)*2 = 32 +Debug I/Os: 168 +Other I/Os: 711- 32-32 - 384 - 168 = 95 + +According to "Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC +Server on a Chip" 90% of I/Os are SerDers (the calucaltion is +384+64/(711-168)=83% about the same as the 90% reported in the paper) +--> around 80Pins are common I/Os. +Common I/Os consumes 71mW/Gb/s according to Cadence ChipEstimate @65nm +Niagara 2 I/O clock is 1/4 of core clock. --> 87pin (<--((711-168)*17%)) * +71mW/Gb/s *0.25*1.4Ghz = 2.17W + +Total dynamic power of FBDIMM, NIC, PCIe = 84*0.132 + 84*0.049*0.132 = 11.14 +- 2.17 = 8.98 Further, if assuming I/O logic power is about 50% of I/Os then +Total energy of FBDIMM, NIC, PCIe = 11.14 - 2.17*1.5 = 7.89 + */ + +/* + * A bug in Cadence ChipEstimator: After update the clock rate in the clock tab, + * a user need to re-select the IP clock (the same clk) and then click Estimate. + * if not reselect the new clock rate may not be propogate into the IPs. + * + */ + +NIUController::NIUController(ParseXML *XML_interface, + InputParameter *interface_ip_) + : XML(XML_interface), interface_ip(*interface_ip_) { + double frontend_area; + // double phy_area; + double mac_area; + double SerDer_area; + double frontend_dyn; + double mac_dyn; + double SerDer_dyn; + double frontend_gates; + double mac_gates; + // double SerDer_gates = 0.; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing; + double PMOS_sizing; + + set_niu_param(); + local_result = init_interface(&interface_ip); + + if (niup.type == 0) // high performance NIU + { + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate using 65nm. + mac_area = (1.53 + 0.3) / 2 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2, ISSCC "An + // 800mW 10Gb Ethernet Transceiver in 0.13μm CMOS" and"A 1.2-V-Only 900-mW + // 10 Gb Ethernet Transceiver and XAUI Interface With Robust VCO Tuning + // Technique" Frontend is PCS + frontend_area = (9.8 + (6 + 18) * 65 / 130 * 65 / 130) / 3 * + (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate hard IP @65nm. SerDer is very hard to scale + SerDer_area = (1.39 + 0.36) * (interface_ip.F_sz_um / + 0.065); //* (interface_ip.F_sz_um/0.065); + // phy_area = frontend_area + SerDer_area; + // total area + area.set_area((mac_area + frontend_area + SerDer_area) * 1e6); + // Power + // Cadence ChipEstimate using 65nm (mac, front_end are all energy. E=P*T = + // P/F = 1.37/1Ghz = 1.37e-9); + mac_dyn = 2.19e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // //2.19W@1GHz fully active + // according to Cadence + // ChipEstimate @65nm + // Cadence ChipEstimate using 65nm soft IP; + frontend_dyn = 0.27e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // according to "A 100mW 9.6Gb/s Transceiver in 90nm CMOS..." ISSCC 2006 + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 10 * sqrt(interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2; + SerDer_dyn /= + niup.clockRate; // covert to energy per clock cycle of whole NIU + + // Cadence ChipEstimate using 65nm + mac_gates = 111700; + frontend_gates = 320000; + // SerDer_gates = 200000; + NMOS_sizing = 5 * g_tp.min_w_nmos_; + PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + else { // Low power implementations are mostly from Cadence ChipEstimator; + // Ignore the multiple IP effect + // ---When there are multiple IP (same kind or not) selected, Cadence + // ChipEstimator results are not a simple summation of all IPs. Ignore this + // effect + mac_area = + 0.24 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + frontend_area = + 0.1 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); // Frontend is the PCS layer + SerDer_area = + 0.35 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // Compare 130um implementation in "A 1.2-V-Only 900-mW 10 Gb Ethernet + // Transceiver and XAUI Interface With Robust VCO Tuning Technique" and the + // ChipEstimator XAUI PHY hard IP, confirm that even PHY can scale perfectly + // with the technology total area + area.set_area((mac_area + frontend_area + SerDer_area) * 1e6); + // Power + // Cadence ChipEstimate using 65nm (mac, front_end are all energy. E=P*T = + // P/F = 1.37/1Ghz = 1.37e-9); + mac_dyn = 1.257e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // //2.19W@1GHz fully active + // according to Cadence + // ChipEstimate @65nm + // Cadence ChipEstimate using 65nm soft IP; + frontend_dyn = 0.6e-9 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); // niup.clockRate; + // SerDer_dyn is power not energy, scaling from 216mw/10Gb/s @130nm + SerDer_dyn = 0.0216 * 10 * (interface_ip.F_sz_um / 0.13) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2; + SerDer_dyn /= + niup.clockRate; // covert to energy per clock cycle of whole NIU + + mac_gates = 111700; + frontend_gates = 52000; + // SerDer_gates = 199260; + + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + + power_t.readOp.dynamic = mac_dyn + frontend_dyn + SerDer_dyn; + power_t.readOp.leakage = + (mac_gates + frontend_gates + frontend_gates) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; + + power_t.readOp.gate_leakage = + (mac_gates + frontend_gates + frontend_gates) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W +} + +void NIUController::computeEnergy(bool is_tdp) { + if (is_tdp) { + power = power_t; + power.readOp.dynamic *= niup.duty_cycle; + } + else { + rt_power = power_t; + rt_power.readOp.dynamic *= niup.perc_load; + } +} + +void NIUController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "NIU:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * niup.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic * niup.clockRate + << " W" << endl; + cout << endl; + } + else { + } +} + +void NIUController::set_niu_param() { + niup.clockRate = XML->sys.niu.clockrate; + niup.clockRate *= 1e6; + niup.num_units = XML->sys.niu.number_units; + niup.duty_cycle = XML->sys.niu.duty_cycle; + niup.perc_load = XML->sys.niu.total_load_perc; + niup.type = XML->sys.niu.type; + if (XML->sys.niu.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.niu.vdd; + interface_ip.lop_Vdd = XML->sys.niu.vdd; + interface_ip.lstp_Vdd = XML->sys.niu.vdd; + } + + if (XML->sys.niu.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.niu.power_gating_vcc; + } + // niup.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); +} + +PCIeController::PCIeController(ParseXML *XML_interface, + InputParameter *interface_ip_) + : XML(XML_interface), interface_ip(*interface_ip_) { + // double frontend_area; + // double phy_area; + double ctrl_area; + double SerDer_area; + double ctrl_dyn; + // double frontend_dyn; + double SerDer_dyn; + double ctrl_gates; + // double frontend_gates; + double SerDer_gates = 0.; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing; + double PMOS_sizing; + + /* Assuming PCIe is bit-slice based architecture + * This is the reason for /8 in both area and power calculation + * to get per lane numbers + */ + set_pcie_param(); + local_result = init_interface(&interface_ip); + + if (pciep.type == 0) // high performance NIU + { + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate @ 65nm. + ctrl_area = (5.2 + 0.5) / 2 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2, and Cadence + // ChipEstimate @ 65nm. + // frontend_area = (5.2 + 0.1) / 2 * (interface_ip.F_sz_um / 0.065) * + // (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2 and Cadence + // ChipEstimate hard IP @65nm. SerDer is very hard to scale + SerDer_area = (3.03 + 0.36) * (interface_ip.F_sz_um / + 0.065); //* (interface_ip.F_sz_um/0.065); + // phy_area = frontend_area + SerDer_area; + // total area + // Power + // Cadence ChipEstimate using 65nm the controller includes everything: the + // PHY, the data link and transaction layer + ctrl_dyn = 3.75e-9 / 8 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); + // //Cadence ChipEstimate using 65nm soft IP; + // frontend_dyn = + // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / + 1.2; // PCIe 2.0 max per lane speed is 4Gb/s + SerDer_dyn /= pciep.clockRate; // covert to energy per clock cycle + + // power_t.readOp.dynamic = (ctrl_dyn)*pciep.num_channels; + // Cadence ChipEstimate using 65nm + ctrl_gates = 900000 / 8 * pciep.num_channels; + // frontend_gates = 120000/8; + // SerDer_gates = 200000/8; + NMOS_sizing = 5 * g_tp.min_w_nmos_; + PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + else { + ctrl_area = + 0.412 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // Area estimation based on average of die photo from Niagara 2, and Cadence + // ChipEstimate @ 65nm. + SerDer_area = + 0.36 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // total area + // Power + // Cadence ChipEstimate using 65nm the controller includes everything: the + // PHY, the data link and transaction layer + ctrl_dyn = 2.21e-9 / 8 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / + 1.1 * (interface_ip.F_sz_nm / 65.0); + // //Cadence ChipEstimate using 65nm soft IP; + // frontend_dyn = + // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0); + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / + 1.2; // PCIe 2.0 max per lane speed is 4Gb/s + SerDer_dyn /= pciep.clockRate; // covert to energy per clock cycle + + // Cadence ChipEstimate using 65nm + ctrl_gates = 200000 / 8 * pciep.num_channels; + // frontend_gates = 120000/8; + SerDer_gates = 200000 / 8 * pciep.num_channels; + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + area.set_area(((ctrl_area + (pciep.withPHY ? SerDer_area : 0)) / 8 * + pciep.num_channels) * + 1e6); + power_t.readOp.dynamic = + (ctrl_dyn + (pciep.withPHY ? SerDer_dyn : 0)) * pciep.num_channels; + power_t.readOp.leakage = + (ctrl_gates + (pciep.withPHY ? SerDer_gates : 0)) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; + power_t.readOp.gate_leakage = + (ctrl_gates + (pciep.withPHY ? SerDer_gates : 0)) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W +} + +void PCIeController::computeEnergy(bool is_tdp) { + if (is_tdp) { + power = power_t; + power.readOp.dynamic *= pciep.duty_cycle; + } + else { + rt_power = power_t; + rt_power.readOp.dynamic *= pciep.perc_load; + } +} + +void PCIeController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "PCIe:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * pciep.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic * pciep.clockRate + << " W" << endl; + cout << endl; + } + else { + } +} + +void PCIeController::set_pcie_param() { + pciep.clockRate = XML->sys.pcie.clockrate; + pciep.clockRate *= 1e6; + pciep.num_units = XML->sys.pcie.number_units; + pciep.num_channels = XML->sys.pcie.num_channels; + pciep.duty_cycle = XML->sys.pcie.duty_cycle; + pciep.perc_load = XML->sys.pcie.total_load_perc; + pciep.type = XML->sys.pcie.type; + pciep.withPHY = XML->sys.pcie.withPHY; + + if (XML->sys.pcie.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.pcie.vdd; + interface_ip.lop_Vdd = XML->sys.pcie.vdd; + interface_ip.lstp_Vdd = XML->sys.pcie.vdd; + } + + if (XML->sys.pcie.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.pcie.power_gating_vcc; + } + // pciep.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); +} + +FlashController::FlashController(ParseXML *XML_interface, + InputParameter *interface_ip_) + : XML(XML_interface), interface_ip(*interface_ip_) { + // double frontend_area; + // double phy_area; + double ctrl_area; + double SerDer_area; + double ctrl_dyn; + // double frontend_dyn; + double SerDer_dyn; + double ctrl_gates; + // double frontend_gates; + double SerDer_gates = 0.; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing; + double PMOS_sizing; + + /* Assuming PCIe is bit-slice based architecture + * This is the reason for /8 in both area and power calculation + * to get per lane numbers + */ + + set_fc_param(); + local_result = init_interface(&interface_ip); + if (fcp.type == 0) // high performance NIU + { + cout << "Current McPAT does not support high performance flash contorller " + "since even low power designs are enough for maintain throughput" + << endl; + exit(0); + NMOS_sizing = 5 * g_tp.min_w_nmos_; + PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + } + else { + ctrl_area = + 0.243 * (interface_ip.F_sz_um / 0.065) * (interface_ip.F_sz_um / 0.065); + // Area estimation based on Cadence ChipEstimate @ 65nm: NANDFLASH-CTRL from + // CAST + SerDer_area = 0.36 / 8 * (interface_ip.F_sz_um / 0.065) * + (interface_ip.F_sz_um / 0.065); + // based On PCIe PHY TSMC65GP from Cadence ChipEstimate @ 65nm, it support + // 8x lanes with each lane speed up to 250MB/s (PCIe1.1x) This is already + // saturate the 200MB/s of the flash controller core above. + ctrl_gates = 129267; + SerDer_gates = 200000 / 8; + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + + // Power + // Cadence ChipEstimate using 65nm the controller 125mW for every 200MB/s + // This is power not energy! + ctrl_dyn = 0.125 * g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / 1.1 * + (interface_ip.F_sz_nm / 65.0); + // SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm + SerDer_dyn = 0.01 * 1.6 * (interface_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2; + // max Per controller speed is 1.6Gb/s (200MB/s) + } + double number_channel = 1 + (fcp.num_channels - 1) * 0.2; + area.set_area((ctrl_area + (fcp.withPHY ? SerDer_area : 0)) * 1e6 * + number_channel); + power_t.readOp.dynamic = + (ctrl_dyn + (fcp.withPHY ? SerDer_dyn : 0)) * number_channel; + power_t.readOp.leakage = + ((ctrl_gates + (fcp.withPHY ? SerDer_gates : 0)) * number_channel) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + double pg_reduction = power_gating_leakage_reduction( + false); // array structure all retain state; + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; + power_t.readOp.gate_leakage = + ((ctrl_gates + (fcp.withPHY ? SerDer_gates : 0)) * number_channel) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W +} + +void FlashController::computeEnergy(bool is_tdp) { + if (is_tdp) { + power = power_t; + power.readOp.dynamic *= fcp.duty_cycle; + } + else { + rt_power = power_t; + rt_power.readOp.dynamic *= fcp.perc_load; + } +} + +void FlashController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "Flash Controller:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic << " W" + << endl; // no multiply of clock since this is power already + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic + << " W" << endl; + cout << endl; + } + else { + } +} + +void FlashController::set_fc_param() { + // fcp.clockRate = XML->sys.flashc.mc_clock; + // fcp.clockRate *= 1e6; + fcp.peakDataTransferRate = XML->sys.flashc.peak_transfer_rate; + fcp.num_channels = ceil(fcp.peakDataTransferRate / 200); + fcp.num_mcs = XML->sys.flashc.number_mcs; + fcp.duty_cycle = XML->sys.flashc.duty_cycle; + fcp.perc_load = XML->sys.flashc.total_load_perc; + fcp.type = XML->sys.flashc.type; + fcp.withPHY = XML->sys.flashc.withPHY; + // flashcp.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + if (XML->sys.flashc.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.flashc.vdd; + interface_ip.lop_Vdd = XML->sys.flashc.vdd; + interface_ip.lstp_Vdd = XML->sys.flashc.vdd; + } + if (XML->sys.flashc.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.flashc.power_gating_vcc; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/iocontrollers.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/iocontrollers.h new file mode 100644 index 0000000000..9f80cc48dc --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/iocontrollers.h @@ -0,0 +1,85 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#ifndef IOCONTROLLERS_H_ +#define IOCONTROLLERS_H_ + +#endif /* IOCONTROLLERS_H_ */ + +#include "XML_Parse.h" +#include "cacti/parameter.h" +//#include "io.h" +#include "array.h" +//#include "Undifferentiated_Core_Area.h" +#include +#include "basic_components.h" +using namespace cacti; + +class NIUController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + NIUParam niup; + powerDef power_t; + uca_org_t local_result; + NIUController(ParseXML *XML_interface, InputParameter *interface_ip_); + void set_niu_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~NIUController(){}; +}; + +class PCIeController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + PCIeParam pciep; + powerDef power_t; + uca_org_t local_result; + PCIeController(ParseXML *XML_interface, InputParameter *interface_ip_); + void set_pcie_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~PCIeController(){}; +}; + +class FlashController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + MCParam fcp; + powerDef power_t; + uca_org_t local_result; + FlashController(ParseXML *XML_interface, InputParameter *interface_ip_); + void set_fc_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~FlashController(){}; +}; diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/logic.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/logic.cc new file mode 100644 index 0000000000..e22c4d0d98 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/logic.cc @@ -0,0 +1,1370 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "logic.h" + +// selection_logic +selection_logic::selection_logic(bool _is_default, int win_entries_, + int issue_width_, + const InputParameter *configure_interface, + enum Device_ty device_ty_, + enum Core_type core_ty_) + // const ParseXML *_XML_interface) + : is_default(_is_default), + win_entries(win_entries_), + issue_width(issue_width_), + device_ty(device_ty_), + core_ty(core_ty_) { + // uca_org_t result2; + l_ip = *configure_interface; + local_result = init_interface(&l_ip); + // init_tech_params(l_ip.F_sz_um, false); + // win_entries=numIBEntries;//IQentries; + // issue_width=issueWidth; + selection_power(); + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void selection_logic::selection_power() { // based on cost effective + // superscalar processor TR pp27-31 + double Ctotal, Cor, Cpencode; + int num_arbiter; + double WSelORn, WSelORprequ, WSelPn, WSelPp, WSelEnn, WSelEnp; + + // TODO: the 0.8um process data is used. + WSelORn = + 12.5 * l_ip.F_sz_um; // this was 10 micron for the 0.8 micron process + WSelORprequ = + 50 * l_ip.F_sz_um; // this was 40 micron for the 0.8 micron process + WSelPn = 12.5 * l_ip.F_sz_um; // this was 10mcron for the 0.8 micron process + WSelPp = + 18.75 * l_ip.F_sz_um; // this was 15 micron for the 0.8 micron process + WSelEnn = 6.25 * l_ip.F_sz_um; // this was 5 micron for the 0.8 micron + // process + WSelEnp = + 12.5 * l_ip.F_sz_um; // this was 10 micron for the 0.8 micron process + + Ctotal = 0; + num_arbiter = 1; + while (win_entries > 4) { + win_entries = (int)ceil((double)win_entries / 4.0); + num_arbiter += win_entries; + } + // the 4-input OR logic to generate anyreq + Cor = 4 * drain_C_(WSelORn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelORprequ, PCH, 1, 1, g_tp.cell_h_def); + power.readOp.gate_leakage = + cmos_Ig_leakage(WSelORn, WSelORprequ, 4, nor) * g_tp.peri_global.Vdd; + + // The total capacity of the 4-bit priority encoder + Cpencode = + drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 1, 1, g_tp.cell_h_def) + + 2 * drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 2, 1, g_tp.cell_h_def) + + 3 * drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 3, 1, g_tp.cell_h_def) + + 4 * drain_C_(WSelPn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(WSelPp, PCH, 4, 1, + g_tp.cell_h_def) + // precompute priority logic + 2 * 4 * gate_C(WSelEnn + WSelEnp, 20.0) + + 4 * drain_C_(WSelEnn, NCH, 1, 1, g_tp.cell_h_def) + + 2 * 4 * drain_C_(WSelEnp, PCH, 1, 1, g_tp.cell_h_def) + // enable logic + (2 * 4 + 2 * 3 + 2 * 2 + 2) * + gate_C(WSelPn + WSelPp, 10.0); // requests signal + + Ctotal += issue_width * num_arbiter * (Cor + Cpencode); + + power.readOp.dynamic = + Ctotal * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * + 2; // 2 means the abitration signal need to travel round trip + power.readOp.leakage = + issue_width * num_arbiter * + (cmos_Isub_leakage( + WSelPn, WSelPp, 2, + nor) /*approximate precompute with a nor gate*/ // grant1p + + cmos_Isub_leakage(WSelPn, WSelPp, 3, nor) // grant2p + + cmos_Isub_leakage(WSelPn, WSelPp, 4, nor) // grant3p + + cmos_Isub_leakage(WSelEnn, WSelEnp, 2, nor) * 4 // enable logic + + cmos_Isub_leakage(WSelEnn, WSelEnp, 1, inv) * 2 * + 3 // for each grant there are two inverters, there are 3 grant + // sIsubnals + ) * + g_tp.peri_global.Vdd; + power.readOp.gate_leakage = + issue_width * num_arbiter * + (cmos_Ig_leakage( + WSelPn, WSelPp, 2, + nor) /*approximate precompute with a nor gate*/ // grant1p + + cmos_Ig_leakage(WSelPn, WSelPp, 3, nor) // grant2p + + cmos_Ig_leakage(WSelPn, WSelPp, 4, nor) // grant3p + + cmos_Ig_leakage(WSelEnn, WSelEnp, 2, nor) * 4 // enable logic + + cmos_Ig_leakage(WSelEnn, WSelEnp, 1, inv) * 2 * + 3 // for each grant there are two inverters, there are 3 grant + // signals + ) * + g_tp.peri_global.Vdd; +} + +dep_resource_conflict_check::dep_resource_conflict_check( + const InputParameter *configure_interface, const CoreDynParam &dyn_p_, + int compare_bits_, bool _is_default) + : l_ip(*configure_interface), + coredynp(dyn_p_), + compare_bits(compare_bits_), + is_default(_is_default) { + Wcompn = 25 * l_ip.F_sz_um; // this was 20.0 micron for the 0.8 micron + // process + Wevalinvp = + 25 * l_ip.F_sz_um; // this was 20.0 micron for the 0.8 micron process + Wevalinvn = + 100 * l_ip.F_sz_um; // this was 80.0 mcron for the 0.8 micron process + Wcomppreequ = + 50 * l_ip.F_sz_um; // this was 40.0 micron for the 0.8 micron process + WNORn = 6.75 * l_ip.F_sz_um; // this was 5.4 micron for the 0.8 micron + // process + WNORp = + 38.125 * l_ip.F_sz_um; // this was 30.5 micron for the 0.8 micron process + + local_result = init_interface(&l_ip); + + if (coredynp.core_ty == Inorder) + compare_bits += 16 + 8 + 8; // TODO: opcode bits + log(shared resources) + + // REG TAG BITS-->opcode comparator + else + compare_bits += 16 + 8 + 8; + + conflict_check_power(); + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; +} + +void dep_resource_conflict_check::conflict_check_power() { + double Ctotal; + int num_comparators; + num_comparators = 3 * ((coredynp.decodeW) * (coredynp.decodeW) - + coredynp.decodeW); // 2(N*N-N) is used for source to + // dest comparison, (N*N-N) is used + // for dest to dest comparision. + // When decode-width ==1, no dcl logic + + Ctotal = num_comparators * compare_cap(); + // printf("%i,%s\n",XML_interface->sys.core[0].predictor.predictor_entries,XML_interface->sys.core[0].predictor.prediction_scheme); + + power.readOp.dynamic = + Ctotal * /*CLOCKRATE*/ g_tp.peri_global.Vdd * g_tp.peri_global.Vdd /*AF*/; + power.readOp.leakage = num_comparators * compare_bits * 2 * + simplified_nmos_leakage(Wcompn, false); + + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + power.readOp.gate_leakage = + num_comparators * compare_bits * 2 * cmos_Ig_leakage(Wcompn, 0, 2, nmos); + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +/* estimate comparator power consumption (this comparator is similar + to the tag-match structure in a CAM */ +double dep_resource_conflict_check::compare_cap() { + double c1, c2; + + WNORp = WNORp * compare_bits / + 2.0; // resize the big NOR gate at the DCL according to fan in. + /* bottom part of comparator */ + c2 = (compare_bits) * (drain_C_(Wcompn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(Wcompn, NCH, 2, 1, g_tp.cell_h_def)) + + drain_C_(Wevalinvp, PCH, 1, 1, g_tp.cell_h_def) + + drain_C_(Wevalinvn, NCH, 1, 1, g_tp.cell_h_def); + + /* top part of comparator */ + c1 = (compare_bits) * (drain_C_(Wcompn, NCH, 1, 1, g_tp.cell_h_def) + + drain_C_(Wcompn, NCH, 2, 1, g_tp.cell_h_def) + + drain_C_(Wcomppreequ, NCH, 1, 1, g_tp.cell_h_def)) + + gate_C(WNORn + WNORp, 10.0) + + drain_C_(WNORp, NCH, 2, 1, g_tp.cell_h_def) + + compare_bits * drain_C_(WNORn, NCH, 2, 1, g_tp.cell_h_def); + return (c1 + c2); +} + +void dep_resource_conflict_check::leakage_feedback(double temperature) { + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + uca_org_t init_result = init_interface(&l_ip); // init_result is dummy + + // This is part of conflict_check_power() + int num_comparators = 3 * ((coredynp.decodeW) * (coredynp.decodeW) - + coredynp.decodeW); // 2(N*N-N) is used for source + // to dest comparison, (N*N-N) + // is used for dest to dest + // comparision. + power.readOp.leakage = num_comparators * compare_bits * 2 * + simplified_nmos_leakage(Wcompn, false); + + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + power.readOp.gate_leakage = + num_comparators * compare_bits * 2 * cmos_Ig_leakage(Wcompn, 0, 2, nmos); + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +// TODO: add inverter and transmission gate base DFF. + +DFFCell::DFFCell(bool _is_dram, double _WdecNANDn, double _WdecNANDp, + double _cell_load, const InputParameter *configure_interface) + : is_dram(_is_dram), + cell_load(_cell_load), + WdecNANDn(_WdecNANDn), + WdecNANDp(_WdecNANDp) { // this model is based on the NAND2 based DFF. + l_ip = *configure_interface; + // area.set_area(730*l_ip.F_sz_um*l_ip.F_sz_um); + area.set_area( + 5 * compute_gate_area(NAND, 2, WdecNANDn, WdecNANDp, g_tp.cell_h_def) + + compute_gate_area(NAND, 2, WdecNANDn, WdecNANDn, g_tp.cell_h_def)); +} + +double DFFCell::fpfp_node_cap(unsigned int fan_in, unsigned int fan_out) { + double Ctotal = 0; + // printf("WdecNANDn = %E\n", WdecNANDn); + + /* part 1: drain cap of NAND gate */ + Ctotal += drain_C_(WdecNANDn, NCH, 2, 1, g_tp.cell_h_def, is_dram) + + fan_in * drain_C_(WdecNANDp, PCH, 1, 1, g_tp.cell_h_def, is_dram); + + /* part 2: gate cap of NAND gates */ + Ctotal += fan_out * gate_C(WdecNANDn + WdecNANDp, 0, is_dram); + + return Ctotal; +} + +void DFFCell::compute_DFF_cell() { + double c1, c2, c3, c4, c5, c6; + /* node 5 and node 6 are identical to node 1 in capacitance */ + c1 = c5 = c6 = fpfp_node_cap(2, 1); + c2 = fpfp_node_cap(2, 3); + c3 = fpfp_node_cap(3, 2); + c4 = fpfp_node_cap(2, 2); + + // cap-load of the clock signal in each Dff, actually the clock signal only + // connected to one NAND2 + clock_cap = 2 * gate_C(WdecNANDn + WdecNANDp, 0, is_dram); + e_switch.readOp.dynamic += (c4 + c1 + c2 + c3 + c5 + c6 + 2 * cell_load) * + 0.5 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + ; + + /* no 1/2 for e_keep and e_clock because clock signal switches twice in one + * cycle */ + e_keep_1.readOp.dynamic += c3 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + e_keep_0.readOp.dynamic += c2 * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + e_clock.readOp.dynamic += + clock_cap * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd; + ; + + /* static power */ + e_switch.readOp.leakage += + (cmos_Isub_leakage(WdecNANDn, WdecNANDp, 2, nand) * + 5 // 5 NAND2 and 1 NAND3 in a DFF + + cmos_Isub_leakage(WdecNANDn, WdecNANDn, 3, nand)) * + g_tp.peri_global.Vdd; + e_switch.readOp.gate_leakage += + (cmos_Ig_leakage(WdecNANDn, WdecNANDp, 2, nand) * + 5 // 5 NAND2 and 1 NAND3 in a DFF + + cmos_Ig_leakage(WdecNANDn, WdecNANDn, 3, nand)) * + g_tp.peri_global.Vdd; + // printf("leakage =%E\n",cmos_Ileak(1, is_dram) ); +} + +Pipeline::Pipeline(const InputParameter *configure_interface, + const CoreDynParam &dyn_p_, enum Device_ty device_ty_, + bool _is_core_pipeline, bool _is_default) + : l_ip(*configure_interface), + coredynp(dyn_p_), + device_ty(device_ty_), + is_core_pipeline(_is_core_pipeline), + is_default(_is_default), + num_piperegs(0.0) + +{ + local_result = init_interface(&l_ip); + if (!coredynp.Embedded) + process_ind = true; + else + process_ind = false; + WNANDn = + (process_ind) + ? 25 * l_ip.F_sz_um + : g_tp.min_w_nmos_; // this was 20 micron for the 0.8 micron process + WNANDp = (process_ind) + ? 37.5 * l_ip.F_sz_um + : g_tp.min_w_nmos_ * pmos_to_nmos_sz_ratio(); // this was 30 + // micron for the + // 0.8 micron + // process + load_per_pipeline_stage = 2 * gate_C(WNANDn + WNANDp, 0, false); + compute(); +} + +void Pipeline::compute() { + compute_stage_vector(); + DFFCell pipe_reg(false, WNANDn, WNANDp, load_per_pipeline_stage, &l_ip); + pipe_reg.compute_DFF_cell(); + + double clock_power_pipereg = num_piperegs * pipe_reg.e_clock.readOp.dynamic; + //******************pipeline power: currently, we average all the + // possibilities of the states of DFFs in the pipeline. A better way to do it + // is to consider the harming distance of two consecutive signals, However + // McPAT does not have plan to do this in near future as it focuses on worst + // case power. + double pipe_reg_power = + num_piperegs * + (pipe_reg.e_switch.readOp.dynamic + pipe_reg.e_keep_0.readOp.dynamic + + pipe_reg.e_keep_1.readOp.dynamic) / + 3 + + clock_power_pipereg; + double pipe_reg_leakage = num_piperegs * pipe_reg.e_switch.readOp.leakage; + double pipe_reg_gate_leakage = + num_piperegs * pipe_reg.e_switch.readOp.gate_leakage; + power.readOp.dynamic += pipe_reg_power; + power.readOp.leakage += pipe_reg_leakage; + power.readOp.gate_leakage += pipe_reg_gate_leakage; + area.set_area(num_piperegs * pipe_reg.area.get_area()); + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + double macro_layout_overhead = g_tp.macro_layout_overhead; + if (!coredynp.Embedded) + area.set_area(area.get_area() * macro_layout_overhead); +} + +void Pipeline::compute_stage_vector() { + double num_stages, tot_stage_vector, per_stage_vector; + int opcode_length = + coredynp.x86 ? coredynp.micro_opcode_length : coredynp.opcode_length; + // Hthread = thread_clock_gated? 1:num_thread; + + if (!is_core_pipeline) { + num_piperegs = l_ip.pipeline_stages * + l_ip.per_stage_vector; // The number of pipeline stages are + // calculated based on the achievable + // throughput and required throughput + } + else { + if (coredynp.core_ty == Inorder) { + /* assume 6 pipe stages and try to estimate bits per pipe stage */ + /* pipe stage 0/IF */ + num_piperegs += coredynp.pc_width * 2 * coredynp.num_hthreads; + /* pipe stage IF/ID */ + num_piperegs += coredynp.fetchW * + (coredynp.instruction_length + coredynp.pc_width) * + coredynp.num_hthreads; + /* pipe stage IF/ThreadSEL */ + if (coredynp.multithreaded) + num_piperegs += coredynp.num_hthreads * + coredynp.perThreadState; // 8 bit thread states + /* pipe stage ID/EXE */ + num_piperegs += coredynp.decodeW * + (coredynp.instruction_length + coredynp.pc_width + + pow(2.0, opcode_length) + 2 * coredynp.int_data_width) * + coredynp.num_hthreads; + /* pipe stage EXE/MEM */ + num_piperegs += + coredynp.issueW * + (3 * coredynp.arch_ireg_width + pow(2.0, opcode_length) + + 8 * 2 * coredynp.int_data_width /*+2*powers (2,reg_length)*/); + /* pipe stage MEM/WB the 2^opcode_length means the total decoded signal + * for the opcode*/ + num_piperegs += + coredynp.issueW * + (2 * coredynp.int_data_width + pow(2.0, opcode_length) + + 8 * 2 * coredynp.int_data_width /*+2*powers (2,reg_length)*/); + // /* pipe stage 5/6 */ + // num_piperegs += issueWidth*(data_width + powers + //(2,opcode_length)/*+2*powers (2,reg_length)*/); + // /* pipe stage 6/7 */ + // num_piperegs += issueWidth*(data_width + powers + //(2,opcode_length)/*+2*powers (2,reg_length)*/); + // /* pipe stage 7/8 */ + // num_piperegs += issueWidth*(data_width + powers + //(2,opcode_length)/**2*powers (2,reg_length)*/); + // /* assume 50% extra in control signals (rule of thumb) + //*/ + num_stages = 6; + } + else { + /* assume 12 stage pipe stages and try to estimate bits per pipe stage */ + /*OOO: Fetch, decode, rename, IssueQ, dispatch, regread, EXE, MEM, WB, CM + */ + + /* pipe stage 0/1F*/ + num_piperegs += + coredynp.pc_width * 2 * coredynp.num_hthreads; // PC and Next PC + /* pipe stage IF/ID */ + num_piperegs += + coredynp.fetchW * (coredynp.instruction_length + coredynp.pc_width) * + coredynp.num_hthreads; // PC is used to feed branch predictor in ID + /* pipe stage 1D/Renaming*/ + num_piperegs += + coredynp.decodeW * (coredynp.instruction_length + coredynp.pc_width) * + coredynp.num_hthreads; // PC is for branch exe in later stage. + /* pipe stage Renaming/wire_drive */ + num_piperegs += + coredynp.decodeW * (coredynp.instruction_length + coredynp.pc_width); + /* pipe stage Renaming/IssueQ */ + num_piperegs += coredynp.issueW * + (coredynp.instruction_length + coredynp.pc_width + + 3 * coredynp.phy_ireg_width) * + coredynp.num_hthreads; // 3*coredynp.phy_ireg_width means + // 2 sources and 1 dest + /* pipe stage IssueQ/Dispatch */ + num_piperegs += coredynp.issueW * (coredynp.instruction_length + + 3 * coredynp.phy_ireg_width); + /* pipe stage Dispatch/EXE */ + + num_piperegs += coredynp.issueW * + (3 * coredynp.phy_ireg_width + coredynp.pc_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); + /* 2^opcode_length means the total decoded signal for the opcode*/ + num_piperegs += coredynp.issueW * + (2 * coredynp.int_data_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); + /*2 source operands in EXE; Assume 2EXE stages* since we do not really + * distinguish OP*/ + num_piperegs += coredynp.issueW * + (2 * coredynp.int_data_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); + /* pipe stage EXE/MEM, data need to be read/write, address*/ + num_piperegs += + coredynp.issueW * + (coredynp.int_data_width + coredynp.v_address_width + + pow(2.0, opcode_length) /*+2*powers (2,reg_length)*/); // memory + // Opcode + // still need + // to be + // passed + /* pipe stage MEM/WB; result data, writeback regs */ + num_piperegs += + coredynp.issueW * (coredynp.int_data_width + coredynp.phy_ireg_width /* powers (2,opcode_length) + (2,opcode_length)+2*powers (2,reg_length)*/); + /* pipe stage WB/CM ; result data, regs need to be updated, address for + * resolve memory ops in ROB's top*/ + num_piperegs += + coredynp.commitW * + (coredynp.int_data_width + coredynp.v_address_width + coredynp.phy_ireg_width /*+ powers (2,opcode_length)*2*powers (2,reg_length)*/) * + coredynp.num_hthreads; + // if (multithreaded) + // { + // + // } + num_stages = 12; + } + + /* assume 50% extra in control registers and interrupt registers (rule of + * thumb) */ + num_piperegs = num_piperegs * 1.5; + tot_stage_vector = num_piperegs; + per_stage_vector = tot_stage_vector / num_stages; + + if (coredynp.core_ty == Inorder) { + if (coredynp.pipeline_stages > 6) + num_piperegs = per_stage_vector * coredynp.pipeline_stages; + } + else // OOO + { + if (coredynp.pipeline_stages > 12) + num_piperegs = per_stage_vector * coredynp.pipeline_stages; + } + } +} + +FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, + enum FU_type fu_type_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + fu_type(fu_type_) { + double area_t; //, leakage, gate_leakage; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + clockRate = coredynp.clockRate; + executionTime = coredynp.executionTime; + + // XML_interface=_XML_interface; + uca_org_t result2; + result2 = init_interface(&interface_ip); + if (XML->sys.Embedded) { + if (fu_type == FPU) { + num_fu = coredynp.num_fpus; + // area_t = 8.47*1e6*g_tp.scaling_factor.logic_scaling_co_eff;//this is + // um^2 + area_t = 4.47 * 1e6 * + (g_ip->F_sz_nm * g_ip->F_sz_nm / 90.0 / + 90.0); // this is um^2 The base number + // 4.47 contains both VFP and NEON processing unit, VFP is about 40% and + // NEON is about 60% + if (g_ip->F_sz_nm > 90) + area_t = 4.47 * 1e6 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage( + 5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + // energy = 0.3529/10*1e-9;//this is the energy(nJ) for a FP instruction + // in FPU usually it can have up to 20 cycles. + // base_energy = coredynp.core_ty==Inorder? 0: + // 89e-3*3; //W The base energy of ALU average numbers from Intel 4G and + // 773Mhz (Wattch) base_energy + //*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2); + base_energy = 0; + per_access_energy = + 1.15 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); // g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + // //This is per Hz energy(nJ) + // FPU power from Sandia's processor sizing tech report + FU_height = + (18667 * num_fu) * interface_ip.F_sz_um; // FPU from Sun's data + } + else if (fu_type == ALU) { + num_fu = coredynp.num_alus; + area_t = + 280 * 260 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + // base_energy = coredynp.core_ty==Inorder? + // 0:89e-3; //W The base energy of ALU average numbers from Intel 4G and + // 773Mhz (Wattch) base_energy + //*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2); + base_energy = 0; + per_access_energy = + 1.15 / 3 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ) + FU_height = (6222 * num_fu) * interface_ip.F_sz_um; // integer ALU + } + else if (fu_type == MUL) { + num_fu = coredynp.num_muls; + area_t = + 280 * 260 * 3 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + // base_energy = coredynp.core_ty==Inorder? + // 0:89e-3*2; //W The base energy of ALU average numbers from Intel 4G and + // 773Mhz (Wattch) base_energy + //*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2); + base_energy = 0; + per_access_energy = + 1.15 * 2 / 3 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ), coefficient based on Wattch + FU_height = (9334 * num_fu) * + interface_ip.F_sz_um; // divider/mul from Sun's data + } + else { + cout << "Unknown Functional Unit Type" << endl; + exit(0); + } + per_access_energy *= 0.5; // According to ARM data embedded processor has + // much lower per acc energy + } + else { + if (fu_type == FPU) { + num_fu = coredynp.num_fpus; + // area_t = 8.47*1e6*g_tp.scaling_factor.logic_scaling_co_eff;//this is + // um^2 + area_t = 8.47 * 1e6 * + (g_ip->F_sz_nm * g_ip->F_sz_nm / 90.0 / 90.0); // this is um^2 + if (g_ip->F_sz_nm > 90) + area_t = 8.47 * 1e6 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage( + 5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + // energy = 0.3529/10*1e-9;//this is the energy(nJ) for a FP instruction + // in FPU usually it can have up to 20 cycles. + base_energy = + coredynp.core_ty == Inorder ? 0 : 89e-3 * 3; // W The base energy of + // ALU average numbers + // from Intel 4G and + // 773Mhz (Wattch) + base_energy *= (g_tp.peri_global.Vdd * g_tp.peri_global.Vdd / 1.2 / 1.2); + per_access_energy = + 1.15 * 3 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); // g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + // //This is per op energy(nJ) + FU_height = + (38667 * num_fu) * interface_ip.F_sz_um; // FPU from Sun's data + } + else if (fu_type == ALU) { + num_fu = coredynp.num_alus; + area_t = + 280 * 260 * 2 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + base_energy = coredynp.core_ty == Inorder + ? 0 + : 89e-3; // W The base energy of ALU + // average numbers from Intel + // 4G and 773Mhz (Wattch) + base_energy *= (g_tp.peri_global.Vdd * g_tp.peri_global.Vdd / 1.2 / 1.2); + per_access_energy = + 1.15 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ) + FU_height = (6222 * num_fu) * interface_ip.F_sz_um; // integer ALU + } + else if (fu_type == MUL) { + num_fu = coredynp.num_muls; + area_t = + 280 * 260 * 2 * 3 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; + base_energy = + coredynp.core_ty == Inorder ? 0 : 89e-3 * 2; // W The base energy of + // ALU average numbers + // from Intel 4G and + // 773Mhz (Wattch) + base_energy *= (g_tp.peri_global.Vdd * g_tp.peri_global.Vdd / 1.2 / 1.2); + per_access_energy = + 1.15 * 2 / 1e9 / 4 / 1.3 / 1.3 * g_tp.peri_global.Vdd * + g_tp.peri_global.Vdd * + (g_ip->F_sz_nm / + 90.0); //(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);//0.00649*1e-9; + ////This is per cycle energy(nJ), coefficient based on Wattch + FU_height = (9334 * num_fu) * + interface_ip.F_sz_um; // divider/mul from Sun's data + } + else { + cout << "Unknown Functional Unit Type" << endl; + exit(0); + } + } + // IEXEU, simple ALU and FPU + // double C_ALU, C_EXEU, C_FPU; //Lum Equivalent capacitance of IEXEU and + // FPU. Based on Intel and Sun 90nm process fabracation. + // + // C_ALU = 0.025e-9;//F + // C_EXEU = 0.05e-9; //F + // C_FPU = 0.35e-9;//F + area.set_area(area_t * num_fu); + leakage *= num_fu; + gate_leakage *= num_fu; + double macro_layout_overhead = g_tp.macro_layout_overhead; + // if (!XML->sys.Embedded) + area.set_area(area.get_area() * macro_layout_overhead); +} + +void FunctionalUnit::computeEnergy(bool is_tdp) { + double pppm_t[4] = {1, 1, 1, 1}; + double FU_duty_cycle = 0.; + if (is_tdp) { + set_pppm(pppm_t, 2, 2, 2, 2); // 2 means two source operands needs to be + // passed for each int instruction. + if (fu_type == FPU) { + stats_t.readAc.access = num_fu; + tdp_stats = stats_t; + FU_duty_cycle = coredynp.FPU_duty_cycle; + } + else if (fu_type == ALU) { + stats_t.readAc.access = 1 * num_fu; + tdp_stats = stats_t; + FU_duty_cycle = coredynp.ALU_duty_cycle; + } + else if (fu_type == MUL) { + stats_t.readAc.access = num_fu; + tdp_stats = stats_t; + FU_duty_cycle = coredynp.MUL_duty_cycle; + } + + // power.readOp.dynamic = base_energy/clockRate + + // energy*stats_t.readAc.access; + power.readOp.dynamic = + per_access_energy * stats_t.readAc.access + base_energy / clockRate; + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation * FU_duty_cycle; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + power.readOp.leakage = leakage; + power.readOp.gate_leakage = gate_leakage; + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + } + else { + if (fu_type == FPU) { + stats_t.readAc.access = XML->sys.core[ithCore].fpu_accesses; + rtp_stats = stats_t; + } + else if (fu_type == ALU) { + stats_t.readAc.access = XML->sys.core[ithCore].ialu_accesses; + rtp_stats = stats_t; + } + else if (fu_type == MUL) { + stats_t.readAc.access = XML->sys.core[ithCore].mul_accesses; + rtp_stats = stats_t; + } + + // rt_power.readOp.dynamic = base_energy*executionTime + + // energy*stats_t.readAc.access; + rt_power.readOp.dynamic = + per_access_energy * stats_t.readAc.access + base_energy * executionTime; + double sckRation = g_tp.sckt_co_eff; + rt_power.readOp.dynamic *= sckRation; + rt_power.writeOp.dynamic *= sckRation; + rt_power.searchOp.dynamic *= sckRation; + } +} + +void FunctionalUnit::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + // cout << indent_str_next << "Results Broadcast Bus Area = " << + // bypass->area.get_area() *1e-6 << " mm^2" << endl; + if (is_tdp) { + if (fu_type == FPU) { + cout << indent_str + << "Floating Point Units (FPUs) (Count: " << coredynp.num_fpus + << " ):" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= " << power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + else if (fu_type == ALU) { + cout << indent_str << "Integer ALUs (Count: " << coredynp.num_alus + << " ):" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= " << power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + else if (fu_type == MUL) { + cout << indent_str + << "Complex ALUs (Mul/Div) (Count: " << coredynp.num_muls + << " ):" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage + //= " << power.readOp.leakage << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << rt_power.readOp.dynamic / executionTime + << " W" << endl; + cout << endl; + } + } + else { + } +} + +void FunctionalUnit::leakage_feedback(double temperature) { + // Update the temperature and initialize the global interfaces. + interface_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + + uca_org_t init_result = + init_interface(&interface_ip); // init_result is dummy + + // This is part of FunctionalUnit() + double area_t, leakage, gate_leakage; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + + if (fu_type == FPU) { + area_t = 4.47 * 1e6 * + (g_ip->F_sz_nm * g_ip->F_sz_nm / 90.0 / + 90.0); // this is um^2 The base number + if (g_ip->F_sz_nm > 90) + area_t = 4.47 * 1e6 * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(5 * g_tp.min_w_nmos_, + 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + } + else if (fu_type == ALU) { + area_t = + 280 * 260 * 2 * num_fu * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; + } + else if (fu_type == MUL) { + area_t = + 280 * 260 * 2 * 3 * num_fu * + g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2 ALU + MUl + leakage = area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, + 1, inv) * + g_tp.peri_global.Vdd / 2; // unit W + gate_leakage = + area_t * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(20 * g_tp.min_w_nmos_, + 20 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd / 2; + } + else { + cout << "Unknown Functional Unit Type" << endl; + exit(1); + } + + power.readOp.leakage = leakage * num_fu; + power.readOp.gate_leakage = gate_leakage * num_fu; + power.readOp.longer_channel_leakage = + longer_channel_device_reduction(Core_device, coredynp.core_ty) * + power.readOp.leakage; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; +} + +UndiffCore::UndiffCore(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, + const CoreDynParam &dyn_p_, bool exist_, bool embedded_) + : XML(XML_interface), + ithCore(ithCore_), + interface_ip(*interface_ip_), + coredynp(dyn_p_), + core_ty(coredynp.core_ty), + embedded(XML->sys.Embedded), + pipeline_stage(coredynp.pipeline_stages), + num_hthreads(coredynp.num_hthreads), + issue_width(coredynp.issueW), + exist(exist_) +// is_default(_is_default) +{ + if (!exist) + return; + double undifferentiated_core = 0; + double core_tx_density = 0; + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double undifferentiated_core_coe; + // XML_interface=_XML_interface; + uca_org_t result2; + result2 = init_interface(&interface_ip); + + // Compute undifferentiated core area at 90nm. + if (embedded == false) { + // Based on the results of polynomial/log curve fitting based on + // undifferentiated core of Niagara, Niagara2, Merom, Penyrn, Prescott, + // Opteron die measurements + if (core_ty == OOO) { + // undifferentiated_core = (0.0764*pipeline_stage*pipeline_stage + // -2.3685*pipeline_stage + 10.405);//OOO + undifferentiated_core = (3.57 * log(pipeline_stage) - 1.2643) > 0 + ? (3.57 * log(pipeline_stage) - 1.2643) + : 0; + } + else if (core_ty == Inorder) { + // undifferentiated_core = (0.1238*pipeline_stage + 7.2572)*0.9;//inorder + undifferentiated_core = (-2.19 * log(pipeline_stage) + 6.55) > 0 + ? (-2.19 * log(pipeline_stage) + 6.55) + : 0; + } + else { + cout << "invalid core type" << endl; + exit(0); + } + undifferentiated_core *= (1 + logtwo(num_hthreads) * 0.0716); + } + else { + // Based on the results in paper "parametrized processor models" Sandia Labs + if (XML->sys.opt_clockrate) + undifferentiated_core_coe = 0.05; + else + undifferentiated_core_coe = 0; + undifferentiated_core = + (0.4109 * pipeline_stage - 0.776) * undifferentiated_core_coe; + undifferentiated_core *= (1 + logtwo(num_hthreads) * 0.0426); + } + + undifferentiated_core *= g_tp.scaling_factor.logic_scaling_co_eff * + 1e6; // change from mm^2 to um^2 + core_tx_density = g_tp.scaling_factor.core_tx_density; + // undifferentiated_core = 3*1e6; + // undifferentiated_core *= + // g_tp.scaling_factor.logic_scaling_co_eff;//(g_ip->F_sz_um*g_ip->F_sz_um/0.09/0.09)*; + power.readOp.leakage = + undifferentiated_core * + (core_tx_density)*cmos_Isub_leakage( + 5 * g_tp.min_w_nmos_, 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd; // unit W + power.readOp.gate_leakage = + undifferentiated_core * + (core_tx_density)*cmos_Ig_leakage( + 5 * g_tp.min_w_nmos_, 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, + inv) * + g_tp.peri_global.Vdd; + + double long_channel_device_reduction = + longer_channel_device_reduction(Core_device, coredynp.core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; + + area.set_area(undifferentiated_core); + + scktRatio = g_tp.sckt_co_eff; + power.readOp.dynamic *= scktRatio; + power.writeOp.dynamic *= scktRatio; + power.searchOp.dynamic *= scktRatio; + macro_PR_overhead = g_tp.macro_layout_overhead; + area.set_area(area.get_area() * macro_PR_overhead); + + // double vt=g_tp.peri_global.Vth; + // double velocity_index=1.1; + // double c_in=gate_C(g_tp.min_w_nmos_, + // g_tp.min_w_nmos_*pmos_to_nmos_sizing_r , 0.0, false); double + // c_out= drain_C_(g_tp.min_w_nmos_, NCH, 2, 1, g_tp.cell_h_def, false) + + // drain_C_(g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, PCH, 1, 1, + // g_tp.cell_h_def, false) + c_in; double w_nmos=g_tp.min_w_nmos_; + // double w_pmos=g_tp.min_w_nmos_*pmos_to_nmos_sizing_r; + // double i_on_n=1.0; + // double i_on_p=1.0; + // double i_on_n_in=1.0; + // double i_on_p_in=1; + // double vdd=g_tp.peri_global.Vdd; + + // power.readOp.sc=shortcircuit_simple(vt, velocity_index, c_in, + // c_out, w_nmos,w_pmos, i_on_n, i_on_p,i_on_n_in, i_on_p_in, vdd); + // power.readOp.dynamic=c_out*vdd*vdd/2; + + // cout<sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "UndiffCore:" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + // cout << indent_str_next << "Subthreshold Leakage = " << + // power.readOp.leakage <<" W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + // cout << indent_str_next << "Runtime Dynamic = " << + // rt_power.readOp.dynamic/executionTime << " W" << endl; + cout << endl; + } + else { + cout << indent_str << "UndiffCore:" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " << power.readOp.leakage + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + // cout << indent_str_next << "Runtime Dynamic = " << + // rt_power.readOp.dynamic/executionTime << " W" << endl; + cout << endl; + } +} + +inst_decoder::inst_decoder(bool _is_default, + const InputParameter *configure_interface, + int opcode_length_, int num_decoders_, bool x86_, + enum Device_ty device_ty_, enum Core_type core_ty_) + : is_default(_is_default), + opcode_length(opcode_length_), + num_decoders(num_decoders_), + x86(x86_), + device_ty(device_ty_), + core_ty(core_ty_) { + /* + * Instruction decoder is different from n to 2^n decoders + * that are commonly used in row decoders in memory arrays. + * The RISC instruction decoder is typically a very simple device. + * We can decode an instruction by simply + * separating the machine word into small parts using wire slices + * The RISC instruction decoder can be approximate by the n to 2^n decoders, + * although this approximation usually underestimate power since each decoded + * instruction normally has more than 1 active signal. + * + * However, decoding a CISC instruction word is much more difficult + * than the RISC case. A CISC decoder is typically set up as a state machine. + * The machine reads the opcode field to determine + * what type of instruction it is, + * and where the other data values are. + * The instruction word is read in piece by piece, + * and decisions are made at each stage as to + * how the remainder of the instruction word will be read. + * (sequencer and ROM are usually needed) + * An x86 decoder can be even more complex since + * it involve both decoding instructions into u-ops and + * merge u-ops when doing micro-ops fusion. + */ + bool is_dram = false; + double pmos_to_nmos_sizing_r; + double load_nmos_width, load_pmos_width; + double C_driver_load, R_wire_load; + Area cell; + + l_ip = *configure_interface; + local_result = init_interface(&l_ip); + cell.h = g_tp.cell_h_def; + cell.w = g_tp.cell_h_def; + + num_decoder_segments = (int)ceil(opcode_length / 18.0); + if (opcode_length > 18) + opcode_length = 18; + num_decoded_signals = (int)pow(2.0, opcode_length); + pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + load_nmos_width = g_tp.max_w_nmos_ / 2; + load_pmos_width = g_tp.max_w_nmos_ * pmos_to_nmos_sizing_r; + C_driver_load = + 1024 * gate_C(load_nmos_width + load_pmos_width, 0, + is_dram); // TODO: this number 1024 needs to be revisited + R_wire_load = 3000 * l_ip.F_sz_um * g_tp.wire_outside_mat.R_per_um; + + final_dec = new Decoder(num_decoded_signals, false, C_driver_load, + R_wire_load, false /*is_fa*/, false /*is_dram*/, + false /*wl_tr*/, // to use peri device + cell); + + PredecBlk *predec_blk1 = + new PredecBlk(num_decoded_signals, final_dec, + 0, // Assuming predec and dec are back to back + 0, + 1, // Each Predec only drives one final dec + false /*is_dram*/, true); + PredecBlk *predec_blk2 = + new PredecBlk(num_decoded_signals, final_dec, + 0, // Assuming predec and dec are back to back + 0, + 1, // Each Predec only drives one final dec + false /*is_dram*/, false); + + PredecBlkDrv *predec_blk_drv1 = new PredecBlkDrv(0, predec_blk1, false); + PredecBlkDrv *predec_blk_drv2 = new PredecBlkDrv(0, predec_blk2, false); + + pre_dec = new Predec(predec_blk_drv1, predec_blk_drv2); + + double area_decoder = final_dec->area.get_area() * num_decoded_signals * + num_decoder_segments * num_decoders; + // double w_decoder = area_decoder / area.get_h(); + double area_pre_dec = + (predec_blk_drv1->area.get_area() + predec_blk_drv2->area.get_area() + + predec_blk1->area.get_area() + predec_blk2->area.get_area()) * + num_decoder_segments * num_decoders; + area.set_area(area.get_area() + area_decoder + area_pre_dec); + double macro_layout_overhead = g_tp.macro_layout_overhead; + double chip_PR_overhead = g_tp.chip_layout_overhead; + area.set_area(area.get_area() * macro_layout_overhead * chip_PR_overhead); + + inst_decoder_delay_power(); + + double sckRation = g_tp.sckt_co_eff; + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void inst_decoder::inst_decoder_delay_power() { + // double dec_outrisetime; + // double inrisetime = 0, outrisetime; + double pppm_t[4] = {1, 1, 1, 1}; + double squencer_passes = x86 ? 2 : 1; + + // outrisetime = pre_dec->compute_delays(inrisetime); + // dec_outrisetime = final_dec->compute_delays(outrisetime); + set_pppm(pppm_t, squencer_passes * num_decoder_segments, num_decoder_segments, + squencer_passes * num_decoder_segments, num_decoder_segments); + power = power + pre_dec->power * pppm_t; + set_pppm(pppm_t, squencer_passes * num_decoder_segments, + num_decoder_segments * num_decoded_signals, + num_decoder_segments * num_decoded_signals, + squencer_passes * num_decoder_segments); + power = power + final_dec->power * pppm_t; +} +void inst_decoder::leakage_feedback(double temperature) { + l_ip.temp = (unsigned int)round(temperature / 10.0) * 10; + uca_org_t init_result = init_interface(&l_ip); // init_result is dummy + + final_dec->leakage_feedback(temperature); + pre_dec->leakage_feedback(temperature); + + double pppm_t[4] = {1, 1, 1, 1}; + double squencer_passes = x86 ? 2 : 1; + + set_pppm(pppm_t, squencer_passes * num_decoder_segments, num_decoder_segments, + squencer_passes * num_decoder_segments, num_decoder_segments); + power = pre_dec->power * pppm_t; + + set_pppm(pppm_t, squencer_passes * num_decoder_segments, + num_decoder_segments * num_decoded_signals, + num_decoder_segments * num_decoded_signals, + squencer_passes * num_decoder_segments); + power = power + final_dec->power * pppm_t; + + double sckRation = g_tp.sckt_co_eff; + + power.readOp.dynamic *= sckRation; + power.writeOp.dynamic *= sckRation; + power.searchOp.dynamic *= sckRation; + + double long_channel_device_reduction = + longer_channel_device_reduction(device_ty, core_ty); + power.readOp.longer_channel_leakage = + power.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power.readOp.power_gated_leakage = power.readOp.leakage * pg_reduction; + power.readOp.power_gated_with_long_channel_leakage = + power.readOp.power_gated_leakage * long_channel_device_reduction; +} + +inst_decoder::~inst_decoder() { + local_result.cleanup(); + + delete final_dec; + + delete pre_dec->blk1; + delete pre_dec->blk2; + delete pre_dec->drv1; + delete pre_dec->drv2; + delete pre_dec; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/logic.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/logic.h new file mode 100644 index 0000000000..10b4f7bc9a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/logic.h @@ -0,0 +1,231 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#ifndef LOGIC_H_ +#define LOGIC_H_ + +#include +#include +#include +#include +#include "XML_Parse.h" +#include "arch_const.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/cacti_interface.h" +#include "cacti/component.h" +#include "cacti/const.h" +#include "cacti/decoder.h" +#include "cacti/parameter.h" + +using namespace std; +using namespace cacti; + +class selection_logic : public Component { + public: + selection_logic( + bool _is_default, int win_entries_, int issue_width_, + const InputParameter *configure_interface, + enum Device_ty device_ty_ = Core_device, + enum Core_type core_ty_ = Inorder); //, const ParseXML *_XML_interface); + bool is_default; + InputParameter l_ip; + uca_org_t local_result; + const ParseXML *XML_interface; + int win_entries; + int issue_width; + int num_threads; + enum Device_ty device_ty; + enum Core_type core_ty; + + void selection_power(); + void leakage_feedback(double temperature); // TODO +}; + +class dep_resource_conflict_check : public Component { + public: + dep_resource_conflict_check(const InputParameter *configure_interface, + const CoreDynParam &dyn_p_, int compare_bits_, + bool _is_default = true); + InputParameter l_ip; + uca_org_t local_result; + double WNORn, WNORp, Wevalinvp, Wevalinvn, Wcompn, Wcompp, Wcomppreequ; + CoreDynParam coredynp; + int compare_bits; + bool is_default; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + + void conflict_check_power(); + double compare_cap(); + ~dep_resource_conflict_check() { local_result.cleanup(); } + + void leakage_feedback(double temperature); +}; + +class inst_decoder : public Component { + public: + inst_decoder(bool _is_default, const InputParameter *configure_interface, + int opcode_length_, int num_decoders_, bool x86_, + enum Device_ty device_ty_ = Core_device, + enum Core_type core_ty_ = Inorder); + inst_decoder(); + bool is_default; + int opcode_length; + int num_decoders; + bool x86; + int num_decoder_segments; + int num_decoded_signals; + InputParameter l_ip; + uca_org_t local_result; + enum Device_ty device_ty; + enum Core_type core_ty; + + cacti::Decoder *final_dec; + Predec *pre_dec; + + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + void inst_decoder_delay_power(); + ~inst_decoder(); + void leakage_feedback(double temperature); +}; + +class DFFCell : public Component { + public: + DFFCell(bool _is_dram, double _WdecNANDn, double _WdecNANDp, + double _cell_load, const InputParameter *configure_interface); + InputParameter l_ip; + bool is_dram; + double cell_load; + double WdecNANDn; + double WdecNANDp; + double clock_cap; + int model; + int n_switch; + int n_keep_1; + int n_keep_0; + int n_clock; + powerDef e_switch; + powerDef e_keep_1; + powerDef e_keep_0; + powerDef e_clock; + + double fpfp_node_cap(unsigned int fan_in, unsigned int fan_out); + void compute_DFF_cell(void); +}; + +class Pipeline : public Component { + public: + Pipeline(const InputParameter *configure_interface, + const CoreDynParam &dyn_p_, enum Device_ty device_ty_ = Core_device, + bool _is_core_pipeline = true, bool _is_default = true); + InputParameter l_ip; + uca_org_t local_result; + CoreDynParam coredynp; + enum Device_ty device_ty; + bool is_core_pipeline, is_default; + double num_piperegs; + // int pipeline_stages; + // int tot_stage_vector, per_stage_vector; + bool process_ind; + double WNANDn; + double WNANDp; + double load_per_pipeline_stage; + // int Hthread, num_thread, fetchWidth, decodeWidth, issueWidth, + // commitWidth, instruction_length; int PC_width, opcode_length, + // num_arch_reg_tag, data_width,num_phsical_reg_tag, address_width; bool + // thread_clock_gated; bool in_order, multithreaded; + void compute_stage_vector(); + void compute(); + ~Pipeline() { local_result.cleanup(); }; +}; + +// class core_pipeline :public pipeline{ +// public: +// int Hthread, num_thread, fetchWidth, decodeWidth, issueWidth, +// commitWidth, instruction_length; int PC_width, opcode_length, +// num_arch_reg_tag, data_width,num_phsical_reg_tag, address_width; bool +// thread_clock_gated; bool in_order, multithreaded; core_pipeline(bool +//_is_default, const InputParameter *configure_interface); virtual void +// compute_stage_vector(); +// +//}; + +class FunctionalUnit : public Component { + public: + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double FU_height; + double clockRate, executionTime; + double num_fu; + double energy, base_energy, per_access_energy, leakage, gate_leakage; + bool is_default; + enum FU_type fu_type; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + + FunctionalUnit(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + enum FU_type fu_type); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + void leakage_feedback(double temperature); +}; + +class UndiffCore : public Component { + public: + UndiffCore(ParseXML *XML_interface, int ithCore_, + InputParameter *interface_ip_, const CoreDynParam &dyn_p_, + bool exist_ = true, bool embedded_ = false); + ParseXML *XML; + int ithCore; + InputParameter interface_ip; + CoreDynParam coredynp; + double clockRate, executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + enum Core_type core_ty; + bool opt_performance, embedded; + double pipeline_stage, num_hthreads, issue_width; + bool is_default; + + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~UndiffCore(){}; + bool exist; +}; +#endif /* LOGIC_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/mcpat.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/mcpat.cc new file mode 100644 index 0000000000..767065ba7c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/mcpat.cc @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "mcpat.h" + +McPAT::McPAT(ParseXML *c) : setting(c) {} + +McPAT::~McPAT() {} + +void McPAT::getPower(Power &power) { + Processor proc(setting); + + proc.compute(); + proc.getPower(&power); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/mcpat.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/mcpat.h new file mode 100644 index 0000000000..9bf58e4be0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/mcpat.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __LIB_MCPAT__ +#define __LIB_MCPAT__ + +#include "XML_Parse.h" +#include "processor.h" + +class McPAT { + private: + ParseXML *setting; + + public: + McPAT(ParseXML *); + ~McPAT(); + + void getPower(Power &); +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/memoryctrl.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/memoryctrl.cc new file mode 100644 index 0000000000..31e09d4ac1 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/memoryctrl.cc @@ -0,0 +1,1019 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#include "memoryctrl.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "basic_components.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +#include "logic.h" + +/* overview of MC models: + * McPAT memory controllers are modeled according to large number of industrial + * data points. The Basic memory controller architecture is base on the Synopsis + * designs (DesignWare DDR2/DDR3-Lite memory controllers and DDR2/DDR3-Lite + * protocol controllers) as in Cadence ChipEstimator Tool + * + * An MC has 3 parts as shown in this design. McPAT models both high performance + * MC based on Niagara processor designs and curving and low power MC based on + * data points in Cadence ChipEstimator Tool. + * + * The frontend is modeled analytically, the backend is modeled empirically + * according to DDR2/DDR3-Lite protocol controllers in Cadence ChipEstimator + * Tool The PHY is modeled based on "A 100mW 9.6Gb/s Transceiver in 90nm CMOS + * for next-generation memory interfaces ," ISSCC 2006, and A 14mW 6.25Gb/s + * Transceiver in 90nm CMOS for Serial Chip-to-Chip Communication," ISSCC 2007 + * + * In Cadence ChipEstimator Tool there are two types of memory controllers: the + * full memory controllers that includes the frontend as the DesignWare + * DDR2/DDR3-Lite memory controllers and the backend only memory controllers as + * the DDR2/DDR3-Lite protocol controllers (except DesignWare DDR2/DDR3-Lite + * memory controllers, all memory controller IP in Cadence ChipEstimator Tool + * are backend memory controllers such as DDRC 1600A and DDRC 800A). Thus,to + * some extend the area and power difference between DesignWare DDR2/DDR3-Lite + * memory controllers and DDR2/DDR3-Lite protocol controllers can be an + * estimation to the frontend power and area, which is very close the + * analitically modeled results of the frontend for Niagara2@65nm + * + */ + +MCBackend::MCBackend(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_) + : l_ip(*interface_ip_), mc_type(mc_type_), mcp(mcp_) { + local_result = init_interface(&l_ip); + compute(); +} + +void MCBackend::compute() { + // double max_row_addr_width = 20.0;//Current address 12~18bits + double C_MCB, mc_power, backend_dyn, + backend_gates; //, refresh_period,refresh_freq;//Equivalent per bit Cap + // for backend, + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + double NMOS_sizing, PMOS_sizing; + + if (mc_type == MC) { + if (mcp.type == 0) { + // area = + // (2.2927*log(peakDataTransferRate)-14.504)*memDataWidth/144.0*(l_ip.F_sz_um/0.09); + area.set_area((2.7927 * log(mcp.peakDataTransferRate * 2) - 19.862) / + 2.0 * mcp.dataBusWidth / 128.0 * (l_ip.F_sz_um / 0.09) * + mcp.num_channels * 1e6); // um^2 + // assuming the approximately same scaling factor as seen in processors. + // C_MCB=0.2/1.3/1.3/266/64/0.09*g_ip.F_sz_um;//based on AMD Geode + // processor which has a very basic mc on chip. C_MCB + // = 1.6/200/1e6/144/1.2/1.2*g_ip.F_sz_um/0.19;//Based on Niagara power + // numbers.The base power (W) is divided by device frequency and vdd and + // scale to target process. mc_power = 0.0291*2;//29.1mW@200MHz @130nm + // From Power Analysis of SystemLevel OnChip Communication Architectures + // by Lahiri et + mc_power = + 4.32 * + 0.1; // 4.32W@1GhzMHz @65nm Cadence ChipEstimator 10% for backend + C_MCB = mc_power / 1e9 / 72 / 1.1 / 1.1 * l_ip.F_sz_um / 0.065; + power_t.readOp.dynamic = + C_MCB * g_tp.peri_global.Vdd * g_tp.peri_global.Vdd * + (mcp.dataBusWidth /*+mcp.addressBusWidth*/); // per access energy in + // memory controller + power_t.readOp.leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + } + else { + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + area.set_area(0.15 * mcp.dataBusWidth / 72.0 * (l_ip.F_sz_um / 0.065) * + (l_ip.F_sz_um / 0.065) * mcp.num_channels * 1e6); // um^2 + backend_dyn = 0.9e-9 / 800e6 * mcp.clockRate / 12800 * + mcp.peakDataTransferRate * mcp.dataBusWidth / 72.0 * + g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / 1.1 * + (l_ip.F_sz_nm / 65.0); // Average on DDR2/3 protocol + // controller and DDRC 1600/800A in + // Cadence ChipEstimate + // Scaling to technology and DIMM feature. The base IP support + // DDR3-1600(PC3 12800) + backend_gates = 50000 * mcp.dataBusWidth / + 64.0; // 50000 is from Cadence ChipEstimator + + power_t.readOp.dynamic = backend_dyn; + power_t.readOp.leakage = + (backend_gates)*cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + (backend_gates)*cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + } + } + else { // skip old model + cout << "Unknown memory controllers" << endl; + exit(0); + area.set_area(0.243 * mcp.dataBusWidth / + 8); // area based on Cadence ChipEstimator for 8bit bus + // mc_power = 4.32*0.1;//4.32W@1GhzMHz @65nm Cadence ChipEstimator 10% for + // backend + C_MCB = mc_power / 1e9 / 72 / 1.1 / 1.1 * l_ip.F_sz_um / 0.065; + power_t.readOp.leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.dynamic *= 1.2; + power_t.readOp.leakage *= 1.2; + power_t.readOp.gate_leakage *= 1.2; + // flash controller has about 20% more backend power since BCH ECC in flash + // is complex and power hungry + } + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void MCBackend::computeEnergy(bool is_tdp) { + // backend uses internal data buswidth + if (is_tdp) { + // init stats for Peak + stats_t.readAc.access = 0.5 * mcp.num_channels; + stats_t.writeAc.access = 0.5 * mcp.num_channels; + tdp_stats = stats_t; + } + else { + // init stats for runtime power (RTP) + stats_t.readAc.access = mcp.reads; + stats_t.writeAc.access = mcp.writes; + tdp_stats = stats_t; + } + if (is_tdp) { + power = power_t; + power.readOp.dynamic = (stats_t.readAc.access + stats_t.writeAc.access) * + power_t.readOp.dynamic; + } + else { + rt_power.readOp.dynamic = (stats_t.readAc.access + stats_t.writeAc.access) * + mcp.llcBlockSize * 8.0 / mcp.dataBusWidth * + power_t.readOp.dynamic; + rt_power = rt_power + power_t * pppm_lkg; + rt_power.readOp.dynamic = + rt_power.readOp.dynamic + power.readOp.dynamic * 0.1 * mcp.clockRate * + mcp.num_mcs * mcp.executionTime; + // Assume 10% of peak power is consumed by routine job including memory + // refreshing and scrubbing + } +} + +MCPHY::MCPHY(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_) + : l_ip(*interface_ip_), mc_type(mc_type_), mcp(mcp_) { + local_result = init_interface(&l_ip); + compute(); +} + +void MCPHY::compute() { + // PHY uses internal data buswidth but the actuall off-chip datawidth is + // 64bits + ecc + double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); + /* + * according to "A 100mW 9.6Gb/s Transceiver in 90nm CMOS for next-generation + * memory interfaces ," ISSCC 2006; From Cadence ChipEstimator for normal I/O + * around 0.4~0.8 mW/Gb/s + */ + double power_per_gb_per_s; + // double phy_dyn; + double phy_gates; + double NMOS_sizing; + double PMOS_sizing; + + if (mc_type == MC) { + if (mcp.type == 0) { + power_per_gb_per_s = mcp.LVDS ? 0.01 : 0.04; + // Based on die photos from Niagara 1 and 2. + // TODO merge this into undifferentiated core.PHY only achieves square + // root of the ideal scaling. area = + // (6.4323*log(peakDataTransferRate)-34.76)*memDataWidth/128.0*(l_ip.F_sz_um/0.09); + area.set_area((6.4323 * log(mcp.peakDataTransferRate * 2) - 48.134) * + mcp.dataBusWidth / 128.0 * (l_ip.F_sz_um / 0.09) * + mcp.num_channels * 1e6 / 2); // TODO:/2 + // This is from curve fitting based on Niagara 1 and 2's PHY die photo. + // This is power not energy, 10mw/Gb/s @90nm for each channel and scaling + // down power.readOp.dynamic = 0.02*memAccesses*llcBlocksize*8;//change + // from Bytes to bits. + power_t.readOp.dynamic = power_per_gb_per_s * sqrt(l_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * + g_tp.peri_global.Vdd / 1.2; + power_t.readOp.leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Isub_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + area.get_area() / 2 * (g_tp.scaling_factor.core_tx_density) * + cmos_Ig_leakage(g_tp.min_w_nmos_, + g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r, 1, inv) * + g_tp.peri_global.Vdd; // unit W + } + else { + NMOS_sizing = g_tp.min_w_nmos_; + PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r; + // Designware/synopsis 16bit DDR3 PHY is 1.3mm (WITH IOs) at 40nm for upto + // DDR3 2133 (PC3 17066) + double non_IO_percentage = 0.2; + area.set_area(1.3 * non_IO_percentage / 2133.0e6 * mcp.clockRate / 17066 * + mcp.peakDataTransferRate * mcp.dataBusWidth / 16.0 * + (l_ip.F_sz_um / 0.040) * (l_ip.F_sz_um / 0.040) * + mcp.num_channels * 1e6); // um^2 + phy_gates = 200000 * mcp.dataBusWidth / 64.0; + power_per_gb_per_s = 0.01; + // This is power not energy, 10mw/Gb/s @90nm for each channel and scaling + // down + power_t.readOp.dynamic = power_per_gb_per_s * (l_ip.F_sz_um / 0.09) * + g_tp.peri_global.Vdd / 1.2 * + g_tp.peri_global.Vdd / 1.2; + power_t.readOp.leakage = + (mcp.withPHY ? phy_gates : 0) * + cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + power_t.readOp.gate_leakage = + (mcp.withPHY ? phy_gates : 0) * + cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) * + g_tp.peri_global.Vdd; // unit W + } + } + else { + area.set_area(0.4e6 / 2 * mcp.dataBusWidth / + 8); // area based on Cadence ChipEstimator for 8bit bus + } + + // double phy_factor = (int)ceil(mcp.dataBusWidth/72.0);//Previous phy power + // numbers are based on 72 bit DIMM interface power_t.readOp.dynamic *= + // phy_factor; power_t.readOp.leakage *= phy_factor; + // power_t.readOp.gate_leakage *= phy_factor; + + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + power_t.readOp.longer_channel_leakage = + power_t.readOp.leakage * long_channel_device_reduction; + + double pg_reduction = power_gating_leakage_reduction(false); + power_t.readOp.power_gated_leakage = power_t.readOp.leakage * pg_reduction; + power_t.readOp.power_gated_with_long_channel_leakage = + power_t.readOp.power_gated_leakage * long_channel_device_reduction; +} + +void MCPHY::computeEnergy(bool is_tdp) { + if (is_tdp) { + // init stats for Peak + stats_t.readAc.access = 0.5 * mcp.num_channels; // time share on buses + stats_t.writeAc.access = 0.5 * mcp.num_channels; + tdp_stats = stats_t; + } + else { + // init stats for runtime power (RTP) + stats_t.readAc.access = mcp.reads; + stats_t.writeAc.access = mcp.writes; + tdp_stats = stats_t; + } + + if (is_tdp) { + double data_transfer_unit = (mc_type == MC) ? 72 : 16; /*DIMM data width*/ + power = power_t; + power.readOp.dynamic = + power.readOp.dynamic * + (mcp.peakDataTransferRate * 8 * 1e6 / 1e9 /*change to Gbs*/) * + mcp.dataBusWidth / data_transfer_unit * mcp.num_channels / + mcp.clockRate; + // divide by clock rate is for match the final computation where *clock is + // used + //(stats_t.readAc.access*power_t.readOp.dynamic+ + // stats_t.writeAc.access*power_t.readOp.dynamic); + } + else { + rt_power = power_t; + // rt_power.readOp.dynamic = + // (stats_t.readAc.access*power_t.readOp.dynamic+ + // stats_t.writeAc.access*power_t.readOp.dynamic); + + rt_power.readOp.dynamic = power_t.readOp.dynamic * + (stats_t.readAc.access + stats_t.writeAc.access) * + (mcp.llcBlockSize) * 8 / 1e9 / mcp.executionTime * + (mcp.executionTime); + rt_power.readOp.dynamic = + rt_power.readOp.dynamic + power.readOp.dynamic * 0.1 * mcp.clockRate * + mcp.num_mcs * mcp.executionTime; + } +} + +MCFrontEnd::MCFrontEnd(ParseXML *XML_interface, InputParameter *interface_ip_, + const MCParam &mcp_, enum MemoryCtrl_type mc_type_) + : XML(XML_interface), + interface_ip(*interface_ip_), + mc_type(mc_type_), + mcp(mcp_), + MC_arb(0), + frontendBuffer(0), + readBuffer(0), + writeBuffer(0) { + /* All computations are for a single MC + * + */ + + int tag, data; + bool is_default = true; // indication for default setup + + /* MC frontend engine channels share the same engines but logically + * partitioned For all hardware inside MC. different channels do not share + * resources. + * TODO: add docodeing/mux stage to steer memory requests to different + * channels. + */ + + // memory request reorder buffer + tag = mcp.addressBusWidth + EXTRA_TAG_BITS + mcp.opcodeW; + data = int(ceil((XML->sys.physical_address_width + mcp.opcodeW) / 8.0)); + interface_ip.cache_sz = data * XML->sys.mc.req_window_size_per_channel; + interface_ip.line_sz = data; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / mcp.clockRate; + interface_ip.latency = 1.0 / mcp.clockRate; + interface_ip.is_cache = true; + interface_ip.pure_cam = false; + interface_ip.pure_ram = false; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.mc.memory_channels_per_mc; + interface_ip.num_wr_ports = interface_ip.num_rd_ports; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = XML->sys.mc.memory_channels_per_mc; + frontendBuffer = + new ArrayST(&interface_ip, "MC ReorderBuffer", Uncore_device); + frontendBuffer->area.set_area(frontendBuffer->area.get_area() + + frontendBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + area.set_area(area.get_area() + frontendBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + + // selection and arbitration logic + interface_ip.assoc = + 1; // reset to prevent unnecessary warning messages when init_interface + MC_arb = + new selection_logic(is_default, XML->sys.mc.req_window_size_per_channel, + 1, &interface_ip, Uncore_device); + + // read buffers. + data = (int)ceil(mcp.dataBusWidth / 8.0); // Support key words first + // operation //8 means converting + // bit to Byte + interface_ip.cache_sz = + data * XML->sys.mc.IO_buffer_size_per_channel; //*llcBlockSize; + interface_ip.line_sz = data; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 1; + interface_ip.throughput = 1.0 / mcp.clockRate; + interface_ip.latency = 1.0 / mcp.clockRate; + interface_ip.is_cache = false; + interface_ip.pure_cam = false; + interface_ip.pure_ram = true; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = + 0; // XML->sys.mc.memory_channels_per_mc*2>2?2:XML->sys.mc.memory_channels_per_mc*2; + interface_ip.num_rd_ports = XML->sys.mc.memory_channels_per_mc; + interface_ip.num_wr_ports = interface_ip.num_rd_ports; + interface_ip.num_se_rd_ports = 0; + readBuffer = new ArrayST(&interface_ip, "MC ReadBuffer", Uncore_device); + readBuffer->area.set_area(readBuffer->area.get_area() + + readBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + area.set_area(area.get_area() + readBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + + // write buffer + data = (int)ceil(mcp.dataBusWidth / 8.0); // Support key words first + // operation //8 means converting + // bit to Byte + interface_ip.cache_sz = + data * XML->sys.mc.IO_buffer_size_per_channel; //*llcBlockSize; + interface_ip.line_sz = data; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.access_mode = 0; + interface_ip.throughput = 1.0 / mcp.clockRate; + interface_ip.latency = 1.0 / mcp.clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 0; + interface_ip.num_rd_ports = XML->sys.mc.memory_channels_per_mc; + interface_ip.num_wr_ports = interface_ip.num_rd_ports; + interface_ip.num_se_rd_ports = 0; + writeBuffer = new ArrayST(&interface_ip, "MC writeBuffer", Uncore_device); + writeBuffer->area.set_area(writeBuffer->area.get_area() + + writeBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); + area.set_area(area.get_area() + writeBuffer->local_result.area * + XML->sys.mc.memory_channels_per_mc); +} + +void MCFrontEnd::computeEnergy(bool is_tdp) { + if (is_tdp) { + // init stats for Peak + frontendBuffer->stats_t.readAc.access = + frontendBuffer->l_ip.num_search_ports; + frontendBuffer->stats_t.writeAc.access = frontendBuffer->l_ip.num_wr_ports; + frontendBuffer->tdp_stats = frontendBuffer->stats_t; + + readBuffer->stats_t.readAc.access = + readBuffer->l_ip.num_rd_ports * mcp.frontend_duty_cycle; + readBuffer->stats_t.writeAc.access = + readBuffer->l_ip.num_wr_ports * mcp.frontend_duty_cycle; + readBuffer->tdp_stats = readBuffer->stats_t; + + writeBuffer->stats_t.readAc.access = + writeBuffer->l_ip.num_rd_ports * mcp.frontend_duty_cycle; + writeBuffer->stats_t.writeAc.access = + writeBuffer->l_ip.num_wr_ports * mcp.frontend_duty_cycle; + writeBuffer->tdp_stats = writeBuffer->stats_t; + } + else { + // init stats for runtime power (RTP) + frontendBuffer->stats_t.readAc.access = + XML->sys.mc.memory_reads * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth * + mcp.dataBusWidth / 72; + // For each channel, each memory word need to check the address data to + // achieve best scheduling results. and this need to be done on all + // physical DIMMs in each logical memory DIMM *mcp.dataBusWidth/72 + frontendBuffer->stats_t.writeAc.access = + XML->sys.mc.memory_writes * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth * + mcp.dataBusWidth / 72; + frontendBuffer->rtp_stats = frontendBuffer->stats_t; + + readBuffer->stats_t.readAc.access = + XML->sys.mc.memory_reads * mcp.llcBlockSize * 8.0 / + mcp.dataBusWidth; // support key word first + readBuffer->stats_t.writeAc.access = + XML->sys.mc.memory_reads * mcp.llcBlockSize * 8.0 / + mcp.dataBusWidth; // support key word first + readBuffer->rtp_stats = readBuffer->stats_t; + + writeBuffer->stats_t.readAc.access = + XML->sys.mc.memory_writes * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth; + writeBuffer->stats_t.writeAc.access = + XML->sys.mc.memory_writes * mcp.llcBlockSize * 8.0 / mcp.dataBusWidth; + writeBuffer->rtp_stats = writeBuffer->stats_t; + } + + frontendBuffer->power_t.reset(); + readBuffer->power_t.reset(); + writeBuffer->power_t.reset(); + + // frontendBuffer->power_t.readOp.dynamic += + //(frontendBuffer->stats_t.readAc.access* + // (frontendBuffer->local_result.power.searchOp.dynamic+frontendBuffer->local_result.power.readOp.dynamic)+ + // frontendBuffer->stats_t.writeAc.access*frontendBuffer->local_result.power.writeOp.dynamic); + + frontendBuffer->power_t.readOp.dynamic += + (frontendBuffer->stats_t.readAc.access + + frontendBuffer->stats_t.writeAc.access) * + frontendBuffer->local_result.power.searchOp.dynamic + + frontendBuffer->stats_t.readAc.access * + frontendBuffer->local_result.power.readOp.dynamic + + frontendBuffer->stats_t.writeAc.access * + frontendBuffer->local_result.power.writeOp.dynamic; + + readBuffer->power_t.readOp.dynamic += + (readBuffer->stats_t.readAc.access * + readBuffer->local_result.power.readOp.dynamic + + readBuffer->stats_t.writeAc.access * + readBuffer->local_result.power.writeOp.dynamic); + writeBuffer->power_t.readOp.dynamic += + (writeBuffer->stats_t.readAc.access * + writeBuffer->local_result.power.readOp.dynamic + + writeBuffer->stats_t.writeAc.access * + writeBuffer->local_result.power.writeOp.dynamic); + + if (is_tdp) { + power = power + frontendBuffer->power_t + readBuffer->power_t + + writeBuffer->power_t + + (frontendBuffer->local_result.power + + readBuffer->local_result.power + writeBuffer->local_result.power) * + pppm_lkg; + } + else { + rt_power = + rt_power + frontendBuffer->power_t + readBuffer->power_t + + writeBuffer->power_t + + (frontendBuffer->local_result.power + readBuffer->local_result.power + + writeBuffer->local_result.power) * + pppm_lkg; + rt_power.readOp.dynamic = + rt_power.readOp.dynamic + power.readOp.dynamic * 0.1 * mcp.clockRate * + mcp.num_mcs * mcp.executionTime; + } +} + +void MCFrontEnd::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << indent_str << "Front End ROB:" << endl; + cout << indent_str_next + << "Area = " << frontendBuffer->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << frontendBuffer->power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << frontendBuffer->power.readOp.leakage + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? frontendBuffer->power.readOp + .power_gated_with_long_channel_leakage + : frontendBuffer->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << frontendBuffer->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << frontendBuffer->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + + cout << endl; + cout << indent_str << "Read Buffer:" << endl; + cout << indent_str_next << "Area = " << readBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << readBuffer->power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << readBuffer->power.readOp.leakage + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? readBuffer->power.readOp + .power_gated_with_long_channel_leakage + : readBuffer->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << readBuffer->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << readBuffer->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + cout << indent_str << "Write Buffer:" << endl; + cout << indent_str_next << "Area = " << writeBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << writeBuffer->power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << writeBuffer->power.readOp.leakage + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? writeBuffer->power.readOp + .power_gated_with_long_channel_leakage + : writeBuffer->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << writeBuffer->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << writeBuffer->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + } + else { + cout << indent_str << "Front End ROB:" << endl; + cout << indent_str_next + << "Area = " << frontendBuffer->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << frontendBuffer->rt_power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << frontendBuffer->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << frontendBuffer->rt_power.readOp.gate_leakage + << " W" << endl; + cout << endl; + cout << indent_str << "Read Buffer:" << endl; + cout << indent_str_next << "Area = " << readBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << readBuffer->rt_power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << readBuffer->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << readBuffer->rt_power.readOp.gate_leakage + << " W" << endl; + cout << endl; + cout << indent_str << "Write Buffer:" << endl; + cout << indent_str_next << "Area = " << writeBuffer->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << writeBuffer->rt_power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next + << "Subthreshold Leakage = " << writeBuffer->rt_power.readOp.leakage + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << writeBuffer->rt_power.readOp.gate_leakage + << " W" << endl; + } +} + +MemoryController::MemoryController(ParseXML *XML_interface, + InputParameter *interface_ip_, + enum MemoryCtrl_type mc_type_) + : XML(XML_interface), + interface_ip(*interface_ip_), + mc_type(mc_type_), + frontend(0), + transecEngine(0), + PHY(0), + pipeLogic(0) { + /* All computations are for a single MC + * + */ + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + interface_ip.wt = Global; + set_mc_param(); + frontend = new MCFrontEnd(XML, &interface_ip, mcp, mc_type); + area.set_area(area.get_area() + frontend->area.get_area()); + transecEngine = new MCBackend(&interface_ip, mcp, mc_type); + area.set_area(area.get_area() + transecEngine->area.get_area()); + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + PHY = new MCPHY(&interface_ip, mcp, mc_type); + area.set_area(area.get_area() + PHY->area.get_area()); + } + //+++++++++Transaction engine +++++++++++++++++ ////TODO needs better numbers, + // Run the RTL code from OpenSparc. + // transecEngine.initialize(&interface_ip); + // transecEngine.peakDataTransferRate = XML->sys.mem.peak_transfer_rate; + // transecEngine.memDataWidth = dataBusWidth; + // transecEngine.memRank = XML->sys.mem.number_ranks; + // //transecEngine.memAccesses=XML->sys.mc.memory_accesses; + // //transecEngine.llcBlocksize=llcBlockSize; + // transecEngine.compute(); + // transecEngine.area.set_area(XML->sys.mc.memory_channels_per_mc*transecEngine.area.get_area()) + // ; area.set_area(area.get_area()+ transecEngine.area.get_area()); + // ///cout<<"area="<sys.mem.peak_transfer_rate; + // PHY.memDataWidth = dataBusWidth; + // //PHY.memAccesses=PHY.peakDataTransferRate;//this is the max power + // //PHY.llcBlocksize=llcBlockSize; + // PHY.compute(); + // PHY.area.set_area(XML->sys.mc.memory_channels_per_mc*PHY.area.get_area()) + // ; area.set_area(area.get_area()+ PHY.area.get_area()); + /// cout<<"area="<sys.core[0].opcode_width + dataBusWidth; pipeLogic = new + // pipeline(is_default, &interface_ip); + // //pipeLogic.init_pipeline(is_default, &interface_ip); + // pipeLogic->compute_pipeline(); + // area.set_area(area.get_area()+ pipeLogic->area.get_area()*1e-6); + // area.set_area((area.get_area()+mc_area*1e-6)*1.1);//placement and routing + // overhead + // + // + //// //clock + //// clockNetwork.init_wire_external(is_default, &interface_ip); + //// clockNetwork.clk_area =area*1.1;//10% of placement overhead. + /// rule of thumb / clockNetwork.end_wiring_level =5;//toplevel metal / + /// clockNetwork.start_wiring_level =5;//toplevel metal / + /// clockNetwork.num_regs = pipeLogic.tot_stage_vector; / + /// clockNetwork.optimize_wire(); +} +void MemoryController::computeEnergy(bool is_tdp) { + frontend->computeEnergy(is_tdp); + transecEngine->computeEnergy(is_tdp); + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + PHY->computeEnergy(is_tdp); + } + if (is_tdp) { + power = power + frontend->power + transecEngine->power; + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + power = power + PHY->power; + } + } + else { + rt_power = rt_power + frontend->rt_power + transecEngine->rt_power; + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + rt_power = rt_power + PHY->rt_power; + } + } +} + +void MemoryController::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << "Memory Controller:" << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str + << "Runtime Dynamic = " << rt_power.readOp.dynamic / mcp.executionTime + << " W" << endl; + cout << endl; + cout << indent_str << "Front End Engine:" << endl; + cout << indent_str_next << "Area = " << frontend->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << frontend->power.readOp.dynamic * mcp.clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? frontend->power.readOp.longer_channel_leakage + : frontend->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout + << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? frontend->power.readOp.power_gated_with_long_channel_leakage + : frontend->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << frontend->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << frontend->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + if (plevel > 2) { + frontend->displayEnergy(indent + 4, is_tdp); + } + cout << indent_str << "Transaction Engine:" << endl; + cout << indent_str_next + << "Area = " << transecEngine->area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next << "Peak Dynamic = " + << transecEngine->power.readOp.dynamic * mcp.clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? transecEngine->power.readOp.longer_channel_leakage + : transecEngine->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel ? transecEngine->power.readOp + .power_gated_with_long_channel_leakage + : transecEngine->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << transecEngine->power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << transecEngine->rt_power.readOp.dynamic / mcp.executionTime << " W" + << endl; + cout << endl; + if (mcp.type == 0 || (mcp.type == 1 && mcp.withPHY)) { + cout << indent_str << "PHY:" << endl; + cout << indent_str_next << "Area = " << PHY->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next + << "Peak Dynamic = " << PHY->power.readOp.dynamic * mcp.clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? PHY->power.readOp.longer_channel_leakage + : PHY->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? PHY->power.readOp.power_gated_with_long_channel_leakage + : PHY->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << PHY->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << PHY->rt_power.readOp.dynamic / mcp.executionTime << " W" << endl; + cout << endl; + } + } + else { + cout << "Memory Controller:" << endl; + cout << indent_str_next << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << power.readOp.dynamic * mcp.clockRate << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " << power.readOp.leakage + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " << power.readOp.gate_leakage + << " W" << endl; + cout << endl; + } +} + +void MemoryController::set_mc_param() { + if (mc_type == MC) { + mcp.clockRate = XML->sys.mc.mc_clock * 2; // DDR double pumped + mcp.clockRate *= 1e6; + mcp.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + + mcp.llcBlockSize = int(ceil(XML->sys.mc.llc_line_length / 8.0)) + + XML->sys.mc.llc_line_length; // ecc overhead + mcp.dataBusWidth = + int(ceil(XML->sys.mc.databus_width / 8.0)) + XML->sys.mc.databus_width; + mcp.addressBusWidth = int(ceil( + XML->sys.mc.addressbus_width)); // XML->sys.physical_address_width; + mcp.opcodeW = 16; + mcp.num_mcs = XML->sys.mc.number_mcs; + mcp.num_channels = XML->sys.mc.memory_channels_per_mc; + mcp.reads = XML->sys.mc.memory_reads; + mcp.writes = XML->sys.mc.memory_writes; + //+++++++++Transaction engine +++++++++++++++++ ////TODO needs better + // numbers, Run the RTL code from OpenSparc. + mcp.peakDataTransferRate = XML->sys.mc.peak_transfer_rate; + mcp.memRank = XML->sys.mc.number_ranks; + //++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs better numbers + // PHY.memAccesses=PHY.peakDataTransferRate;//this is the max power + // PHY.llcBlocksize=llcBlockSize; + mcp.frontend_duty_cycle = 0.5; // for max power, the actual off-chip links + // is bidirectional but time shared + mcp.LVDS = XML->sys.mc.LVDS; + mcp.type = XML->sys.mc.type; + mcp.withPHY = XML->sys.mc.withPHY; + + if (XML->sys.mc.vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.mc.vdd; + interface_ip.lop_Vdd = XML->sys.mc.vdd; + interface_ip.lstp_Vdd = XML->sys.mc.vdd; + } + if (XML->sys.mc.power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.mc.power_gating_vcc; + } + } + // else if (mc_type==FLASHC) + // { + // mcp.clockRate =XML->sys.flashc.mc_clock*2;//DDR double + // pumped mcp.clockRate *= 1e6; + // mcp.executionTime = + // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6); + // + // mcp.llcBlockSize + //=int(ceil(XML->sys.flashc.llc_line_length/8.0))+XML->sys.flashc.llc_line_length;//ecc + // overhead mcp.dataBusWidth + //=int(ceil(XML->sys.flashc.databus_width/8.0)) + + // XML->sys.flashc.databus_width; mcp.addressBusWidth + //=int(ceil(XML->sys.flashc.addressbus_width));//XML->sys.physical_address_width; + // mcp.opcodeW =16; + // mcp.num_mcs = XML->sys.flashc.number_mcs; + // mcp.num_channels = XML->sys.flashc.memory_channels_per_mc; + // mcp.reads = XML->sys.flashc.memory_reads; + // mcp.writes = XML->sys.flashc.memory_writes; + // //+++++++++Transaction engine +++++++++++++++++ ////TODO needs + // better numbers, Run the RTL code from OpenSparc. + // mcp.peakDataTransferRate = XML->sys.flashc.peak_transfer_rate; + // mcp.memRank = XML->sys.flashc.number_ranks; + // //++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs + // better numbers + // //PHY.memAccesses=PHY.peakDataTransferRate;//this is the max + // power + // //PHY.llcBlocksize=llcBlockSize; + // mcp.frontend_duty_cycle = 0.5;//for max power, the actual + // off-chip links is bidirectional but time shared mcp.LVDS = + // XML->sys.flashc.LVDS; mcp.type = XML->sys.flashc.type; + // } + else { + cout << "Unknown memory controller type: neither DRAM controller nor Flash " + "controller" + << endl; + exit(0); + } +} + +MCFrontEnd ::~MCFrontEnd() { + if (MC_arb) { + delete MC_arb; + MC_arb = 0; + } + if (frontendBuffer) { + delete frontendBuffer; + frontendBuffer = 0; + } + if (readBuffer) { + delete readBuffer; + readBuffer = 0; + } + if (writeBuffer) { + delete writeBuffer; + writeBuffer = 0; + } +} + +MemoryController ::~MemoryController() { + if (frontend) { + delete frontend; + frontend = 0; + } + if (transecEngine) { + delete transecEngine; + transecEngine = 0; + } + if (PHY) { + delete PHY; + PHY = 0; + } + if (pipeLogic) { + delete pipeLogic; + pipeLogic = 0; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/memoryctrl.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/memoryctrl.h new file mode 100644 index 0000000000..c2fbb922e2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/memoryctrl.h @@ -0,0 +1,118 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef MEMORYCTRL_H_ +#define MEMORYCTRL_H_ + +#include "XML_Parse.h" +#include "cacti/parameter.h" +//#include "io.h" +#include "array.h" +//#include "Undifferentiated_Core_Area.h" +#include +#include "basic_components.h" +#include "logic.h" +using namespace cacti; + +class MCBackend : public Component { + public: + InputParameter l_ip; + uca_org_t local_result; + enum MemoryCtrl_type mc_type; + MCParam mcp; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + MCBackend(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_); + void compute(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MCBackend(){}; +}; + +class MCPHY : public Component { + public: + InputParameter l_ip; + uca_org_t local_result; + enum MemoryCtrl_type mc_type; + MCParam mcp; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + MCPHY(InputParameter *interface_ip_, const MCParam &mcp_, + enum MemoryCtrl_type mc_type_); + void compute(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MCPHY(){}; +}; + +class MCFrontEnd : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + enum MemoryCtrl_type mc_type; + MCParam mcp; + selection_logic *MC_arb; + ArrayST *frontendBuffer; + ArrayST *readBuffer; + ArrayST *writeBuffer; + + MCFrontEnd(ParseXML *XML_interface, InputParameter *interface_ip_, + const MCParam &mcp_, enum MemoryCtrl_type mc_type_); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MCFrontEnd(); +}; + +class MemoryController : public Component { + public: + ParseXML *XML; + InputParameter interface_ip; + enum MemoryCtrl_type mc_type; + MCParam mcp; + MCFrontEnd *frontend; + MCBackend *transecEngine; + MCPHY *PHY; + Pipeline *pipeLogic; + + // clock_network clockNetwork; + MemoryController(ParseXML *XML_interface, InputParameter *interface_ip_, + enum MemoryCtrl_type mc_type_); + void set_mc_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + ~MemoryController(); +}; +#endif /* MEMORYCTRL_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/noc.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/noc.cc new file mode 100644 index 0000000000..f5a8bf2c66 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/noc.cc @@ -0,0 +1,530 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "noc.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" + +NoC::NoC(ParseXML *XML_interface, int ithNoC_, InputParameter *interface_ip_, + double M_traffic_pattern_, double link_len_) + : XML(XML_interface), + ithNoC(ithNoC_), + interface_ip(*interface_ip_), + router(0), + link_bus(0), + link_bus_exist(false), + router_exist(false), + M_traffic_pattern(M_traffic_pattern_) { + /* + * initialize, compute and optimize individual components. + */ + + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 1; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + } + set_noc_param(); + local_result = init_interface(&interface_ip); + scktRatio = g_tp.sckt_co_eff; + + if (nocdynp.type) { /* + * if NOC compute router, router links must be computed + * separately and called from external since total chip + * area must be known first + */ + init_router(); + } + else { + init_link_bus(link_len_); // if bus compute bus + } + + // //clock power + // clockNetwork.init_wire_external(is_default, &interface_ip); + // clockNetwork.clk_area =area*1.1;//10% of placement overhead. + // rule of thumb clockNetwork.end_wiring_level =5;//toplevel metal + // clockNetwork.start_wiring_level =5;//toplevel metal + // clockNetwork.num_regs = corepipe.tot_stage_vector; + // clockNetwork.optimize_wire(); +} + +void NoC::init_router() { + router = new Router( + nocdynp.flit_size, + nocdynp.virtual_channel_per_port * nocdynp.input_buffer_entries_per_vc, + nocdynp.virtual_channel_per_port, &(g_tp.peri_global), + nocdynp.input_ports, nocdynp.output_ports, M_traffic_pattern); + // router->print_router(); + area.set_area(area.get_area() + + router->area.get_area() * nocdynp.total_nodes); + + double long_channel_device_reduction = + longer_channel_device_reduction(Uncore_device); + double pg_reduction_retain = power_gating_leakage_reduction( + false); // state retaining array structure; + double pg_reduction_nonretain = power_gating_leakage_reduction( + false); // non-state-retaining array structure; + + router->power.readOp.longer_channel_leakage = + router->power.readOp.leakage * long_channel_device_reduction; + router->buffer.power.readOp.longer_channel_leakage = + router->buffer.power.readOp.leakage * long_channel_device_reduction; + router->crossbar.power.readOp.longer_channel_leakage = + router->crossbar.power.readOp.leakage * long_channel_device_reduction; + router->arbiter.power.readOp.longer_channel_leakage = + router->arbiter.power.readOp.leakage * long_channel_device_reduction; + + router->buffer.power.readOp.power_gated_leakage = + router->buffer.power.readOp.leakage * + pg_reduction_retain; // TODO: this is a simplified version; should use + // the power_gated_leakage generated in buff + router->crossbar.power.readOp.power_gated_leakage = + router->crossbar.power.readOp.leakage * pg_reduction_nonretain; + router->arbiter.power.readOp.power_gated_leakage = + router->arbiter.power.readOp.leakage * pg_reduction_nonretain; + router->power.readOp.power_gated_leakage = + router->buffer.power.readOp.power_gated_leakage + + router->crossbar.power.readOp.power_gated_leakage + + router->arbiter.power.readOp.power_gated_leakage; + + router->buffer.power.readOp.power_gated_with_long_channel_leakage = + router->buffer.power.readOp.power_gated_leakage * + long_channel_device_reduction; // TODO: this is a simplified version; + // should use the power_gated_leakage + // generated in buff + router->crossbar.power.readOp.power_gated_with_long_channel_leakage = + router->crossbar.power.readOp.power_gated_leakage * + long_channel_device_reduction; + router->arbiter.power.readOp.power_gated_with_long_channel_leakage = + router->arbiter.power.readOp.power_gated_leakage * + long_channel_device_reduction; + router->power.readOp.power_gated_with_long_channel_leakage = + router->buffer.power.readOp.power_gated_with_long_channel_leakage + + router->crossbar.power.readOp.power_gated_with_long_channel_leakage + + router->arbiter.power.readOp.power_gated_with_long_channel_leakage; + + router_exist = true; +} + +void NoC ::init_link_bus(double link_len_) { + // if (nocdynp.min_ports==1 ) + if (nocdynp.type) + link_name = "Links"; + else + link_name = "Bus"; + + link_len = link_len_; + assert(link_len > 0); + + interface_ip.throughput = nocdynp.link_throughput / nocdynp.clockRate; + interface_ip.latency = nocdynp.link_latency / nocdynp.clockRate; + + link_len /= (nocdynp.horizontal_nodes + nocdynp.vertical_nodes) / 2; + + if (nocdynp.total_nodes > 1) + link_len /= 2; // All links are shared by neighbors + link_bus = new interconnect(name, Uncore_device, 1, 1, nocdynp.flit_size, + link_len, &interface_ip, 3, true /*pipelinable*/, + nocdynp.route_over_perc); + + link_bus_tot_per_Router.area.set_area( + link_bus_tot_per_Router.area.get_area() + + link_bus->area.get_area() * nocdynp.global_linked_ports); + + area.set_area(area.get_area() + + link_bus_tot_per_Router.area.get_area() * nocdynp.total_nodes); + link_bus_exist = true; +} +void NoC::computeEnergy(bool is_tdp) { + // power_point_product_masks + double pppm_t[4] = {1, 1, 1, 1}; + double M = nocdynp.duty_cycle; + if (is_tdp) { + // init stats for TDP + stats_t.readAc.access = M; + tdp_stats = stats_t; + if (router_exist) { + set_pppm(pppm_t, 1 * M, 1, 1, 1); // reset traffic pattern + router->power = router->power * pppm_t; + set_pppm(pppm_t, nocdynp.total_nodes, nocdynp.total_nodes, + nocdynp.total_nodes, nocdynp.total_nodes); + power = power + router->power * pppm_t; + } + if (link_bus_exist) { + if (nocdynp.type) + set_pppm(pppm_t, 1 * M_traffic_pattern * M * (nocdynp.min_ports - 1), + nocdynp.global_linked_ports, nocdynp.global_linked_ports, + nocdynp.global_linked_ports); + // reset traffic pattern; local port do not have router links + else + set_pppm(pppm_t, 1 * M_traffic_pattern * M * (nocdynp.min_ports), + nocdynp.global_linked_ports, nocdynp.global_linked_ports, + nocdynp.global_linked_ports); // reset traffic pattern + + link_bus_tot_per_Router.power = link_bus->power * pppm_t; + + set_pppm(pppm_t, nocdynp.total_nodes, nocdynp.total_nodes, + nocdynp.total_nodes, nocdynp.total_nodes); + power = power + link_bus_tot_per_Router.power * pppm_t; + } + } + else { + // init stats for runtime power (RTP) + stats_t.readAc.access = XML->sys.NoC[ithNoC].total_accesses; + rtp_stats = stats_t; + set_pppm(pppm_t, 1, 0, 0, 0); + if (router_exist) { + router->buffer.rt_power.readOp.dynamic = + (router->buffer.power.readOp.dynamic + + router->buffer.power.writeOp.dynamic) * + rtp_stats.readAc.access; + router->crossbar.rt_power.readOp.dynamic = + router->crossbar.power.readOp.dynamic * rtp_stats.readAc.access; + router->arbiter.rt_power.readOp.dynamic = + router->arbiter.power.readOp.dynamic * rtp_stats.readAc.access; + + router->rt_power = + router->rt_power + + (router->buffer.rt_power + router->crossbar.rt_power + + router->arbiter.rt_power) * + pppm_t + + router->power * pppm_lkg; // TDP power must be calculated first! + rt_power = rt_power + router->rt_power; + } + if (link_bus_exist) { + set_pppm(pppm_t, rtp_stats.readAc.access, 1, 1, rtp_stats.readAc.access); + link_bus->rt_power = link_bus->power * pppm_t; + rt_power = rt_power + link_bus->rt_power; + } + } +} + +void NoC::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + double M = M_traffic_pattern * nocdynp.duty_cycle; + /*only router as a whole has been applied the M_traffic_pattern(0.6 by + * default) factor in router.cc; When power of crossbars, arbiters, etc need + * to be displayed, the M_traffic_pattern factor need to be applied together + * with McPAT's extra traffic pattern. + * */ + if (is_tdp) { + cout << name << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * nocdynp.clockRate + << " W" << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (power.readOp.power_gated_leakage * + (long_channel + ? power.readOp.longer_channel_leakage / power.readOp.leakage + : 1)) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " + << rt_power.readOp.dynamic / nocdynp.executionTime << " W" << endl; + cout << endl; + + if (router_exist) { + cout << indent_str << "Router: " << endl; + cout << indent_str_next << "Area = " << router->area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << router->power.readOp.dynamic * nocdynp.clockRate << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? router->power.readOp.longer_channel_leakage + : router->power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout + << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->power.readOp.power_gated_with_long_channel_leakage + : router->power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << router->power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next << "Runtime Dynamic = " + << router->rt_power.readOp.dynamic / nocdynp.executionTime << " W" + << endl; + cout << endl; + if (plevel > 2) { + cout << indent_str << indent_str << "Virtual Channel Buffer:" << endl; + cout << indent_str << indent_str_next << "Area = " + << router->buffer.area.get_area() * 1e-6 * nocdynp.input_ports + << " mm^2" << endl; + cout << indent_str << indent_str_next << "Peak Dynamic = " + << (router->buffer.power.readOp.dynamic + + router->buffer.power.writeOp.dynamic) * + nocdynp.min_ports * M * nocdynp.clockRate + << " W" << endl; + cout << indent_str << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? router->buffer.power.readOp.longer_channel_leakage * + nocdynp.input_ports + : router->buffer.power.readOp.leakage * + nocdynp.input_ports) + << " W" << endl; + if (power_gating) + cout << indent_str << indent_str_next + << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->buffer.power.readOp + .power_gated_with_long_channel_leakage + : router->buffer.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << indent_str_next << "Gate Leakage = " + << router->buffer.power.readOp.gate_leakage * nocdynp.input_ports + << " W" << endl; + cout << indent_str << indent_str_next << "Runtime Dynamic = " + << router->buffer.rt_power.readOp.dynamic / nocdynp.executionTime + << " W" << endl; + cout << endl; + cout << indent_str << indent_str << "Crossbar:" << endl; + cout << indent_str << indent_str_next + << "Area = " << router->crossbar.area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << indent_str_next << "Peak Dynamic = " + << router->crossbar.power.readOp.dynamic * nocdynp.clockRate * + nocdynp.min_ports * M + << " W" << endl; + cout << indent_str << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? router->crossbar.power.readOp.longer_channel_leakage + : router->crossbar.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << indent_str_next + << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->crossbar.power.readOp + .power_gated_with_long_channel_leakage + : router->crossbar.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << indent_str_next + << "Gate Leakage = " << router->crossbar.power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << indent_str_next << "Runtime Dynamic = " + << router->crossbar.rt_power.readOp.dynamic / nocdynp.executionTime + << " W" << endl; + cout << endl; + cout << indent_str << indent_str << "Arbiter:" << endl; + cout << indent_str << indent_str_next << "Peak Dynamic = " + << router->arbiter.power.readOp.dynamic * nocdynp.clockRate * + nocdynp.min_ports * M + << " W" << endl; + cout << indent_str << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? router->arbiter.power.readOp.longer_channel_leakage + : router->arbiter.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << indent_str_next + << "Subthreshold Leakage with power gating = " + << (long_channel + ? router->arbiter.power.readOp + .power_gated_with_long_channel_leakage + : router->arbiter.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << indent_str_next + << "Gate Leakage = " << router->arbiter.power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << indent_str_next << "Runtime Dynamic = " + << router->arbiter.rt_power.readOp.dynamic / nocdynp.executionTime + << " W" << endl; + cout << endl; + } + } + if (link_bus_exist) { + cout << indent_str << (nocdynp.type ? "Per Router " : "") << link_name + << ": " << endl; + cout << indent_str_next + << "Area = " << link_bus_tot_per_Router.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " + << link_bus_tot_per_Router.power.readOp.dynamic * nocdynp.clockRate + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? link_bus_tot_per_Router.power.readOp.longer_channel_leakage + : link_bus_tot_per_Router.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? link_bus_tot_per_Router.power.readOp + .power_gated_with_long_channel_leakage + : link_bus_tot_per_Router.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next << "Gate Leakage = " + << link_bus_tot_per_Router.power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next << "Runtime Dynamic = " + << link_bus->rt_power.readOp.dynamic / nocdynp.executionTime << " W" + << endl; + cout << endl; + } + } + else { + // cout << indent_str_next << "Instruction Fetch Unit Peak + // Dynamic + //= + //" + //<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Subthreshold + // Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl; + // cout << indent_str_next << "Instruction Fetch Unit Gate + // Leakage + //= + //" + //<< ifu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Peak Dynamic = " << + // lsu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Load Store Unit Subthreshold Leakage = " << + // lsu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Load Store Unit Gate Leakage = " << + // lsu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Peak Dynamic = " << + // mmu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Memory Management Unit Subthreshold Leakage = " + // << mmu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Memory Management Unit Gate Leakage = " << + // mmu->rt_power.readOp.gate_leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Peak Dynamic = " << + // exu->rt_power.readOp.dynamic*clockRate << " W" << endl; + // cout + // << indent_str_next << "Execution Unit Subthreshold Leakage = " << + // exu->rt_power.readOp.leakage << " W" << endl; cout << + // indent_str_next << "Execution Unit Gate Leakage = " << + // exu->rt_power.readOp.gate_leakage << " W" << endl; + } +} + +void NoC::set_noc_param() { + nocdynp.type = XML->sys.NoC[ithNoC].type; + nocdynp.clockRate = XML->sys.NoC[ithNoC].clockrate; + nocdynp.clockRate *= 1e6; + nocdynp.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + + nocdynp.flit_size = XML->sys.NoC[ithNoC].flit_bits; + if (nocdynp.type) { + nocdynp.input_ports = XML->sys.NoC[ithNoC].input_ports; + nocdynp.output_ports = XML->sys.NoC[ithNoC].output_ports; // later minus 1 + nocdynp.min_ports = min(nocdynp.input_ports, nocdynp.output_ports); + nocdynp.global_linked_ports = + (nocdynp.input_ports - 1) + (nocdynp.output_ports - 1); + /* + * Except local i/o ports, all ports needs links( global_linked_ports); + * However only min_ports can be fully active simultaneously + * since the fewer number of ports (input or output ) is the bottleneck. + */ + } + else { + nocdynp.input_ports = 1; + nocdynp.output_ports = 1; + nocdynp.min_ports = min(nocdynp.input_ports, nocdynp.output_ports); + nocdynp.global_linked_ports = 1; + } + + nocdynp.virtual_channel_per_port = + XML->sys.NoC[ithNoC].virtual_channel_per_port; + nocdynp.input_buffer_entries_per_vc = + XML->sys.NoC[ithNoC].input_buffer_entries_per_vc; + + nocdynp.horizontal_nodes = XML->sys.NoC[ithNoC].horizontal_nodes; + nocdynp.vertical_nodes = XML->sys.NoC[ithNoC].vertical_nodes; + nocdynp.total_nodes = nocdynp.horizontal_nodes * nocdynp.vertical_nodes; + nocdynp.duty_cycle = XML->sys.NoC[ithNoC].duty_cycle; + nocdynp.has_global_link = XML->sys.NoC[ithNoC].has_global_link; + nocdynp.link_throughput = XML->sys.NoC[ithNoC].link_throughput; + nocdynp.link_latency = XML->sys.NoC[ithNoC].link_latency; + nocdynp.chip_coverage = XML->sys.NoC[ithNoC].chip_coverage; + nocdynp.route_over_perc = XML->sys.NoC[ithNoC].route_over_perc; + + assert(nocdynp.chip_coverage <= 1); + assert(nocdynp.route_over_perc <= 1); + + if (nocdynp.type) + name = "NOC"; + else + name = "BUSES"; + + if (XML->sys.NoC[ithNoC].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.NoC[ithNoC].vdd; + interface_ip.lop_Vdd = XML->sys.NoC[ithNoC].vdd; + interface_ip.lstp_Vdd = XML->sys.NoC[ithNoC].vdd; + } + + if (XML->sys.NoC[ithNoC].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = XML->sys.NoC[ithNoC].power_gating_vcc; + } +} + +NoC ::~NoC() { + if (router) { + delete router; + router = 0; + } + if (link_bus) { + delete link_bus; + link_bus = 0; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/noc.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/noc.h new file mode 100644 index 0000000000..3cf23e8312 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/noc.h @@ -0,0 +1,77 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef NOC_H_ +#define NOC_H_ +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/parameter.h" +#include "cacti/router.h" +#include "interconnect.h" +#include "logic.h" +using namespace cacti; + +class NoC : public Component { + public: + ParseXML *XML; + int ithNoC; + InputParameter interface_ip; + double link_len; + double executionTime; + double scktRatio, chip_PR_overhead, macro_PR_overhead; + Router *router; + interconnect *link_bus; + NoCParam nocdynp; + uca_org_t local_result; + statsDef tdp_stats; + statsDef rtp_stats; + statsDef stats_t; + powerDef power_t; + Component link_bus_tot_per_Router; + bool link_bus_exist; + bool router_exist; + string name, link_name; + double M_traffic_pattern; + NoC(ParseXML *XML_interface, int ithNoC_, InputParameter *interface_ip_, + double M_traffic_pattern_ = 0.6, double link_len_ = 0); + void set_noc_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + void init_link_bus(double link_len_); + void init_router(); + void computeEnergy_link_bus(bool is_tdp = true); + void displayEnergy_link_bus(uint32_t indent = 0, int plevel = 100, + bool is_tdp = true); + ~NoC(); +}; + +#endif /* NOC_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/processor.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/processor.cc new file mode 100644 index 0000000000..1a0310d49e --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/processor.cc @@ -0,0 +1,1188 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#include "processor.h" +#include +#include +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "array.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/parameter.h" +#include "version.h" + +Processor::Processor(ParseXML *XML_interface) + : XML(XML_interface), // TODO: using one global copy may have problems. + mc(0), + niu(0), + pcie(0), + flashcontroller(0) { + /* + * placement and routing overhead is 10%, core scales worse than cache 40% is + * accumulated from 90 to 22nm There is no point to have heterogeneous memory + * controller on chip, thus McPAT only support homogeneous memory + * controllers. + */ + int i; + set_proc_param(); + if (procdynp.homoCore) + numCore = procdynp.numCore == 0 ? 0 : 1; + else + numCore = procdynp.numCore; + + if (procdynp.homoL2) + numL2 = procdynp.numL2 == 0 ? 0 : 1; + else + numL2 = procdynp.numL2; + + if (XML->sys.Private_L2 && numCore != numL2) { + cout << "Number of private L2 does not match number of cores" << endl; + exit(0); + } + + if (procdynp.homoL3) + numL3 = procdynp.numL3 == 0 ? 0 : 1; + else + numL3 = procdynp.numL3; + + if (procdynp.homoNOC) + numNOC = procdynp.numNOC == 0 ? 0 : 1; + else + numNOC = procdynp.numNOC; + + // if (!procdynp.homoNOC) + // { + // cout<<"Current McPAT does not support heterogeneous NOC"<area.get_area() * procdynp.numCore); + area.set_area( + area.get_area() + + core.area.get_area()); // placement and routing overhead is + // 10%, core scales worse than cache + // 40% is accumulated from 90 to 22nm + } + else { + core.area.set_area(core.area.get_area() + cores[i]->area.get_area()); + area.set_area(area.get_area() + + cores[i]->area.get_area()); // placement and routing + // overhead is 10%, core scales + // worse than cache 40% is + // accumulated from 90 to 22nm + } + } + + if (!XML->sys.Private_L2) { + if (numL2 > 0) + for (i = 0; i < numL2; i++) { + l2array.push_back(new SharedCache(XML, i, &interface_ip)); + if (procdynp.homoL2) { + l2.area.set_area(l2.area.get_area() + + l2array[i]->area.get_area() * procdynp.numL2); + area.set_area(area.get_area() + + l2.area.get_area()); // placement and routing overhead + // is 10%, l2 scales worse than + // cache 40% is accumulated from + // 90 to 22nm + } + else { + l2.area.set_area(l2.area.get_area() + l2array[i]->area.get_area()); + area.set_area( + area.get_area() + + l2array[i]->area.get_area()); // placement and routing + // overhead is 10%, l2 + // scales worse than cache + // 40% is accumulated from + // 90 to 22nm + } + } + } + + if (numL3 > 0) + for (i = 0; i < numL3; i++) { + l3array.push_back(new SharedCache(XML, i, &interface_ip, L3)); + if (procdynp.homoL3) { + l3.area.set_area(l3.area.get_area() + + l3array[i]->area.get_area() * procdynp.numL3); + area.set_area( + area.get_area() + + l3.area.get_area()); // placement and routing overhead is + // 10%, l3 scales worse than cache + // 40% is accumulated from 90 to 22nm + } + else { + l3.area.set_area(l3.area.get_area() + l3array[i]->area.get_area()); + area.set_area(area.get_area() + + l3array[i]->area.get_area()); // placement and routing + // overhead is 10%, l3 + // scales worse than cache + // 40% is accumulated from + // 90 to 22nm + } + } + if (numL1Dir > 0) + for (i = 0; i < numL1Dir; i++) { + l1dirarray.push_back(new SharedCache(XML, i, &interface_ip, L1Directory)); + if (procdynp.homoL1Dir) { + l1dir.area.set_area(l1dir.area.get_area() + + l1dirarray[i]->area.get_area() * procdynp.numL1Dir); + area.set_area(area.get_area() + + l1dir.area.get_area()); // placement and routing overhead + // is 10%, l1dir scales worse + // than cache 40% is accumulated + // from 90 to 22nm + power = power + l1dir.power; + rt_power = rt_power + l1dir.rt_power; + } + else { + l1dir.area.set_area(l1dir.area.get_area() + + l1dirarray[i]->area.get_area()); + area.set_area(area.get_area() + l1dirarray[i]->area.get_area()); + } + } + + if (numL2Dir > 0) + for (i = 0; i < numL2Dir; i++) { + l2dirarray.push_back(new SharedCache(XML, i, &interface_ip, L2Directory)); + if (procdynp.homoL2Dir) { + l2dir.area.set_area(l2dir.area.get_area() + + l2dirarray[i]->area.get_area() * procdynp.numL2Dir); + area.set_area(area.get_area() + + l2dir.area.get_area()); // placement and routing overhead + // is 10%, l2dir scales worse + // than cache 40% is accumulated + // from 90 to 22nm + } + else { + l2dir.area.set_area(l2dir.area.get_area() + + l2dirarray[i]->area.get_area()); + area.set_area(area.get_area() + l2dirarray[i]->area.get_area()); + } + } + + if (XML->sys.mc.number_mcs > 0 && XML->sys.mc.memory_channels_per_mc > 0) { + mc = new MemoryController(XML, &interface_ip, MC); + mcs.area.set_area(mcs.area.get_area() + + mc->area.get_area() * XML->sys.mc.number_mcs); + area.set_area(area.get_area() + + mc->area.get_area() * XML->sys.mc.number_mcs); + } + + if (XML->sys.flashc.number_mcs > 0) // flash controller + { + flashcontroller = new FlashController(XML, &interface_ip); + double number_fcs = flashcontroller->fcp.num_mcs; + flashcontrollers.area.set_area(flashcontrollers.area.get_area() + + flashcontroller->area.get_area() * + number_fcs); + area.set_area(area.get_area() + flashcontrollers.area.get_area()); + } + + if (XML->sys.niu.number_units > 0) { + niu = new NIUController(XML, &interface_ip); + nius.area.set_area(nius.area.get_area() + + niu->area.get_area() * XML->sys.niu.number_units); + area.set_area(area.get_area() + + niu->area.get_area() * XML->sys.niu.number_units); + } + + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + pcie = new PCIeController(XML, &interface_ip); + pcies.area.set_area(pcies.area.get_area() + + pcie->area.get_area() * XML->sys.pcie.number_units); + area.set_area(area.get_area() + + pcie->area.get_area() * XML->sys.pcie.number_units); + } + + if (numNOC > 0) { + for (i = 0; i < numNOC; i++) { + if (XML->sys.NoC[i].type) { // First add up area of routers if NoC is + // used + nocs.push_back(new NoC(XML, i, &interface_ip, 1)); + if (procdynp.homoNOC) { + noc.area.set_area(noc.area.get_area() + + nocs[i]->area.get_area() * procdynp.numNOC); + area.set_area(area.get_area() + noc.area.get_area()); + } + else { + noc.area.set_area(noc.area.get_area() + nocs[i]->area.get_area()); + area.set_area(area.get_area() + nocs[i]->area.get_area()); + } + } + else { // Bus based interconnect + nocs.push_back( + new NoC(XML, i, &interface_ip, 1, + sqrt(area.get_area() * XML->sys.NoC[i].chip_coverage))); + if (procdynp.homoNOC) { + noc.area.set_area(noc.area.get_area() + + nocs[i]->area.get_area() * procdynp.numNOC); + area.set_area(area.get_area() + noc.area.get_area()); + } + else { + noc.area.set_area(noc.area.get_area() + nocs[i]->area.get_area()); + area.set_area(area.get_area() + nocs[i]->area.get_area()); + } + } + } + + /* + * Compute global links associated with each NOC, if any. This must be done + * at the end (even after the NOC router part) since the total chip area + * must be obtain to decide the link routing + */ + for (i = 0; i < numNOC; i++) { + if (nocs[i]->nocdynp.has_global_link && XML->sys.NoC[i].type) { + nocs[i]->init_link_bus( + sqrt(area.get_area() * + XML->sys.NoC[i].chip_coverage)); // compute global links + if (procdynp.homoNOC) { + noc.area.set_area(noc.area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes * procdynp.numNOC); + area.set_area(area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes * procdynp.numNOC); + } + else { + noc.area.set_area(noc.area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes); + area.set_area(area.get_area() + + nocs[i]->link_bus_tot_per_Router.area.get_area() * + nocs[i]->nocdynp.total_nodes); + } + } + } + } + + // //clock power + // globalClock.init_wire_external(is_default, &interface_ip); + // globalClock.clk_area =area*1e6; //change it from mm^2 to um^2 + // globalClock.end_wiring_level =5;//toplevel metal + // globalClock.start_wiring_level =5;//toplevel metal + // globalClock.l_ip.with_clock_grid=false;//global clock does not drive local + // final nodes globalClock.optimize_wire(); +} + +void Processor::compute() { + int i; + double pppm_t[4] = {1, 1, 1, 1}; + + for (i = 0; i < numCore; i++) { + cores[i]->computeEnergy(); + cores[i]->computeEnergy(false); + if (procdynp.homoCore) { + set_pppm(pppm_t, cores[i]->clockRate * procdynp.numCore, procdynp.numCore, + procdynp.numCore, procdynp.numCore); + core.power = core.power + cores[i]->power * pppm_t; + set_pppm(pppm_t, 1 / cores[i]->executionTime, procdynp.numCore, + procdynp.numCore, procdynp.numCore); + core.rt_power = core.rt_power + cores[i]->rt_power * pppm_t; + power = power + core.power; + rt_power = rt_power + core.rt_power; + } + else { + set_pppm(pppm_t, cores[i]->clockRate, 1, 1, 1); + core.power = core.power + cores[i]->power * pppm_t; + power = power + cores[i]->power * pppm_t; + + set_pppm(pppm_t, 1 / cores[i]->executionTime, 1, 1, 1); + core.rt_power = core.rt_power + cores[i]->rt_power * pppm_t; + rt_power = rt_power + cores[i]->rt_power * pppm_t; + } + } + + if (!XML->sys.Private_L2) { + if (numL2 > 0) + for (i = 0; i < numL2; i++) { + l2array[i]->computeEnergy(); + l2array[i]->computeEnergy(false); + if (procdynp.homoL2) { + set_pppm(pppm_t, l2array[i]->cachep.clockRate * procdynp.numL2, + procdynp.numL2, procdynp.numL2, procdynp.numL2); + l2.power = l2.power + l2array[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l2array[i]->cachep.executionTime, procdynp.numL2, + procdynp.numL2, procdynp.numL2); + l2.rt_power = l2.rt_power + l2array[i]->rt_power * pppm_t; + power = power + l2.power; + rt_power = rt_power + l2.rt_power; + } + else { + set_pppm(pppm_t, l2array[i]->cachep.clockRate, 1, 1, 1); + l2.power = l2.power + l2array[i]->power * pppm_t; + power = power + l2array[i]->power * pppm_t; + ; + set_pppm(pppm_t, 1 / l2array[i]->cachep.executionTime, 1, 1, 1); + l2.rt_power = l2.rt_power + l2array[i]->rt_power * pppm_t; + rt_power = rt_power + l2array[i]->rt_power * pppm_t; + } + } + } + + if (numL3 > 0) + for (i = 0; i < numL3; i++) { + l3array[i]->computeEnergy(); + l3array[i]->computeEnergy(false); + if (procdynp.homoL3) { + set_pppm(pppm_t, l3array[i]->cachep.clockRate * procdynp.numL3, + procdynp.numL3, procdynp.numL3, procdynp.numL3); + l3.power = l3.power + l3array[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l3array[i]->cachep.executionTime, procdynp.numL3, + procdynp.numL3, procdynp.numL3); + l3.rt_power = l3.rt_power + l3array[i]->rt_power * pppm_t; + power = power + l3.power; + rt_power = rt_power + l3.rt_power; + } + else { + set_pppm(pppm_t, l3array[i]->cachep.clockRate, 1, 1, 1); + l3.power = l3.power + l3array[i]->power * pppm_t; + power = power + l3array[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l3array[i]->cachep.executionTime, 1, 1, 1); + l3.rt_power = l3.rt_power + l3array[i]->rt_power * pppm_t; + rt_power = rt_power + l3array[i]->rt_power * pppm_t; + } + } + if (numL1Dir > 0) + for (i = 0; i < numL1Dir; i++) { + l1dirarray[i]->computeEnergy(); + l1dirarray[i]->computeEnergy(false); + if (procdynp.homoL1Dir) { + set_pppm(pppm_t, l1dirarray[i]->cachep.clockRate * procdynp.numL1Dir, + procdynp.numL1Dir, procdynp.numL1Dir, procdynp.numL1Dir); + l1dir.power = l1dir.power + l1dirarray[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l1dirarray[i]->cachep.executionTime, + procdynp.numL1Dir, procdynp.numL1Dir, procdynp.numL1Dir); + l1dir.rt_power = l1dir.rt_power + l1dirarray[i]->rt_power * pppm_t; + power = power + l1dir.power; + rt_power = rt_power + l1dir.rt_power; + } + else { + set_pppm(pppm_t, l1dirarray[i]->cachep.clockRate, 1, 1, 1); + l1dir.power = l1dir.power + l1dirarray[i]->power * pppm_t; + power = power + l1dirarray[i]->power; + set_pppm(pppm_t, 1 / l1dirarray[i]->cachep.executionTime, 1, 1, 1); + l1dir.rt_power = l1dir.rt_power + l1dirarray[i]->rt_power * pppm_t; + rt_power = rt_power + l1dirarray[i]->rt_power; + } + } + + if (numL2Dir > 0) + for (i = 0; i < numL2Dir; i++) { + l2dirarray[i]->computeEnergy(); + l2dirarray[i]->computeEnergy(false); + if (procdynp.homoL2Dir) { + set_pppm(pppm_t, l2dirarray[i]->cachep.clockRate * procdynp.numL2Dir, + procdynp.numL2Dir, procdynp.numL2Dir, procdynp.numL2Dir); + l2dir.power = l2dir.power + l2dirarray[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l2dirarray[i]->cachep.executionTime, + procdynp.numL2Dir, procdynp.numL2Dir, procdynp.numL2Dir); + l2dir.rt_power = l2dir.rt_power + l2dirarray[i]->rt_power * pppm_t; + power = power + l2dir.power; + rt_power = rt_power + l2dir.rt_power; + } + else { + set_pppm(pppm_t, l2dirarray[i]->cachep.clockRate, 1, 1, 1); + l2dir.power = l2dir.power + l2dirarray[i]->power * pppm_t; + power = power + l2dirarray[i]->power * pppm_t; + set_pppm(pppm_t, 1 / l2dirarray[i]->cachep.executionTime, 1, 1, 1); + l2dir.rt_power = l2dir.rt_power + l2dirarray[i]->rt_power * pppm_t; + rt_power = rt_power + l2dirarray[i]->rt_power * pppm_t; + } + } + + if (XML->sys.mc.number_mcs > 0 && XML->sys.mc.memory_channels_per_mc > 0) { + mc->computeEnergy(); + mc->computeEnergy(false); + set_pppm(pppm_t, XML->sys.mc.number_mcs * mc->mcp.clockRate, + XML->sys.mc.number_mcs, XML->sys.mc.number_mcs, + XML->sys.mc.number_mcs); + mcs.power = mc->power * pppm_t; + power = power + mcs.power; + set_pppm(pppm_t, 1 / mc->mcp.executionTime, XML->sys.mc.number_mcs, + XML->sys.mc.number_mcs, XML->sys.mc.number_mcs); + mcs.rt_power = mc->rt_power * pppm_t; + rt_power = rt_power + mcs.rt_power; + } + + if (XML->sys.flashc.number_mcs > 0) // flash controller + { + flashcontroller->computeEnergy(); + flashcontroller->computeEnergy(false); + double number_fcs = flashcontroller->fcp.num_mcs; + set_pppm(pppm_t, number_fcs, number_fcs, number_fcs, number_fcs); + flashcontrollers.power = flashcontroller->power * pppm_t; + power = power + flashcontrollers.power; + set_pppm(pppm_t, number_fcs, number_fcs, number_fcs, number_fcs); + flashcontrollers.rt_power = flashcontroller->rt_power * pppm_t; + rt_power = rt_power + flashcontrollers.rt_power; + } + + if (XML->sys.niu.number_units > 0) { + niu->computeEnergy(); + niu->computeEnergy(false); + set_pppm(pppm_t, XML->sys.niu.number_units * niu->niup.clockRate, + XML->sys.niu.number_units, XML->sys.niu.number_units, + XML->sys.niu.number_units); + nius.power = niu->power * pppm_t; + power = power + nius.power; + set_pppm(pppm_t, XML->sys.niu.number_units * niu->niup.clockRate, + XML->sys.niu.number_units, XML->sys.niu.number_units, + XML->sys.niu.number_units); + nius.rt_power = niu->rt_power * pppm_t; + rt_power = rt_power + nius.rt_power; + } + + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + pcie->computeEnergy(); + pcie->computeEnergy(false); + set_pppm(pppm_t, XML->sys.pcie.number_units * pcie->pciep.clockRate, + XML->sys.pcie.number_units, XML->sys.pcie.number_units, + XML->sys.pcie.number_units); + pcies.power = pcie->power * pppm_t; + power = power + pcies.power; + set_pppm(pppm_t, XML->sys.pcie.number_units * pcie->pciep.clockRate, + XML->sys.pcie.number_units, XML->sys.pcie.number_units, + XML->sys.pcie.number_units); + pcies.rt_power = pcie->rt_power * pppm_t; + rt_power = rt_power + pcies.rt_power; + } + + if (numNOC > 0) { + // Compute energy of NoC (w or w/o links) or buses + for (i = 0; i < numNOC; i++) { + nocs[i]->computeEnergy(); + nocs[i]->computeEnergy(false); + if (procdynp.homoNOC) { + set_pppm(pppm_t, procdynp.numNOC * nocs[i]->nocdynp.clockRate, + procdynp.numNOC, procdynp.numNOC, procdynp.numNOC); + noc.power = noc.power + nocs[i]->power * pppm_t; + set_pppm(pppm_t, 1 / nocs[i]->nocdynp.executionTime, procdynp.numNOC, + procdynp.numNOC, procdynp.numNOC); + noc.rt_power = noc.rt_power + nocs[i]->rt_power * pppm_t; + power = power + noc.power; + rt_power = rt_power + noc.rt_power; + } + else { + set_pppm(pppm_t, nocs[i]->nocdynp.clockRate, 1, 1, 1); + noc.power = noc.power + nocs[i]->power * pppm_t; + power = power + nocs[i]->power * pppm_t; + set_pppm(pppm_t, 1 / nocs[i]->nocdynp.executionTime, 1, 1, 1); + noc.rt_power = noc.rt_power + nocs[i]->rt_power * pppm_t; + rt_power = rt_power + nocs[i]->rt_power * pppm_t; + } + } + } + + // //clock power + // globalClock.init_wire_external(is_default, &interface_ip); + // globalClock.clk_area =area*1e6; //change it from mm^2 to um^2 + // globalClock.end_wiring_level =5;//toplevel metal + // globalClock.start_wiring_level =5;//toplevel metal + // globalClock.l_ip.with_clock_grid=false;//global clock does not drive local + // final nodes globalClock.optimize_wire(); +} + +void Processor::getPower(Power *value) { + bool long_channel = XML->sys.longer_channel_device; + + if (value) { + value->core.area = core.area.get_area() * 1e-6; + value->core.peakDynamic = core.power.readOp.dynamic; + value->core.subthresholdLeakage = + long_channel ? core.power.readOp.longer_channel_leakage + : core.power.readOp.leakage; + value->core.gateLeakage = core.power.readOp.gate_leakage; + value->core.runtimeDynamic = core.rt_power.readOp.dynamic; + + if (!XML->sys.Private_L2) { + if (numL2 > 0) { + value->level2.area = l2.area.get_area() * 1e-6; + value->level2.peakDynamic = l2.power.readOp.dynamic; + value->level2.subthresholdLeakage = + long_channel ? l2.power.readOp.longer_channel_leakage + : l2.power.readOp.leakage; + value->level2.gateLeakage = l2.power.readOp.gate_leakage; + value->level2.runtimeDynamic = l2.rt_power.readOp.dynamic; + } + } + + if (numL3 > 0) { + value->level3.area = l3.area.get_area() * 1e-6; + value->level3.peakDynamic = l3.power.readOp.dynamic; + value->level3.subthresholdLeakage = + long_channel ? l3.power.readOp.longer_channel_leakage + : l3.power.readOp.leakage; + value->level3.gateLeakage = l3.power.readOp.gate_leakage; + value->level3.runtimeDynamic = l3.rt_power.readOp.dynamic; + } + } +} + +void Processor::displayDeviceType(int device_type_, uint32_t indent) { + string indent_str(indent, ' '); + + switch (device_type_) { + case 0: + cout << indent_str << "Device Type= " + << "ITRS high performance device type" << endl; + break; + case 1: + cout << indent_str << "Device Type= " + << "ITRS low standby power device type" << endl; + break; + case 2: + cout << indent_str << "Device Type= " + << "ITRS low operating power device type" << endl; + break; + case 3: + cout << indent_str << "Device Type= " + << "LP-DRAM device type" << endl; + break; + case 4: + cout << indent_str << "Device Type= " + << "COMM-DRAM device type" << endl; + break; + default: { + cout << indent_str << "Unknown Device Type" << endl; + exit(0); + } + } +} + +void Processor::displayInterconnectType(int interconnect_type_, + uint32_t indent) { + string indent_str(indent, ' '); + + switch (interconnect_type_) { + case 0: + cout << indent_str << "Interconnect metal projection= " + << "aggressive interconnect technology projection" << endl; + break; + case 1: + cout << indent_str << "Interconnect metal projection= " + << "conservative interconnect technology projection" << endl; + break; + default: { + cout << indent_str << "Unknown Interconnect Projection Type" << endl; + exit(0); + } + } +} + +void Processor::displayEnergy(uint32_t indent, int plevel, bool is_tdp) { + int i; + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + if (is_tdp) { + if (plevel < 5) { + cout + << "\nMcPAT (version " << VER_MAJOR << "." << VER_MINOR << " of " + << VER_UPDATE << ") results (current print level is " << plevel + << ", please increase print level to see the details in components): " + << endl; + } + else { + cout << "\nMcPAT (version " << VER_MAJOR << "." << VER_MINOR << " of " + << VER_UPDATE << ") results (current print level is 5)" << endl; + } + cout << "******************************************************************" + "***********************" + << endl; + cout << indent_str << "Technology " << XML->sys.core_tech_node << " nm" + << endl; + // cout <sys.interconnect_projection_type<sys.interconnect_projection_type, indent); + cout << indent_str << "Core clock Rate(MHz) " << XML->sys.core[0].clock_rate + << endl; + cout << endl; + cout << "******************************************************************" + "***********************" + << endl; + cout << "Processor: " << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str << "Peak Power = " + << power.readOp.dynamic + + (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + + power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << "Total Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + + power.readOp.gate_leakage + << " W" << endl; + cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic + << " W" << endl; + cout << endl; + if (numCore > 0) { + cout << indent_str << "Total Cores: " << XML->sys.number_of_cores + << " cores " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << core.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << core.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? core.power.readOp.longer_channel_leakage + : core.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? core.power.readOp.power_gated_with_long_channel_leakage + : core.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << core.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << core.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (!XML->sys.Private_L2) { + if (numL2 > 0) { + cout << indent_str << "Total L2s: " << endl; + displayDeviceType(XML->sys.L2[0].device_type, indent); + cout << indent_str_next << "Area = " << l2.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l2.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l2.power.readOp.longer_channel_leakage + : l2.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l2.power.readOp.power_gated_with_long_channel_leakage + : l2.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l2.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l2.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + } + if (numL3 > 0) { + cout << indent_str << "Total L3s: " << endl; + displayDeviceType(XML->sys.L3[0].device_type, indent); + cout << indent_str_next << "Area = " << l3.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l3.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l3.power.readOp.longer_channel_leakage + : l3.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l3.power.readOp.power_gated_with_long_channel_leakage + : l3.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l3.power.readOp.gate_leakage << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l3.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (numL1Dir > 0) { + cout << indent_str << "Total First Level Directory: " << endl; + displayDeviceType(XML->sys.L1Directory[0].device_type, indent); + cout << indent_str_next << "Area = " << l1dir.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l1dir.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l1dir.power.readOp.longer_channel_leakage + : l1dir.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l1dir.power.readOp.power_gated_with_long_channel_leakage + : l1dir.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l1dir.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l1dir.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (numL2Dir > 0) { + cout << indent_str << "Total Second Level Directory: " << endl; + displayDeviceType(XML->sys.L1Directory[0].device_type, indent); + cout << indent_str_next << "Area = " << l2dir.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << l2dir.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? l2dir.power.readOp.longer_channel_leakage + : l2dir.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? l2dir.power.readOp.power_gated_with_long_channel_leakage + : l2dir.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << l2dir.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << l2dir.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (numNOC > 0) { + cout << indent_str << "Total NoCs (Network/Bus): " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << noc.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << noc.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? noc.power.readOp.longer_channel_leakage + : noc.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? noc.power.readOp.power_gated_with_long_channel_leakage + : noc.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << noc.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << noc.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (XML->sys.mc.number_mcs > 0 && XML->sys.mc.memory_channels_per_mc > 0) { + cout << indent_str << "Total MCs: " << XML->sys.mc.number_mcs + << " Memory Controllers " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << mcs.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << mcs.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? mcs.power.readOp.longer_channel_leakage + : mcs.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? mcs.power.readOp.power_gated_with_long_channel_leakage + : mcs.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << mcs.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << mcs.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (XML->sys.flashc.number_mcs > 0) { + cout << indent_str + << "Total Flash/SSD Controllers: " << flashcontroller->fcp.num_mcs + << " Flash/SSD Controllers " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next + << "Area = " << flashcontrollers.area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str_next + << "Peak Dynamic = " << flashcontrollers.power.readOp.dynamic << " W" + << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel + ? flashcontrollers.power.readOp.longer_channel_leakage + : flashcontrollers.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? flashcontrollers.power.readOp + .power_gated_with_long_channel_leakage + : flashcontrollers.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << flashcontrollers.power.readOp.gate_leakage + << " W" << endl; + cout << indent_str_next + << "Runtime Dynamic = " << flashcontrollers.rt_power.readOp.dynamic + << " W" << endl; + cout << endl; + } + if (XML->sys.niu.number_units > 0) { + cout << indent_str << "Total NIUs: " << niu->niup.num_units + << " Network Interface Units " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << nius.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << nius.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? nius.power.readOp.longer_channel_leakage + : nius.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? nius.power.readOp.power_gated_with_long_channel_leakage + : nius.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << nius.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << nius.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + cout << indent_str << "Total PCIes: " << pcie->pciep.num_units + << " PCIe Controllers " << endl; + displayDeviceType(XML->sys.device_type, indent); + cout << indent_str_next << "Area = " << pcies.area.get_area() * 1e-6 + << " mm^2" << endl; + cout << indent_str_next << "Peak Dynamic = " << pcies.power.readOp.dynamic + << " W" << endl; + cout << indent_str_next << "Subthreshold Leakage = " + << (long_channel ? pcies.power.readOp.longer_channel_leakage + : pcies.power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str_next << "Subthreshold Leakage with power gating = " + << (long_channel + ? pcies.power.readOp.power_gated_with_long_channel_leakage + : pcies.power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str_next + << "Gate Leakage = " << pcies.power.readOp.gate_leakage << " W" + << endl; + cout << indent_str_next + << "Runtime Dynamic = " << pcies.rt_power.readOp.dynamic << " W" + << endl; + cout << endl; + } + cout << "******************************************************************" + "***********************" + << endl; + if (plevel > 1) { + for (i = 0; i < numCore; i++) { + cores[i]->displayEnergy(indent + 4, plevel, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (!XML->sys.Private_L2) { + for (i = 0; i < numL2; i++) { + l2array[i]->displayEnergy(indent + 4, is_tdp); + cout << "************************************************************" + "*****************************" + << endl; + } + } + for (i = 0; i < numL3; i++) { + l3array[i]->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + for (i = 0; i < numL1Dir; i++) { + l1dirarray[i]->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + for (i = 0; i < numL2Dir; i++) { + l2dirarray[i]->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.mc.number_mcs > 0 && + XML->sys.mc.memory_channels_per_mc > 0) { + mc->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.flashc.number_mcs > 0 && + XML->sys.flashc.memory_channels_per_mc > 0) { + flashcontroller->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.niu.number_units > 0) { + niu->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + if (XML->sys.pcie.number_units > 0 && XML->sys.pcie.num_channels > 0) { + pcie->displayEnergy(indent + 4, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + + for (i = 0; i < numNOC; i++) { + nocs[i]->displayEnergy(indent + 4, plevel, is_tdp); + cout << "**************************************************************" + "***************************" + << endl; + } + } + } + else { + } +} + +void Processor::set_proc_param() { + bool debug = false; + + procdynp.homoCore = bool(debug ? 1 : XML->sys.homogeneous_cores); + procdynp.homoL2 = bool(debug ? 1 : XML->sys.homogeneous_L2s); + procdynp.homoL3 = bool(debug ? 1 : XML->sys.homogeneous_L3s); + procdynp.homoNOC = bool(debug ? 1 : XML->sys.homogeneous_NoCs); + procdynp.homoL1Dir = bool(debug ? 1 : XML->sys.homogeneous_L1Directories); + procdynp.homoL2Dir = bool(debug ? 1 : XML->sys.homogeneous_L2Directories); + + procdynp.numCore = XML->sys.number_of_cores; + procdynp.numL2 = XML->sys.number_of_L2s; + procdynp.numL3 = XML->sys.number_of_L3s; + procdynp.numNOC = XML->sys.number_of_NoCs; + procdynp.numL1Dir = XML->sys.number_of_L1Directories; + procdynp.numL2Dir = XML->sys.number_of_L2Directories; + procdynp.numMC = XML->sys.mc.number_mcs; + procdynp.numMCChannel = XML->sys.mc.memory_channels_per_mc; + + // if (procdynp.numCore<1) + // { + // cout<<" The target processor should at least have one core on + // chip." + //<2) + // { + // cout <<"number of NOCs must be 1 (only global NOCs) or 2 (both global + // and local NOCs)"<sys.device_type; + interface_ip.data_arr_peri_global_tech_type = + debug ? 0 : XML->sys.device_type; + interface_ip.tag_arr_ram_cell_tech_type = debug ? 0 : XML->sys.device_type; + interface_ip.tag_arr_peri_global_tech_type = debug ? 0 : XML->sys.device_type; + + interface_ip.specific_hp_vdd = false; + interface_ip.specific_lop_vdd = false; + interface_ip.specific_lstp_vdd = false; + + interface_ip.specific_vcc_min = false; + + interface_ip.ic_proj_type = debug ? 0 : XML->sys.interconnect_projection_type; + interface_ip.delay_wt = + 100; // Fixed number, make sure timing can be satisfied. + interface_ip.area_wt = 0; // Fixed number, This is used to exhaustive search + // for individual components. + interface_ip.dynamic_power_wt = 100; // Fixed number, This is used to + // exhaustive search for individual + // components. + interface_ip.leakage_power_wt = 0; + interface_ip.cycle_time_wt = 0; + + interface_ip.delay_dev = + 10000; // Fixed number, make sure timing can be satisfied. + interface_ip.area_dev = 10000; // Fixed number, This is used to exhaustive + // search for individual components. + interface_ip.dynamic_power_dev = 10000; // Fixed number, This is used to + // exhaustive search for individual + // components. + interface_ip.leakage_power_dev = 10000; + interface_ip.cycle_time_dev = 10000; + + interface_ip.ed = 2; + interface_ip.burst_len = 1; // parameters are fixed for processor section, + // since memory is processed separately + interface_ip.int_prefetch_w = 1; + interface_ip.page_sz_bits = 0; + interface_ip.temp = debug ? 360 : XML->sys.temperature; + interface_ip.F_sz_nm = + debug ? 90 : XML->sys.core_tech_node; // XML->sys.core_tech_node; + interface_ip.F_sz_um = interface_ip.F_sz_nm / 1000; + + //***********This section of code does not have real meaning, they are just to + // ensure all data will have initial value to prevent errors. They will be + // overridden during each components initialization + interface_ip.cache_sz = 64; + interface_ip.line_sz = 1; + interface_ip.assoc = 1; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8; + interface_ip.specific_tag = 1; + interface_ip.tag_w = 64; + interface_ip.access_mode = 2; + + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + + interface_ip.is_main_mem = false; + interface_ip.rpters_in_htree = true; + interface_ip.ver_htree_wires_over_array = 0; + interface_ip.broadcast_addr_din_over_ver_htrees = 0; + + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 1; + interface_ip.nuca = 0; + interface_ip.nuca_bank_count = 0; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.force_cache_config = false; + interface_ip.power_gating = XML->sys.power_gating; + + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 0; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + } + interface_ip.force_wiretype = false; + interface_ip.print_detail = 1; + interface_ip.add_ecc_b_ = true; +} + +Processor::~Processor() { + while (!cores.empty()) { + delete cores.back(); + cores.pop_back(); + } + while (!l2array.empty()) { + delete l2array.back(); + l2array.pop_back(); + } + while (!l3array.empty()) { + delete l3array.back(); + l3array.pop_back(); + } + while (!nocs.empty()) { + delete nocs.back(); + nocs.pop_back(); + } + while (!l1dirarray.empty()) { + delete l1dirarray.back(); + l1dirarray.pop_back(); + } + while (!l2dirarray.empty()) { + delete l2dirarray.back(); + l2dirarray.pop_back(); + } + if (mc) { + delete mc; + mc = 0; + } + if (niu) { + delete niu; + niu = 0; + } + if (pcie) { + delete pcie; + pcie = 0; + } + if (flashcontroller) { + delete flashcontroller; + flashcontroller = 0; + } +}; diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/processor.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/processor.h new file mode 100644 index 0000000000..1ce5b9410d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/processor.h @@ -0,0 +1,102 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ +#ifndef PROCESSOR_H_ +#define PROCESSOR_H_ + +#include +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/arbiter.h" +#include "cacti/area.h" +#include "cacti/decoder.h" +#include "cacti/parameter.h" +#include "cacti/router.h" +#include "core.h" +#include "iocontrollers.h" +#include "memoryctrl.h" +#include "noc.h" +#include "sharedcache.h" + +struct PowerGroup { + double area; // Unit: mm^2 + double peakDynamic; // Unit: W + double subthresholdLeakage; // Unit: W + double gateLeakage; // Unit: W + double runtimeDynamic; // Unit: W + + PowerGroup() + : area(0.0), + peakDynamic(0.0), + subthresholdLeakage(0.0), + gateLeakage(0.0), + runtimeDynamic(0.0) {} +}; + +struct Power { + PowerGroup core; // Total cores including all per-core elements + PowerGroup level2; + PowerGroup level3; +}; + +using namespace cacti; + +class Processor : public Component { + public: + ParseXML *XML; + vector cores; + vector l2array; + vector l3array; + vector l1dirarray; + vector l2dirarray; + vector nocs; + MemoryController *mc; + NIUController *niu; + PCIeController *pcie; + FlashController *flashcontroller; + InputParameter interface_ip; + ProcParam procdynp; + // wire globalInterconnect; + // clock_network globalClock; + Component core, l2, l3, l1dir, l2dir, noc, mcs, cc, nius, pcies, + flashcontrollers; + int numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir; + Processor(ParseXML *XML_interface); + void compute(); + void set_proc_param(); + void getPower(Power *); + void displayEnergy(uint32_t indent = 0, int plevel = 100, bool is_tdp = true); + void displayDeviceType(int device_type_, uint32_t indent = 0); + void displayInterconnectType(int interconnect_type_, uint32_t indent = 0); + ~Processor(); +}; + +#endif /* PROCESSOR_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/sharedcache.cc b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/sharedcache.cc new file mode 100644 index 0000000000..a847a2f33c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/sharedcache.cc @@ -0,0 +1,1454 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#include "sharedcache.h" +#include +#include +#include +#include +#include +#include "XML_Parse.h" +#include "array.h" +#include "cacti/arbiter.h" +#include "cacti/basic_circuit.h" +#include "cacti/const.h" +#include "cacti/io.h" +#include "cacti/parameter.h" +#include "logic.h" + +SharedCache::SharedCache(ParseXML *XML_interface, int ithCache_, + InputParameter *interface_ip_, + enum cache_level cacheL_) + : XML(XML_interface), + ithCache(ithCache_), + interface_ip(*interface_ip_), + cacheL(cacheL_), + dir_overhead(0) { + int idx; + int tag, data; + // bool is_default; + bool debug; + enum Device_ty device_t; + enum Core_type core_t; + double size, line, assoc, banks; + if (cacheL == L2 && XML->sys.Private_L2) { + device_t = Core_device; + core_t = (enum Core_type)XML->sys.core[ithCache].machine_type; + } + else { + device_t = LLC_device; + core_t = Inorder; + } + + debug = false; + // is_default = true; // indication for default setup + if (XML->sys.Embedded) { + interface_ip.wt = Global_30; + interface_ip.wire_is_mat_type = 0; + interface_ip.wire_os_mat_type = 1; + } + else { + interface_ip.wt = Global; + interface_ip.wire_is_mat_type = 2; + interface_ip.wire_os_mat_type = 2; + } + set_cache_param(); + + // All lower level cache are physically indexed and tagged. + size = cachep.capacity; + line = cachep.blockW; + assoc = cachep.assoc; + banks = cachep.nbanks; + if ((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory)) { + assoc = 0; + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + interface_ip.num_search_ports = 1; + } + else { + idx = debug ? 9 : int(ceil(log2(size / line / assoc))); + tag = debug ? 51 + : XML->sys.physical_address_width - idx - + int(ceil(log2(line))) + EXTRA_TAG_BITS; + interface_ip.num_search_ports = 0; + if (cachep.dir_ty == SBT) { + dir_overhead = + ceil(XML->sys.number_of_cores / 8.0) * 8 / (cachep.blockW * 8); + line = cachep.blockW * (1 + dir_overhead); + size = cachep.capacity * (1 + dir_overhead); + } + } + // if (XML->sys.first_level_dir==2) + // tag += int(XML->sys.domain_size + 5); + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.cache_sz = (int)size; + interface_ip.line_sz = (int)line; + interface_ip.assoc = (int)assoc; + interface_ip.nbanks = (int)banks; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 1; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; // lower level cache usually has one port. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + // interface_ip.force_cache_config =true; + // interface_ip.ndwl = 4; + // interface_ip.ndbl = 8; + // interface_ip.nspd = 1; + // interface_ip.ndcm =1 ; + // interface_ip.ndsam1 =1; + // interface_ip.ndsam2 =1; + unicache.caches = + new ArrayST(&interface_ip, cachep.name + "cache", device_t, true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.caches->local_result.area); + area.set_area(area.get_area() + unicache.caches->local_result.area); + interface_ip.force_cache_config = false; + + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = (XML->sys.physical_address_width) + int(ceil(log2(size / line))) + + unicache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data / 8.0)); // int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = cachep.missb_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.is_cache = true; + interface_ip.pure_ram = false; + interface_ip.pure_cam = false; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; // means cycle time + interface_ip.latency = cachep.latency; // means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + interface_ip.num_search_ports = 1; + unicache.missb = new ArrayST(&interface_ip, cachep.name + "MissB", device_t, + true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.missb->local_result.area); + area.set_area(area.get_area() + unicache.missb->local_result.area); + // fill buffer + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = unicache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data * cachep.fu_size; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + unicache.ifb = new ArrayST(&interface_ip, cachep.name + "FillB", device_t, + true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.ifb->local_result.area); + area.set_area(area.get_area() + unicache.ifb->local_result.area); + // prefetch buffer + tag = XML->sys.physical_address_width + + EXTRA_TAG_BITS; // check with previous entries to decide wthether to + // merge. + data = unicache.caches->l_ip + .line_sz; // separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; // int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = cachep.prefetchb_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + unicache.prefetchb = new ArrayST(&interface_ip, cachep.name + "PrefetchB", + device_t, true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.prefetchb->local_result.area); + area.set_area(area.get_area() + unicache.prefetchb->local_result.area); + // WBB + tag = XML->sys.physical_address_width + EXTRA_TAG_BITS; + data = unicache.caches->l_ip.line_sz; + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = cachep.wbb_size * interface_ip.line_sz; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz * 8 / 2; + interface_ip.access_mode = 0; + interface_ip.throughput = cachep.throughput; + interface_ip.latency = cachep.latency; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + unicache.wbb = + new ArrayST(&interface_ip, cachep.name + "WBB", device_t, true, core_t); + unicache.area.set_area(unicache.area.get_area() + + unicache.wbb->local_result.area); + area.set_area(area.get_area() + unicache.wbb->local_result.area); + } + // //pipeline + // interface_ip.pipeline_stages = + // int(ceil(llCache.caches.local_result.access_time/llCache.caches.local_result.cycle_time)); + // interface_ip.per_stage_vector = llCache.caches.l_ip.out_w + + // llCache.caches.l_ip.tag_w ; pipeLogicCache.init_pipeline(is_default, + // &interface_ip); pipeLogicCache.compute_pipeline(); + + /* + if (!((XML->sys.number_of_dir_levels==1 && XML->sys.first_level_dir ==1) + ||(XML->sys.number_of_dir_levels==1 && + XML->sys.first_level_dir ==2)))//not single level IC and DIC + { + //directory Now assuming one directory per bank, TODO:should change it later + size = XML->sys.L2directory.L2Dir_config[0]; + line = XML->sys.L2directory.L2Dir_config[1]; + assoc = XML->sys.L2directory.L2Dir_config[2]; + banks = XML->sys.L2directory.L2Dir_config[3]; + tag = + debug?51:XML->sys.physical_address_width + EXTRA_TAG_BITS;//TODO: a little bit + over estimate interface_ip.specific_tag = 0; interface_ip.tag_w + = tag; interface_ip.cache_sz = + XML->sys.L2directory.L2Dir_config[0]; interface_ip.line_sz = + XML->sys.L2directory.L2Dir_config[1]; interface_ip.assoc = + XML->sys.L2directory.L2Dir_config[2]; interface_ip.nbanks = + XML->sys.L2directory.L2Dir_config[3]; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = + 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5]; + interface_ip.throughput = + XML->sys.L2directory.L2Dir_config[4]/clockRate; interface_ip.latency + = XML->sys.L2directory.L2Dir_config[5]/clockRate; interface_ip.is_cache + = true; interface_ip.obj_func_dyn_energy = 0; interface_ip.obj_func_dyn_power + = 0; interface_ip.obj_func_leak_power = 0; interface_ip.obj_func_cycle_t = + 1; interface_ip.num_rw_ports = 1;//lower level cache usually has one port. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + + strcpy(directory.caches.name,"L2 Directory"); + directory.caches.init_cache(&interface_ip); + directory.caches.optimize_array(); + directory.area += directory.caches.local_result.area; + //output_data_csv(directory.caches.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; + data = + (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + + directory.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[0]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate;//means cycle time + interface_ip.latency = + XML->sys.L2[ithCache].L2_config[5]/clockRate;//means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.missb.name,"directoryMissB"); + directory.missb.init_cache(&interface_ip); + directory.missb.optimize_array(); + directory.area += directory.missb.local_result.area; + //output_data_csv(directory.missb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data*XML->sys.L2[ithCache].buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz*8; + interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.ifb.name,"directoryFillB"); + directory.ifb.init_cache(&interface_ip); + directory.ifb.optimize_array(); + directory.area += directory.ifb.local_result.area; + //output_data_csv(directory.ifb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries + to decide wthether to merge. + data = + directory.caches.l_ip.line_sz;//separate queue to prevent from cache polution. + interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[2]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.prefetchb.name,"directoryPrefetchB"); + directory.prefetchb.init_cache(&interface_ip); + directory.prefetchb.optimize_array(); + directory.area += directory.prefetchb.local_result.area; + //output_data_csv(directory.prefetchb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[3]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[4]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory.wbb.name,"directoryWBB"); + directory.wbb.init_cache(&interface_ip); + directory.wbb.optimize_array(); + directory.area += directory.wbb.local_result.area; + } + + if (XML->sys.number_of_dir_levels ==2 && XML->sys.first_level_dir==0) + { + //first level directory + size = + XML->sys.L2directory.L2Dir_config[0]*XML->sys.domain_size/128; line + = int(ceil(XML->sys.domain_size/8.0)); assoc = + XML->sys.L2directory.L2Dir_config[2]; banks = + XML->sys.L2directory.L2Dir_config[3]; tag + = debug?51:XML->sys.physical_address_width + EXTRA_TAG_BITS;//TODO: a little + bit over estimate interface_ip.specific_tag = 1; interface_ip.tag_w + = tag; interface_ip.cache_sz = + XML->sys.L2directory.L2Dir_config[0]; interface_ip.line_sz = + XML->sys.L2directory.L2Dir_config[1]; interface_ip.assoc = + XML->sys.L2directory.L2Dir_config[2]; interface_ip.nbanks = + XML->sys.L2directory.L2Dir_config[3]; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = + 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5]; + interface_ip.throughput = + XML->sys.L2directory.L2Dir_config[4]/clockRate; interface_ip.latency + = XML->sys.L2directory.L2Dir_config[5]/clockRate; interface_ip.is_cache + = true; interface_ip.obj_func_dyn_energy = 0; interface_ip.obj_func_dyn_power + = 0; interface_ip.obj_func_leak_power = 0; interface_ip.obj_func_cycle_t = + 1; interface_ip.num_rw_ports = 1;//lower level cache usually has one port. + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + + strcpy(directory1.caches.name,"first level Directory"); + directory1.caches.init_cache(&interface_ip); + directory1.caches.optimize_array(); + directory1.area += directory1.caches.local_result.area; + //output_data_csv(directory.caches.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; + data = + (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + + directory1.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = + int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0)); + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[0]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate;//means cycle time + interface_ip.latency = + XML->sys.L2[ithCache].L2_config[5]/clockRate;//means access time + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.missb.name,"directory1MissB"); + directory1.missb.init_cache(&interface_ip); + directory1.missb.optimize_array(); + directory1.area += directory1.missb.local_result.area; + //output_data_csv(directory.missb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory1.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data)))); + interface_ip.cache_sz = data*XML->sys.L2[ithCache].buffer_sizes[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1; + interface_ip.out_w = interface_ip.line_sz*8; + interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.ifb.name,"directory1FillB"); + directory1.ifb.init_cache(&interface_ip); + directory1.ifb.optimize_array(); + directory1.area += directory1.ifb.local_result.area; + //output_data_csv(directory.ifb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries + to decide wthether to merge. + data = + directory1.caches.l_ip.line_sz;//separate queue to prevent from cache + polution. interface_ip.specific_tag = 1; interface_ip.tag_w + = tag; interface_ip.line_sz = + data;//int(pow(2.0,ceil(log2(data)))); interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[2]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.prefetchb.name,"directory1PrefetchB"); + directory1.prefetchb.init_cache(&interface_ip); + directory1.prefetchb.optimize_array(); + directory1.area += directory1.prefetchb.local_result.area; + //output_data_csv(directory.prefetchb.local_result); + ///cout<<"area="<sys.physical_address_width + EXTRA_TAG_BITS; data + = directory1.caches.l_ip.line_sz; interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.L2[ithCache].buffer_sizes[3]*interface_ip.line_sz; interface_ip.assoc + = 0; interface_ip.nbanks = 1; interface_ip.out_w = + interface_ip.line_sz*8; interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(directory1.wbb.name,"directoryWBB"); + directory1.wbb.init_cache(&interface_ip); + directory1.wbb.optimize_array(); + directory1.area += directory1.wbb.local_result.area; + } + + if (XML->sys.first_level_dir==1)//IC + { + tag = + XML->sys.physical_address_width + EXTRA_TAG_BITS; data + = int(ceil(XML->sys.domain_size/8.0)); interface_ip.specific_tag = 1; + interface_ip.tag_w = tag; + interface_ip.line_sz = data; + interface_ip.cache_sz = + XML->sys.domain_size*data*XML->sys.L2[ithCache].L2_config[0]/XML->sys.L2[ithCache].L2_config[1]; + interface_ip.assoc = 0; + interface_ip.nbanks = 1024; + interface_ip.out_w = interface_ip.line_sz*8; + interface_ip.access_mode = 0; + interface_ip.throughput = + XML->sys.L2[ithCache].L2_config[4]/clockRate; interface_ip.latency + = XML->sys.L2[ithCache].L2_config[5]/clockRate; + interface_ip.obj_func_dyn_energy = 0; + interface_ip.obj_func_dyn_power = 0; + interface_ip.obj_func_leak_power = 0; + interface_ip.obj_func_cycle_t = 1; + interface_ip.num_rw_ports = 1; + interface_ip.num_rd_ports = 0; + interface_ip.num_wr_ports = 0; + interface_ip.num_se_rd_ports = 0; + strcpy(inv_dir.caches.name,"inv_dir"); + inv_dir.caches.init_cache(&interface_ip); + inv_dir.caches.optimize_array(); + inv_dir.area = inv_dir.caches.local_result.area; + + } +*/ + // //pipeline + // interface_ip.pipeline_stages = + // int(ceil(directory.caches.local_result.access_time/directory.caches.local_result.cycle_time)); + // interface_ip.per_stage_vector = directory.caches.l_ip.out_w + + // directory.caches.l_ip.tag_w ; pipeLogicDirectory.init_pipeline(is_default, + // &interface_ip); pipeLogicDirectory.compute_pipeline(); + // + // //clock power + // clockNetwork.init_wire_external(is_default, &interface_ip); + // clockNetwork.clk_area =area*1.1;//10% of placement overhead. + // rule of thumb clockNetwork.end_wiring_level =5;//toplevel metal + // clockNetwork.start_wiring_level =5;//toplevel metal + // clockNetwork.num_regs = pipeLogicCache.tot_stage_vector + + // pipeLogicDirectory.tot_stage_vector; clockNetwork.optimize_wire(); +} + +void SharedCache::computeEnergy(bool is_tdp) { + double homenode_data_access = (cachep.dir_ty == SBT) ? 0.9 : 1.0; + if (is_tdp) { + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + // init stats for Peak + unicache.caches->stats_t.readAc.access = + .67 * unicache.caches->l_ip.num_rw_ports * cachep.duty_cycle * + homenode_data_access; + unicache.caches->stats_t.readAc.miss = 0; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + .33 * unicache.caches->l_ip.num_rw_ports * cachep.duty_cycle * + homenode_data_access; + unicache.caches->stats_t.writeAc.miss = 0; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->tdp_stats = unicache.caches->stats_t; + + if (cachep.dir_ty == SBT) { + homenode_stats_t.readAc.access = + .67 * unicache.caches->l_ip.num_rw_ports * cachep.dir_duty_cycle * + (1 - homenode_data_access); + homenode_stats_t.readAc.miss = 0; + homenode_stats_t.readAc.hit = + homenode_stats_t.readAc.access - homenode_stats_t.readAc.miss; + homenode_stats_t.writeAc.access = + .67 * unicache.caches->l_ip.num_rw_ports * cachep.dir_duty_cycle * + (1 - homenode_data_access); + homenode_stats_t.writeAc.miss = 0; + homenode_stats_t.writeAc.hit = + homenode_stats_t.writeAc.access - homenode_stats_t.writeAc.miss; + homenode_tdp_stats = homenode_stats_t; + } + + unicache.missb->stats_t.readAc.access = + unicache.missb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.missb->stats_t.writeAc.access = + unicache.missb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.missb->tdp_stats = unicache.missb->stats_t; + + unicache.ifb->stats_t.readAc.access = + unicache.ifb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.ifb->stats_t.writeAc.access = + unicache.ifb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.ifb->tdp_stats = unicache.ifb->stats_t; + + unicache.prefetchb->stats_t.readAc.access = + unicache.prefetchb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.prefetchb->stats_t.writeAc.access = + unicache.ifb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.prefetchb->tdp_stats = unicache.prefetchb->stats_t; + + unicache.wbb->stats_t.readAc.access = + unicache.wbb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.wbb->stats_t.writeAc.access = + unicache.wbb->l_ip.num_search_ports * cachep.duty_cycle; + unicache.wbb->tdp_stats = unicache.wbb->stats_t; + } + else { + unicache.caches->stats_t.readAc.access = + unicache.caches->l_ip.num_search_ports * cachep.duty_cycle; + unicache.caches->stats_t.readAc.miss = 0; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = 0; + unicache.caches->stats_t.writeAc.miss = 0; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->tdp_stats = unicache.caches->stats_t; + } + } + else { + // init stats for runtime power (RTP) + if (cacheL == L2) { + unicache.caches->stats_t.readAc.access = + XML->sys.L2[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = XML->sys.L2[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L2[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L2[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + + if (cachep.dir_ty == SBT) { + homenode_rtp_stats.readAc.access = + XML->sys.L2[ithCache].homenode_read_accesses; + homenode_rtp_stats.readAc.miss = + XML->sys.L2[ithCache].homenode_read_misses; + homenode_rtp_stats.readAc.hit = + homenode_rtp_stats.readAc.access - homenode_rtp_stats.readAc.miss; + homenode_rtp_stats.writeAc.access = + XML->sys.L2[ithCache].homenode_write_accesses; + homenode_rtp_stats.writeAc.miss = + XML->sys.L2[ithCache].homenode_write_misses; + homenode_rtp_stats.writeAc.hit = + homenode_rtp_stats.writeAc.access - homenode_rtp_stats.writeAc.miss; + } + } + else if (cacheL == L3) { + unicache.caches->stats_t.readAc.access = + XML->sys.L3[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = XML->sys.L3[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L3[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L3[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + + if (cachep.dir_ty == SBT) { + homenode_rtp_stats.readAc.access = + XML->sys.L3[ithCache].homenode_read_accesses; + homenode_rtp_stats.readAc.miss = + XML->sys.L3[ithCache].homenode_read_misses; + homenode_rtp_stats.readAc.hit = + homenode_rtp_stats.readAc.access - homenode_rtp_stats.readAc.miss; + homenode_rtp_stats.writeAc.access = + XML->sys.L3[ithCache].homenode_write_accesses; + homenode_rtp_stats.writeAc.miss = + XML->sys.L3[ithCache].homenode_write_misses; + homenode_rtp_stats.writeAc.hit = + homenode_rtp_stats.writeAc.access - homenode_rtp_stats.writeAc.miss; + } + } + else if (cacheL == L1Directory) { + unicache.caches->stats_t.readAc.access = + XML->sys.L1Directory[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = + XML->sys.L1Directory[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L1Directory[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L1Directory[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + } + else if (cacheL == L2Directory) { + unicache.caches->stats_t.readAc.access = + XML->sys.L2Directory[ithCache].read_accesses; + unicache.caches->stats_t.readAc.miss = + XML->sys.L2Directory[ithCache].read_misses; + unicache.caches->stats_t.readAc.hit = + unicache.caches->stats_t.readAc.access - + unicache.caches->stats_t.readAc.miss; + unicache.caches->stats_t.writeAc.access = + XML->sys.L2Directory[ithCache].write_accesses; + unicache.caches->stats_t.writeAc.miss = + XML->sys.L2Directory[ithCache].write_misses; + unicache.caches->stats_t.writeAc.hit = + unicache.caches->stats_t.writeAc.access - + unicache.caches->stats_t.writeAc.miss; + unicache.caches->rtp_stats = unicache.caches->stats_t; + } + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && + cacheL == + L2Directory))) { // Assuming write back and write-allocate cache + + unicache.missb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.missb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.missb->rtp_stats = unicache.missb->stats_t; + + unicache.ifb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.ifb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.ifb->rtp_stats = unicache.ifb->stats_t; + + unicache.prefetchb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.prefetchb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.prefetchb->rtp_stats = unicache.prefetchb->stats_t; + + unicache.wbb->stats_t.readAc.access = + unicache.caches->stats_t.writeAc.miss; + unicache.wbb->stats_t.writeAc.access = + unicache.caches->stats_t.writeAc.miss; + if (cachep.dir_ty == SBT) { + unicache.missb->stats_t.readAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->stats_t.writeAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->rtp_stats = unicache.missb->stats_t; + + unicache.missb->stats_t.readAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->stats_t.writeAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.missb->rtp_stats = unicache.missb->stats_t; + + unicache.ifb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss; + unicache.ifb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss; + unicache.ifb->rtp_stats = unicache.ifb->stats_t; + + unicache.prefetchb->stats_t.readAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.prefetchb->stats_t.writeAc.access += + homenode_rtp_stats.writeAc.miss; + unicache.prefetchb->rtp_stats = unicache.prefetchb->stats_t; + + unicache.wbb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss; + unicache.wbb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss; + } + unicache.wbb->rtp_stats = unicache.wbb->stats_t; + } + } + + unicache.power_t.reset(); + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + unicache.power_t.readOp.dynamic += + (unicache.caches->stats_t.readAc.hit * + unicache.caches->local_result.power.readOp.dynamic + + unicache.caches->stats_t.readAc.miss * + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + unicache.caches->stats_t.writeAc.miss * + unicache.caches->local_result.tag_array2->power.writeOp.dynamic + + unicache.caches->stats_t.writeAc.access * + unicache.caches->local_result.power.writeOp + .dynamic); // write miss will also generate a write later + + if (cachep.dir_ty == SBT) { + unicache.power_t.readOp.dynamic += + homenode_stats_t.readAc.hit * + (unicache.caches->local_result.data_array2->power.readOp.dynamic * + dir_overhead + + unicache.caches->local_result.tag_array2->power.readOp.dynamic) + + homenode_stats_t.readAc.miss * + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + homenode_stats_t.writeAc.miss * + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + homenode_stats_t.writeAc.hit * + (unicache.caches->local_result.data_array2->power.writeOp + .dynamic * + dir_overhead + + unicache.caches->local_result.tag_array2->power.readOp.dynamic + + homenode_stats_t.writeAc.miss * + unicache.caches->local_result.power.writeOp + .dynamic); // write miss on dynamic home node will + // generate a replacement write on whole + // cache block + } + + unicache.power_t.readOp.dynamic += + unicache.missb->stats_t.readAc.access * + unicache.missb->local_result.power.searchOp.dynamic + + unicache.missb->stats_t.writeAc.access * + unicache.missb->local_result.power.writeOp + .dynamic; // each access to missb involves a CAM and a write + unicache.power_t.readOp.dynamic += + unicache.ifb->stats_t.readAc.access * + unicache.ifb->local_result.power.searchOp.dynamic + + unicache.ifb->stats_t.writeAc.access * + unicache.ifb->local_result.power.writeOp.dynamic; + unicache.power_t.readOp.dynamic += + unicache.prefetchb->stats_t.readAc.access * + unicache.prefetchb->local_result.power.searchOp.dynamic + + unicache.prefetchb->stats_t.writeAc.access * + unicache.prefetchb->local_result.power.writeOp.dynamic; + unicache.power_t.readOp.dynamic += + unicache.wbb->stats_t.readAc.access * + unicache.wbb->local_result.power.searchOp.dynamic + + unicache.wbb->stats_t.writeAc.access * + unicache.wbb->local_result.power.writeOp.dynamic; + } + else { + unicache.power_t.readOp.dynamic += + (unicache.caches->stats_t.readAc.access * + unicache.caches->local_result.power.searchOp.dynamic + + unicache.caches->stats_t.writeAc.access * + unicache.caches->local_result.power.writeOp.dynamic); + } + + if (is_tdp) { + unicache.power = + unicache.power_t + (unicache.caches->local_result.power) * pppm_lkg; + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + unicache.power = + unicache.power + (unicache.missb->local_result.power + + unicache.ifb->local_result.power + + unicache.prefetchb->local_result.power + + unicache.wbb->local_result.power) * + pppm_lkg; + } + power = power + unicache.power; + // cout<<"unicache.caches->local_result.power.readOp.dynamic"<local_result.power.readOp.dynamic<local_result.power.writeOp.dynamic"<local_result.power.writeOp.dynamic<local_result.power) * pppm_lkg; + if (!((cachep.dir_ty == ST && cacheL == L1Directory) || + (cachep.dir_ty == ST && cacheL == L2Directory))) { + unicache.rt_power = + unicache.rt_power + (unicache.missb->local_result.power + + unicache.ifb->local_result.power + + unicache.prefetchb->local_result.power + + unicache.wbb->local_result.power) * + pppm_lkg; + } + rt_power = rt_power + unicache.rt_power; + } +} + +void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) { + string indent_str(indent, ' '); + string indent_str_next(indent + 2, ' '); + bool long_channel = XML->sys.longer_channel_device; + bool power_gating = XML->sys.power_gating; + + if (is_tdp) { + cout << (XML->sys.Private_L2 ? indent_str : "") << cachep.name << endl; + cout << indent_str << "Area = " << area.get_area() * 1e-6 << " mm^2" + << endl; + cout << indent_str + << "Peak Dynamic = " << power.readOp.dynamic * cachep.clockRate << " W" + << endl; + cout << indent_str << "Subthreshold Leakage = " + << (long_channel ? power.readOp.longer_channel_leakage + : power.readOp.leakage) + << " W" << endl; + if (power_gating) + cout << indent_str << "Subthreshold Leakage with power gating = " + << (long_channel ? power.readOp.power_gated_with_long_channel_leakage + : power.readOp.power_gated_leakage) + << " W" << endl; + cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" + << endl; + cout << indent_str << "Runtime Dynamic = " + << rt_power.readOp.dynamic / cachep.executionTime << " W" << endl; + cout << endl; + } + else { + } +} + +// void SharedCache::computeMaxPower() +//{ +// //Compute maximum power and runtime power. +// //When computing runtime power, McPAT gets or reasons out the statistics +// based on XML input. maxPower = 0.0; +// //llCache,itlb +// llCache.maxPower = 0.0; +// llCache.maxPower += +// (llCache.caches.l_ip.num_rw_ports*(0.67*llCache.caches.local_result.power.readOp.dynamic+0.33*llCache.caches.local_result.power.writeOp.dynamic) +// +llCache.caches.l_ip.num_rd_ports*llCache.caches.local_result.power.readOp.dynamic+llCache.caches.l_ip.num_wr_ports*llCache.caches.local_result.power.writeOp.dynamic +// +llCache.caches.l_ip.num_se_rd_ports*llCache.caches.local_result.power.readOp.dynamic)*clockRate; +// ///cout<<"llCache.maxPower=" <sys.first_level_dir==1) +// { +// inv_dir.maxPower = +// inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size; +// cc.power.readOp.dynamic = +// inv_dir.maxPower*scktRatio*64/XML->sys.domain_size; +// cc.power.readOp.leakage = +// inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*64/XML->sys.domain_size; +// +// cc.area.set_area(inv_dir.area*64/XML->sys.domain_size); +// cout<<"CC area="<sys.number_of_dir_levels==2) +// { +// +// directory.maxPower = 0.0; +// directory.maxPower += +//(directory.caches.l_ip.num_rw_ports*(0.67*directory.caches.local_result.power.readOp.dynamic+0.33*directory.caches.local_result.power.writeOp.dynamic) +// +directory.caches.l_ip.num_rd_ports*directory.caches.local_result.power.readOp.dynamic+directory.caches.l_ip.num_wr_ports*directory.caches.local_result.power.writeOp.dynamic +// +directory.caches.l_ip.num_se_rd_ports*directory.caches.local_result.power.readOp.dynamic)*clockRate; +// ///cout<<"directory.maxPower=" +//<sys.L2[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L2[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L2[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L2[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L2[ithCache].device_type; + cachep.capacity = XML->sys.L2[ithCache].L2_config[0]; + cachep.blockW = XML->sys.L2[ithCache].L2_config[1]; + cachep.assoc = XML->sys.L2[ithCache].L2_config[2]; + cachep.nbanks = XML->sys.L2[ithCache].L2_config[3]; + cachep.throughput = XML->sys.L2[ithCache].L2_config[4] / cachep.clockRate; + cachep.latency = XML->sys.L2[ithCache].L2_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L2[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L2[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L2[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L2[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L2[ithCache].duty_cycle; + if (!XML->sys.L2[ithCache].merged_dir) { + cachep.dir_ty = NonDir; + } + else { + cachep.dir_ty = SBT; + cachep.dir_duty_cycle = XML->sys.L2[ithCache].dir_duty_cycle; + } + + if (XML->sys.Private_L2 && XML->sys.core[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.core[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.core[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.core[ithCache].vdd; + } + + if (XML->sys.Private_L2 && XML->sys.core[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.core[ithCache].power_gating_vcc; + } + if (!XML->sys.Private_L2 && XML->sys.L2[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L2[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L2[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L2[ithCache].vdd; + } + if (!XML->sys.Private_L2 && XML->sys.L2[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L2[ithCache].power_gating_vcc; + } + } + else if (cacheL == L3) { + cachep.name = "L3"; + cachep.clockRate = XML->sys.L3[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L3[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L3[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L3[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L3[ithCache].device_type; + cachep.capacity = XML->sys.L3[ithCache].L3_config[0]; + cachep.blockW = XML->sys.L3[ithCache].L3_config[1]; + cachep.assoc = XML->sys.L3[ithCache].L3_config[2]; + cachep.nbanks = XML->sys.L3[ithCache].L3_config[3]; + cachep.throughput = XML->sys.L3[ithCache].L3_config[4] / cachep.clockRate; + cachep.latency = XML->sys.L3[ithCache].L3_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L3[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L3[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L3[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L3[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L3[ithCache].duty_cycle; + if (!XML->sys.L2[ithCache].merged_dir) { + cachep.dir_ty = NonDir; + } + else { + cachep.dir_ty = SBT; + cachep.dir_duty_cycle = XML->sys.L2[ithCache].dir_duty_cycle; + } + if (XML->sys.L3[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L3[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L3[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L3[ithCache].vdd; + } + + if (XML->sys.L3[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L3[ithCache].power_gating_vcc; + } + } + else if (cacheL == L1Directory) { + cachep.name = "First Level Directory"; + cachep.dir_ty = + (enum Dir_type)XML->sys.L1Directory[ithCache].Directory_type; + cachep.clockRate = XML->sys.L1Directory[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L1Directory[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L1Directory[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = + XML->sys.L1Directory[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L1Directory[ithCache].device_type; + cachep.capacity = XML->sys.L1Directory[ithCache].Dir_config[0]; + cachep.blockW = XML->sys.L1Directory[ithCache].Dir_config[1]; + cachep.assoc = XML->sys.L1Directory[ithCache].Dir_config[2]; + cachep.nbanks = XML->sys.L1Directory[ithCache].Dir_config[3]; + cachep.throughput = + XML->sys.L1Directory[ithCache].Dir_config[4] / cachep.clockRate; + cachep.latency = + XML->sys.L1Directory[ithCache].Dir_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L1Directory[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L1Directory[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L1Directory[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L1Directory[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L1Directory[ithCache].duty_cycle; + + if (XML->sys.L1Directory[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L1Directory[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L1Directory[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L1Directory[ithCache].vdd; + } + + if (XML->sys.L1Directory[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L1Directory[ithCache].power_gating_vcc; + } + } + else if (cacheL == L2Directory) { + cachep.name = "Second Level Directory"; + cachep.dir_ty = + (enum Dir_type)XML->sys.L2Directory[ithCache].Directory_type; + cachep.clockRate = XML->sys.L2Directory[ithCache].clockrate; + cachep.clockRate *= 1e6; + cachep.executionTime = + XML->sys.total_cycles / (XML->sys.target_core_clockrate * 1e6); + interface_ip.data_arr_ram_cell_tech_type = + XML->sys.L2Directory[ithCache].device_type; // long channel device LSTP + interface_ip.data_arr_peri_global_tech_type = + XML->sys.L2Directory[ithCache].device_type; + interface_ip.tag_arr_ram_cell_tech_type = + XML->sys.L2Directory[ithCache].device_type; + interface_ip.tag_arr_peri_global_tech_type = + XML->sys.L2Directory[ithCache].device_type; + cachep.capacity = XML->sys.L2Directory[ithCache].Dir_config[0]; + cachep.blockW = XML->sys.L2Directory[ithCache].Dir_config[1]; + cachep.assoc = XML->sys.L2Directory[ithCache].Dir_config[2]; + cachep.nbanks = XML->sys.L2Directory[ithCache].Dir_config[3]; + cachep.throughput = + XML->sys.L2Directory[ithCache].Dir_config[4] / cachep.clockRate; + cachep.latency = + XML->sys.L2Directory[ithCache].Dir_config[5] / cachep.clockRate; + cachep.missb_size = XML->sys.L2Directory[ithCache].buffer_sizes[0]; + cachep.fu_size = XML->sys.L2Directory[ithCache].buffer_sizes[1]; + cachep.prefetchb_size = XML->sys.L2Directory[ithCache].buffer_sizes[2]; + cachep.wbb_size = XML->sys.L2Directory[ithCache].buffer_sizes[3]; + cachep.duty_cycle = XML->sys.L2Directory[ithCache].duty_cycle; + + if (XML->sys.L2Directory[ithCache].vdd > 0) { + interface_ip.specific_hp_vdd = true; + interface_ip.specific_lop_vdd = true; + interface_ip.specific_lstp_vdd = true; + interface_ip.hp_Vdd = XML->sys.L2Directory[ithCache].vdd; + interface_ip.lop_Vdd = XML->sys.L2Directory[ithCache].vdd; + interface_ip.lstp_Vdd = XML->sys.L2Directory[ithCache].vdd; + } + + if (XML->sys.L2Directory[ithCache].power_gating_vcc > -1) { + interface_ip.specific_vcc_min = true; + interface_ip.user_defined_vcc_min = + XML->sys.L2Directory[ithCache].power_gating_vcc; + } + } + // cachep.cache_duty_cycle=cachep.dir_duty_cycle = 0.35; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/sharedcache.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/sharedcache.h new file mode 100644 index 0000000000..26aa42c0ca --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/sharedcache.h @@ -0,0 +1,90 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef SHAREDCACHE_H_ +#define SHAREDCACHE_H_ +#include +#include "XML_Parse.h" +#include "array.h" +#include "basic_components.h" +#include "cacti/area.h" +#include "cacti/parameter.h" +#include "logic.h" +using namespace cacti; + +class SharedCache : public Component { + public: + ParseXML *XML; + int ithCache; + InputParameter interface_ip; + enum cache_level cacheL; + DataCache unicache; // Shared cache + CacheDynParam cachep; + statsDef homenode_tdp_stats; + statsDef homenode_rtp_stats; + statsDef homenode_stats_t; + double dir_overhead; + // cache_processor llCache,directory, directory1, inv_dir; + + // pipeline pipeLogicCache, pipeLogicDirectory; + // clock_network clockNetwork; + double scktRatio, executionTime; + // Component L2Tot, cc, cc1, ccTot; + + SharedCache(ParseXML *XML_interface, int ithCache_, + InputParameter *interface_ip_, enum cache_level cacheL_ = L2); + void set_cache_param(); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, bool is_tdp = true); + ~SharedCache(){}; +}; + +class CCdir : public Component { + public: + ParseXML *XML; + int ithCache; + InputParameter interface_ip; + DataCache dc; // Shared cache + ArrayST *shadow_dir; + // cache_processor llCache,directory, directory1, inv_dir; + + // pipeline pipeLogicCache, pipeLogicDirectory; + // clock_network clockNetwork; + double scktRatio, clockRate, executionTime; + Component L2Tot, cc, cc1, ccTot; + + CCdir(ParseXML *XML_interface, int ithCache_, InputParameter *interface_ip_); + void computeEnergy(bool is_tdp = true); + void displayEnergy(uint32_t indent = 0, bool is_tdp = true); + ~CCdir(); +}; + +#endif /* SHAREDCACHE_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/version.h b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/version.h new file mode 100644 index 0000000000..ec8e616d04 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/lib/mcpat/version.h @@ -0,0 +1,40 @@ +/***************************************************************************** + * McPAT + * SOFTWARE LICENSE AGREEMENT + * Copyright 2012 Hewlett-Packard Development Company, L.P. + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” + * + ***************************************************************************/ + +#ifndef VERSION_H_ +#define VERSION_H_ + +#define VER_MAJOR 1 +#define VER_MINOR 3 + +#define VER_UPDATE "Feb, 2015" + +#endif /* VERSION_H_ */ diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/abstract_pal.hh b/hotness/SimpleSSD-Standalone/simplessd/pal/abstract_pal.hh new file mode 100644 index 0000000000..86ad5e86c2 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/abstract_pal.hh @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_ABSTRACT_PAL__ +#define __PAL_ABSTRACT_PAL__ + +#include + +#include "pal/pal.hh" + +namespace SimpleSSD { + +namespace PAL { + +class AbstractPAL : public StatObject { + protected: + Parameter ¶m; + ConfigReader &conf; + + public: + AbstractPAL(Parameter &p, ConfigReader &c) : param(p), conf(c) {} + virtual ~AbstractPAL() {} + + virtual void read(Request &, uint64_t &) = 0; + virtual void write(Request &, uint64_t &) = 0; + virtual void erase(Request &, uint64_t &) = 0; +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/config.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/config.cc new file mode 100644 index 0000000000..f9bf83d0d3 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/config.cc @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "pal/config.hh" + +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace PAL { + +const char NAME_CHANNEL[] = "Channel"; +const char NAME_PACKAGE[] = "Package"; +const char NAME_PAGE_ALLOCATION[] = "PageAllocation"; +const char NAME_SUPER_BLOCK[] = "SuperblockSize"; + +/* NAND config TODO: seperate this */ +const char NAME_DIE[] = "Die"; +const char NAME_PLANE[] = "Plane"; +const char NAME_BLOCK[] = "Block"; +const char NAME_PAGE[] = "Page"; +const char NAME_PAGE_SIZE[] = "PageSize"; +const char NAME_USE_MULTI_PLANE_OP[] = "EnableMultiPlaneOperation"; +const char NAME_DMA_SPEED[] = "DMASpeed"; +const char NAME_DMA_WIDTH[] = "DMAWidth"; +const char NAME_FLASH_TYPE[] = "NANDType"; + +/* NAND timing TODO: seperate this */ +const char NAME_NAND_LSB_READ[] = "LSBRead"; +const char NAME_NAND_LSB_WRITE[] = "LSBWrite"; +const char NAME_NAND_CSB_READ[] = "CSBRead"; +const char NAME_NAND_CSB_WRITE[] = "CSBWrite"; +const char NAME_NAND_MSB_READ[] = "MSBRead"; +const char NAME_NAND_MSB_WRITE[] = "MSBWrite"; +const char NAME_NAND_ERASE[] = "Erase"; + +/* NAND power TODO: seperate this */ +const char NAME_NAND_VOLTAGE[] = "Voltage"; +const char NAME_NAND_CURRENT_READ[] = "ReadCurrent"; +const char NAME_NAND_CURRENT_PROGRAM[] = "ProgramCurrent"; +const char NAME_NAND_CURRENT_ERASE[] = "EraseCurrent"; +const char NAME_NAND_CURRENT_IDLE[] = "IdleCurrent"; +const char NAME_NAND_CURRENT_STANDBY[] = "StandbyCurrent"; + +/* Constants for calculating DMA time based on ONFI 3.x spec */ +// READ : <00h> <30h> [tWB] [tR] [tRR] +// WRITE: <80h> [tADL] <10h> [tWB] [tPROG] +// ERASE: <60h> [tWB] [tBERS] +const uint8_t readCycle = 7; +const uint8_t writeCycle = 7; +const uint8_t eraseCycle = 5; + +Config::Config() { + channel = 8; + package = 4; + die = 2; + plane = 1; + block = 512; + page = 512; + pageSize = 16384; + useMultiPlaneOperation = true; + dmaSpeed = 400; + dmaWidth = 8; + nandType = NAND_MLC; + + // Set NAND timing (Default: MLC, csb is not used) + nandTiming.lsb.read = 40000000; // 40us + nandTiming.lsb.write = 500000000; // 500us + nandTiming.csb.read = 0; + nandTiming.csb.write = 0; + nandTiming.msb.read = 65000000; // 65us + nandTiming.msb.write = 1300000000; // 1300us + nandTiming.erase = 3500000000; // 3.5ms + + // Set NAND power (From: Micron's MT29F64*) + nandPower.voltage = 3300; // 3.3V + nandPower.current.read = 25000; // 25mA + nandPower.current.program = 25000; // 25mA + nandPower.current.erase = 25000; // 25mA + nandPower.current.busIdle = 5000; // 5mA + nandPower.current.standby = 10; // 10uA + + superblock = 0; + memset(PageAllocation, 0, 4); +} + +bool Config::setConfig(const char *name, const char *value) { + bool ret = true; + + if (MATCH_NAME(NAME_CHANNEL)) { + channel = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PACKAGE)) { + package = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DIE)) { + die = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PLANE)) { + plane = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_BLOCK)) { + block = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PAGE)) { + page = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_PAGE_SIZE)) { + pageSize = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_USE_MULTI_PLANE_OP)) { + useMultiPlaneOperation = convertBool(value); + } + else if (MATCH_NAME(NAME_DMA_SPEED)) { + dmaSpeed = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_DMA_WIDTH)) { + dmaWidth = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_FLASH_TYPE)) { + nandType = (NAND_TYPE)strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_SUPER_BLOCK)) { + _superblock = value; + } + else if (MATCH_NAME(NAME_PAGE_ALLOCATION)) { + _pageAllocation = value; + } + else if (MATCH_NAME(NAME_NAND_LSB_READ)) { + nandTiming.lsb.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_LSB_WRITE)) { + nandTiming.lsb.write = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CSB_READ)) { + nandTiming.csb.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CSB_WRITE)) { + nandTiming.csb.write = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_MSB_READ)) { + nandTiming.msb.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_MSB_WRITE)) { + nandTiming.msb.write = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_ERASE)) { + nandTiming.erase = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_VOLTAGE)) { + nandPower.voltage = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_READ)) { + nandPower.current.read = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_PROGRAM)) { + nandPower.current.program = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_ERASE)) { + nandPower.current.erase = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_IDLE)) { + nandPower.current.busIdle = strtoul(value, nullptr, 10); + } + else if (MATCH_NAME(NAME_NAND_CURRENT_STANDBY)) { + nandPower.current.standby = strtoul(value, nullptr, 10); + } + else { + ret = false; + } + + return ret; +} + +void Config::update() { + if (dmaWidth & 0x07) { + panic("dmaWidth should be multiple of 8."); + } + + // DMA time calculation + // MT/s MT -> T ms us ns ps + float tCK = 1.f / (dmaSpeed * 1048576) * 1000 * 1000 * 1000 * 1000; + + nandTiming.dma0.read = readCycle * tCK / (dmaWidth / 8); + nandTiming.dma0.write = (writeCycle + pageSize) * tCK / (dmaWidth / 8); + nandTiming.dma0.erase = eraseCycle * tCK / (dmaWidth / 8); + nandTiming.dma1.read = pageSize * tCK / (dmaWidth / 8); + nandTiming.dma1.write = 1 * tCK / (dmaWidth / 8); + nandTiming.dma1.erase = 1 * tCK / (dmaWidth / 8); + + // Parse page allocation setting + int i = 0; + uint8_t check = 0; + bool fail = false; + + for (auto iter : _pageAllocation) { + if ((iter == 'C') | (iter == 'c')) { + if (check & INDEX_CHANNEL) { + fail = true; + } + + PageAllocation[i++] = INDEX_CHANNEL; + check |= INDEX_CHANNEL; + } + else if ((iter == 'W') | (iter == 'w')) { + if (check & INDEX_PACKAGE) { + fail = true; + } + + PageAllocation[i++] = INDEX_PACKAGE; + check |= INDEX_PACKAGE; + } + else if ((iter == 'D') | (iter == 'd')) { + if (check & INDEX_DIE) { + fail = true; + } + + PageAllocation[i++] = INDEX_DIE; + check |= INDEX_DIE; + } + else if ((iter == 'P') | (iter == 'p')) { + if (check & INDEX_PLANE) { + fail = true; + } + + PageAllocation[i++] = INDEX_PLANE; + check |= INDEX_PLANE; + } + + if (i == 4) { + break; + } + } + + if (check != (INDEX_CHANNEL | INDEX_PACKAGE | INDEX_DIE | INDEX_PLANE)) { + fail = true; + } + + if (useMultiPlaneOperation) { + // Move P to front + for (i = 0; i < 4; i++) { + if (PageAllocation[i] == INDEX_PLANE) { + for (int j = i; j > 0; j--) { + PageAllocation[j] = PageAllocation[j - 1]; + } + + PageAllocation[0] = INDEX_PLANE; + + break; + } + } + } + + if (fail) { + panic("Invalid page allocation string"); + } + + // Parse super block size setting + if (_superblock.length() > 0) { + superblock = 0x00; + + for (auto iter : _superblock) { + if ((iter == 'C') | (iter == 'c')) { + superblock |= INDEX_CHANNEL; + } + else if ((iter == 'W') | (iter == 'w')) { + superblock |= INDEX_PACKAGE; + } + else if ((iter == 'D') | (iter == 'd')) { + superblock |= INDEX_DIE; + } + else if ((iter == 'P') | (iter == 'p')) { + superblock |= INDEX_PLANE; + } + } + } + + if (useMultiPlaneOperation) { + superblock |= INDEX_PLANE; + } +} + +int64_t Config::readInt(uint32_t idx) { + int64_t ret = 0; + + switch (idx) { + case NAND_FLASH_TYPE: + ret = nandType; + break; + } + + return ret; +} + +uint64_t Config::readUint(uint32_t idx) { + uint64_t ret = 0; + + switch (idx) { + case PAL_CHANNEL: + ret = channel; + break; + case PAL_PACKAGE: + ret = package; + break; + case NAND_DIE: + ret = die; + break; + case NAND_PLANE: + ret = plane; + break; + case NAND_BLOCK: + ret = block; + break; + case NAND_PAGE: + ret = page; + break; + case NAND_PAGE_SIZE: + ret = pageSize; + break; + case NAND_DMA_SPEED: + ret = dmaSpeed; + break; + case NAND_DMA_WIDTH: + ret = dmaWidth; + break; + } + + return ret; +} + +bool Config::readBoolean(uint32_t idx) { + bool ret = false; + + switch (idx) { + case NAND_USE_MULTI_PLANE_OP: + ret = useMultiPlaneOperation; + break; + } + + return ret; +} + +uint8_t Config::getSuperblockConfig() { + return superblock; +} + +uint32_t Config::getPageAllocationConfig() { + return (uint32_t)PageAllocation[0] | ((uint32_t)PageAllocation[1] << 8) | + ((uint32_t)PageAllocation[2] << 16) | + ((uint32_t)PageAllocation[3] << 24); +} + +Config::NANDTiming *Config::getNANDTiming() { + return &nandTiming; +} + +Config::NANDPower *Config::getNANDPower() { + return &nandPower; +} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/config.hh b/hotness/SimpleSSD-Standalone/simplessd/pal/config.hh new file mode 100644 index 0000000000..b7e7f79da7 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/config.hh @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_CONFIG__ +#define __PAL_CONFIG__ + +#include "sim/base_config.hh" + +namespace SimpleSSD { + +namespace PAL { + +typedef enum { + /* PAL config */ + PAL_CHANNEL, + PAL_PACKAGE, + + /* NAND config TODO: seperate this */ + NAND_DIE, + NAND_PLANE, + NAND_BLOCK, + NAND_PAGE, + NAND_PAGE_SIZE, + NAND_USE_MULTI_PLANE_OP, + NAND_DMA_SPEED, + NAND_DMA_WIDTH, + NAND_FLASH_TYPE, +} PAL_CONFIG; + +typedef enum { + NAND_SLC, + NAND_MLC, + NAND_TLC, +} NAND_TYPE; + +typedef enum : uint8_t { + INDEX_CHANNEL = 0x01, + INDEX_PACKAGE = 0x02, + INDEX_DIE = 0x04, + INDEX_PLANE = 0x08, +} ADDR_INDEX; + +class Config : public BaseConfig { + public: + typedef struct { + uint64_t read; + uint64_t write; + } PAGETiming; + + typedef struct { + uint64_t read; + uint64_t write; + uint64_t erase; + } DMATiming; + + typedef struct { + PAGETiming lsb; + PAGETiming csb; + PAGETiming msb; + DMATiming dma0; + DMATiming dma1; + uint64_t erase; + } NANDTiming; + + typedef struct { + uint64_t voltage; //!< Unit: mV + struct { //!< Unit: uA + uint64_t read; + uint64_t program; + uint64_t erase; + uint64_t busIdle; + uint64_t standby; + } current; + } NANDPower; + + private: + uint32_t channel; //!< Default: 8 + uint32_t package; //!< Default: 4 + + uint32_t die; //!< Default: 2 + uint32_t plane; //!< Default: 1 + uint32_t block; //!< Default: 512 + uint32_t page; //!< Default: 512 + uint32_t pageSize; //!< Default: 16384 + bool useMultiPlaneOperation; //!< Default: true + uint32_t dmaSpeed; //!< Default: 400 + uint32_t dmaWidth; //!< Default: 8 + NAND_TYPE nandType; //!< Default: NAND_MLC + uint8_t superblock; //!< Default: All (0x0F) + uint8_t PageAllocation[4]; //!< Default: CWDP (0x01, 0x02, 0x04, 0x08) + + NANDTiming nandTiming; + NANDPower nandPower; + + // Raw variable + std::string _superblock; + std::string _pageAllocation; + + public: + Config(); + + bool setConfig(const char *, const char *) override; + void update() override; + + int64_t readInt(uint32_t) override; + uint64_t readUint(uint32_t) override; + bool readBoolean(uint32_t) override; + + uint8_t getSuperblockConfig(); + uint32_t getPageAllocationConfig(); + + NANDTiming *getNANDTiming(); + NANDPower *getNANDPower(); +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/Latency.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/Latency.cc new file mode 100644 index 0000000000..0c20ca78a0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/Latency.cc @@ -0,0 +1,58 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "Latency.h" + +/*============================== + Latency +==============================*/ + +/* + Latency class is inherited to: + - TLC + - MLC + - SLC +*/ + +Latency::Latency(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : timing(t), power(p) {} + +Latency::~Latency() {} + +// Unit conversion: mV * uA = nW +uint64_t Latency::GetPower(uint8_t Oper, uint8_t Busy) { + switch (Busy) { + case BUSY_DMA0: + case BUSY_DMA1: + return power.voltage * power.current.busIdle; + case BUSY_MEM: + if (Oper == OPER_READ) { + return power.voltage * power.current.read; + } + else if (Oper == OPER_WRITE) { + return power.voltage * power.current.program; + } + else { + return power.voltage * power.current.erase; + } + + break; + default: + return power.voltage * power.current.standby; + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/Latency.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/Latency.h new file mode 100644 index 0000000000..dbbe80b054 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/Latency.h @@ -0,0 +1,56 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __Latency_h__ +#define __Latency_h__ + +#include "util/old/SimpleSSD_types.h" + +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +#include "pal/config.hh" + +/*============================== + Latency +==============================*/ +class Latency { + protected: + SimpleSSD::PAL::Config::NANDTiming timing; + SimpleSSD::PAL::Config::NANDPower power; + + public: + Latency(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + virtual ~Latency(); + + // Get Latency for PageAddress(L/C/MSBpage), Operation(RWE), + // BusyFor(Ch.DMA/Mem.Work) + virtual uint64_t GetLatency(uint32_t, uint8_t, uint8_t) { return 0; }; + virtual inline uint8_t GetPageType(uint32_t) { return PAGE_NUM; }; + + // Setup DMA speed and pagesize + virtual uint64_t GetPower(uint8_t, uint8_t); +}; + +#endif //__Latency_h__ diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyMLC.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyMLC.cc new file mode 100644 index 0000000000..c4382fda5c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyMLC.cc @@ -0,0 +1,84 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "LatencyMLC.h" + +LatencyMLC::LatencyMLC(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : Latency(t, p) {} + +LatencyMLC::~LatencyMLC() {} + +inline uint8_t LatencyMLC::GetPageType(uint32_t AddrPage) { + return AddrPage % 2; +} + +uint64_t LatencyMLC::GetLatency(uint32_t AddrPage, uint8_t Oper, uint8_t Busy) { + SimpleSSD::PAL::Config::PAGETiming *pTiming = nullptr; + + switch (Busy) { + case BUSY_DMA0: + if (Oper == OPER_READ) { + return timing.dma0.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma0.write; + } + else { + return timing.dma0.erase; + } + + break; + case BUSY_DMA1: + if (Oper == OPER_READ) { + return timing.dma1.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma1.write; + } + else { + return timing.dma1.erase; + } + + break; + case BUSY_MEM: { + if (Oper == OPER_ERASE) { + return timing.erase; + } + + if (GetPageType(AddrPage) == PAGE_LSB) { + pTiming = &timing.lsb; + } + else { + pTiming = &timing.msb; + } + + if (Oper == OPER_READ) { + return pTiming->read; + } + else { + return pTiming->write; + } + + break; + } + default: + break; + } + + return 10; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyMLC.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyMLC.h new file mode 100644 index 0000000000..19dbafb088 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyMLC.h @@ -0,0 +1,33 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __LatencyMLC_h__ +#define __LatencyMLC_h__ + +#include "Latency.h" + +class LatencyMLC : public Latency { + public: + LatencyMLC(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + ~LatencyMLC(); + + uint64_t GetLatency(uint32_t, uint8_t, uint8_t) override; + inline uint8_t GetPageType(uint32_t) override; +}; + +#endif //__LatencyMLC_h__ diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencySLC.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencySLC.cc new file mode 100644 index 0000000000..a6b6c2a83d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencySLC.cc @@ -0,0 +1,73 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "LatencySLC.h" + +LatencySLC::LatencySLC(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : Latency(t, p) {} + +LatencySLC::~LatencySLC() {} + +inline uint8_t LatencySLC::GetPageType(uint32_t) { + return PAGE_LSB; +} + +uint64_t LatencySLC::GetLatency(uint32_t, uint8_t Oper, uint8_t Busy) { + switch (Busy) { + case BUSY_DMA0: + if (Oper == OPER_READ) { + return timing.dma0.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma0.write; + } + else { + return timing.dma0.erase; + } + + break; + case BUSY_DMA1: + if (Oper == OPER_READ) { + return timing.dma1.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma1.write; + } + else { + return timing.dma1.erase; + } + + break; + case BUSY_MEM: + if (Oper == OPER_READ) { + return timing.lsb.read; + } + else if (Oper == OPER_WRITE) { + return timing.lsb.write; + } + else { + return timing.erase; + } + + break; + default: + break; + } + + return 10; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencySLC.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencySLC.h new file mode 100644 index 0000000000..97da54c931 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencySLC.h @@ -0,0 +1,33 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __LatencySLC_h__ +#define __LatencySLC_h__ + +#include "Latency.h" + +class LatencySLC : public Latency { + public: + LatencySLC(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + ~LatencySLC(); + + uint64_t GetLatency(uint32_t, uint8_t, uint8_t) override; + inline uint8_t GetPageType(uint32_t) override; +}; + +#endif //__LatencyTLC_h__ diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyTLC.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyTLC.cc new file mode 100644 index 0000000000..db056acfb9 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyTLC.cc @@ -0,0 +1,90 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "LatencyTLC.h" + +LatencyTLC::LatencyTLC(SimpleSSD::PAL::Config::NANDTiming t, + SimpleSSD::PAL::Config::NANDPower p) + : Latency(t, p) {} + +LatencyTLC::~LatencyTLC() {} + +inline uint8_t LatencyTLC::GetPageType(uint32_t AddrPage) { + return (AddrPage <= 5) ? (uint8_t)PAGE_LSB + : ((AddrPage <= 7) ? (uint8_t)PAGE_CSB + : (((AddrPage - 8) >> 1) % 3)); +} + +uint64_t LatencyTLC::GetLatency(uint32_t AddrPage, uint8_t Oper, uint8_t Busy) { + SimpleSSD::PAL::Config::PAGETiming *pTiming = nullptr; + uint8_t pType = GetPageType(AddrPage); + + switch (Busy) { + case BUSY_DMA0: + if (Oper == OPER_READ) { + return timing.dma0.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma0.write; + } + else { + return timing.dma0.erase; + } + + break; + case BUSY_DMA1: + if (Oper == OPER_READ) { + return timing.dma1.read; + } + else if (Oper == OPER_WRITE) { + return timing.dma1.write; + } + else { + return timing.dma1.erase; + } + + break; + case BUSY_MEM: { + if (Oper == OPER_ERASE) { + return timing.erase; + } + + if (pType == PAGE_LSB) { + pTiming = &timing.lsb; + } + else if (pType == PAGE_CSB) { + pTiming = &timing.csb; + } + else { + pTiming = &timing.msb; + } + + if (Oper == OPER_READ) { + return pTiming->read; + } + else { + return pTiming->write; + } + + break; + } + default: + break; + } + + return 10; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyTLC.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyTLC.h new file mode 100644 index 0000000000..fe0d794836 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/LatencyTLC.h @@ -0,0 +1,33 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __LatencyTLC_h__ +#define __LatencyTLC_h__ + +#include "Latency.h" + +class LatencyTLC : public Latency { + public: + LatencyTLC(SimpleSSD::PAL::Config::NANDTiming, + SimpleSSD::PAL::Config::NANDPower); + ~LatencyTLC(); + + uint64_t GetLatency(uint32_t, uint8_t, uint8_t) override; + inline uint8_t GetPageType(uint32_t) override; +}; + +#endif //__LatencyTLC_h__ diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2.cc new file mode 100644 index 0000000000..1964cb6a36 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2.cc @@ -0,0 +1,963 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#include "PAL2.h" + +#include "util/algorithm.hh" + +PAL2::PAL2(PALStatistics *statistics, SimpleSSD::PAL::Parameter *p, + SimpleSSD::ConfigReader *c, Latency *l) + : pParam(p), lat(l), stats(statistics) { + uint32_t OriginalSizes[7]; + + uint32_t SPDIV = + c->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_DMA_SPEED) / 50; + uint32_t PGDIV = 16384 / c->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE); + + if (SPDIV == 0 || PGDIV == 0) { + SimpleSSD::panic("SPDIV or PGDIV is 0"); + } + + OriginalSizes[ADDR_CHANNEL] = pParam->channel; + OriginalSizes[ADDR_PACKAGE] = pParam->package; + OriginalSizes[ADDR_DIE] = pParam->die; + + if (c->readBoolean(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_USE_MULTI_PLANE_OP)) { + OriginalSizes[ADDR_PLANE] = 1; + } + else { + OriginalSizes[ADDR_PLANE] = pParam->plane; + } + + OriginalSizes[ADDR_BLOCK] = pParam->block; + OriginalSizes[ADDR_PAGE] = pParam->page; + OriginalSizes[6] = 0; // Add remaining bits + + AddrRemap[0] = ADDR_PAGE; + AddrRemap[1] = ADDR_BLOCK; + AddrRemap[2] = ADDR_PLANE; + AddrRemap[3] = ADDR_DIE; + AddrRemap[4] = ADDR_PACKAGE; + AddrRemap[5] = ADDR_CHANNEL; + + RearrangedSizes[6] = OriginalSizes[6]; + for (int i = 0; i < 6; i++) { + RearrangedSizes[i] = OriginalSizes[AddrRemap[i]]; + + // DPRINTF(PAL,"PAL: [%d] ORI(%s): %u --> REARR(%s): %u\n", i, + // ADDR_STRINFO[ i ], OriginalSizes[ i ], ADDR_STRINFO[ gconf->AddrSeq[i] + // ], RearrangedSizes[i]); //Use DPRINTF here + } + + totalDie = pParam->channel * pParam->package * pParam->die; + + ChFreeSlots = + new std::map *>[pParam->channel]; + ChStartPoint = new uint64_t[pParam->channel]; + for (unsigned i = 0; i < pParam->channel; i++) + ChStartPoint[i] = 0; + + DieFreeSlots = + new std::map *>[totalDie]; + DieStartPoint = new uint64_t[totalDie]; + for (unsigned i = 0; i < totalDie; i++) + DieStartPoint[i] = 0; + + // currently, hard code pre-dma, mem-op and post-dma values + for (unsigned i = 0; i < pParam->channel; i++) { + std::map *tmp; + switch ( + c->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_FLASH_TYPE)) { + case SimpleSSD::PAL::NAND_SLC: + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV)] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV) + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][1500000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_MLC: + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV)] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV) + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][1500000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_TLC: + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][100000 / SPDIV + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV)] = tmp; + tmp = new std::map; + ChFreeSlots[i][185000000 / (PGDIV * SPDIV) + 100000 / SPDIV] = tmp; + tmp = new std::map; + ChFreeSlots[i][1500000 / SPDIV] = tmp; + break; + default: + printf("unsupported NAND types!\n"); + std::terminate(); + break; + } + } + + for (unsigned i = 0; i < totalDie; i++) { + std::map *tmp; + switch ( + c->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_FLASH_TYPE)) { + case SimpleSSD::PAL::NAND_SLC: + tmp = new std::map; + DieFreeSlots[i][25000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][300000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][2000000000 + 100000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_MLC: + tmp = new std::map; + DieFreeSlots[i][40000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][90000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][500000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][1300000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][3500000000 + 100000 / SPDIV] = tmp; + break; + case SimpleSSD::PAL::NAND_TLC: + tmp = new std::map; + DieFreeSlots[i][58000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][78000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][107000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][558000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][2201000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][5001000000 + 100000 / SPDIV] = tmp; + tmp = new std::map; + DieFreeSlots[i][2274000000 + 100000 / SPDIV] = tmp; + break; + default: + printf("unsupported NAND types!\n"); + std::terminate(); + break; + } + } +} + +PAL2::~PAL2() { + FlushTimeSlots(MAX64); + + for (uint i = 0; i < pParam->channel; i++) { + for (auto &iter : ChFreeSlots[i]) { + { + delete iter.second; + iter.second = NULL; + } + } + } + delete[] ChFreeSlots; + + for (uint i = 0; i < totalDie; i++) { + for (auto &iter : DieFreeSlots[i]) { + { + delete iter.second; + iter.second = NULL; + } + } + } + delete[] DieFreeSlots; + + delete[] ChStartPoint; + delete[] DieStartPoint; +} + +void PAL2::TimelineScheduling(Command &req, CPDPBP &reqCPD) { + // ensure we can erase multiple blocks from single request + unsigned erase_block = 1; + /*=========== CONFLICT data gather ============*/ + for (unsigned cur_command = 0; cur_command < erase_block; cur_command++) { +#if GATHER_RESOURCE_CONFLICT + uint8_t confType = CONFLICT_NONE; +#endif + req.ppn = req.ppn - (req.ppn & (erase_block - 1)) + cur_command; + uint32_t reqCh = reqCPD.Channel; + uint32_t reqDieIdx = CPDPBPtoDieIdx(&reqCPD); + TimeSlot tsDMA0, tsMEM, tsDMA1; + uint64_t tickDMA0 = 0, tickMEM = 0, + tickDMA1 = 0; // start tick of the free slot + uint64_t latDMA0, latMEM, latDMA1, totalLat; + uint64_t DMA0tickFrom, MEMtickFrom, DMA1tickFrom; // starting point + uint64_t latANTI; // anticipate time slot + bool conflicts; // check conflict when scheduling + latDMA0 = lat->GetLatency(reqCPD.Page, req.operation, BUSY_DMA0); + latMEM = lat->GetLatency(reqCPD.Page, req.operation, BUSY_MEM); + latDMA1 = lat->GetLatency(reqCPD.Page, req.operation, BUSY_DMA1); + latANTI = lat->GetLatency(reqCPD.Page, OPER_READ, BUSY_DMA0); + // Start Finding available Slot + DMA0tickFrom = req.arrived; // get Current System Time + while (1) // LOOP0 + { + while (1) // LOOP1 + { + // 1a) LOOP1 - Find DMA0 available slot in ChTimeSlots + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA0, DMA0tickFrom, tickDMA0, + conflicts)) { + if (DMA0tickFrom < ChStartPoint[reqCh]) { + DMA0tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA0 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA0tickFrom = tickDMA0; + } + /*=========== CONFLICT check - DMA0 ============*/ +#if GATHER_RESOURCE_CONFLICT + if (conflicts && !(confType & CONFLICT_MEM)) { + confType |= CONFLICT_DMA0; + } +#endif + + // 2b) LOOP1 - Find MEM avaiable slot in DieTimeSlots + MEMtickFrom = DMA0tickFrom; + if (!FindFreeTime(DieFreeSlots[reqDieIdx], (latDMA0 + latMEM), + MEMtickFrom, tickMEM, conflicts)) { + if (MEMtickFrom < DieStartPoint[reqDieIdx]) { + MEMtickFrom = DieStartPoint[reqDieIdx]; + conflicts = true; + } + else { + conflicts = false; + } + tickMEM = DieStartPoint[reqDieIdx]; + } + else { + if (conflicts) + MEMtickFrom = tickMEM; + } + if (tickMEM == tickDMA0) + break; + DMA0tickFrom = MEMtickFrom; + + uint64_t tickDMA0_vrfy; + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA0, DMA0tickFrom, + tickDMA0_vrfy, conflicts)) { + tickDMA0_vrfy = ChStartPoint[reqCh]; + } + if (tickDMA0_vrfy == tickDMA0) + break; + /*=========== CONFLICT check - MEM ============*/ +#if GATHER_RESOURCE_CONFLICT + if (conflicts && !(confType & CONFLICT_DMA0)) { + confType |= CONFLICT_MEM; + } +#endif + + } // LOOP1 + + // 3) Find DMA1 available slot + DMA1tickFrom = DMA0tickFrom + (latDMA0 + latMEM); + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA1 + latANTI, DMA1tickFrom, + tickDMA1, conflicts)) { + if (DMA1tickFrom < ChStartPoint[reqCh]) { + DMA1tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA1 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA1tickFrom = tickDMA1; + } + + // 4) Re-verify MEM slot + // The target die should be free during (DMA0_start ~ DMA1_end) + totalLat = (DMA1tickFrom + latDMA1 + latANTI) - DMA0tickFrom; + uint64_t tickMEM_vrfy; + if (!FindFreeTime(DieFreeSlots[reqDieIdx], totalLat, DMA0tickFrom, + tickMEM_vrfy, conflicts)) { + tickMEM_vrfy = DieStartPoint[reqDieIdx]; + } + if (tickMEM_vrfy == tickMEM) + break; + /*=========== CONFLICT check - DMA1 ============*/ +#if GATHER_RESOURCE_CONFLICT + { confType |= CONFLICT_DMA1; } +#endif + + DMA0tickFrom = tickMEM_vrfy; // or re-search for next available resource! + } // LOOP0 + + // 5) Assign dma0, dma1, mem + { + InsertFreeSlot(ChFreeSlots[reqCh], latDMA0, DMA0tickFrom, tickDMA0, + ChStartPoint[reqCh], 0); + + if (!FindFreeTime(ChFreeSlots[reqCh], latDMA1 + latANTI, DMA1tickFrom, + tickDMA1, conflicts)) { + if (DMA1tickFrom < ChStartPoint[reqCh]) { + DMA1tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA1 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA1tickFrom = tickDMA1; + } + if (DMA1tickFrom > tickDMA1) + InsertFreeSlot(ChFreeSlots[reqCh], latDMA1, DMA1tickFrom + latANTI, + tickDMA1, ChStartPoint[reqCh], 0); + else + InsertFreeSlot(ChFreeSlots[reqCh], latDMA1, tickDMA1 + latANTI, + tickDMA1, ChStartPoint[reqCh], 0); + + // temporarily use previous MergedTimeSlots design + InsertFreeSlot(DieFreeSlots[reqDieIdx], totalLat, DMA0tickFrom, tickMEM, + DieStartPoint[reqDieIdx], 0); + + if (DMA0tickFrom < tickDMA0) + tsDMA0 = TimeSlot(tickDMA0, latDMA0); + else + tsDMA0 = TimeSlot(DMA0tickFrom, latDMA0); + + if (DMA1tickFrom < tickDMA1) + tsDMA1 = TimeSlot(tickDMA1 + latANTI, latDMA1); + else + tsDMA1 = TimeSlot(DMA1tickFrom + latANTI, latDMA1); + + if (DMA0tickFrom < tickMEM) + tsMEM = TimeSlot(tickMEM, totalLat); + else + tsMEM = TimeSlot(DMA0tickFrom, totalLat); + + //******************************************************************// + if (DMA0tickFrom > tickDMA0) + DMA0tickFrom = DMA0tickFrom + latDMA0; + else + DMA0tickFrom = tickDMA0 + latDMA0; + uint64_t tmpTick = DMA0tickFrom; + if (!FindFreeTime(ChFreeSlots[reqCh], latANTI * 2, DMA0tickFrom, tickDMA0, + conflicts)) { + if (DMA0tickFrom < ChStartPoint[reqCh]) { + DMA0tickFrom = ChStartPoint[reqCh]; + conflicts = true; + } + else + conflicts = false; + tickDMA0 = ChStartPoint[reqCh]; + } + else { + if (conflicts) + DMA0tickFrom = tickDMA0; + } + if (DMA0tickFrom == tmpTick) + InsertFreeSlot(ChFreeSlots[reqCh], latANTI * 2, DMA0tickFrom, tickDMA0, + ChStartPoint[reqCh], 1); + //******************************************************************// +#if 1 + // Manage MergedTimeSlots + if (MergedTimeSlots.size() == 0) { + MergedTimeSlots.push_back( + TimeSlot(tsMEM.StartTick, tsMEM.EndTick - tsMEM.StartTick + 1)); + } + else { + uint64_t s = tsMEM.StartTick; + uint64_t e = tsMEM.EndTick; + int spnt = 0, epnt = 0; // inside(0), rightside(1) + std::list::iterator cur; + std::list::iterator spos = MergedTimeSlots.end(); + std::list::iterator epos = MergedTimeSlots.end(); + + // find s position + cur = MergedTimeSlots.begin(); + + while (cur != MergedTimeSlots.end()) { + if (cur->StartTick <= s && s <= cur->EndTick) { + spos = cur; + spnt = 0; // inside + break; + } + + auto next = cur; + + next++; + + if ((next == MergedTimeSlots.end()) || + (next != MergedTimeSlots.end() && (s < next->StartTick))) { + spos = cur; + spnt = 1; // rightside + break; + } + + cur = next; + } + + // find e position + cur = MergedTimeSlots.begin(); + + while (cur != MergedTimeSlots.end()) { + if (cur->StartTick <= e && e <= cur->EndTick) { + epos = cur; + epnt = 0; // inside + break; + } + + auto next = cur; + + next++; + + if ((next == MergedTimeSlots.end()) || + (next != MergedTimeSlots.end() && (e < next->StartTick))) { + epos = cur; + epnt = 1; // rightside + break; + } + + cur = next; + } + + // merge + // if both side is in a merged slot, skip + if (!(spos != MergedTimeSlots.end() && epos != MergedTimeSlots.end() && + (spos == epos && spnt == 0 && epnt == 0))) { + if (spos != MergedTimeSlots.end() && + spnt == 1) { // right side of spos + bool update = false; + + if (spos == epos) { + update = true; + } + + // duration will be updated later + // Insert tmp after spos + auto tmp = MergedTimeSlots.insert( + ++spos, + TimeSlot(tsMEM.StartTick, tsMEM.EndTick - tsMEM.StartTick + 1)); + + if (update) { + epos = tmp; + } + + spos = --tmp; // update spos + } + else { + if (epos == MergedTimeSlots.end()) // both new + { + auto tmp = + TimeSlot(tsMEM.StartTick, + tsMEM.EndTick - tsMEM.StartTick + 1); // copy one + + MergedTimeSlots.insert(MergedTimeSlots.begin(), tmp); + } + else { + auto tmp = TimeSlot(tsMEM.StartTick, + 999); // duration will be updated later + spos = MergedTimeSlots.insert(MergedTimeSlots.begin(), tmp); + } + } + + if (epos != MergedTimeSlots.end()) { + if (epnt == 0) { + spos->EndTick = epos->EndTick; + } + else if (epnt == 1) { + spos->EndTick = tsMEM.EndTick; + } + + // remove [ spos->Next ~ epos ] + auto iter = spos; + + for (iter++; iter != epos;) { + iter = MergedTimeSlots.erase(iter); + } + + // We need to erase epos + MergedTimeSlots.erase(epos); + } + } + } +#endif // END MERGE TIMESLOT + } + + // print Log +#if 1 // DBG_PRINT_BUSY + if (1) { +#if DBG_PRINT_REQUEST + // DPRINTF(PAL, + // "PAL: %s PPN 0x%" PRIX64 " ch%02d die%05d : REQTime %" PRIu64 + // "\n", + // OPER_STRINFO[req.operation], req.ppn, reqCPD.Channel, + // reqDieIdx, req.arrived); // Use DPRINTF here + printCPDPBP(&reqCPD); + // DPRINTF(PAL, + // "PAL: %s PPN 0x%" PRIX64 " ch%02d die%05d : DMA0 %" PRIu64 + // " ~ %" PRIu64 " (%" PRIu64 ") , MEM %" PRIu64 " ~ %" PRIu64 + // " (%" PRIu64 ") , DMA1 %" PRIu64 " ~ %" PRIu64 " (%" PRIu64 + // ")\n", OPER_STRINFO[req.operation], req.ppn, reqCPD.Channel, + // reqDieIdx, tsDMA0->StartTick, tsDMA0->EndTick, (tsDMA0->EndTick + // - tsDMA0->StartTick + 1), tsMEM->StartTick, tsMEM->EndTick, + // (tsMEM->EndTick - tsMEM->StartTick + 1) - + // (tsDMA0->EndTick - tsDMA0->StartTick + 1) - + // (tsDMA1->EndTick - tsDMA1->StartTick + 1), + // tsDMA1->StartTick, tsDMA1->EndTick, + // (tsDMA1->EndTick - tsDMA1->StartTick + 1)); // Use DPRINTF + // here + + // DPRINTF(PAL, + // "PAL: %s PPN 0x%" PRIX64 + // " ch%02d die%05d : REQ~DMA0start(%" PRIu64 + // "), DMA0~DMA1end(%" PRIu64 ")\n", + // OPER_STRINFO[req.operation], req.ppn, reqCPD.Channel, + // reqDieIdx, (tsDMA0->StartTick - 1 - req.arrived + 1), + // (tsDMA1->EndTick - tsDMA0->StartTick + 1)); // Use DPRINTF + // here +#endif + } +#endif + + // 6) Write-back latency on RequestLL + req.finished = tsDMA1.EndTick; + + // categorize the time spent for read/write operation + std::map::iterator e; + e = OpTimeStamp[req.operation].find(tsDMA0.StartTick); + if (e != OpTimeStamp[req.operation].end()) { + if (e->second < tsDMA1.EndTick) + e->second = tsDMA1.EndTick; + } + else { + OpTimeStamp[req.operation][tsDMA0.StartTick] = tsDMA1.EndTick; + } + FlushOpTimeStamp(); + + // Update stats +#if 1 + stats->UpdateLastTick(tsDMA1.EndTick); +#if GATHER_RESOURCE_CONFLICT + stats->AddLatency(req, &reqCPD, reqDieIdx, tsDMA0, tsMEM, tsDMA1, confType); +#else + stats->AddLatency(req, &reqCPD, reqDieIdx, tsDMA0, tsMEM, tsDMA1); +#endif +#endif + + if (req.operation == OPER_ERASE || req.mergeSnapshot) { + stats->MergeSnapshot(); + } + } +} + +void PAL2::submit(Command &cmd, CPDPBP &addr) { + TimelineScheduling(cmd, addr); +} + +void PAL2::FlushATimeSlotBusyTime(std::list &tgtTimeSlot, + uint64_t currentTick, uint64_t *TimeSum) { + auto cur = tgtTimeSlot.begin(); + + while (cur != tgtTimeSlot.end()) { + if (cur->EndTick < currentTick) { + *TimeSum += (cur->EndTick - cur->StartTick + 1); + + cur = tgtTimeSlot.erase(cur); + + continue; + } + + break; + } +} + +void PAL2::FlushOpTimeStamp() // currently only used during garbage collection +{ + // flush OpTimeStamp + std::map::iterator e; + for (unsigned Oper = 0; Oper < 3; Oper++) { + uint64_t start_tick = (uint64_t)-1, end_tick = (uint64_t)-1; + for (e = OpTimeStamp[Oper].begin(); e != OpTimeStamp[Oper].end();) { + if (start_tick == (uint64_t)-1 && end_tick == (uint64_t)-1) { + start_tick = e->first; + end_tick = e->second; + } + else if (e->first < end_tick && e->second <= end_tick) { + } + else if (e->first < end_tick && e->second > end_tick) { + end_tick = e->second; + } + else if (e->first >= end_tick) { + stats->OpBusyTime[Oper] += end_tick - start_tick + 1; + start_tick = e->first; + end_tick = e->second; + } + OpTimeStamp[Oper].erase(e); + e = OpTimeStamp[Oper].begin(); + } + stats->OpBusyTime[Oper] += end_tick - start_tick + 1; + } +} + +void PAL2::FlushTimeSlots(uint64_t currentTick) { + FlushATimeSlotBusyTime(MergedTimeSlots, currentTick, &(stats->ExactBusyTime)); + + stats->Access_Capacity.update(); + stats->Ticks_Total.update(); +} + +void PAL2::FlushFreeSlots(uint64_t currentTick) { + for (uint32_t i = 0; i < pParam->channel; i++) { + FlushAFreeSlot(ChFreeSlots[i], currentTick); + } + for (uint32_t i = 0; i < totalDie; i++) { + FlushAFreeSlot(DieFreeSlots[i], currentTick); + } + + FlushATimeSlotBusyTime(MergedTimeSlots, currentTick, &(stats->ExactBusyTime)); + + stats->Access_Capacity.update(); + stats->Ticks_Total.update(); +} + +void PAL2::FlushAFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t currentTick) { + for (std::map *>::iterator e = + tgtFreeSlot.begin(); + e != tgtFreeSlot.end(); e++) { + std::map::iterator f = (e->second)->begin(); + std::map::iterator g = (e->second)->end(); + + for (; f != g;) { + // count++; + if (f->second < currentTick) + (e->second)->erase(f++); + else + break; + } + } +} + +std::list::iterator PAL2::FindFreeTime( + std::list &tgtTimeSlot, uint64_t tickLen, uint64_t fromTick) { + auto cur = tgtTimeSlot.begin(); + auto next = cur; + + while (cur != tgtTimeSlot.end()) { + // printf("FindFreeTime.FIND : cur->ST=%llu, cur->ET=%llu, next=0x%X\n", + // cur->StartTick, cur->EndTick, (unsigned int)next); //DBG + next++; + + if (next == tgtTimeSlot.end()) { + break; + } + + if (cur->EndTick < fromTick && fromTick < next->StartTick) { + if ((next->StartTick - fromTick) >= tickLen) { + // printf("FindFreeTime.RET A: cur->ET=%llu, next->ST=%llu, ft=%llu, + // tickLen=%llu\n", cur->EndTick, next->StartTick, fromTick, tickLen); + // //DBG + break; + } + } + else if (fromTick <= cur->EndTick) { + if ((next->StartTick - (cur->EndTick + 1)) >= tickLen) { + break; + } + } + + cur++; + } + + // v-- this condition looks strange? but [minus of uint64_t values] do not + // work correctly without this! + if ((tgtTimeSlot.begin()->StartTick > fromTick) && + ((tgtTimeSlot.begin()->StartTick - fromTick) >= tickLen)) { + cur = tgtTimeSlot.end(); // if there is an available time slot before first + // cmd, return NULL! + } + + return cur; +} + +bool PAL2::FindFreeTime( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t &startTick, bool &conflicts) { + auto e = tgtFreeSlot.upper_bound(tickLen); + if (e == tgtFreeSlot.end()) { + e--; // Jie: tgtFreeSlot is not empty + auto f = (e->second)->upper_bound(tickFrom); + if (f != (e->second)->begin()) { + f--; + if (f->second >= tickLen + tickFrom - (uint64_t)1) { + startTick = f->first; + conflicts = false; + return true; + } + f++; + } + while (f != (e->second)->end()) { + if (f->second >= tickLen + f->first - 1) { + startTick = f->first; + conflicts = true; + return true; + } + f++; + } + // reach this means no FreeSlot satisfy the requirement; allocate unused + // slots startTick will be updated in upper function + conflicts = false; + return false; + } + if (e != tgtFreeSlot.begin()) + e--; + uint64_t minTick = (uint64_t)-1; + while (e != tgtFreeSlot.end()) { + std::map::iterator f = + (e->second)->upper_bound(tickFrom); + if (f != (e->second)->begin()) { + f--; + if (f->second >= + tickLen + tickFrom - (uint64_t)1) { // this free slot is + // best fit one, skip + // checking others + startTick = f->first; + conflicts = false; + return true; + } + f++; + } + while (f != (e->second)->end()) { + if (f->second >= tickLen + f->first - (uint64_t)1) { + if (minTick == (uint64_t)-1 || minTick > f->first) { + conflicts = true; + minTick = f->first; + } + break; + } + f++; + } + e++; + } + if (minTick == (uint64_t)-1) { + // startTick will be updated in upper function + conflicts = false; + return false; + } + else { + startTick = minTick; + return true; + } +} + +void PAL2::InsertFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t startTick, + uint64_t &startPoint, bool split) { + if (startTick == startPoint) { + if (tickFrom == startTick) { + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, startPoint); + startPoint = startPoint + tickLen; // Jie: just need to shift startPoint + } + else { + assert(tickFrom > startTick); + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, tickFrom); + startPoint = tickFrom + tickLen; + AddFreeSlot(tgtFreeSlot, tickFrom - startTick, startTick); + } + } + else { + std::pair *>::iterator, + std::map *>::iterator> + ePair; + ePair = tgtFreeSlot.equal_range(tickLen); + std::map::iterator f; + std::map *>::iterator e = + tgtFreeSlot.upper_bound(tickLen); + if (e != tgtFreeSlot.begin()) + e--; + while (e != tgtFreeSlot.end()) { + f = e->second->find(startTick); + if (f != e->second->end()) { + uint64_t tmpStartTick = f->first; + uint64_t tmpEndTick = f->second; + e->second->erase(f); + if (tmpStartTick < tickFrom) { + AddFreeSlot(tgtFreeSlot, tickFrom - tmpStartTick, tmpStartTick); + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, tickFrom); + assert(tmpEndTick - tickFrom + 1 >= tickLen); + if (tmpEndTick > tickLen + tickFrom - (uint64_t)1) { + AddFreeSlot(tgtFreeSlot, tmpEndTick - (tickFrom + tickLen - 1), + tickFrom + tickLen); + } + } + else { + assert(tmpStartTick == tickFrom); + assert(tmpEndTick - tickFrom + 1 >= tickLen); + if (split) + AddFreeSlot(tgtFreeSlot, tickLen, tmpStartTick); + if (tmpEndTick > tickLen + tickFrom - (uint64_t)1) { + AddFreeSlot(tgtFreeSlot, tmpEndTick - (tickFrom + tickLen - 1), + tmpStartTick + tickLen); + } + } + break; + } + e++; + } + } +} + +void PAL2::AddFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom) { + std::map *>::iterator e; + e = tgtFreeSlot.upper_bound(tickLen); + if (e != tgtFreeSlot.begin()) { + e--; + (e->second)->insert(std::pair( + tickFrom, tickFrom + tickLen - (uint64_t)1)); + } +} +// PPN number conversion +uint32_t PAL2::CPDPBPtoDieIdx(CPDPBP *pCPDPBP) { + //[Channel][Package][Die]; + uint32_t ret = 0; + ret += pCPDPBP->Die; + ret += pCPDPBP->Package * pParam->die; + ret += pCPDPBP->Channel * pParam->die * pParam->package; + + return ret; +} + +void PAL2::printCPDPBP(CPDPBP *) {} +// void PAL2::printCPDPBP(CPDPBP *pCPDPBP) { +// uint32_t *pCPDPBP_IDX = ((uint32_t *)pCPDPBP); +// +// DPRINTF(PAL, "PAL: %7s | %7s | %7s | %7s | %7s | %7s\n", +// ADDR_STRINFO[gconf->AddrSeq[0]], ADDR_STRINFO[gconf->AddrSeq[1]], +// ADDR_STRINFO[gconf->AddrSeq[2]], ADDR_STRINFO[gconf->AddrSeq[3]], +// ADDR_STRINFO[gconf->AddrSeq[4]], +// ADDR_STRINFO[gconf->AddrSeq[5]]); // Use DPRINTF here +// DPRINTF(PAL, "PAL: %7u | %7u | %7u | %7u | %7u | %7u\n", +// pCPDPBP_IDX[gconf->AddrSeq[0]], pCPDPBP_IDX[gconf->AddrSeq[1]], +// pCPDPBP_IDX[gconf->AddrSeq[2]], pCPDPBP_IDX[gconf->AddrSeq[3]], +// pCPDPBP_IDX[gconf->AddrSeq[4]], +// pCPDPBP_IDX[gconf->AddrSeq[5]]); // Use DPRINTF here +// } + +void PAL2::PPNdisassemble(uint64_t *pPPN, CPDPBP *pCPDPBP) { + uint32_t *pCPDPBP_IDX = ((uint32_t *)pCPDPBP); + uint64_t tmp_MOD = *pPPN; + uint8_t *AS = AddrRemap; + uint32_t *RS = RearrangedSizes; + for (uint32_t i = 0; i < 6; i++) { + pCPDPBP_IDX[i] = 0; + } + if (RS[6] == 0) // there is no misalignment + { + pCPDPBP_IDX[AS[0]] = tmp_MOD / (RS[5] * RS[4] * RS[3] * RS[2] * RS[1]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4] * RS[3] * RS[2] * RS[1]); + + pCPDPBP_IDX[AS[1]] = tmp_MOD / (RS[5] * RS[4] * RS[3] * RS[2]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4] * RS[3] * RS[2]); + + pCPDPBP_IDX[AS[2]] = tmp_MOD / (RS[5] * RS[4] * RS[3]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4] * RS[3]); + + pCPDPBP_IDX[AS[3]] = tmp_MOD / (RS[5] * RS[4]); + tmp_MOD = tmp_MOD % (RS[5] * RS[4]); + + pCPDPBP_IDX[AS[4]] = tmp_MOD / (RS[5]); + tmp_MOD = tmp_MOD % (RS[5]); + + pCPDPBP_IDX[AS[5]] = tmp_MOD; + } + else { + uint32_t tmp_size = RS[6] * RS[5] * RS[4] * RS[3] * RS[2] * RS[1] * RS[0]; + for (int i = 0; i < (4 - AS[6]); i++) { + tmp_size /= RS[i]; + pCPDPBP_IDX[AS[i]] = tmp_MOD / tmp_size; + tmp_MOD = tmp_MOD % tmp_size; + } + tmp_size /= RS[6]; + uint32_t tmp = tmp_MOD / tmp_size; + tmp_MOD = tmp_MOD % tmp_size; + for (int i = (4 - AS[6]); i < 6; i++) { + tmp_size /= RS[i]; + pCPDPBP_IDX[AS[i]] = tmp_MOD / tmp_size; + tmp_MOD = tmp_MOD % tmp_size; + } + pCPDPBP_IDX[AS[5 - AS[6]]] *= tmp; + } + +#if DBG_PRINT_PPN + DPRINTF(PAL, "PAL: 0x%llX (%llu) ==>\n", *pPPN, + *pPPN); // Use DPRINTF here + printCPDPBP(pCPDPBP); +#endif +} + +void PAL2::AssemblePPN(CPDPBP *pCPDPBP, uint64_t *pPPN) { + uint64_t AddrPPN = 0; + + // with re-arrange ... I hate current structure! too dirty even made with + // FOR-LOOP! (less-readability) + uint32_t *pCPDPBP_IDX = ((uint32_t *)pCPDPBP); + uint8_t *AS = AddrRemap; + uint32_t *RS = RearrangedSizes; + AddrPPN += pCPDPBP_IDX[AS[5]]; + AddrPPN += pCPDPBP_IDX[AS[4]] * (RS[5]); + AddrPPN += pCPDPBP_IDX[AS[3]] * (RS[5] * RS[4]); + AddrPPN += pCPDPBP_IDX[AS[2]] * (RS[5] * RS[4] * RS[3]); + AddrPPN += pCPDPBP_IDX[AS[1]] * (RS[5] * RS[4] * RS[3] * RS[2]); + AddrPPN += pCPDPBP_IDX[AS[0]] * (RS[5] * RS[4] * RS[3] * RS[2] * RS[1]); + + *pPPN = AddrPPN; + +#if DBG_PRINT_PPN + printCPDPBP(pCPDPBP); + DPRINTF(PAL, "PAL ==> 0x%llx (%llu)\n", *pPPN, *pPPN); // Use DPRINTF here +#endif +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2.h new file mode 100644 index 0000000000..75b56398f7 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2.h @@ -0,0 +1,105 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#ifndef __PAL2_h__ +#define __PAL2_h__ + +#include "util/old/SimpleSSD_types.h" + +#include "Latency.h" +#include "PALStatistics.h" +#include "pal/pal.hh" + +#include "PAL2_TimeSlot.h" + +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +class PALStatistics; + +class PAL2 // let's not inherit PAL1 +{ + public: + PAL2(PALStatistics *statistics, SimpleSSD::PAL::Parameter *p, + SimpleSSD::ConfigReader *c, Latency *l); + ~PAL2(); + + SimpleSSD::PAL::Parameter *pParam; + Latency *lat; + PALStatistics *stats; // statistics of PAL2, not created by itself + + std::list MergedTimeSlots; // for gathering busy time + + uint64_t totalDie; + + std::map OpTimeStamp[3]; + + std::map *> *ChFreeSlots; + uint64_t *ChStartPoint; // record the start point of rightmost free slot + std::map *> *DieFreeSlots; + uint64_t *DieStartPoint; + + void submit(Command &cmd, CPDPBP &addr); + void TimelineScheduling(Command &req, CPDPBP &reqCPD); + void FlushTimeSlots(uint64_t currentTick); + void FlushOpTimeStamp(); + void FlushATimeSlotBusyTime(std::list &tgtTimeSlot, + uint64_t currentTick, uint64_t *TimeSum); + + // you can insert a tickLen + // TimeSlot after Returned + // TimeSlot. + std::list::iterator FindFreeTime(std::list &tgtTimeSlot, + uint64_t tickLen, + uint64_t tickFrom); + + // Jie: return: FreeSlot is found? + bool FindFreeTime( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t &startTick, + bool &conflicts); + void InsertFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom, uint64_t startTick, + uint64_t &startPoint, bool split); + void AddFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t tickLen, uint64_t tickFrom); + void FlushFreeSlots(uint64_t currentTick); + void FlushAFreeSlot( + std::map *> &tgtFreeSlot, + uint64_t currentTick); + + // PPN Conversion related //ToDo: Shifted-Mode is also required for better + // performance. + uint32_t RearrangedSizes[7]; + uint8_t AddrRemap[6]; + uint32_t CPDPBPtoDieIdx(CPDPBP *pCPDPBP); + void printCPDPBP(CPDPBP *pCPDPBP); + void PPNdisassemble(uint64_t *pPPN, CPDPBP *pCPDPBP); + void AssemblePPN(CPDPBP *pCPDPBP, uint64_t *pPPN); +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2_TimeSlot.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2_TimeSlot.cc new file mode 100644 index 0000000000..bc3ff93756 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2_TimeSlot.cc @@ -0,0 +1,25 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#include "PAL2_TimeSlot.h" + +TimeSlot::TimeSlot(uint64_t startTick, uint64_t duration) { + StartTick = startTick; + EndTick = startTick + duration - 1; +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2_TimeSlot.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2_TimeSlot.h new file mode 100644 index 0000000000..4ed6563029 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PAL2_TimeSlot.h @@ -0,0 +1,43 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#ifndef __PAL2_TimeSlot_h__ +#define __PAL2_TimeSlot_h__ + +#include "util/old/SimpleSSD_types.h" + +#include +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +struct TimeSlot { + uint64_t StartTick; + uint64_t EndTick; + + TimeSlot(uint64_t startTick, uint64_t duration); + TimeSlot() : StartTick(0ull), EndTick(0ull){}; +}; + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/PALStatistics.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PALStatistics.cc new file mode 100644 index 0000000000..e1ba2ea2c0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PALStatistics.cc @@ -0,0 +1,1111 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#include "PALStatistics.h" +#include "util/algorithm.hh" +#include "util/old/SimpleSSD_types.h" + +char ADDR_STRINFO[ADDR_NUM][10] = {"Channel", "Package", "Die", + "Plane", "Block", "Page"}; +char ADDR_STRINFO2[ADDR_NUM][15] = {"ADDR_CHANNEL", "ADDR_PACKAGE", + "ADDR_DIE", "ADDR_PLANE", + "ADDR_BLOCK", "ADDR_PAGE"}; +char OPER_STRINFO[OPER_NUM][10] = {"R", "W", "E"}; +char OPER_STRINFO2[OPER_NUM][10] = {"Read ", "Write", "Erase"}; +char BUSY_STRINFO[BUSY_NUM][10] = {"IDLE", "DMA0", "MEM", + "DMA1WAIT", "DMA1", "END"}; +char PAGE_STRINFO[PAGE_NUM][10] = {"LSB", "CSB", "MSB"}; +char NAND_STRINFO[NAND_NUM][10] = {"SLC", "MLC", "TLC"}; +#if GATHER_RESOURCE_CONFLICT +char CONFLICT_STRINFO[CONFLICT_NUM][10] = {"NONE", "DMA0", "MEM", "DMA1"}; +#endif + +PALStatistics::Counter::Counter() { + init(); +} + +void PALStatistics::Counter::init() { + cnt = 0; +} + +void PALStatistics::Counter::add() { + cnt++; +} + +PALStatistics::CounterOper::CounterOper() { + init(); +} + +void PALStatistics::CounterOper::init() { + for (int i = 0; i < OPER_ALL; i++) + cnts[i].init(); +} + +void PALStatistics::CounterOper::add(uint32_t oper) { + cnts[oper].add(); + cnts[OPER_NUM].add(); +} + +void PALStatistics::CounterOper::printstat(const char *) {} +// void PALStatistics::CounterOper::printstat(const char *namestr) { +// char OPER_STR[OPER_ALL][8] = {"Read ", "Write", "Erase", "Total"}; +// DPRINTF(PAL, "[ %s ]:\n", namestr); +// DPRINTF(PAL, "OPER, COUNT\n"); +// for (int i = 0; i < OPER_ALL; i++) { +// DPRINTF(PAL, "%s, %" PRIu64 "\n", OPER_STR[i], cnts[i].cnt); +// } +// } + +PALStatistics::Value::Value() { + init(); +} + +void PALStatistics::Value::init() { + sum = 0; + cnt = 0; + sampled_sum = 0; + sampled_cnt = 0; + minval = MAX64; + maxval = 0; + legacy_sum = 0; + legacy_cnt = 0; + legacy_minval = MAX64; + legacy_maxval = 0; +} +void PALStatistics::Value::backup() { + sampled_sum = sum; + sampled_cnt = cnt; +} + +void PALStatistics::Value::update() { + legacy_sum = sum; + legacy_cnt = cnt; + legacy_minval = minval; + legacy_maxval = maxval; +} + +void PALStatistics::Value::add(double val) { + sum += val; + cnt += 1; + minval = MIN(val, minval); + maxval = MAX(val, maxval); +} + +double PALStatistics::Value::avg() { + return SAFEDIV(sum, cnt); +} + +double PALStatistics::Value::legacy_avg() { + return SAFEDIV(legacy_sum, legacy_cnt); +} + +PALStatistics::ValueOper::ValueOper() { + init(); +} +PALStatistics::ValueOper::ValueOper(ValueOper *_ValueOper) { + for (int i = 0; i < OPER_ALL; i++) { + vals[i].sum = _ValueOper->vals[i].sum; + vals[i].cnt = _ValueOper->vals[i].cnt; + vals[i].sampled_sum = _ValueOper->vals[i].sampled_sum; + vals[i].sampled_cnt = _ValueOper->vals[i].sampled_cnt; + vals[i].minval = _ValueOper->vals[i].minval; + vals[i].maxval = _ValueOper->vals[i].maxval; + vals[i].legacy_sum = _ValueOper->vals[i].legacy_sum; + vals[i].legacy_cnt = _ValueOper->vals[i].legacy_cnt; + vals[i].legacy_minval = _ValueOper->vals[i].legacy_minval; + vals[i].legacy_maxval = _ValueOper->vals[i].legacy_maxval; + } +} + +void PALStatistics::ValueOper::init() { + for (int i = 0; i < OPER_ALL; i++) + vals[i].init(); +} + +void PALStatistics::ValueOper::update() { + for (int i = 0; i < OPER_ALL; i++) + vals[i].update(); +} + +void PALStatistics::ValueOper::add(uint32_t oper, double val) { + vals[oper].add(val); + vals[OPER_NUM].add(val); +} + +void PALStatistics::ValueOper::exclusive_add(uint32_t oper, double val) { + vals[oper].add(val); +} + +void PALStatistics::ValueOper::printstat(const char *) {} +// void PALStatistics::ValueOper::printstat( +// const char *namestr) // This is only used by access capacity +// { +// char OPER_STR[OPER_ALL][8] = {"Read ", "Write", "Erase", "Total"}; +// DPRINTF(PAL, "[ %s ]:\n", namestr); +// DPRINTF(PAL, "OPER, AVERAGE, COUNT, TOTAL, MIN, MAX\n"); +// for (int i = 0; i < OPER_ALL; i++) { +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s, ( NO DATA )\n", OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s, %" PRIu64 ", %" PRIu64 ", %" PRIu64 ", %" PRIu64 ", %" +// PRIu64 +// "\n", +// OPER_STR[i], (uint64_t)vals[i].avg(), (uint64_t)vals[i].cnt, +// (uint64_t)vals[i].sum, (uint64_t)vals[i].minval, +// (uint64_t)vals[i].maxval); +// } +// } +// } + +void PALStatistics::getTickStat(OperStats &stat) { + stat.read = Ticks_Total.vals[OPER_READ].avg(); + stat.write = Ticks_Total.vals[OPER_WRITE].avg(); + stat.erase = Ticks_Total.vals[OPER_ERASE].avg(); + stat.total = Ticks_Total.vals[OPER_NUM].avg(); +} + +void PALStatistics::getEnergyStat(OperStats &stat) { + // val = [pJ] / [10^6] = [uJ] + stat.read = Energy_Total.vals[OPER_READ].sum / 1000000; // uJ + stat.write = Energy_Total.vals[OPER_WRITE].sum / 1000000; // uJ + stat.erase = Energy_Total.vals[OPER_ERASE].sum / 1000000; // uJ + stat.total = stat.read + stat.write + stat.erase; +} + +void PALStatistics::ValueOper::printstat_energy(const char *) {} +// void PALStatistics::ValueOper::printstat_energy(const char *namestr) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// printf("[ %s ]:\n", namestr); +// printf("PAL: OPER, AVERAGE(nJ), COUNT, TOTAL(uJ)\n"); +// +// for (int i = 0; i < OPER_ALL; i++) { +// if (vals[i].cnt == 0) { +// printf("PAL: %s, ( NO DATA )\n", OPER_STR[i]); +// } +// else { +// printf("PAL: %s, %llu, %llu, %llu\n", OPER_STR[i], +// (uint64_t)vals[i].avg() / 1000000, (uint64_t)vals[i].cnt, +// (uint64_t)vals[i].sum / 1000000); +// } +// } +// } + +// get average tick spent in each step during read +void PALStatistics::getReadBreakdown(Breakdown &value) { + value.dma0wait = Ticks_DMA0WAIT.vals[OPER_READ].avg(); + value.dma0 = Ticks_DMA0.vals[OPER_READ].avg(); + value.mem = Ticks_MEM.vals[OPER_READ].avg(); + value.dma1wait = Ticks_DMA1WAIT.vals[OPER_READ].avg(); + value.dma1 = Ticks_DMA1.vals[OPER_READ].avg(); +} + +// get average tick spent in each step during write +void PALStatistics::getWriteBreakdown(Breakdown &value) { + value.dma0wait = Ticks_DMA0WAIT.vals[OPER_WRITE].avg(); + value.dma0 = Ticks_DMA0.vals[OPER_WRITE].avg(); + value.mem = Ticks_MEM.vals[OPER_WRITE].avg(); + value.dma1wait = Ticks_DMA1WAIT.vals[OPER_WRITE].avg(); + value.dma1 = Ticks_DMA1.vals[OPER_WRITE].avg(); +} + +void PALStatistics::getEraseBreakdown(Breakdown &value) { + value.dma0wait = Ticks_DMA0WAIT.vals[OPER_ERASE].avg(); + value.dma0 = Ticks_DMA0.vals[OPER_ERASE].avg(); + value.mem = Ticks_MEM.vals[OPER_ERASE].avg(); + value.dma1wait = Ticks_DMA1WAIT.vals[OPER_ERASE].avg(); + value.dma1 = Ticks_DMA1.vals[OPER_ERASE].avg(); +} + +void PALStatistics::getChannelActiveTime(uint32_t c, ActiveTime &stat) { + static uint32_t numOfChannel = + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + + if (c < numOfChannel) { + stat.min = Ticks_Active_ch[c].vals[OPER_NUM].minval; + stat.max = Ticks_Active_ch[c].vals[OPER_NUM].maxval; + stat.average = Ticks_Active_ch[c].vals[OPER_NUM].avg(); + } +} + +void PALStatistics::getDieActiveTime(uint32_t d, ActiveTime &stat) { + if (d < totalDie) { + stat.min = Ticks_Active_die[d].vals[OPER_NUM].minval; + stat.max = Ticks_Active_die[d].vals[OPER_NUM].maxval; + stat.average = Ticks_Active_die[d].vals[OPER_NUM].avg(); + } +} + +void PALStatistics::getChannelActiveTimeAll(ActiveTime &stat) { + static uint32_t numOfChannel = + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + ActiveTime tmp; + + stat.min = (double)std::numeric_limits::max(); + stat.max = 0.; + stat.average = 0.; + + for (uint32_t i = 0; i < numOfChannel; i++) { + getChannelActiveTime(i, tmp); + + if (stat.min > tmp.min) { + stat.min = tmp.min; + } + if (stat.max < tmp.max) { + stat.max = tmp.max; + } + + stat.average += tmp.average; + } + + stat.average /= numOfChannel; +} + +void PALStatistics::getDieActiveTimeAll(ActiveTime &stat) { + ActiveTime tmp; + + stat.min = (double)std::numeric_limits::max(); + stat.max = 0.; + stat.average = 0.; + + for (uint32_t i = 0; i < totalDie; i++) { + getDieActiveTime(i, tmp); + + if (stat.min > tmp.min) { + stat.min = tmp.min; + } + if (stat.max < tmp.max) { + stat.max = tmp.max; + } + + stat.average += tmp.average; + } + + stat.average /= totalDie; +} + +void PALStatistics::PrintDieIdleTicks(uint32_t, uint64_t, uint64_t) {} +// void PALStatistics::PrintDieIdleTicks(uint32_t die_num, uint64_t sim_time_ps, +// uint64_t idle_power_nw) { +// uint64_t active_time_ps = Ticks_Active_die[die_num].vals[OPER_ALL - 1].sum; +// uint64_t idle_time_ps = sim_time_ps - active_time_ps; +// uint64_t idle_energy = idle_power_nw * idle_time_ps; +// +// printf("PAL: Idle(pJ), Die%d, %llu\n", die_num, idle_energy / 1000000000); +// } + +void PALStatistics::ValueOper::printstat_bandwidth(class ValueOper *, uint64_t, + uint64_t) {} +// void PALStatistics::ValueOper::printstat_bandwidth( +// class ValueOper *Access_Capacity, uint64_t ExactBusyTime, +// uint64_t LastExactBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// if (ExactBusyTime > LastExactBusyTime) { +// // +// printf("sum=%f\tsampled_sum=%f\n", Access_Capacity->vals[i].sum, +// Access_Capacity->vals[i].sampled_sum); +// this->exclusive_add( +// i, (Access_Capacity->vals[i].sum - +// Access_Capacity->vals[i].sampled_sum) * +// 1.0 / MBYTE / +// ((ExactBusyTime - LastExactBusyTime) * 1.0 / PSEC)); +// } +// if (vals[i].cnt == 0) { +// DPRINTF( +// PAL, "%s bandwidth excluding idle time (min, max, average): ( NO +// DATA +// )\n ", OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s bandwidth excluding idle time (min, max, average): %.6lf " +// "MB/s, %.6lf MB/s, %.6lf MB/s\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].sum) * 1.0 / MBYTE / +// ((ExactBusyTime)*1.0 / PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_bandwidth_widle(class ValueOper *, + uint64_t, uint64_t) {} +// void PALStatistics::ValueOper::printstat_bandwidth_widle( +// class ValueOper *Access_Capacity, uint64_t ExecutionTime, +// uint64_t LastExecutionTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// assert(ExecutionTime > LastExecutionTime); +// this->exclusive_add( +// i, +// (Access_Capacity->vals[i].sum - Access_Capacity->vals[i].sampled_sum) +// * +// 1.0 / MBYTE / ((ExecutionTime - LastExecutionTime) * 1.0 / +// PSEC)); +// +// if (vals[i].cnt == 0) { +// DPRINTF( +// PAL, "%s bandwidth including idle time (min, max, average): ( NO +// DATA +// )\n ", OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s bandwidth including idle time (min, max, average): %.6lf " +// "MB/s, %.6lf MB/s, %.6lf MB/s\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].sum) * 1.0 / MBYTE / +// ((ExecutionTime)*1.0 / PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_oper_bandwidth(class ValueOper *, + uint64_t *, + uint64_t *) {} +// void PALStatistics::ValueOper::printstat_oper_bandwidth( +// class ValueOper *Access_Capacity, uint64_t *OpBusyTime, +// uint64_t *LastOpBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < 3; i++) // only read/write/erase +// { +// if (OpBusyTime[i] > LastOpBusyTime[i]) +// this->exclusive_add( +// i, (Access_Capacity->vals[i].sum - +// Access_Capacity->vals[i].sampled_sum) * +// 1.0 / MBYTE / +// ((OpBusyTime[i] - LastOpBusyTime[i]) * 1.0 / PSEC)); +// +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s-only bandwidth (min, max, average): ( NO DATA )\n", +// OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s-only bandwidth (min, max, average): %.6lf MB/s, %.6lf MB/s, +// " +// "%.6lf MB/s\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].sum) * 1.0 / MBYTE / +// ((OpBusyTime[i]) * 1.0 / PSEC)); +// } +// } +// } +void PALStatistics::ValueOper::printstat_iops(class ValueOper *, uint64_t, + uint64_t) {} +// void PALStatistics::ValueOper::printstat_iops(class ValueOper +// *Access_Capacity, +// uint64_t ExactBusyTime, +// uint64_t LastExactBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// if (ExactBusyTime > LastExactBusyTime) +// this->exclusive_add( +// i, (Access_Capacity->vals[i].cnt - +// Access_Capacity->vals[i].sampled_cnt) * +// 1.0 / ((ExactBusyTime - LastExactBusyTime) * 1.0 / PSEC)); +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s IOPS excluding idle time (min, max, average): ( NO +// DATA +// )\n ", OPER_STR[i]); +// } +// else { +// DPRINTF( +// PAL, +// "%s IOPS excluding idle time (min, max, average): %.6lf, %.6lf, " +// "%.6lf\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].cnt) * 1.0 / ((ExactBusyTime)*1.0 / +// PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_iops_widle(class ValueOper *, uint64_t, + uint64_t) {} +// void PALStatistics::ValueOper::printstat_iops_widle( +// class ValueOper *Access_Capacity, uint64_t ExecutionTime, +// uint64_t LastExecutionTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// this->exclusive_add( +// i, +// (Access_Capacity->vals[i].cnt - Access_Capacity->vals[i].sampled_cnt) +// * +// 1.0 / ((ExecutionTime - LastExecutionTime) * 1.0 / PSEC)); +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, +// "%s IOPS including idle time (min, max, average): ( NO DATA +// )\n", OPER_STR[i]); +// } +// else { +// DPRINTF( +// PAL, +// "%s IOPS including idle time (min, max, average): %.6lf, %.6lf, " +// "%.6lf\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].cnt) * 1.0 / ((ExecutionTime)*1.0 / +// PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_oper_iops(class ValueOper *, + uint64_t *, uint64_t *) {} +// void PALStatistics::ValueOper::printstat_oper_iops( +// class ValueOper *Access_Capacity, uint64_t *OpBusyTime, +// uint64_t *LastOpBusyTime) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < 3; i++) // only read/write/erase +// { +// if (OpBusyTime[i] > LastOpBusyTime[i]) +// this->exclusive_add( +// i, (Access_Capacity->vals[i].cnt - +// Access_Capacity->vals[i].sampled_cnt) * +// 1.0 / ((OpBusyTime[i] - LastOpBusyTime[i]) * 1.0 / PSEC)); +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s-only IOPS (min, max, average): ( NO DATA )\n", +// OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, "%s-only IOPS (min, max, average): %.6lf, %.6lf, %.6lf\n", +// OPER_STR[i], vals[i].minval, vals[i].maxval, +// (Access_Capacity->vals[i].cnt) * 1.0 / +// ((OpBusyTime[i]) * 1.0 / PSEC)); +// } +// } +// } + +void PALStatistics::ValueOper::printstat_latency(const char *) {} +// void PALStatistics::ValueOper::printstat_latency(const char *namestr) { +// char OPER_STR[OPER_ALL][8] = {"Read", "Write", "Erase", "Total"}; +// for (int i = 0; i < OPER_ALL; i++) { +// if (vals[i].cnt == 0) { +// DPRINTF(PAL, "%s latency (min, max, average): ( NO DATA )\n", +// OPER_STR[i]); +// } +// else { +// DPRINTF(PAL, +// "%s latency (min, max, average): %" PRIu64 " us, %" PRIu64 +// " us, %" PRIu64 " us\n", +// OPER_STR[i], (uint64_t)(vals[i].minval * 1.0 / 1000000), +// (uint64_t)(vals[i].maxval * 1.0 / 1000000), +// (uint64_t)(vals[i].avg() * 1.0 / 1000000)); +// } +// } +// } + +PALStatistics::PALStatistics(SimpleSSD::ConfigReader *c, Latency *l) + : gconf(c), lat(l) { + LastTick = 0; + + InitStats(); + + SampledTick = 0; + skip = true; +} + +PALStatistics::~PALStatistics() { + // PrintStats(curTick()); + ClearStats(); +} + +void PALStatistics::ResetStats() { + ClearStats(); + InitStats(); +} + +void PALStatistics::InitStats() { + sim_start_time_ps = 0; + + ExactBusyTime = 0; + LastExactBusyTime = 0; + LastExecutionTime = 0; + OpBusyTime[0] = OpBusyTime[1] = OpBusyTime[2] = 0; + LastOpBusyTime[0] = LastOpBusyTime[1] = LastOpBusyTime[2] = 0; + + totalDie = + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + totalDie *= + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_PACKAGE); + totalDie *= gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_DIE); + + PPN_requested_ch = new CounterOper[gconf->readUint( + SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL)]; + PPN_requested_die = new CounterOper[totalDie]; + Ticks_Active_ch = new ValueOper[gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::PAL_CHANNEL)]; + Ticks_Active_die = new ValueOper[totalDie]; + + PPN_requested_rwe.init(); + for (int j = 0; j < PAGE_ALL; j++) { + PPN_requested_pagetype[j].init(); + }; + // PPN_requested_ch + // PPN_requested_die + CF_DMA0_dma.init(); + CF_DMA0_mem.init(); + CF_DMA0_none.init(); + CF_DMA1_dma.init(); + CF_DMA1_none.init(); + + Ticks_DMA0WAIT.init(); + Ticks_DMA0.init(); + Ticks_MEM.init(); + Ticks_DMA1WAIT.init(); + Ticks_DMA1.init(); + Ticks_Total.init(); + Ticks_TotalOpti.init(); + // Ticks_Active_ch + Energy_DMA0.init(); + Energy_MEM.init(); + Energy_DMA1.init(); + Energy_Total.init(); + + // Ticks_Active_ch + // Ticks_Active_die + Access_Capacity.init(); + Access_Bandwidth.init(); + Access_Bandwidth_widle.init(); + Access_Oper_Bandwidth.init(); + Access_Iops.init(); + Access_Iops_widle.init(); + Access_Oper_Iops.init(); +} + +void PALStatistics::ClearStats() { + delete[] PPN_requested_ch; + delete[] PPN_requested_die; + delete[] Ticks_Active_ch; + delete[] Ticks_Active_die; + + for (auto &iter : Ticks_Total_snapshot) { + delete iter.second; + } + + for (auto &iter : Access_Capacity_snapshot) { + delete iter.second; + } +} + +void PALStatistics::UpdateLastTick(uint64_t tick) { + if (LastTick < tick) + LastTick = tick; +} + +uint64_t PALStatistics::GetLastTick() { + return LastTick; +} + +void PALStatistics::MergeSnapshot() { + if (Ticks_Total_snapshot.size() != 0) { + std::map::iterator e = Ticks_Total_snapshot.end(); + e--; + for (std::map::iterator f = + Ticks_Total_snapshot.begin(); + f != e;) { + delete f->second; + Ticks_Total_snapshot.erase(f++); + } + } + if (Access_Capacity_snapshot.size() != 0) { + std::map::iterator e = + Access_Capacity_snapshot.end(); + e--; + for (std::map::iterator f = + Access_Capacity_snapshot.begin(); + f != e;) { + delete f->second; + Access_Capacity_snapshot.erase(f++); + } + } +} + +#if GATHER_RESOURCE_CONFLICT +void PALStatistics::AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, + TimeSlot &DMA0, TimeSlot &MEM, TimeSlot &DMA1, + uint8_t confType) +#else +void PALStatistics::AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, + TimeSlot &DMA0, TimeSlot &MEM, TimeSlot &DMA1) +#endif +{ + uint32_t oper = CMD.operation; + uint32_t chIdx = CPD->Channel; + uint64_t time_all[TICK_STAT_NUM]; + uint8_t pageType = lat->GetPageType(CPD->Page); + memset(time_all, 0, sizeof(time_all)); + + /* + TICK_IOREQUESTED, CMD.arrived_time + TICK_DMA0WAIT, let it 0 + TICK_DMA0, DMA0->StartTick + TICK_MEM, MEM->StartTick + TICK_DMA1WAIT, + TICK_DMA1, DMA1->StartTick + TICK_IOEND, DMA1->TickEnd + */ + + time_all[TICK_DMA0WAIT] = + DMA0.StartTick - + CMD.arrived; // FETCH_WAIT --> when DMA0 couldn't start immediatly + time_all[TICK_DMA0] = lat->GetLatency(CPD->Page, CMD.operation, BUSY_DMA0); + time_all[TICK_DMA0_SUSPEND] = 0; // no suspend in new design + time_all[TICK_MEM] = lat->GetLatency(CPD->Page, CMD.operation, BUSY_MEM); + time_all[TICK_DMA1WAIT] = + (MEM.EndTick - MEM.StartTick + 1) - + (lat->GetLatency(CPD->Page, CMD.operation, BUSY_DMA0) + + lat->GetLatency(CPD->Page, CMD.operation, BUSY_MEM) + + lat->GetLatency(CPD->Page, CMD.operation, + BUSY_DMA1)); // --> when DMA1 didn't start immediatly. + time_all[TICK_DMA1] = lat->GetLatency(CPD->Page, CMD.operation, BUSY_DMA1); + time_all[TICK_DMA1_SUSPEND] = 0; // no suspend in new design + time_all[TICK_FULL] = + DMA1.EndTick - CMD.arrived + 1; // D0W+D0+M+D1W+D1 full latency + time_all[TICK_PROC] = time_all[TICK_DMA0] + time_all[TICK_MEM] + + time_all[TICK_DMA1]; // OPTIMUM_TIME + + PPN_requested_rwe.add(oper); + PPN_requested_pagetype[pageType].add(oper); + PPN_requested_ch[chIdx].add(oper); // PPN_requested_ch[ch#] + PPN_requested_die[dieIdx].add(oper); // PPN_requested_die[die#] + + if (confType & CONFLICT_DMA0) + CF_DMA0_dma.add(oper); + if (confType & CONFLICT_MEM) + CF_DMA0_mem.add(oper); + if (!(confType & (CONFLICT_DMA0 | CONFLICT_MEM))) + CF_DMA0_none.add(oper); + + if (confType & CONFLICT_DMA1) + CF_DMA1_dma.add(oper); + if (!(confType & CONFLICT_DMA1)) + CF_DMA1_none.add(oper); + + Ticks_DMA0WAIT.add(oper, time_all[TICK_DMA0WAIT]); + Ticks_DMA0.add(oper, time_all[TICK_DMA0]); + Ticks_MEM.add(oper, time_all[TICK_MEM]); + Ticks_DMA1WAIT.add(oper, time_all[TICK_DMA1WAIT]); + Ticks_DMA1.add(oper, time_all[TICK_DMA1]); + Ticks_Total.add(oper, time_all[TICK_FULL]); + //*********************************************** + // energy = [nW] * [ps] / [10^9] = [pJ] + uint64_t energy_dma0 = lat->GetPower(CMD.operation, BUSY_DMA0) * + time_all[TICK_DMA0] / 1000000000; + uint64_t energy_mem = + lat->GetPower(CMD.operation, BUSY_MEM) * time_all[TICK_MEM] / 1000000000; + uint64_t energy_dma1 = lat->GetPower(CMD.operation, BUSY_DMA1) * + time_all[TICK_DMA1] / 1000000000; + Energy_DMA0.add(oper, energy_dma0); + Energy_MEM.add(oper, energy_mem); + Energy_DMA1.add(oper, energy_dma1); + Energy_Total.add(oper, energy_dma0 + energy_mem + energy_dma1); + // printf("[Energy(fJ) of Oper(%d)] DMA0(%llu) MEM(%llu) DMA1(%llu)\n", oper, + // energy_dma0, energy_mem, energy_dma1); + uint64_t finished_time = CMD.finished; + uint64_t update_point = finished_time / EPOCH_INTERVAL; + std::map::iterator e = + Ticks_Total_snapshot.find(update_point); + if (e != Ticks_Total_snapshot.end()) + e->second->add(oper, time_all[TICK_FULL]); + else { + e = Ticks_Total_snapshot.upper_bound(update_point); + if (e != Ticks_Total_snapshot.end()) { + if (e != Ticks_Total_snapshot.begin()) { + e--; + Ticks_Total_snapshot[update_point] = new ValueOper(e->second); + } + else { + Ticks_Total_snapshot[update_point] = new ValueOper(); + } + } + else { + if (Ticks_Total_snapshot.size() == 0) + Ticks_Total_snapshot[update_point] = new ValueOper(); + else { + e--; + Ticks_Total_snapshot[update_point] = new ValueOper(e->second); + } + } + Ticks_Total_snapshot[update_point]->add(oper, time_all[TICK_FULL]); + } + + e = Ticks_Total_snapshot.upper_bound(update_point); + while (e != Ticks_Total_snapshot.end()) { + e->second->add(oper, time_all[TICK_FULL]); + + e = Ticks_Total_snapshot.upper_bound(e->first); + } + //*********************************************** + Ticks_TotalOpti.add(oper, time_all[TICK_PROC]); + Ticks_Active_ch[chIdx].add(oper, time_all[TICK_DMA0] + time_all[TICK_DMA1]); + Ticks_Active_die[dieIdx].add(oper, + (time_all[TICK_DMA0] + time_all[TICK_MEM] + + time_all[TICK_DMA1WAIT] + time_all[TICK_DMA1])); + if (oper == OPER_ERASE) + Access_Capacity.add( + oper, + gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + Access_Capacity.add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + //************************************************ + update_point = finished_time / EPOCH_INTERVAL; + std::map::iterator f = + Access_Capacity_snapshot.find(update_point); + if (f != Access_Capacity_snapshot.end()) { + if (oper == OPER_ERASE) + f->second->add(oper, + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + f->second->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + } + else { + f = Access_Capacity_snapshot.upper_bound(update_point); + if (f != Access_Capacity_snapshot.end()) { + if (f != Access_Capacity_snapshot.begin()) { + f--; + Access_Capacity_snapshot[update_point] = new ValueOper(f->second); + } + else { + Access_Capacity_snapshot[update_point] = new ValueOper(); + } + } + else { + if (Access_Capacity_snapshot.size() == 0) + Access_Capacity_snapshot[update_point] = new ValueOper(); + else { + f--; + Access_Capacity_snapshot[update_point] = new ValueOper(f->second); + } + } + + if (oper == OPER_ERASE) + Access_Capacity_snapshot[update_point]->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + Access_Capacity_snapshot[update_point]->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + } + f = Access_Capacity_snapshot.upper_bound(update_point); + while (f != Access_Capacity_snapshot.end()) { + if (oper == OPER_ERASE) + f->second->add(oper, + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE) * + gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE)); // ERASE + else + f->second->add( + oper, gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::NAND_PAGE_SIZE)); // READ,WRITE + f = Access_Capacity_snapshot.upper_bound(f->first); + } + //************************************************ +} + +/* +#define fDPRINTF(out_to, fmt, ...) \ + do { \ + char buf[1024]; \ + sprintf(buf, fmt, ##__VA_ARGS__); \ + DPRINTF(out_to, "%s", buf); \ + } while (0); +*/ + +void PALStatistics::PrintFinalStats(uint64_t sim_time_ps) { + // DPRINTF(PAL, "PAL Final Stats Report ]\n"); + // DPRINTF(PAL, "Total execution time (ms), Total SSD active time (ms)\n"); + // DPRINTF(PAL, "%.2f\t\t\t, %.2f\n", sim_time_ps * 1.0 / 1000000000, + // SampledExactBusyTime * 1.0 / 1000000000); + + assert(Access_Capacity_snapshot.size() > 0); + std::map::iterator e = Access_Capacity_snapshot.end(); + e--; + + e->second->printstat("Info of Access Capacity"); + Access_Bandwidth.printstat_bandwidth(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Bandwidth_widle.printstat_bandwidth_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Bandwidth.printstat_oper_bandwidth(e->second, OpBusyTime, + LastOpBusyTime); + + assert(Ticks_Total_snapshot.size() > 0); + std::map::iterator f = Ticks_Total_snapshot.end(); + f--; + + f->second->printstat_latency("Info of Latency"); + Access_Iops.printstat_iops(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Iops_widle.printstat_iops_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Iops.printstat_oper_iops(e->second, OpBusyTime, LastOpBusyTime); + // DPRINTF(PAL, "===================\n"); + PPN_requested_rwe.printstat("Num of PPN IO request"); + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < PAGE_NUM; i++) { + char str[256]; + sprintf(str, "Num of %s page PPN IO request", PAGE_STRINFO[i]); + PPN_requested_pagetype[i].printstat(str); + } + printf("===================\n"); + + for (uint32_t i = 0; + i < gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Num of CH_%u PPN IO request", i); + PPN_requested_ch[i].printstat(str); + } + printf("===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Num of DIE_%u PPN IO request", i); + PPN_requested_die[i].printstat(str); + } + printf("===================\n"); + + CF_DMA0_dma.printstat("Num of conflict DMA0-CH"); + CF_DMA0_mem.printstat("Num of conflict DMA0-MEM"); + CF_DMA0_none.printstat("Num of conflict DMA0-None"); + printf("===================\n"); + + CF_DMA1_dma.printstat("Num of conflict DMA1-CH"); + CF_DMA1_none.printstat("Num of conflict DMA1-None"); + printf("===================\n"); + + Ticks_DMA0WAIT.printstat("Info of DMA0WAIT Tick"); + Ticks_DMA0.printstat("Info of DMA0 Tick"); + Ticks_MEM.printstat("Info of MEM Tick"); + Ticks_DMA1WAIT.printstat("Info of DMA1WAIT Tick"); + Ticks_DMA1.printstat("Info of DMA1 Tick"); + Ticks_Total.printstat("Info of TOTAL(D0W+D0+M+D1W+D1) Tick"); + Ticks_TotalOpti.printstat("Info of OPTIMUM(D0+M+D1) Tick"); + // power + printf("===================\n"); + Energy_DMA0.printstat_energy("Energy consumption of DMA0"); + Energy_MEM.printstat_energy("Energy consumption of MEM"); + Energy_DMA1.printstat_energy("Energy consumption of DAM1"); + Energy_Total.printstat_energy("Total Energy consumption"); + printf("-------------------\n"); + for (uint32_t i = 0; i < totalDie; i++) { + PrintDieIdleTicks(i, sim_time_ps, lat->GetPower(10, 10)); + } + printf("===================\n"); + + for (uint32_t i = 0; + i < gconf->readUint(SimpleSSD::CONFIG_PAL, SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Info of CH_%u Active Tick", i); + Ticks_Active_ch[i].printstat(str); + } + printf("===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Info of DIE_%u Active Tick", i); + Ticks_Active_die[i].printstat(str); + } + printf("===================\n"); +} + +void PALStatistics::PrintStats(uint64_t sim_time_ps) { + // uint64_t elapsed_time_ps = (sim_time_ps - sim_start_time_ps) + 1; + // if (LastExecutionTime == 0) + // LastExecutionTime = sim_start_time_ps; + // DPRINTF(PAL, "Execution time = %" PRIu64 "\n", sim_time_ps); + // DPRINTF(PAL, "Last Execution time = %" PRIu64 "\n", LastExecutionTime); + // if (sim_start_time_ps >= sim_time_ps) // abnormal case + // { + // elapsed_time_ps = sim_time_ps + 1; + // } + + // DPRINTF(PAL, "[ PAL Stats ]\n"); + +#define SIM_TIME_SEC ((long double)elapsed_time_ps / PSEC) +#define BUSY_TIME_SEC ((long double)ExactBusyTime / PSEC) +#define TRANSFER_TOTAL_MB \ + ((long double)(Access_Capacity.vals[OPER_READ].sum + \ + Access_Capacity.vals[OPER_WRITE].sum) / \ + MBYTE) + + // fDPRINTF(PAL, "Sim.Time : %Lf Sec. , %" PRIu64 " ps\n", SIM_TIME_SEC, + // elapsed_time_ps); + // fDPRINTF(PAL, "Transferred : %Lf MB\n", TRANSFER_TOTAL_MB); + // fDPRINTF(PAL, "Performance: %Lf MB/Sec\n", + // (long double)TRANSFER_TOTAL_MB / SIM_TIME_SEC); + // fDPRINTF(PAL, "Busy Sim.Time: %Lf Sec. , %" PRIu64 " ps\n", BUSY_TIME_SEC, + // ExactBusyTime); + // fDPRINTF(PAL, "Busy Performance: %Lf MB/Sec\n", + // (long double)TRANSFER_TOTAL_MB / BUSY_TIME_SEC); + + std::map::iterator e = + Access_Capacity_snapshot.find(sim_time_ps / EPOCH_INTERVAL - 1); + if (sim_time_ps > 0 && e != Access_Capacity_snapshot.end()) { + PPN_requested_rwe.printstat("Num of PPN IO request"); + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < PAGE_NUM; i++) { + char str[256]; + sprintf(str, "Num of %s page PPN IO request", PAGE_STRINFO[i]); + PPN_requested_pagetype[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Num of CH_%u PPN IO request", i); + PPN_requested_ch[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Num of DIE_%u PPN IO request", i); + PPN_requested_die[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + CF_DMA0_dma.printstat("Num of conflict DMA0-CH"); + CF_DMA0_mem.printstat("Num of conflict DMA0-MEM"); + CF_DMA0_none.printstat("Num of conflict DMA0-None"); + // DPRINTF(PAL, "===================\n"); + + CF_DMA1_dma.printstat("Num of conflict DMA1-CH"); + CF_DMA1_none.printstat("Num of conflict DMA1-None"); + // DPRINTF(PAL, "===================\n"); + + Ticks_DMA0WAIT.printstat("Info of DMA0WAIT Tick"); + Ticks_DMA0.printstat("Info of DMA0 Tick"); + Ticks_MEM.printstat("Info of MEM Tick"); + Ticks_DMA1WAIT.printstat("Info of DMA1WAIT Tick"); + Ticks_DMA1.printstat("Info of DMA1 Tick"); + Ticks_Total.printstat("Info of TOTAL(D0W+D0+M+D1W+D1) Tick"); + Ticks_TotalOpti.printstat("Info of OPTIMUM(D0+M+D1) Tick"); + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < gconf->readUint(SimpleSSD::CONFIG_PAL, + SimpleSSD::PAL::PAL_CHANNEL); + i++) { + char str[256]; + sprintf(str, "Info of CH_%u Active Tick", i); + Ticks_Active_ch[i].printstat(str); + } + // DPRINTF(PAL, "===================\n"); + + for (uint32_t i = 0; i < totalDie; i++) { + char str[256]; + sprintf(str, "Info of DIE_%u Active Tick", i); + Ticks_Active_die[i].printstat(str); + } + // DPRINTF(PAL, "===================\n") + + e->second->printstat("Info of Access Capacity"); + // DPRINTF(PAL, "Total execution time (ms)\n"); + // DPRINTF(PAL, "%.2f\n", SampledExactBusyTime * 1.0 / 1000000000); + Access_Bandwidth.printstat_bandwidth(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Bandwidth_widle.printstat_bandwidth_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Bandwidth.printstat_oper_bandwidth(e->second, OpBusyTime, + LastOpBusyTime); + std::map::iterator f = + Ticks_Total_snapshot.find(sim_time_ps / EPOCH_INTERVAL - 1); + f->second->printstat_latency("Info of Latency"); + Access_Iops.printstat_iops(e->second, SampledExactBusyTime, + LastExactBusyTime); + Access_Iops_widle.printstat_iops_widle(e->second, sim_time_ps, + LastExecutionTime); + Access_Oper_Iops.printstat_oper_iops(e->second, OpBusyTime, LastOpBusyTime); + LastExactBusyTime = SampledExactBusyTime; + LastExecutionTime = sim_time_ps; + LastOpBusyTime[0] = OpBusyTime[0]; + LastOpBusyTime[1] = OpBusyTime[1]; + LastOpBusyTime[2] = OpBusyTime[2]; + std::map::iterator g = + Access_Capacity_snapshot.upper_bound(sim_time_ps / EPOCH_INTERVAL - 1); + if (g != Access_Capacity_snapshot.end()) { + for (int i = 0; i < OPER_ALL; i++) { + g->second->vals[i].sampled_sum = e->second->vals[i].sum; + g->second->vals[i].sampled_cnt = e->second->vals[i].cnt; + e->second->vals[i].sampled_sum = e->second->vals[i].sum; + e->second->vals[i].sampled_cnt = e->second->vals[i].cnt; + } + } + else { + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL] = new ValueOper( + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL - 1]); + for (int i = 0; i < OPER_ALL; i++) { + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_sum = e->second->vals[i].sum; + Access_Capacity_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_cnt = e->second->vals[i].cnt; + } + } + std::map::iterator h = + Ticks_Total_snapshot.upper_bound(sim_time_ps / EPOCH_INTERVAL - 1); + if (h != Ticks_Total_snapshot.end()) { + for (int i = 0; i < OPER_ALL; i++) { + h->second->vals[i].sampled_sum = f->second->vals[i].sum; + h->second->vals[i].sampled_cnt = f->second->vals[i].cnt; + f->second->vals[i].sampled_sum = f->second->vals[i].sum; + f->second->vals[i].sampled_cnt = f->second->vals[i].cnt; + } + } + else { + Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL] = + new ValueOper(Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL - 1]); + for (int i = 0; i < OPER_ALL; i++) { + Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_sum = f->second->vals[i].sum; + Ticks_Total_snapshot[sim_time_ps / EPOCH_INTERVAL] + ->vals[i] + .sampled_cnt = f->second->vals[i].cnt; + } + } + Access_Capacity_snapshot.erase(sim_time_ps / EPOCH_INTERVAL - 1); + Ticks_Total_snapshot.erase(sim_time_ps / EPOCH_INTERVAL - 1); + } + + for (int i = 0; i < OPER_ALL; i++) { + Access_Capacity.vals[i].backup(); + } +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/old/PALStatistics.h b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PALStatistics.h new file mode 100644 index 0000000000..77e504785b --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/old/PALStatistics.h @@ -0,0 +1,329 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + */ + +#ifndef __PALStatistics_h__ +#define __PALStatistics_h__ + +#include "util/old/SimpleSSD_types.h" + +#include "Latency.h" +#include "PAL2_TimeSlot.h" + +#include "sim/config_reader.hh" +#include "sim/simulator.hh" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +using namespace std; + +#define OPER_ALL (OPER_NUM + 1) +#define PAGE_ALL (PAGE_NUM + 1) + +// From ftl_command.hh +typedef struct _Command { + Tick arrived; + Tick finished; + Addr ppn; + PAL_OPERATION operation; + bool mergeSnapshot; + uint64_t size; + + _Command() + : arrived(0), + finished(0), + ppn(0), + operation(OPER_NUM), + mergeSnapshot(false), + size(0) {} + _Command(Tick t, Addr a, PAL_OPERATION op, uint64_t s) + : arrived(t), + finished(0), + ppn(a), + operation(op), + mergeSnapshot(false), + size(s) {} + + Tick getLatency() { + if (finished > 0) { + return finished - arrived; + } + else { + return 0; + } + } +} Command; + +// From ftl_defs.hh +#define EPOCH_INTERVAL 100000000000 + +class PALStatistics { + public: + enum { + /* + BUSY_DMA0WAIT = 0, + BUSY_DMA0 = 1, + BUSY_MEM = 2, + BUSY_DMA1WAIT = 3, + BUSY_DMA1 = 4, + BUSY_END = 5 + */ + TICK_DMA0_CHANNEL_CONFLICT = TICK_NUM, + TICK_DMA0_PLANE_CONFLICT, + TICK_DMA1_CONFLICT, + TICK_DMA0_SUSPEND, + TICK_DMA1_SUSPEND, + TICK_PROC, + TICK_FULL, + TICK_STAT_NUM + }; + + SimpleSSD::ConfigReader *gconf; + Latency *lat; + uint64_t totalDie; + +#if 0 // ch-die io count (legacy) + class mini_cnt_page + { + public: + mini_cnt_page(); + uint64_t c[OPER_NUM][PAGE_NUM]; + }; + mini_cnt_page* ch_io_cnt; + mini_cnt_page* die_io_cnt; +#endif + +#if GATHER_RESOURCE_CONFLICT && 0 // conflict gather (legacy) + class mini_cnt_conflict { + public: + mini_cnt_conflict(); + uint64_t c[OPER_NUM][CONFLICT_NUM]; + }; + mini_cnt_conflict *ch_conflict_cnt; + mini_cnt_conflict *ch_conflict_length; + mini_cnt_conflict *die_conflict_cnt; + mini_cnt_conflict *die_conflict_length; +#endif + +#if 0 // latency (legacy method) + uint64_t latency_cnt[OPER_NUM][TICK_STAT_NUM]; // RWE count for: (page_size * cnt)/SIM_TIME + uint64_t latency_sum[OPER_NUM][TICK_STAT_NUM]; +#endif + +#if 0 // util time (legacy method) + uint64_t* channel_util_time_sum; + uint64_t* die_util_time_sum_mem; //mem only-mem occupy + uint64_t* die_util_time_sum_optimum; //mem oper occupy optimum (DMA0+MEM+DMA1) + uint64_t* die_util_time_sum_all; //mem oper actual occupy +#endif + +#if 0 // stall + /* StallInfo: + Actually, only use 5 entries --- 1a) TICK_DMA0_CHANNEL_CONFLICT, 1b) TICK_DMA0_PLANE_CONFLICT, + 2) TICK_DMA1WAIT, 3) TICK_DMA0_SUSPEND, 4) TICK_DMA1_SUSPEND */ + uint64_t stall_sum[OPER_NUM][TICK_STAT_NUM]; + uint64_t stall_cnt[OPER_NUM][TICK_STAT_NUM]; + uint8_t LastDMA0Stall; + uint64_t LastDMA0AttemptTick; + + void CountStall(uint8_t oper, uint8_t stall_kind); + void AddStall(uint8_t oper, uint8_t stall_kind, uint64_t lat); +#endif + + PALStatistics(SimpleSSD::ConfigReader *, Latency *); + + ~PALStatistics(); + + /* + void AddLatency(uint32_t lat, uint8_t oper, uint8_t busyfor); + */ + + void AddLatency(Task *task); + + /* + void AddOccupy(uint32_t ch, uint64_t ch_time, uint64_t pl, uint64_t pl_time, + uint64_t pl2_time); + */ + + uint64_t sim_start_time_ps; + uint64_t LastTick; + void UpdateLastTick(uint64_t tick); + uint64_t GetLastTick(); +#if GATHER_RESOURCE_CONFLICT + void AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, TimeSlot &DMA0, + TimeSlot &MEM, TimeSlot &DMA1, uint8_t confType); +#else + void AddLatency(Command &CMD, CPDPBP *CPD, uint32_t dieIdx, TimeSlot &DMA0, + TimeSlot &MEM, TimeSlot &DMA1); +#endif + void MergeSnapshot(); + uint64_t ExactBusyTime, SampledExactBusyTime; + uint64_t OpBusyTime[3], LastOpBusyTime[3]; // 0: Read, 1: Write, 2: Erase; + uint64_t LastExactBusyTime; + uint64_t LastExecutionTime; + + struct Breakdown { + double dma0wait; + double dma0; + double mem; + double dma1wait; + double dma1; + + Breakdown() : dma0wait(0.), dma0(0.), mem(0.), dma1wait(0.), dma1(0.) {} + }; + + struct OperStats { + double read; + double write; + double erase; + double total; + + OperStats() : read(0.), write(0.), erase(0.), total(0.) {} + }; + + struct ActiveTime { + double min; + double average; + double max; + + ActiveTime() : min(0.), average(0.), max(0.) {} + }; + + void PrintStats(uint64_t sim_time_ps); + void ResetStats(); + void PrintFinalStats(uint64_t sim_time_ps); + + void getTickStat(OperStats &); // Return busy ticks in ps + void getEnergyStat(OperStats &); // Return energy in uJ + void getReadBreakdown(Breakdown &); // Return READ breakdown in ps + void getWriteBreakdown(Breakdown &); // Return WRITE breakdown in ps + void getEraseBreakdown(Breakdown &); // Return ERASE breakdown in ps + void getChannelActiveTime(uint32_t, ActiveTime &); + void getDieActiveTime(uint32_t, ActiveTime &); + void getChannelActiveTimeAll(ActiveTime &); + void getDieActiveTimeAll(ActiveTime &); + + class Counter { + public: + Counter(); + void init(); + void add(); + uint64_t cnt; + }; + + class CounterOper { + public: + CounterOper(); + Counter cnts[OPER_ALL]; + void init(); + void add(uint32_t oper); + void printstat(const char *namestr); + }; + + CounterOper PPN_requested_rwe; + CounterOper PPN_requested_pagetype[PAGE_ALL]; + CounterOper *PPN_requested_ch; // channels + CounterOper *PPN_requested_die; // dies + CounterOper CF_DMA0_dma; + CounterOper CF_DMA0_mem; + CounterOper CF_DMA0_none; + CounterOper CF_DMA1_dma; + CounterOper CF_DMA1_none; + + class Value { + public: + Value(); + void init(); + void add(double val); + void backup(); + void update(); + double avg(); + double legacy_avg(); + double sum, minval, maxval, cnt, sampled_sum, sampled_cnt, legacy_sum, + legacy_cnt, legacy_minval, legacy_maxval; + }; + + class ValueOper { + public: + ValueOper(); + ValueOper(ValueOper *_ValueOper); + Value vals[OPER_ALL]; + void init(); + void update(); + void add(uint32_t oper, double val); + void exclusive_add(uint32_t oper, double val); + void printstat(const char *namestr); + void printstat_bandwidth(class ValueOper *, uint64_t, + uint64_t); // bandwidth excluding idle time + void printstat_bandwidth_widle(class ValueOper *, uint64_t, + uint64_t); // bandwidth including idle time + void printstat_oper_bandwidth( + class ValueOper *, uint64_t *, + uint64_t *); // read/write/erase-only bandwidth + void printstat_latency(const char *namestr); + void printstat_iops(class ValueOper *, uint64_t, uint64_t); + void printstat_iops_widle(class ValueOper *, uint64_t, uint64_t); + void printstat_oper_iops(class ValueOper *, uint64_t *, uint64_t *); + + void printstat_energy(const char *namestr); + }; + + ValueOper Ticks_DMA0WAIT; + ValueOper Ticks_DMA0; + ValueOper Ticks_MEM; + ValueOper Ticks_DMA1WAIT; + ValueOper Ticks_DMA1; + ValueOper Ticks_Total; // Total = D0W+D0+M+D1W+D1 + // power + ValueOper Energy_DMA0; + ValueOper Energy_MEM; + ValueOper Energy_DMA1; + ValueOper Energy_Total; + + std::map Ticks_Total_snapshot; + ValueOper Ticks_TotalOpti; // TotalOpti = D0+M+D1 --- exclude WAIT + ValueOper *Ticks_Active_ch; // channels + ValueOper *Ticks_Active_die; // dies + ValueOper Access_Capacity; + std::map Access_Capacity_snapshot; + ValueOper Access_Bandwidth; + ValueOper Access_Bandwidth_widle; + ValueOper Access_Oper_Bandwidth; + ValueOper Access_Iops; + ValueOper Access_Iops_widle; + ValueOper Access_Oper_Iops; + uint64_t SampledTick; + bool skip; + + void PrintDieIdleTicks(uint32_t die_num, uint64_t sim_time_ps, + uint64_t idle_power_nw); + + private: + void ClearStats(); + void InitStats(); +}; + +#endif //__PALStatistics_h__ diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/pal.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/pal.cc new file mode 100644 index 0000000000..ea1fd8b800 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/pal.cc @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "pal/pal.hh" + +#include "pal/pal_old.hh" +namespace SimpleSSD { + +namespace PAL { + +PAL::PAL(ConfigReader &c) : conf(c) { + static const char name[4][16] = {"Channel", "Way", "Die", "Plane"}; + uint32_t value[4]; + uint8_t superblock = conf.getSuperblockConfig(); + + param.channel = conf.readUint(CONFIG_PAL, PAL_CHANNEL); + param.package = conf.readUint(CONFIG_PAL, PAL_PACKAGE); + + param.die = conf.readUint(CONFIG_PAL, NAND_DIE); + param.plane = conf.readUint(CONFIG_PAL, NAND_PLANE); + param.block = conf.readUint(CONFIG_PAL, NAND_BLOCK); + param.page = conf.readUint(CONFIG_PAL, NAND_PAGE); + param.pageSize = conf.readUint(CONFIG_PAL, NAND_PAGE_SIZE); + param.superBlock = param.block; + param.superPageSize = param.pageSize; + + // Super block includes channel + if (superblock & INDEX_CHANNEL) { + param.superPageSize *= param.channel; + value[0] = param.channel; + } + else { + param.superBlock *= param.channel; + } + + // Super block includes way (package) + if (superblock & INDEX_PACKAGE) { + param.superPageSize *= param.package; + value[1] = param.package; + } + else { + param.superBlock *= param.package; + } + + // Super block includes die + if (superblock & INDEX_DIE) { + param.superPageSize *= param.die; + value[2] = param.die; + } + else { + param.superBlock *= param.die; + } + + // Super block includes plane + if (conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP) || + (superblock & INDEX_PLANE)) { + param.superPageSize *= param.plane; + value[3] = param.plane; + } + else { + param.superBlock *= param.plane; + } + + // Partial I/O tweak + param.pageInSuperPage = param.superPageSize / param.pageSize; + + // TODO: If PAL revised, this code may not needed + if (conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP)) { + param.pageInSuperPage /= param.plane; + } + + // Print super block information + debugprint(LOG_PAL, + "Channel | Way | Die | Plane | Block | Page "); + debugprint(LOG_PAL, "%7u | %7u | %7u | %7u | %7u | %7u", param.channel, + param.package, param.die, param.plane, param.block, param.page); + debugprint(LOG_PAL, "Multi-plane mode %s", + conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP) + ? "enabled" + : "disabled"); + debugprint(LOG_PAL, "Superblock multiplier"); + + for (int i = 0; i < 4; i++) { + if (superblock & (1 << i)) { + debugprint(LOG_PAL, "x%u (%s)", value[i], name[i]); + } + } + + debugprint(LOG_PAL, "Page size %u -> %u", param.pageSize, + param.superPageSize); + debugprint( + LOG_PAL, "Total block count %u -> %u", + param.channel * param.package * param.die * param.plane * param.block, + param.superBlock); + + pPAL = new PALOLD(param, c); +} + +PAL::~PAL() { + delete pPAL; +} + +void PAL::read(Request &req, uint64_t &tick) { + pPAL->read(req, tick); +} + +void PAL::write(Request &req, uint64_t &tick) { + pPAL->write(req, tick); +} + +void PAL::erase(Request &req, uint64_t &tick) { + printf("erase"); + pPAL->erase(req, tick); +} + +void PAL::copyback(uint32_t, uint32_t, uint32_t, uint64_t &) { + panic("Copyback not implemented"); +} + +Parameter *PAL::getInfo() { + return ¶m; +} + +void PAL::getStatList(std::vector &list, std::string prefix) { + pPAL->getStatList(list, prefix + "pal."); +} + +void PAL::getStatValues(std::vector &values) { + pPAL->getStatValues(values); +} + +void PAL::resetStatValues() { + pPAL->resetStatValues(); +} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/pal.hh b/hotness/SimpleSSD-Standalone/simplessd/pal/pal.hh new file mode 100644 index 0000000000..cee31e4622 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/pal.hh @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_PAL__ +#define __PAL_PAL__ + +#include "util/def.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +namespace PAL { + +class AbstractPAL; + +typedef struct { + uint32_t channel; //!< Total # channels + uint32_t package; //!< # packages / channel + uint32_t die; //!< # dies / package + uint32_t plane; //!< # planes / die + uint32_t block; //!< # blocks / plane + uint32_t page; //!< # pages / block + uint32_t superBlock; //!< Total super blocks + uint32_t pageSize; //!< Size of page in bytes + uint32_t superPageSize; //!< Size of super page in bytes + uint32_t pageInSuperPage; //!< # pages in one superpage +} Parameter; + +class PAL : public StatObject { + private: + Parameter param; + AbstractPAL *pPAL; + + ConfigReader &conf; + + public: + PAL(ConfigReader &); + ~PAL(); + + void read(Request &, uint64_t &); + void write(Request &, uint64_t &); + void erase(Request &, uint64_t &); + void copyback(uint32_t, uint32_t, uint32_t, uint64_t &); + + Parameter *getInfo(); + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/pal_old.cc b/hotness/SimpleSSD-Standalone/simplessd/pal/pal_old.cc new file mode 100644 index 0000000000..4162d2f724 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/pal_old.cc @@ -0,0 +1,560 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "pal/pal_old.hh" + +#include + +#include "pal/old/Latency.h" +#include "pal/old/LatencyMLC.h" +#include "pal/old/LatencySLC.h" +#include "pal/old/LatencyTLC.h" +#include "pal/old/PAL2.h" +#include "pal/old/PALStatistics.h" +#include "util/algorithm.hh" + +#define FLUSH_PERIOD 100000000000ull // 0.1sec +#define FLUSH_RANGE 10000000000ull // 0.01sec + +namespace SimpleSSD { + +namespace PAL { + +PALOLD::PALOLD(Parameter &p, ConfigReader &c) + : AbstractPAL(p, c), lastResetTick(0) { + Config::NANDTiming *pTiming = c.getNANDTiming(); + Config::NANDPower *pPower = c.getNANDPower(); + + memset(&stat, 0, sizeof(stat)); + + switch (conf.readInt(CONFIG_PAL, NAND_FLASH_TYPE)) { + case NAND_SLC: + lat = new LatencySLC(*pTiming, *pPower); + break; + case NAND_MLC: + lat = new LatencyMLC(*pTiming, *pPower); + break; + case NAND_TLC: + lat = new LatencyTLC(*pTiming, *pPower); + break; + } + + debugprint(LOG_PAL_OLD, "NAND timing:"); + debugprint(LOG_PAL_OLD, "Operation | LSB | CSB | MSB | " + " DMA 0 | DMA "); + debugprint(LOG_PAL_OLD, + " READ | %10" PRIu64 " | %10" PRIu64 " | %10" PRIu64 + " | %10" PRIu64 " | %10" PRIu64, + pTiming->lsb.read, pTiming->csb.read, pTiming->msb.read, + pTiming->dma0.read, pTiming->dma1.read); + debugprint(LOG_PAL_OLD, + " WRITE | %10" PRIu64 " | %10" PRIu64 " | %10" PRIu64 + " | %10" PRIu64 " | %10" PRIu64, + pTiming->lsb.write, pTiming->csb.write, pTiming->msb.write, + pTiming->dma0.write, pTiming->dma1.write); + debugprint(LOG_PAL_OLD, + " ERASE | %10" PRIu64 " | %10" PRIu64 + " | %10" PRIu64, + pTiming->erase, pTiming->dma0.erase, pTiming->dma1.erase); + + stats = new PALStatistics(&conf, lat); + pal = new PAL2(stats, ¶m, &conf, lat); + + // We will periodically flush timeslot for saving memory + flushFunction = [this](uint64_t tick) { + pal->FlushFreeSlots(tick - FLUSH_RANGE); + pal->FlushTimeSlots(tick - FLUSH_RANGE); + + schedule(flushEvent, tick + FLUSH_PERIOD); + }; + flushEvent = allocate(flushFunction); + schedule(flushEvent, getTick() + FLUSH_PERIOD); +} + +PALOLD::~PALOLD() { + delete pal; + delete stats; + delete lat; +} + +void PALOLD::read(Request &req, uint64_t &tick) { + uint64_t finishedAt = tick; + ::Command cmd(tick, 0, OPER_READ, param.superPageSize); + std::vector<::CPDPBP> list; + + printPPN(req, "READ"); + + convertCPDPBP(req, list); + + for (auto &iter : list) { + printCPDPBP(iter, "READ"); + + pal->submit(cmd, iter); + stat.readCount++; + + finishedAt = MAX(finishedAt, cmd.finished); + } + + tick = finishedAt; +} + +void PALOLD::write(Request &req, uint64_t &tick) { + uint64_t finishedAt = tick; + ::Command cmd(tick, 0, OPER_WRITE, param.superPageSize); + std::vector<::CPDPBP> list; + + printPPN(req, "WRITE"); + + convertCPDPBP(req, list); + + for (auto &iter : list) { + printCPDPBP(iter, "WRITE"); + + pal->submit(cmd, iter); + stat.writeCount++; + + finishedAt = MAX(finishedAt, cmd.finished); + } + + tick = finishedAt; +} + +void PALOLD::erase(Request &req, uint64_t &tick) { + printf(">>> DEBUG: PALOLD::erase() 호출 "); + fflush(stdout); + + uint64_t finishedAt = tick; + ::Command cmd(tick, 0, OPER_ERASE, param.superPageSize * param.page); + std::vector<::CPDPBP> list; + + printPPN(req, "ERASE"); + + convertCPDPBP(req, list); + + for (auto &iter : list) { + printCPDPBP(iter, "ERASE"); + + pal->submit(cmd, iter); + stat.eraseCount++; + + finishedAt = MAX(finishedAt, cmd.finished); + } + + tick = finishedAt; +} + +void PALOLD::convertCPDPBP(Request &req, std::vector<::CPDPBP> &list) { + ::CPDPBP addr; + static uint32_t pageAllocation = conf.getPageAllocationConfig(); + static uint8_t superblock = conf.getSuperblockConfig(); + static bool useMultiplaneOP = + conf.readBoolean(CONFIG_PAL, NAND_USE_MULTI_PLANE_OP); + static uint32_t pageInSuperPage = param.pageInSuperPage; + static bool bRandomTweak = + conf.readBoolean(CONFIG_FTL, FTL::FTL_USE_RANDOM_IO_TWEAK); + uint32_t value[4]; + uint32_t *ptr[4]; + uint64_t tmp = req.blockIndex; + int count = 0; + + if (bRandomTweak && req.ioFlag.size() != pageInSuperPage) { + panic("Invalid size of I/O flag"); + } + + if (!bRandomTweak && req.ioFlag.size() != pageInSuperPage) { + req.ioFlag = Bitset(pageInSuperPage); + req.ioFlag.set(); + } + + list.clear(); + + addr.Plane = 0; + + for (int i = 0; i < 4; i++) { + uint8_t idx = (pageAllocation >> (i * 8)) & 0xFF; + + switch (idx) { + case INDEX_CHANNEL: + if (superblock & INDEX_CHANNEL) { + value[count] = param.channel; + ptr[count++] = &addr.Channel; + } + else { + addr.Channel = tmp % param.channel; + tmp /= param.channel; + } + + break; + case INDEX_PACKAGE: + if (superblock & INDEX_PACKAGE) { + value[count] = param.package; + ptr[count++] = &addr.Package; + } + else { + addr.Package = tmp % param.package; + tmp /= param.package; + } + + break; + case INDEX_DIE: + if (superblock & INDEX_DIE) { + value[count] = param.die; + ptr[count++] = &addr.Die; + } + else { + addr.Die = tmp % param.die; + tmp /= param.die; + } + + break; + case INDEX_PLANE: + if (!useMultiplaneOP) { + if (superblock & INDEX_PLANE) { + value[count] = param.plane; + ptr[count++] = &addr.Plane; + } + else { + addr.Plane = tmp % param.plane; + tmp /= param.plane; + } + } + + break; + default: + break; + } + } + + addr.Block = tmp; + addr.Page = req.pageIndex; + + // Index of ioFlag + tmp = 0; + + if (count == 4) { + list.reserve(value[0] * value[1] * value[2] * value[3]); + + for (uint32_t i = 0; i < value[3]; i++) { + for (uint32_t j = 0; j < value[2]; j++) { + for (uint32_t k = 0; k < value[1]; k++) { + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + *ptr[1] = k; + *ptr[2] = j; + *ptr[3] = i; + + list.push_back(addr); + } + } + } + } + } + } + else if (count == 3) { + list.reserve(value[0] * value[1] * value[2]); + + for (uint32_t j = 0; j < value[2]; j++) { + for (uint32_t k = 0; k < value[1]; k++) { + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + *ptr[1] = k; + *ptr[2] = j; + + list.push_back(addr); + } + } + } + } + } + else if (count == 2) { + list.reserve(value[0] * value[1]); + + for (uint32_t k = 0; k < value[1]; k++) { + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + *ptr[1] = k; + + list.push_back(addr); + } + } + } + } + else if (count == 1) { + list.reserve(value[0]); + + for (uint32_t l = 0; l < value[0]; l++) { + if (req.ioFlag.test(tmp++)) { + *ptr[0] = l; + + list.push_back(addr); + } + } + } + else { + if (req.ioFlag.test(tmp++)) { + list.push_back(addr); + } + } + + if (tmp != pageInSuperPage) { + panic("I/O flag size != # pages in super page"); + } +} + +void PALOLD::printCPDPBP(::CPDPBP &addr, const char *prefix) { + debugprint(LOG_PAL_OLD, + "%-5s | C %5u | W %5u | D %5u | P %5u | B %5u | P %5u", prefix, + addr.Channel, addr.Package, addr.Die, addr.Plane, addr.Block, + addr.Page); +} + +void PALOLD::printPPN(Request &req, const char *prefix) { + debugprint(LOG_PAL_OLD, "%-5s | Block %u | Page %u", prefix, req.blockIndex, + req.pageIndex); +} + +void PALOLD::getStatList(std::vector &list, std::string prefix) { + Stats temp; + + temp.name = prefix + "energy.read"; + temp.desc = "Consumed energy by NAND read operation (uJ)"; + list.push_back(temp); + + temp.name = prefix + "energy.program"; + temp.desc = "Consumed energy by NAND program operation (uJ)"; + list.push_back(temp); + + temp.name = prefix + "energy.erase"; + temp.desc = "Consumed energy by NAND erase operation (uJ)"; + list.push_back(temp); + + temp.name = prefix + "energy.total"; + temp.desc = "Total consumed energy by NAND (uJ)"; + list.push_back(temp); + + temp.name = prefix + "power"; + temp.desc = "Average power consumed by NAND (uW)"; + list.push_back(temp); + + temp.name = prefix + "read.count"; + temp.desc = "Total read operation count"; + list.push_back(temp); + + temp.name = prefix + "program.count"; + temp.desc = "Total program operation count"; + list.push_back(temp); + + temp.name = prefix + "erase.count"; + temp.desc = "Total erase operation count"; + list.push_back(temp); + + temp.name = prefix + "read.bytes"; + temp.desc = "Total read operation bytes"; + list.push_back(temp); + + temp.name = prefix + "program.bytes"; + temp.desc = "Total program operation bytes"; + list.push_back(temp); + + temp.name = prefix + "erase.bytes"; + temp.desc = "Total erase operation bytes"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma0.wait"; + temp.desc = "Average dma0 wait time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma0"; + temp.desc = "Average dma0 time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.mem"; + temp.desc = "Average memory operation time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma1.wait"; + temp.desc = "Average dma1 wait time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.dma1"; + temp.desc = "Average dma1 time of read"; + list.push_back(temp); + + temp.name = prefix + "read.time.total"; + temp.desc = "Average time of read"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma0.wait"; + temp.desc = "Average dma0 wait time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma0"; + temp.desc = "Average dma0 time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.mem"; + temp.desc = "Average memory operation time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma1.wait"; + temp.desc = "Average dma1 wait time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.dma1"; + temp.desc = "Average dma1 time of program"; + list.push_back(temp); + + temp.name = prefix + "program.time.total"; + temp.desc = "Average time of program"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma0.wait"; + temp.desc = "Average dma0 wait time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma0"; + temp.desc = "Average dma0 time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.mem"; + temp.desc = "Average memory operation time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma1.wait"; + temp.desc = "Average dma1 wait time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.dma1"; + temp.desc = "Average dma1 time of erase"; + list.push_back(temp); + + temp.name = prefix + "erase.time.total"; + temp.desc = "Average time of erase"; + list.push_back(temp); + + temp.name = prefix + "channel.time.active"; + temp.desc = "Average active time of all channels"; + list.push_back(temp); + + temp.name = prefix + "die.time.active"; + temp.desc = "Average active time of all dies"; + list.push_back(temp); +} + +void PALOLD::getStatValues(std::vector &values) { + PALStatistics::OperStats energy; + PALStatistics::OperStats ticks; + PALStatistics::ActiveTime active; + PALStatistics::Breakdown breakdown; + double elapsedTick = (double)(getTick() - lastResetTick); + + stats->getEnergyStat(energy); + stats->getTickStat(ticks); + + values.push_back(energy.read); + values.push_back(energy.write); + values.push_back(energy.erase); + values.push_back(energy.total); + + // uW = uJ / ps * 1e+12 + energy.total /= elapsedTick / 1e+12; + values.push_back(energy.total); + + values.push_back(stat.readCount); + values.push_back(stat.writeCount); + values.push_back(stat.eraseCount); + + values.push_back(stat.readCount * param.pageSize); + values.push_back(stat.writeCount * param.pageSize); + values.push_back(stat.eraseCount * param.pageSize * param.page); + + stats->getReadBreakdown(breakdown); + values.push_back(breakdown.dma0wait); + values.push_back(breakdown.dma0); + values.push_back(breakdown.mem); + values.push_back(breakdown.dma1wait); + values.push_back(breakdown.dma1); + values.push_back(ticks.read); + + stats->getWriteBreakdown(breakdown); + values.push_back(breakdown.dma0wait); + values.push_back(breakdown.dma0); + values.push_back(breakdown.mem); + values.push_back(breakdown.dma1wait); + values.push_back(breakdown.dma1); + values.push_back(ticks.write); + + stats->getEraseBreakdown(breakdown); + values.push_back(breakdown.dma0wait); + values.push_back(breakdown.dma0); + values.push_back(breakdown.mem); + values.push_back(breakdown.dma1wait); + values.push_back(breakdown.dma1); + values.push_back(ticks.erase); + + stats->getChannelActiveTimeAll(active); + values.push_back(active.average); + + stats->getDieActiveTimeAll(active); + values.push_back(active.average); +} + +void PALOLD::resetStatValues() { + stats->ResetStats(); + lastResetTick = getTick(); + + memset(&stat, 0, sizeof(stat)); +} + +void PALOLD::read(::CPDPBP &addr, uint64_t &tick) { + ::Command cmd(tick, 0, OPER_READ, param.superPageSize); + + printCPDPBP(addr, "READ"); + pal->submit(cmd, addr); + stat.readCount++; + + tick = cmd.finished; +} + +void PALOLD::write(::CPDPBP &addr, uint64_t &tick) { + ::Command cmd(tick, 0, OPER_WRITE, param.superPageSize); + + printCPDPBP(addr, "WRITE"); + pal->submit(cmd, addr); + stat.writeCount++; + + tick = cmd.finished; +} + +void PALOLD::erase(::CPDPBP &addr, uint64_t &tick) { + ::Command cmd(tick, 0, OPER_ERASE, param.superPageSize * param.page); + + printCPDPBP(addr, "ERASE"); + pal->submit(cmd, addr); + stat.eraseCount++; + + tick = cmd.finished; +} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/pal/pal_old.hh b/hotness/SimpleSSD-Standalone/simplessd/pal/pal_old.hh new file mode 100644 index 0000000000..29f4a46520 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/pal/pal_old.hh @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#ifndef __PAL_PAL_OLD__ +#define __PAL_PAL_OLD__ + +#include +#include + +#include "pal/abstract_pal.hh" +#include "util/old/SimpleSSD_types.h" + +class PAL2; +class PALStatistics; +class Latency; + +namespace SimpleSSD { + +namespace PAL { + +class PALOLD : public AbstractPAL { + private: + ::PAL2 *pal; + ::PALStatistics *stats; + ::Latency *lat; + + Event flushEvent; + EventFunction flushFunction; + + uint8_t lastResetTick; + + struct { + uint64_t readCount; + uint64_t writeCount; + uint64_t eraseCount; + } stat; + + void convertCPDPBP(Request &, std::vector<::CPDPBP> &); + void printCPDPBP(::CPDPBP &, const char *); + void printPPN(Request &, const char *); + + public: + PALOLD(Parameter &, ConfigReader &); + ~PALOLD(); + + void read(Request &, uint64_t &) override; + void write(Request &, uint64_t &) override; + void erase(Request &, uint64_t &) override; + + void getStatList(std::vector &, std::string) override; + void getStatValues(std::vector &) override; + void resetStatValues() override; + + // Direct interface for OCSSD + void read(::CPDPBP &, uint64_t &); + void write(::CPDPBP &, uint64_t &); + void erase(::CPDPBP &, uint64_t &); +}; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/base_config.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/base_config.hh new file mode 100644 index 0000000000..0ca91f9625 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/base_config.hh @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_BASE_CONFIG__ +#define __SIM_BASE_CONFIG__ + +#include +#include +#include + +namespace SimpleSSD { + +#define MATCH_SECTION(str) (strcmp(section, str) == 0) +#define MATCH_NAME(str) (strcmp(name, str) == 0) +#define MATCH_VALUE(str) (strcmp(value, str) == 0) + +class BaseConfig { + protected: + bool convertBool(const char *); + + public: + BaseConfig() {} + virtual ~BaseConfig() {} + + virtual bool setConfig(const char *, const char *) = 0; + virtual void update() {} + + virtual int64_t readInt(uint32_t) { return 0; } + virtual uint64_t readUint(uint32_t) { return 0; } + virtual float readFloat(uint32_t) { return 0.f; } + virtual std::string readString(uint32_t) { return std::string(); } + virtual bool readBoolean(uint32_t) { return false; } +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/config_reader.cc b/hotness/SimpleSSD-Standalone/simplessd/sim/config_reader.cc new file mode 100644 index 0000000000..8117b77c06 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/config_reader.cc @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/config_reader.hh" + +#include "sim/base_config.hh" +#include "sim/trace.hh" + +#ifdef _MSC_VER +#define strcasecmp _stricmp +#else +#include +#endif + +namespace SimpleSSD { + +const char SECTION_CPU[] = "cpu"; +const char SECTION_DRAM[] = "dram"; +const char SECTION_FTL[] = "ftl"; +const char SECTION_NVME[] = "nvme"; +const char SECTION_ICL[] = "icl"; +const char SECTION_PAL[] = "pal"; +const char SECTION_SATA[] = "sata"; +const char SECTION_UFS[] = "ufs"; + +bool BaseConfig::convertBool(const char *value) { + bool ret = false; + + if (strcasecmp(value, "true") == 0 || strtoul(value, nullptr, 10)) { + ret = true; + } + + return ret; +} + +bool ConfigReader::init(std::string file) { + if (ini_parse(file.c_str(), parserHandler, this) < 0) { + return false; + } + + // Update all + cpuConfig.update(); + dramConfig.update(); + ftlConfig.update(); + nvmeConfig.update(); + iclConfig.update(); + palConfig.update(); + sataConfig.update(); + ufsConfig.update(); + + return true; +} + +int64_t ConfigReader::readInt(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readInt(idx); + case CONFIG_DRAM: + return dramConfig.readInt(idx); + case CONFIG_FTL: + return ftlConfig.readInt(idx); + case CONFIG_NVME: + return nvmeConfig.readInt(idx); + case CONFIG_SATA: + return sataConfig.readInt(idx); + case CONFIG_UFS: + return ufsConfig.readInt(idx); + case CONFIG_ICL: + return iclConfig.readInt(idx); + case CONFIG_PAL: + return palConfig.readInt(idx); + default: + return 0; + } +} + +uint64_t ConfigReader::readUint(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readUint(idx); + case CONFIG_DRAM: + return dramConfig.readUint(idx); + case CONFIG_FTL: + return ftlConfig.readUint(idx); + case CONFIG_NVME: + return nvmeConfig.readUint(idx); + case CONFIG_SATA: + return sataConfig.readUint(idx); + case CONFIG_UFS: + return ufsConfig.readUint(idx); + case CONFIG_ICL: + return iclConfig.readUint(idx); + case CONFIG_PAL: + return palConfig.readUint(idx); + default: + return 0; + } +} + +float ConfigReader::readFloat(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readFloat(idx); + case CONFIG_DRAM: + return dramConfig.readFloat(idx); + case CONFIG_FTL: + return ftlConfig.readFloat(idx); + case CONFIG_NVME: + return nvmeConfig.readFloat(idx); + case CONFIG_SATA: + return sataConfig.readFloat(idx); + case CONFIG_UFS: + return ufsConfig.readFloat(idx); + case CONFIG_ICL: + return iclConfig.readFloat(idx); + case CONFIG_PAL: + return palConfig.readFloat(idx); + default: + return 0.f; + } +} + +std::string ConfigReader::readString(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readString(idx); + case CONFIG_DRAM: + return dramConfig.readString(idx); + case CONFIG_FTL: + return ftlConfig.readString(idx); + case CONFIG_NVME: + return nvmeConfig.readString(idx); + case CONFIG_SATA: + return sataConfig.readString(idx); + case CONFIG_UFS: + return ufsConfig.readString(idx); + case CONFIG_ICL: + return iclConfig.readString(idx); + case CONFIG_PAL: + return palConfig.readString(idx); + default: + return std::string(); + } +} + +bool ConfigReader::readBoolean(CONFIG_SECTION section, uint32_t idx) { + switch (section) { + case CONFIG_CPU: + return cpuConfig.readBoolean(idx); + case CONFIG_DRAM: + return dramConfig.readBoolean(idx); + case CONFIG_FTL: + return ftlConfig.readBoolean(idx); + case CONFIG_NVME: + return nvmeConfig.readBoolean(idx); + case CONFIG_SATA: + return sataConfig.readBoolean(idx); + case CONFIG_UFS: + return ufsConfig.readBoolean(idx); + case CONFIG_ICL: + return iclConfig.readBoolean(idx); + case CONFIG_PAL: + return palConfig.readBoolean(idx); + default: + return false; + } +} + +int ConfigReader::parserHandler(void *context, const char *section, + const char *name, const char *value) { + ConfigReader *pThis = (ConfigReader *)context; + bool handled = false; + + if (MATCH_SECTION(SECTION_CPU)) { + handled = pThis->cpuConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_DRAM)) { + handled = pThis->dramConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_FTL)) { + handled = pThis->ftlConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_NVME)) { + handled = pThis->nvmeConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_SATA)) { + handled = pThis->sataConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_UFS)) { + handled = pThis->ufsConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_ICL)) { + handled = pThis->iclConfig.setConfig(name, value); + } + else if (MATCH_SECTION(SECTION_PAL)) { + handled = pThis->palConfig.setConfig(name, value); + } + + if (!handled) { + warn("Config [%s] %s = %s not handled", section, name, value); + } + + return 1; +} + +DRAM::Config::DRAMStructure *ConfigReader::getDRAMStructure() { + return dramConfig.getDRAMStructure(); +} + +DRAM::Config::DRAMTiming *ConfigReader::getDRAMTiming() { + return dramConfig.getDRAMTiming(); +} + +DRAM::Config::DRAMPower *ConfigReader::getDRAMPower() { + return dramConfig.getDRAMPower(); +} + +uint8_t ConfigReader::getSuperblockConfig() { + return palConfig.getSuperblockConfig(); +} + +uint32_t ConfigReader::getPageAllocationConfig() { + return palConfig.getPageAllocationConfig(); +} + +PAL::Config::NANDTiming *ConfigReader::getNANDTiming() { + return palConfig.getNANDTiming(); +} + +PAL::Config::NANDPower *ConfigReader::getNANDPower() { + return palConfig.getNANDPower(); +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/config_reader.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/config_reader.hh new file mode 100644 index 0000000000..e831329c66 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/config_reader.hh @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_CONFIG_READER__ +#define __SIM_CONFIG_READER__ + +#include +#include + +#include "cpu/config.hh" +#include "dram/config.hh" +#include "ftl/config.hh" +#include "hil/nvme/config.hh" +#include "hil/sata/config.hh" +#include "hil/ufs/config.hh" +#include "icl/config.hh" +#include "lib/inih/ini.h" +#include "pal/config.hh" + +namespace SimpleSSD { + +typedef enum { + CONFIG_CPU, + CONFIG_DRAM, + CONFIG_FTL, + CONFIG_NVME, + CONFIG_SATA, + CONFIG_UFS, + CONFIG_ICL, + CONFIG_PAL, +} CONFIG_SECTION; + +class ConfigReader { + private: + CPU::Config cpuConfig; + DRAM::Config dramConfig; + FTL::Config ftlConfig; + HIL::NVMe::Config nvmeConfig; + HIL::SATA::Config sataConfig; + HIL::UFS::Config ufsConfig; + ICL::Config iclConfig; + PAL::Config palConfig; + + static int parserHandler(void *, const char *, const char *, const char *); + + public: + bool init(std::string); + + int64_t readInt(CONFIG_SECTION, uint32_t); + uint64_t readUint(CONFIG_SECTION, uint32_t); + float readFloat(CONFIG_SECTION, uint32_t); + std::string readString(CONFIG_SECTION, uint32_t); + bool readBoolean(CONFIG_SECTION, uint32_t); + + // DRAM::Config + DRAM::Config::DRAMStructure *getDRAMStructure(); + DRAM::Config::DRAMTiming *getDRAMTiming(); + DRAM::Config::DRAMPower *getDRAMPower(); + + // PAL::Config + uint8_t getSuperblockConfig(); + uint32_t getPageAllocationConfig(); + + PAL::Config::NANDTiming *getNANDTiming(); + PAL::Config::NANDPower *getNANDPower(); +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/cpu.cc b/hotness/SimpleSSD-Standalone/simplessd/sim/cpu.cc new file mode 100644 index 0000000000..ac01439b89 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/cpu.cc @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/cpu.hh" + +namespace SimpleSSD { + +// Defined in sim/cpu.hh +CPU::CPU *cpu = nullptr; +DMAFunction cpuHandler = commonCPUHandler; + +CPUContext::_CPUContext(DMAFunction &f, void *c) : func(f), context(c) {} + +CPUContext::_CPUContext(DMAFunction &f, void *c, CPU::NAMESPACE n, + CPU::FUNCTION fc) + : func(f), context(c), ns(n), fct(fc), delay(0) {} + +CPUContext::_CPUContext(DMAFunction &f, void *c, CPU::NAMESPACE n, + CPU::FUNCTION fc, uint64_t d) + : func(f), context(c), ns(n), fct(fc), delay(d) {} + +void initCPU(ConfigReader &conf) { + if (cpu) { + delete cpu; + } + + cpu = new CPU::CPU(conf); +} + +void deInitCPU() { + delete cpu; + cpu = nullptr; +} + +void getCPUStatList(std::vector &list, std::string prefix) { + if (cpu) { + cpu->getStatList(list, prefix); + } +} + +void getCPUStatValues(std::vector &values) { + if (cpu) { + cpu->getStatValues(values); + } +} + +void resetCPUStatValues() { + if (cpu) { + cpu->resetStatValues(); + } +} + +void printCPULastStat() { + if (cpu) { + cpu->printLastStat(); + } +} + +void execute(CPU::NAMESPACE ns, CPU::FUNCTION fct, DMAFunction &func, + void *context, uint64_t delay) { + if (cpu) { + cpu->execute(ns, fct, func, context, delay); + } +} + +void commonCPUHandler(uint64_t, void *context) { + CPUContext *pContext = (CPUContext *)context; + + execute(pContext->ns, pContext->fct, pContext->func, pContext->context, + pContext->delay); + + delete pContext; +} + +uint64_t applyLatency(CPU::NAMESPACE ns, CPU::FUNCTION fct) { + if (cpu) { + return cpu->applyLatency(ns, fct); + } + + return 0; +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/cpu.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/cpu.hh new file mode 100644 index 0000000000..4d49048d7a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/cpu.hh @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_CPU__ +#define __SIM_CPU__ + +#include +#include + +#include "cpu/cpu.hh" + +namespace SimpleSSD { + +typedef struct _CPUContext { + DMAFunction func; + void *context; + + CPU::NAMESPACE ns; + CPU::FUNCTION fct; + uint64_t delay; + + _CPUContext(DMAFunction &, void *); + _CPUContext(DMAFunction &, void *, CPU::NAMESPACE, CPU::FUNCTION); + _CPUContext(DMAFunction &, void *, CPU::NAMESPACE, CPU::FUNCTION, uint64_t); +} CPUContext; + +void initCPU(ConfigReader &); +void deInitCPU(); +void getCPUStatList(std::vector &, std::string); +void getCPUStatValues(std::vector &); +void resetCPUStatValues(); +void printCPULastStat(); + +void execute(CPU::NAMESPACE, CPU::FUNCTION, DMAFunction &, void * = nullptr, + uint64_t = 0); +uint64_t applyLatency(CPU::NAMESPACE, CPU::FUNCTION); + +void commonCPUHandler(uint64_t, void *); + +// Defined at sim/cpu.cc +extern DMAFunction cpuHandler; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/dma_interface.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/dma_interface.hh new file mode 100644 index 0000000000..40af0d1b1a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/dma_interface.hh @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_DMA_INTERFACE__ +#define __SIM_DMA_INTERFACE__ + +#include +#include + +namespace SimpleSSD { + +typedef std::function DMAFunction; + +typedef struct _DMAContext { + int counter; + DMAFunction function; + void *context; + + _DMAContext(DMAFunction &f) : counter(0), function(f), context(nullptr) {} + _DMAContext(DMAFunction &f, void *c) : counter(0), function(f), context(c) {} +} DMAContext; + +class DMAInterface { + public: + DMAInterface() {} + virtual ~DMAInterface() {} + + virtual void dmaRead(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; + virtual void dmaWrite(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) = 0; +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/log.cc b/hotness/SimpleSSD-Standalone/simplessd/sim/log.cc new file mode 100644 index 0000000000..31335f0368 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/log.cc @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/log.hh" +#include "sim/trace.hh" + +#include +#include +#include +#include +#include + +#include "util/simplessd.hh" + +namespace SimpleSSD { + +struct Logger { + std::ostream *outfile; + std::ostream *errfile; + + Logger(std::ostream *o, std::ostream *e) : outfile(o), errfile(e) {} +}; + +Logger *logger = nullptr; + +void panic(const char *format, ...) { + if (logger) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + if (logger->errfile) { + *(logger->errfile) << getTick() << ": panic: " << str.data() << std::endl; + } + else { + std::cerr << getTick() << ": panic: " << str.data() << std::endl; + } + } + + std::terminate(); +} + +void warn(const char *format, ...) { + if (logger && logger->errfile) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + *(logger->errfile) << getTick() << ": warn: " << str.data() << std::endl; + } +} + +void info(const char *format, ...) { + if (logger && logger->errfile) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + *(logger->errfile) << getTick() << ": info: " << str.data() << std::endl; + } +} + +const std::string logName[LOG_NUM] = { + "global", //!< LOG_COMMON + "CPU", //!< LOG_CPU + "HIL", //!< LOG_HIL + "HIL::NVMe", //!< LOG_HIL_NVME + "HIL::SATA", //!< LOG_HIL_SATA + "HIL::UFS", //!< LOG_HIL_UFS + "ICL", //!< LOG_ICL + "ICL::GenericCache", //!< LOG_ICL_GENERIC_CACHE + "FTL", //!< LOG_FTL + "FTL::PageMapping", //!< LOG_FTL_PAGE_MAPPING + "PAL", //!< LOG_PAL + "PAL::PALOLD", //!< LOG_PAL_OLD +}; + +void debugprint(LOG_ID id, const char *format, ...) { + if (logger && logger->outfile && id < LOG_NUM) { + va_list args, copied; + std::vector str; + + va_start(args, format); + va_copy(copied, args); + str.resize(vsnprintf(nullptr, 0, format, args) + 1); + va_end(args); + vsnprintf(str.data(), str.size(), format, copied); + va_end(copied); + + *(logger->outfile) << getTick() << ": " << logName[id] << ": " << str.data() + << std::endl; + } +} + +void debugprint(LOG_ID id, const uint8_t *buffer, uint64_t size) { + if (logger && logger->outfile && id < LOG_NUM) { + uint32_t temp; + + temp = id; + logger->outfile->write((char *)&temp, 4); + logger->outfile->write((char *)&size, 8); + logger->outfile->write((const char *)buffer, size); + } +} + +void initLogSystem(std::ostream *out, std::ostream *err) { + destroyLogSystem(); + + logger = new Logger(out, err); +} + +void destroyLogSystem() { + delete logger; +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/log.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/log.hh new file mode 100644 index 0000000000..23df8293fd --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/log.hh @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_LOG__ +#define __SIM_LOG__ + +#include + +namespace SimpleSSD { + +void initLogSystem(std::ostream *, std::ostream *); +void destroyLogSystem(); + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/simulator.cc b/hotness/SimpleSSD-Standalone/simplessd/sim/simulator.cc new file mode 100644 index 0000000000..8e3c2d1682 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/simulator.cc @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/simulator.hh" + +namespace SimpleSSD { + +// Defined in sim/simulator.hh +Simulator *sim = nullptr; + +void setSimulator(Simulator *p) { + sim = p; +} + +uint64_t getTick() { + if (sim) { + return sim->getCurrentTick(); + } + + return 0; +} + +Event allocate(EventFunction f) { + if (sim) { + return sim->allocateEvent(f); + } + + return 0; +} + +void schedule(Event e, uint64_t t) { + if (sim) { + sim->scheduleEvent(e, t); + } +} + +void deschedule(Event e) { + if (sim) { + sim->descheduleEvent(e); + } +} + +bool scheduled(Event e, uint64_t *p) { + if (sim) { + return sim->isScheduled(e, p); + } + + return false; +} + +void deallocate(Event e) { + if (sim) { + sim->deallocateEvent(e); + } +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/simulator.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/simulator.hh new file mode 100644 index 0000000000..9a1d27e5b6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/simulator.hh @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_SIMULATOR__ +#define __SIM_SIMULATOR__ + +#include +#include + +#include "sim/config_reader.hh" + +namespace SimpleSSD { + +typedef uint64_t Event; +typedef std::function EventFunction; + +class Simulator { + public: + Simulator() {} + virtual ~Simulator() {} + + virtual uint64_t getCurrentTick() = 0; + + virtual Event allocateEvent(EventFunction) = 0; + virtual void scheduleEvent(Event, uint64_t) = 0; + virtual void descheduleEvent(Event) = 0; + virtual bool isScheduled(Event, uint64_t * = nullptr) = 0; + virtual void deallocateEvent(Event) = 0; +}; + +void setSimulator(Simulator *p); +uint64_t getTick(); +Event allocate(EventFunction f); +void schedule(Event e, uint64_t t); +void deschedule(Event e); +bool scheduled(Event e, uint64_t *p = nullptr); +void deallocate(Event e); + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/state.cc b/hotness/SimpleSSD-Standalone/simplessd/sim/state.cc new file mode 100644 index 0000000000..728b0446a9 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/state.cc @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "sim/state.hh" + +#include + +#include "sim/trace.hh" + +namespace SimpleSSD { + +template +void StateObject::pushValue(std::vector &data, T value) { + uint32_t valueSize = sizeof(value); + uint8_t *src = (uint8_t *)&value; + uint8_t *dst = nullptr; + + data.resize(data.size() + valueSize); + + dst = data.data() + data.size() - valueSize; + memcpy(dst, src, valueSize); +} + +template +void StateObject::popValue(std::vector &data, T value) { + uint32_t valueSize = sizeof(value); + uint8_t *dst = (uint8_t *)&value; + uint8_t *src = nullptr; + + if (data.size() < valueSize) { + panic("Invalid data stream size"); + } + + src = data.data() + data.size() - valueSize; + memcpy(dst, src, valueSize); + + data.erase(data.begin() + data.size() - valueSize, data.end()); +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/state.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/state.hh new file mode 100644 index 0000000000..b74789dbc0 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/state.hh @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_STATE__ +#define __SIM_STATE__ + +#include +#include + +namespace SimpleSSD { + +class StateObject { + protected: + template + static void pushValue(std::vector &, T); + template + static void popValue(std::vector &, T); + + public: + StateObject() {} + virtual ~StateObject() {} + + virtual void saveState(std::vector &) {} + virtual void loadState(std::vector &) {} +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/statistics.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/statistics.hh new file mode 100644 index 0000000000..7ee6f9eb5c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/statistics.hh @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_STATISTICS__ +#define __SIM_STATISTICS__ + +#include +#include +#include + +namespace SimpleSSD { + +typedef struct { + std::string name; + std::string desc; +} Stats; + +class StatObject { + public: + StatObject() {} + virtual ~StatObject() {} + + virtual void getStatList(std::vector &, std::string) {} + virtual void getStatValues(std::vector &) {} + virtual void resetStatValues() {} +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/sim/trace.hh b/hotness/SimpleSSD-Standalone/simplessd/sim/trace.hh new file mode 100644 index 0000000000..2bdd0c423d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/sim/trace.hh @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __SIM_TRACE__ +#define __SIM_TRACE__ + +#include + +namespace SimpleSSD { + +typedef enum { + LOG_COMMON, + LOG_CPU, + LOG_HIL, + LOG_HIL_NVME, + LOG_HIL_SATA, + LOG_HIL_UFS, + LOG_ICL, + LOG_ICL_GENERIC_CACHE, + LOG_FTL, + LOG_FTL_PAGE_MAPPING, + LOG_PAL, + LOG_PAL_OLD, + LOG_NUM +} LOG_ID; + +void debugprint(LOG_ID, const char *, ...); +void debugprint(LOG_ID, const uint8_t *, uint64_t); + +void panic(const char *, ...); +void warn(const char *, ...); +void info(const char *, ...); + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/algorithm.hh b/hotness/SimpleSSD-Standalone/simplessd/util/algorithm.hh new file mode 100644 index 0000000000..03ee065859 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/algorithm.hh @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_ALGORITHM__ +#define __UTIL_ALGORITHM__ + +#include +#include +#include + +#ifdef _MSC_VER + +#include + +#include + +#define __builtin_bswap16 _byteswap_ushort +#define __builtin_bswap32 _byteswap_ulong +#define __builtin_bswap64 _byteswap_uint64 + +inline uint32_t __builtin_clzl(uint32_t val) { + unsigned long leadingZero = 0; + + if (_BitScanReverse(&leadingZero, val)) { + return 31 - leadingZero; + } + + return 32; +} + +inline uint32_t __builtin_ffsl(uint32_t val) { + unsigned long trailingZero = 0; + + if (_BitScanForward(&trailingZero, val)) { + return trailingZero + 1; + } + + return 0; +} + +#endif + +#ifndef MIN +#define MIN(x, y) ((x) > (y) ? (y) : (x)) +#endif + +#ifndef MAX +#define MAX(x, y) ((x) > (y) ? (x) : (y)) +#endif + +#define DIVCEIL(x, y) (((x)-1) / (y) + 1) + +namespace SimpleSSD { + +template +uint8_t popcount(T v) { + v = v - ((v >> 1) & (T) ~(T)0 / 3); + v = (v & (T) ~(T)0 / 15 * 3) + ((v >> 2) & (T) ~(T)0 / 15 * 3); + v = (v + (v >> 4)) & (T) ~(T)0 / 255 * 15; + v = (T)(v * ((T) ~(T)0 / 255)) >> (sizeof(T) - 1) * CHAR_BIT; + + return (uint8_t)v; +} + +inline uint64_t generateMask(uint32_t val, uint32_t &count) { + uint64_t mask = (uint64_t)-1; + uint32_t tmp = 0; + + if (val > 0) { + int shift = __builtin_clzl(val); + + if (shift + __builtin_ffsl(val) == 64) { + shift++; + } + + tmp = 64 - shift; + mask = (mask << tmp); + } + + mask = (~mask) << count; + count += tmp; + + return mask; +} + +inline uint16_t bswap16(uint16_t val) { + return __builtin_bswap16(val); +} + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/bitset.cc b/hotness/SimpleSSD-Standalone/simplessd/util/bitset.cc new file mode 100644 index 0000000000..559fd478af --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/bitset.cc @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/bitset.hh" + +#include +#include + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +Bitset::Bitset() : data(nullptr), dataSize(0), allocSize(0) {} + +Bitset::Bitset(uint32_t size) : Bitset() { + if (size > 0) { + dataSize = size; + allocSize = DIVCEIL(dataSize, 8); + data = (uint8_t *)calloc(allocSize, 1); + } +} + +Bitset::Bitset(const Bitset &rhs) : Bitset(rhs.dataSize) { + if (rhs.data) { + memcpy(data, rhs.data, allocSize); + } +} + +Bitset::Bitset(Bitset &&rhs) noexcept { + dataSize = std::move(rhs.dataSize); + allocSize = std::move(rhs.allocSize); + data = std::move(rhs.data); + + rhs.dataSize = 0; + rhs.allocSize = 0; + rhs.data = nullptr; +} + +Bitset::~Bitset() { + free(data); + + data = nullptr; + dataSize = 0; + allocSize = 0; +} + +bool Bitset::test(uint32_t idx) noexcept { + return data[idx / 8] & (0x01 << (idx % 8)); +} + +bool Bitset::all() noexcept { + uint8_t ret = 0xFF; + uint8_t mask = 0xFF << (dataSize + 8 - allocSize * 8); + + for (uint32_t i = 0; i < allocSize - 1; i++) { + ret &= data[i]; + } + + ret &= data[allocSize - 1] | mask; + + return ret == 0xFF; +} + +bool Bitset::any() noexcept { + return !none(); +} + +bool Bitset::none() noexcept { + uint8_t ret = 0x00; + + for (uint32_t i = 0; i < allocSize; i++) { + ret |= data[i]; + } + + return ret == 0x00; +} + +uint32_t Bitset::count() noexcept { + uint32_t count = 0; + + for (uint32_t i = 0; i < allocSize; i++) { + count += popcount(data[i]); + } + + return count; +} + +uint32_t Bitset::size() noexcept { + return dataSize; +} + +void Bitset::set() noexcept { + uint8_t mask = 0xFF >> (allocSize * 8 - dataSize); + + for (uint32_t i = 0; i < allocSize - 1; i++) { + data[i] = 0xFF; + } + + data[allocSize - 1] = mask; +} + +void Bitset::set(uint32_t idx, bool value) noexcept { + data[idx / 8] &= ~(0x01 << (idx % 8)); + + if (value) { + data[idx / 8] = data[idx / 8] | (0x01 << (idx % 8)); + } +} + +void Bitset::reset() noexcept { + for (uint32_t i = 0; i < allocSize; i++) { + data[i] = 0x00; + } +} + +void Bitset::reset(uint32_t idx) noexcept { + data[idx / 8] &= ~(0x01 << (idx % 8)); +} + +void Bitset::flip() noexcept { + uint8_t mask = 0xFF >> (allocSize * 8 - dataSize); + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] = ~data[i]; + } + + data[allocSize - 1] &= mask; +} + +void Bitset::flip(uint32_t idx) noexcept { + data[idx / 8] = (~data[idx / 8] & (0x01 << (idx % 8))) | + (data[idx / 8] & ~(0x01 << (idx % 8))); +} + +bool Bitset::operator[](uint32_t idx) noexcept { + return test(idx); +} + +Bitset &Bitset::operator&=(const Bitset &rhs) { + if (dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] &= rhs.data[i]; + } + + return *this; +} + +Bitset &Bitset::operator|=(const Bitset &rhs) { + if (dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] |= rhs.data[i]; + } + + return *this; +} + +Bitset &Bitset::operator^=(const Bitset &rhs) { + if (dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < allocSize; i++) { + data[i] ^= rhs.data[i]; + } + + return *this; +} + +Bitset &Bitset::operator=(const Bitset &rhs) { + if (this != &rhs) { + free(data); + data = nullptr; + + *this = Bitset(rhs); + } + + return *this; +} + +Bitset &Bitset::operator=(Bitset &&rhs) noexcept { + if (this != &rhs) { + free(data); + + dataSize = std::move(rhs.dataSize); + allocSize = std::move(rhs.allocSize); + data = std::move(rhs.data); + + rhs.dataSize = 0; + rhs.allocSize = 0; + rhs.data = nullptr; + } + + return *this; +} + +Bitset Bitset::operator~() const { + Bitset ret(*this); + + ret.flip(); + + return ret; +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/bitset.hh b/hotness/SimpleSSD-Standalone/simplessd/util/bitset.hh new file mode 100644 index 0000000000..f0b2854e64 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/bitset.hh @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_BITSET__ +#define __UTIL_BITSET__ + +#include +#include + +#include "sim/trace.hh" + +namespace SimpleSSD { + +// TODO: use SIMD operation if possible +class Bitset { + private: + uint8_t *data; + uint32_t dataSize; + uint32_t allocSize; + + public: + Bitset(); + Bitset(uint32_t); + Bitset(const Bitset &); + Bitset(Bitset &&) noexcept; + ~Bitset(); + + bool test(uint32_t) noexcept; + bool all() noexcept; + bool any() noexcept; + bool none() noexcept; + uint32_t count() noexcept; + uint32_t size() noexcept; + void set() noexcept; + void set(uint32_t, bool = true) noexcept; + void reset() noexcept; + void reset(uint32_t) noexcept; + void flip() noexcept; + void flip(uint32_t) noexcept; + + bool operator[](uint32_t) noexcept; + Bitset &operator&=(const Bitset &); + Bitset &operator|=(const Bitset &); + Bitset &operator^=(const Bitset &); + Bitset &operator=(const Bitset &); + Bitset &operator=(Bitset &&) noexcept; + Bitset operator~() const; + + friend Bitset &operator&(Bitset lhs, const Bitset &rhs) { return lhs &= rhs; } + friend Bitset &operator|(Bitset lhs, const Bitset &rhs) { return lhs |= rhs; } + friend Bitset &operator^(Bitset lhs, const Bitset &rhs) { return lhs ^= rhs; } + friend bool operator==(const Bitset &lhs, const Bitset &rhs) { + bool ret = true; + + if (lhs.dataSize != rhs.dataSize) { + panic("Size does not match"); + } + + for (uint32_t i = 0; i < lhs.allocSize; i++) { + if (lhs.data[i] != rhs.data[i]) { + ret = false; + + break; + } + } + + return ret; + } + + friend bool operator!=(const Bitset &lhs, const Bitset &rhs) { + return !operator==(lhs, rhs); + } +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/def.cc b/hotness/SimpleSSD-Standalone/simplessd/util/def.cc new file mode 100644 index 0000000000..e7e28af5e4 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/def.cc @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/def.hh" + +#include +#include + +namespace SimpleSSD { + +LPNRange::_LPNRange() : slpn(0), nlp(0) {} + +LPNRange::_LPNRange(uint64_t s, uint64_t n) : slpn(s), nlp(n) {} + +namespace HIL { + +Request::_Request() + : reqID(0), + reqSubID(0), + offset(0), + length(0), + finishedAt(0), + temperature(0), + context(nullptr) {} + +Request::_Request(DMAFunction &f, void *c) + : reqID(0), + reqSubID(0), + offset(0), + length(0), + finishedAt(0), + temperature(0), + function(f), + context(c) {} + +bool Request::operator()(const Request &a, const Request &b) { + return a.finishedAt > b.finishedAt; +} + +} // namespace HIL + +namespace ICL { + +Request::_Request() : reqID(0), reqSubID(0), offset(0), length(0),temperature(0) {} + +Request::_Request(HIL::Request &r) + : reqID(r.reqID), + reqSubID(r.reqSubID), + offset(r.offset), + length(r.length), + range(r.range), + temperature(r.temperature) {}; +} // namespace ICL + +namespace FTL { + +Request::_Request(uint32_t iocount) + : reqID(0), reqSubID(0), lpn(0), ioFlag(iocount),temperature(0) {} + +Request::_Request(uint32_t iocount, ICL::Request &r) + : reqID(r.reqID), + reqSubID(r.reqSubID), + lpn(r.range.slpn / iocount), + ioFlag(iocount), + temperature(r.temperature) { + ioFlag.set(r.range.slpn % iocount); +} + +} // namespace FTL + +namespace PAL { + +Request::_Request(uint32_t iocount) + : reqID(0), reqSubID(0), blockIndex(0), pageIndex(0), ioFlag(iocount) {} + +Request::_Request(FTL::Request &r) + : reqID(r.reqID), + reqSubID(r.reqSubID), + blockIndex(0), + pageIndex(0), + ioFlag(r.ioFlag) {} + +} // namespace PAL + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/def.hh b/hotness/SimpleSSD-Standalone/simplessd/util/def.hh new file mode 100644 index 0000000000..826198a93c --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/def.hh @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_DEF__ +#define __UTIL_DEF__ + +#include + +#include "sim/dma_interface.hh" +#include "util/bitset.hh" + +namespace SimpleSSD { + +typedef struct _LPNRange { + uint64_t slpn; + uint64_t nlp; + + _LPNRange(); + _LPNRange(uint64_t, uint64_t); +} LPNRange; + +namespace HIL { + +typedef struct _Request { + uint64_t reqID; + uint64_t reqSubID; + uint64_t offset; + uint64_t length; + LPNRange range; + uint64_t finishedAt; + int temperature; + DMAFunction function; + void *context; + + _Request(); + _Request(DMAFunction &, void *); + + bool operator()(const _Request &a, const _Request &b); +} Request; + +} // namespace HIL + +namespace ICL { + +typedef struct _Request { + uint64_t reqID; + uint64_t reqSubID; + uint64_t offset; + uint64_t length; + LPNRange range; + int temperature; + _Request(); + _Request(HIL::Request &); +} Request; + +} // namespace ICL + +namespace FTL { + +typedef struct _Request { + uint64_t reqID; // ID of ICL::Request + uint64_t reqSubID; + uint64_t lpn; + Bitset ioFlag; + int temperature; + _Request(uint32_t); + _Request(uint32_t, ICL::Request &); +} Request; + +} // namespace FTL + +namespace PAL { + +typedef struct _Request { + uint64_t reqID; // ID of ICL::Request + uint64_t reqSubID; + uint32_t blockIndex; + uint32_t pageIndex; + Bitset ioFlag; + _Request(uint32_t); + _Request(FTL::Request &); +} Request; + +} // namespace PAL + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/disk.cc b/hotness/SimpleSSD-Standalone/simplessd/util/disk.cc new file mode 100644 index 0000000000..1987d7b0a6 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/disk.cc @@ -0,0 +1,314 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/disk.hh" + +#include + +#ifdef _MSC_VER +#include +#else +#include +#include +#endif + +namespace SimpleSSD { + +Disk::Disk() : diskSize(0), sectorSize(0) {} + +Disk::~Disk() { + close(); +} + +uint64_t Disk::open(std::string path, uint64_t desiredSize, uint32_t lbaSize) { + filename = path; + sectorSize = lbaSize; + + // Validate size +#ifdef _MSC_VER + LARGE_INTEGER size; + HANDLE hFile = CreateFileA(path.c_str(), GENERIC_READ | GENERIC_WRITE, NULL, + NULL, OPEN_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); + + if (GetLastError() == ERROR_ALREADY_EXISTS) { + if (GetFileSizeEx(hFile, &size)) { + diskSize = size.QuadPart; + } + else { + // panic("Get file size failed!"); + } + } + else { + size.QuadPart = desiredSize; + + if (SetFilePointerEx(hFile, size, nullptr, FILE_BEGIN)) { + if (SetEndOfFile(hFile)) { + diskSize = desiredSize; + } + else { + // panic("SetEndOfFile failed"); + } + } + else { + // panic("SetFilePointerEx failed"); + } + } + + CloseHandle(hFile); +#else + struct stat s; + + if (stat(filename.c_str(), &s) == 0) { + // File exists + if (S_ISREG(s.st_mode)) { + diskSize = s.st_size; + } + else { + // panic("nvme_disk: Specified file %s is not regular file.\n", + // filename.c_str()); + } + } + else { + // Create zero-sized file + disk.open(filename, std::ios::out | std::ios::binary); + disk.close(); + + // Set file size + if (truncate(filename.c_str(), desiredSize) == 0) { + diskSize = desiredSize; + } + else { + // panic("nvme_disk: Failed to set disk size %" PRIu64 " errno=%d\n", + // diskSize, errno); + } + } +#endif + + // Open file + disk.open(filename, std::ios::in | std::ios::out | std::ios::binary); + + if (!disk.is_open()) { + // panic("failed to open file"); + } + + return diskSize; +} + +void Disk::close() { + if (disk.is_open()) { + disk.close(); + } +} + +uint16_t Disk::read(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t ret = 0; + + if (disk.is_open()) { + uint64_t avail; + + slba *= sectorSize; + avail = nlblk * sectorSize; + + if (slba + avail > diskSize) { + if (slba >= diskSize) { + avail = 0; + } + else { + avail = diskSize - slba; + } + } + + if (avail > 0) { + disk.seekg(slba, std::ios::beg); + if (!disk.good()) { + // panic("nvme_disk: Fail to seek to %" PRIu64 "\n", slba); + } + + disk.read((char *)buffer, avail); + } + + memset(buffer + avail, 0, nlblk * sectorSize - avail); + + // DPRINTF(NVMeDisk, "DISK | READ | BYTE %016" PRIX64 " + %X\n", + // slba, nlblk * sectorSize); + + ret = nlblk; + } + + return ret; +} + +uint16_t Disk::write(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t ret = 0; + + if (disk.is_open()) { + slba *= sectorSize; + + disk.seekp(slba, std::ios::beg); + if (!disk.good()) { + // panic("nvme_disk: Fail to seek to %" PRIu64 "\n", slba); + } + + uint64_t offset = disk.tellp(); + disk.write((char *)buffer, sectorSize * nlblk); + offset = (uint64_t)disk.tellp() - offset; + + // DPRINTF(NVMeDisk, "DISK | WRITE | BYTE %016" PRIX64 " + %X\n", slba, + // offset); + + ret = offset / sectorSize; + } + + return ret; +} + +uint16_t Disk::erase(uint64_t, uint16_t nlblk) { + return nlblk; +} + +CoWDisk::CoWDisk() {} + +CoWDisk::~CoWDisk() { + close(); +} + +void CoWDisk::close() { + table.clear(); + + Disk::close(); +} + +uint16_t CoWDisk::read(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t read = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(buffer + i * sectorSize, block->second.data(), sectorSize); + read++; + } + else { + read += Disk::read(slba + i, 1, buffer + i * sectorSize); + } + } + + return read; +} + +uint16_t CoWDisk::write(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t write = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(block->second.data(), buffer + i * sectorSize, sectorSize); + } + else { + std::vector data; + + data.resize(sectorSize); + memcpy(data.data(), buffer + i * sectorSize, sectorSize); + + table.insert({slba + i, data}); + } + + write++; + } + + return write; +} + +uint64_t MemDisk::open(std::string, uint64_t size, uint32_t lbaSize) { + diskSize = size; + sectorSize = lbaSize; + + return size; +} + +void MemDisk::close() { + table.clear(); +} + +MemDisk::MemDisk() {} + +MemDisk::~MemDisk() { + close(); +} + +uint16_t MemDisk::read(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t read = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(buffer + i * sectorSize, block->second.data(), sectorSize); + } + else { + memset(buffer + i * sectorSize, 0, sectorSize); + } + + read++; + } + + return read; +} + +uint16_t MemDisk::write(uint64_t slba, uint16_t nlblk, uint8_t *buffer) { + uint16_t write = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + memcpy(block->second.data(), buffer + i * sectorSize, sectorSize); + } + else { + std::vector data; + + data.resize(sectorSize); + memcpy(data.data(), buffer + i * sectorSize, sectorSize); + + table.insert({slba + i, data}); + } + + write++; + } + + return write; +} +uint16_t MemDisk::erase(uint64_t slba, uint16_t nlblk) { + uint16_t erase = 0; + + for (uint64_t i = 0; i < nlblk; i++) { + auto block = table.find(slba + i); + + if (block != table.end()) { + table.erase(block); + } + + erase++; + } + + return erase; +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/disk.hh b/hotness/SimpleSSD-Standalone/simplessd/util/disk.hh new file mode 100644 index 0000000000..77342c2d7a --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/disk.hh @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_DISK__ +#define __UTIL_DISK__ + +#include +#include +#include +#include +#include + +namespace SimpleSSD { + +class Disk { + protected: + std::string filename; + uint64_t diskSize; + uint32_t sectorSize; + + std::fstream disk; + + public: + Disk(); + Disk(const Disk &) = delete; + virtual ~Disk(); + + virtual uint64_t open(std::string, uint64_t, uint32_t); + virtual void close(); + + virtual uint16_t read(uint64_t, uint16_t, uint8_t *); + virtual uint16_t write(uint64_t, uint16_t, uint8_t *); + virtual uint16_t erase(uint64_t, uint16_t); +}; + +class CoWDisk : public Disk { + private: + std::unordered_map> table; + + public: + CoWDisk(); + CoWDisk(const CoWDisk &) = delete; + ~CoWDisk(); + + void close() override; + + uint16_t read(uint64_t, uint16_t, uint8_t *) override; + uint16_t write(uint64_t, uint16_t, uint8_t *) override; +}; + +class MemDisk : public Disk { + private: + std::unordered_map> table; + + public: + MemDisk(); + MemDisk(const MemDisk &) = delete; + ~MemDisk(); + + uint64_t open(std::string, uint64_t, uint32_t) override; + void close() override; + + uint16_t read(uint64_t, uint16_t, uint8_t *) override; + uint16_t write(uint64_t, uint16_t, uint8_t *) override; + uint16_t erase(uint64_t, uint16_t) override; +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/fifo.cc b/hotness/SimpleSSD-Standalone/simplessd/util/fifo.cc new file mode 100644 index 0000000000..50a7cdc8dc --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/fifo.cc @@ -0,0 +1,421 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/fifo.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +FIFOEntry::FIFOEntry() + : last(true), + id(0), + addr(0), + size(0), + buffer(nullptr), + arrivedAt(0), + insertBeginAt(0), + insertEndAt(0), + context(nullptr) {} + +FIFOEntry::FIFOEntry(uint64_t a, uint64_t s, uint8_t *b, DMAFunction &f, + void *c) + : last(true), + id(0), + addr(a), + size(s), + buffer(b), + arrivedAt(getTick()), + insertBeginAt(0), + insertEndAt(0), + func(f), + context(c) {} + +ReadEntry::ReadEntry() : id(0), insertEndAt(0), dmaEndAt(0), latency(0) {} + +ReadEntry::ReadEntry(uint64_t a, uint64_t i, uint64_t d, uint64_t l) + : id(a), insertEndAt(i), dmaEndAt(d), latency(l) {} + +FIFO::Queue::Queue(uint64_t c) + : capacity(c), usage(0), insertPending(false), transferPending(false) {} + +FIFO::FIFO(DMAInterface *up, FIFOParam &p) + : upstream(up), + param(p), + readQueue(p.rqSize), + writeQueue(p.wqSize), + counter(0) { + // Sanity check + if (param.transferUnit > param.rqSize || param.transferUnit > param.wqSize) { + panic("Invalid transferUnit size"); + } + + // Set Transfer Unit Latency + unitLatency = param.latency(param.transferUnit); + + // Allocate events and functions for each queue + writeQueue.insertDone = allocate([this](uint64_t) { insertWriteDone(); }); + writeQueue.beginTransfer = allocate([this](uint64_t) { transferWrite(); }); + writeQueue.submitCompletion = + allocate([this](uint64_t) { transferWriteDoneNext(); }); + writeQueue.transferDone = [this](uint64_t, void *) { transferWriteDone(); }; + readQueue.insertDone = allocate([this](uint64_t) { insertReadDone(); }); + readQueue.beginTransfer = allocate([this](uint64_t) { insertRead(); }); + readQueue.submitCompletion = + allocate([this](uint64_t) { insertReadDoneNext(); }); + readQueue.transferDone = [this](uint64_t, void *) { transferReadDone(); }; +} + +FIFO::~FIFO() {} + +std::list::iterator FIFO::find(uint64_t id) { + auto iter = readCompletion.begin(); + + for (; iter != readCompletion.end(); iter++) { + if (iter->id == id) { + break; + } + } + + return iter; +} + +uint64_t FIFO::calcSize(uint64_t size, bool &b) { + if (size < param.transferUnit) { + b = true; + + return size; + } + + return DIVCEIL(size, param.transferUnit) * param.transferUnit; +} + +void FIFO::insertWrite() { + auto iter = writeQueue.waitQueue.begin(); + bool smallerThanUnit = false; + uint64_t now = getTick(); + uint64_t size = calcSize(iter->size, smallerThanUnit); + + if ((writeQueue.insertPending || + writeQueue.usage + size > writeQueue.capacity) && + size <= param.wqSize) { + return; + } + + // We need to split large request + if (size > param.wqSize) { + FIFOEntry copy = *iter; + + // copy is next one + copy.last = true; + copy.addr = iter->addr + param.transferUnit; + copy.size = iter->size - param.transferUnit; + copy.buffer = iter->buffer ? iter->buffer + param.transferUnit : nullptr; + + // iter is current one + iter->last = false; + iter->size = param.transferUnit; + + // Insert copy after iter + writeQueue.waitQueue.insert(++iter, copy); + + // iter should first one + iter = writeQueue.waitQueue.begin(); + size = calcSize(iter->size, smallerThanUnit); + } + + writeQueue.insertPending = true; + + // Current item will be written to FIFO + writeQueue.usage += size; + iter->insertBeginAt = now; + iter->insertEndAt = now + param.latency(size); + + // When insertion done, call handler + schedule(writeQueue.insertDone, iter->insertEndAt); + + // Current item will be transferred after one transferUnit written to FIFO + // If we alwritey scheduled, current item will be transffered after last one + if (!scheduled(writeQueue.beginTransfer)) { + schedule(writeQueue.beginTransfer, + now + (smallerThanUnit ? param.latency(size) : unitLatency)); + } + + // Push current item to transferQueue + writeQueue.transferQueue.push(*iter); +} + +void FIFO::insertWriteDone() { + // Pop last item + writeQueue.waitQueue.pop_front(); + writeQueue.insertPending = false; + + // Insert next waiting item + if (writeQueue.waitQueue.size() > 0) { + insertWrite(); + } +} + +void FIFO::transferWrite() { + auto &iter = writeQueue.transferQueue.front(); + + if (writeQueue.transferPending) { + return; + } + + writeQueue.transferPending = true; + + // Begin transfer + upstream->dmaWrite(iter.addr, iter.size, iter.buffer, + writeQueue.transferDone); +} + +void FIFO::transferWriteDone() { + auto &iter = writeQueue.transferQueue.front(); + uint64_t now = getTick(); + uint64_t latency = + (iter.size < param.transferUnit) ? param.latency(iter.size) : unitLatency; + + if (now >= iter.insertEndAt + latency) { // Upstream <= downstream + // Finish immediately + transferWriteDoneNext(); + } + else { // upstream is faster than downstream + // Should finish at insertedEndAt + upstreamLatency(transferUnit) + // TODO: Applying unitLatency is not correct (more slower result) + schedule(writeQueue.submitCompletion, iter.insertEndAt + latency); + } +} + +void FIFO::transferWriteDoneNext() { + auto &iter = writeQueue.transferQueue.front(); + bool unused; + uint64_t now = getTick(); + + // Call handler + if (iter.last) { + iter.func(now, iter.context); + } + + // Transfer done + writeQueue.usage -= calcSize(iter.size, unused); + writeQueue.transferPending = false; + writeQueue.transferQueue.pop(); + + // Do next transfer if we have + if (writeQueue.transferQueue.size() > 0) { + if (!scheduled(writeQueue.beginTransfer)) { + transferWrite(); + } + } + + // Do next insertion if we have + if (writeQueue.waitQueue.size() > 0) { + insertWrite(); + } +} + +void FIFO::transferRead() { + auto iter = readQueue.waitQueue.begin(); + bool smallerThanUnit = false; + uint64_t size = calcSize(iter->size, smallerThanUnit); + + if ((readQueue.transferPending || + readQueue.usage + size > readQueue.capacity) && + size <= param.rqSize) { + return; + } + + // We need to split large request + if (size > param.rqSize) { + FIFOEntry copy = *iter; + + // copy is next one + copy.last = true; + copy.addr = iter->addr + param.transferUnit; + copy.size = iter->size - param.transferUnit; + copy.buffer = iter->buffer ? iter->buffer + param.transferUnit : nullptr; + + // iter is current one + iter->last = false; + iter->size = param.transferUnit; + + // Insert copy after iter + readQueue.waitQueue.insert(++iter, copy); + + // iter should first one + iter = readQueue.waitQueue.begin(); + size = calcSize(iter->size, smallerThanUnit); + } + + readQueue.transferPending = true; + + // Set ID + iter->id = counter++; + + // Current item will be requested to be read + readQueue.usage += size; + + // When all data is read to FIFO, call handler + upstream->dmaRead(iter->addr, iter->size, iter->buffer, + readQueue.transferDone); + + if (!scheduled(readQueue.beginTransfer)) { + schedule(readQueue.beginTransfer, + getTick() + (smallerThanUnit ? param.latency(size) : unitLatency)); + } + + // Push current item to transferQueue + readQueue.transferQueue.push(*iter); +} + +void FIFO::transferReadDone() { + auto &iter = readQueue.waitQueue.front(); + uint64_t latency = + (iter.size < param.transferUnit) ? param.latency(iter.size) : unitLatency; + + // Save DMA end time + auto comp = find(iter.id); + + if (comp == readCompletion.end()) { + readCompletion.push_back(ReadEntry(iter.id, 0, getTick(), latency)); + } + else { + comp->dmaEndAt = getTick(); + + insertReadDoneMerge(comp); + } + + // Pop last item + readQueue.waitQueue.pop_front(); + readQueue.transferPending = false; + + // Transfer next waiting item + if (readQueue.waitQueue.size() > 0) { + transferRead(); + } +} + +void FIFO::insertRead() { + auto &iter = readQueue.transferQueue.front(); + bool unused; + uint64_t now = getTick(); + + if (readQueue.insertPending) { + return; + } + + readQueue.insertPending = true; + + // Begin insertion + iter.insertBeginAt = now; + iter.insertEndAt = now + param.latency(calcSize(iter.size, unused)); + + // When insertion done, call handler + if (!scheduled(readQueue.insertDone)) { + schedule(readQueue.insertDone, iter.insertEndAt); + } +} + +void FIFO::insertReadDone() { + auto &iter = readQueue.transferQueue.front(); + uint64_t latency = + (iter.size < param.transferUnit) ? param.latency(iter.size) : unitLatency; + + auto comp = find(iter.id); + + if (comp == readCompletion.end()) { + readCompletion.push_back(ReadEntry(iter.id, getTick(), 0, latency)); + } + else { + insertReadDoneMerge(comp); + } +} + +void FIFO::insertReadDoneMerge(std::list::iterator comp) { + uint64_t now = getTick(); + + if (now >= comp->dmaEndAt + comp->latency) { // Upstream <= downstream + // Finish immediately + insertReadDoneNext(); + } + else { // upstream is faster than downstream + // Should finish at insertedEndAt + upstreamLatency(transferUnit) + // TODO: Applying unitLatency is not correct (more slower result) + schedule(readQueue.submitCompletion, comp->dmaEndAt + comp->latency); + } + + readCompletion.erase(comp); +} + +void FIFO::insertReadDoneNext() { + auto &iter = readQueue.transferQueue.front(); + bool unused; + uint64_t now = getTick(); + + // Call handler + if (iter.last) { + iter.func(now, iter.context); + } + + // Insert done + readQueue.usage -= calcSize(iter.size, unused); + readQueue.insertPending = false; + readQueue.transferQueue.pop(); + + // Do next insert if we have + if (readQueue.transferQueue.size() > 0) { + if (!scheduled(readQueue.beginTransfer)) { + insertRead(); + } + } + + // Do next transfer if we have + if (readQueue.waitQueue.size() > 0) { + transferRead(); + } +} + +void FIFO::dmaRead(uint64_t addr, uint64_t size, uint8_t *buffer, + DMAFunction &func, void *context) { + if (size == 0) { + warn("FIFO: zero-size DMA read request. Ignore."); + + return; + } + + readQueue.waitQueue.push_back(FIFOEntry(addr, size, buffer, func, context)); + + transferRead(); +} + +void FIFO::dmaWrite(uint64_t addr, uint64_t size, uint8_t *buffer, + DMAFunction &func, void *context) { + if (size == 0) { + warn("FIFO: zero-size DMA write request. Ignore."); + + return; + } + + writeQueue.waitQueue.push_back(FIFOEntry(addr, size, buffer, func, context)); + + insertWrite(); +} + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/fifo.hh b/hotness/SimpleSSD-Standalone/simplessd/util/fifo.hh new file mode 100644 index 0000000000..213b6c72fe --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/fifo.hh @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_FIFO__ +#define __UTIL_FIFO__ + +#include +#include + +#include "sim/dma_interface.hh" +#include "util/simplessd.hh" + +namespace SimpleSSD { + +typedef std::function LatencyFunction; + +struct FIFOParam { + uint64_t rqSize; //!< Read Queue size + uint64_t wqSize; //!< Write Queue size + uint64_t transferUnit; //!< Transfer unit used to interleave DMA + LatencyFunction latency; //!< Downstream latency function +}; + +struct FIFOEntry { + bool last; //!< This is last entry of splitted request + uint64_t id; + + uint64_t addr; + uint64_t size; + uint8_t *buffer; + + uint64_t arrivedAt; //!< Request arrived to FIFO + uint64_t insertBeginAt; //!< Request is now begin to written on FIFO + uint64_t insertEndAt; //!< Request is fully written on FIFO + + DMAFunction func; + void *context; + + FIFOEntry(); + FIFOEntry(uint64_t, uint64_t, uint8_t *, DMAFunction &, void *); +}; + +struct ReadEntry { + uint64_t id; + uint64_t insertEndAt; + uint64_t dmaEndAt; + uint64_t latency; + + ReadEntry(); + ReadEntry(uint64_t, uint64_t, uint64_t, uint64_t); +}; + +class FIFO : public DMAInterface { + protected: + class Queue { + public: + uint64_t capacity; + uint64_t usage; + + std::list waitQueue; + std::queue transferQueue; + + Event insertDone; + Event beginTransfer; + Event submitCompletion; + DMAFunction transferDone; + + bool insertPending; + bool transferPending; + + Queue(uint64_t); + }; + + DMAInterface *upstream; + FIFOParam param; + uint64_t unitLatency; + + Queue readQueue; + Queue writeQueue; + + uint64_t counter; + std::list readCompletion; + + std::list::iterator find(uint64_t); + + uint64_t calcSize(uint64_t, bool &); + + // Write + void insertWrite(); + void insertWriteDone(); + void transferWrite(); + void transferWriteDone(); + void transferWriteDoneNext(); + + // Read + void transferRead(); + void transferReadDone(); + void insertRead(); + void insertReadDone(); + void insertReadDoneMerge(std::list::iterator); + void insertReadDoneNext(); + + public: + FIFO() = delete; + FIFO(DMAInterface *, FIFOParam &); + FIFO(const FIFO &) = delete; + ~FIFO(); + + void dmaRead(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; + void dmaWrite(uint64_t, uint64_t, uint8_t *, DMAFunction &, + void * = nullptr) override; +}; + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/interface.cc b/hotness/SimpleSSD-Standalone/simplessd/util/interface.cc new file mode 100644 index 0000000000..89f35bca53 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/interface.cc @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/interface.hh" + +#include "util/algorithm.hh" + +namespace SimpleSSD { + +namespace PCIExpress { + +static const uint32_t maxPayloadSize = 4096; // Bytes +static const uint32_t packetOverhead = 36; // Bytes +static const uint32_t internalDelay[PCIE_NUM] = {19, 70, 115}; // Symbol +static const float encoding[PCIE_NUM] = {1.25f, 1.25f, 1.015625f}; // Ratio +static const uint32_t delay[PCIE_NUM] = {3200, 1600, 1000}; // pico-second + +uint64_t calculateDelay(PCIE_GEN gen, uint8_t lane, uint64_t bytesize) { + uint64_t nTLP = MAX(DIVCEIL(bytesize, maxPayloadSize), 1); + uint64_t nSymbol; + + nSymbol = bytesize + nTLP * (packetOverhead); + nSymbol = DIVCEIL(nSymbol, lane) + 1 + nTLP * internalDelay[gen]; + + return (uint64_t)(delay[gen] * encoding[gen] * nSymbol + 0.5f); +} + +} // namespace PCIExpress + +namespace SATA { + +// Each primitive is 1 DWORD (4bytes) +// One Fram contains SOF/EOF/CRC and HOLD/A primitives +// Just assume no HOLD/HOLDA + +static const uint32_t packetOverhead = 3; // Primitive +static const uint32_t internalDelay = 12; // DWORD +static const float encoding = 1.25f; // Ratio +static const uint32_t delay[SATA_NUM] = {5336, 2667, 1333}; // pico-second + +uint64_t calculateDelay(SATA_GEN gen, uint64_t bytesize) { + uint64_t dwords = DIVCEIL(bytesize, 4) + internalDelay + packetOverhead; + + dwords = dwords * 4; + + return (uint64_t)(delay[gen] * encoding * dwords + 0.5f); +} + +} // namespace SATA + +namespace MIPI { + +namespace M_PHY { + +// See M-PHY spec v4.0 section 4.7.2 BURST, Figure 14 and 15 +static const uint32_t tLine = 7000; // pico-second +static const uint32_t nPrepare = 15; // Bytes +static const uint32_t nSync = 15; // Bytes +static const uint32_t nStall = 7; // Bytes +static const float encoding = 1.25f; // Ratio +static const uint32_t delay[HS_NUM] = {6410, 3205, 1603, 801}; // pico-second + +uint64_t calculateDelay(M_PHY_MODE mode, uint8_t lane, uint64_t symbol) { + uint64_t nSymbol = nPrepare + nSync + 1 + symbol * 2 + nStall; + + nSymbol = (nSymbol - 1) / lane + 2; + + return (uint64_t)(delay[mode] * encoding * nSymbol + 0.5f + tLine); +} + +} // namespace M_PHY + +namespace UniPro { + +static const uint32_t maxPayloadSize = 254; // Bytes +static const uint32_t packetOverhead = 7; // Symbol + +uint64_t calculateDelay(M_PHY::M_PHY_MODE mode, uint8_t lane, + uint64_t bytesize) { + uint64_t nPacket = MAX((bytesize - 1) / maxPayloadSize + 1, 1); + uint64_t nSymbol = (bytesize + 1) / 2; + + nSymbol += nPacket * packetOverhead; + + return M_PHY::calculateDelay(mode, lane, nSymbol); +} + +} // namespace UniPro + +} // namespace MIPI + +namespace ARM { + +namespace AXI { + +// Two cycles per one data beat +// Two cycles for address, one cycle for write response +// One burst request should contain 1, 2, 4, 8 .. of beats + +static const uint32_t maxPayloadSize = 4096; // Bytes + +uint64_t calculateDelay(uint64_t clock, BUS_WIDTH width, uint64_t bytesize) { + uint32_t nBeats = MAX(DIVCEIL(bytesize, width), 1); + uint32_t nBursts = popcount(nBeats) + (bytesize - 1) / maxPayloadSize; + uint32_t nClocks = nBeats * 2 + nBursts * 3; + uint64_t period = (uint64_t)(1000000000000.0 / clock + 0.5); + + return nClocks * period; +} + +namespace Stream { + +// Unlimited bursts +// If master and slave can handle data sufficiently fast, +// one cycle per one data beat +// No address and responses + +uint64_t calculateDelay(uint64_t clock, BUS_WIDTH width, uint64_t bytesize) { + uint64_t period = (uint64_t)(1000000000000.0 / clock + 0.5); + + return bytesize / width * period; +} + +} // namespace Stream + +} // namespace AXI + +} // namespace ARM + +} // namespace SimpleSSD diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/interface.hh b/hotness/SimpleSSD-Standalone/simplessd/util/interface.hh new file mode 100644 index 0000000000..012b851c9f --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/interface.hh @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_INTERFACE__ +#define __UTIL_INTERFACE__ + +#include + +namespace SimpleSSD { + +namespace PCIExpress { + +typedef enum { + PCIE_1_X, // PCI Express Gen. 1.x + PCIE_2_X, // PCI Express Gen. 2.x + PCIE_3_X, // PCI Express Gen. 3.x + PCIE_NUM +} PCIE_GEN; + +uint64_t calculateDelay(PCIE_GEN, uint8_t, uint64_t); + +} // namespace PCIExpress + +namespace SATA { + +typedef enum { + SATA_1_0, // SATA 1.0 (1.5Gbps) + SATA_2_0, // SATA 2.0 (3Gbps) + SATA_3_0, // SATA 3.0/3.1 (6Gbps) + SATA_NUM +} SATA_GEN; + +uint64_t calculateDelay(SATA_GEN, uint64_t); + +} // namespace SATA + +namespace MIPI { + +namespace M_PHY { + +typedef enum { + HS_G1, // High Speed Gear 1 + HS_G2, // High Speed Gear 2 + HS_G3, // High Speed Gear 3 + HS_G4, // High Speed Gear 4 + HS_NUM +} M_PHY_MODE; + +uint64_t calculateDelay(M_PHY_MODE, uint8_t, uint64_t); + +} // namespace M_PHY + +namespace UniPro { + +uint64_t calculateDelay(M_PHY::M_PHY_MODE, uint8_t, uint64_t); + +} // namespace UniPro + +} // namespace MIPI + +namespace ARM { + +namespace AXI { + +typedef enum { + BUS_32BIT = 4, + BUS_64BIT = 8, + BUS_128BIT = 16, + BUS_256BIT = 32, + BUS_512BIT = 64, + BUS_1024BIT = 128, +} BUS_WIDTH; + +uint64_t calculateDelay(uint64_t, BUS_WIDTH, uint64_t); + +namespace Stream { + +uint64_t calculateDelay(uint64_t, BUS_WIDTH, uint64_t); + +} // namespace Stream + +} // namespace AXI + +} // namespace ARM + +} // namespace SimpleSSD + +#endif diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/old/SimpleSSD_types.h b/hotness/SimpleSSD-Standalone/simplessd/util/old/SimpleSSD_types.h new file mode 100644 index 0000000000..75872b3725 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/old/SimpleSSD_types.h @@ -0,0 +1,273 @@ +/** + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + * + * Authors: Jie Zhang + * Donghyun Gouk + */ + +#ifndef __ssdsim_types_h__ +#define __ssdsim_types_h__ + +#include + +/*============================== +Switches +==============================*/ + +// Option Switch +#define DMA_PREEMPTION 1 // For distingushing before-implementation. On/off is available at config file. +#define ENABLE_FTL 1 //FTL integration + + +// DBG Print Switch +#define DBG_PRINT 1 +#if DBG_PRINT +#define DBG_PRINT_PPN 0 +#define DBG_PRINT_TICK 0 +#define DBG_PRINT_CHANNEL 0 +#define DBG_PRINT_BUSY 0 +#define DBG_PRINT_REQSTART 1 +#define DBG_PRINT_REQDONE 1 +#define DBG_PRINT_CONFLICT 0 +#define DBG_PRINT_CONFIGPARSER 0 +#define DBG_PRINT_REQUEST 1 +#endif + +#define LOG_PRINT_ABSOLUTE_TIME 0 +#define LOG_PRINT_CONSUMED_TIME 0 + +#define LOG_PRINT_OCCUPY_EACH 0 + +#define GATHER_TIME_SERIES 0 +#define GATHER_RESOURCE_CONFLICT 1 +#define FULL_VERIFY_TIMELINE 0 // don't flush timeline for verification at the end +#define HARD_VERIFY_TIMELINE 0 // Verify PAL Timeline on every update! ... CAUCTION: takes VERY LONG time + + +/*============================== +Strings +==============================*/ +extern char ADDR_STRINFO[][10]; +extern char ADDR_STRINFO2[][15]; +extern char OPER_STRINFO[][10]; +extern char OPER_STRINFO2[][10]; +extern char BUSY_STRINFO[][10]; +extern char PAGE_STRINFO[][10]; +extern char NAND_STRINFO[][10]; +#if GATHER_RESOURCE_CONFLICT +extern char CONFLICT_STRINFO[][10]; +#endif + +typedef uint64_t Tick; +typedef uint64_t Addr; + +/*============================== +Macros +==============================*/ +//#define GET_ACCESSOR(propName, propType) propType get##propName() const { return m_##propName; } +//#define SET_ACCESSOR(propName, propType) void set##propName(const propType &newVal) { m_##propName = newVal; } + +#define CREATE_ACCESSOR(propType, propName) \ +private: \ +propType propName; \ +public: \ +void set##propName(const propType newVal) { propName = newVal; }; \ +propType get##propName() const { return propName; }; + +#ifdef _MSC_VER +#define printa(fmt, ...) do { printf(fmt, __VA_ARGS__); if (outfp) fprintf(outfp, fmt, __VA_ARGS__); } while(0); +#define printo(fmt, ...) do { if (!outfp) printf(fmt, __VA_ARGS__); if(outfp) fprintf(outfp, fmt, __VA_ARGS__); } while(0); +#define printft(fmt, ...) do { printf(" "); printf(fmt, __VA_ARGS__); } while(0); +#else +#define printa(fmt...) do { printf(fmt); if (outfp) fprintf(outfp, fmt); } while(0); +#define printo(fmt...) do { if (!outfp) printf(fmt); if(outfp) fprintf(outfp, fmt); } while(0); +#define printft(fmt...) do { printf(" "); printf(fmt); } while(0); +#endif + +//#define ERR_EXIT(fmt...) {printf(fmt); std::terminate();} +#define SAFEDIV(left,right) ((right)==0?0:(left)/(right)) + + +/*============================== +Type & Struct +==============================*/ +#define MAX64 0xFFFFFFFFFFFFFFFF +#define MAX32 0xFFFFFFFF + +#define BYTE (1) +#define KBYTE (1024) +#define MBYTE (1024*KBYTE) +#define GBYTE (1024*MBYTE) +#define TBYTE (1024*GBYTE) + +#define SEC (1) +#define MSEC (1000) // 1 000 +#define USEC (1000*MSEC) // 1 000 000 +#define NSEC ((uint64_t)1000*USEC) // 1 000 000 000 +#define PSEC ((uint64_t)1000*NSEC) // 1 000 000 000 000 + +//===== Address Sequence ===== +enum { + ADDR_CHANNEL = 0, + ADDR_PACKAGE = 1, + ADDR_DIE = 2, + ADDR_PLANE = 3, + ADDR_BLOCK = 4, + ADDR_PAGE = 5, + ADDR_NUM +}; + +enum { + FTL_PAGE_MAPPING, + FTL_BLOCK_MAPPING, + FTL_HYBRID_MAPPING +}; + +enum { + CACHE_EVICT_SUPER_PAGE, + CACHE_EVICT_SUPER_BLOCK +}; + +//===== Operation Types ===== +typedef enum _PAL_OPERATION { + OPER_READ = 0, + OPER_WRITE = 1, + OPER_ERASE = 2, + OPER_NUM +} PAL_OPERATION; + +//===== Busy Types ===== +enum { + BUSY_DMA0WAIT, + BUSY_DMA0, + BUSY_MEM, + BUSY_DMA1WAIT, + BUSY_DMA1, + BUSY_END, + BUSY_NUM +}; + + +//===== Log-purpose: Tick types ===== +enum { + TICK_DMA0WAIT = 0, // == TICK_IOREQUESTED + TICK_DMA0, + TICK_MEM, + TICK_DMA1WAIT, + TICK_DMA1, + TICK_IOEND, + TICK_NUM +}; + +//===== NAND Flash - Page address kind ===== +enum { + PAGE_LSB = 0, + PAGE_CSB = 1, + PAGE_MSB = 2, + PAGE_NUM +}; + +//===== NAND Flash type ===== +enum { + NAND_SLC, + NAND_MLC, + NAND_TLC, + NAND_NUM +}; + +//===== Request2 Status type ===== +enum +{ + REQSTAT_NEW, + REQSTAT_PROC, + REQSTAT_END +}; + + +#if GATHER_RESOURCE_CONFLICT +enum +{ + CONFLICT_NONE = 0, + CONFLICT_DMA0 = 1<<0, //DMA0 couldn't start due to CH BUSY --- exclusive to CONFLICT_MEM + CONFLICT_MEM = 1<<1, //DMA0 couldn't start due to MEM BUSY --- exclusive to CONFLICT_DMA0 + CONFLICT_DMA1 = 1<<2, //DMA1 couldn't start due to CH BUSY + CONFLICT_NUM = 4 //0~3 = 4 +}; +#endif + +/* +Todo: Make those structs to class?, to check address limitation & warn. +*/ + +//===== Divided Address ===== +typedef struct _CPDPBP +{ + uint32_t Channel; + uint32_t Package; + uint32_t Die; + uint32_t Plane; + uint32_t Block; + uint32_t Page; +}CPDPBP; + +//===== PPN Request Info (would be in the queue) ===== +class RequestFTL +{ +public: + uint64_t PPN; + uint8_t Oper; + uint64_t TickRequested; +}; + +//===== Task which can be assign to Channel or Memory ===== +class Task +{ +public: + uint64_t PPN; + CPDPBP CPD; + uint32_t PlaneIdx; + uint8_t Oper; + uint8_t Busy; + #if DMA_PREEMPTION + uint64_t DMASuspend; // 0 = no suspend, true = suspended & left time + #endif + uint64_t TickStart[TICK_NUM]; // End Time of each BUSY status, [BUSY_NUM] = END_TIME, actually not needed for simulation itself. + uint64_t TickNext; +}; + +//===== PPN Request Info (would be in the queue) ===== +class RequestLL +{ +public: + uint64_t PPN; + uint8_t Oper; + uint64_t TickRequested; + uint64_t TickFinished; + + CPDPBP CPD; + uint8_t status; // 0-New, 1-Fetched, 2-Finished + RequestLL* LLprev; //Dual-Linked-List + RequestLL* LLnext; //Dual-Linked-List +}; + +//===== Task which can be assign to Channel or Memory ===== +class TaskLL : Task +{ +public: + RequestLL* SrcRequest; //Dual-Linked-List +}; + +#endif //__ssdsim_types_h__ diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/simplessd.cc b/hotness/SimpleSSD-Standalone/simplessd/util/simplessd.cc new file mode 100644 index 0000000000..6dd6df6ef8 --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/simplessd.cc @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#include "util/simplessd.hh" + +#include "sim/log.hh" + +using namespace SimpleSSD; + +ConfigReader initSimpleSSDEngine(Simulator *sim, std::ostream *info, + std::ostream *err, std::string config) { + ConfigReader conf; + + setSimulator(sim); + initLogSystem(info, err); + + if (!conf.init(config)) { + panic("Failed to open configuration file %s", config.c_str()); + } + + initCPU(conf); + + return conf; +} + +void releaseSimpleSSDEngine() { + printCPULastStat(); + + deInitCPU(); +} diff --git a/hotness/SimpleSSD-Standalone/simplessd/util/simplessd.hh b/hotness/SimpleSSD-Standalone/simplessd/util/simplessd.hh new file mode 100644 index 0000000000..90bb27e26e --- /dev/null +++ b/hotness/SimpleSSD-Standalone/simplessd/util/simplessd.hh @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 CAMELab + * + * This file is part of SimpleSSD. + * + * SimpleSSD is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * SimpleSSD is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SimpleSSD. If not, see . + */ + +#pragma once + +#ifndef __UTIL_SIMPLESSD__ +#define __UTIL_SIMPLESSD__ + +#include "sim/config_reader.hh" +#include "sim/cpu.hh" +#include "sim/simulator.hh" +#include "sim/statistics.hh" +#include "sim/trace.hh" + +SimpleSSD::ConfigReader initSimpleSSDEngine(SimpleSSD::Simulator *, + std::ostream *, std::ostream *, + std::string); +void releaseSimpleSSDEngine(); + +#endif diff --git a/hotness/SimpleSSD-Standalone/third_party/.DS_Store b/hotness/SimpleSSD-Standalone/third_party/.DS_Store new file mode 100644 index 0000000000..4cb0544c10 Binary files /dev/null and b/hotness/SimpleSSD-Standalone/third_party/.DS_Store differ diff --git a/hotness/SimpleSSD-Standalone/third_party/json/json.hpp b/hotness/SimpleSSD-Standalone/third_party/json/json.hpp new file mode 100644 index 0000000000..82d69f7c5d --- /dev/null +++ b/hotness/SimpleSSD-Standalone/third_party/json/json.hpp @@ -0,0 +1,25526 @@ +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + +/****************************************************************************\ + * Note on documentation: The source files contain links to the online * + * documentation of the public API at https://json.nlohmann.me. This URL * + * contains the most recent documentation and should also be applicable to * + * previous versions; documentation for deprecated functions is not * + * removed, but marked deprecated. See "Generate documentation" section in * + * file docs/README.md. * +\****************************************************************************/ + +#ifndef INCLUDE_NLOHMANN_JSON_HPP_ +#define INCLUDE_NLOHMANN_JSON_HPP_ + +#include // all_of, find, for_each +#include // nullptr_t, ptrdiff_t, size_t +#include // hash, less +#include // initializer_list +#ifndef JSON_NO_IO + #include // istream, ostream +#endif // JSON_NO_IO +#include // random_access_iterator_tag +#include // unique_ptr +#include // string, stoi, to_string +#include // declval, forward, move, pair, swap +#include // vector + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// This file contains all macro definitions affecting or depending on the ABI + +#ifndef JSON_SKIP_LIBRARY_VERSION_CHECK + #if defined(NLOHMANN_JSON_VERSION_MAJOR) && defined(NLOHMANN_JSON_VERSION_MINOR) && defined(NLOHMANN_JSON_VERSION_PATCH) + #if NLOHMANN_JSON_VERSION_MAJOR != 3 || NLOHMANN_JSON_VERSION_MINOR != 12 || NLOHMANN_JSON_VERSION_PATCH != 0 + #warning "Already included a different version of the library!" + #endif + #endif +#endif + +#define NLOHMANN_JSON_VERSION_MAJOR 3 // NOLINT(modernize-macro-to-enum) +#define NLOHMANN_JSON_VERSION_MINOR 12 // NOLINT(modernize-macro-to-enum) +#define NLOHMANN_JSON_VERSION_PATCH 0 // NOLINT(modernize-macro-to-enum) + +#ifndef JSON_DIAGNOSTICS + #define JSON_DIAGNOSTICS 0 +#endif + +#ifndef JSON_DIAGNOSTIC_POSITIONS + #define JSON_DIAGNOSTIC_POSITIONS 0 +#endif + +#ifndef JSON_USE_LEGACY_DISCARDED_VALUE_COMPARISON + #define JSON_USE_LEGACY_DISCARDED_VALUE_COMPARISON 0 +#endif + +#if JSON_DIAGNOSTICS + #define NLOHMANN_JSON_ABI_TAG_DIAGNOSTICS _diag +#else + #define NLOHMANN_JSON_ABI_TAG_DIAGNOSTICS +#endif + +#if JSON_DIAGNOSTIC_POSITIONS + #define NLOHMANN_JSON_ABI_TAG_DIAGNOSTIC_POSITIONS _dp +#else + #define NLOHMANN_JSON_ABI_TAG_DIAGNOSTIC_POSITIONS +#endif + +#if JSON_USE_LEGACY_DISCARDED_VALUE_COMPARISON + #define NLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON _ldvcmp +#else + #define NLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON +#endif + +#ifndef NLOHMANN_JSON_NAMESPACE_NO_VERSION + #define NLOHMANN_JSON_NAMESPACE_NO_VERSION 0 +#endif + +// Construct the namespace ABI tags component +#define NLOHMANN_JSON_ABI_TAGS_CONCAT_EX(a, b, c) json_abi ## a ## b ## c +#define NLOHMANN_JSON_ABI_TAGS_CONCAT(a, b, c) \ + NLOHMANN_JSON_ABI_TAGS_CONCAT_EX(a, b, c) + +#define NLOHMANN_JSON_ABI_TAGS \ + NLOHMANN_JSON_ABI_TAGS_CONCAT( \ + NLOHMANN_JSON_ABI_TAG_DIAGNOSTICS, \ + NLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON, \ + NLOHMANN_JSON_ABI_TAG_DIAGNOSTIC_POSITIONS) + +// Construct the namespace version component +#define NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT_EX(major, minor, patch) \ + _v ## major ## _ ## minor ## _ ## patch +#define NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT(major, minor, patch) \ + NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT_EX(major, minor, patch) + +#if NLOHMANN_JSON_NAMESPACE_NO_VERSION +#define NLOHMANN_JSON_NAMESPACE_VERSION +#else +#define NLOHMANN_JSON_NAMESPACE_VERSION \ + NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT(NLOHMANN_JSON_VERSION_MAJOR, \ + NLOHMANN_JSON_VERSION_MINOR, \ + NLOHMANN_JSON_VERSION_PATCH) +#endif + +// Combine namespace components +#define NLOHMANN_JSON_NAMESPACE_CONCAT_EX(a, b) a ## b +#define NLOHMANN_JSON_NAMESPACE_CONCAT(a, b) \ + NLOHMANN_JSON_NAMESPACE_CONCAT_EX(a, b) + +#ifndef NLOHMANN_JSON_NAMESPACE +#define NLOHMANN_JSON_NAMESPACE \ + nlohmann::NLOHMANN_JSON_NAMESPACE_CONCAT( \ + NLOHMANN_JSON_ABI_TAGS, \ + NLOHMANN_JSON_NAMESPACE_VERSION) +#endif + +#ifndef NLOHMANN_JSON_NAMESPACE_BEGIN +#define NLOHMANN_JSON_NAMESPACE_BEGIN \ + namespace nlohmann \ + { \ + inline namespace NLOHMANN_JSON_NAMESPACE_CONCAT( \ + NLOHMANN_JSON_ABI_TAGS, \ + NLOHMANN_JSON_NAMESPACE_VERSION) \ + { +#endif + +#ifndef NLOHMANN_JSON_NAMESPACE_END +#define NLOHMANN_JSON_NAMESPACE_END \ + } /* namespace (inline namespace) NOLINT(readability/namespace) */ \ + } // namespace nlohmann +#endif + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // transform +#include // array +#include // forward_list +#include // inserter, front_inserter, end +#include // map +#ifdef JSON_HAS_CPP_17 + #include // optional +#endif +#include // string +#include // tuple, make_tuple +#include // is_arithmetic, is_same, is_enum, underlying_type, is_convertible +#include // unordered_map +#include // pair, declval +#include // valarray + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // nullptr_t +#include // exception +#if JSON_DIAGNOSTICS + #include // accumulate +#endif +#include // runtime_error +#include // to_string +#include // vector + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // array +#include // size_t +#include // uint8_t +#include // string + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // declval, pair +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +template struct make_void +{ + using type = void; +}; +template using void_t = typename make_void::type; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +// https://en.cppreference.com/w/cpp/experimental/is_detected +struct nonesuch +{ + nonesuch() = delete; + ~nonesuch() = delete; + nonesuch(nonesuch const&) = delete; + nonesuch(nonesuch const&&) = delete; + void operator=(nonesuch const&) = delete; + void operator=(nonesuch&&) = delete; +}; + +template class Op, + class... Args> +struct detector +{ + using value_t = std::false_type; + using type = Default; +}; + +template class Op, class... Args> +struct detector>, Op, Args...> +{ + using value_t = std::true_type; + using type = Op; +}; + +template class Op, class... Args> +using is_detected = typename detector::value_t; + +template class Op, class... Args> +struct is_detected_lazy : is_detected { }; + +template class Op, class... Args> +using detected_t = typename detector::type; + +template class Op, class... Args> +using detected_or = detector; + +template class Op, class... Args> +using detected_or_t = typename detected_or::type; + +template class Op, class... Args> +using is_detected_exact = std::is_same>; + +template class Op, class... Args> +using is_detected_convertible = + std::is_convertible, To>; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include + + +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-FileCopyrightText: 2016 - 2021 Evan Nemerson +// SPDX-License-Identifier: MIT + +/* Hedley - https://nemequ.github.io/hedley + * Created by Evan Nemerson + */ + +#if !defined(JSON_HEDLEY_VERSION) || (JSON_HEDLEY_VERSION < 15) +#if defined(JSON_HEDLEY_VERSION) + #undef JSON_HEDLEY_VERSION +#endif +#define JSON_HEDLEY_VERSION 15 + +#if defined(JSON_HEDLEY_STRINGIFY_EX) + #undef JSON_HEDLEY_STRINGIFY_EX +#endif +#define JSON_HEDLEY_STRINGIFY_EX(x) #x + +#if defined(JSON_HEDLEY_STRINGIFY) + #undef JSON_HEDLEY_STRINGIFY +#endif +#define JSON_HEDLEY_STRINGIFY(x) JSON_HEDLEY_STRINGIFY_EX(x) + +#if defined(JSON_HEDLEY_CONCAT_EX) + #undef JSON_HEDLEY_CONCAT_EX +#endif +#define JSON_HEDLEY_CONCAT_EX(a,b) a##b + +#if defined(JSON_HEDLEY_CONCAT) + #undef JSON_HEDLEY_CONCAT +#endif +#define JSON_HEDLEY_CONCAT(a,b) JSON_HEDLEY_CONCAT_EX(a,b) + +#if defined(JSON_HEDLEY_CONCAT3_EX) + #undef JSON_HEDLEY_CONCAT3_EX +#endif +#define JSON_HEDLEY_CONCAT3_EX(a,b,c) a##b##c + +#if defined(JSON_HEDLEY_CONCAT3) + #undef JSON_HEDLEY_CONCAT3 +#endif +#define JSON_HEDLEY_CONCAT3(a,b,c) JSON_HEDLEY_CONCAT3_EX(a,b,c) + +#if defined(JSON_HEDLEY_VERSION_ENCODE) + #undef JSON_HEDLEY_VERSION_ENCODE +#endif +#define JSON_HEDLEY_VERSION_ENCODE(major,minor,revision) (((major) * 1000000) + ((minor) * 1000) + (revision)) + +#if defined(JSON_HEDLEY_VERSION_DECODE_MAJOR) + #undef JSON_HEDLEY_VERSION_DECODE_MAJOR +#endif +#define JSON_HEDLEY_VERSION_DECODE_MAJOR(version) ((version) / 1000000) + +#if defined(JSON_HEDLEY_VERSION_DECODE_MINOR) + #undef JSON_HEDLEY_VERSION_DECODE_MINOR +#endif +#define JSON_HEDLEY_VERSION_DECODE_MINOR(version) (((version) % 1000000) / 1000) + +#if defined(JSON_HEDLEY_VERSION_DECODE_REVISION) + #undef JSON_HEDLEY_VERSION_DECODE_REVISION +#endif +#define JSON_HEDLEY_VERSION_DECODE_REVISION(version) ((version) % 1000) + +#if defined(JSON_HEDLEY_GNUC_VERSION) + #undef JSON_HEDLEY_GNUC_VERSION +#endif +#if defined(__GNUC__) && defined(__GNUC_PATCHLEVEL__) + #define JSON_HEDLEY_GNUC_VERSION JSON_HEDLEY_VERSION_ENCODE(__GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__) +#elif defined(__GNUC__) + #define JSON_HEDLEY_GNUC_VERSION JSON_HEDLEY_VERSION_ENCODE(__GNUC__, __GNUC_MINOR__, 0) +#endif + +#if defined(JSON_HEDLEY_GNUC_VERSION_CHECK) + #undef JSON_HEDLEY_GNUC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_GNUC_VERSION) + #define JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_GNUC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_MSVC_VERSION) + #undef JSON_HEDLEY_MSVC_VERSION +#endif +#if defined(_MSC_FULL_VER) && (_MSC_FULL_VER >= 140000000) && !defined(__ICL) + #define JSON_HEDLEY_MSVC_VERSION JSON_HEDLEY_VERSION_ENCODE(_MSC_FULL_VER / 10000000, (_MSC_FULL_VER % 10000000) / 100000, (_MSC_FULL_VER % 100000) / 100) +#elif defined(_MSC_FULL_VER) && !defined(__ICL) + #define JSON_HEDLEY_MSVC_VERSION JSON_HEDLEY_VERSION_ENCODE(_MSC_FULL_VER / 1000000, (_MSC_FULL_VER % 1000000) / 10000, (_MSC_FULL_VER % 10000) / 10) +#elif defined(_MSC_VER) && !defined(__ICL) + #define JSON_HEDLEY_MSVC_VERSION JSON_HEDLEY_VERSION_ENCODE(_MSC_VER / 100, _MSC_VER % 100, 0) +#endif + +#if defined(JSON_HEDLEY_MSVC_VERSION_CHECK) + #undef JSON_HEDLEY_MSVC_VERSION_CHECK +#endif +#if !defined(JSON_HEDLEY_MSVC_VERSION) + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (0) +#elif defined(_MSC_VER) && (_MSC_VER >= 1400) + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_FULL_VER >= ((major * 10000000) + (minor * 100000) + (patch))) +#elif defined(_MSC_VER) && (_MSC_VER >= 1200) + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_FULL_VER >= ((major * 1000000) + (minor * 10000) + (patch))) +#else + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_VER >= ((major * 100) + (minor))) +#endif + +#if defined(JSON_HEDLEY_INTEL_VERSION) + #undef JSON_HEDLEY_INTEL_VERSION +#endif +#if defined(__INTEL_COMPILER) && defined(__INTEL_COMPILER_UPDATE) && !defined(__ICL) + #define JSON_HEDLEY_INTEL_VERSION JSON_HEDLEY_VERSION_ENCODE(__INTEL_COMPILER / 100, __INTEL_COMPILER % 100, __INTEL_COMPILER_UPDATE) +#elif defined(__INTEL_COMPILER) && !defined(__ICL) + #define JSON_HEDLEY_INTEL_VERSION JSON_HEDLEY_VERSION_ENCODE(__INTEL_COMPILER / 100, __INTEL_COMPILER % 100, 0) +#endif + +#if defined(JSON_HEDLEY_INTEL_VERSION_CHECK) + #undef JSON_HEDLEY_INTEL_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_INTEL_VERSION) + #define JSON_HEDLEY_INTEL_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_INTEL_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_INTEL_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_INTEL_CL_VERSION) + #undef JSON_HEDLEY_INTEL_CL_VERSION +#endif +#if defined(__INTEL_COMPILER) && defined(__INTEL_COMPILER_UPDATE) && defined(__ICL) + #define JSON_HEDLEY_INTEL_CL_VERSION JSON_HEDLEY_VERSION_ENCODE(__INTEL_COMPILER, __INTEL_COMPILER_UPDATE, 0) +#endif + +#if defined(JSON_HEDLEY_INTEL_CL_VERSION_CHECK) + #undef JSON_HEDLEY_INTEL_CL_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_INTEL_CL_VERSION) + #define JSON_HEDLEY_INTEL_CL_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_INTEL_CL_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_INTEL_CL_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_PGI_VERSION) + #undef JSON_HEDLEY_PGI_VERSION +#endif +#if defined(__PGI) && defined(__PGIC__) && defined(__PGIC_MINOR__) && defined(__PGIC_PATCHLEVEL__) + #define JSON_HEDLEY_PGI_VERSION JSON_HEDLEY_VERSION_ENCODE(__PGIC__, __PGIC_MINOR__, __PGIC_PATCHLEVEL__) +#endif + +#if defined(JSON_HEDLEY_PGI_VERSION_CHECK) + #undef JSON_HEDLEY_PGI_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_PGI_VERSION) + #define JSON_HEDLEY_PGI_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_PGI_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_PGI_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_SUNPRO_VERSION) + #undef JSON_HEDLEY_SUNPRO_VERSION +#endif +#if defined(__SUNPRO_C) && (__SUNPRO_C > 0x1000) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((((__SUNPRO_C >> 16) & 0xf) * 10) + ((__SUNPRO_C >> 12) & 0xf), (((__SUNPRO_C >> 8) & 0xf) * 10) + ((__SUNPRO_C >> 4) & 0xf), (__SUNPRO_C & 0xf) * 10) +#elif defined(__SUNPRO_C) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((__SUNPRO_C >> 8) & 0xf, (__SUNPRO_C >> 4) & 0xf, (__SUNPRO_C) & 0xf) +#elif defined(__SUNPRO_CC) && (__SUNPRO_CC > 0x1000) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((((__SUNPRO_CC >> 16) & 0xf) * 10) + ((__SUNPRO_CC >> 12) & 0xf), (((__SUNPRO_CC >> 8) & 0xf) * 10) + ((__SUNPRO_CC >> 4) & 0xf), (__SUNPRO_CC & 0xf) * 10) +#elif defined(__SUNPRO_CC) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((__SUNPRO_CC >> 8) & 0xf, (__SUNPRO_CC >> 4) & 0xf, (__SUNPRO_CC) & 0xf) +#endif + +#if defined(JSON_HEDLEY_SUNPRO_VERSION_CHECK) + #undef JSON_HEDLEY_SUNPRO_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_SUNPRO_VERSION) + #define JSON_HEDLEY_SUNPRO_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_SUNPRO_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_SUNPRO_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_EMSCRIPTEN_VERSION) + #undef JSON_HEDLEY_EMSCRIPTEN_VERSION +#endif +#if defined(__EMSCRIPTEN__) + #define JSON_HEDLEY_EMSCRIPTEN_VERSION JSON_HEDLEY_VERSION_ENCODE(__EMSCRIPTEN_major__, __EMSCRIPTEN_minor__, __EMSCRIPTEN_tiny__) +#endif + +#if defined(JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK) + #undef JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_EMSCRIPTEN_VERSION) + #define JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_EMSCRIPTEN_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_ARM_VERSION) + #undef JSON_HEDLEY_ARM_VERSION +#endif +#if defined(__CC_ARM) && defined(__ARMCOMPILER_VERSION) + #define JSON_HEDLEY_ARM_VERSION JSON_HEDLEY_VERSION_ENCODE(__ARMCOMPILER_VERSION / 1000000, (__ARMCOMPILER_VERSION % 1000000) / 10000, (__ARMCOMPILER_VERSION % 10000) / 100) +#elif defined(__CC_ARM) && defined(__ARMCC_VERSION) + #define JSON_HEDLEY_ARM_VERSION JSON_HEDLEY_VERSION_ENCODE(__ARMCC_VERSION / 1000000, (__ARMCC_VERSION % 1000000) / 10000, (__ARMCC_VERSION % 10000) / 100) +#endif + +#if defined(JSON_HEDLEY_ARM_VERSION_CHECK) + #undef JSON_HEDLEY_ARM_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_ARM_VERSION) + #define JSON_HEDLEY_ARM_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_ARM_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_ARM_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_IBM_VERSION) + #undef JSON_HEDLEY_IBM_VERSION +#endif +#if defined(__ibmxl__) + #define JSON_HEDLEY_IBM_VERSION JSON_HEDLEY_VERSION_ENCODE(__ibmxl_version__, __ibmxl_release__, __ibmxl_modification__) +#elif defined(__xlC__) && defined(__xlC_ver__) + #define JSON_HEDLEY_IBM_VERSION JSON_HEDLEY_VERSION_ENCODE(__xlC__ >> 8, __xlC__ & 0xff, (__xlC_ver__ >> 8) & 0xff) +#elif defined(__xlC__) + #define JSON_HEDLEY_IBM_VERSION JSON_HEDLEY_VERSION_ENCODE(__xlC__ >> 8, __xlC__ & 0xff, 0) +#endif + +#if defined(JSON_HEDLEY_IBM_VERSION_CHECK) + #undef JSON_HEDLEY_IBM_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_IBM_VERSION) + #define JSON_HEDLEY_IBM_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_IBM_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_IBM_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_VERSION) + #undef JSON_HEDLEY_TI_VERSION +#endif +#if \ + defined(__TI_COMPILER_VERSION__) && \ + ( \ + defined(__TMS470__) || defined(__TI_ARM__) || \ + defined(__MSP430__) || \ + defined(__TMS320C2000__) \ + ) +#if (__TI_COMPILER_VERSION__ >= 16000000) + #define JSON_HEDLEY_TI_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif +#endif + +#if defined(JSON_HEDLEY_TI_VERSION_CHECK) + #undef JSON_HEDLEY_TI_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_VERSION) + #define JSON_HEDLEY_TI_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL2000_VERSION) + #undef JSON_HEDLEY_TI_CL2000_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__TMS320C2000__) + #define JSON_HEDLEY_TI_CL2000_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL2000_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL2000_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL2000_VERSION) + #define JSON_HEDLEY_TI_CL2000_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL2000_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL2000_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL430_VERSION) + #undef JSON_HEDLEY_TI_CL430_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__MSP430__) + #define JSON_HEDLEY_TI_CL430_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL430_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL430_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL430_VERSION) + #define JSON_HEDLEY_TI_CL430_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL430_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL430_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_ARMCL_VERSION) + #undef JSON_HEDLEY_TI_ARMCL_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && (defined(__TMS470__) || defined(__TI_ARM__)) + #define JSON_HEDLEY_TI_ARMCL_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_ARMCL_VERSION_CHECK) + #undef JSON_HEDLEY_TI_ARMCL_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_ARMCL_VERSION) + #define JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_ARMCL_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL6X_VERSION) + #undef JSON_HEDLEY_TI_CL6X_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__TMS320C6X__) + #define JSON_HEDLEY_TI_CL6X_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL6X_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL6X_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL6X_VERSION) + #define JSON_HEDLEY_TI_CL6X_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL6X_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL6X_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL7X_VERSION) + #undef JSON_HEDLEY_TI_CL7X_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__C7000__) + #define JSON_HEDLEY_TI_CL7X_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL7X_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL7X_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL7X_VERSION) + #define JSON_HEDLEY_TI_CL7X_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL7X_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL7X_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CLPRU_VERSION) + #undef JSON_HEDLEY_TI_CLPRU_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__PRU__) + #define JSON_HEDLEY_TI_CLPRU_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CLPRU_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CLPRU_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CLPRU_VERSION) + #define JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CLPRU_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_CRAY_VERSION) + #undef JSON_HEDLEY_CRAY_VERSION +#endif +#if defined(_CRAYC) + #if defined(_RELEASE_PATCHLEVEL) + #define JSON_HEDLEY_CRAY_VERSION JSON_HEDLEY_VERSION_ENCODE(_RELEASE_MAJOR, _RELEASE_MINOR, _RELEASE_PATCHLEVEL) + #else + #define JSON_HEDLEY_CRAY_VERSION JSON_HEDLEY_VERSION_ENCODE(_RELEASE_MAJOR, _RELEASE_MINOR, 0) + #endif +#endif + +#if defined(JSON_HEDLEY_CRAY_VERSION_CHECK) + #undef JSON_HEDLEY_CRAY_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_CRAY_VERSION) + #define JSON_HEDLEY_CRAY_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_CRAY_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_CRAY_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_IAR_VERSION) + #undef JSON_HEDLEY_IAR_VERSION +#endif +#if defined(__IAR_SYSTEMS_ICC__) + #if __VER__ > 1000 + #define JSON_HEDLEY_IAR_VERSION JSON_HEDLEY_VERSION_ENCODE((__VER__ / 1000000), ((__VER__ / 1000) % 1000), (__VER__ % 1000)) + #else + #define JSON_HEDLEY_IAR_VERSION JSON_HEDLEY_VERSION_ENCODE(__VER__ / 100, __VER__ % 100, 0) + #endif +#endif + +#if defined(JSON_HEDLEY_IAR_VERSION_CHECK) + #undef JSON_HEDLEY_IAR_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_IAR_VERSION) + #define JSON_HEDLEY_IAR_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_IAR_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_IAR_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TINYC_VERSION) + #undef JSON_HEDLEY_TINYC_VERSION +#endif +#if defined(__TINYC__) + #define JSON_HEDLEY_TINYC_VERSION JSON_HEDLEY_VERSION_ENCODE(__TINYC__ / 1000, (__TINYC__ / 100) % 10, __TINYC__ % 100) +#endif + +#if defined(JSON_HEDLEY_TINYC_VERSION_CHECK) + #undef JSON_HEDLEY_TINYC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TINYC_VERSION) + #define JSON_HEDLEY_TINYC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TINYC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TINYC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_DMC_VERSION) + #undef JSON_HEDLEY_DMC_VERSION +#endif +#if defined(__DMC__) + #define JSON_HEDLEY_DMC_VERSION JSON_HEDLEY_VERSION_ENCODE(__DMC__ >> 8, (__DMC__ >> 4) & 0xf, __DMC__ & 0xf) +#endif + +#if defined(JSON_HEDLEY_DMC_VERSION_CHECK) + #undef JSON_HEDLEY_DMC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_DMC_VERSION) + #define JSON_HEDLEY_DMC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_DMC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_DMC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_COMPCERT_VERSION) + #undef JSON_HEDLEY_COMPCERT_VERSION +#endif +#if defined(__COMPCERT_VERSION__) + #define JSON_HEDLEY_COMPCERT_VERSION JSON_HEDLEY_VERSION_ENCODE(__COMPCERT_VERSION__ / 10000, (__COMPCERT_VERSION__ / 100) % 100, __COMPCERT_VERSION__ % 100) +#endif + +#if defined(JSON_HEDLEY_COMPCERT_VERSION_CHECK) + #undef JSON_HEDLEY_COMPCERT_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_COMPCERT_VERSION) + #define JSON_HEDLEY_COMPCERT_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_COMPCERT_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_COMPCERT_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_PELLES_VERSION) + #undef JSON_HEDLEY_PELLES_VERSION +#endif +#if defined(__POCC__) + #define JSON_HEDLEY_PELLES_VERSION JSON_HEDLEY_VERSION_ENCODE(__POCC__ / 100, __POCC__ % 100, 0) +#endif + +#if defined(JSON_HEDLEY_PELLES_VERSION_CHECK) + #undef JSON_HEDLEY_PELLES_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_PELLES_VERSION) + #define JSON_HEDLEY_PELLES_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_PELLES_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_PELLES_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_MCST_LCC_VERSION) + #undef JSON_HEDLEY_MCST_LCC_VERSION +#endif +#if defined(__LCC__) && defined(__LCC_MINOR__) + #define JSON_HEDLEY_MCST_LCC_VERSION JSON_HEDLEY_VERSION_ENCODE(__LCC__ / 100, __LCC__ % 100, __LCC_MINOR__) +#endif + +#if defined(JSON_HEDLEY_MCST_LCC_VERSION_CHECK) + #undef JSON_HEDLEY_MCST_LCC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_MCST_LCC_VERSION) + #define JSON_HEDLEY_MCST_LCC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_MCST_LCC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_MCST_LCC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_GCC_VERSION) + #undef JSON_HEDLEY_GCC_VERSION +#endif +#if \ + defined(JSON_HEDLEY_GNUC_VERSION) && \ + !defined(__clang__) && \ + !defined(JSON_HEDLEY_INTEL_VERSION) && \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_ARM_VERSION) && \ + !defined(JSON_HEDLEY_CRAY_VERSION) && \ + !defined(JSON_HEDLEY_TI_VERSION) && \ + !defined(JSON_HEDLEY_TI_ARMCL_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL430_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL2000_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL6X_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL7X_VERSION) && \ + !defined(JSON_HEDLEY_TI_CLPRU_VERSION) && \ + !defined(__COMPCERT__) && \ + !defined(JSON_HEDLEY_MCST_LCC_VERSION) + #define JSON_HEDLEY_GCC_VERSION JSON_HEDLEY_GNUC_VERSION +#endif + +#if defined(JSON_HEDLEY_GCC_VERSION_CHECK) + #undef JSON_HEDLEY_GCC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_GCC_VERSION) + #define JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_GCC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_HAS_ATTRIBUTE +#endif +#if \ + defined(__has_attribute) && \ + ( \ + (!defined(JSON_HEDLEY_IAR_VERSION) || JSON_HEDLEY_IAR_VERSION_CHECK(8,5,9)) \ + ) +# define JSON_HEDLEY_HAS_ATTRIBUTE(attribute) __has_attribute(attribute) +#else +# define JSON_HEDLEY_HAS_ATTRIBUTE(attribute) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_GNUC_HAS_ATTRIBUTE +#endif +#if defined(__has_attribute) + #define JSON_HEDLEY_GNUC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_HAS_ATTRIBUTE(attribute) +#else + #define JSON_HEDLEY_GNUC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_GCC_HAS_ATTRIBUTE +#endif +#if defined(__has_attribute) + #define JSON_HEDLEY_GCC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_HAS_ATTRIBUTE(attribute) +#else + #define JSON_HEDLEY_GCC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_HAS_CPP_ATTRIBUTE +#endif +#if \ + defined(__has_cpp_attribute) && \ + defined(__cplusplus) && \ + (!defined(JSON_HEDLEY_SUNPRO_VERSION) || JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0)) + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE(attribute) __has_cpp_attribute(attribute) +#else + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE(attribute) (0) +#endif + +#if defined(JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS) + #undef JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS +#endif +#if !defined(__cplusplus) || !defined(__has_cpp_attribute) + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) (0) +#elif \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_IAR_VERSION) && \ + (!defined(JSON_HEDLEY_SUNPRO_VERSION) || JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0)) && \ + (!defined(JSON_HEDLEY_MSVC_VERSION) || JSON_HEDLEY_MSVC_VERSION_CHECK(19,20,0)) + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) JSON_HEDLEY_HAS_CPP_ATTRIBUTE(ns::attribute) +#else + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE +#endif +#if defined(__has_cpp_attribute) && defined(__cplusplus) + #define JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) __has_cpp_attribute(attribute) +#else + #define JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE +#endif +#if defined(__has_cpp_attribute) && defined(__cplusplus) + #define JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) __has_cpp_attribute(attribute) +#else + #define JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_BUILTIN) + #undef JSON_HEDLEY_HAS_BUILTIN +#endif +#if defined(__has_builtin) + #define JSON_HEDLEY_HAS_BUILTIN(builtin) __has_builtin(builtin) +#else + #define JSON_HEDLEY_HAS_BUILTIN(builtin) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_BUILTIN) + #undef JSON_HEDLEY_GNUC_HAS_BUILTIN +#endif +#if defined(__has_builtin) + #define JSON_HEDLEY_GNUC_HAS_BUILTIN(builtin,major,minor,patch) __has_builtin(builtin) +#else + #define JSON_HEDLEY_GNUC_HAS_BUILTIN(builtin,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_BUILTIN) + #undef JSON_HEDLEY_GCC_HAS_BUILTIN +#endif +#if defined(__has_builtin) + #define JSON_HEDLEY_GCC_HAS_BUILTIN(builtin,major,minor,patch) __has_builtin(builtin) +#else + #define JSON_HEDLEY_GCC_HAS_BUILTIN(builtin,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_FEATURE) + #undef JSON_HEDLEY_HAS_FEATURE +#endif +#if defined(__has_feature) + #define JSON_HEDLEY_HAS_FEATURE(feature) __has_feature(feature) +#else + #define JSON_HEDLEY_HAS_FEATURE(feature) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_FEATURE) + #undef JSON_HEDLEY_GNUC_HAS_FEATURE +#endif +#if defined(__has_feature) + #define JSON_HEDLEY_GNUC_HAS_FEATURE(feature,major,minor,patch) __has_feature(feature) +#else + #define JSON_HEDLEY_GNUC_HAS_FEATURE(feature,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_FEATURE) + #undef JSON_HEDLEY_GCC_HAS_FEATURE +#endif +#if defined(__has_feature) + #define JSON_HEDLEY_GCC_HAS_FEATURE(feature,major,minor,patch) __has_feature(feature) +#else + #define JSON_HEDLEY_GCC_HAS_FEATURE(feature,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_EXTENSION) + #undef JSON_HEDLEY_HAS_EXTENSION +#endif +#if defined(__has_extension) + #define JSON_HEDLEY_HAS_EXTENSION(extension) __has_extension(extension) +#else + #define JSON_HEDLEY_HAS_EXTENSION(extension) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_EXTENSION) + #undef JSON_HEDLEY_GNUC_HAS_EXTENSION +#endif +#if defined(__has_extension) + #define JSON_HEDLEY_GNUC_HAS_EXTENSION(extension,major,minor,patch) __has_extension(extension) +#else + #define JSON_HEDLEY_GNUC_HAS_EXTENSION(extension,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_EXTENSION) + #undef JSON_HEDLEY_GCC_HAS_EXTENSION +#endif +#if defined(__has_extension) + #define JSON_HEDLEY_GCC_HAS_EXTENSION(extension,major,minor,patch) __has_extension(extension) +#else + #define JSON_HEDLEY_GCC_HAS_EXTENSION(extension,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE +#endif +#if defined(__has_declspec_attribute) + #define JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) __has_declspec_attribute(attribute) +#else + #define JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE +#endif +#if defined(__has_declspec_attribute) + #define JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) __has_declspec_attribute(attribute) +#else + #define JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE +#endif +#if defined(__has_declspec_attribute) + #define JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) __has_declspec_attribute(attribute) +#else + #define JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_WARNING) + #undef JSON_HEDLEY_HAS_WARNING +#endif +#if defined(__has_warning) + #define JSON_HEDLEY_HAS_WARNING(warning) __has_warning(warning) +#else + #define JSON_HEDLEY_HAS_WARNING(warning) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_WARNING) + #undef JSON_HEDLEY_GNUC_HAS_WARNING +#endif +#if defined(__has_warning) + #define JSON_HEDLEY_GNUC_HAS_WARNING(warning,major,minor,patch) __has_warning(warning) +#else + #define JSON_HEDLEY_GNUC_HAS_WARNING(warning,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_WARNING) + #undef JSON_HEDLEY_GCC_HAS_WARNING +#endif +#if defined(__has_warning) + #define JSON_HEDLEY_GCC_HAS_WARNING(warning,major,minor,patch) __has_warning(warning) +#else + #define JSON_HEDLEY_GCC_HAS_WARNING(warning,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if \ + (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || \ + defined(__clang__) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(18,4,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,7,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(2,0,1) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(5,0,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,17) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(8,0,0) || \ + (JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) && defined(__C99_PRAGMA_OPERATOR)) + #define JSON_HEDLEY_PRAGMA(value) _Pragma(#value) +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) + #define JSON_HEDLEY_PRAGMA(value) __pragma(value) +#else + #define JSON_HEDLEY_PRAGMA(value) +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_PUSH) + #undef JSON_HEDLEY_DIAGNOSTIC_PUSH +#endif +#if defined(JSON_HEDLEY_DIAGNOSTIC_POP) + #undef JSON_HEDLEY_DIAGNOSTIC_POP +#endif +#if defined(__clang__) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("clang diagnostic push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("clang diagnostic pop") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("warning(push)") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("warning(pop)") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,6,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("GCC diagnostic push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("GCC diagnostic pop") +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH __pragma(warning(push)) + #define JSON_HEDLEY_DIAGNOSTIC_POP __pragma(warning(pop)) +#elif JSON_HEDLEY_ARM_VERSION_CHECK(5,6,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("pop") +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,4,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("diag_push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("diag_pop") +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(2,90,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("warning(push)") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("warning(pop)") +#else + #define JSON_HEDLEY_DIAGNOSTIC_PUSH + #define JSON_HEDLEY_DIAGNOSTIC_POP +#endif + +/* JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_ is for + HEDLEY INTERNAL USE ONLY. API subject to change without notice. */ +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_ +#endif +#if defined(__cplusplus) +# if JSON_HEDLEY_HAS_WARNING("-Wc++98-compat") +# if JSON_HEDLEY_HAS_WARNING("-Wc++17-extensions") +# if JSON_HEDLEY_HAS_WARNING("-Wc++1z-extensions") +# define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \ + _Pragma("clang diagnostic ignored \"-Wc++17-extensions\"") \ + _Pragma("clang diagnostic ignored \"-Wc++1z-extensions\"") \ + xpr \ + JSON_HEDLEY_DIAGNOSTIC_POP +# else +# define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \ + _Pragma("clang diagnostic ignored \"-Wc++17-extensions\"") \ + xpr \ + JSON_HEDLEY_DIAGNOSTIC_POP +# endif +# else +# define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \ + xpr \ + JSON_HEDLEY_DIAGNOSTIC_POP +# endif +# endif +#endif +#if !defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(x) x +#endif + +#if defined(JSON_HEDLEY_CONST_CAST) + #undef JSON_HEDLEY_CONST_CAST +#endif +#if defined(__cplusplus) +# define JSON_HEDLEY_CONST_CAST(T, expr) (const_cast(expr)) +#elif \ + JSON_HEDLEY_HAS_WARNING("-Wcast-qual") || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,6,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) +# define JSON_HEDLEY_CONST_CAST(T, expr) (__extension__ ({ \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL \ + ((T) (expr)); \ + JSON_HEDLEY_DIAGNOSTIC_POP \ + })) +#else +# define JSON_HEDLEY_CONST_CAST(T, expr) ((T) (expr)) +#endif + +#if defined(JSON_HEDLEY_REINTERPRET_CAST) + #undef JSON_HEDLEY_REINTERPRET_CAST +#endif +#if defined(__cplusplus) + #define JSON_HEDLEY_REINTERPRET_CAST(T, expr) (reinterpret_cast(expr)) +#else + #define JSON_HEDLEY_REINTERPRET_CAST(T, expr) ((T) (expr)) +#endif + +#if defined(JSON_HEDLEY_STATIC_CAST) + #undef JSON_HEDLEY_STATIC_CAST +#endif +#if defined(__cplusplus) + #define JSON_HEDLEY_STATIC_CAST(T, expr) (static_cast(expr)) +#else + #define JSON_HEDLEY_STATIC_CAST(T, expr) ((T) (expr)) +#endif + +#if defined(JSON_HEDLEY_CPP_CAST) + #undef JSON_HEDLEY_CPP_CAST +#endif +#if defined(__cplusplus) +# if JSON_HEDLEY_HAS_WARNING("-Wold-style-cast") +# define JSON_HEDLEY_CPP_CAST(T, expr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wold-style-cast\"") \ + ((T) (expr)) \ + JSON_HEDLEY_DIAGNOSTIC_POP +# elif JSON_HEDLEY_IAR_VERSION_CHECK(8,3,0) +# define JSON_HEDLEY_CPP_CAST(T, expr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("diag_suppress=Pe137") \ + JSON_HEDLEY_DIAGNOSTIC_POP +# else +# define JSON_HEDLEY_CPP_CAST(T, expr) ((T) (expr)) +# endif +#else +# define JSON_HEDLEY_CPP_CAST(T, expr) (expr) +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wdeprecated-declarations") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("clang diagnostic ignored \"-Wdeprecated-declarations\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("warning(disable:1478 1786)") +#elif JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED __pragma(warning(disable:1478 1786)) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(20,7,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1216,1444,1445") +#elif JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1444") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,3,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"") +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED __pragma(warning(disable:4996)) +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1444") +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1291,1718") +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) && !defined(__cplusplus) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("error_messages(off,E_DEPRECATED_ATT,E_DEPRECATED_ATT_MESS)") +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) && defined(__cplusplus) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("error_messages(off,symdeprecated,symdeprecated2)") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress=Pe1444,Pe1215") +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(2,90,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("warn(disable:2241)") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-pragmas") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("clang diagnostic ignored \"-Wunknown-pragmas\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("warning(disable:161)") +#elif JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS __pragma(warning(disable:161)) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 1675") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,3,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("GCC diagnostic ignored \"-Wunknown-pragmas\"") +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS __pragma(warning(disable:4068)) +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(16,9,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,3,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 163") +#elif JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 163") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress=Pe161") +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 161") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-attributes") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("clang diagnostic ignored \"-Wunknown-attributes\"") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,6,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(17,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("warning(disable:1292)") +#elif JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES __pragma(warning(disable:1292)) +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(19,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES __pragma(warning(disable:5030)) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(20,7,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097,1098") +#elif JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097") +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,14,0) && defined(__cplusplus) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("error_messages(off,attrskipunsup)") +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(18,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,3,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1173") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress=Pe1097") +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wcast-qual") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("clang diagnostic ignored \"-Wcast-qual\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("warning(disable:2203 2331)") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(3,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("GCC diagnostic ignored \"-Wcast-qual\"") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunused-function") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("clang diagnostic ignored \"-Wunused-function\"") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("GCC diagnostic ignored \"-Wunused-function\"") +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(1,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION __pragma(warning(disable:4505)) +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("diag_suppress 3142") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION +#endif + +#if defined(JSON_HEDLEY_DEPRECATED) + #undef JSON_HEDLEY_DEPRECATED +#endif +#if defined(JSON_HEDLEY_DEPRECATED_FOR) + #undef JSON_HEDLEY_DEPRECATED_FOR +#endif +#if \ + JSON_HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DEPRECATED(since) __declspec(deprecated("Since " # since)) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __declspec(deprecated("Since " #since "; use " #replacement)) +#elif \ + (JSON_HEDLEY_HAS_EXTENSION(attribute_deprecated_with_message) && !defined(JSON_HEDLEY_IAR_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,5,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,6,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(18,1,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(18,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,3,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,3,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DEPRECATED(since) __attribute__((__deprecated__("Since " #since))) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __attribute__((__deprecated__("Since " #since "; use " #replacement))) +#elif defined(__cplusplus) && (__cplusplus >= 201402L) + #define JSON_HEDLEY_DEPRECATED(since) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[deprecated("Since " #since)]]) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[deprecated("Since " #since "; use " #replacement)]]) +#elif \ + JSON_HEDLEY_HAS_ATTRIBUTE(deprecated) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) + #define JSON_HEDLEY_DEPRECATED(since) __attribute__((__deprecated__)) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __attribute__((__deprecated__)) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_PELLES_VERSION_CHECK(6,50,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DEPRECATED(since) __declspec(deprecated) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __declspec(deprecated) +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DEPRECATED(since) _Pragma("deprecated") + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) _Pragma("deprecated") +#else + #define JSON_HEDLEY_DEPRECATED(since) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) +#endif + +#if defined(JSON_HEDLEY_UNAVAILABLE) + #undef JSON_HEDLEY_UNAVAILABLE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(warning) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,3,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_UNAVAILABLE(available_since) __attribute__((__warning__("Not available until " #available_since))) +#else + #define JSON_HEDLEY_UNAVAILABLE(available_since) +#endif + +#if defined(JSON_HEDLEY_WARN_UNUSED_RESULT) + #undef JSON_HEDLEY_WARN_UNUSED_RESULT +#endif +#if defined(JSON_HEDLEY_WARN_UNUSED_RESULT_MSG) + #undef JSON_HEDLEY_WARN_UNUSED_RESULT_MSG +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(warn_unused_result) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0) && defined(__cplusplus)) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_WARN_UNUSED_RESULT __attribute__((__warn_unused_result__)) + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) __attribute__((__warn_unused_result__)) +#elif (JSON_HEDLEY_HAS_CPP_ATTRIBUTE(nodiscard) >= 201907L) + #define JSON_HEDLEY_WARN_UNUSED_RESULT JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]]) + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard(msg)]]) +#elif JSON_HEDLEY_HAS_CPP_ATTRIBUTE(nodiscard) + #define JSON_HEDLEY_WARN_UNUSED_RESULT JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]]) + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]]) +#elif defined(_Check_return_) /* SAL */ + #define JSON_HEDLEY_WARN_UNUSED_RESULT _Check_return_ + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) _Check_return_ +#else + #define JSON_HEDLEY_WARN_UNUSED_RESULT + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) +#endif + +#if defined(JSON_HEDLEY_SENTINEL) + #undef JSON_HEDLEY_SENTINEL +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(sentinel) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,4,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_SENTINEL(position) __attribute__((__sentinel__(position))) +#else + #define JSON_HEDLEY_SENTINEL(position) +#endif + +#if defined(JSON_HEDLEY_NO_RETURN) + #undef JSON_HEDLEY_NO_RETURN +#endif +#if JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_NO_RETURN __noreturn +#elif \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_NO_RETURN __attribute__((__noreturn__)) +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define JSON_HEDLEY_NO_RETURN _Noreturn +#elif defined(__cplusplus) && (__cplusplus >= 201103L) + #define JSON_HEDLEY_NO_RETURN JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[noreturn]]) +#elif \ + JSON_HEDLEY_HAS_ATTRIBUTE(noreturn) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,2,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) + #define JSON_HEDLEY_NO_RETURN __attribute__((__noreturn__)) +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) + #define JSON_HEDLEY_NO_RETURN _Pragma("does_not_return") +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_NO_RETURN __declspec(noreturn) +#elif JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,0,0) && defined(__cplusplus) + #define JSON_HEDLEY_NO_RETURN _Pragma("FUNC_NEVER_RETURNS;") +#elif JSON_HEDLEY_COMPCERT_VERSION_CHECK(3,2,0) + #define JSON_HEDLEY_NO_RETURN __attribute((noreturn)) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(9,0,0) + #define JSON_HEDLEY_NO_RETURN __declspec(noreturn) +#else + #define JSON_HEDLEY_NO_RETURN +#endif + +#if defined(JSON_HEDLEY_NO_ESCAPE) + #undef JSON_HEDLEY_NO_ESCAPE +#endif +#if JSON_HEDLEY_HAS_ATTRIBUTE(noescape) + #define JSON_HEDLEY_NO_ESCAPE __attribute__((__noescape__)) +#else + #define JSON_HEDLEY_NO_ESCAPE +#endif + +#if defined(JSON_HEDLEY_UNREACHABLE) + #undef JSON_HEDLEY_UNREACHABLE +#endif +#if defined(JSON_HEDLEY_UNREACHABLE_RETURN) + #undef JSON_HEDLEY_UNREACHABLE_RETURN +#endif +#if defined(JSON_HEDLEY_ASSUME) + #undef JSON_HEDLEY_ASSUME +#endif +#if \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_ASSUME(expr) __assume(expr) +#elif JSON_HEDLEY_HAS_BUILTIN(__builtin_assume) + #define JSON_HEDLEY_ASSUME(expr) __builtin_assume(expr) +#elif \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) + #if defined(__cplusplus) + #define JSON_HEDLEY_ASSUME(expr) std::_nassert(expr) + #else + #define JSON_HEDLEY_ASSUME(expr) _nassert(expr) + #endif +#endif +#if \ + (JSON_HEDLEY_HAS_BUILTIN(__builtin_unreachable) && (!defined(JSON_HEDLEY_ARM_VERSION))) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,5,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(18,10,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,5) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(10,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_UNREACHABLE() __builtin_unreachable() +#elif defined(JSON_HEDLEY_ASSUME) + #define JSON_HEDLEY_UNREACHABLE() JSON_HEDLEY_ASSUME(0) +#endif +#if !defined(JSON_HEDLEY_ASSUME) + #if defined(JSON_HEDLEY_UNREACHABLE) + #define JSON_HEDLEY_ASSUME(expr) JSON_HEDLEY_STATIC_CAST(void, ((expr) ? 1 : (JSON_HEDLEY_UNREACHABLE(), 1))) + #else + #define JSON_HEDLEY_ASSUME(expr) JSON_HEDLEY_STATIC_CAST(void, expr) + #endif +#endif +#if defined(JSON_HEDLEY_UNREACHABLE) + #if \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) + #define JSON_HEDLEY_UNREACHABLE_RETURN(value) return (JSON_HEDLEY_STATIC_CAST(void, JSON_HEDLEY_ASSUME(0)), (value)) + #else + #define JSON_HEDLEY_UNREACHABLE_RETURN(value) JSON_HEDLEY_UNREACHABLE() + #endif +#else + #define JSON_HEDLEY_UNREACHABLE_RETURN(value) return (value) +#endif +#if !defined(JSON_HEDLEY_UNREACHABLE) + #define JSON_HEDLEY_UNREACHABLE() JSON_HEDLEY_ASSUME(0) +#endif + +JSON_HEDLEY_DIAGNOSTIC_PUSH +#if JSON_HEDLEY_HAS_WARNING("-Wpedantic") + #pragma clang diagnostic ignored "-Wpedantic" +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wc++98-compat-pedantic") && defined(__cplusplus) + #pragma clang diagnostic ignored "-Wc++98-compat-pedantic" +#endif +#if JSON_HEDLEY_GCC_HAS_WARNING("-Wvariadic-macros",4,0,0) + #if defined(__clang__) + #pragma clang diagnostic ignored "-Wvariadic-macros" + #elif defined(JSON_HEDLEY_GCC_VERSION) + #pragma GCC diagnostic ignored "-Wvariadic-macros" + #endif +#endif +#if defined(JSON_HEDLEY_NON_NULL) + #undef JSON_HEDLEY_NON_NULL +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(nonnull) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,3,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) + #define JSON_HEDLEY_NON_NULL(...) __attribute__((__nonnull__(__VA_ARGS__))) +#else + #define JSON_HEDLEY_NON_NULL(...) +#endif +JSON_HEDLEY_DIAGNOSTIC_POP + +#if defined(JSON_HEDLEY_PRINTF_FORMAT) + #undef JSON_HEDLEY_PRINTF_FORMAT +#endif +#if defined(__MINGW32__) && JSON_HEDLEY_GCC_HAS_ATTRIBUTE(format,4,4,0) && !defined(__USE_MINGW_ANSI_STDIO) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(ms_printf, string_idx, first_to_check))) +#elif defined(__MINGW32__) && JSON_HEDLEY_GCC_HAS_ATTRIBUTE(format,4,4,0) && defined(__USE_MINGW_ANSI_STDIO) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(gnu_printf, string_idx, first_to_check))) +#elif \ + JSON_HEDLEY_HAS_ATTRIBUTE(format) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,6,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(__printf__, string_idx, first_to_check))) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(6,0,0) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __declspec(vaformat(printf,string_idx,first_to_check)) +#else + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) +#endif + +#if defined(JSON_HEDLEY_CONSTEXPR) + #undef JSON_HEDLEY_CONSTEXPR +#endif +#if defined(__cplusplus) + #if __cplusplus >= 201103L + #define JSON_HEDLEY_CONSTEXPR JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(constexpr) + #endif +#endif +#if !defined(JSON_HEDLEY_CONSTEXPR) + #define JSON_HEDLEY_CONSTEXPR +#endif + +#if defined(JSON_HEDLEY_PREDICT) + #undef JSON_HEDLEY_PREDICT +#endif +#if defined(JSON_HEDLEY_LIKELY) + #undef JSON_HEDLEY_LIKELY +#endif +#if defined(JSON_HEDLEY_UNLIKELY) + #undef JSON_HEDLEY_UNLIKELY +#endif +#if defined(JSON_HEDLEY_UNPREDICTABLE) + #undef JSON_HEDLEY_UNPREDICTABLE +#endif +#if JSON_HEDLEY_HAS_BUILTIN(__builtin_unpredictable) + #define JSON_HEDLEY_UNPREDICTABLE(expr) __builtin_unpredictable((expr)) +#endif +#if \ + (JSON_HEDLEY_HAS_BUILTIN(__builtin_expect_with_probability) && !defined(JSON_HEDLEY_PGI_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(9,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PREDICT(expr, value, probability) __builtin_expect_with_probability( (expr), (value), (probability)) +# define JSON_HEDLEY_PREDICT_TRUE(expr, probability) __builtin_expect_with_probability(!!(expr), 1 , (probability)) +# define JSON_HEDLEY_PREDICT_FALSE(expr, probability) __builtin_expect_with_probability(!!(expr), 0 , (probability)) +# define JSON_HEDLEY_LIKELY(expr) __builtin_expect (!!(expr), 1 ) +# define JSON_HEDLEY_UNLIKELY(expr) __builtin_expect (!!(expr), 0 ) +#elif \ + (JSON_HEDLEY_HAS_BUILTIN(__builtin_expect) && !defined(JSON_HEDLEY_INTEL_CL_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0) && defined(__cplusplus)) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,7,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,27) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PREDICT(expr, expected, probability) \ + (((probability) >= 0.9) ? __builtin_expect((expr), (expected)) : (JSON_HEDLEY_STATIC_CAST(void, expected), (expr))) +# define JSON_HEDLEY_PREDICT_TRUE(expr, probability) \ + (__extension__ ({ \ + double hedley_probability_ = (probability); \ + ((hedley_probability_ >= 0.9) ? __builtin_expect(!!(expr), 1) : ((hedley_probability_ <= 0.1) ? __builtin_expect(!!(expr), 0) : !!(expr))); \ + })) +# define JSON_HEDLEY_PREDICT_FALSE(expr, probability) \ + (__extension__ ({ \ + double hedley_probability_ = (probability); \ + ((hedley_probability_ >= 0.9) ? __builtin_expect(!!(expr), 0) : ((hedley_probability_ <= 0.1) ? __builtin_expect(!!(expr), 1) : !!(expr))); \ + })) +# define JSON_HEDLEY_LIKELY(expr) __builtin_expect(!!(expr), 1) +# define JSON_HEDLEY_UNLIKELY(expr) __builtin_expect(!!(expr), 0) +#else +# define JSON_HEDLEY_PREDICT(expr, expected, probability) (JSON_HEDLEY_STATIC_CAST(void, expected), (expr)) +# define JSON_HEDLEY_PREDICT_TRUE(expr, probability) (!!(expr)) +# define JSON_HEDLEY_PREDICT_FALSE(expr, probability) (!!(expr)) +# define JSON_HEDLEY_LIKELY(expr) (!!(expr)) +# define JSON_HEDLEY_UNLIKELY(expr) (!!(expr)) +#endif +#if !defined(JSON_HEDLEY_UNPREDICTABLE) + #define JSON_HEDLEY_UNPREDICTABLE(expr) JSON_HEDLEY_PREDICT(expr, 1, 0.5) +#endif + +#if defined(JSON_HEDLEY_MALLOC) + #undef JSON_HEDLEY_MALLOC +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(malloc) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(12,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_MALLOC __attribute__((__malloc__)) +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) + #define JSON_HEDLEY_MALLOC _Pragma("returns_new_memory") +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_MALLOC __declspec(restrict) +#else + #define JSON_HEDLEY_MALLOC +#endif + +#if defined(JSON_HEDLEY_PURE) + #undef JSON_HEDLEY_PURE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(pure) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(2,96,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PURE __attribute__((__pure__)) +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) +# define JSON_HEDLEY_PURE _Pragma("does_not_write_global_data") +#elif defined(__cplusplus) && \ + ( \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(2,0,1) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) \ + ) +# define JSON_HEDLEY_PURE _Pragma("FUNC_IS_PURE;") +#else +# define JSON_HEDLEY_PURE +#endif + +#if defined(JSON_HEDLEY_CONST) + #undef JSON_HEDLEY_CONST +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(const) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(2,5,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_CONST __attribute__((__const__)) +#elif \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) + #define JSON_HEDLEY_CONST _Pragma("no_side_effect") +#else + #define JSON_HEDLEY_CONST JSON_HEDLEY_PURE +#endif + +#if defined(JSON_HEDLEY_RESTRICT) + #undef JSON_HEDLEY_RESTRICT +#endif +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) && !defined(__cplusplus) + #define JSON_HEDLEY_RESTRICT restrict +#elif \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,4) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,14,0) && defined(__cplusplus)) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) || \ + defined(__clang__) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_RESTRICT __restrict +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,3,0) && !defined(__cplusplus) + #define JSON_HEDLEY_RESTRICT _Restrict +#else + #define JSON_HEDLEY_RESTRICT +#endif + +#if defined(JSON_HEDLEY_INLINE) + #undef JSON_HEDLEY_INLINE +#endif +#if \ + (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || \ + (defined(__cplusplus) && (__cplusplus >= 199711L)) + #define JSON_HEDLEY_INLINE inline +#elif \ + defined(JSON_HEDLEY_GCC_VERSION) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(6,2,0) + #define JSON_HEDLEY_INLINE __inline__ +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(12,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,1,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_INLINE __inline +#else + #define JSON_HEDLEY_INLINE +#endif + +#if defined(JSON_HEDLEY_ALWAYS_INLINE) + #undef JSON_HEDLEY_ALWAYS_INLINE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(always_inline) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) +# define JSON_HEDLEY_ALWAYS_INLINE __attribute__((__always_inline__)) JSON_HEDLEY_INLINE +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(12,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) +# define JSON_HEDLEY_ALWAYS_INLINE __forceinline +#elif defined(__cplusplus) && \ + ( \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) \ + ) +# define JSON_HEDLEY_ALWAYS_INLINE _Pragma("FUNC_ALWAYS_INLINE;") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) +# define JSON_HEDLEY_ALWAYS_INLINE _Pragma("inline=forced") +#else +# define JSON_HEDLEY_ALWAYS_INLINE JSON_HEDLEY_INLINE +#endif + +#if defined(JSON_HEDLEY_NEVER_INLINE) + #undef JSON_HEDLEY_NEVER_INLINE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(noinline) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) + #define JSON_HEDLEY_NEVER_INLINE __attribute__((__noinline__)) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_NEVER_INLINE __declspec(noinline) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(10,2,0) + #define JSON_HEDLEY_NEVER_INLINE _Pragma("noinline") +#elif JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,0,0) && defined(__cplusplus) + #define JSON_HEDLEY_NEVER_INLINE _Pragma("FUNC_CANNOT_INLINE;") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_NEVER_INLINE _Pragma("inline=never") +#elif JSON_HEDLEY_COMPCERT_VERSION_CHECK(3,2,0) + #define JSON_HEDLEY_NEVER_INLINE __attribute((noinline)) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(9,0,0) + #define JSON_HEDLEY_NEVER_INLINE __declspec(noinline) +#else + #define JSON_HEDLEY_NEVER_INLINE +#endif + +#if defined(JSON_HEDLEY_PRIVATE) + #undef JSON_HEDLEY_PRIVATE +#endif +#if defined(JSON_HEDLEY_PUBLIC) + #undef JSON_HEDLEY_PUBLIC +#endif +#if defined(JSON_HEDLEY_IMPORT) + #undef JSON_HEDLEY_IMPORT +#endif +#if defined(_WIN32) || defined(__CYGWIN__) +# define JSON_HEDLEY_PRIVATE +# define JSON_HEDLEY_PUBLIC __declspec(dllexport) +# define JSON_HEDLEY_IMPORT __declspec(dllimport) +#else +# if \ + JSON_HEDLEY_HAS_ATTRIBUTE(visibility) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,3,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,0) || \ + ( \ + defined(__TI_EABI__) && \ + ( \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) \ + ) \ + ) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PRIVATE __attribute__((__visibility__("hidden"))) +# define JSON_HEDLEY_PUBLIC __attribute__((__visibility__("default"))) +# else +# define JSON_HEDLEY_PRIVATE +# define JSON_HEDLEY_PUBLIC +# endif +# define JSON_HEDLEY_IMPORT extern +#endif + +#if defined(JSON_HEDLEY_NO_THROW) + #undef JSON_HEDLEY_NO_THROW +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(nothrow) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,3,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_NO_THROW __attribute__((__nothrow__)) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,1,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) + #define JSON_HEDLEY_NO_THROW __declspec(nothrow) +#else + #define JSON_HEDLEY_NO_THROW +#endif + +#if defined(JSON_HEDLEY_FALL_THROUGH) + #undef JSON_HEDLEY_FALL_THROUGH +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(fallthrough) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(7,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_FALL_THROUGH __attribute__((__fallthrough__)) +#elif JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(clang,fallthrough) + #define JSON_HEDLEY_FALL_THROUGH JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[clang::fallthrough]]) +#elif JSON_HEDLEY_HAS_CPP_ATTRIBUTE(fallthrough) + #define JSON_HEDLEY_FALL_THROUGH JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[fallthrough]]) +#elif defined(__fallthrough) /* SAL */ + #define JSON_HEDLEY_FALL_THROUGH __fallthrough +#else + #define JSON_HEDLEY_FALL_THROUGH +#endif + +#if defined(JSON_HEDLEY_RETURNS_NON_NULL) + #undef JSON_HEDLEY_RETURNS_NON_NULL +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(returns_nonnull) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,9,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_RETURNS_NON_NULL __attribute__((__returns_nonnull__)) +#elif defined(_Ret_notnull_) /* SAL */ + #define JSON_HEDLEY_RETURNS_NON_NULL _Ret_notnull_ +#else + #define JSON_HEDLEY_RETURNS_NON_NULL +#endif + +#if defined(JSON_HEDLEY_ARRAY_PARAM) + #undef JSON_HEDLEY_ARRAY_PARAM +#endif +#if \ + defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) && \ + !defined(__STDC_NO_VLA__) && \ + !defined(__cplusplus) && \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_TINYC_VERSION) + #define JSON_HEDLEY_ARRAY_PARAM(name) (name) +#else + #define JSON_HEDLEY_ARRAY_PARAM(name) +#endif + +#if defined(JSON_HEDLEY_IS_CONSTANT) + #undef JSON_HEDLEY_IS_CONSTANT +#endif +#if defined(JSON_HEDLEY_REQUIRE_CONSTEXPR) + #undef JSON_HEDLEY_REQUIRE_CONSTEXPR +#endif +/* JSON_HEDLEY_IS_CONSTEXPR_ is for + HEDLEY INTERNAL USE ONLY. API subject to change without notice. */ +#if defined(JSON_HEDLEY_IS_CONSTEXPR_) + #undef JSON_HEDLEY_IS_CONSTEXPR_ +#endif +#if \ + JSON_HEDLEY_HAS_BUILTIN(__builtin_constant_p) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,19) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) && !defined(__cplusplus)) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_IS_CONSTANT(expr) __builtin_constant_p(expr) +#endif +#if !defined(__cplusplus) +# if \ + JSON_HEDLEY_HAS_BUILTIN(__builtin_types_compatible_p) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,0) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,4,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,24) +#if defined(__INTPTR_TYPE__) + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) __builtin_types_compatible_p(__typeof__((1 ? (void*) ((__INTPTR_TYPE__) ((expr) * 0)) : (int*) 0)), int*) +#else + #include + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) __builtin_types_compatible_p(__typeof__((1 ? (void*) ((intptr_t) ((expr) * 0)) : (int*) 0)), int*) +#endif +# elif \ + ( \ + defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) && \ + !defined(JSON_HEDLEY_SUNPRO_VERSION) && \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_IAR_VERSION)) || \ + (JSON_HEDLEY_HAS_EXTENSION(c_generic_selections) && !defined(JSON_HEDLEY_IAR_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,9,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(17,0,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(12,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,3,0) +#if defined(__INTPTR_TYPE__) + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) _Generic((1 ? (void*) ((__INTPTR_TYPE__) ((expr) * 0)) : (int*) 0), int*: 1, void*: 0) +#else + #include + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) _Generic((1 ? (void*) ((intptr_t) * 0) : (int*) 0), int*: 1, void*: 0) +#endif +# elif \ + defined(JSON_HEDLEY_GCC_VERSION) || \ + defined(JSON_HEDLEY_INTEL_VERSION) || \ + defined(JSON_HEDLEY_TINYC_VERSION) || \ + defined(JSON_HEDLEY_TI_ARMCL_VERSION) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(18,12,0) || \ + defined(JSON_HEDLEY_TI_CL2000_VERSION) || \ + defined(JSON_HEDLEY_TI_CL6X_VERSION) || \ + defined(JSON_HEDLEY_TI_CL7X_VERSION) || \ + defined(JSON_HEDLEY_TI_CLPRU_VERSION) || \ + defined(__clang__) +# define JSON_HEDLEY_IS_CONSTEXPR_(expr) ( \ + sizeof(void) != \ + sizeof(*( \ + 1 ? \ + ((void*) ((expr) * 0L) ) : \ +((struct { char v[sizeof(void) * 2]; } *) 1) \ + ) \ + ) \ + ) +# endif +#endif +#if defined(JSON_HEDLEY_IS_CONSTEXPR_) + #if !defined(JSON_HEDLEY_IS_CONSTANT) + #define JSON_HEDLEY_IS_CONSTANT(expr) JSON_HEDLEY_IS_CONSTEXPR_(expr) + #endif + #define JSON_HEDLEY_REQUIRE_CONSTEXPR(expr) (JSON_HEDLEY_IS_CONSTEXPR_(expr) ? (expr) : (-1)) +#else + #if !defined(JSON_HEDLEY_IS_CONSTANT) + #define JSON_HEDLEY_IS_CONSTANT(expr) (0) + #endif + #define JSON_HEDLEY_REQUIRE_CONSTEXPR(expr) (expr) +#endif + +#if defined(JSON_HEDLEY_BEGIN_C_DECLS) + #undef JSON_HEDLEY_BEGIN_C_DECLS +#endif +#if defined(JSON_HEDLEY_END_C_DECLS) + #undef JSON_HEDLEY_END_C_DECLS +#endif +#if defined(JSON_HEDLEY_C_DECL) + #undef JSON_HEDLEY_C_DECL +#endif +#if defined(__cplusplus) + #define JSON_HEDLEY_BEGIN_C_DECLS extern "C" { + #define JSON_HEDLEY_END_C_DECLS } + #define JSON_HEDLEY_C_DECL extern "C" +#else + #define JSON_HEDLEY_BEGIN_C_DECLS + #define JSON_HEDLEY_END_C_DECLS + #define JSON_HEDLEY_C_DECL +#endif + +#if defined(JSON_HEDLEY_STATIC_ASSERT) + #undef JSON_HEDLEY_STATIC_ASSERT +#endif +#if \ + !defined(__cplusplus) && ( \ + (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)) || \ + (JSON_HEDLEY_HAS_FEATURE(c_static_assert) && !defined(JSON_HEDLEY_INTEL_CL_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(6,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + defined(_Static_assert) \ + ) +# define JSON_HEDLEY_STATIC_ASSERT(expr, message) _Static_assert(expr, message) +#elif \ + (defined(__cplusplus) && (__cplusplus >= 201103L)) || \ + JSON_HEDLEY_MSVC_VERSION_CHECK(16,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) +# define JSON_HEDLEY_STATIC_ASSERT(expr, message) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(static_assert(expr, message)) +#else +# define JSON_HEDLEY_STATIC_ASSERT(expr, message) +#endif + +#if defined(JSON_HEDLEY_NULL) + #undef JSON_HEDLEY_NULL +#endif +#if defined(__cplusplus) + #if __cplusplus >= 201103L + #define JSON_HEDLEY_NULL JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(nullptr) + #elif defined(NULL) + #define JSON_HEDLEY_NULL NULL + #else + #define JSON_HEDLEY_NULL JSON_HEDLEY_STATIC_CAST(void*, 0) + #endif +#elif defined(NULL) + #define JSON_HEDLEY_NULL NULL +#else + #define JSON_HEDLEY_NULL ((void*) 0) +#endif + +#if defined(JSON_HEDLEY_MESSAGE) + #undef JSON_HEDLEY_MESSAGE +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-pragmas") +# define JSON_HEDLEY_MESSAGE(msg) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS \ + JSON_HEDLEY_PRAGMA(message msg) \ + JSON_HEDLEY_DIAGNOSTIC_POP +#elif \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(message msg) +#elif JSON_HEDLEY_CRAY_VERSION_CHECK(5,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(_CRI message msg) +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(message(msg)) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(2,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(message(msg)) +#else +# define JSON_HEDLEY_MESSAGE(msg) +#endif + +#if defined(JSON_HEDLEY_WARNING) + #undef JSON_HEDLEY_WARNING +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-pragmas") +# define JSON_HEDLEY_WARNING(msg) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS \ + JSON_HEDLEY_PRAGMA(clang warning msg) \ + JSON_HEDLEY_DIAGNOSTIC_POP +#elif \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,8,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(18,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) +# define JSON_HEDLEY_WARNING(msg) JSON_HEDLEY_PRAGMA(GCC warning msg) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) +# define JSON_HEDLEY_WARNING(msg) JSON_HEDLEY_PRAGMA(message(msg)) +#else +# define JSON_HEDLEY_WARNING(msg) JSON_HEDLEY_MESSAGE(msg) +#endif + +#if defined(JSON_HEDLEY_REQUIRE) + #undef JSON_HEDLEY_REQUIRE +#endif +#if defined(JSON_HEDLEY_REQUIRE_MSG) + #undef JSON_HEDLEY_REQUIRE_MSG +#endif +#if JSON_HEDLEY_HAS_ATTRIBUTE(diagnose_if) +# if JSON_HEDLEY_HAS_WARNING("-Wgcc-compat") +# define JSON_HEDLEY_REQUIRE(expr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wgcc-compat\"") \ + __attribute__((diagnose_if(!(expr), #expr, "error"))) \ + JSON_HEDLEY_DIAGNOSTIC_POP +# define JSON_HEDLEY_REQUIRE_MSG(expr,msg) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wgcc-compat\"") \ + __attribute__((diagnose_if(!(expr), msg, "error"))) \ + JSON_HEDLEY_DIAGNOSTIC_POP +# else +# define JSON_HEDLEY_REQUIRE(expr) __attribute__((diagnose_if(!(expr), #expr, "error"))) +# define JSON_HEDLEY_REQUIRE_MSG(expr,msg) __attribute__((diagnose_if(!(expr), msg, "error"))) +# endif +#else +# define JSON_HEDLEY_REQUIRE(expr) +# define JSON_HEDLEY_REQUIRE_MSG(expr,msg) +#endif + +#if defined(JSON_HEDLEY_FLAGS) + #undef JSON_HEDLEY_FLAGS +#endif +#if JSON_HEDLEY_HAS_ATTRIBUTE(flag_enum) && (!defined(__cplusplus) || JSON_HEDLEY_HAS_WARNING("-Wbitfield-enum-conversion")) + #define JSON_HEDLEY_FLAGS __attribute__((__flag_enum__)) +#else + #define JSON_HEDLEY_FLAGS +#endif + +#if defined(JSON_HEDLEY_FLAGS_CAST) + #undef JSON_HEDLEY_FLAGS_CAST +#endif +#if JSON_HEDLEY_INTEL_VERSION_CHECK(19,0,0) +# define JSON_HEDLEY_FLAGS_CAST(T, expr) (__extension__ ({ \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("warning(disable:188)") \ + ((T) (expr)); \ + JSON_HEDLEY_DIAGNOSTIC_POP \ + })) +#else +# define JSON_HEDLEY_FLAGS_CAST(T, expr) JSON_HEDLEY_STATIC_CAST(T, expr) +#endif + +#if defined(JSON_HEDLEY_EMPTY_BASES) + #undef JSON_HEDLEY_EMPTY_BASES +#endif +#if \ + (JSON_HEDLEY_MSVC_VERSION_CHECK(19,0,23918) && !JSON_HEDLEY_MSVC_VERSION_CHECK(20,0,0)) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_EMPTY_BASES __declspec(empty_bases) +#else + #define JSON_HEDLEY_EMPTY_BASES +#endif + +/* Remaining macros are deprecated. */ + +#if defined(JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK) + #undef JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK +#endif +#if defined(__clang__) + #define JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK(major,minor,patch) (0) +#else + #define JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK(major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_CLANG_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_CLANG_HAS_ATTRIBUTE +#endif +#define JSON_HEDLEY_CLANG_HAS_ATTRIBUTE(attribute) JSON_HEDLEY_HAS_ATTRIBUTE(attribute) + +#if defined(JSON_HEDLEY_CLANG_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_CLANG_HAS_CPP_ATTRIBUTE +#endif +#define JSON_HEDLEY_CLANG_HAS_CPP_ATTRIBUTE(attribute) JSON_HEDLEY_HAS_CPP_ATTRIBUTE(attribute) + +#if defined(JSON_HEDLEY_CLANG_HAS_BUILTIN) + #undef JSON_HEDLEY_CLANG_HAS_BUILTIN +#endif +#define JSON_HEDLEY_CLANG_HAS_BUILTIN(builtin) JSON_HEDLEY_HAS_BUILTIN(builtin) + +#if defined(JSON_HEDLEY_CLANG_HAS_FEATURE) + #undef JSON_HEDLEY_CLANG_HAS_FEATURE +#endif +#define JSON_HEDLEY_CLANG_HAS_FEATURE(feature) JSON_HEDLEY_HAS_FEATURE(feature) + +#if defined(JSON_HEDLEY_CLANG_HAS_EXTENSION) + #undef JSON_HEDLEY_CLANG_HAS_EXTENSION +#endif +#define JSON_HEDLEY_CLANG_HAS_EXTENSION(extension) JSON_HEDLEY_HAS_EXTENSION(extension) + +#if defined(JSON_HEDLEY_CLANG_HAS_DECLSPEC_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_CLANG_HAS_DECLSPEC_DECLSPEC_ATTRIBUTE +#endif +#define JSON_HEDLEY_CLANG_HAS_DECLSPEC_ATTRIBUTE(attribute) JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) + +#if defined(JSON_HEDLEY_CLANG_HAS_WARNING) + #undef JSON_HEDLEY_CLANG_HAS_WARNING +#endif +#define JSON_HEDLEY_CLANG_HAS_WARNING(warning) JSON_HEDLEY_HAS_WARNING(warning) + +#endif /* !defined(JSON_HEDLEY_VERSION) || (JSON_HEDLEY_VERSION < X) */ + + +// This file contains all internal macro definitions (except those affecting ABI) +// You MUST include macro_unscope.hpp at the end of json.hpp to undef all of them + +// #include + + +// exclude unsupported compilers +#if !defined(JSON_SKIP_UNSUPPORTED_COMPILER_CHECK) + #if defined(__clang__) + #if (__clang_major__ * 10000 + __clang_minor__ * 100 + __clang_patchlevel__) < 30400 + #error "unsupported Clang version - see https://github.com/nlohmann/json#supported-compilers" + #endif + #elif defined(__GNUC__) && !(defined(__ICC) || defined(__INTEL_COMPILER)) + #if (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) < 40800 + #error "unsupported GCC version - see https://github.com/nlohmann/json#supported-compilers" + #endif + #endif +#endif + +// C++ language standard detection +// if the user manually specified the used c++ version this is skipped +#if !defined(JSON_HAS_CPP_23) && !defined(JSON_HAS_CPP_20) && !defined(JSON_HAS_CPP_17) && !defined(JSON_HAS_CPP_14) && !defined(JSON_HAS_CPP_11) + #if (defined(__cplusplus) && __cplusplus > 202002L) || (defined(_MSVC_LANG) && _MSVC_LANG > 202002L) + #define JSON_HAS_CPP_23 + #define JSON_HAS_CPP_20 + #define JSON_HAS_CPP_17 + #define JSON_HAS_CPP_14 + #elif (defined(__cplusplus) && __cplusplus > 201703L) || (defined(_MSVC_LANG) && _MSVC_LANG > 201703L) + #define JSON_HAS_CPP_20 + #define JSON_HAS_CPP_17 + #define JSON_HAS_CPP_14 + #elif (defined(__cplusplus) && __cplusplus > 201402L) || (defined(_HAS_CXX17) && _HAS_CXX17 == 1) // fix for issue #464 + #define JSON_HAS_CPP_17 + #define JSON_HAS_CPP_14 + #elif (defined(__cplusplus) && __cplusplus > 201103L) || (defined(_HAS_CXX14) && _HAS_CXX14 == 1) + #define JSON_HAS_CPP_14 + #endif + // the cpp 11 flag is always specified because it is the minimal required version + #define JSON_HAS_CPP_11 +#endif + +#ifdef __has_include + #if __has_include() + #include + #endif +#endif + +#if !defined(JSON_HAS_FILESYSTEM) && !defined(JSON_HAS_EXPERIMENTAL_FILESYSTEM) + #ifdef JSON_HAS_CPP_17 + #if defined(__cpp_lib_filesystem) + #define JSON_HAS_FILESYSTEM 1 + #elif defined(__cpp_lib_experimental_filesystem) + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 1 + #elif !defined(__has_include) + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 1 + #elif __has_include() + #define JSON_HAS_FILESYSTEM 1 + #elif __has_include() + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 1 + #endif + + // std::filesystem does not work on MinGW GCC 8: https://sourceforge.net/p/mingw-w64/bugs/737/ + #if defined(__MINGW32__) && defined(__GNUC__) && __GNUC__ == 8 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before GCC 8: https://en.cppreference.com/w/cpp/compiler_support + #if defined(__GNUC__) && !defined(__clang__) && __GNUC__ < 8 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before Clang 7: https://en.cppreference.com/w/cpp/compiler_support + #if defined(__clang_major__) && __clang_major__ < 7 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before MSVC 19.14: https://en.cppreference.com/w/cpp/compiler_support + #if defined(_MSC_VER) && _MSC_VER < 1914 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before iOS 13 + #if defined(__IPHONE_OS_VERSION_MIN_REQUIRED) && __IPHONE_OS_VERSION_MIN_REQUIRED < 130000 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before macOS Catalina + #if defined(__MAC_OS_X_VERSION_MIN_REQUIRED) && __MAC_OS_X_VERSION_MIN_REQUIRED < 101500 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + #endif +#endif + +#ifndef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 0 +#endif + +#ifndef JSON_HAS_FILESYSTEM + #define JSON_HAS_FILESYSTEM 0 +#endif + +#ifndef JSON_HAS_THREE_WAY_COMPARISON + #if defined(__cpp_impl_three_way_comparison) && __cpp_impl_three_way_comparison >= 201907L \ + && defined(__cpp_lib_three_way_comparison) && __cpp_lib_three_way_comparison >= 201907L + #define JSON_HAS_THREE_WAY_COMPARISON 1 + #else + #define JSON_HAS_THREE_WAY_COMPARISON 0 + #endif +#endif + +#ifndef JSON_HAS_RANGES + // ranges header shipping in GCC 11.1.0 (released 2021-04-27) has syntax error + #if defined(__GLIBCXX__) && __GLIBCXX__ == 20210427 + #define JSON_HAS_RANGES 0 + #elif defined(__cpp_lib_ranges) + #define JSON_HAS_RANGES 1 + #else + #define JSON_HAS_RANGES 0 + #endif +#endif + +#ifndef JSON_HAS_STATIC_RTTI + #if !defined(_HAS_STATIC_RTTI) || _HAS_STATIC_RTTI != 0 + #define JSON_HAS_STATIC_RTTI 1 + #else + #define JSON_HAS_STATIC_RTTI 0 + #endif +#endif + +#ifdef JSON_HAS_CPP_17 + #define JSON_INLINE_VARIABLE inline +#else + #define JSON_INLINE_VARIABLE +#endif + +#if JSON_HEDLEY_HAS_ATTRIBUTE(no_unique_address) + #define JSON_NO_UNIQUE_ADDRESS [[no_unique_address]] +#else + #define JSON_NO_UNIQUE_ADDRESS +#endif + +// disable documentation warnings on clang +#if defined(__clang__) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wdocumentation" + #pragma clang diagnostic ignored "-Wdocumentation-unknown-command" +#endif + +// allow disabling exceptions +#if (defined(__cpp_exceptions) || defined(__EXCEPTIONS) || defined(_CPPUNWIND)) && !defined(JSON_NOEXCEPTION) + #define JSON_THROW(exception) throw exception + #define JSON_TRY try + #define JSON_CATCH(exception) catch(exception) + #define JSON_INTERNAL_CATCH(exception) catch(exception) +#else + #include + #define JSON_THROW(exception) std::abort() + #define JSON_TRY if(true) + #define JSON_CATCH(exception) if(false) + #define JSON_INTERNAL_CATCH(exception) if(false) +#endif + +// override exception macros +#if defined(JSON_THROW_USER) + #undef JSON_THROW + #define JSON_THROW JSON_THROW_USER +#endif +#if defined(JSON_TRY_USER) + #undef JSON_TRY + #define JSON_TRY JSON_TRY_USER +#endif +#if defined(JSON_CATCH_USER) + #undef JSON_CATCH + #define JSON_CATCH JSON_CATCH_USER + #undef JSON_INTERNAL_CATCH + #define JSON_INTERNAL_CATCH JSON_CATCH_USER +#endif +#if defined(JSON_INTERNAL_CATCH_USER) + #undef JSON_INTERNAL_CATCH + #define JSON_INTERNAL_CATCH JSON_INTERNAL_CATCH_USER +#endif + +// allow overriding assert +#if !defined(JSON_ASSERT) + #include // assert + #define JSON_ASSERT(x) assert(x) +#endif + +// allow to access some private functions (needed by the test suite) +#if defined(JSON_TESTS_PRIVATE) + #define JSON_PRIVATE_UNLESS_TESTED public +#else + #define JSON_PRIVATE_UNLESS_TESTED private +#endif + +/*! +@brief macro to briefly define a mapping between an enum and JSON +@def NLOHMANN_JSON_SERIALIZE_ENUM +@since version 3.4.0 +*/ +#define NLOHMANN_JSON_SERIALIZE_ENUM(ENUM_TYPE, ...) \ + template \ + inline void to_json(BasicJsonType& j, const ENUM_TYPE& e) \ + { \ + /* NOLINTNEXTLINE(modernize-type-traits) we use C++11 */ \ + static_assert(std::is_enum::value, #ENUM_TYPE " must be an enum!"); \ + /* NOLINTNEXTLINE(modernize-avoid-c-arrays) we don't want to depend on */ \ + static const std::pair m[] = __VA_ARGS__; \ + auto it = std::find_if(std::begin(m), std::end(m), \ + [e](const std::pair& ej_pair) -> bool \ + { \ + return ej_pair.first == e; \ + }); \ + j = ((it != std::end(m)) ? it : std::begin(m))->second; \ + } \ + template \ + inline void from_json(const BasicJsonType& j, ENUM_TYPE& e) \ + { \ + /* NOLINTNEXTLINE(modernize-type-traits) we use C++11 */ \ + static_assert(std::is_enum::value, #ENUM_TYPE " must be an enum!"); \ + /* NOLINTNEXTLINE(modernize-avoid-c-arrays) we don't want to depend on */ \ + static const std::pair m[] = __VA_ARGS__; \ + auto it = std::find_if(std::begin(m), std::end(m), \ + [&j](const std::pair& ej_pair) -> bool \ + { \ + return ej_pair.second == j; \ + }); \ + e = ((it != std::end(m)) ? it : std::begin(m))->first; \ + } + +// Ugly macros to avoid uglier copy-paste when specializing basic_json. They +// may be removed in the future once the class is split. + +#define NLOHMANN_BASIC_JSON_TPL_DECLARATION \ + template class ObjectType, \ + template class ArrayType, \ + class StringType, class BooleanType, class NumberIntegerType, \ + class NumberUnsignedType, class NumberFloatType, \ + template class AllocatorType, \ + template class JSONSerializer, \ + class BinaryType, \ + class CustomBaseClass> + +#define NLOHMANN_BASIC_JSON_TPL \ + basic_json + +// Macros to simplify conversion from/to types + +#define NLOHMANN_JSON_EXPAND( x ) x +#define NLOHMANN_JSON_GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, _61, _62, _63, _64, NAME,...) NAME +#define NLOHMANN_JSON_PASTE(...) NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_GET_MACRO(__VA_ARGS__, \ + NLOHMANN_JSON_PASTE64, \ + NLOHMANN_JSON_PASTE63, \ + NLOHMANN_JSON_PASTE62, \ + NLOHMANN_JSON_PASTE61, \ + NLOHMANN_JSON_PASTE60, \ + NLOHMANN_JSON_PASTE59, \ + NLOHMANN_JSON_PASTE58, \ + NLOHMANN_JSON_PASTE57, \ + NLOHMANN_JSON_PASTE56, \ + NLOHMANN_JSON_PASTE55, \ + NLOHMANN_JSON_PASTE54, \ + NLOHMANN_JSON_PASTE53, \ + NLOHMANN_JSON_PASTE52, \ + NLOHMANN_JSON_PASTE51, \ + NLOHMANN_JSON_PASTE50, \ + NLOHMANN_JSON_PASTE49, \ + NLOHMANN_JSON_PASTE48, \ + NLOHMANN_JSON_PASTE47, \ + NLOHMANN_JSON_PASTE46, \ + NLOHMANN_JSON_PASTE45, \ + NLOHMANN_JSON_PASTE44, \ + NLOHMANN_JSON_PASTE43, \ + NLOHMANN_JSON_PASTE42, \ + NLOHMANN_JSON_PASTE41, \ + NLOHMANN_JSON_PASTE40, \ + NLOHMANN_JSON_PASTE39, \ + NLOHMANN_JSON_PASTE38, \ + NLOHMANN_JSON_PASTE37, \ + NLOHMANN_JSON_PASTE36, \ + NLOHMANN_JSON_PASTE35, \ + NLOHMANN_JSON_PASTE34, \ + NLOHMANN_JSON_PASTE33, \ + NLOHMANN_JSON_PASTE32, \ + NLOHMANN_JSON_PASTE31, \ + NLOHMANN_JSON_PASTE30, \ + NLOHMANN_JSON_PASTE29, \ + NLOHMANN_JSON_PASTE28, \ + NLOHMANN_JSON_PASTE27, \ + NLOHMANN_JSON_PASTE26, \ + NLOHMANN_JSON_PASTE25, \ + NLOHMANN_JSON_PASTE24, \ + NLOHMANN_JSON_PASTE23, \ + NLOHMANN_JSON_PASTE22, \ + NLOHMANN_JSON_PASTE21, \ + NLOHMANN_JSON_PASTE20, \ + NLOHMANN_JSON_PASTE19, \ + NLOHMANN_JSON_PASTE18, \ + NLOHMANN_JSON_PASTE17, \ + NLOHMANN_JSON_PASTE16, \ + NLOHMANN_JSON_PASTE15, \ + NLOHMANN_JSON_PASTE14, \ + NLOHMANN_JSON_PASTE13, \ + NLOHMANN_JSON_PASTE12, \ + NLOHMANN_JSON_PASTE11, \ + NLOHMANN_JSON_PASTE10, \ + NLOHMANN_JSON_PASTE9, \ + NLOHMANN_JSON_PASTE8, \ + NLOHMANN_JSON_PASTE7, \ + NLOHMANN_JSON_PASTE6, \ + NLOHMANN_JSON_PASTE5, \ + NLOHMANN_JSON_PASTE4, \ + NLOHMANN_JSON_PASTE3, \ + NLOHMANN_JSON_PASTE2, \ + NLOHMANN_JSON_PASTE1)(__VA_ARGS__)) +#define NLOHMANN_JSON_PASTE2(func, v1) func(v1) +#define NLOHMANN_JSON_PASTE3(func, v1, v2) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE2(func, v2) +#define NLOHMANN_JSON_PASTE4(func, v1, v2, v3) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE3(func, v2, v3) +#define NLOHMANN_JSON_PASTE5(func, v1, v2, v3, v4) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE4(func, v2, v3, v4) +#define NLOHMANN_JSON_PASTE6(func, v1, v2, v3, v4, v5) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE5(func, v2, v3, v4, v5) +#define NLOHMANN_JSON_PASTE7(func, v1, v2, v3, v4, v5, v6) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE6(func, v2, v3, v4, v5, v6) +#define NLOHMANN_JSON_PASTE8(func, v1, v2, v3, v4, v5, v6, v7) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE7(func, v2, v3, v4, v5, v6, v7) +#define NLOHMANN_JSON_PASTE9(func, v1, v2, v3, v4, v5, v6, v7, v8) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE8(func, v2, v3, v4, v5, v6, v7, v8) +#define NLOHMANN_JSON_PASTE10(func, v1, v2, v3, v4, v5, v6, v7, v8, v9) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE9(func, v2, v3, v4, v5, v6, v7, v8, v9) +#define NLOHMANN_JSON_PASTE11(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE10(func, v2, v3, v4, v5, v6, v7, v8, v9, v10) +#define NLOHMANN_JSON_PASTE12(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE11(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11) +#define NLOHMANN_JSON_PASTE13(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE12(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12) +#define NLOHMANN_JSON_PASTE14(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE13(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13) +#define NLOHMANN_JSON_PASTE15(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE14(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14) +#define NLOHMANN_JSON_PASTE16(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE15(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15) +#define NLOHMANN_JSON_PASTE17(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE16(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16) +#define NLOHMANN_JSON_PASTE18(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE17(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17) +#define NLOHMANN_JSON_PASTE19(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE18(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18) +#define NLOHMANN_JSON_PASTE20(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE19(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19) +#define NLOHMANN_JSON_PASTE21(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE20(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20) +#define NLOHMANN_JSON_PASTE22(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE21(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21) +#define NLOHMANN_JSON_PASTE23(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE22(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22) +#define NLOHMANN_JSON_PASTE24(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE23(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23) +#define NLOHMANN_JSON_PASTE25(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE24(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24) +#define NLOHMANN_JSON_PASTE26(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE25(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25) +#define NLOHMANN_JSON_PASTE27(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE26(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26) +#define NLOHMANN_JSON_PASTE28(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE27(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27) +#define NLOHMANN_JSON_PASTE29(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE28(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28) +#define NLOHMANN_JSON_PASTE30(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE29(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29) +#define NLOHMANN_JSON_PASTE31(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE30(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30) +#define NLOHMANN_JSON_PASTE32(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE31(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31) +#define NLOHMANN_JSON_PASTE33(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE32(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32) +#define NLOHMANN_JSON_PASTE34(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE33(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33) +#define NLOHMANN_JSON_PASTE35(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE34(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34) +#define NLOHMANN_JSON_PASTE36(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE35(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35) +#define NLOHMANN_JSON_PASTE37(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE36(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36) +#define NLOHMANN_JSON_PASTE38(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE37(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37) +#define NLOHMANN_JSON_PASTE39(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE38(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38) +#define NLOHMANN_JSON_PASTE40(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE39(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39) +#define NLOHMANN_JSON_PASTE41(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE40(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40) +#define NLOHMANN_JSON_PASTE42(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE41(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41) +#define NLOHMANN_JSON_PASTE43(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE42(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42) +#define NLOHMANN_JSON_PASTE44(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE43(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43) +#define NLOHMANN_JSON_PASTE45(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE44(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44) +#define NLOHMANN_JSON_PASTE46(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE45(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45) +#define NLOHMANN_JSON_PASTE47(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE46(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46) +#define NLOHMANN_JSON_PASTE48(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE47(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47) +#define NLOHMANN_JSON_PASTE49(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE48(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48) +#define NLOHMANN_JSON_PASTE50(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE49(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49) +#define NLOHMANN_JSON_PASTE51(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE50(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50) +#define NLOHMANN_JSON_PASTE52(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE51(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51) +#define NLOHMANN_JSON_PASTE53(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE52(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52) +#define NLOHMANN_JSON_PASTE54(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE53(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53) +#define NLOHMANN_JSON_PASTE55(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE54(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54) +#define NLOHMANN_JSON_PASTE56(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE55(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55) +#define NLOHMANN_JSON_PASTE57(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE56(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56) +#define NLOHMANN_JSON_PASTE58(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE57(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57) +#define NLOHMANN_JSON_PASTE59(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE58(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58) +#define NLOHMANN_JSON_PASTE60(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE59(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59) +#define NLOHMANN_JSON_PASTE61(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE60(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60) +#define NLOHMANN_JSON_PASTE62(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE61(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61) +#define NLOHMANN_JSON_PASTE63(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE62(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62) +#define NLOHMANN_JSON_PASTE64(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE63(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63) + +#define NLOHMANN_JSON_TO(v1) nlohmann_json_j[#v1] = nlohmann_json_t.v1; +#define NLOHMANN_JSON_FROM(v1) nlohmann_json_j.at(#v1).get_to(nlohmann_json_t.v1); +#define NLOHMANN_JSON_FROM_WITH_DEFAULT(v1) nlohmann_json_t.v1 = !nlohmann_json_j.is_null() ? nlohmann_json_j.value(#v1, nlohmann_json_default_obj.v1) : nlohmann_json_default_obj.v1; + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_INTRUSIVE +@since version 3.9.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_type_intrusive/ +*/ +#define NLOHMANN_DEFINE_TYPE_INTRUSIVE(Type, ...) \ + template::value, int> = 0> \ + friend void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + friend void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_INTRUSIVE_WITH_DEFAULT +@since version 3.11.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_type_intrusive/ +*/ +#define NLOHMANN_DEFINE_TYPE_INTRUSIVE_WITH_DEFAULT(Type, ...) \ + template::value, int> = 0> \ + friend void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + friend void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { const Type nlohmann_json_default_obj{}; NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM_WITH_DEFAULT, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_INTRUSIVE_ONLY_SERIALIZE +@since version 3.11.3 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_type_intrusive/ +*/ +#define NLOHMANN_DEFINE_TYPE_INTRUSIVE_ONLY_SERIALIZE(Type, ...) \ + template::value, int> = 0> \ + friend void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE +@since version 3.9.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_type_non_intrusive/ +*/ +#define NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE(Type, ...) \ + template::value, int> = 0> \ + void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE_WITH_DEFAULT +@since version 3.11.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_type_non_intrusive/ +*/ +#define NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE_WITH_DEFAULT(Type, ...) \ + template::value, int> = 0> \ + void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { const Type nlohmann_json_default_obj{}; NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM_WITH_DEFAULT, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE_ONLY_SERIALIZE +@since version 3.11.3 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_type_non_intrusive/ +*/ +#define NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE_ONLY_SERIALIZE(Type, ...) \ + template::value, int> = 0> \ + void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_DERIVED_TYPE_INTRUSIVE +@since version 3.12.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_derived_type/ +*/ +#define NLOHMANN_DEFINE_DERIVED_TYPE_INTRUSIVE(Type, BaseType, ...) \ + template::value, int> = 0> \ + friend void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { nlohmann::to_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + friend void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { nlohmann::from_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_DERIVED_TYPE_INTRUSIVE_WITH_DEFAULT +@since version 3.12.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_derived_type/ +*/ +#define NLOHMANN_DEFINE_DERIVED_TYPE_INTRUSIVE_WITH_DEFAULT(Type, BaseType, ...) \ + template::value, int> = 0> \ + friend void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { nlohmann::to_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + friend void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { nlohmann::from_json(nlohmann_json_j, static_cast(nlohmann_json_t)); const Type nlohmann_json_default_obj{}; NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM_WITH_DEFAULT, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_DERIVED_TYPE_INTRUSIVE_ONLY_SERIALIZE +@since version 3.12.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_derived_type/ +*/ +#define NLOHMANN_DEFINE_DERIVED_TYPE_INTRUSIVE_ONLY_SERIALIZE(Type, BaseType, ...) \ + template::value, int> = 0> \ + friend void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { nlohmann::to_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_DERIVED_TYPE_NON_INTRUSIVE +@since version 3.12.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_derived_type/ +*/ +#define NLOHMANN_DEFINE_DERIVED_TYPE_NON_INTRUSIVE(Type, BaseType, ...) \ + template::value, int> = 0> \ + void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { nlohmann::to_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { nlohmann::from_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_DERIVED_TYPE_NON_INTRUSIVE_WITH_DEFAULT +@since version 3.12.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_derived_type/ +*/ +#define NLOHMANN_DEFINE_DERIVED_TYPE_NON_INTRUSIVE_WITH_DEFAULT(Type, BaseType, ...) \ + template::value, int> = 0> \ + void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { nlohmann::to_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + template::value, int> = 0> \ + void from_json(const BasicJsonType& nlohmann_json_j, Type& nlohmann_json_t) { nlohmann::from_json(nlohmann_json_j, static_cast(nlohmann_json_t)); const Type nlohmann_json_default_obj{}; NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM_WITH_DEFAULT, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_DERIVED_TYPE_NON_INTRUSIVE_ONLY_SERIALIZE +@since version 3.12.0 +@sa https://json.nlohmann.me/api/macros/nlohmann_define_derived_type/ +*/ +#define NLOHMANN_DEFINE_DERIVED_TYPE_NON_INTRUSIVE_ONLY_SERIALIZE(Type, BaseType, ...) \ + template::value, int> = 0> \ + void to_json(BasicJsonType& nlohmann_json_j, const Type& nlohmann_json_t) { nlohmann::to_json(nlohmann_json_j, static_cast(nlohmann_json_t)); NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } + +// inspired from https://stackoverflow.com/a/26745591 +// allows calling any std function as if (e.g., with begin): +// using std::begin; begin(x); +// +// it allows using the detected idiom to retrieve the return type +// of such an expression +#define NLOHMANN_CAN_CALL_STD_FUNC_IMPL(std_name) \ + namespace detail { \ + using std::std_name; \ + \ + template \ + using result_of_##std_name = decltype(std_name(std::declval()...)); \ + } \ + \ + namespace detail2 { \ + struct std_name##_tag \ + { \ + }; \ + \ + template \ + std_name##_tag std_name(T&&...); \ + \ + template \ + using result_of_##std_name = decltype(std_name(std::declval()...)); \ + \ + template \ + struct would_call_std_##std_name \ + { \ + static constexpr auto const value = ::nlohmann::detail:: \ + is_detected_exact::value; \ + }; \ + } /* namespace detail2 */ \ + \ + template \ + struct would_call_std_##std_name : detail2::would_call_std_##std_name \ + { \ + } + +#ifndef JSON_USE_IMPLICIT_CONVERSIONS + #define JSON_USE_IMPLICIT_CONVERSIONS 1 +#endif + +#if JSON_USE_IMPLICIT_CONVERSIONS + #define JSON_EXPLICIT +#else + #define JSON_EXPLICIT explicit +#endif + +#ifndef JSON_DISABLE_ENUM_SERIALIZATION + #define JSON_DISABLE_ENUM_SERIALIZATION 0 +#endif + +#ifndef JSON_USE_GLOBAL_UDLS + #define JSON_USE_GLOBAL_UDLS 1 +#endif + +#if JSON_HAS_THREE_WAY_COMPARISON + #include // partial_ordering +#endif + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +/////////////////////////// +// JSON type enumeration // +/////////////////////////// + +/*! +@brief the JSON type enumeration + +This enumeration collects the different JSON types. It is internally used to +distinguish the stored values, and the functions @ref basic_json::is_null(), +@ref basic_json::is_object(), @ref basic_json::is_array(), +@ref basic_json::is_string(), @ref basic_json::is_boolean(), +@ref basic_json::is_number() (with @ref basic_json::is_number_integer(), +@ref basic_json::is_number_unsigned(), and @ref basic_json::is_number_float()), +@ref basic_json::is_discarded(), @ref basic_json::is_primitive(), and +@ref basic_json::is_structured() rely on it. + +@note There are three enumeration entries (number_integer, number_unsigned, and +number_float), because the library distinguishes these three types for numbers: +@ref basic_json::number_unsigned_t is used for unsigned integers, +@ref basic_json::number_integer_t is used for signed integers, and +@ref basic_json::number_float_t is used for floating-point numbers or to +approximate integers which do not fit in the limits of their respective type. + +@sa see @ref basic_json::basic_json(const value_t value_type) -- create a JSON +value with the default value for a given type + +@since version 1.0.0 +*/ +enum class value_t : std::uint8_t +{ + null, ///< null value + object, ///< object (unordered set of name/value pairs) + array, ///< array (ordered collection of values) + string, ///< string value + boolean, ///< boolean value + number_integer, ///< number value (signed integer) + number_unsigned, ///< number value (unsigned integer) + number_float, ///< number value (floating-point) + binary, ///< binary array (ordered collection of bytes) + discarded ///< discarded by the parser callback function +}; + +/*! +@brief comparison operator for JSON types + +Returns an ordering that is similar to Python: +- order: null < boolean < number < object < array < string < binary +- furthermore, each type is not smaller than itself +- discarded values are not comparable +- binary is represented as a b"" string in python and directly comparable to a + string; however, making a binary array directly comparable with a string would + be surprising behavior in a JSON file. + +@since version 1.0.0 +*/ +#if JSON_HAS_THREE_WAY_COMPARISON + inline std::partial_ordering operator<=>(const value_t lhs, const value_t rhs) noexcept // *NOPAD* +#else + inline bool operator<(const value_t lhs, const value_t rhs) noexcept +#endif +{ + static constexpr std::array order = {{ + 0 /* null */, 3 /* object */, 4 /* array */, 5 /* string */, + 1 /* boolean */, 2 /* integer */, 2 /* unsigned */, 2 /* float */, + 6 /* binary */ + } + }; + + const auto l_index = static_cast(lhs); + const auto r_index = static_cast(rhs); +#if JSON_HAS_THREE_WAY_COMPARISON + if (l_index < order.size() && r_index < order.size()) + { + return order[l_index] <=> order[r_index]; // *NOPAD* + } + return std::partial_ordering::unordered; +#else + return l_index < order.size() && r_index < order.size() && order[l_index] < order[r_index]; +#endif +} + +// GCC selects the built-in operator< over an operator rewritten from +// a user-defined spaceship operator +// Clang, MSVC, and ICC select the rewritten candidate +// (see GCC bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105200) +#if JSON_HAS_THREE_WAY_COMPARISON && defined(__GNUC__) +inline bool operator<(const value_t lhs, const value_t rhs) noexcept +{ + return std::is_lt(lhs <=> rhs); // *NOPAD* +} +#endif + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +/*! +@brief replace all occurrences of a substring by another string + +@param[in,out] s the string to manipulate; changed so that all + occurrences of @a f are replaced with @a t +@param[in] f the substring to replace with @a t +@param[in] t the string to replace @a f + +@pre The search string @a f must not be empty. **This precondition is +enforced with an assertion.** + +@since version 2.0.0 +*/ +template +inline void replace_substring(StringType& s, const StringType& f, + const StringType& t) +{ + JSON_ASSERT(!f.empty()); + for (auto pos = s.find(f); // find first occurrence of f + pos != StringType::npos; // make sure f was found + s.replace(pos, f.size(), t), // replace with t, and + pos = s.find(f, pos + t.size())) // find next occurrence of f + {} +} + +/*! + * @brief string escaping as described in RFC 6901 (Sect. 4) + * @param[in] s string to escape + * @return escaped string + * + * Note the order of escaping "~" to "~0" and "/" to "~1" is important. + */ +template +inline StringType escape(StringType s) +{ + replace_substring(s, StringType{"~"}, StringType{"~0"}); + replace_substring(s, StringType{"/"}, StringType{"~1"}); + return s; +} + +/*! + * @brief string unescaping as described in RFC 6901 (Sect. 4) + * @param[in] s string to unescape + * @return unescaped string + * + * Note the order of escaping "~1" to "/" and "~0" to "~" is important. + */ +template +static void unescape(StringType& s) +{ + replace_substring(s, StringType{"~1"}, StringType{"/"}); + replace_substring(s, StringType{"~0"}, StringType{"~"}); +} + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // size_t + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +/// struct to capture the start position of the current token +struct position_t +{ + /// the total number of characters read + std::size_t chars_read_total = 0; + /// the number of characters read in the current line + std::size_t chars_read_current_line = 0; + /// the number of lines read + std::size_t lines_read = 0; + + /// conversion to size_t to preserve SAX interface + constexpr operator size_t() const + { + return chars_read_total; + } +}; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-FileCopyrightText: 2018 The Abseil Authors +// SPDX-License-Identifier: MIT + + + +#include // array +#include // size_t +#include // conditional, enable_if, false_type, integral_constant, is_constructible, is_integral, is_same, remove_cv, remove_reference, true_type +#include // index_sequence, make_index_sequence, index_sequence_for + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +template +using uncvref_t = typename std::remove_cv::type>::type; + +#ifdef JSON_HAS_CPP_14 + +// the following utilities are natively available in C++14 +using std::enable_if_t; +using std::index_sequence; +using std::make_index_sequence; +using std::index_sequence_for; + +#else + +// alias templates to reduce boilerplate +template +using enable_if_t = typename std::enable_if::type; + +// The following code is taken from https://github.com/abseil/abseil-cpp/blob/10cb35e459f5ecca5b2ff107635da0bfa41011b4/absl/utility/utility.h +// which is part of Google Abseil (https://github.com/abseil/abseil-cpp), licensed under the Apache License 2.0. + +//// START OF CODE FROM GOOGLE ABSEIL + +// integer_sequence +// +// Class template representing a compile-time integer sequence. An instantiation +// of `integer_sequence` has a sequence of integers encoded in its +// type through its template arguments (which is a common need when +// working with C++11 variadic templates). `absl::integer_sequence` is designed +// to be a drop-in replacement for C++14's `std::integer_sequence`. +// +// Example: +// +// template< class T, T... Ints > +// void user_function(integer_sequence); +// +// int main() +// { +// // user_function's `T` will be deduced to `int` and `Ints...` +// // will be deduced to `0, 1, 2, 3, 4`. +// user_function(make_integer_sequence()); +// } +template +struct integer_sequence +{ + using value_type = T; + static constexpr std::size_t size() noexcept + { + return sizeof...(Ints); + } +}; + +// index_sequence +// +// A helper template for an `integer_sequence` of `size_t`, +// `absl::index_sequence` is designed to be a drop-in replacement for C++14's +// `std::index_sequence`. +template +using index_sequence = integer_sequence; + +namespace utility_internal +{ + +template +struct Extend; + +// Note that SeqSize == sizeof...(Ints). It's passed explicitly for efficiency. +template +struct Extend, SeqSize, 0> +{ + using type = integer_sequence < T, Ints..., (Ints + SeqSize)... >; +}; + +template +struct Extend, SeqSize, 1> +{ + using type = integer_sequence < T, Ints..., (Ints + SeqSize)..., 2 * SeqSize >; +}; + +// Recursion helper for 'make_integer_sequence'. +// 'Gen::type' is an alias for 'integer_sequence'. +template +struct Gen +{ + using type = + typename Extend < typename Gen < T, N / 2 >::type, N / 2, N % 2 >::type; +}; + +template +struct Gen +{ + using type = integer_sequence; +}; + +} // namespace utility_internal + +// Compile-time sequences of integers + +// make_integer_sequence +// +// This template alias is equivalent to +// `integer_sequence`, and is designed to be a drop-in +// replacement for C++14's `std::make_integer_sequence`. +template +using make_integer_sequence = typename utility_internal::Gen::type; + +// make_index_sequence +// +// This template alias is equivalent to `index_sequence<0, 1, ..., N-1>`, +// and is designed to be a drop-in replacement for C++14's +// `std::make_index_sequence`. +template +using make_index_sequence = make_integer_sequence; + +// index_sequence_for +// +// Converts a typename pack into an index sequence of the same length, and +// is designed to be a drop-in replacement for C++14's +// `std::index_sequence_for()` +template +using index_sequence_for = make_index_sequence; + +//// END OF CODE FROM GOOGLE ABSEIL + +#endif + +// dispatch utility (taken from ranges-v3) +template struct priority_tag : priority_tag < N - 1 > {}; +template<> struct priority_tag<0> {}; + +// taken from ranges-v3 +template +struct static_const +{ + static JSON_INLINE_VARIABLE constexpr T value{}; +}; + +#ifndef JSON_HAS_CPP_17 + template + constexpr T static_const::value; +#endif + +template +constexpr std::array make_array(Args&& ... args) +{ + return std::array {{static_cast(std::forward(args))...}}; +} + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // numeric_limits +#include // char_traits +#include // tuple +#include // false_type, is_constructible, is_integral, is_same, true_type +#include // declval + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // random_access_iterator_tag + +// #include + +// #include + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +template +struct iterator_types {}; + +template +struct iterator_types < + It, + void_t> +{ + using difference_type = typename It::difference_type; + using value_type = typename It::value_type; + using pointer = typename It::pointer; + using reference = typename It::reference; + using iterator_category = typename It::iterator_category; +}; + +// This is required as some compilers implement std::iterator_traits in a way that +// doesn't work with SFINAE. See https://github.com/nlohmann/json/issues/1341. +template +struct iterator_traits +{ +}; + +template +struct iterator_traits < T, enable_if_t < !std::is_pointer::value >> + : iterator_types +{ +}; + +template +struct iterator_traits::value>> +{ + using iterator_category = std::random_access_iterator_tag; + using value_type = T; + using difference_type = ptrdiff_t; + using pointer = T*; + using reference = T&; +}; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN + +NLOHMANN_CAN_CALL_STD_FUNC_IMPL(begin); + +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN + +NLOHMANN_CAN_CALL_STD_FUNC_IMPL(end); + +NLOHMANN_JSON_NAMESPACE_END + +// #include + +// #include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.12.0 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013 - 2025 Niels Lohmann +// SPDX-License-Identifier: MIT + +#ifndef INCLUDE_NLOHMANN_JSON_FWD_HPP_ + #define INCLUDE_NLOHMANN_JSON_FWD_HPP_ + + #include // int64_t, uint64_t + #include // map + #include // allocator + #include // string + #include // vector + + // #include + + + /*! + @brief namespace for Niels Lohmann + @see https://github.com/nlohmann + @since version 1.0.0 + */ + NLOHMANN_JSON_NAMESPACE_BEGIN + + /*! + @brief default JSONSerializer template argument + + This serializer ignores the template arguments and uses ADL + ([argument-dependent lookup](https://en.cppreference.com/w/cpp/language/adl)) + for serialization. + */ + template + struct adl_serializer; + + /// a class to store JSON values + /// @sa https://json.nlohmann.me/api/basic_json/ + template class ObjectType = + std::map, + template class ArrayType = std::vector, + class StringType = std::string, class BooleanType = bool, + class NumberIntegerType = std::int64_t, + class NumberUnsignedType = std::uint64_t, + class NumberFloatType = double, + template class AllocatorType = std::allocator, + template class JSONSerializer = + adl_serializer, + class BinaryType = std::vector, // cppcheck-suppress syntaxError + class CustomBaseClass = void> + class basic_json; + + /// @brief JSON Pointer defines a string syntax for identifying a specific value within a JSON document + /// @sa https://json.nlohmann.me/api/json_pointer/ + template + class json_pointer; + + /*! + @brief default specialization + @sa https://json.nlohmann.me/api/json/ + */ + using json = basic_json<>; + + /// @brief a minimal map-like container that preserves insertion order + /// @sa https://json.nlohmann.me/api/ordered_map/ + template + struct ordered_map; + + /// @brief specialization that maintains the insertion order of object keys + /// @sa https://json.nlohmann.me/api/ordered_json/ + using ordered_json = basic_json; + + NLOHMANN_JSON_NAMESPACE_END + +#endif // INCLUDE_NLOHMANN_JSON_FWD_HPP_ + + +NLOHMANN_JSON_NAMESPACE_BEGIN +/*! +@brief detail namespace with internal helper functions + +This namespace collects functions that should not be exposed, +implementations of some @ref basic_json methods, and meta-programming helpers. + +@since version 2.1.0 +*/ +namespace detail +{ + +///////////// +// helpers // +///////////// + +// Note to maintainers: +// +// Every trait in this file expects a non CV-qualified type. +// The only exceptions are in the 'aliases for detected' section +// (i.e. those of the form: decltype(T::member_function(std::declval()))) +// +// In this case, T has to be properly CV-qualified to constraint the function arguments +// (e.g. to_json(BasicJsonType&, const T&)) + +template struct is_basic_json : std::false_type {}; + +NLOHMANN_BASIC_JSON_TPL_DECLARATION +struct is_basic_json : std::true_type {}; + +// used by exceptions create() member functions +// true_type for pointer to possibly cv-qualified basic_json or std::nullptr_t +// false_type otherwise +template +struct is_basic_json_context : + std::integral_constant < bool, + is_basic_json::type>::type>::value + || std::is_same::value > +{}; + +////////////////////// +// json_ref helpers // +////////////////////// + +template +class json_ref; + +template +struct is_json_ref : std::false_type {}; + +template +struct is_json_ref> : std::true_type {}; + +////////////////////////// +// aliases for detected // +////////////////////////// + +template +using mapped_type_t = typename T::mapped_type; + +template +using key_type_t = typename T::key_type; + +template +using value_type_t = typename T::value_type; + +template +using difference_type_t = typename T::difference_type; + +template +using pointer_t = typename T::pointer; + +template +using reference_t = typename T::reference; + +template +using iterator_category_t = typename T::iterator_category; + +template +using to_json_function = decltype(T::to_json(std::declval()...)); + +template +using from_json_function = decltype(T::from_json(std::declval()...)); + +template +using get_template_function = decltype(std::declval().template get()); + +// trait checking if JSONSerializer::from_json(json const&, udt&) exists +template +struct has_from_json : std::false_type {}; + +// trait checking if j.get is valid +// use this trait instead of std::is_constructible or std::is_convertible, +// both rely on, or make use of implicit conversions, and thus fail when T +// has several constructors/operator= (see https://github.com/nlohmann/json/issues/958) +template +struct is_getable +{ + static constexpr bool value = is_detected::value; +}; + +template +struct has_from_json < BasicJsonType, T, enable_if_t < !is_basic_json::value >> +{ + using serializer = typename BasicJsonType::template json_serializer; + + static constexpr bool value = + is_detected_exact::value; +}; + +// This trait checks if JSONSerializer::from_json(json const&) exists +// this overload is used for non-default-constructible user-defined-types +template +struct has_non_default_from_json : std::false_type {}; + +template +struct has_non_default_from_json < BasicJsonType, T, enable_if_t < !is_basic_json::value >> +{ + using serializer = typename BasicJsonType::template json_serializer; + + static constexpr bool value = + is_detected_exact::value; +}; + +// This trait checks if BasicJsonType::json_serializer::to_json exists +// Do not evaluate the trait when T is a basic_json type, to avoid template instantiation infinite recursion. +template +struct has_to_json : std::false_type {}; + +template +struct has_to_json < BasicJsonType, T, enable_if_t < !is_basic_json::value >> +{ + using serializer = typename BasicJsonType::template json_serializer; + + static constexpr bool value = + is_detected_exact::value; +}; + +template +using detect_key_compare = typename T::key_compare; + +template +struct has_key_compare : std::integral_constant::value> {}; + +// obtains the actual object key comparator +template +struct actual_object_comparator +{ + using object_t = typename BasicJsonType::object_t; + using object_comparator_t = typename BasicJsonType::default_object_comparator_t; + using type = typename std::conditional < has_key_compare::value, + typename object_t::key_compare, object_comparator_t>::type; +}; + +template +using actual_object_comparator_t = typename actual_object_comparator::type; + +///////////////// +// char_traits // +///////////////// + +// Primary template of char_traits calls std char_traits +template +struct char_traits : std::char_traits +{}; + +// Explicitly define char traits for unsigned char since it is not standard +template<> +struct char_traits : std::char_traits +{ + using char_type = unsigned char; + using int_type = uint64_t; + + // Redefine to_int_type function + static int_type to_int_type(char_type c) noexcept + { + return static_cast(c); + } + + static char_type to_char_type(int_type i) noexcept + { + return static_cast(i); + } + + static constexpr int_type eof() noexcept + { + return static_cast(std::char_traits::eof()); + } +}; + +// Explicitly define char traits for signed char since it is not standard +template<> +struct char_traits : std::char_traits +{ + using char_type = signed char; + using int_type = uint64_t; + + // Redefine to_int_type function + static int_type to_int_type(char_type c) noexcept + { + return static_cast(c); + } + + static char_type to_char_type(int_type i) noexcept + { + return static_cast(i); + } + + static constexpr int_type eof() noexcept + { + return static_cast(std::char_traits::eof()); + } +}; + +/////////////////// +// is_ functions // +/////////////////// + +// https://en.cppreference.com/w/cpp/types/conjunction +template struct conjunction : std::true_type { }; +template struct conjunction : B { }; +template +struct conjunction +: std::conditional(B::value), conjunction, B>::type {}; + +// https://en.cppreference.com/w/cpp/types/negation +template struct negation : std::integral_constant < bool, !B::value > { }; + +// Reimplementation of is_constructible and is_default_constructible, due to them being broken for +// std::pair and std::tuple until LWG 2367 fix (see https://cplusplus.github.io/LWG/lwg-defects.html#2367). +// This causes compile errors in e.g. clang 3.5 or gcc 4.9. +template +struct is_default_constructible : std::is_default_constructible {}; + +template +struct is_default_constructible> + : conjunction, is_default_constructible> {}; + +template +struct is_default_constructible> + : conjunction, is_default_constructible> {}; + +template +struct is_default_constructible> + : conjunction...> {}; + +template +struct is_default_constructible> + : conjunction...> {}; + +template +struct is_constructible : std::is_constructible {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_iterator_traits : std::false_type {}; + +template +struct is_iterator_traits> +{ + private: + using traits = iterator_traits; + + public: + static constexpr auto value = + is_detected::value && + is_detected::value && + is_detected::value && + is_detected::value && + is_detected::value; +}; + +template +struct is_range +{ + private: + using t_ref = typename std::add_lvalue_reference::type; + + using iterator = detected_t; + using sentinel = detected_t; + + // to be 100% correct, it should use https://en.cppreference.com/w/cpp/iterator/input_or_output_iterator + // and https://en.cppreference.com/w/cpp/iterator/sentinel_for + // but reimplementing these would be too much work, as a lot of other concepts are used underneath + static constexpr auto is_iterator_begin = + is_iterator_traits>::value; + + public: + static constexpr bool value = !std::is_same::value && !std::is_same::value && is_iterator_begin; +}; + +template +using iterator_t = enable_if_t::value, result_of_begin())>>; + +template +using range_value_t = value_type_t>>; + +// The following implementation of is_complete_type is taken from +// https://blogs.msdn.microsoft.com/vcblog/2015/12/02/partial-support-for-expression-sfinae-in-vs-2015-update-1/ +// and is written by Xiang Fan who agreed to using it in this library. + +template +struct is_complete_type : std::false_type {}; + +template +struct is_complete_type : std::true_type {}; + +template +struct is_compatible_object_type_impl : std::false_type {}; + +template +struct is_compatible_object_type_impl < + BasicJsonType, CompatibleObjectType, + enable_if_t < is_detected::value&& + is_detected::value >> +{ + using object_t = typename BasicJsonType::object_t; + + // macOS's is_constructible does not play well with nonesuch... + static constexpr bool value = + is_constructible::value && + is_constructible::value; +}; + +template +struct is_compatible_object_type + : is_compatible_object_type_impl {}; + +template +struct is_constructible_object_type_impl : std::false_type {}; + +template +struct is_constructible_object_type_impl < + BasicJsonType, ConstructibleObjectType, + enable_if_t < is_detected::value&& + is_detected::value >> +{ + using object_t = typename BasicJsonType::object_t; + + static constexpr bool value = + (is_default_constructible::value && + (std::is_move_assignable::value || + std::is_copy_assignable::value) && + (is_constructible::value && + std::is_same < + typename object_t::mapped_type, + typename ConstructibleObjectType::mapped_type >::value)) || + (has_from_json::value || + has_non_default_from_json < + BasicJsonType, + typename ConstructibleObjectType::mapped_type >::value); +}; + +template +struct is_constructible_object_type + : is_constructible_object_type_impl {}; + +template +struct is_compatible_string_type +{ + static constexpr auto value = + is_constructible::value; +}; + +template +struct is_constructible_string_type +{ + // launder type through decltype() to fix compilation failure on ICPC +#ifdef __INTEL_COMPILER + using laundered_type = decltype(std::declval()); +#else + using laundered_type = ConstructibleStringType; +#endif + + static constexpr auto value = + conjunction < + is_constructible, + is_detected_exact>::value; +}; + +template +struct is_compatible_array_type_impl : std::false_type {}; + +template +struct is_compatible_array_type_impl < + BasicJsonType, CompatibleArrayType, + enable_if_t < + is_detected::value&& + is_iterator_traits>>::value&& +// special case for types like std::filesystem::path whose iterator's value_type are themselves +// c.f. https://github.com/nlohmann/json/pull/3073 + !std::is_same>::value >> +{ + static constexpr bool value = + is_constructible>::value; +}; + +template +struct is_compatible_array_type + : is_compatible_array_type_impl {}; + +template +struct is_constructible_array_type_impl : std::false_type {}; + +template +struct is_constructible_array_type_impl < + BasicJsonType, ConstructibleArrayType, + enable_if_t::value >> + : std::true_type {}; + +template +struct is_constructible_array_type_impl < + BasicJsonType, ConstructibleArrayType, + enable_if_t < !std::is_same::value&& + !is_compatible_string_type::value&& + is_default_constructible::value&& +(std::is_move_assignable::value || + std::is_copy_assignable::value)&& +is_detected::value&& +is_iterator_traits>>::value&& +is_detected::value&& +// special case for types like std::filesystem::path whose iterator's value_type are themselves +// c.f. https://github.com/nlohmann/json/pull/3073 +!std::is_same>::value&& +is_complete_type < +detected_t>::value >> +{ + using value_type = range_value_t; + + static constexpr bool value = + std::is_same::value || + has_from_json::value || + has_non_default_from_json < + BasicJsonType, + value_type >::value; +}; + +template +struct is_constructible_array_type + : is_constructible_array_type_impl {}; + +template +struct is_compatible_integer_type_impl : std::false_type {}; + +template +struct is_compatible_integer_type_impl < + RealIntegerType, CompatibleNumberIntegerType, + enable_if_t < std::is_integral::value&& + std::is_integral::value&& + !std::is_same::value >> +{ + // is there an assert somewhere on overflows? + using RealLimits = std::numeric_limits; + using CompatibleLimits = std::numeric_limits; + + static constexpr auto value = + is_constructible::value && + CompatibleLimits::is_integer && + RealLimits::is_signed == CompatibleLimits::is_signed; +}; + +template +struct is_compatible_integer_type + : is_compatible_integer_type_impl {}; + +template +struct is_compatible_type_impl: std::false_type {}; + +template +struct is_compatible_type_impl < + BasicJsonType, CompatibleType, + enable_if_t::value >> +{ + static constexpr bool value = + has_to_json::value; +}; + +template +struct is_compatible_type + : is_compatible_type_impl {}; + +template +struct is_constructible_tuple : std::false_type {}; + +template +struct is_constructible_tuple> : conjunction...> {}; + +template +struct is_json_iterator_of : std::false_type {}; + +template +struct is_json_iterator_of : std::true_type {}; + +template +struct is_json_iterator_of : std::true_type +{}; + +// checks if a given type T is a template specialization of Primary +template