common_cells.core

CAPI=2:

name : pulp-platform.org::common_cells:2.0.0
description: Common SystemVerilog components

filesets:
  rtl:
    depend:
      - ">=pulp-platform.org::tech_cells_generic:0.2.14"
    files:
      - include/common_cells/registers.svh : {is_include_file : true, include_path : include}
      - include/common_cells/assertions.svh : {is_include_file : true, include_path : include}
      # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
      # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
      # etc. Files within a level are ordered alphabetically.
      # Level 0
      - src/assert_rpt_pkg.sv
      - src/cc_binary_to_gray.sv
      - src/cc_pkg.sv
      - src/cc_onehot.sv
      - src/cc_clk_int_div.sv
      - src/cc_clk_int_div_static.sv
      - src/cc_credit_counter.sv
      - src/cc_delta_counter.sv
      - src/cc_edge_propagator_tx.sv
      - src/cc_exp_backoff.sv
      - src/cc_fifo.sv
      - src/cc_gray_to_binary.sv
      - src/cc_heaviside.sv
      - src/cc_isochronous_4phase_handshake.sv
      - src/cc_isochronous_spill_register.sv
      - src/cc_lfsr.sv
      - src/cc_lfsr_16bit.sv
      - src/cc_lfsr_8bit.sv
      - src/cc_lossy_valid_to_stream.sv
      - src/cc_multiaddr_decode.sv
      - src/cc_onehot_to_bin.sv
      - src/cc_plru_tree.sv
      - src/cc_passthrough_stream_fifo.sv
      - src/cc_popcount.sv
      - src/cc_ring_buffer.sv
      - src/cc_rr_arb_tree.sv
      - src/cc_rstgen_bypass.sv
      - src/cc_serial_deglitch.sv
      - src/cc_shift_register.sv
      - src/cc_shift_register_gated.sv
      - src/cc_spill_register_flushable.sv
      - src/cc_stream_demux.sv
      - src/cc_stream_filter.sv
      - src/cc_stream_fork.sv
      - src/cc_stream_intf.sv
      - src/cc_stream_join.sv
      - src/cc_stream_join_dynamic.sv
      - src/cc_stream_mux.sv
      - src/cc_stream_throttle.sv
      - src/cc_sub_per_hash.sv
      - src/cc_sync_wedge.sv
      - src/cc_unread.sv
      - src/cc_read.sv
      # Level 1
      - src/cc_addr_decode_dync.sv
      - src/cc_boxcar.sv
      - src/cc_cdc_2phase.sv
      - src/cc_cdc_4phase.sv
      - src/cc_cb_filter.sv
      - src/cc_cdc_fifo_2phase.sv
      - src/cc_counter.sv
      - src/cc_ecc_decode.sv
      - src/cc_ecc_encode.sv
      - src/cc_edge_detect.sv
      - src/cc_edge_propagator_ack.sv
      - src/cc_edge_propagator_rx.sv
      - src/cc_trip_counter.sv
      - src/cc_lzc.sv
      - src/cc_majority_vote_filter.sv
      - src/cc_max_counter.sv
      - src/cc_rstgen.sv
      - src/cc_spill_register.sv
      - src/cc_stream_delay.sv
      - src/cc_stream_fifo.sv
      - src/cc_stream_fork_dynamic.sv
      - src/cc_clk_mux_glitch_free.sv
      # Level 2
      - src/cc_addr_decode.sv
      - src/cc_addr_decode_napot.sv
      - src/cc_cdc_reset_ctrlr.sv
      - src/cc_cdc_fifo_gray.sv
      - src/cc_edge_propagator.sv
      - src/cc_fall_through_register.sv
      - src/cc_id_queue.sv
      - src/cc_stream_to_mem.sv
      - src/cc_stream_arbiter.sv
      - src/cc_stream_downsizer.sv
      - src/cc_stream_fifo_optimal_wrap.sv
      - src/cc_stream_register.sv
      - src/cc_stream_upsizer.sv
      - src/cc_stream_xbar.sv
      # Level 3
      - src/cc_cdc_fifo_gray_clearable.sv
      - src/cc_cdc_2phase_clearable.sv
      - src/cc_mem_to_banks_detailed.sv
      - src/cc_stream_omega_net.sv
      # Level 4
      - src/cc_mem_to_banks.sv
    file_type : systemVerilogSource

targets:
  default:
    filesets : [rtl]
    parameters: [COMMON_CELLS_ASSERTS_OFF]

parameters:
  COMMON_CELLS_ASSERTS_OFF:
    datatype: bool
    description: Turn off asserts for PULP common cells
    paramtype: vlogdefine