|
| 1 | +from typing import List, Optional |
| 2 | + |
| 3 | +import capstone |
| 4 | +from capstone import x86_const, arm_const, arm64_const, CS_AC_READ, CS_AC_WRITE |
| 5 | +from enum import IntEnum |
| 6 | +from collections import namedtuple |
| 7 | + |
| 8 | +Reg = namedtuple("Reg", "name") |
| 9 | + |
| 10 | + |
| 11 | +class Opnd: |
| 12 | + def __init__(self, cs_op, arch): |
| 13 | + self._cs_op = cs_op |
| 14 | + self._arch = arch |
| 15 | + |
| 16 | + @property |
| 17 | + def type(self): |
| 18 | + return self._cs_op.type |
| 19 | + |
| 20 | + def is_read(self) -> bool: |
| 21 | + return bool(self._cs_op.access & CS_AC_READ) |
| 22 | + |
| 23 | + def is_written(self) -> bool: |
| 24 | + return bool(self._cs_op.access & CS_AC_WRITE) |
| 25 | + |
| 26 | + def is_register(self) -> bool: |
| 27 | + return self.type == self._arch.optypes.REG |
| 28 | + |
| 29 | + def is_memory(self) -> bool: |
| 30 | + return self.type == self._arch.optypes.MEM |
| 31 | + |
| 32 | + |
| 33 | +class Instr: |
| 34 | + def __init__(self, cs_ins, arch): |
| 35 | + self._cs_ins = cs_ins |
| 36 | + self._arch = arch |
| 37 | + |
| 38 | + @property |
| 39 | + def bytes(self): |
| 40 | + return bytes(self._cs_ins.bytes) |
| 41 | + |
| 42 | + def __str__(self): |
| 43 | + return self._cs_ins.mnemonic + " " + self._cs_ins.op_str |
| 44 | + |
| 45 | + @property |
| 46 | + def operands(self): |
| 47 | + return [Opnd(x, self._arch) for x in self._cs_ins.operands] |
| 48 | + |
| 49 | + |
| 50 | +class Arch: |
| 51 | + _CSD = None |
| 52 | + |
| 53 | + def disasm(cls, asm: bytes, addr: int) -> List[Instr]: |
| 54 | + cls._CSD.detail = True |
| 55 | + return [Instr(x, cls) for x in cls._CSD.disasm(asm, addr)] |
| 56 | + |
| 57 | + def disasm_one(cls, asm: bytes, addr: int) -> Instr: |
| 58 | + r = cls.disasm(asm, addr) |
| 59 | + return r[0] if r else None |
| 60 | + |
| 61 | + |
| 62 | + |
| 63 | +class _ArchX86(Arch): |
| 64 | + NAME = "x86" |
| 65 | + INS_PTR = Reg('eip') |
| 66 | + STK_PTR = Reg('esp') |
| 67 | + _CSD = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_32) |
| 68 | + nop_instruction = b"\x90" |
| 69 | + |
| 70 | + class optypes(IntEnum): |
| 71 | + INVALID = x86_const.X86_OP_INVALID |
| 72 | + IMM = x86_const.X86_OP_IMM |
| 73 | + REG = x86_const.X86_OP_REG |
| 74 | + MEM = x86_const.X86_OP_MEM |
| 75 | + |
| 76 | + |
| 77 | +class _ArchX64(_ArchX86): |
| 78 | + NAME = "x86_64" |
| 79 | + INS_PTR = Reg('rip') |
| 80 | + STK_PTR = Reg('rsp') |
| 81 | + _CSD = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_64) |
| 82 | + |
| 83 | + |
| 84 | + |
| 85 | +class _ArchARM(Arch): |
| 86 | + NAME = "ARM" |
| 87 | + INS_PTR = Reg('pc') |
| 88 | + STK_PTR = Reg('sp') |
| 89 | + _CSD = capstone.Cs(capstone.CS_ARCH_ARM, capstone.CS_MODE_ARM) |
| 90 | + nop_instruction = b"\x00\xf0\x20\xe3" |
| 91 | + |
| 92 | + class optypes(IntEnum): |
| 93 | + INVALID = arm_const.ARM_OP_INVALID |
| 94 | + REG = arm_const.ARM_OP_REG |
| 95 | + IMM = arm_const.ARM_OP_IMM |
| 96 | + MEM = arm_const.ARM_OP_MEM |
| 97 | + FP = arm_const.ARM_OP_FP |
| 98 | + CIMM = arm_const.ARM_OP_CIMM |
| 99 | + PIMM = arm_const.ARM_OP_PIMM |
| 100 | + SETEND = arm_const.ARM_OP_SETEND |
| 101 | + SYSREG = arm_const.ARM_OP_SYSREG |
| 102 | + |
| 103 | + |
| 104 | +class _ArchARM64(Arch): |
| 105 | + NAME = "AARCH64" |
| 106 | + INS_PTR = Reg('x28') |
| 107 | + STK_PTR = Reg('sp') |
| 108 | + _CSD = capstone.Cs(capstone.CS_ARCH_ARM64, capstone.CS_MODE_ARM) |
| 109 | + nop_instruction = b"\x1f\x20\x03\xd5" |
| 110 | + |
| 111 | + class optypes(IntEnum): |
| 112 | + INVALID = arm64_const.ARM64_OP_INVALID |
| 113 | + REG = arm64_const.ARM64_OP_REG |
| 114 | + IMM = arm64_const.ARM64_OP_IMM |
| 115 | + MEM = arm64_const.ARM64_OP_MEM |
| 116 | + FP = arm64_const.ARM64_OP_FP |
| 117 | + CIMM = arm64_const.ARM64_OP_CIMM |
| 118 | + REG_MRS = arm64_const.ARM64_OP_REG_MRS |
| 119 | + REG_MSR = arm64_const.ARM64_OP_REG_MSR |
| 120 | + PSTATE = arm64_const.ARM64_OP_PSTATE |
| 121 | + SYS = arm64_const.ARM64_OP_SYS |
| 122 | + PREFETCH = arm64_const.ARM64_OP_PREFETCH |
| 123 | + BARRIER = arm64_const.ARM64_OP_BARRIER |
| 124 | + |
| 125 | + |
| 126 | +ArchX86 = _ArchX86() |
| 127 | +ArchX64 = _ArchX64() |
| 128 | +ArchARM = _ArchARM() |
| 129 | +ArchARM64 = _ArchARM64() |
| 130 | + |
| 131 | + |
| 132 | +class ArchsManager: |
| 133 | + @staticmethod |
| 134 | + def get_supported_regs(arch: Arch) -> List[Reg]: |
| 135 | + if isinstance(arch, _ArchX64): |
| 136 | + return [Reg('RAX'), Reg('RBX'), Reg('RCX'), Reg('RDX'), Reg('RDI'), Reg('RSI'), Reg('RBP'), Reg('RSP'), |
| 137 | + Reg('RIP'), Reg('EFLAGS'), Reg('R8'), Reg('R9'), Reg('R10'), Reg('R11'), Reg('R12'), Reg('R13'), |
| 138 | + Reg('R14'), Reg('R15')] |
| 139 | + elif isinstance(arch, _ArchX86): |
| 140 | + return [Reg('EAX'), Reg('EBX'), Reg('ECX'), Reg('EDX'), Reg('EDI'), Reg('ESI'), Reg('EBP'), Reg('ESP'), Reg('EIP'), Reg('EFLAGS')] |
| 141 | + elif isinstance(arch, _ArchARM): |
| 142 | + return [Reg('R0'), Reg('R1'), Reg('R2'), Reg('R3'), Reg('R4'), Reg('R5'), Reg('R6'), Reg('R7'), Reg('R8'), |
| 143 | + Reg('R9'), Reg('R10'), Reg('R11'), Reg('R12'), Reg('R13'), Reg('R14'), Reg('R15'), Reg('CPSR')] |
| 144 | + elif isinstance(arch, _ArchARM64): |
| 145 | + return [Reg('X0'), Reg('X1'), Reg('X2'), Reg('X3'), Reg('X4'), Reg('X5'), Reg('X6'), Reg('X7'), Reg('X8'), |
| 146 | + Reg('X9'), Reg('X10'), Reg('X11'), Reg('X12'), Reg('X13'), Reg('X14'), Reg('X15'), Reg('X16'), |
| 147 | + Reg('X17'), Reg('X18'), Reg('X19'), Reg('X20'), Reg('X21'), Reg('X22'), Reg('R23'), Reg('X24'), |
| 148 | + Reg('X25'), Reg('X26'), Reg('X27'), Reg('X28'), Reg('X29'), Reg('X30')] |
| 149 | + else: |
| 150 | + assert False |
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