diff --git a/progalgxc3s.cpp b/progalgxc3s.cpp index 7c9f592..911a156 100644 --- a/progalgxc3s.cpp +++ b/progalgxc3s.cpp @@ -61,6 +61,7 @@ ProgAlgXC3S::ProgAlgXC3S(Jtag &j, int fam) case FAMILY_XC5VSXT: case FAMILY_XC5VFXT: case FAMILY_XC5VTXT: + case FAMILY_XC7: tck_len = 12; array_transfer_len = 32; break; @@ -97,14 +98,14 @@ void ProgAlgXC3S::flow_array_program(BitFile &file) { Timer timer; unsigned int i; - for(i=0; ishiftIR(ISC_PROGRAM); jtag->shiftDR(&(file.getData())[i/8],0,array_transfer_len); jtag->cycleTCK(1); if((i % (10000*array_transfer_len)) == 0) { - fprintf(stdout,"."); + fprintf(stderr,"."); fflush(stderr); } } @@ -236,11 +237,16 @@ void ProgAlgXC3S::array_program(BitFile &file) } } - /* use leagcy, as large USB transfers are faster then chunks */ + /* use legacy, as large USB transfers are faster then chunks */ flow_program_legacy(file); /*flow_array_program(file);*/ flow_disable(); + /* NOTE: Virtex7 devices do not support flow_program_legacy according + to the Xilinx IEEE 1532 files. However, my tests with flow_array_program + failed, while flow_program_legacy appears to work just fine on XC7VX690T. + (jorisvr) */ + /* Wait until device comes up */ while ((( buf[0] & 0x23) != 0x21) && (i <50)) { diff --git a/progalgxc3s.h b/progalgxc3s.h index 5f9036b..d0a56cc 100644 --- a/progalgxc3s.h +++ b/progalgxc3s.h @@ -43,6 +43,7 @@ Dmitry Teytelman [dimtey@gmail.com] 14 Jun 2006 [applied 13 Aug 2006]: #define FAMILY_XC5VLXT 0x15 #define FAMILY_XC5VSXT 0x17 #define FAMILY_XC5VFXT 0x19 +#define FAMILY_XC7 0x1b #define FAMILY_XC3SD 0x1c #define FAMILY_XC6S 0x20 #define FAMILY_XC5VTXT 0x22 diff --git a/xc3sprog.cpp b/xc3sprog.cpp index 7e754e8..6463dcb 100644 --- a/xc3sprog.cpp +++ b/xc3sprog.cpp @@ -876,7 +876,8 @@ int main(int argc, char **args) (family == FAMILY_XC5VLXT) || (family == FAMILY_XC5VSXT) || (family == FAMILY_XC5VFXT) || - (family == FAMILY_XC5VTXT) + (family == FAMILY_XC5VTXT) || + (family == FAMILY_XC7) ) return programXC3S(jtag, argc, args, verbose, reconfigure, family);