diff --git a/coverpoints/norm/Vx.yaml b/coverpoints/norm/Vx.yaml index 84d3f63bf9..e7701e69c8 100644 --- a/coverpoints/norm/Vx.yaml +++ b/coverpoints/norm/Vx.yaml @@ -10,7 +10,7 @@ normative_rule_definitions: # The number of bits in a single vector register, VLEN {ge} ELEN, which must be a # power of 2, and must be no greater than 2^16^. - name: VLEN - coverpoint: [""] + coverpoint: ["implicit"] # A small implementation supporting ELEN=32 requires only seven bits of state in # vtype: two bits for ma and ta, two bits for vsew[1:0] and three bits for @@ -18,12 +18,12 @@ normative_rule_definitions: # using the illegal 64-bit combination in vsew[1:0] without requiring an # additional storage bit to hold vill. - name: vill_implicit_encoding - coverpoint: [""] + coverpoint: ["implicit"] # Implementations may also change mstatus.VS or vsstatus.VS from Initial or Clean # to Dirty at any time, even when there is no change in vector state. - name: hw_mstatus_vs_dirty_update - coverpoint: [""] + coverpoint: ["untestable"] # Implementations may set vill in either case. - name: reserved_vill_set @@ -32,103 +32,149 @@ normative_rule_definitions: # The vector extension adds 32 architectural vector registers, v0-v31 to the base # scalar RISC-V ISA. - name: vreg_count - coverpoint: [""] + coverpoint: + [ + "Vf16_vfmv_f_s_cg/cp_custom_fmv_fs_vs2_all_lmul_regs", + "Vf16_vfadd_vf_cg/cp_vd", + "Vf16_vfadd_vv_cg/cp_vs1", + "Vf16_vfadd_vv_cg/cmp_vd_vs1_vs2", + "Vls16_vs1r_v_cg/cp_vs3", + "Vls16_vsoxei16_v_cg/cmp_vs3_vs2", + "Vf16_vfadd_vf_cg/cp_vs2", + "Vf16_vfadd_vv_cg/cmp_vs1_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # A vector context status field, VS, is added to mstatus[10:9] and shadowed in # sstatus[10:9]. It is defined analogously to the floating-point context status # field, FS. - name: mstatus-vs_op - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # When mstatus.VS is set to Initial or Clean, executing any instruction that # changes vector state, including the vector CSRs, will change mstatus.VS to # Dirty. Implementations may also change mstatus.VS from Initial or Clean to Dirty # at any time, even when there is no change in vector state. - name: mstatus_vs_op_initial_clean - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + "Vf16_vfmv_f_s_cg/cp_custom_vfp_register_state_mstatus_dirty", + "SmV_cg/cp_mstatus_vs_set_dirty_arithmetic", + "SmV_cg/cp_mstatus_vs_set_dirty_csr", + ] # When V=1, both vsstatus.VS and mstatus.VS are in effect: attempts to execute any # vector instruction, or to access the vector CSRs, raise an illegal-instruction # exception when either field is set to Off. - name: vsstatus-vs_mstatus_vs_op_off - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # When the hypervisor extension is present, a vector context status field, VS, is # added to vsstatus[10:9]. It is defined analogously to the floating-point context # status field, FS. - names: [vsstatus_vs_sz, vsstatus_vs_acc] - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # Attempts to execute any vector instruction, or to access the vector CSRs, raise # an illegal-instruction exception when mstatus.VS is set to Off. - name: mstatus_vs_op_off - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # When V=1 and neither vsstatus.VS nor mstatus.VS is set to Off, executing any # instruction that changes vector state, including the vector CSRs, will change # both mstatus.VS and vsstatus.VS to Dirty. - name: mstatus_vs_op_active - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # A vector context status field, VS, is added to mstatus[10:9] and shadowed in # sstatus[10:9]. It is defined analogously to the floating-point context status # field, FS. - name: sstatus_vs_op - coverpoint: [""] + coverpoint: ["untestable"] # Similarly, when V=1, both vsstatus.VS and the HS-level sstatus.VS are in effect. # Attempts to execute a vector instruction when either field is 0 (Off) raise an # illegal-instruction exception. Modifying the vector state when V=1 causes both # fields to be set to 3 (Dirty). - name: vsstatus_vs_op2 - coverpoint: [""] + coverpoint: ["untestable"] # When V=1, both vsstatus.VS and mstatus.VS are in effect: attempts to execute any # vector instruction, or to access the vector CSRs, raise an illegal-instruction # exception when either field is set to Off. - name: vsstatus_vs_op_off - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # When V=1 and neither vsstatus.VS nor mstatus.VS is set to Off, executing any # instruction that changes vector state, including the vector CSRs, will change # both mstatus.VS and vsstatus.VS to Dirty. - name: vsstatus_vs_op_active - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # If vsstatus.VS is Dirty, vsstatus.SD is 1; otherwise, vsstatus.SD is set in # accordance with existing specifications. - name: vsstatus_sd_op_vs - coverpoint: [""] + coverpoint: ["untestable"] # If mstatus.VS is Dirty, mstatus.SD is 1; otherwise, mstatus.SD is set in # accordance with existing specifications. - name: mstatus-sd_op - coverpoint: [""] + coverpoint: ["untestable"] # If mstatus.VS is Dirty, mstatus.SD is 1; otherwise, mstatus.SD is set in # accordance with existing specifications. - name: mstatus_sd_op_vs - coverpoint: [""] + coverpoint: ["untestable"] # Implementations may have a writable misa.V field. - name: mutable_misa_v - coverpoint: [""] + coverpoint: ["SmV_cg/cp_misa_v_clear_set"] # Analogous to the way in which the floating-point unit is handled, the mstatus.VS # field may exist even if misa.V is clear. - name: mstatus_vs_exists - coverpoint: [""] + coverpoint: ["untestable"] # For implementations with a writable misa.V field, the vsstatus.VS field may # exist even if misa.V is clear. - name: vsstatus_vs_exists - coverpoint: [""] + coverpoint: ["untestable"] # The read-only XLEN-wide vector type CSR, vtype provides the default type used to # interpret the contents of the vector register file, and can only be updated by # vset{i}vl{i} instructions. - names: [vtype_sz, vtype_op] - coverpoint: [""] + coverpoint: ["SmV_cg/cp_sew_lmul_vset_i_vli", "SmV_cg/cp_sew_lmul_vsetvl"] # The vtype register has five fields, vill, vma, vta, vsew[2:0], and vlmul[2:0]. # Bits vtype[XLEN-2:8] should be written with zero, and non-zero values in this @@ -140,7 +186,8 @@ normative_rule_definitions: # The value in vsew sets the dynamic selected element width (SEW). By default, a # vector register is viewed as being divided into VLEN/SEW elements. - name: vtype_vsew_op - coverpoint: [""] + coverpoint: + ["SmV_cg/cp_sew_lmul_vset_i_vli", "Vf16_vfadd_vf_cg/cr_vl_lmul_sew16"] # While it is anticipated the larger vsew[2:0] encodings (100-111) will be used to # encode larger SEW, the encodings are formally reserved at this point. @@ -149,7 +196,8 @@ normative_rule_definitions: # Implementations must support LMUL integer values of 1, 2, 4, and 8. - name: vtype_lmul_val - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cr_vl_lmul_sew16", "SmV_cg/cp_sew_lmul_vset_i_vli"] # Implementations must provide fractional LMUL settings that allow the narrowest # supported type to occupy a fraction of a vector register corresponding to the @@ -161,75 +209,115 @@ normative_rule_definitions: # supported. For standard vector extensions with ELEN=64, fractional LMULs of 1/2, # 1/4, and 1/8 must be supported. - name: vtype_lmul_fval - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cr_vl_lmul_sew16", "SmV_cg/cp_sew_lmul_vset_i_vli"] # For a given supported fractional LMUL setting, implementations must support SEW # settings between SEWMIN and LMUL * ELEN, inclusive. - name: vtype_sew_val - coverpoint: [""] + coverpoint: ["SmV_cg/cp_sew_lmul_vset_i_vli"] # The use of vtype encodings with LMUL < SEWMIN/ELEN is reserved, but # implementations can set vill if they do not support these configurations. - name: vtype_lmul_fval_rsv - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vtype_vill_set_vl_0"] # LMUL is set by the signed vlmul field in vtype (i.e., LMUL = 2vlmul[2:0]). - name: LMUL - coverpoint: [""] + coverpoint: + [ + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_lmul", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + ] # The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of # elements that can be operated on with a single vector instruction given the # current SEW and LMUL settings as shown in the table below. - name: VLMAX - coverpoint: [""] + coverpoint: + [ + "Vx16_vmadc_vi_cg/cp_custom_vmask_write_lmulge1", + "Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_ge_vlmax", + "Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_gt_vl_lt_vlmax", + "Vf16_vfadd_vf_cg/cp_masking_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + ] # Instructions specifying an LMUL=2 vector register group with an odd-numbered # vector register are reserved. - name: vreg_offgroup_LMUL2_rsv - coverpoint: [""] + coverpoint: + [ + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs1_vd_vs1_lmul2", + "Vf16_vfadd_vf_cg/cp_vd", + "Vf16_vfadd_vf_cg/cp_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # instructions specifying an LMUL=4 vector register group using vector register # numbers that are not multiples of four are reserved. - name: vreg_offgroup_LMUL4_rsv - coverpoint: [""] + coverpoint: + [ + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul4", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul4", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs1_vd_vs1_lmul4", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # instructions specifying an LMUL=8 vector register group using register numbers # that are not multiples of eight are reserved. - name: vreg_offgroup_LMUL8_rsv - coverpoint: [""] + coverpoint: + [ + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul8", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # Mask registers are always contained in a single vector register, regardless of # LMUL. - name: vreg_mask_LMUL_indp - coverpoint: [""] + coverpoint: + [ + "Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16", + "Vx16_vmadc_vi_cg/cp_custom_vmask_write_lmulge1", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vf16_vfadd_vf_cg/cp_masking_edges", + ] # These two bits modify the behavior of destination tail elements and destination # inactive masked-off elements respectively during the execution of vector # instructions. The tail and inactive sets contain element positions that are not # receiving new results during a vector operation, as defined in . - name: vtype_vta_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cr_vtype_agnostic"] # These two bits modify the behavior of destination tail elements and destination # inactive masked-off elements respectively during the execution of vector # instructions. The tail and inactive sets contain element positions that are not # receiving new results during a vector operation, as defined in . - name: vtype_vma_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cr_vtype_agnostic"] # All systems must support all four options: - names: [vtype_vta_val, vtype_vma_val] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cr_vtype_agnostic"] # Mask destination tail elements are always treated as tail-agnostic, regardless # of the setting of vta. - name: vreg_mask_tail_agn - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # When a set is marked undisturbed, the corresponding set of destination elements # in a vector register group retain the value they previously held. - name: vreg_mask_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # When a set is marked agnostic, the corresponding set of destination elements in # any vector destination operand can either retain the value they previously held, @@ -239,7 +327,8 @@ normative_rule_definitions: # required to be deterministic when the instruction is executed with the same # inputs. - name: vreg_agnostic_op - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cp_masking_edges", "Vf16_vfadd_vf_cg/cp_vl_0"] # In addition, except for mask load instructions, any element in the tail of a # mask result can also be written with the value the mask-producing operation @@ -254,37 +343,38 @@ normative_rule_definitions: # If the vill bit is set, then any attempt to execute a vector instruction that # depends upon vtype will raise an illegal-instruction exception. - name: vtype_vill_op - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vtype_vill_set_vl_0"] # The XLEN-bit-wide read-only vl CSR can only be updated by the vset{i}vl{i} # instructions, and the fault-only-first vector load instruction variants. - name: vl_acc - coverpoint: [""] + coverpoint: ["Vls16_vle16ff_v_cg/cp_custom_ffLS_update_vl"] # The vl register holds an unsigned integer specifying the number of elements to # be updated with results from a vector instruction, as further detailed in . - name: vl_op - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cr_vl_lmul_sew16", "Vf16_vfadd_vf_cg/cp_vl_0"] # The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e., the vector # register length in bytes. - names: [vlenb_op, vlenb_acc] - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrrswc"] # The XLEN-bit-wide read-write vstart CSR specifies the index of the first element # to be executed by a vector instruction, as described in . - names: [vstart_acc, vstart_sz] - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrs_walking1s", "SmV_cg/cp_vstart_out_of_bounds"] # All vector instructions are defined to begin execution with the element number # given in the vstart CSR, leaving earlier elements in the destination vector # undisturbed - name: vstart_op - coverpoint: [""] + coverpoint: ["Vx16_vcpop_m_cg/cp_custom_gprWriting_vstart_eq_vl"] # reset the vstart CSR to zero at the end of execution. - name: vstart_update - coverpoint: [""] + coverpoint: ["Vx16_vcpop_m_cg/cp_custom_gprWriting_vstart_eq_vl"] # vstart is not modified by vector instructions that raise illegal-instruction # exceptions. @@ -294,7 +384,7 @@ normative_rule_definitions: # The vstart CSR is defined to have only enough writable bits to hold the largest # element index (one less than the maximum VLMAX). - name: vstart_sz_writable - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrs_walking1s", "SmV_cg/cp_vstart_out_of_bounds"] # The use of vstart values greater than the largest element index for the current # vtype setting is reserved. @@ -312,29 +402,40 @@ normative_rule_definitions: # rounding-mode field in the least-significant bits (vxrm[1:0]). The upper bits, # vxrm[XLEN-1:2], should be written as zeros. - names: [vxrm_acc, vxrm_sz, vxrm_val] - coverpoint: [""] + coverpoint: + [ + "SmV_cg/cp_vcsrs_walking1s", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # The vector fixed-point rounding-mode is given a separate CSR address to allow # independent access, but is also reflected as a field in vcsr. - name: vcsr_vxrm_op - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrrswc"] # The fixed-point rounding algorithm is specified as follows. Suppose the # pre-rounding result is v, and d bits of that result are to be rounded off. Then # the rounded result is (v >> d) + r, where r depends on the rounding mode # as specified in the following table. - name: vxrm_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # The vxsat CSR has a single read-write least-significant bit (vxsat[0]) that # indicates if a fixed-point instruction has had to saturate an output value to # fit into a destination format. Bits vxsat[XLEN-1:1] should be written as zeros. - names: [vxsat_op, vxsat_acc, vxsat_sz] - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrs_walking1s"] # The vxsat bit is mirrored in vcsr. - name: vcsr_vxsat_op - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrrswc"] # The vxrm and vxsat separate CSRs can also be accessed via fields in the # XLEN-bit-wide vector control and status CSR, vcsr. @@ -344,72 +445,182 @@ normative_rule_definitions: # When LMUL=1, elements are simply packed in order from the least-significant to # most-significant bits of the vector register. - name: vreg_lmul1_op - coverpoint: [""] + coverpoint: ["Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul1"] # When LMUL < 1, only the first LMUL*VLEN/SEW elements in the vector register # are used. The remaining space in the vector register is treated as part of the # tail, and hence must obey the vta setting. - name: vreg_flmul_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cr_vl_lmul_sew16"] # When vector registers are grouped, the elements of the vector register group are # packed contiguously in element order beginning with the lowest-numbered vector # register and moving to the next-highest-numbered vector register in the group # once each vector register is filled. - name: vreg_lmulge2_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs1_vd_vs1_lmul4", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul4", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul2", + ] # A vector mask occupies only one vector register regardless of SEW and LMUL. - name: vreg_mask_vtype_indp - coverpoint: [""] + coverpoint: + [ + "Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16", + "Vx16_vmadc_vi_cg/cp_custom_vmask_write_lmulge1", + ] # Each element is allocated a single mask bit in a mask vector register. The mask # bit for element i is located in bit i of the mask register, independent of SEW # or LMUL. - name: vreg_mask_sz - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Any vector register can be used to hold a scalar regardless of the current LMUL # setting. - name: vreg_scalar_lmul_indp - coverpoint: [""] + coverpoint: + [ + "Vf16_vfmv_s_f_cg/cp_custom_fmv_sf_vd_all_lmul_regs", + "Vf16_vfmv_f_s_cg/cp_custom_fmv_fs_vs2_all_lmul_regs", + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul2", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul2", + "Vx16_vmv_x_s_cg/cp_custom_voffgroup_vs2_lmul2", + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul4", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul4", + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul8", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul8", + "Vx16_vwredsum_vs_cg/cp_custom_vreductionw_vd_vs1_emul_16", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vf16_vfadd_vv_cg/cp_vs1", + ] # Each vector operand has an effective element width (EEW) and an effective LMUL # (EMUL) that is used to determine the size and location of all the elements # within a vector register group. By default, for most operands of most # instructions, EEW=SEW and EMUL=LMUL. - name: EEW - coverpoint: [""] + coverpoint: + [ + "Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul1", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + ] # Each vector operand has an effective element width (EEW) and an effective LMUL # (EMUL) that is used to determine the size and location of all the elements # within a vector register group. By default, for most operands of most # instructions, EEW=SEW and EMUL=LMUL. - name: EMUL - coverpoint: [""] + coverpoint: + [ + "Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul4", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul1", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + ] # EEW/EMUL = SEW/LMUL. - name: EMUL_SEW_LMUL_dep - coverpoint: [""] + coverpoint: + [ + "Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + ] # EEW/EMUL = SEW/LMUL. - name: EEW_SEW_LMUL_dep - coverpoint: [""] + coverpoint: + [ + "Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + ] # Narrowing instructions have a source operand that has EEW=2*SEW and EMUL=2*LMUL # but with a destination where EEW=SEW and EMUL=LMUL. - name: vnarrowing_EEW - coverpoint: [""] + coverpoint: + [ + "Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rup_overflow", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # Narrowing instructions have a source operand that has EEW=2*SEW and EMUL=2*LMUL # but with a destination where EEW=SEW and EMUL=LMUL. - name: vnarrowing_EMUL - coverpoint: [""] + coverpoint: + [ + "Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rup_overflow", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # Using other than the lowest-numbered vector register to specify a vector # register group is a reserved encoding. - name: EMUL_offgroup_rsv - coverpoint: [""] + coverpoint: + [ + "Vf16_vfadd_vf_cg/cp_vd", + "Vf16_vfadd_vv_cg/cp_vs1", + "Vls16_vs1r_v_cg/cp_vs3", + "Vf16_vfadd_vf_cg/cp_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # A vector register cannot be used to provide source operands with more than one # EEW for a single instruction. A mask register source is considered to have EEW=1 @@ -418,27 +629,77 @@ normative_rule_definitions: # appears at different positions within two or more vector register groups, is # reserved. - name: vreg_source_EEW_rsv - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vv_cg/cmp_vs1_vs2"] # A destination vector register group can overlap a source vector register group # only if one of the following holds: - name: vreg_overlap_legal - coverpoint: [""] + coverpoint: + [ + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs1_vd_vs1_lmul1", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs1_vd_vs1_lmul2", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs1_vd_vs1_lmul4", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul1", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul2", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul4", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs1_vd_vs1_lmul1", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs1_vd_vs1_lmul2", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs1_vd_vs1_lmul4", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul1", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul4", + "Vf16_vfadd_vf_cg/cmp_vd_vs2", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vf16_vfadd_vv_cg/cmp_vs1_vs2", + "Vf16_vfadd_vv_cg/cmp_vd_vs1_vs2", + "Vls16_vsoxei16_v_cg/cmp_vs3_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # For the purpose of determining register group overlap constraints, mask elements # have EEW=1. - name: vreg_mask_overlap - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Any instruction encoding that violates the overlap constraints is reserved. - name: vreg_overlap_rsv - coverpoint: [""] + coverpoint: + [ + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs1_vd_vs1_lmul2", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul2", + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs2_vd_vs2_lmul4", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs1_vd_vs1_lmul2", + "Vx16_vwadd_vv_cg/cp_custom_allVdOverlapTopVs2_vd_vs2_lmul1", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vf16_vfadd_vv_cg/cmp_vd_vs1_vs2", + "Vf16_vfadd_vf_cg/cmp_vd_vs2", + "Vls16_vsoxei16_v_cg/cmp_vs3_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # When source and destination registers overlap and have different EEW, the # instruction is mask- and tail-agnostic, regardless of the setting of the vta and # vma bits in vtype. - name: vreg_overlap_agn - coverpoint: [""] + coverpoint: + [ + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul4", + "Vf16_vfadd_vf_cg/cmp_vd_vs2", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vls16_vsoxei16_v_cg/cmp_vs3_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The largest vector register group used by an instruction can not be greater than # 8 vector registers (i.e., EMUL≤8), and if a vector instruction would require @@ -447,12 +708,19 @@ normative_rule_definitions: # register group result when LMUL=8 is reserved as this would imply a result # EMUL=16. - name: EMUL_rsv - coverpoint: [""] + coverpoint: ["Vx16_vwredsum_vs_cg/cp_custom_vreductionw_vd_vs1_emul_16"] # Widened scalar values, e.g., input and output to a widening reduction operation, # are held in the first element of a vector register and have EMUL=1. - name: vreg_scalar_EMUL - coverpoint: [""] + coverpoint: + [ + "Vx16_vwredsum_vs_cg/cp_custom_vreductionw_vd_vs1_emul_16", + "Vf16_vfadd_vv_cg/cp_vs1", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # Element operations that are masked off (inactive) never generate exceptions. The # destination vector register elements corresponding to masked-off elements are @@ -460,30 +728,53 @@ normative_rule_definitions: # setting of the vma bit in vtype Where available, masking is encoded in a # single-bit vm field in the instruction (inst[25]). - name: vmask_op - coverpoint: [""] + coverpoint: + [ + "Vf16_vfrsqrt7_v_cg/cp_custom_vfp_flags_inactive_not_set", + "Vf16_vfadd_vf_cg/cp_masking_edges", + ] # The mask value used to control execution of a masked vector instruction is # always supplied by vector register v0. - name: vreg_vmask - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_masked_vs2_v0", + "Vf16_vfadd_vf_cg/cp_masking_edges", + ] # The destination vector register group for a masked vector instruction cannot # overlap the source mask register (v0), unless the destination vector register is # being written with a mask value (e.g., compares) or the scalar result of a # reduction. These instruction encodings are reserved. - name: vreg_vmask_rsv - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_masked_vs2_v0", + "Vx16_vmadc_vim_cg/cp_custom_vmask_write_v0_masked", + "Vf16_vfadd_vf_cg/cp_vd", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vf16_vfadd_vv_cg/cmp_vs1_vs2", + "Vf16_vfadd_vv_cg/cmp_vd_vs1_vs2", + "Vf16_vfadd_vf_cg/cmp_vd_vs2", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # When vstart ≥ vl, there are no body elements, and no elements are updated in any # destination vector register group, including that no tail elements are updated # with agnostic values. - name: vstart_vl_dep - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vl_0"] # Instructions that write an x register or f register do so even when vstart ≥ vl, # including when vl=0. - name: vstart_vl_scalar_indp - coverpoint: [""] + coverpoint: + [ + "Vx16_vcpop_m_cg/cp_custom_gprWriting_vstart_eq_vl", + "D_fclass_d_cg/cp_rd", + "Vf16_vfadd_vf_cg/cp_vl_0", + ] # The prestart elements do not raise exceptions and do not update the destination # vector register. @@ -494,7 +785,12 @@ normative_rule_definitions: # vector register group unless masked agnostic is specified (vtype.vma=1), in # which case inactive elements may be overwritten with 1s. - name: vector_inactive_element - coverpoint: [""] + coverpoint: + [ + "Vf16_vfrsqrt7_v_cg/cp_custom_vfp_flags_inactive_not_set", + "Vx16_vredand_vs_cg/cp_custom_element0Masked", + "Vf16_vfadd_vf_cg/cp_masking_edges", + ] # The tail elements do not raise exceptions, and do not update any destination # vector register group unless tail agnostic is specified (vtype.vta=1), in which @@ -503,7 +799,8 @@ normative_rule_definitions: # When LMUL < 1, the tail includes the elements past VLMAX that are held in the # same vector register. - name: vector_tail_element - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cp_vl_0", "Vf16_vfadd_vf_cg/cp_masking_edges"] # The vset{i}vl{i} instructions set the vtype and vl CSRs based on their # arguments, and write the new value of vl into rd. @@ -512,7 +809,13 @@ normative_rule_definitions: # the vl register is also set to zero. - name: vtype_vstart_op - coverpoint: [""] + coverpoint: + [ + "SmV_cg/cp_mstatus_vs_set_dirty_csr", + "SmV_cg/cp_sew_lmul_vset_i_vli", + "SmV_cg/cp_sew_lmul_vsetvl", + "SmV_cg/cp_vtype_vill_set_vl_0", + ] # The new vtype value is encoded in the immediate fields of vsetvli and vsetivli, # and in the rs2 register for vsetvl. The read-only XLEN-wide vector type CSR, @@ -528,7 +831,7 @@ normative_rule_definitions: # supported. An unsupported value in any location within the vtype value must # result in vill being set. - name: vtype_vill_set - coverpoint: [""] + coverpoint: ["Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_vill"] # When rs1 is not x0, the AVL is an unsigned integer held in the x register # specified by rs1, and the new vl value is also written to the x register @@ -550,7 +853,7 @@ normative_rule_definitions: # For the vsetivli instruction, the AVL is encoded as a 5-bit zero-extended # immediate (0—​31) in the rs1 field. - name: vsetivli_op - coverpoint: [""] + coverpoint: ["SmV_cg/cp_sew_lmul_vset_i_vli"] # The vset{i}vl{i} instructions first set VLMAX according to their vtype argument, # then set vl obeying the following constraints: vl = AVL if AVL ≤ VLMAX ceil(AVL @@ -561,7 +864,7 @@ normative_rule_definitions: # argument to vset{i}vl{i} results in the same value in vl, provided the resultant # VLMAX equals the value of VLMAX at the time that vl was read - name: vl_val - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vl_0"] # All vector loads and stores may generate and accept a non-zero vstart value. - name: vector_ls_vstart @@ -569,23 +872,28 @@ normative_rule_definitions: # Vector load/store base registers and strides are taken from the GPR x registers. - name: vector_ls_base_stride_regtype - coverpoint: [""] + coverpoint: ["D_fcvt_d_w_cg/cp_rs1", "E_add_cg/cp_rs2"] # The base effective address for all vector accesses is given by the contents of # the x register named in rs1. - name: vector_ls_base - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_zero_extended_sew8", + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_zero_extended_sew16", + "D_fcvt_d_w_cg/cp_rs1", + ] # Vector unit-stride operations access elements stored contiguously in memory # starting from the base effective address. - name: vector_ls_unit_stride_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Vector constant-stride operations access the first memory element at the base # effective address, and then access subsequent elements at address increments # given by the byte offset contained in the x register specified by rs2. - name: vector_ls_constant_stride_op - coverpoint: [""] + coverpoint: ["E_add_cg/cp_rs2"] # Vector memory unit-stride and constant-stride operations directly encode EEW of # the data to be transferred statically in the instruction to reduce the number of @@ -597,12 +905,12 @@ normative_rule_definitions: # For stores, the vs3 register is read to provide the first field to be stored to # each segment. - name: vector_ls_seg_unit_stride_vd_vs3 - coverpoint: [""] + coverpoint: ["Vls16_vs1r_v_cg/cp_vs3"] # Support for misaligned vector memory accesses is independent of an # implementation’s support for misaligned scalar memory accesses. - name: vector_ls_scalar_missaligned_independence - coverpoint: [""] + coverpoint: ["implicit"] # Vector misaligned memory accesses follow the same rules for atomicity as scalar # misaligned memory accesses. @@ -612,14 +920,14 @@ normative_rule_definitions: # However, even for the ordered form, accesses to the fields within an individual # segment are not ordered with respect to each other. - name: vector_ls_seg_indexed_unordered - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # If element 0 raises an exception, vl is not modified, and the trap is taken. If # an element > 0 raises an exception, the corresponding trap is not taken, and # the vector length vl is reduced to the index of the element that would have # raised an exception. - name: vector_ff_op - coverpoint: [""] + coverpoint: ["Vls16_vle16ff_v_cg/cp_custom_ffLS_update_vl"] # Vector indexed operations add the contents of each element of the vector offset # operand specified by vs2 to the base effective address to give the effective @@ -627,12 +935,19 @@ normative_rule_definitions: # while the offset vector register group has EEW encoded in the instruction and # EMUL=(EEW/SEW)*LMUL. - name: vector_ls_indexed_op - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_zero_extended_sew8", + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_zero_extended_sew16", + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_truncated", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vls16_vsoxei16_v_cg/cmp_vs3_vs2", + ] # Indexed operations use the explicit EEW encoding in the instruction to set the # size of the indices used, and use SEW/LMUL to specify the data width. - name: vector_ls_indexed_EEW - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # Implementations must provide vector loads and stores with EEWs corresponding to # all supported SEW settings. @@ -645,14 +960,20 @@ normative_rule_definitions: # The vector offset operand is treated as a vector of byte-address offsets. - name: vector_ls_bytewise - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # If the vector offset elements are narrower than XLEN, they are zero-extended to # XLEN before adding to the base effective address. If the vector offset elements # are wider than XLEN, the least-significant XLEN bits are used in the address # calculation. - name: vector_ls_XLEN_dep - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_zero_extended_sew8", + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_zero_extended_sew16", + "Vls16_vloxei16_v_cg/cp_custom_ls_indexed_truncated", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + ] # If the implementation does not support the EEW of the offset elements, the # instruction is reserved. @@ -664,13 +985,13 @@ normative_rule_definitions: # operations have two forms, ordered and unordered. The indexed-ordered variants # preserve element ordering on memory accesses. - name: vector_ls_stride_ordered_op - coverpoint: [""] + coverpoint: ["E_add_cg/cp_rs2_edges", "Vx16_vaadd_vv_cg/cp_vs2_edges"] # For unordered instructions (mop[1:0]!=11) there is no guarantee on element # access order. If the accesses are to a strongly ordered IO region, the element # accesses can be initiated in any order. - name: vector_ls_stride_unordered_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # For implementations with precise vector traps, exceptions on indexed-unordered # stores must also be precise. @@ -688,17 +1009,21 @@ normative_rule_definitions: # The nf[2:0] field also encodes the number of whole vector registers to transfer # for the whole vector register load/store instructions. - name: vector_wholels_nf_op - coverpoint: [""] + coverpoint: + [ + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_vill", + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_lmul", + ] # Vector loads and stores have an EEW encoded directly in the instruction. The # corresponding EMUL is calculated as EMUL = (EEW/SEW)*LMUL. - name: vector_ls_EEW - coverpoint: [""] + coverpoint: ["Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16"] # Vector loads and stores have an EEW encoded directly in the instruction. The # corresponding EMUL is calculated as EMUL = (EEW/SEW)*LMUL. - name: vector_ls_EMUL - coverpoint: [""] + coverpoint: ["Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16"] # If the EMUL would be out of range (EMUL>8 or EMUL<1/8), the instruction # encoding is reserved. @@ -708,14 +1033,14 @@ normative_rule_definitions: # The vector register groups must have legal register specifiers for the selected # EMUL, otherwise the instruction encoding is reserved. - name: vector_ls_EMUL_offgroup_rsv - coverpoint: [""] + coverpoint: ["Vls16_vs1r_v_cg/cp_vs3"] # Vector unit-stride and constant-stride use the EEW/EMUL encoded in the # instruction for the data values, while vector indexed loads and stores use the # EEW/EMUL encoded in the instruction for the index values and the SEW/LMUL # encoded in vtype for the data values. - name: vector_ls_indexed_EMUL - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The mew bit (inst[28]) when set is expected to be used to encode expanded memory # sizes of 128 bits and above, but these encodings are currently reserved. @@ -728,34 +1053,46 @@ normative_rule_definitions: # EMUL=1), and the destination register is always written with a tail-agnostic # policy. - name: vector_ls_unit_stride_mask - coverpoint: [""] + coverpoint: ["Vls16_vlm_v_cg/cp_custom_maskLS_emul_ge_16"] # Negative and zero strides are supported. - name: vector_ls_neg_stride - coverpoint: [""] + coverpoint: + [ + "Vls16_vlse8_v_cg/cp_rs2_edges_ls_e8", + "Vls16_vlse16_v_cg/cp_rs2_edges_ls_e16", + "Vls16_vlse32_v_cg/cp_rs2_edges_ls_e32", + "Vls16_vlse64_v_cg/cp_rs2_edges_ls_e64", + ] # Negative and zero strides are supported. - name: vector_ls_zero_stride - coverpoint: [""] + coverpoint: + [ + "Vls16_vlse8_v_cg/cp_rs2_edges_ls_e8", + "Vls16_vlse16_v_cg/cp_rs2_edges_ls_e16", + "Vls16_vlse32_v_cg/cp_rs2_edges_ls_e32", + "Vls16_vlse64_v_cg/cp_rs2_edges_ls_e64", + ] # Element accesses within a constant-stride instruction are unordered with respect # to each other. - name: vector_ls_constant_stride_unordered - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # When rs2=x0, then an implementation is allowed, but not required, to perform # fewer memory operations than the number of active elements, and may perform # different numbers of memory operations across different dynamic executions of # the same static instruction. - name: vector_ls_constant-stride_x0 - coverpoint: [""] + coverpoint: ["E_add_cg/cp_rs2"] # The unit-stride fault-only-first load instructions are used to vectorize loops # with data-dependent exit conditions ("while" loops). These instructions execute # as a regular load except that they will only take a trap caused by a synchronous # exception on element 0. - name: vector_ff_trigger - coverpoint: [""] + coverpoint: ["Vls16_vle16ff_v_cg/cp_custom_ffLS_update_vl"] # Load instructions may overwrite active destination vector register group # elements past the element index at which the trap is reported. @@ -770,18 +1107,18 @@ normative_rule_definitions: # corresponding element load operation will not be restarted due to a trap or # vector-length trimming. - name: vector_ff_past_trap - coverpoint: [""] + coverpoint: ["untestable"] # Even when an exception is not raised, implementations are permitted to process # fewer than vl elements and reduce vl accordingly, but if vstart=0 and vl>0, # then at least one element must be processed. - name: vector_ff_no_exception - coverpoint: [""] + coverpoint: ["Vls16_vle16ff_v_cg/cp_custom_ffLS_update_vl"] # When the fault-only-first instruction takes a trap due to an interrupt, # implementations should not reduce vl and should instead set a vstart value. - name: vector_ff_interrupt_behavior - coverpoint: [""] + coverpoint: ["Vls16_vle16ff_v_cg/cp_custom_ffLS_update_vl"] # The three-bit nf field in the vector instruction encoding is an unsigned integer # that contains one less than the number of fields per segment, NFIELDS. Each @@ -793,7 +1130,7 @@ normative_rule_definitions: # even vector register, but does not have to start at a multiple of 8 vector # register number). - name: NFIELDS - coverpoint: [""] + coverpoint: ["Vls16_vs1r_v_cg/cp_vs3"] # The EMUL setting must be such that EMUL * NFIELDS ≤ 8, otherwise the instruction # encoding is reserved. @@ -803,19 +1140,19 @@ normative_rule_definitions: # If the vector register numbers accessed by the segment load or store would # increment past 31, then the instruction encoding is reserved. - name: vector_ls_seg_rsv - coverpoint: [""] + coverpoint: ["Vls16_vs1r_v_cg/cp_vs3", "Vls16_vsoxei16_v_cg/cmp_vs3_vs2"] # The vl register gives the number of segments to move, which is equal to the # number of elements transferred to each vector register group. Masking is also # applied at the level of whole segments. - name: vector_ls_seg_op - coverpoint: [""] + coverpoint: ["E_add_cg/cp_rs2_edges", "Vx16_vaadd_vv_cg/cp_vs2_edges"] # For segment loads and stores, the individual memory accesses used to access # fields within each segment are unordered with respect to each other even for # ordered indexed segment loads and stores. - name: vector_ls_seg_unordered - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vstart value is in units of whole segments. - name: vector_ls_seg_vstart_dep @@ -825,57 +1162,58 @@ normative_rule_definitions: # whether a subset of the faulting segment's accesses are performed before the # trap is taken. - name: vector_ls_seg_partial_access - coverpoint: [""] + coverpoint: ["untestable"] # The vector unit-stride load and store segment instructions move packed # contiguous segments into multiple destination vector register groups. - name: vector_ls_seg_unit_stride_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # For fault-only-first segment loads, if an exception is detected partway through # accessing the zeroth segment, the trap is taken. If an exception is detected # partway through accessing a subsequent segment, vl is reduced to the index of # that segment. - name: vector_ls_seg_ff_unit_stride_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # In both cases, it is implementation-defined whether a subset of the segment is # loaded. - name: vector_ff_seg_partial_access - coverpoint: [""] + coverpoint: ["untestable"] # These instructions may overwrite destination vector register group elements past # the point at which a trap is reported or past the point at which vector length # is trimmed. - name: vector_ls_seg_ff_overload - coverpoint: [""] + coverpoint: ["untestable"] # Vector constant-stride segment loads and stores move contiguous segments where # each segment is separated by the byte-stride offset given in the rs2 GPR # argument. - name: vector_ls_seg_constant_stride_op - coverpoint: [""] + coverpoint: ["E_add_cg/cp_rs2"] # Accesses to the fields within each segment can occur in any order, including the # case where the byte stride is such that segments overlap in memory. - name: vector_ls_seg_constant_stride_unordered - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Vector indexed segment loads and stores move contiguous segments where each # segment is located at an address given by adding the scalar base address in the # rs1 field to byte offsets in vector register vs2. - name: vector_ls_seg_indexed_op - coverpoint: [""] + coverpoint: + ["Vx16_vaadd_vv_cg/cp_vs2_edges", "Vls16_vsoxei16_v_cg/cmp_vs3_vs2"] # The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector # register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL. - name: vector_ls_seg_indexed_EMUL_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector # register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL. - name: vector_ls_seg_indexed_EEW_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The EMUL * NFIELDS ≤ 8 constraint applies to the data vector register group. - name: vector_ls_seg_indexed_EMUL_NFIELDS_val @@ -885,7 +1223,7 @@ normative_rule_definitions: # overlap the source vector register group (specified by vs2), else the # instruction encoding is reserved. - name: vector_ls_seg_indexed_vreg_rsv - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cmp_vd_vs2"] # The load instructions have an EEW encoded in the mew and width fields following # the pattern of regular unit-stride loads. @@ -895,17 +1233,26 @@ normative_rule_definitions: # NFIELDS indicates the number of vector registers to transfer, numbered # successively after the base. - name: vector_ls_seg_wholereg_op - coverpoint: [""] + coverpoint: + [ + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_vill", + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_lmul", + "Vls16_vs1r_v_cg/cp_vs3", + ] # Only NFIELDS values of 1, 2, 4, 8 are supported, with other values reserved. - name: vector_ls_seg_wholereg_nf_rsv - coverpoint: [""] + coverpoint: + [ + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_lmul", + "Vls16_vs1r_v_cg/cp_vs3", + ] # When multiple registers are transferred, the lowest-numbered vector register is # held in the lowest-numbered memory addresses and successive vector register # numbers are placed contiguously in memory. - name: vector_ls_seg_wholereg_op_cont - coverpoint: [""] + coverpoint: ["Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_lmul"] # The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW, # regardless of current settings in vtype and vl. The usual property that no @@ -914,7 +1261,11 @@ normative_rule_definitions: # largest element index for the current vtype setting does not apply. Instead, the # instructions are reserved if vstart ≥ evl. - name: vector_ls_seg_wholereg_evl - coverpoint: [""] + coverpoint: + [ + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_vill", + "Vls16_vl1re16_v_cg/cp_custom_vwholeRegLS_lmul", + ] # Implementations are allowed to raise a misaligned address exception on whole # register loads and stores if the base address is not naturally aligned to the @@ -931,87 +1282,151 @@ normative_rule_definitions: # Vector memory instructions appear to execute in program order on the local hart. - name: vector_ls_program_order - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Vector memory instructions follow RVWMO at the instruction level. - name: vector_ls_RVWMO - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Except for vector indexed-ordered loads and stores, element operations are # unordered within the instruction. - name: vector_ls_indexed_ordered_ordered - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Vector indexed-ordered loads and stores read and write elements from/to memory # in element order respectively, obeying RVWMO at the element level. - name: vector_ls_indexed_ordered_RVWMO - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Instructions affected by the vector length register vl have a control dependency # on vl, rather than a data dependency. - name: vl_control_dependency - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cp_vl_0", "Vf16_vfadd_vf_cg/cp_masking_edges"] # Similarly, masked vector instructions have a control dependency on the source # mask register, rather than a data dependency. - name: vmask_control_dependency - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_masked_vs2_v0", + "Vf16_vfadd_vf_cg/cp_masking_edges", + ] # All vector floating-point operations use the dynamic rounding mode in the frm # register. - name: V_fp_frm - coverpoint: [""] + coverpoint: + [ + "Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rup_overflow", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "D_fcvt_d_s_cg/cp_fs1_edges", + "D_fadd_d_cg/cp_csr_frm", + ] # Use of the frm field when it contains an invalid rounding mode by any vector # floating-point instruction--even those that do not depend on the rounding mode, # or when vl=0, or when vstart {ge} vl--is reserved. - name: V_inv_frm_rsv - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_csr_frm"] # Vector-vector operations take two vectors of operands from vector register # groups specified by vs2 and vs1 respectively. - name: vop-vv_vreg_vs2_vs1 - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_masked_vs2_v0", + "Vf16_vfadd_vv_cg/cp_vs1", + "Vf16_vfadd_vv_cg/cmp_vs1_vs2", + "Vf16_vfadd_vv_cg/cmp_vd_vs1_vs2", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # the vector register group operand is specified by vs2. - names: [vop-vx_vreg_vs2, vop-vi_vreg_vs2] - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # For integer operations, the scalar can be a 5-bit immediate, imm[4:0], encoded # in the rs1 field. The value is sign-extended to SEW bits, unless otherwise # specified. - name: vop-vi_imm_5bit - coverpoint: [""] + coverpoint: + [ + "D_fld_cg/cp_imm_edges", + "Vx16_vadc_vim_cg/cp_imm_5bit", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # For integer operations, the scalar can be taken from the scalar x register # specified by rs1. - name: vop-vx_xreg_rs1 - coverpoint: [""] + coverpoint: + [ + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_32", + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_64", + "D_fcvt_d_w_cg/cp_rs1", + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + ] # If XLEN>SEW, the least-significant SEW bits of the x register are used, # unless otherwise specified. - name: vop-vx_rs1_trunc_lsb_sewbits - coverpoint: [""] + coverpoint: + [ + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_32", + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_64", + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + ] # If XLEN<SEW, the value from the x register is sign-extended to SEW bits. - name: vop-vx_rs1_sext_sewbits - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + ] # For floating-point operations, the scalar can be taken from a scalar f register. - name: vfop_freg - coverpoint: [""] + coverpoint: + [ + "D_fadd_d_cg/cp_fs1", + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # If FLEN > SEW, the value in the f registers is checked for a valid NaN-boxed # value, in which case the least-significant SEW bits of the f register are used, # else the canonical NaN value is used. - name: vfop_freg_NaNbox_lsb_sewbits - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # Vector instructions where any floating-point vector operand's EEW is not a # supported floating-point type width (which includes when FLEN < SEW) are # reserved. - name: V_fp_eew_rsv - coverpoint: [""] + coverpoint: + ["Vx16_vaadd_vv_cg/cp_vs2_edges", "Vx16_vaadd_vv_cg/cp_vs1_edges"] # When adding a vector extension to the Zfinx/Zdinx/Zhinx extensions, # floating-point scalar arguments are taken from the x registers. NaN-boxing is @@ -1019,57 +1434,136 @@ normative_rule_definitions: # not checked for a NaN box; bits XLEN-1:EEW are ignored. For RV32_Zdinx, EEW=64 # scalar arguments are supplied by an x-register pair. - name: V_Zfinx_fp_scalar - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Vector arithmetic instructions are masked under control of the vm field. - name: V_masked - coverpoint: [""] + coverpoint: + [ + "Vls16_vloxei16_v_cg/cp_custom_masked_vs2_v0", + "Vx16_vredand_vs_cg/cp_custom_element0Masked", + "Vf16_vfadd_vf_cg/cp_masking_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + ] # A few vector arithmetic instructions are defined to be widening operations where # the destination vector register group has EEW=2*SEW and EMUL=2*LMUL. - name: vwop_vd_eew_emul - coverpoint: [""] + coverpoint: + [ + "Vx16_vwaddu_vv_cg/cp_custom_vdOverlapTopVs1_vd_vs1_lmul1", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # A few instructions are provided to convert double-width source vectors into # single-width destination vectors. These instructions convert a vector register # group specified by vs2 with EEW/EMUL=2*SEW/2*LMUL to a vector register group # with the current SEW/LMUL setting. - names: [vnop_vd_eew_emul, vnop_vs2_eew_emul] - coverpoint: [""] + coverpoint: + [ + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_vdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul1", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul2", + "Vx16_vnclip_wi_cg/cp_custom_allVdOverlapBtmVs2_vd_vs2_lmul4", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + "Vf16_vfadd_vf_cg/cp_vs2", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # Where there is a second source vector register group (specified by vs1), this # has the same (narrower) width as the result (i.e., EEW=SEW). - name: vnop_vs1_eew_emul - coverpoint: [""] + coverpoint: + [ + "Vf16_vfadd_vv_cg/cp_vs1", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # Vector integer add and subtract are provided. - names: [vadd_op, vsub_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # Reverse-subtract instructions are also provided for the vector-scalar forms. - name: vrsub_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + ] # The widening add/subtract instructions are provided in both signed and unsigned # variants, depending on whether the narrower source operands are first sign- or # zero-extended before forming the double-width sum. - names: [vwaddu_op, vwadd_op, vwsubu_op, vwsub_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The vector integer extension instructions zero- or sign-extend a source vector # integer operand with EEW less than SEW to fill SEW-sized elements in the # destination. - names: [vsext_op, vzext_op] - coverpoint: [""] + coverpoint: + [ + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + ] # The EEW of the source is 1/2, 1/4, or 1/8 of SEW, while EMUL of the source is # (EEW/SEW)*LMUL. - names: [vsext_vs_eew_emul, vzext_vs_eew_emul] - coverpoint: [""] + coverpoint: + [ + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + ] # The destination has EEW equal to SEW and EMUL equal to LMUL. - names: [vsext_vd_eew_emul, vzext_vd_eew_emul] - coverpoint: [""] + coverpoint: + [ + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul8", + "Vx64_vsext_vf8_cg/cp_custom_vext8_overlapping_vd_vs2_lmul8", + "Vf16_vfadd_vf_cg/cp_vd", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul2", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul4", + "Vx16_vsext_vf2_cg/cp_custom_vext2_overlapping_vd_vs2_lmul8", + "Vx32_vsext_vf4_cg/cp_custom_vext4_overlapping_vd_vs2_lmul4", + ] # If the source EEW is not a supported width, or source EMUL would be below the # minimum legal LMUL, the instruction encoding is reserved. @@ -1080,17 +1574,25 @@ normative_rule_definitions: # described in <<sec-mask-register-layout>>. Due to encoding # constraints, the carry input must come from the implicit v0 register, - names: [vmadc_carry_v0, vmsbc_carry_v0, vadc_carry_v0, vsbc_carry_v0] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vv_cg/cp_vs1"] # vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, # and write the result to vector register vd. - names: [vadc_op, vsbc_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # These instructions are encoded as masked instructions (vm=0), but they operate # on and write back all body elements. - names: [vadc_masked_write_all_elem, vsbc_masked_write_all_elem] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Encodings corresponding to the unmasked versions (vm=1) are reserved. - names: [vadc_unmasked_rsv, vsbc_unmasked_rsv] @@ -1101,33 +1603,53 @@ normative_rule_definitions: # borrow-out back to mask register vd. If unmasked (vm=1), there is no carry-in or # borrow-in. - name: vmadc_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # vmadc and vmsbc add or subtract the source operands, optionally add the carry-in # or subtract the borrow-in if masked (vm=0), and write the resulting carry-out or # borrow-out back to mask register vd. If unmasked (vm=1), there is no carry-in or # borrow-in. - name: vmsbc_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # These instructions operate on and write back all body elements, even if masked. - names: [vmadc_masked_write_all_elem, vmsbc_masked_write_all_elem] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Because these instructions produce a mask value, they always operate with a # tail-agnostic policy. - names: [vmadc_tail_agnostic, vmsbc_tail_agnostic] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # For vmsbc, the borrow is defined to be 1 iff the difference, prior to # truncation, is negative. - name: vmsbc_borrow_neg - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cr_vs2_vs1_edges"] # For vadc and vsbc, the instruction encoding is reserved if the destination # vector register is v0. - names: [vadc_vd_v0_rsv, vsbc_vd_v0_rsv] - coverpoint: [""] + coverpoint: + [ + "Vf16_vfadd_vf_cg/cp_vd", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vf16_vfadd_vv_cg/cmp_vd_vs1_vs2", + ] # # Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx # vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate @@ -1136,7 +1658,15 @@ normative_rule_definitions: # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # # vector-immediate - names: [vand_op, vor_op, vxor_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # A full set of vector shift instructions are provided, including logical shift # left (sll), and logical (zero-extending srl) and arithmetic (sign-extending sra) @@ -1144,12 +1674,25 @@ normative_rule_definitions: # vs2 and the shift amount value can come from a vector register group vs1, a # scalar integer register rs1, or a zero-extended 5-bit immediate. - names: [vsll_op, vsrl_op, vsra_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # Only the low lg2(SEW) bits of the shift-amount value are used to control the # shift amount. - names: [vsll_shamt, vsrl_shamt, vsra_shamt] - coverpoint: [""] + coverpoint: + [ + "Vx16_vsll_vv_cg/cp_custom_vshift_upperbits_vs1_ones", + "Vx16_vsll_vx_cg/cp_custom_vshift_upperbits_rs1_ones", + "Vx16_vadc_vim_cg/cp_imm_5bit", + ] # The narrowing right shifts extract a smaller field from a wider operand and have # both zero-extending (srl) and sign-extending (sra) forms. The shift amount can @@ -1161,7 +1704,12 @@ normative_rule_definitions: # The low lg2(2*SEW) bits of the shift-amount value are used (e.g., the low 6 bits # for a SEW=64-bit to SEW=32-bit narrowing operation). - names: [vnsrl_shamt, vnsra_shamt] - coverpoint: [""] + coverpoint: + [ + "Vx16_vnclip_wv_cg/cp_custom_vshiftn_upperbits_vs1_ones", + "Vx16_vnclip_wx_cg/cp_custom_vshiftn_upperbits_rs1_ones", + "Vx16_vadc_vim_cg/cp_imm_5bit", + ] # The following integer compare instructions write 1 to the destination mask # register element if the comparison evaluates to true, and 0 otherwise. The @@ -1178,7 +1726,15 @@ normative_rule_definitions: vmsgtu_op, vmsgt_op, ] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The destination mask vector register may be the same as the source vector mask # register (v0). @@ -1193,7 +1749,7 @@ normative_rule_definitions: vmsgtu_vd_v0_legal, vmsgt_vd_v0_legal, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vd"] # Compares effectively AND in the mask under a mask-undisturbed policy if the # destination register is v0, @@ -1208,7 +1764,7 @@ normative_rule_definitions: vmsgtu_maskundisturbed, vmsgt_maskundisturbed, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Compares write mask registers, and so always operate under a tail-agnostic # policy. @@ -1223,11 +1779,18 @@ normative_rule_definitions: vmsgtu_tail_agnostic, vmsgt_tail_agnostic, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Signed and unsigned integer minimum and maximum instructions are supported. - names: [vminu_op, vmin_op, vmaxu_op, vmax_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The single-width multiply instructions perform a SEW-bit*SEW-bit multiply to # generate a 2*SEW-bit product, then return one half of the product in the @@ -1235,51 +1798,107 @@ normative_rule_definitions: # the destination register, while the mulh versions write the high word of the # product to the destination register. - names: [vmul_op, vmulh_op, vmulhu_op, vmulhsu_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The divide and remainder instructions are equivalent to the RISC-V standard # scalar integer multiply/divides, with the same results for extreme inputs. - names: [vdivu_op, vdiv_op, vremu_op, vrem_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The widening integer multiply instructions return the full 2*SEW-bit product # from an SEW-bit*SEW-bit multiply. - names: [vwmul_op, vwmulu_op, vwmulsu_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The integer multiply-add instructions are destructive and are provided in two # forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that # overwrites the first multiplicand (vmadd, vnmsub). The low half of the product # is added or subtracted from the third operand. - name: vmacc_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The integer multiply-add instructions are destructive and are provided in two # forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that # overwrites the first multiplicand (vmadd, vnmsub). The low half of the product # is added or subtracted from the third operand. - name: vnmsac_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The integer multiply-add instructions are destructive and are provided in two # forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that # overwrites the first multiplicand (vmadd, vnmsub). The low half of the product # is added or subtracted from the third operand. - name: vmadd_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The integer multiply-add instructions are destructive and are provided in two # forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that # overwrites the first multiplicand (vmadd, vnmsub). The low half of the product # is added or subtracted from the third operand. - name: vnmsub_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The widening integer multiply-add instructions add the full 2*SEW-bit product # from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and produce a 2*SEW-bit # result. - names: [vwmaccu_op, vwmacc_op, vwmaccsu_op, vwmaccus_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The vector integer merge instructions combine two source operands based on a # mask. The vmerge instructions are encoded as masked instructions (vm=0). The @@ -1290,19 +1909,28 @@ normative_rule_definitions: # register group specified by vs1 or a scalar x register specified by rs1 or a # 5-bit sign-extended immediate. - name: vmerge_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vv_cg/cp_vs1", "Vf16_vfadd_vf_cg/cp_vs2"] # Unlike regular arithmetic instructions, the merge operates on all body elements # (i.e., the set of elements from vstart up to the current vector length in vl). - name: vmerge_all_elem - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # The vector integer move instructions copy a source operand to a vector register # group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x # and vmv.v.i variants splat a scalar register or immediate to all active elements # of the destination vector register group. - name: vmv_op - coverpoint: [""] + coverpoint: + [ + "D_fadd_d_cg/cp_asm_count", + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The first operand specifier (vs2) must contain v0, and any other vector register # number in vs2 is reserved. @@ -1343,39 +1971,55 @@ normative_rule_definitions: # performed in infinite precision before rounding and truncating. For vasub and # vasubu, overflow is ignored and the result wraps around. - name: vaaddu_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # The averaging add and subtract instructions right shift the result by one bit # and round off the result according to the setting in vxrm. Computation is # performed in infinite precision before rounding and truncating. For vasub and # vasubu, overflow is ignored and the result wraps around. - name: vaadd_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # The averaging add and subtract instructions right shift the result by one bit # and round off the result according to the setting in vxrm. Computation is # performed in infinite precision before rounding and truncating. For vasub and # vasubu, overflow is ignored and the result wraps around. - name: vasubu_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # The averaging add and subtract instructions right shift the result by one bit # and round off the result according to the setting in vxrm. Computation is # performed in infinite precision before rounding and truncating. For vasub and # vasubu, overflow is ignored and the result wraps around. - name: vasub_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # The signed fractional multiply instruction produces a 2*SEW product of the two # SEW inputs, then shifts the result right by SEW-1 bits, rounding these bits # according to vxrm, then saturates the result to fit into SEW bits. If the result # causes saturation, the vxsat bit is set. - name: vsmul_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges"] # If the result causes saturation, the vxsat bit is set. - name: vxsat_op_vsmul - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges"] # These instructions shift the input value right, and round off the shifted out # bits according to vxrm. The scaling right shifts have both zero-extending @@ -1384,12 +2028,21 @@ normative_rule_definitions: # a vector register group vs1, a scalar integer register rs1, or a zero-extended # 5-bit immediate. - names: [vssrl_op, vssra_op] - coverpoint: [""] + coverpoint: + [ + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # Only the low lg2(SEW) bits of the shift-amount value are used to control the # shift amount. - names: [vssrl_shamt, vssra_shamt] - coverpoint: [""] + coverpoint: + [ + "Vx16_vsll_vv_cg/cp_custom_vshift_upperbits_vs1_ones", + "Vx16_vadc_vim_cg/cp_imm_5bit", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # The vnclip instructions are used to pack a fixed-point value into a narrower # destination. The instructions support rounding, scaling, and saturation into the @@ -1397,30 +2050,53 @@ normative_rule_definitions: # specified by vs2. The scaling shift amount value can come from a vector register # group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. - names: [vnclipu_op, vnclip_op] - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # The low lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the # low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are used to # control the right shift amount, which provides the scaling. - names: [vnclipu_shamt, vnclip_shamt] - coverpoint: [""] + coverpoint: + [ + "Vx16_vnclip_wv_cg/cp_custom_vshiftn_upperbits_vs1_ones", + "Vx16_vadc_vim_cg/cp_imm_5bit", + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # For vnclipu, the shifted rounded source value is treated as an unsigned integer # and saturates if the result would overflow the destination viewed as an unsigned # integer. - name: vnclipu_overflow - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # For vnclip, the shifted rounded source value is treated as a signed integer and # saturates if the result would overflow the destination viewed as a signed # integer. - name: vnclip_overflow - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + ] # If any destination element is saturated, the vxsat bit is set in the vxsat # register. - name: vxsat_op_vnclip_u - coverpoint: [""] + coverpoint: + [ + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # If the EEW of a vector floating-point operand does not correspond to a supported # IEEE floating-point type, the instruction encoding is reserved. @@ -1431,12 +2107,16 @@ normative_rule_definitions: # execute a vector floating-point instruction will raise an illegal-instruction # exception. - name: mstatus_FS_off_V_fp_ill - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # Any vector floating-point instruction that modifies any floating-point extension # state (i.e., floating-point CSRs or f registers) must set mstatus.FS to Dirty. - name: mstatus_FS_dirty_V_fp - coverpoint: [""] + coverpoint: ["Vf16_vfmv_f_s_cg/cp_custom_vfp_register_state_mstatus_dirty"] # If the hypervisor extension is implemented and V=1, the vsstatus.FS field is # additionally in effect for vector floating-point instructions. If vsstatus.FS or @@ -1444,26 +2124,55 @@ normative_rule_definitions: # instruction will raise an illegal-instruction exception. - names: [vsstatus_FS_off_hypervisor_V_fp_ill, mstatus_FS_off_hypervisor_V_fp_ill] - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + ] # Any vector floating-point instruction that modifies any floating-point extension # state (i.e., floating-point CSRs or f registers) must set both mstatus.FS and # vsstatus.FS to Dirty. - names: [vsstatus_FS_dirty_hypervisor_V_fp, mstatus_FS_dirty_hypervisor_V_fp] - coverpoint: [""] + coverpoint: + [ + "ExceptionsHV_cg/cp_mstatus_vs_off", + "ExceptionsHV_cg/cp_vsstatus_vs_off", + "SmVF_cg/cp_vectorfp_mstatus_fs_state_affecting_register", + "SmVF_cg/cp_vectorfp_mstatus_fs_state_affecting_csr", + ] # A vector floating-point exception at any active floating-point element sets the # standard FP exception flags in the fflags register. Inactive elements do not set # FP exception flags. - name: fflags_op_V_fp - coverpoint: [""] + coverpoint: + [ + "Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rup_overflow", + "Vf16_vfadd_vf_cg/cp_custom_vfp_flags_set", + "Vf16_vfrsqrt7_v_cg/cp_custom_vfp_flags_inactive_not_set", + "Vf16_vfrsqrt7_v_cg/cp_custom_FpRecSqrtEst_flag_edges", + "Vf16_vfrec7_v_cg/cp_custom_FpRecipEst_flag_edges", + "Vf16_vfadd_vf_cg/cp_custom_vfp_NaN_input", + "Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rod_overflow", + "Vf16_vfredosum_vs_cg/cp_custom_vfredosum_NAN_vl0", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + "D_fadd_d_cg/cp_csr_fflags_von", + ] # # Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, # rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] # vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] - names: [vfadd_op, vfsub_op, vfrsub_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # # Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, @@ -1472,7 +2181,12 @@ normative_rule_definitions: # vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar - name: vfwadd_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # # Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, # vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # @@ -1480,12 +2194,20 @@ normative_rule_definitions: # divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, # vd[i] = f[rs1]/vs2[i] - names: [vfmul_op, vfdiv_op, vfrdiv_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # # Widening floating-point multiply vfwmul.vv vd, vs2, vs1, vm # vector-vector # vfwmul.vf vd, vs2, rs1, vm # vector-scalar - name: vfwmul_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # All four varieties of fused multiply-add are provided, and in two destructive # forms that overwrite one of the operands, either the addend or the first @@ -1501,17 +2223,25 @@ normative_rule_definitions: vfmsub_op, vfnmsub_op, ] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # The widening floating-point fused multiply-add instructions all overwrite the # wide addend with the result. The multiplier inputs are all SEW wide, while the # addend and destination is 2*SEW bits wide. - names: [vfwmacc_op, vfwnmacc_op, vfwmsac_op, vfwnmsac_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # # Floating-point square root vfsqrt.v vd, vs2, vm # Vector-vector square root - name: vfsqrt_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # This is a unary vector-vector instruction that returns an estimate of 1/sqrt(x) # accurate to 7 bits. For the non-exceptional cases, the low bit of the exponent @@ -1530,7 +2260,11 @@ normative_rule_definitions: # exponent) / 2), where B is the exponent bias. The output sign equals the input # sign. - name: vfrsqrt7_op - coverpoint: [""] + coverpoint: + [ + "Vf16_vfrsqrt7_v_cg/cp_custom_FpRecSqrtEst_flag_edges", + "Vf16_vfrsqrt7_v_cg/cp_custom_FpRecSqrtEst_edges", + ] # This is a unary vector-vector instruction that returns an estimate of 1/x # accurate to 7 bits. For the non-exceptional cases, the seven high bits of @@ -1559,24 +2293,43 @@ normative_rule_definitions: # output significand equals the normalized output significand. The output sign # equals the input sign. - name: vfrec7_op - coverpoint: [""] + coverpoint: + [ + "Vf16_vfrec7_v_cg/cp_custom_FpRecipEst_flag_edges", + "Vf16_vfrec7_v_cg/cp_custom_FpRecipEst_edges", + ] # The vector floating-point vfmin and vfmax instructions have the same behavior as # the corresponding scalar floating-point instructions in version 2.2 of the # RISC-V F/D/Q extension: they perform the minimumNumber or maximumNumber # operation on active elements. - names: [vfmin_op, vfmax_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # Vector versions of the scalar sign-injection instructions. The result takes all # bits except the sign bit from the vector vs2 operands. - names: [vfsgnj_op, vfsgnjn_op, vfsgnjx_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + ] # These vector FP compare instructions compare two source operands and write the # comparison result to a mask register. - names: [vmfeq_op, vmfne_op, vmflt_op, vmfle_op, vmfgt_op, vmfge_op] - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The destination mask vector is always held in a single vector register, with a # layout of elements as described in <<sec-mask-register-layout>>. @@ -1589,7 +2342,7 @@ normative_rule_definitions: vmfgt_vd_single_vreg, vmfge_vd_single_vreg, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vd"] # The destination mask vector register may be the same as the source vector mask # register (v0). @@ -1615,12 +2368,12 @@ normative_rule_definitions: vmfgt_tail_agnostic, vmfge_tail_agnostic, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # vmfeq and vmfne raise the invalid operation exception only on signaling NaN # inputs. - names: [vmfeq_sNaN_invalid, vmfne_sNaN_invalid] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_custom_vfp_NaN_input"] # vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both # signaling and quiet NaN inputs. @@ -1653,30 +2406,30 @@ normative_rule_definitions: # placed in the least-significant bits of the result elements. The upper (SEW-10) # bits of the result are filled with zeros. - name: vfclass_op - coverpoint: [""] + coverpoint: ["Vf16_vfclass_v_cg/cp_custom_vfclass_onehot"] # The instruction is only defined for SEW=16b and above, so the result will always # fit in the destination elements. - name: vfclass_SEWge16 - coverpoint: [""] + coverpoint: ["Vf16_vfclass_v_cg/cp_custom_vfclass_onehot"] # A vector-scalar floating-point merge instruction is provided, At elements where # the mask value is zero, the first vector operand is copied to the destination # element, otherwise a scalar floating-point register value is copied to the # destination element. - name: vfmerge_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vs2", "D_fcvt_d_s_cg/cp_fs1_edges"] # operates on all body elements from vstart up to the current vector length in vl # regardless of mask value. - name: vfmerge_all_elem - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # The vector floating-point move instruction splats a floating-point scalar # operand to a vector register group. The instruction copies a scalar f register # value to all active elements of a vector register group. - name: vfmv_op - coverpoint: [""] + coverpoint: ["D_fcvt_d_s_cg/cp_fs1_edges"] # The instruction must have the vs2 field set to v0, with all other values for vs2 # reserved. @@ -1689,27 +2442,27 @@ normative_rule_definitions: # scalar conversion instructions. The conversions use the dynamic rounding mode in # frm, except for the rtz variants, which round towards zero. - name: vfcvt_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # A set of conversion instructions is provided to convert between narrower integer # and floating-point datatypes to a type of twice the width. - name: vfwcvt_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # These instructions have the same constraints on vector register overlap as other # widening instructions (see <<sec-widening>>). - name: vfwcvt_vreg_constr - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cmp_vd_vs2"] # A set of conversion instructions is provided to convert wider integer and # floating-point datatypes to a type of half the width. - name: vfncvt_op - coverpoint: [""] + coverpoint: ["Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rup_overflow"] # These instructions have the same constraints on vector register overlap as other # narrowing instructions (see <<sec-narrowing>>). - name: vfncvt_vreg_constr - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cmp_vd_vs2"] # Vector reduction operations take a vector register group of elements and a # scalar held in element 0 of a vector register, and perform a reduction using @@ -1721,22 +2474,44 @@ normative_rule_definitions: # reduction, but the scalar operand is always included regardless of the mask # values. - name: vreduction_scalar - coverpoint: [""] + coverpoint: + [ + "Vf16_vfredosum_vs_cg/cp_custom_vfredosum_ordered_sum", + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul2", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul2", + "Vx16_vmv_x_s_cg/cp_custom_voffgroup_vs2_lmul2", + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul4", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul4", + "Vx16_vmv_s_x_cg/cp_custom_voffgroup_vd_lmul8", + "Vx16_vredand_vs_cg/cp_custom_voffgroup_vs1_lmul8", + "Vx16_vwredsum_vs_cg/cp_custom_vreductionw_vd_vs1_emul_16", + "Vx16_vredand_vs_cg/cp_custom_element0Masked", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + "Vf16_vfadd_vv_cg/cp_vs1", + ] # The destination vector register can overlap the source operands, including the # mask register. - name: vreduction_vd_overlap_vs - coverpoint: [""] + coverpoint: + [ + "Vf16_vfadd_vv_cg/cp_vs1", + "Vf16_vfadd_vf_cg/cmp_vd_vs2", + "Vf16_vfadd_vv_cg/cmp_vd_vs1", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The other elements in the destination vector register ( 0 < index < # VLEN/SEW) are considered the tail and are managed with the current tail # agnostic/undisturbed policy. - name: vreduction_tail_agnostic - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # If vl=0, no operation is performed and the destination register is not updated. - name: vreduction_vl_0 - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vl_0"] # Traps on vector reduction instructions are always reported with a vstart of 0. - name: vreduction_trap @@ -1760,7 +2535,12 @@ normative_rule_definitions: vredor_op, vredxor_op, ] - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # Overflows wrap around on arithmetic sums. - names: @@ -1794,7 +2574,12 @@ normative_rule_definitions: # generating or propagating special values. When the operation is masked (vm=0), # the masked-off elements do not affect the result or the exception flags. - name: vfredosum_op - coverpoint: [""] + coverpoint: + [ + "Vf16_vfredosum_vs_cg/cp_custom_vfredosum_ordered_sum", + "Vf16_vfredosum_vs_cg/cp_custom_vfredosum_NAN_vl0", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + ] # The implementation must produce a result equivalent to a reduction tree composed # of binary operator nodes, with the inputs being elements from the source vector @@ -1813,56 +2598,67 @@ normative_rule_definitions: # using the dynamic rounding mode) to the standard floating-point format indicated # by SEW. - name: vfredusum_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs1_edges"] # The additive identity is +0.0 when rounding down (towards -{inf}) or -0.0 for # all other rounding modes. - name: vfredusum_additive_impl - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_csr_frm"] # The reduction tree structure must be deterministic for a given value in vtype # and vl. - name: vfredusum_redtree - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cr_vl_lmul_sew16"] # The vfredmin and vfredmax instructions reduce the scalar argument in vs1[0] and # active elements in vs2 using the minimumNumber and maximumNumber operations, # respectively. - names: [vfredmin_op, vfredmax_op] - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs1_edges"] # Widening forms of the sum reductions are provided that read and write a # double-width reduction result. The reduction of the SEW-width elements is # performed as in the single-width reduction case, with the elements in vs2 # promoted to 2*SEW bits before adding to the 2*SEW-bit accumulator. - name: vfwredosum_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs1_edges"] # Widening forms of the sum reductions are provided that read and write a # double-width reduction result. The reduction of the SEW-width elements is # performed as in the single-width reduction case, with the elements in vs2 # promoted to 2*SEW bits before adding to the 2*SEW-bit accumulator. - name: vfwredusum_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs1_edges"] # Vector mask-register logical operations operate on mask registers. Each element # in a mask register is a single bit, - name: vmask_maskreg - coverpoint: [""] + coverpoint: + [ + "Vx16_vmadc_vi_cg/cp_custom_vmask_write_lmulge1", + "Vx16_vmadc_vim_cg/cp_custom_vmask_write_v0_masked", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The destination vector register may be the same as either source vector # register. - name: vmask_vd_overlap_vs - coverpoint: [""] + coverpoint: + [ + "Vx16_vmadc_vim_cg/cp_custom_vmask_write_v0_masked", + "Vf16_vfadd_vf_cg/cmp_vd_vs2", + ] # As with other vector instructions, the elements with indices less than vstart # are unchanged, and vstart is reset to zero after execution. - name: vmask_vstart - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Vector mask logical instructions are always unmasked, - name: vmasklogical_unmasked - coverpoint: [""] + coverpoint: ["Vx16_vmadc_vim_cg/cp_custom_vmask_write_v0_masked"] # so there are no inactive elements, and the encodings with vm=0 are reserved. - name: vmasklogical_masked_rsv @@ -1871,7 +2667,7 @@ normative_rule_definitions: # Mask elements past vl, the tail elements, are always updated with a # tail-agnostic policy. - name: vmasklogical_tail_agnostic - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] # vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) @@ -1892,28 +2688,33 @@ normative_rule_definitions: vmorn_op, vmxnor_op, ] - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # The source operand is a single vector register holding mask register values as # described in <<sec-mask-register-layout>>. - name: vcpop_vs_single_vreg - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vs2"] # The vcpop.m instruction counts the number of mask elements of the active # elements of the vector source mask register that have the value 1 and writes the # result to a scalar x register. The operation can be performed under a mask, in # which case only the masked elements are counted. - name: vcpop_op - coverpoint: [""] + coverpoint: ["D_fclass_d_cg/cp_rd"] # The vcpop.m instruction writes x[rd] even if vl=0 (with the value 0, since no # mask elements are active). - name: vcpop_vl0 - coverpoint: [""] + coverpoint: ["D_fclass_d_cg/cp_rd", "Vf16_vfadd_vf_cg/cp_vl_0"] # Traps on vcpop.m are always reported with a vstart of 0. - name: vcpop_trap - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vcpop.m instruction will raise an illegal-instruction exception if vstart is # non-zero. @@ -1924,16 +2725,16 @@ normative_rule_definitions: # mask vector that has the value 1 and writes that element's index to a GPR. If no # active element has the value 1, -1 is written to the GPR. - name: vfirst_op - coverpoint: [""] + coverpoint: ["D_fclass_d_cg/cp_rd"] # The vfirst.m instruction writes x[rd] even if vl=0 (with the value -1, since no # mask elements are active). - name: vfirst_vl0 - coverpoint: [""] + coverpoint: ["D_fclass_d_cg/cp_rd", "Vf16_vfadd_vf_cg/cp_vl_0"] # Traps on vfirst are always reported with a vstart of 0. - name: vfirst_trap - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vfirst instruction will raise an illegal-instruction exception if vstart is # non-zero. @@ -1946,16 +2747,16 @@ normative_rule_definitions: # following active elements. If there is no set bit in the active elements of the # source vector, then all active elements in the destination are written with a 1. - name: vmsbf_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The tail elements in the destination mask register are updated under a # tail-agnostic policy. - name: vmsbf_tail_agnostic - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Traps on vmsbf.m are always reported with a vstart of 0. - name: vmsbf_trap - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vmsbf instruction will raise an illegal-instruction exception if vstart is # non-zero. @@ -1970,16 +2771,16 @@ normative_rule_definitions: # The vector mask set-including-first instruction is similar to set-before-first, # except it also includes the element with a set bit. - name: vmsif_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The tail elements in the destination mask register are updated under a # tail-agnostic policy. - name: vmsif_tail_agnostic - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Traps on vmsif.m are always reported with a vstart of 0. - name: vmsif_trap - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vmsif instruction will raise an illegal-instruction exception if vstart is # non-zero. @@ -1994,16 +2795,16 @@ normative_rule_definitions: # The vector mask set-only-first instruction is similar to set-before-first, # except it only sets the first element with a bit set, if any. - name: vmsof_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The tail elements in the destination mask register are updated under a # tail-agnostic policy. - name: vmsof_tail_agnostic - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # Traps on vmsof.m are always reported with a vstart of 0. - name: vmsof_trap - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vmsof instruction will raise an illegal-instruction exception if vstart is # non-zero. @@ -2024,11 +2825,11 @@ normative_rule_definitions: # If the result value would overflow the destination SEW, the least-significant # SEW bits are retained. - name: viota_op - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # Traps on viota.m are always reported with a vstart of 0, - name: viota_trap - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # An illegal-instruction exception is raised if vstart is non-zero. - name: viota_vstart_n0_ill @@ -2037,7 +2838,7 @@ normative_rule_definitions: # The destination register group cannot overlap the source register and, if # masked, cannot overlap the mask register (v0). - name: viota_vreg_constr - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cmp_vd_vs2"] # The vid.v instruction writes each element's index to the destination vector # register group, from 0 to vl-1. The instruction can be masked. Masking does not @@ -2046,7 +2847,7 @@ normative_rule_definitions: # If the result value would overflow the destination SEW, the least-significant # SEW bits are retained. - name: vid_op - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # The vs2 field of the instruction must be set to v0, otherwise the encoding is # reserved. @@ -2055,18 +2856,27 @@ normative_rule_definitions: # The instructions ignore LMUL and vector register groups. - names: [vmv-x-s_ignoreLMUL, vmv-s-x_ignoreLMUL] - coverpoint: [""] + coverpoint: + [ + "Vf16_vfmv_f_s_cg/cp_custom_fmv_fs_vs2_all_lmul_regs", + "Vf16_vfmv_s_f_cg/cp_custom_fmv_sf_vd_all_lmul_regs", + ] # The vmv.x.s instruction copies a single SEW-wide element from index 0 of the # source vector register to a destination integer register. If SEW > XLEN, the # least-significant XLEN bits are transferred and the upper SEW-XLEN bits are # ignored. If SEW < XLEN, the value is sign-extended to XLEN bits. - name: vmv-x-s_op - coverpoint: [""] + coverpoint: ["D_fclass_d_cg/cp_rd"] # vmv.x.s performs its operation even if vstart {ge} vl or vl=0. - names: [vmv-x-s_vstart_ge_vl, vmv-x-s_vl0] - coverpoint: [""] + coverpoint: + [ + "Vx16_vcpop_m_cg/cp_custom_gprWriting_vstart_eq_vl", + "D_fclass_d_cg/cp_rd", + "Vf16_vfadd_vf_cg/cp_vl_0", + ] # The vmv.s.x instruction copies the scalar integer register to element 0 of the # destination vector register. If SEW < XLEN, the least-significant bits are @@ -2075,12 +2885,12 @@ normative_rule_definitions: # ( 0 < index < VLEN/SEW) are treated as tail elements using the current # tail agnostic/undisturbed policy. - name: vmv-s-x_op - coverpoint: [""] + coverpoint: ["D_fcvt_d_w_cg/cp_rs1_edges"] # If vstart {ge} vl, no operation is performed and the destination register is not # updated. - name: vmv-s-x_vstart_ge_vl - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vl_0"] # The encodings corresponding to the masked versions (vm=0) of vmv.x.s and vmv.s.x # are reserved. @@ -2089,24 +2899,28 @@ normative_rule_definitions: # The instructions ignore LMUL and vector register groups. - names: [vfmv-f-s_ignoreLMUL, vfmv-s-f_ignoreLMUL] - coverpoint: [""] + coverpoint: + [ + "Vf16_vfmv_f_s_cg/cp_custom_fmv_fs_vs2_all_lmul_regs", + "Vf16_vfmv_s_f_cg/cp_custom_fmv_sf_vd_all_lmul_regs", + ] # The vfmv.f.s instruction copies a single SEW-wide element from index 0 of the # source vector register to a destination scalar floating-point register. - name: vfmv-f-s_op - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_fd"] # The vfmv.s.f instruction copies the scalar floating-point register to element 0 # of the destination vector register. The other elements in the destination vector # register ( 0 < index < VLEN/SEW) are treated as tail elements using the # current tail agnostic/undisturbed policy. - name: vfmv-s-f_op - coverpoint: [""] + coverpoint: ["Vf16_vfmv_f_s_cg/cp_custom_vfp_register_state_mstatus_dirty"] # If vstart {ge} vl, no operation is performed and the destination register is not # updated. - name: vfmv-s-f_vstart_ge_vl - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vl_0"] # The encodings corresponding to the masked versions (vm=0) of vfmv.f.s and # vfmv.s.f are reserved. @@ -2125,7 +2939,7 @@ normative_rule_definitions: vfslide1up_vstart_ge_vl, vfslide1down_vstart_ge_vl, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vl_0"] # The slide instructions may be masked, with mask element i controlling whether # destination element i is written. The mask undisturbed/agnostic policy is @@ -2139,7 +2953,7 @@ normative_rule_definitions: vfslide1up_mask, vfslide1down_mask, ] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # For vslideup, the value in vl specifies the maximum number of destination # elements that are written. The start index (OFFSET) for the destination can be @@ -2148,7 +2962,13 @@ normative_rule_definitions: # not truncated to SEW bits. Destination elements OFFSET through vl-1 are written # if unmasked and if OFFSET < vl. - name: vslideup_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + ] # The destination vector register group for vslideup cannot overlap the source # vector register group, otherwise the instruction encoding is reserved. @@ -2162,7 +2982,13 @@ normative_rule_definitions: # x register specified by rs1, or a 5-bit immediate, zero-extended to XLEN bits. # If XLEN > SEW, OFFSET is not truncated to SEW bits. - name: vslidedown_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + ] # The vslide1up instruction places the x register argument at location 0 of the # destination vector register group, provided that element 0 is active, otherwise @@ -2175,7 +3001,14 @@ normative_rule_definitions: # register elements updated with source values, and remaining elements past vl are # handled according to the current tail policy (<<sec-agnostic>>). - name: vslide1up-vx_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + ] # The vslide1up instruction requires that the destination vector register group # does not overlap the source vector register group. Otherwise, the instruction @@ -2186,7 +3019,7 @@ normative_rule_definitions: # The vfslide1up instruction is defined analogously to vslide1up, but sources its # scalar argument from an f register. - name: vslide1up-vf_op - coverpoint: [""] + coverpoint: ["D_fcvt_d_s_cg/cp_fs1_edges"] # The vslide1down instruction copies the first vl-1 active elements values from # index i+1 in the source vector register group to index i in the destination @@ -2200,39 +3033,56 @@ normative_rule_definitions: # sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are # copied over and the high SEW-XLEN bits are ignored. - name: vslide1down-vx_op - coverpoint: [""] + coverpoint: + [ + "D_fcvt_d_s_cg/cp_fs1_edges", + "D_fcvt_d_w_cg/cp_rs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vf16_vfadd_vf_cg/cr_vs2_fs1_edges_f_sew16", + "Vx16_vaadd_vx_cg/cr_vs2_rs1_edges", + ] # The vfslide1down instruction is defined analogously to vslide1down, but sources # its scalar argument from an f register. - name: vslide1down-vf_op - coverpoint: [""] + coverpoint: ["D_fcvt_d_s_cg/cp_fs1_edges"] # The index values in the second vector are treated as unsigned integers. - names: [vrgather_vs2_uint, vrgatherei16_vs2_uint] - coverpoint: [""] + coverpoint: + [ + "Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_gt_vl_lt_vlmax", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + ] # The source vector can be read at any index < VLMAX regardless of vl. - names: [vrgather_vs_ignore_vl, vrgatherei16_vs_ignore_vl] - coverpoint: [""] + coverpoint: + [ + "Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_gt_vl_lt_vlmax", + "Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_ge_vlmax", + ] # The maximum number of elements to write to the destination register is given by # vl, - names: [vrgather_vl, vrgatherei16_vl] - coverpoint: [""] + coverpoint: + ["Vf16_vfadd_vf_cg/cr_vl_lmul_sew16", "Vf16_vfadd_vf_cg/cp_vl_0"] # and the remaining elements past vl are handled according to the current tail # policy (<<sec-agnostic>>). - names: [vrgather_tail, vrgatherei16_tail] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cr_vtype_agnostic"] # The operation can be masked, and the mask undisturbed/agnostic policy is # followed for inactive elements. - names: [vrgather_mask, vrgatherei16_mask] - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_masking_edges"] # The vrgather.vv form uses SEW/LMUL for both the data and indices. - name: vrgather-vv_sew_lmul - coverpoint: [""] + coverpoint: + ["SmV_cg/cp_sew_lmul_vset_i_vli", "Vf16_vfadd_vf_cg/cr_vl_lmul_sew16"] # The vrgatherei16.vv form uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = # (16/SEW)*LMUL for the indices in vs1. @@ -2242,7 +3092,12 @@ normative_rule_definitions: # If an element index is out of range ( vs1[i] {ge} VLMAX ) then zero is returned # for the element value. - names: [vrgather_id_ge_VLMAX, vrgatherei16_id_ge_VLMAX] - coverpoint: [""] + coverpoint: + [ + "Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_ge_vlmax", + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_32", + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_64", + ] # Vector-scalar and vector-immediate forms of the register gather are also # provided. These read one element from the source vector at the given index, and @@ -2251,7 +3106,13 @@ normative_rule_definitions: # bits, are treated as unsigned integers. If XLEN > SEW, the index value is not # truncated to SEW bits. - names: [vrgather-vx_op, vrgather-vi_op] - coverpoint: [""] + coverpoint: + [ + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_32", + "Vx16_vrgather_vx_cg/cp_custom_vindexVX_rs1_not_truncated_64", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vadc_vim_cg/cr_vs2_imm_edges", + ] # For any vrgather instruction, the destination vector register group cannot # overlap with the source vector register groups, otherwise the instruction @@ -2265,7 +3126,12 @@ normative_rule_definitions: # elements of vd are treated as tail elements according to the current tail policy # (<<sec-agnostic>>). - name: vcompress_op - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vv_cg/cp_vs1_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # T`vcompress` is encoded as an unmasked instruction (vm=1). - name: vcompress_enc @@ -2312,11 +3178,11 @@ normative_rule_definitions: # The source and destination vector register numbers must be aligned appropriately # for the vector register group size, - name: vmv-nr-r_vreg_constr - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vd"] # encodings with other vector register numbers are reserved. - name: vmv-nr-r_unaligned_rsv - coverpoint: [""] + coverpoint: ["Vf16_vfadd_vf_cg/cp_vd"] # On a trap during a vector instruction (caused by either a synchronous exception # or an asynchronous interrupt), the existing *epc CSR is written with a pointer @@ -2327,19 +3193,19 @@ normative_rule_definitions: # Any of these extensions can be added to base ISAs with XLEN=32 or XLEN=64. - name: Zve_XLEN - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The Zve32f and Zve64x extensions depend on the Zve32x extension. - name: Zve32f_Zve64x_dependent_Zve32x - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The Zve64f extension depends on the Zve32f and Zve64x extensions. - name: Zve64f_dependent_Zve32f_Zve64x - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The Zve64d extension depends on the Zve64f extension. - name: Zve64d_dependent_Zve64f - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # All Zve* extensions have precise traps. - name: Zve_precise_traps @@ -2362,24 +3228,24 @@ normative_rule_definitions: # vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in # Zve64*. - name: Zve64_eew64_nsupport_vmulh - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # All Zve* extensions support all vector fixed-point arithmetic instructions # (<<sec-vector-fixed-point>>), except that vsmul.vv and vsmul.vx are # not included in EEW=64 in Zve64*. - name: Zve64_eew64_nsupport_vsmul - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # All Zve* extensions support all vector permutation instructions # (<<sec-vector-permute>>), except that Zve32x and Zve64x do not # include those with floating-point operands, and Zve64f does not include those # with EEW=64 floating-point operands. - name: Zve32x_Zve64x_nsupport_freg - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The Zve32x extension depends on the Zicsr extension. - name: Zve32x_dependent_Zicsr - coverpoint: [""] + coverpoint: ["SmV_cg/cp_vcsrrswc"] # The Zve32f and Zve64f extensions depend upon the F extension, and implement all # vector floating-point instructions (<<sec-vector-float>>) for @@ -2387,11 +3253,11 @@ normative_rule_definitions: # reduction operations (<<sec-vector-float-reduce>>) for EEW=32 are # supported. - names: [Zve32f_dependent_F, Zve64f_dependent_F] - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The misa.v bit is set for implementations providing misa and supporting V. - name: misa-V_op - coverpoint: [""] + coverpoint: ["SmV_cg/cp_misa_v_clear_set"] # The V vector extension has precise traps. - name: V_precise_traps @@ -2399,11 +3265,11 @@ normative_rule_definitions: # The V vector extension depends upon the Zvl128b and Zve64d extensions. - name: V_dependent_Zvl128b_Zve64d - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The V extension supports EEW of 8, 16, and 32, and 64. - name: V_supported_eew - coverpoint: [""] + coverpoint: ["Vx16_vaadd_vv_cg/cp_vs2_edges"] # The V extension supports the vector configuration instructions # (<<sec-vector-config>>). The V extension supports all vector load @@ -2419,7 +3285,7 @@ normative_rule_definitions: # supports all vector permutation instructions # (<<sec-vector-permute>>). - name: V_instr - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The V extension depends upon the F and D extensions, and implements all vector # floating-point instructions (<<sec-vector-float>>) for @@ -2432,7 +3298,7 @@ normative_rule_definitions: # The Zvfhmin extension depends on the Zve32f extension. - name: Zvfhmin_dependent_Zve32f - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # When the Zvfh extension is implemented, all instructions in # <<sec-vector-float>>, <<sec-vector-float-reduce>>, @@ -2444,25 +3310,25 @@ normative_rule_definitions: # integer-to-floating-point widening conversions (vfwcvt.f.x[u].v) become defined # when SEW=8. - name: Zvfh_instr - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The EEW=16 floating-point operands of these instructions use the binary16 # format. - name: Zvfh_eew16 - coverpoint: [""] + coverpoint: ["Vf16_vfncvt_rod_f_f_w_cg/cp_custom_vfncvt_rup_overflow"] # The Zvfh extension depends on the Zve32f and Zfhmin extensions. - name: Zvfh_dependent_Zve32f_Zfhmin - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # Vector instructions with EGS > VLMAX are reserved. - name: egs_ge_vlmax_rsv - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # When an operand is a vector of element groups, the vl setting must correspond to # an integer multiple of the element group size, with other values of vl reserved. - name: egs_vl_rsv - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # When element group instructions are present, an additional constraint is placed # on the setting of vl based on an AVL value (augmenting @@ -2470,14 +3336,14 @@ normative_rule_definitions: # by the implementation. When AVL > VLMAX, the value of vl must be set to # either VLMAX or a positive integer multiple of EGSMAX. - name: egs_vl_avl - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # The vtype SEW can be used to indicate or calculate the effective element size # (EEW) of one or more operands of an element group instruction. Where the operand # is an element group, SEW and EEW refer to the number of bits in each individual # element within a group not the number of bits in the group as a whole. - name: egs_sew_eew - coverpoint: [""] + coverpoint: ["implicit"] # The vtype LMUL setting can be used to indicate or calculate the effective length # multiplier (EMUL) for one or more operands. Element group instructions tend to @@ -2487,30 +3353,40 @@ normative_rule_definitions: # 1-element groups with EEW=32b. In this case, the input and output EMUL values # are equal even though the EEW settings differ by a factor of 4. - name: egs_lmul_emul - coverpoint: [""] + coverpoint: ["implicit"] # The element group width (EGW) is the number of bits in the element group as a # whole. For example, the SHA-256 instructions in the Zvknha extension operate on # an EGW of 128, with EGS=4 and EEW=32. It is possible to use LMUL to concatenate # multiple vector registers together to support larger EGW>VLEN. - name: egs_egw - coverpoint: [""] + coverpoint: ["implicit"] # The active elements can raise exceptions and update the destination vector # register group. - name: vector_active_element - coverpoint: [""] + coverpoint: + [ + "Vls16_vle16ff_v_cg/cp_custom_ffLS_update_vl", + "Vf16_vfadd_vf_cg/cp_masking_edges", + "Vx16_vaadd_vv_cg/cp_vs2_edges", + ] # If the Ztso extension is implemented, vector memory instructions additionally # follow RVTSO at the instruction level. - name: vector_ls_rvtso - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # For vnclipu/vnclip, the rounding mode is specified in the vxrm CSR. Rounding # occurs around the least-significant bit of the destination and before # saturation. - name: vnclipu_vnclip_rounding - coverpoint: [""] + coverpoint: + [ + "Vx16_vaadd_vx_cg/cr_vxrm_vs2_rs1_edges", + "Vx16_vssra_vi_cg/cr_vxrm_vs2_imm_edges", + "Vx16_vaadd_vv_cg/cr_vxrm_vs2_vs1_edges", + ] # Vector floating-point instructions require the presence of base scalar # floating-point extensions corresponding to the supported vector floating-point @@ -2521,15 +3397,20 @@ normative_rule_definitions: # so these instructions all operate on single vector registers regardless of the # setting of the vlmul field in vtype. They do not change the value of vlmul. - name: instrgrp_vmask_disregard_vlmul - coverpoint: [""] + coverpoint: + [ + "Vx16_vmadc_vi_cg/cp_custom_vmask_write_lmulge1", + "Vx16_vaadd_vv_cg/cr_vs2_vs1_edges", + ] # execution is always restarted from the beginning when resuming after a trap # handler. - name: viota_restart - coverpoint: [""] + coverpoint: ["D_fadd_d_cg/cp_asm_count"] # vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; # vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : # vs2[vs1[i]]; - name: vrgather-vv_op_vrgatherei16-vv_op - coverpoint: [""] + coverpoint: + ["Vx16_vrgather_vv_cg/cp_custom_vindexCorners_index_gt_vl_lt_vlmax"]