|
4 | 4 | {reg: [
|
5 | 5 | {bits: 7, name: 'opcode', attr: ['7', 'OP=0110011'], type: 8},
|
6 | 6 | {bits: 5, name: 'cd', attr: ['5', 'dest'], type: 2},
|
7 |
| - {bits: 3, name: 'funct3', attr: ['3', 'CSETMODE=000'], type: 8}, |
| 7 | + {bits: 3, name: 'funct3', attr: ['7', 'CSETMODE=111'], type: 8}, |
8 | 8 | {bits: 5, name: 'cs1', attr: ['5', 'src1'], type: 4},
|
9 |
| - {bits: 5, name: 'rs2', attr: ['5', 'CSETMODE=0011'], type: 3}, |
10 |
| - {bits: 7, name: 'funct7', attr: ['7', 'CSETMODE=0001000'], type: 3}, |
| 9 | + {bits: 5, name: 'rs2', attr: ['5', 'src2'], type: 3}, |
| 10 | + {bits: 7, name: 'funct7', attr: ['7', 'CSETMODE=0000110'], type: 3}, |
11 | 11 | ]}
|
12 | 12 | ....
|
0 commit comments