diff --git a/src/insns/cjal_jal_32bit.adoc b/src/insns/cjal_jal_32bit.adoc
index e3bed1f2..b4f10e01 100644
--- a/src/insns/cjal_jal_32bit.adoc
+++ b/src/insns/cjal_jal_32bit.adoc
@@ -1,6 +1,16 @@
 <<<
 //[#insns-cjal_jal-32bit,reftext="Jumps (CJAL, JAL), 32-bit encodings"]
 
+[#CJ,reftext="CJ"]
+==== CJ
+
+Expands to <<CJAL>> following the expansion rule for <<J>> expanding to <<JAL>> from cite:[riscv-unpriv-spec].
+
+[#J,reftext="J"]
+==== J
+
+Expands to <<JAL>> following the expansion rule from cite:[riscv-unpriv-spec].
+
 [#CJAL,reftext="CJAL"]
 ==== CJAL
 
diff --git a/src/insns/cjalr_jalr_32bit.adoc b/src/insns/cjalr_jalr_32bit.adoc
index 6ab8beb6..79a7c327 100644
--- a/src/insns/cjalr_jalr_32bit.adoc
+++ b/src/insns/cjalr_jalr_32bit.adoc
@@ -1,5 +1,15 @@
 <<<
 
+[#CJR,reftext="CJR"]
+==== CJR
+
+Expands to <<CJALR>> following the expansion rule for <<JR>> expanding to <<JARL>> from cite:[riscv-unpriv-spec].
+
+[#JR,reftext="JR"]
+==== JR
+
+Expands to <<JALR>> following the expansion rule from cite:[riscv-unpriv-spec].
+
 [#CJALR,reftext="CJALR"]
 ==== CJALR
 
diff --git a/src/instructions.adoc b/src/instructions.adoc
index 32ec6ce1..0dab8e15 100644
--- a/src/instructions.adoc
+++ b/src/instructions.adoc
@@ -255,7 +255,18 @@ include::img/jvtcreg.edn[]
 
 All instruction fetches from the jump vector table are checked against <<jvtc>>.
 
-See <<CM.CJALT>>, <<CM.JALT>>, <<CM.CJT>>, <<CM.JT>>.
+See <<CM_CJALT>>, <<CM_JALT>>, <<CM_CJT>>, <<CM_JT>>.
+
+If the access to the jump table succeeds, then the instructions execute as follows:
+
+* In capability mode
+** <<CM_JT>> executes as <<CJ>> or <<AUIPCC>>+<<CJR>>
+** <<CM_JALT>> executes as <<CJAL>> or <<AUIPCC>>+<<CJALR>>
+* In legacy mode
+** <<CM_JT>> executes as <<J>> or <<AUIPC>>+<<JR>>
+** <<CM_JALT>> executes as <<JAL>> or <<AUIPC>>+<<JALR>>
+
+As a result the capability metadata is retained in the <<pcc>> during execution.
 
 include::insns/zcmt_cmjalt.adoc[]