From 4e8651d687ab71d22488894cbe1bc7493e173506 Mon Sep 17 00:00:00 2001 From: Tom Aird <24192817+tomaird@users.noreply.github.com> Date: Tue, 10 Dec 2024 16:14:52 +0000 Subject: [PATCH] Clarify mtval wording (#468) The wording in this sentence was a bit ambiguous whether "it" referred to `mtval` or `mtval2`. It only made sense if it referred to `mtval`, but it's better if it's explicitly clear to avoid confusion. Co-authored-by: Tom Aird --- src/riscv-integration.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 08ea3119..9a799e3a 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -758,7 +758,7 @@ a CHERI fault taken into M-mode, <> is written with the MXLEN-bit effective address which caused the fault according to the existing rules for reporting load/store addresses from cite:[riscv-priv-spec]. In this case the TYPE field of <> shown in xref:mtval2-cheri-type[xrefstyle=short] is -set to {cheri_excep_type_data}. For all other CHERI faults it is set to zero. +set to {cheri_excep_type_data}. For all other CHERI faults <> is set to zero. The behavior of <> is otherwise as described in cite:[riscv-priv-spec].