From 643e79c2c37057462b08c646c2843b8c9157354b Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Mon, 3 Feb 2025 16:21:47 +0000 Subject: [PATCH] Stop using term executable vector (#516) Fixes https://github.com/riscv/riscv-cheri/issues/510 Co-authored-by: Andres Amaya Garcia --- src/csv/CHERI_CSR.csv | 2 +- src/riscv-integration.adoc | 6 +++--- src/scripts/generate_tables.py | 4 ++-- src/tables.adoc | 12 +++++++----- 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/csv/CHERI_CSR.csv b/src/csv/CHERI_CSR.csv index 40e6e0c8..9dfdc193 100644 --- a/src/csv/CHERI_CSR.csv +++ b/src/csv/CHERI_CSR.csv @@ -1,4 +1,4 @@ -"CLEN CSR","Address","Alias","Mode","Permissions","Reset Value","Action on XLEN write","Action on CLEN write","Executable Vector","Data Pointer","Unseal On Execution","Store full metadata","Prerequisites","Description","","","","","","","","","","","","","","","","","","","","","" +"CLEN CSR","Address","Alias","Mode","Permissions","Reset Value","Action on XLEN write","Action on CLEN write","Code Pointer","Data Pointer","Unseal On Execution","Store full metadata","Prerequisites","Description","","","","","","","","","","","","","","","","","","","","","" "dpcc","0x7b1","dpc","D","DRW","tag=0, otherwise undefined","Apply <>. Always update the CSR with <> even if the address didn't change.","Apply <> and update the CSR with the result if the address changed, direct write if address didn't change","✔","","✔","","Sdext","Debug Program Counter Capability","","","","","","","","","","","","","","","","","","","","","" diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index a154b1af..6db65d92 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -457,7 +457,7 @@ ISAs must support both {cheri_base_ext_name} and {cheri_default_ext_name}. ==== Machine Trap Vector Base Address Register (mtvec) The <> register is as defined in cite:[riscv-priv-spec]. It is an -MXLEN-bit register used as the executable vector jumped to when taking traps +MXLEN-bit register used as the code pointer jumped to when taking traps into machine mode. It is extended into <>. @@ -469,7 +469,7 @@ include::img/mtvecreg.edn[] The <> register is a renamed extension of <> that holds a capability. Its reset value is the <> capability. The capability -represents an executable vector. +represents a code pointer. .Machine-mode trap-vector base-capability register include::img/mtveccreg.edn[] @@ -877,7 +877,7 @@ hold capabilities or with other new functions. <> in the <> is ty ==== Supervisor Trap Vector Base Address Register (stvec) The <> register is as defined in cite:[riscv-priv-spec]. It is an -SXLEN-bit register used as the executable vector jumped to when taking traps +SXLEN-bit register used as the code pointer jumped to when taking traps into supervisor mode. It is extended into <>. .Supervisor trap-vector base-address register diff --git a/src/scripts/generate_tables.py b/src/scripts/generate_tables.py index 350f74d9..f3027c5e 100755 --- a/src/scripts/generate_tables.py +++ b/src/scripts/generate_tables.py @@ -592,7 +592,7 @@ def check(self,row): return row[self.header.index("CLEN CSR")] != "" class csr_exevectors(table): - cols = ["CLEN CSR", "Executable Vector", "Data Pointer", "Unseal On Execution"] + cols = ["CLEN CSR", "Code Pointer", "Data Pointer", "Unseal On Execution"] indices = [] def __init__(self, filename, header): @@ -614,7 +614,7 @@ def update(self, row): self.file.write(outStr+'\n') def check(self,row): - return row[self.header.index("Executable Vector")] == "✔" or \ + return row[self.header.index("Code Pointer")] == "✔" or \ row[self.header.index("Unseal On Execution")] == "✔" or \ row[self.header.index("Data Pointer")] == "✔" diff --git a/src/tables.adoc b/src/tables.adoc index b9ef0520..e213a6db 100644 --- a/src/tables.adoc +++ b/src/tables.adoc @@ -103,17 +103,19 @@ NOTE: Implementations which allow misa.C to be writable need to legalize *Xepcc* on _reading_ if the misa.C value has changed since the value was written as this can cause the read value of bit [1] to change state. -.CLEN-wide CSRs storing executable vectors or data pointers +.CLEN-wide CSRs storing code pointers or data pointers [#CSR_exevectors] [width="100%",options=header,cols="1,1,1,1"] |============================================================================== include::generated/csr_exevectors_table_body.adoc[] |============================================================================== -Some CSRs store executable vectors or data pointers as shown in xref:CSR_exevectors[xrefstyle=short]. -These CSRs do not need to store the full width address on RV64. -If they store fewer address bits then writes are subject to the invalid address -check in <>. +Some CSRs store code pointers or data pointers as shown in xref:CSR_exevectors[xrefstyle=short]. +These are WARL CSRs that do not need to store full 64-bit addresses on RV64, and so need not be capable +of holding all possible invalid addresses. Prior to writing an invalid address to these CSRs, +the address must be converted to another invalid address that the CSR is capable of holding. +CSRs that store fewer address bits are also subject to the invalid address +check in <> on writing. .CLEN-wide CSRs which store all CLEN+1 bits [#CSR_metadata]