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Remove C prefix from capability mode load/store/atomics (#87)
First phase of renaming for #80 This commit handles Loads/stores/atomics. Prefetch, CBO, jumps, shxadd to be done in a follow-up change.
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Diff for: ‎src/csv/CHERI_ISA.csv

+57-84
Large diffs are not rendered by default.

Diff for: ‎src/insns/amo_32bit.adoc

+8-20
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,4 @@
11
<<<
2-
//[#insns-amo-32bit,reftext="Atomic (CAMO<OP>.W, CAMO<OP>.D, AMO<OP>.W, AMO<OP>.D), 32-bit encodings"]
3-
4-
5-
[#CAMOOPW,reftext="CAMO<OP>.W"]
6-
==== CAMO<OP>.W
7-
8-
See <<AMOOPD>>.
9-
10-
[#CAMOOPD,reftext="CAMO<OP>.D"]
11-
==== CAMO<OP>.D
12-
13-
See <<AMOOPD>>.
142

153
[#AMOOPW,reftext="AMO<OP>.W"]
164
==== AMO<OP>.W
@@ -20,16 +8,16 @@ See <<AMOOPD>>.
208
<<<
219

2210
[#AMOOPD,reftext="AMO<OP>.D"]
23-
==== CAMO<OP>.W
11+
==== AMO<OP>.W
2412

2513
Synopsis::
26-
Atomic Operations (CAMO<OP>.W, CAMO<OP>.D, AMO<OP>.W, AMO<OP>.D), 32-bit encodings
14+
Atomic Operations (AMO<OP>.W, AMO<OP>.D), 32-bit encodings
2715

2816
Capability Mode Mnemonics (RV64)::
29-
`camo<op>.[w|d], offset(cs1)`
17+
`amo<op>.[w|d], offset(cs1)`
3018

3119
Capability Mode Mnemonics (RV32)::
32-
`camo<op>.w, offset(cs1)`
20+
`amo<op>.w, offset(cs1)`
3321

3422
Legacy Mode Mnemonics (RV64)::
3523
`amo<op>.[w|d], offset(rs1)`
@@ -48,11 +36,11 @@ Standard atomic instructions, authorised by the capability in <<ddc>>.
4836

4937
include::atomic_exceptions.adoc[]
5038

51-
Prerequisites for CAMO<OP>.W, CAMO<OP>.D::
52-
{cheri_base_ext_name}
39+
Prerequisites for Capability Mode AMO<OP>.W, AMO<OP>.D::
40+
{cheri_base_ext_name}, and A
5341

54-
Prerequisites for AMO<OP>.W, AMO<OP>.D::
55-
{cheri_legacy_ext_name}
42+
Prerequisites for Legacy Mode AMO<OP>.W, AMO<OP>.D::
43+
{cheri_legacy_ext_name}, and A
5644

5745
Capability Mode Operation::
5846
[source,SAIL,subs="verbatim,quotes"]

Diff for: ‎src/insns/amoswap_32bit_cap.adoc

+6-11
Original file line numberDiff line numberDiff line change
@@ -3,20 +3,15 @@
33
[#AMOSWAP_C,reftext="AMOSWAP.C"]
44
==== AMOSWAP.C
55

6-
See <<CAMOSWAP.C>>.
7-
8-
[#CAMOSWAP_C,reftext="CAMOSWAP.C"]
9-
==== CAMOSWAP.C
10-
116
NOTE: The RV64 encoding is intended to also allocate the encoding for AMOSWAP.Q for RV128.
127

138
Synopsis::
14-
Atomic Operations (CAMOSWAP.C, AMOSWAP.C), 32-bit encodings
9+
Atomic Operation (AMOSWAP.C), 32-bit encoding
1510

1611
include::xlen_variable_warning.adoc[]
1712

1813
Capability Mode Mnemonics::
19-
`camoswap.c, offset(cs1)`
14+
`amoswap.c, offset(cs1)`
2015

2116
Legacy Mode Mnemonics::
2217
`amoswap.c, offset(rs1)`
@@ -34,11 +29,11 @@ Atomic swap of capability type, authorised by the capability in <<ddc>>.
3429

3530
include::atomic_exceptions.adoc[]
3631

37-
Prerequisites for CAMOSWAP.C::
38-
{cheri_base_ext_name}
32+
Prerequisites for Capability Mode AMOSWAP.C::
33+
{cheri_base_ext_name}, and A
3934

40-
Prerequisites for AMOSWAP.C::
41-
{cheri_legacy_ext_name}
35+
Prerequisites for Legacy Mode AMOSWAP.C::
36+
{cheri_legacy_ext_name}, and A
4237

4338
Operation::
4439
+

Diff for: ‎src/insns/load_16bit.adoc

+12-21
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,4 @@
11
<<<
2-
//[#insns-load-16bit,reftext="Load (C.CLD, C.CLW, C.LD, C.LW), 16-bit encodings"]
3-
4-
[#C_CLD,reftext="C.CLD"]
5-
==== C.CLD
6-
See <<C_LW>>.
7-
8-
[#C_CLW,reftext="C.CLW"]
9-
==== C.CLW
10-
See <<C_LW>>.
112

123
[#C_LD,reftext="C.LD"]
134
==== C.LD
@@ -19,13 +10,13 @@ See <<C_LW>>.
1910
==== C.LW
2011

2112
Synopsis::
22-
Load (C.CLD, C.CLW, C.LD, C.LW), 16-bit encodings
13+
Load (C.LD, C.LW), 16-bit encodings
2314

2415
Capability Mode Mnemonics (RV64)::
25-
`c.cld/c.clw rd', offset(cs1')`
16+
`c.ld/c.lw rd', offset(cs1')`
2617

2718
Capability Mode Expansions (RV64)::
28-
`cld/clw rd', offset(cs1')`
19+
`ld/lw rd', offset(cs1')`
2920

3021
Legacy Mode Mnemonics (RV64)::
3122
`c.ld/c.lw rd', offset(rs1')`
@@ -34,10 +25,10 @@ Legacy Mode Expansions (RV64)::
3425
`ld/lw rd', offset(rs1')`
3526

3627
Capability Mode Mnemonics (RV32)::
37-
`c.clw rd', offset(cs1')`
28+
`c.lw rd', offset(cs1')`
3829

3930
Capability Mode Expansions (RV32)::
40-
`clw rd', offset(cs1')`
31+
`lw rd', offset(cs1')`
4132

4233
Legacy Mode Mnemonics (RV32)::
4334
`c.lw rd', offset(rs1')`
@@ -56,17 +47,17 @@ Standard load instructions, authorised by the capability in <<ddc>>.
5647

5748
include::load_exceptions.adoc[]
5849

59-
Prerequisites C.CLD::
50+
Prerequisites for Capability Mode C.LD::
6051
RV64, and {c_cheri_base_ext_names}
6152

62-
Prerequisites C.CLW::
63-
{c_cheri_base_ext_names}
64-
65-
Prerequisites C.LD::
53+
Prerequisites for Legacy Mode C.LD::
6654
RV64, {c_cheri_legacy_ext_names}
6755

68-
Prerequisites C.LW::
56+
Prerequisites Capability Mode C.LW::
57+
{c_cheri_base_ext_names}
58+
59+
Prerequisites Legacy Mode C.LW::
6960
{c_cheri_legacy_ext_names}
7061

7162
Operation (after expansion to 32-bit encodings)::
72-
See <<CLD>>, <<CLW>>, <<LD>>, <<LW>>
63+
See <<LD>>, <<LW>>

Diff for: ‎src/insns/load_16bit_Zcb.adoc

+6-21
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,4 @@
11
<<<
2-
//[#insns-load-16bit-Zcb,reftext="Load (C.CLH, C.CLHU, C.CLBU, C.LH, C.LHU, C.LBU), 16-bit encodings"]
3-
4-
5-
6-
[#C_CLH,reftext="C.CLH"]
7-
==== C.CLH
8-
See <<C.LBU>>.
9-
10-
[#C_CLHU,reftext="C.CLHU"]
11-
==== C.CLHU
12-
See <<C.LBU>>.
13-
14-
[#C_CLBU,reftext="C.CLBU"]
15-
==== C.CLBU
16-
See <<C.LBU>>.
172

183
[#C_LH,reftext="C.LH"]
194
==== C.LH
@@ -29,13 +14,13 @@ See <<C.LBU>>.
2914
==== C.LBU
3015

3116
Synopsis::
32-
Load (C.CLH, C.CLHU, C.CLBU, C.LH, C.LHU, C.LBU), 16-bit encodings
17+
Load (C.LH, C.LHU, C.LBU), 16-bit encodings
3318

3419
Capability Mode Mnemonics::
35-
`c.clh/c.clhu/c.clbu rd', offset(cs1')`
20+
`c.lh/c.lhu/c.lbu rd', offset(cs1')`
3621

3722
Capability Mode Expansions::
38-
`clh/clhu/clbu rd, offset(cs1)`
23+
`lh/lhu/lbu rd, offset(cs1)`
3924

4025
Legacy Mode Mnemonics::
4126
`c.lh/c.lhu/c.lbu rd', offset(rs1')`
@@ -55,11 +40,11 @@ Subword load instructions, authorised by the capability in <<ddc>>.
5540

5641
include::load_exceptions.adoc[]
5742

58-
Prerequisites C.CLH, C.CLHU, C.CLBU::
43+
Prerequisites for Capability Mode::
5944
{c_cheri_base_ext_names}, and Zcb
6045

61-
Prerequisites C.LH, C.LHU, C.LBU::
46+
Prerequisites for Legacy Mode::
6247
{c_cheri_legacy_ext_names}, and Zcb
6348

6449
Operation (after expansion to 32-bit encodings)::
65-
See <<C.CLH>>, <<CLHU>>, <<CLBU>>, <<LH>>, <<LHU>>, <<LBU>>
50+
See <<LHU>>, <<LH>>, <<LBU>>

Diff for: ‎src/insns/load_16bit_cap_sprel.adoc

+9-10
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,21 @@
11
<<<
2-
//[#insns-load-16bit-cap-sprel,reftext="Load capability (C.CLC, C.CLCSP), 16-bit encodings"]
32

4-
[#C_CLC,reftext="C.CLC"]
5-
==== C.CLC
3+
[#C_LC,reftext="C.LC"]
4+
==== C.LC
65

7-
see <<C_CLCSP>>.
6+
see <<C_LCSP>>.
87

9-
[#C_CLCSP,reftext="C.CLCSP"]
10-
==== C.CLCSP
8+
[#C_LCSP,reftext="C.LCSP"]
9+
==== C.LCSP
1110

1211
Synopsis::
13-
Capability loads (C.CLC, C.CLCSP), 16-bit encodings
12+
Capability loads (C.LC, C.LCSP), 16-bit encodings
1413

1514
Capability Mode Mnemonics::
16-
`c.clc cd', offset(cs1'/csp)`
15+
`c.lc cd', offset(cs1'/csp)`
1716

1817
Capability Mode Expansions::
19-
`clc cd', offset(cs1'/csp)`
18+
`lc cd', offset(cs1'/csp)`
2019

2120
Encoding::
2221
include::wavedrom/c-sp-load-cap.adoc[]
@@ -32,4 +31,4 @@ Prerequisites::
3231
{c_cheri_base_ext_names}
3332

3433
Operation (after expansion to 32-bit encodings)::
35-
See <<CLC>>
34+
See <<LC>>

Diff for: ‎src/insns/load_16bit_fp_dp.adoc

+10-28
Original file line numberDiff line numberDiff line change
@@ -1,63 +1,45 @@
11
<<<
2-
//[#insns-load-16bit-fp-sprel,reftext="Load (C.CFLD, C.FLD, C.CFLDSP, C.FLDSP), 16-bit encodings"]
3-
4-
[#C_CFLD,reftext="C.CFLD"]
5-
==== C.CFLD
6-
7-
See <<C.FLDSP>>.
8-
92
[#C_FLD,reftext="C.FLD"]
103
==== C.FLD
114

125
See <<C.FLDSP>>.
136

14-
[#C_CFLDSP,reftext="C.CFLDSP"]
15-
==== C.CFLDSP
16-
17-
See <<C.FLDSP>>.
18-
197
<<<
208

219
[#C_FLDSP,reftext="C.FLDSP"]
2210
==== C.FLDSP
2311

2412
Synopsis::
25-
Double precision floating point loads (C.CFLD, C.FLD, C.CFLDSP, C.FLDSP), 16-bit encodings
13+
Double precision floating point loads (C.FLD, C.FLDSP), 16-bit encodings
2614

2715
Capability Mode Mnemonics (RV32)::
28-
`c.cfld frd', offset(cs1'/csp)`
16+
`c.fld frd', offset(cs1'/csp)`
2917

3018
Capability Mode Expansions (RV32)::
31-
`cfld frd', offset(csp)`
19+
`fld frd', offset(csp)`
3220

33-
Legacy Mode Mnemonics (RV32)::
21+
Legacy Mode Mnemonics::
3422
`c.fld fs2, offset(rs1'/sp)`
3523

36-
Legacy Mode Expansions (RV32)::
37-
`fld fs2, offset(rs1'/sp)`
38-
39-
Legacy Mode Mnemonics (RV64)::
40-
`c.fld fs2, offset(rs1'/sp)`
41-
42-
Legacy Mode Expansion (RV64)::
24+
Legacy Mode Expansions::
4325
`fld fs2, offset(rs1'/sp)`
4426

4527
Encoding::
4628
include::wavedrom/c-sp-load-css-dp.adoc[]
4729
include::wavedrom/c-sp-load-css-dp-sprel.adoc[]
4830

4931
Legacy Mode Description::
50-
Standard floating point stack pointer relative load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.CLC>>, <<C.CLCSP>>.
32+
Standard floating point stack pointer relative load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.LC>>, <<C.LCSP>>.
5133

5234
include::load_exceptions.adoc[]
5335

54-
Prerequisites for C.CFLD, C.CFLDSP (RV32 only)::
36+
Prerequisites for Capability Mode (RV32 only)::
5537
{cheri_base_ext_name}, C and D; or +
5638
{cheri_base_ext_name}, Zca and Zcd
5739

58-
Prerequisites for C.FLD, C.FLDSP::
59-
{cheri_base_ext_name}, C and D; or +
60-
{cheri_base_ext_name}, Zca and Zcd
40+
Prerequisites for Legacy Mode::
41+
{cheri_legacy_ext_name}, C and D; or +
42+
{cheri_legacy_ext_name}, Zca and Zcd
6143

6244
Operation (after expansion to 32-bit encodings)::
6345
See <<FLD>>

Diff for: ‎src/insns/load_16bit_fp_sp.adoc

+2-2
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@ include::wavedrom/c-sp-load-css-fp.adoc[]
2222
include::wavedrom/c-sp-load-css-fp-sprel.adoc[]
2323

2424
Legacy Mode Description::
25-
Standard floating point load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.CLC>>, <<C.CLCSP>>.
25+
Standard floating point load instructions, authorised by the capability in <<ddc>>. Note that these instructions are not available in Capability Mode, as they have been remapped to <<C.LC>>, <<C.LCSP>>.
2626

2727
include::load_exceptions.adoc[]
2828

29-
Prerequisites::
29+
Prerequisites for Legacy Mode::
3030
{c_cheri_legacy_ext_names}, and Zcf or F
3131

3232
Operation (after expansion to 32-bit encodings)::

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