From accfc3b02fdd7c91e5efeb5dfa3f83795ae37439 Mon Sep 17 00:00:00 2001 From: Axel Heider Date: Tue, 30 Jan 2024 20:54:13 +0100 Subject: [PATCH] clarify branches and x0/c0 --- src/insns/jalr_cap_32bit.adoc | 4 +++- src/riscv-integration.adoc | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/insns/jalr_cap_32bit.adoc b/src/insns/jalr_cap_32bit.adoc index 4ee92756..566c4211 100644 --- a/src/insns/jalr_cap_32bit.adoc +++ b/src/insns/jalr_cap_32bit.adoc @@ -29,7 +29,9 @@ include::wavedrom/ct-unconditional-jalr-cap.adoc[] Capability Mode Description:: JALR.PCC allows unconditional jumps to a target integer address. The target address in `rs1` is installed in the address field of the <>. The address -of the instruction following the jump (<> + 4) is written to `rd`. This is identical to the standard <> instruction, but with zero offset. +of the instruction following the jump (<> + 4) would be written to `rd`, but +since this is c0 the result is discarded. +This is identical to the standard <> instruction, but with zero offset. Legacy Mode Description:: JALR.CAP allows unconditional jumps to a target capability. The capability in diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 4af24e86..3e4ac951 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -177,7 +177,8 @@ for software to discover and/or control the behaviour# The indirect jump and link <> (<>) instruction allows unconditional jumps to a target address. The target address is provided in an *x* register; the new address is installed in the address field of the <>. The address of -the instruction following the jump (*pc* + 4) is written to an *x* register. +the instruction following the jump (*pc* + 4) is written to an *x* register, unless +it is x0, which causes the write to be discarded. <> causes an exception when a minimum sized instruction at the target address is not within the bounds of the <> or the target address is misaligned. @@ -223,7 +224,8 @@ The capability jump and link (<>) instruction replaces jump and link (<> sign-extends the offset and adds it to the address of the jump instruction to form the target address. The target address is installed in the address field of <>. The capability with the address of the -instruction following the jump (<> + 4) is written to a *c* register. +instruction following the jump (<> + 4) is written to a *c* register. In +case of c0, the capability write is discarded. The capability jump and link register (<>) instruction replaces the jump and link register (<>) instruction at the same encoding. This instruction