clarify exception priorities

Author: tariqkurd-repo

src/cheri-pte-ext.adoc

@@ -164,6 +164,7 @@ and the capability read from memory optionally has its tag set^1^.
  It is legal for the implementation to fault even if the tag is not set since this behavior is only an optimization for software.
  This means it is also legal to only check the tag under certain conditions and conservatively fault otherwise.
  Taking a trap when the tag is not set will introduce additional traps during revocation sweeps.
+ Checking the loaded tag affects the exception priority, see <<exception-priority>>.
 
 ^2^ See <<section_hardware_pte_updates>>.
 

src/riscv-integration.adoc

@@ -698,7 +698,7 @@ _Reserved_
 
 [[exception-priority]]
 .Synchronous exception priority in decreasing priority order. Entries added in {cheri_base_ext_name} are in *bold*
-[%autowidth,float="center",align="center",cols="<,>,<",options="header"]
+[float="center",align="center",cols="<1,>1,<8",options="header"]
 |===
 |Priority |Exc.Code |Description
 |_Highest_ |3 |Instruction address breakpoint
@@ -729,14 +729,21 @@ Load/store/AMO address breakpoint
 Optionally: +
 Load/store/AMO address misaligned
 | .>|13, 15, 5, 7 .<|During address translation for an explicit memory access: +
-First encountered page fault or access fault
+First encountered *CHERI PTE page fault*^12^, page fault or access fault
 | .>|5,7 .<|With physical address for an explicit memory access: +
 Load/store/AMO access fault
-.>|_Lowest_ .>|4,6 .<|If not higher priority: +
-Load/store/AMO address misaligned
+| .>|4,6 .<|If not higher priority: +
+.>|_Lowest_ .>|13 .<|If not higher priority: +
+CHERI load PTE fault^3^
 |===
 
-NOTE: The full details of the CHERI exceptions are in xref:cheri_exception_combs_descriptions[xrefstyle=short].
+^1^ The higher priority CHERI <<cheri_pte_ext,PTE>> page fault covers capability loads or atomics where the loaded tag _is not_ checked, and all capability stores and atomics where the stored tag is set.
+
+^2^ CHERI <<cheri_pte_ext,PTE>> page fault exceptions have the same priority against access faults as normal RISC-V page faults. If a normal RISC-V page fault _and_ a CHERI <<cheri_pte_ext,PTE>> fault are both detected, then the CHERI fault takes priority.
+
+^3^ The lower priority <<cheri_pte_ext,PTE>> fault only covers capability loads and atomics where the loaded tag _is_ checked.
+
+NOTE: The full details of the CHERI exceptions with cause value {cheri_excep_mcause} are in xref:cheri_exception_combs_descriptions[xrefstyle=short].
 
 [#medeleg,reftext="medeleg"]
 ==== Machine Trap Delegation Register (medeleg)

src/trigger-integration.adoc

@@ -7,7 +7,7 @@ shown in xref:trigger-exception-priority[xrefstyle=short].
 
 [[trigger-exception-priority]]
 .Synchronous exception priority (including triggers) in decreasing priority order. Entries added in {cheri_base_ext_name} are in *bold*
-[%autowidth,float="center",align="center",cols="<,>,<,<",options="header"]
+[float="center",align="center",cols="<1,>1,<4,<2",options="header"]
 |===
 |Priority |Exc. Code |Description |Trigger
 |_Highest_ |3 +
@@ -22,7 +22,7 @@ mcontrol/mcontrol6 after (on previous instruction)
 | .>|*{cheri_excep_mcause}* .<|*Prior to instruction address translation:* +
 *CHERI fault due to PCC checks (tag, execute permission, invalid address and bounds)* |
 | .>|12, 1 .<|During instruction address translation: +
-First encountered page fault or access fault |
+First encountered *CHERI PTE page fault*, page fault or access fault |
 | .>|1 .<|With physical address for instruction: +
 Instruction access fault |
 
@@ -49,10 +49,14 @@ Environment break |
 | .>|4,6 .<|Optionally: +
 Load/store/AMO address misaligned |
 | .>|13, 15, 5, 7 .<|During address translation for an explicit memory access: +
-First encountered page fault or access fault |
+First encountered *CHERI <<cheri_pte_ext,PTE>> page fault*, page fault or access fault |
 | .>|5,7 .<|With physical address for an explicit memory access: +
 Load/store/AMO access fault |
 |  .>|4,6 .<|If not higher priority: +
 Load/store/AMO address misaligned |
+| .>|13 .<|If not higher priority: +
+CHERI load <<cheri_pte_ext,PTE>> fault
 |_Lowest_ .>|3 .<| |mcontrol/mcontrol6 load data before
 |===
+
+NOTE: See the notes beneath <<exception-priority>> for details about CHERI <<cheri_pte_ext,PTE>> page fault priority.