From bd7f046f57b22150fa4df38cede33b0149567376 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Thu, 8 Feb 2024 13:34:32 +0100 Subject: [PATCH] remove .cap suffix from prefetch.* and cbo.* --- src/csv/CHERI_ISA.csv | 21 +++++++-------------- src/insns/cbo.clean.adoc | 17 ++++++----------- src/insns/cbo.flush.adoc | 15 +++++---------- src/insns/cbo.inval.adoc | 15 +++++---------- src/insns/cbo.zero.adoc | 15 +++++---------- src/insns/cbo_exceptions.adoc | 2 +- src/insns/prefetch.i.adoc | 14 +++++--------- src/insns/prefetch.r.adoc | 16 ++++++---------- src/insns/prefetch.w.adoc | 14 +++++--------- src/riscv-integration.adoc | 2 +- 10 files changed, 46 insertions(+), 85 deletions(-) diff --git a/src/csv/CHERI_ISA.csv b/src/csv/CHERI_ISA.csv index 7c567b24..252e12a8 100644 --- a/src/csv/CHERI_ISA.csv +++ b/src/csv/CHERI_ISA.csv @@ -76,20 +76,13 @@ "CSRRWI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR write - can also read/write a full capability through an address alias","CSR permission fault","","","","","","","" "CSRRSI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR set - can also read/write a full capability through an address alias","CSR permission fault","","","","","","","" "CSRRCI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR clear - can also read/write a full capability through an address alias","CSR permission fault","","","","","","","" -"CBO.INVAL","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block invalidate (implemented as clean), authorise with DDC","MODE>. - -[#CBO_CLEAN_CAP,reftext="CBO.CLEAN.CAP"] -==== CBO.CLEAN.CAP - Synopsis:: Perform a clean operation on a cache block Capability Mode Mnemonic:: -`cbo.clean.cap 0(cs1)` +`cbo.clean 0(cs1)` Legacy Mode Mnemonic:: `cbo.clean 0(rs1)` @@ -24,13 +19,13 @@ Encoding:: {bits: 7, name: 'opcode', attr: ['7','MISC-MEM=0001111'], type: 8}, {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.CLEAN.CAP=00.001', 'leg: CBO.CLEAN=00.001'], type: 3}, + {bits: 5, name: 'cs1/rs1', attr: ['5','base'] + {bits: 12, name: 'funct12', attr: ['12','CBO.CLEAN=00.001'], type: 3}, ]} .... Capability Mode Description:: -A CBO.CLEAN.CAP instruction performs a clean operation on the cache block +A CBO.CLEAN instruction performs a clean operation on the cache block whose effective address is the base address specified in `cs1`. The authorising capability for this operation is `cs1`. @@ -42,10 +37,10 @@ capability for this operation is <>. :cbo_clean_flush: include::cbo_exceptions.adoc[] -Prerequisites for CBO.CLEAN.CAP:: +Prerequisites for Capability Mode:: Zicbom, {cheri_base_ext_name} -Prerequisites for CBO.CLEAN:: +Prerequisites for Legacy Mode:: Zicbom, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo.flush.adoc b/src/insns/cbo.flush.adoc index 23edf3b7..3307543e 100644 --- a/src/insns/cbo.flush.adoc +++ b/src/insns/cbo.flush.adoc @@ -3,16 +3,11 @@ [#CBO_FLUSH,reftext="CBO.FLUSH"] ==== CBO.FLUSH -See <>. - -[#CBO_FLUSH_CAP,reftext="CBO.FLUSH.CAP"] -==== CBO.FLUSH.CAP - Synopsis:: Perform a flush operation on a cache block Capability Mode Mnemonic:: -`cbo.flush.cap 0(cs1)` +`cbo.flush 0(cs1)` Legacy Mode Mnemonic:: `cbo.flush 0(rs1)` @@ -25,12 +20,12 @@ Encoding:: {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.FLUSH.CAP=00.0010', 'leg: CBO.FLUSH=00.0010'], type: 3}, + {bits: 12, name: 'funct12', attr: ['12','cap: CBO.FLUSH=00.0010'], type: 3}, ]} .... Capability Mode Description:: -A CBO.FLUSH.CAP instruction performs a flush operation on the cache block +A CBO.FLUSH instruction performs a flush operation on the cache block whose effective address is the base address specified in `cs1`. The authorising capability for this operation is `cs1`. @@ -42,10 +37,10 @@ capability for this operation is <>. :cbo_clean_flush: include::cbo_exceptions.adoc[] -Prerequisites for CBO.FLUSH.CAP:: +Prerequisites for Capability Mode:: Zicbom, {cheri_base_ext_name} -Prerequisites for CBO.FLUSH:: +Prerequisites for Legacy Mode:: Zicbom, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo.inval.adoc b/src/insns/cbo.inval.adoc index bc8ce6cc..f1eb552d 100644 --- a/src/insns/cbo.inval.adoc +++ b/src/insns/cbo.inval.adoc @@ -3,16 +3,11 @@ [#CBO_INVAL,reftext="CBO.INVAL"] ==== CBO.INVAL -See <>. - -[#CBO_INVAL_CAP,reftext="CBO.INVAL.CAP"] -==== CBO.INVAL.CAP - Synopsis:: Perform an invalidate operation on a cache block Capability Mode Mnemonic:: -`cbo.inval.cap 0(cs1)` +`cbo.inval 0(cs1)` Legacy Mode Mnemonic:: `cbo.inval 0(rs1)` @@ -25,12 +20,12 @@ Encoding:: {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.INVAL.CAP=00.0000', 'leg: CBO.INVAL=00.0000'], type: 3}, + {bits: 12, name: 'funct12', attr: ['12','CBO.INVAL=00.0000'], type: 3}, ]} .... Capability Mode Description:: -A CBO.INVAL.CAP instruction performs an invalidate operation on the cache block +A CBO.INVAL instruction performs an invalidate operation on the cache block whose effective address is the base address specified in `cs1`. The authorising capability for this operation is `cs1`. @@ -42,10 +37,10 @@ authorising capability for this operation in <>. :cbo_inval: include::cbo_exceptions.adoc[] -Prerequisites for CBO.INVAL.CAP:: +Prerequisites for Capability Mode:: Zicbom, {cheri_base_ext_name} -Prerequisites for CBO.INVAL:: +Prerequisites for Legacy Mode:: Zicbom, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo.zero.adoc b/src/insns/cbo.zero.adoc index 9d3a5e1b..7487e727 100644 --- a/src/insns/cbo.zero.adoc +++ b/src/insns/cbo.zero.adoc @@ -3,16 +3,11 @@ [#CBO_ZERO,reftext="CBO.ZERO"] ==== CBO.ZERO -See <>. - -[#CBO_ZERO_CAP,reftext="CBO.ZERO.CAP"] -==== CBO.ZERO.CAP - Synopsis:: Store zeros to the full set of bytes corresponding to a cache block Capability Mode Mnemonic:: -`cbo.zero.cap 0(cs1)` +`cbo.zero 0(cs1)` Legacy Mode Mnemonic:: `cbo.zero 0(rs1)` @@ -25,12 +20,12 @@ Encoding:: {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.ZERO.CAP=00.0100', 'leg: CBO.ZERO=00.0100'], type: 3}, + {bits: 12, name: 'funct12', attr: ['12','CBO.ZERO=00.0100'], type: 3}, ]} .... Capability Mode Description:: -A `cbo.zero.cap` instruction performs stores of zeros to the full set of bytes +A `cbo.zero` instruction performs stores of zeros to the full set of bytes corresponding to the cache block whose effective address is the base address specified in `cs1`. An implementation may or may not update the entire set of bytes atomically although each individual write must atomically clear the tag @@ -47,10 +42,10 @@ for this operation is <>. include::store_exceptions.adoc[] -Prerequisites for CBO.ZERO.CAP:: +Prerequisites for Capability Mode:: Zicboz, {cheri_base_ext_name} -Prerequisites for CBO.ZERO:: +Prerequisites for Legacy Mode:: Zicboz, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo_exceptions.adoc b/src/insns/cbo_exceptions.adoc index 804625c5..c6707015 100644 --- a/src/insns/cbo_exceptions.adoc +++ b/src/insns/cbo_exceptions.adoc @@ -5,7 +5,7 @@ listed below; in this case, _CHERI data fault_ is reported in the <> or + ifdef::cbo_inval[] The CBIE bit in <> and <> indicates whether -CBO.INVAL.CAP and CBO.INVAL perform cache block flushes instead of +CBO.INVAL performs cache block flushes instead of invalidations for less privileged modes. The instruction checks shown in the table below remain unchanged regardless of the value of CBIE and the privilege mode. diff --git a/src/insns/prefetch.i.adoc b/src/insns/prefetch.i.adoc index 7a844e49..23df3475 100644 --- a/src/insns/prefetch.i.adoc +++ b/src/insns/prefetch.i.adoc @@ -2,17 +2,13 @@ [#PREFETCH_I,reftext="PREFETCH.I"] ==== PREFETCH.I -See <>. - -[#PREFETCH_I_CAP,reftext="PREFETCH.I.CAP"] -==== PREFETCH.I.CAP Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by an instruction fetch in the near future Capability Mode Mnemonic:: -`prefetch.i.cap offset(cs1)` +`prefetch.i offset(cs1)` Legacy Mode Mnemonic:: `prefetch.i offset(rs1)` @@ -25,13 +21,13 @@ Encoding:: {bits: 5, name: 'imm[4:0]', attr: ['5','zero'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','ORI=110'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'funct5', attr: ['5','cap: PREFETCH.I.CAP=00000', 'leg: PREFETCH.I=00000'], type: 3}, + {bits: 5, name: 'funct5', attr: ['5','PREFETCH.I=00000'], type: 3}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... Capability Mode Description:: -A PREFETCH.I.CAP instruction indicates to hardware that the cache block whose +A PREFETCH.I instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in `cs1` and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by an instruction fetch in the near future. The encoding @@ -54,10 +50,10 @@ is only valid if imm[4:0]=0. The authorising capability for this operation is <>. -Prerequisites for PREFETCH.I.CAP:: +Prerequisites for Capability Mode:: Zicbop, {cheri_base_ext_name} -Prerequisites for PREFETCH.I:: +Prerequisites for Legacy Mode:: Zicbop, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/prefetch.r.adoc b/src/insns/prefetch.r.adoc index 28c81592..307303a3 100644 --- a/src/insns/prefetch.r.adoc +++ b/src/insns/prefetch.r.adoc @@ -2,17 +2,13 @@ [#PREFETCH_R,reftext="PREFETCH.R"] ==== PREFETCH.R -See <>. - -[#PREFETCH_R_CAP,reftext="PREFETCH.R.CAP"] -==== PREFETCH.R.CAP Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by a data read in the near future Capability Mode Mnemonic:: -`prefetch.r.cap offset(cs1)` +`prefetch.r offset(cs1)` Legacy Mode Mnemonic:: `prefetch.r offset(rs1)` @@ -24,14 +20,14 @@ Encoding:: {bits: 7, name: 'opcode', attr: ['7','OP-IMM=0010011'], type: 8}, {bits: 5, name: 'imm[4:0]', attr: ['5','zero'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','ORI=110'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'funct5', attr: ['5','cap: PREFETCH.R.CAP=00001', 'leg: PREFETCH.R=00001'], type: 3}, + {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, + {bits: 5, name: 'funct5', attr: ['5','PREFETCH.R=00001'], type: 3}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... Capability Mode Description:: -A PREFETCH.R.CAP instruction indicates to hardware that the cache block whose +A PREFETCH.R instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in `cs1` and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data read (i.e. load) in the near future. The @@ -54,10 +50,10 @@ encoding is only valid if imm[4:0]=0. The authorising capability for this operation is <>. -Prerequisites for PREFETCH.R.CAP:: +Prerequisites for Capability Mode:: Zicbop, {cheri_base_ext_name} -Prerequisites for PREFETCH.R:: +Prerequisites for Legacy Mode:: Zicbop, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/prefetch.w.adoc b/src/insns/prefetch.w.adoc index ed845385..a1fcd95d 100644 --- a/src/insns/prefetch.w.adoc +++ b/src/insns/prefetch.w.adoc @@ -2,17 +2,13 @@ [#PREFETCH_W,reftext="PREFETCH.W"] ==== PREFETCH.W -See <>. - -[#PREFETCH_W_CAP,reftext="PREFETCH.W.CAP"] -==== PREFETCH.W.CAP Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by a data write in the near future Capability Mode Mnemonic:: -`prefetch.w.cap offset(cs1)` +`prefetch.w offset(cs1)` Legacy Mode Mnemonic:: `prefetch.w offset(rs1)` @@ -25,13 +21,13 @@ Encoding:: {bits: 5, name: 'imm[4:0]', attr: ['5','zero'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','ORI=110'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'funct5', attr: ['5','cap: PREFETCH.W.CAP=00011', 'leg: PREFETCH.W=00011'], type: 3}, + {bits: 5, name: 'funct5', attr: ['5','PREFETCH.W=00011'], type: 3}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... Capability Mode Description:: -A PREFETCH.W.CAP instruction indicates to hardware that the cache block whose +A PREFETCH.W instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in `cs1` and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data write (i.e. store) in the near future. The @@ -53,10 +49,10 @@ likely to be accessed by a data write (i.e. store) in the near future. The encoding is only valid if imm[4:0]=0. The authorising capability for this operation is <>. -Prerequisites for PREFETCH.W.CAP:: +Prerequisites for Capability Mode:: Zicbop, {cheri_base_ext_name} -Prerequisites for PREFETCH.W:: +Prerequisites for Legacy Mode:: Zicbop, {cheri_legacy_ext_name} Operation:: diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index c59bc6c6..7c2f6703 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -1083,7 +1083,7 @@ NOTE: `auth_cap` is <> for Legacy mode and `cs1` for Capability Mode NOTE: Indirect branches are <>, <>, <>, <>, conditional branches are <>. -NOTE: <>, <> issues as a cache block wide store. All +NOTE: <> issues as a cache block wide store. All CMOs operate on the cache block which contains the address. Prefetches check that the capability is tagged, not sealed, has the permission (<>, <>, <>) corresponding to the instruction, and has bounds which