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Signed-off-by: Tariq Kurd <[email protected]>
riscv · Dec 17, 2024 · f10751e · f10751e
1 parent b7e3169
commit f10751e
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/hypervisor-integration.adoc b/src/hypervisor-integration.adoc
@@ -75,7 +75,7 @@ part of {cheri_base_ext_name} when the hypervisor extension is supported. Its
 CSR address is 0x64b.
 
 <<htval2>> is updated following the same rules as <<mtval2>> for CHERI exceptions,
-load page fault and store/AMO page fault exceptions which are taken in HS-mode.
+load page fault and store page fault exceptions which are taken in HS-mode.
 
 The fields are identical to <<mtval2>> for CHERI exceptions.
 
@@ -196,7 +196,7 @@ include::img/vstdcreg.edn[]
 The <<vstval>> register is a VSXLEN-bit read-write register.
 
 <<vstval>> is updated following the same rules as <<mtval>> for CHERI exceptions,
-load page fault and store/AMO page faults which are taken in VS-mode.
+load page fault and store page faults which are taken in VS-mode.
 
 .Virtual supervisor trap value register
 [#vstval-format]