From f53f61161c2eeb8316c25ff1c8f2719af02483ff Mon Sep 17 00:00:00 2001 From: Andres Amaya Garcia Date: Wed, 12 Feb 2025 19:50:08 +0800 Subject: [PATCH] Revert MXLEN to XLEN in RV memory description --- src/riscv-integration.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 7ce638d0..2f260b31 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -26,14 +26,14 @@ privileged architecture specified in the RISC-V ISA. === Memory A hart supporting {cheri_base_ext_name} has a single byte-addressable address -space of 2^MXLEN^ bytes for all memory accesses. Each memory region capable of +space of 2^XLEN^ bytes for all memory accesses. Each memory region capable of holding a capability also stores a tag bit for each naturally aligned CLEN bits (e.g. 16 bytes in RV64), so that capabilities with their tag set can only be stored in naturally aligned addresses. Tags must be atomically bound to the data they protect. The memory address space is circular, so the byte at address -2^MXLEN^ - 1 is adjacent to the byte at address zero. A capability's +2^XLEN^ - 1 is adjacent to the byte at address zero. A capability's <> described in xref:section_cap_encoding[xrefstyle=short] is also circular, so address 0 is within the <> of a capability where address 2^MXLEN^ - 1 is within the bounds.