From 17823afaad07e334a263dae713d503a59972c420 Mon Sep 17 00:00:00 2001
From: Jay Williams <jay.williams@codasip.com>
Date: Mon, 13 Jan 2025 09:08:21 +0000
Subject: [PATCH] Fix observing CHERI execution mode code

---
 src/contributors.adoc             | 1 +
 src/riscv-hybrid-integration.adoc | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/contributors.adoc b/src/contributors.adoc
index ae6c02e3..14e6c255 100644
--- a/src/contributors.adoc
+++ b/src/contributors.adoc
@@ -36,5 +36,6 @@ This RISC-V specification has been contributed to directly or indirectly by:
 * Ricki Tura <ricki.tura@codasip.com>
 * Robert N. M. Watson <robert.watson@cl.cam.ac.uk>
 * Toby Wenman <toby.wenman@codasip.com>
+* Jay Williams  <jay.williams@codasip.com>
 * Jonathan Woodruff <jonathan.woodruff@cl.cam.ac.uk>
 * Jason Zhijingcheng Yu <yu.zhi@comp.nus.edu.sg>
diff --git a/src/riscv-hybrid-integration.adoc b/src/riscv-hybrid-integration.adoc
index 2035ac24..9e9016d3 100644
--- a/src/riscv-hybrid-integration.adoc
+++ b/src/riscv-hybrid-integration.adoc
@@ -109,7 +109,7 @@ for {cheri_cap_mode_name} and {INT_MODE_VALUE} for
 
 ```
 auipc c1, 0
-gctag x1, c1
+gcmode x1, c1
 ```
 
 [#section_hybrid_ext_instructions]