diff --git a/REUSE.toml b/REUSE.toml index e0f7534a3b..62b7efa34b 100644 --- a/REUSE.toml +++ b/REUSE.toml @@ -117,3 +117,10 @@ path = [ ] SPDX-FileCopyrightText = "Copyright (c) Jordan Carlin" SPDX-License-Identifier = "BSD-3-Clause-Clear" + +[[annotations]] +path = [ + "param_extraction/**", +] +SPDX-FileCopyrightText = "2025-2026 Contributors to the RISCV UnifiedDB " +SPDX-License-Identifier = "BSD-3-Clause-Clear" diff --git a/param_extraction/data/ground_truth.json b/param_extraction/data/ground_truth.json new file mode 100644 index 0000000000..89d3007d7a --- /dev/null +++ b/param_extraction/data/ground_truth.json @@ -0,0 +1,16463 @@ +{ + "metadata": { + "total_parameters": 185, + "source": "spec/std/isa/param", + "csr_source": "spec/std/isa/csr" + }, + "statistics": { + "by_classification": { + "NORM_CSR_RW": 55, + "NORM_CSR_WARL": 26, + "NORM_DIRECT": 102, + "SW_RULE": 2 + }, + "by_value_type": { + "binary": 111, + "bitmask": 5, + "conditional": 10, + "enum": 36, + "range": 12, + "set": 8, + "value": 3 + }, + "by_confidence": { + "high": 150, + "low": 16, + "medium": 19 + }, + "params_with_csr_references": 94, + "params_with_requirements": 40, + "top_defining_extensions": { + "H": 61, + "Sm": 38, + "S": 29, + "Sdtrig": 10, + "V": 7, + "Ssstateen": 7, + "Zcmt": 6, + "Smstateen": 6, + "U": 5, + "Ssaia": 4, + "Zalrsc": 4, + "F": 3, + "Zicfilp": 3, + "Zicfiss": 3, + "Zicbom": 2 + } + }, + "parameters": [ + { + "name": "ARCH_ID_VALUE", + "long_name": "Vendor-specific architecture ID in `marchid`", + "description": "The value of `marchid`\nThe combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is implemented.", + "defined_by": { + "extensions": ["Sm"], + "params": [ + { + "name": "MARCHID_IMPLEMENTED", + "condition": { + "equal": true + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Sm" + } + }, + { + "param": { + "name": "MARCHID_IMPLEMENTED", + "equal": true, + "reason": "When `marchid` is not implemented, its value is not relevant." + } + } + ] + }, + "summary": "ext:Sm AND param:MARCHID_IMPLEMENTED(equal=True)" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "value", + "details": { + "complex": "allOf" + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "value", + "details": { + "complex": "allOf" + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "marchid", + "field": "Architecture", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'ARCH_ID_VALUE'", + "source_file": "spec/std/isa/param/ARCH_ID_VALUE.yaml" + }, + { + "name": "ASID_WIDTH", + "long_name": "TODO", + "description": "Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 9 + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 16 + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'ASID_WIDTH'", + "source_file": "spec/std/isa/param/ASID_WIDTH.yaml" + }, + { + "name": "CACHE_BLOCK_SIZE", + "long_name": "TODO", + "description": "The observable size of a cache block, in bytes", + "defined_by": { + "extensions": ["Zicbom", "Zicbop", "Zicboz"], + "params": [], + "raw": { + "extension": { + "anyOf": [ + { + "name": "Zicbom" + }, + { + "name": "Zicbop" + }, + { + "name": "Zicboz" + } + ] + } + }, + "summary": "(ext:Zicbom OR ext:Zicbop OR ext:Zicboz)" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 18446744073709551615 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'CACHE_BLOCK_SIZE'", + "source_file": "spec/std/isa/param/CACHE_BLOCK_SIZE.yaml" + }, + { + "name": "CONFIG_PTR_ADDRESS", + "long_name": "Physical address in `mconfigptr`", + "description": "The value returned from `mconfigptr`", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm", + "version": ">= 1.12.0" + } + }, + "summary": "ext:Sm(>= 1.12.0)" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "value", + "details": { + "ref": "schema_defs.json#/$defs/uint32" + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "value", + "details": { + "ref": "schema_defs.json#/$defs/uint64" + } + } + } + ] + } + }, + "has_requirements": true, + "requirements_summary": "The pointer alignment in bits must be no smaller than MXLEN:\ni.e., if MXLEN is 8 x n, then mconfigptr[(log2(n)-1:0] must be zero.\n", + "csr_references": [ + { + "csr": "mconfigptr", + "field": "ADDRESS", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'CONFIG_PTR_ADDRESS'", + "source_file": "spec/std/isa/param/CONFIG_PTR_ADDRESS.yaml" + }, + { + "name": "COUNTINHIBIT_EN", + "long_name": "TODO", + "description": "Indicates which hardware performance monitor counters can be disabled from `mcountinhibit`.\n\nAn unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false,\nit would be illegal to set COUNTINHIBIT_EN[3] to true.\n\nCOUNTINHIBIT_EN[1] can never be true, since it corresponds to `mcountinhibit.TM`,\nwhich is always read-only-0.\n\nCOUNTINHIBIT_EN[3:31] must all be false if `Zihpm` is not implemented.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "bitmask", + "details": { + "length": 32 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mcountinhibit", + "field": "CY", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "CY", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "IR", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "IR", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM3", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM3", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM4", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM4", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM5", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM5", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM6", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM6", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM7", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM7", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM8", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM8", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM9", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM9", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM10", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM10", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM11", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM11", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM12", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM12", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM13", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM13", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM14", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM14", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM15", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM15", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM16", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM16", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM17", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM17", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM18", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM18", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM19", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM19", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM20", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM20", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM21", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM21", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM22", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM22", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM23", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM23", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM24", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM24", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM25", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM25", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM26", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM26", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM27", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM27", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM28", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM28", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM29", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM29", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM30", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM30", + "idl_key": "reset_value()" + }, + { + "csr": "mcountinhibit", + "field": "HPM31", + "idl_key": "type()" + }, + { + "csr": "mcountinhibit", + "field": "HPM31", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of mcountinhibit.CY", + "source_file": "spec/std/isa/param/COUNTINHIBIT_EN.yaml" + }, + { + "name": "DBG_HCONTEXT_WIDTH", + "long_name": "TODO", + "description": "Specifies the size of HCONTEXT", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 14 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "hcontext", + "field": "HCONTEXT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mcontext", + "field": "HCONTEXT", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of hcontext.HCONTEXT", + "source_file": "spec/std/isa/param/DBG_HCONTEXT_WIDTH.yaml" + }, + { + "name": "DBG_SCONTEXT_WIDTH", + "long_name": "TODO", + "description": "Specifies the size of SCONTEXT", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 32 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "scontext", + "field": "DATA", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of scontext.DATA", + "source_file": "spec/std/isa/param/DBG_SCONTEXT_WIDTH.yaml" + }, + { + "name": "DCSR_MPRVEN_TYPE", + "long_name": "TODO", + "description": "Implementation of dcsr.MPRVEN is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.MPRVEN bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["read-only-0", "read-only-1", "rw"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "dcsr", + "field": "MPRVEN", + "idl_key": "type()" + }, + { + "csr": "dcsr", + "field": "MPRVEN", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of dcsr.MPRVEN", + "source_file": "spec/std/isa/param/DCSR_MPRVEN_TYPE.yaml" + }, + { + "name": "DCSR_STEPIE_TYPE", + "long_name": "TODO", + "description": "Implementation of dcsr.STEPIE is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.STEPIE bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["read-only-0", "read-only-1", "rw"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "dcsr", + "field": "STEPIE", + "idl_key": "type()" + }, + { + "csr": "dcsr", + "field": "STEPIE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of dcsr.STEPIE", + "source_file": "spec/std/isa/param/DCSR_STEPIE_TYPE.yaml" + }, + { + "name": "DCSR_STOPCOUNT_TYPE", + "long_name": "TODO", + "description": "Implementation of dcsr.STOPCOUNT is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.STOPCOUNT bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["read-only-0", "read-only-1", "rw"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "dcsr", + "field": "STOPCOUNT", + "idl_key": "type()" + }, + { + "csr": "dcsr", + "field": "STOPCOUNT", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of dcsr.STOPCOUNT", + "source_file": "spec/std/isa/param/DCSR_STOPCOUNT_TYPE.yaml" + }, + { + "name": "DCSR_STOPTIME_TYPE", + "long_name": "TODO", + "description": "Implementation of dcsr.STOPTIME is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.STOPTIME bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["read-only-0", "read-only-1", "rw"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "dcsr", + "field": "STOPTIME", + "idl_key": "type()" + }, + { + "csr": "dcsr", + "field": "STOPTIME", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of dcsr.STOPTIME", + "source_file": "spec/std/isa/param/DCSR_STOPTIME_TYPE.yaml" + }, + { + "name": "ELEN", + "long_name": "TODO", + "description": "The maximum size in bits of a vector element that any operation can produce or consume.", + "defined_by": { + "extensions": ["V"], + "params": [], + "raw": { + "extension": { + "name": "V" + } + }, + "summary": "ext:V" + }, + "value_type": { + "type": "value", + "details": { + "base": "integer" + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'ELEN'", + "source_file": "spec/std/isa/param/ELEN.yaml" + }, + { + "name": "FOLLOW_VTYPE_RESET_RECOMMENDATION", + "long_name": "TODO", + "description": "It is recommended that at reset, vtype.vill is set, the remaining bits in vtype are zero, and vl is set to zero.\nIf this parameter is set to true, this recommendation is followed. If it is false, at reset the respective fields\nwill be UNDEFINED_LEGAL.", + "defined_by": { + "extensions": ["V"], + "params": [], + "raw": { + "extension": { + "name": "V" + } + }, + "summary": "ext:V" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "vl", + "field": "VALUE", + "idl_key": "reset_value()" + }, + { + "csr": "vtype", + "field": "VILL", + "idl_key": "reset_value()" + }, + { + "csr": "vtype", + "field": "VMA", + "idl_key": "reset_value()" + }, + { + "csr": "vtype", + "field": "VTA", + "idl_key": "reset_value()" + }, + { + "csr": "vtype", + "field": "VSEW", + "idl_key": "reset_value()" + }, + { + "csr": "vtype", + "field": "VLMUL", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Implementation behavioral choice parameter", + "source_file": "spec/std/isa/param/FOLLOW_VTYPE_RESET_RECOMMENDATION.yaml" + }, + { + "name": "FORCE_UPGRADE_CBO_INVAL_TO_FLUSH", + "long_name": "TODO", + "description": "When true, an implementation prohibits setting `menvcfg.CBIE` == `11` such that all `cbo.inval`\ninstructions either trap (when `menvcfg.CBIE` == '00') or flush (when `menvcfg.CBIE` == '01').\n\nWhen false, an implementation allows a true INVAL operation for `cbo.inval`, and thus supports\nthe setting `menvcfg.CBIE` == `11`.", + "defined_by": { + "extensions": ["Zicbom"], + "params": [], + "raw": { + "extension": { + "name": "Zicbom" + } + }, + "summary": "ext:Zicbom" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "menvcfg", + "field": "CBIE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of menvcfg.CBIE", + "source_file": "spec/std/isa/param/FORCE_UPGRADE_CBO_INVAL_TO_FLUSH.yaml" + }, + { + "name": "GSTAGE_MODE_BARE", + "long_name": "TODO", + "description": "Whether or not writing mode=Bare is supported in the `hgatp` register.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "# if host is 32 bit, then one of Bare or Sv32X4 must be supported\n$array_includes?(SXLEN, 32) && !SV32X4_TRANSLATION\n -> GSTAGE_MODE_BARE;\n\n# if host is 64 bit, then one of Bare, Sv39X4, Sv48x4, or S", + "csr_references": [ + { + "csr": "hgatp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of hgatp.MODE", + "source_file": "spec/std/isa/param/GSTAGE_MODE_BARE.yaml" + }, + { + "name": "HCONTEXT_AVAILABLE", + "long_name": "TODO", + "description": "Specifies if HCONTEXT is available", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "HCONTEXT cannot exist without MCONTEXT", + "csr_references": [ + { + "csr": "hcontext", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "hcontext", + "field": "HCONTEXT", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('AVAILABLE' suffix)", + "source_file": "spec/std/isa/param/HCONTEXT_AVAILABLE.yaml" + }, + { + "name": "HCOUNTENABLE_EN", + "long_name": "TODO", + "description": "Indicates which counters can delegated via `hcounteren`\n\nAn unimplemented counter cannot be specified, i.e., if\nHPM_COUNTER_EN[3] is false, it would be illegal to set\nHCOUNTENABLE_EN[3] to true.\n\nHCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.\nHCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "bitmask", + "details": { + "length": 32 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "hcounteren", + "field": "CY", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "CY", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "TM", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "TM", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "IR", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "IR", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM3", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM3", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM4", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM4", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM5", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM5", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM6", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM6", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM7", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM7", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM8", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM8", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM9", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM9", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM10", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM10", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM11", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM11", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM12", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM12", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM13", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM13", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM14", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM14", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM15", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM15", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM16", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM16", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM17", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM17", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM18", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM18", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM19", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM19", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM20", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM20", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM21", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM21", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM22", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM22", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM23", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM23", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM24", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM24", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM25", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM25", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM26", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM26", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM27", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM27", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM28", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM28", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM29", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM29", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM30", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM30", + "idl_key": "reset_value()" + }, + { + "csr": "hcounteren", + "field": "HPM31", + "idl_key": "type()" + }, + { + "csr": "hcounteren", + "field": "HPM31", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of hcounteren.CY", + "source_file": "spec/std/isa/param/HCOUNTENABLE_EN.yaml" + }, + { + "name": "HPM_COUNTER_EN", + "long_name": "TODO", + "description": "List of HPM counters that are enabled.\nThere is one entry for each hpmcounter.\n\nThe first three entries *must* be false (as they correspond to CY, IR, TM in, _e.g._ `mhmpcountinhibit`)\nIndex 3 in HPM_COUNTER_EN corresponds to hpmcounter3.\nIndex 31 in HPM_COUNTER_EN corresponds to hpmcounter31.", + "defined_by": { + "extensions": ["Smhpm"], + "params": [], + "raw": { + "extension": { + "name": "Smhpm" + } + }, + "summary": "ext:Smhpm" + }, + "value_type": { + "type": "bitmask", + "details": { + "length": 32 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "scountovf", + "field": "OF3", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF3", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF4", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF4", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF5", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF5", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF6", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF6", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF7", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF7", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF8", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF8", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF9", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF9", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF10", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF10", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF11", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF11", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF12", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF12", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF13", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF13", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF14", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF14", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF15", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF15", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF16", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF16", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF17", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF17", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF18", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF18", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF19", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF19", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF20", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF20", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF21", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF21", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF22", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF22", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF23", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF23", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF24", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF24", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF25", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF25", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF26", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF26", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF27", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF27", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF28", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF28", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF29", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF29", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF30", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF30", + "idl_key": "reset_value()" + }, + { + "csr": "scountovf", + "field": "OF31", + "idl_key": "type()" + }, + { + "csr": "scountovf", + "field": "OF31", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter12h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter12h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter12h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter8", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter8", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter8", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter30", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter30", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter30", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter26", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter26", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter26", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter10", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter10", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter10", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter4", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter4", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter4", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent18", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent18", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter10h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter10h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter10h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter9h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter9h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter9h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter29h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter29h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter29h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter14h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter14h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter14h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter30h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter30h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter30h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter11", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter11", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter11", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter5", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter5", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter5", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent23", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent23", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter27", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter27", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter27", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter31", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter31", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter31", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter16h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter16h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter16h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter9", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter9", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter9", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter16", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter16", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter16", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter11h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter11h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter11h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent4", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent4", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter13h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter13h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter13h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent24h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent24h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent19h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent19h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter20", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter20", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter20", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter21", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter21", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter21", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent5", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent5", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter17h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter17h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter17h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter15h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter15h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter15h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter8h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter8h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter8h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter28h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter28h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter28h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent3h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent3h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter17", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter17", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter17", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter3", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter3", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter3", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent25", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent25", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter31h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter31h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter31h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent22h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent22h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent13h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent13h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter4h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter4h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter4h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter24h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter24h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter24h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter14", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter14", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter14", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent26", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent26", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter19h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter19h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter19h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter22", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter22", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter22", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter26h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter26h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter26h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter6h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter6h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter6h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter18", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter18", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter18", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent6", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent6", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent7", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent7", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent15h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent15h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent9h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent9h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent28h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent28h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter19", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter19", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter19", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent11", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent11", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter23", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter23", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter23", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter22h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter22h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter22h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent27", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent27", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter20h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter20h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter20h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter15", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter15", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter15", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent31", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent31", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter24", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter24", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter24", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter27h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter27h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter27h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter7h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter7h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter7h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent10h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent10h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter28", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter28", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter28", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent12h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent12h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter18h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter18h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter18h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter6", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter6", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter6", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter12", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter12", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter12", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter5h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter5h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter5h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent20", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent20", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter25h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter25h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter25h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent21", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent21", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter21h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter21h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter21h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter7", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter7", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter7", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter13", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter13", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter13", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent16h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent16h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter29", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter29", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter29", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent29h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent29h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent14h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent14h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent8h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent8h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter3h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter3h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter3h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter23h", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter23h", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter23h", + "field": "COUNT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent30h", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent30h", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "OF", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "OF", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "MINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "MINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "SINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "SINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "UINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "UINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "VSINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "VSINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "VUINH", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "VUINH", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmevent17", + "field": "EVENT", + "idl_key": "type()" + }, + { + "csr": "mhpmevent17", + "field": "EVENT", + "idl_key": "reset_value()" + }, + { + "csr": "mhpmcounter25", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mhpmcounter25", + "field": "COUNT", + "idl_key": "type()" + }, + { + "csr": "mhpmcounter25", + "field": "COUNT", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of scountovf.OF3", + "source_file": "spec/std/isa/param/HPM_COUNTER_EN.yaml" + }, + { + "name": "HPM_EVENTS", + "long_name": "TODO", + "description": "List of defined event numbers that can be written into hpmeventN", + "defined_by": { + "extensions": ["Smhpm"], + "params": [], + "raw": { + "extension": { + "name": "Smhpm" + } + }, + "summary": "ext:Smhpm" + }, + "value_type": { + "type": "set", + "details": { + "element_type": "integer", + "min_items": null, + "max_items": null + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mhpmevent14", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent22", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent18", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent19", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent23", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent15", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent3", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent8", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent24", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent28", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent4", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent12", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent13", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent5", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent29", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent25", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent9", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent30", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent26", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent10", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent6", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent7", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent11", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent27", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent31", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent16", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent20", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent21", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mhpmevent17", + "field": "EVENT", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of mhpmevent14.EVENT", + "source_file": "spec/std/isa/param/HPM_EVENTS.yaml" + }, + { + "name": "HSTATEEN_AIA_TYPE", + "long_name": "TODO", + "description": "Behavior of the hstateen0.AIA bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["H", "Ssaia", "Ssstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Ssaia" + }, + { + "name": "H" + }, + { + "name": "Ssstateen" + } + ] + } + }, + "summary": "ext:Ssaia AND ext:H AND ext:Ssstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "HSTATEEN cannot have more options that MSTATEEN\nHSTATEEN cannot have more options that MSTATEEN\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'hstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/HSTATEEN_AIA_TYPE.yaml" + }, + { + "name": "HSTATEEN_CONTEXT_TYPE", + "long_name": "TODO", + "description": "Behavior of the hstateen0.CONTEXT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["H", "Sdtrig", "Ssstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Sdtrig" + }, + { + "name": "H" + }, + { + "name": "Ssstateen" + } + ] + } + }, + "summary": "ext:Sdtrig AND ext:H AND ext:Ssstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "When mstateen0.CONTEXT is read-only-0, hstateen0.CONTEXT must also be read-only-0\n\nWhen mstateen0.CONTEXT is read-only-1, hstateen0.CONTEXT must also be read-only-1\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'hstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml" + }, + { + "name": "HSTATEEN_CSRIND_TYPE", + "long_name": "TODO", + "description": "Behavior of the hstateen0.CSRIND bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["H", "Sscsrind", "Ssstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Sscsrind" + }, + { + "name": "H" + }, + { + "name": "Ssstateen" + } + ] + } + }, + "summary": "ext:Sscsrind AND ext:H AND ext:Ssstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "HSTATEEN cannot have more options that MSTATEEN\nHSTATEEN cannot have more options that MSTATEEN\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'hstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/HSTATEEN_CSRIND_TYPE.yaml" + }, + { + "name": "HSTATEEN_ENVCFG_TYPE", + "long_name": "TODO", + "description": "Behavior of the hstateen0.ENVCFG bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["H", "Ssstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "H", + "version": "~> 1.0" + }, + { + "name": "Ssstateen", + "version": "~> 1.0" + } + ] + } + }, + "summary": "ext:H(~> 1.0) AND ext:Ssstateen(~> 1.0)" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "When mstateen0.ENVCFG is read-only-0, hstateen0.ENVCFG must also be read-only-0\n\nWhen mstateen1.ENVCFG is read-only-1, hstateen0.ENVCFG must also be read-only-1\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'hstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/HSTATEEN_ENVCFG_TYPE.yaml" + }, + { + "name": "HSTATEEN_IMSIC_TYPE", + "long_name": "TODO", + "description": "Behavior of the hstateen0.IMSIC bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["H", "Ssaia", "Ssstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Ssaia" + }, + { + "name": "H" + }, + { + "name": "Ssstateen" + } + ] + } + }, + "summary": "ext:Ssaia AND ext:H AND ext:Ssstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "HSTATEEN cannot have more options that MSTATEEN\nHSTATEEN cannot have more options that MSTATEEN\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'hstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/HSTATEEN_IMSIC_TYPE.yaml" + }, + { + "name": "HSTATEEN_JVT_TYPE", + "long_name": "TODO", + "description": "Behavior of the hstateen0.JVT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["H", "Ssstateen", "Zcmt"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Zcmt" + }, + { + "name": "H" + }, + { + "name": "Ssstateen" + } + ] + } + }, + "summary": "ext:Zcmt AND ext:H AND ext:Ssstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "HSTATEEN cannot have more options that MSTATEEN\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'hstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/HSTATEEN_JVT_TYPE.yaml" + }, + { + "name": "HW_MSTATUS_FS_DIRTY_UPDATE", + "long_name": "TODO", + "description": "Indicates whether or not hardware will write to `mstatus.FS`\n\nValues are:\n[separator=\"!\"]\n!===\nh! never ! Hardware never writes `mstatus.FS`\nh! precise ! Hardware writes `mstatus.FS` to the Dirty (3) state precisely when F registers are modified\nh! imprecise ! Hardware writes `mstatus.FS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write FP state.\n!===", + "defined_by": { + "extensions": ["F"], + "params": [], + "raw": { + "extension": { + "name": "F" + } + }, + "summary": "ext:F" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["never", "precise", "imprecise"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "SD", + "idl_key": "type()" + } + ], + "classification": "SW_RULE", + "classification_confidence": "medium", + "classification_reasoning": "Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing", + "source_file": "spec/std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml" + }, + { + "name": "HW_MSTATUS_VS_DIRTY_UPDATE", + "long_name": "TODO", + "description": "Indicates whether or not hardware will write to `mstatus.VS`\n\nValues are:\n[separator=\"!\"]\n!===\nh! never ! Hardware never writes `mstatus.VS`\nh! precise ! Hardware writes `mstatus.VS` to the Dirty (3) state precisely when V registers are modified\nh! imprecise ! Hardware writes `mstatus.VS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write vector state.\n!===", + "defined_by": { + "extensions": ["V"], + "params": [], + "raw": { + "extension": { + "name": "V" + } + }, + "summary": "ext:V" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["never", "precise", "imprecise"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "SD", + "idl_key": "type()" + } + ], + "classification": "SW_RULE", + "classification_confidence": "medium", + "classification_reasoning": "Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing", + "source_file": "spec/std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml" + }, + { + "name": "IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO", + "long_name": "TODO", + "description": "Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are\nignored (as they are with satp), or if they are treated as WARL, leading to undpredictable\nbehavior.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "vsatp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "vsatp", + "field": "ASID", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "vsatp", + "field": "PPN", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of vsatp.MODE", + "source_file": "spec/std/isa/param/IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO.yaml" + }, + { + "name": "IMP_ID_VALUE", + "long_name": "Vendor-specific implementation ID in `mimpid`", + "description": "A unique encoding of the version of the processor implementation.", + "defined_by": { + "extensions": ["Sm"], + "params": [ + { + "name": "MIMPID_IMPLEMENTED", + "condition": { + "equal": true + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Sm" + } + }, + { + "param": { + "name": "MIMPID_IMPLEMENTED", + "equal": true, + "reason": "IMP_ID_VALUE is not needed if `mimpid` is not implemented." + } + } + ] + }, + "summary": "ext:Sm AND param:MIMPID_IMPLEMENTED(equal=True)" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "value", + "details": { + "ref": "schema_defs.json#/$defs/uint32" + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "value", + "details": { + "ref": "schema_defs.json#/$defs/uint64" + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mimpid", + "field": "Implementation", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'IMP_ID_VALUE'", + "source_file": "spec/std/isa/param/IMP_ID_VALUE.yaml" + }, + { + "name": "JVT_BASE_MASK", + "long_name": "Mask representing the implemented bits of jvt.BASE", + "description": "Mask representing the implemented bits of jvt.BASE.\nIncludes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0.", + "defined_by": { + "extensions": ["Zcmt"], + "params": [ + { + "name": "JVT_BASE_TYPE", + "condition": { + "equal": "mask" + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Zcmt" + } + }, + { + "param": { + "name": "JVT_BASE_TYPE", + "equal": "mask" + } + } + ] + }, + "summary": "ext:Zcmt AND param:JVT_BASE_TYPE(equal=mask)" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 64, + "maximum": 576460752303423487 + } + }, + "has_requirements": true, + "requirements_summary": "Includes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0.\n", + "csr_references": [ + { + "csr": "jvt", + "field": "BASE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of jvt.BASE", + "source_file": "spec/std/isa/param/JVT_BASE_MASK.yaml" + }, + { + "name": "JVT_BASE_TYPE", + "long_name": "Type of the jvt.BASE CSR field", + "description": "Type of the jvt.BASE CSR field. One of:\n\n* mask: jvt.BASE contains one or more implemented bits, which are indicated by JVT_BASE_MASK.\n* custom: Custom behavior. Will cause hart to enter 'unpredictable' state on a write to jvt.BASE.", + "defined_by": { + "extensions": ["Zcmt"], + "params": [], + "raw": { + "extension": { + "name": "Zcmt" + } + }, + "summary": "ext:Zcmt" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["mask", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "jvt", + "field": "BASE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of jvt.BASE", + "source_file": "spec/std/isa/param/JVT_BASE_TYPE.yaml" + }, + { + "name": "JVT_READ_ONLY", + "long_name": "Whether or not the JVT CSR is read-only", + "description": "If Zcmt is implemented, JVT is implemented, but can contain a read-only value", + "defined_by": { + "extensions": ["Zcmt"], + "params": [], + "raw": { + "extension": { + "name": "Zcmt" + } + }, + "summary": "ext:Zcmt" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "jvt", + "field": "BASE", + "idl_key": "type()" + }, + { + "csr": "jvt", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "jvt", + "field": "MODE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of jvt.MODE", + "source_file": "spec/std/isa/param/JVT_READ_ONLY.yaml" + }, + { + "name": "LRSC_FAIL_ON_NON_EXACT_LRSC", + "long_name": "TODO", + "description": "Whether or not a Store Conditional fails if its physical address and size do not\nexactly match the physical address and size of the last Load Reserved in program order\n(independent of whether or not the SC is in the current reservation set)", + "defined_by": { + "extensions": ["Zalrsc"], + "params": [], + "raw": { + "extension": { + "name": "Zalrsc" + } + }, + "summary": "ext:Zalrsc" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Load-reserved/store-conditional behavior parameter", + "source_file": "spec/std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml" + }, + { + "name": "LRSC_FAIL_ON_VA_SYNONYM", + "long_name": "TODO", + "description": "Whether or not an `sc.l`/`sc.d` will fail if its VA does not match the VA of the prior\n`lr.l`/`lr.d`, even if the physical address of the SC and LR are the same", + "defined_by": { + "extensions": ["Zalrsc"], + "params": [], + "raw": { + "extension": { + "name": "Zalrsc" + } + }, + "summary": "ext:Zalrsc" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Load-reserved/store-conditional behavior parameter", + "source_file": "spec/std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml" + }, + { + "name": "LRSC_MISALIGNED_BEHAVIOR", + "long_name": "TODO", + "description": "What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.\n\n * 'always raise misaligned exception': self-explainitory\n * 'always raise access fault': self-explainitory\n * 'custom': Custom behavior; misaligned LR/SC may sometimes raise a misaligned exception and sometimes raise a access fault. Will lead to an 'unpredictable' call on any misaligned LR/SC access", + "defined_by": { + "extensions": ["Zalrsc"], + "params": [], + "raw": { + "extension": { + "name": "Zalrsc" + } + }, + "summary": "ext:Zalrsc" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always raise misaligned exception", + "always raise access fault", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Load-reserved/store-conditional behavior parameter", + "source_file": "spec/std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml" + }, + { + "name": "LRSC_RESERVATION_STRATEGY", + "long_name": "TODO", + "description": "Strategy used to handle reservation sets.\n\n * \"reserve naturally-aligned 64-byte region\": Always reserve the 64-byte block containing the LR/SC address\n * \"reserve naturally-aligned 128-byte region\": Always reserve the 128-byte block containing the LR/SC address\n * \"reserve exactly enough to cover the access\": Always reserve exactly the LR/SC access, and no more\n * \"custom\": Custom behavior, leading to an 'unpredictable' call on any LR/SC", + "defined_by": { + "extensions": ["Zalrsc"], + "params": [], + "raw": { + "extension": { + "name": "Zalrsc" + } + }, + "summary": "ext:Zalrsc" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "reserve naturally-aligned 64-byte region", + "reserve naturally-aligned 128-byte region", + "reserve exactly enough to cover the access", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Load-reserved/store-conditional behavior parameter", + "source_file": "spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml" + }, + { + "name": "MARCHID_IMPLEMENTED", + "long_name": "Whether or not the `marchid` CSR is implemented.", + "description": "* false: `marchid` is not implemented, and must be read-only-0\n* true: `marchid` is implemented, and the value is determined by `ARCH_ID_VALUE`", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('IMPLEMENTED' suffix)", + "source_file": "spec/std/isa/param/MARCHID_IMPLEMENTED.yaml" + }, + { + "name": "MCID_WIDTH", + "long_name": "TODO", + "description": "Number of bits used for the Monitoring Counter ID field (MCID).\nDefault is 12.", + "defined_by": { + "extensions": ["Ssqosid"], + "params": [], + "raw": { + "extension": { + "name": "Ssqosid" + } + }, + "summary": "ext:Ssqosid" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 12 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "srmcfg", + "field": "MCID", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of srmcfg.MCID", + "source_file": "spec/std/isa/param/MCID_WIDTH.yaml" + }, + { + "name": "MCONTEXT_AVAILABLE", + "long_name": "TODO", + "description": "Specifies if MCONTEXT is available", + "defined_by": { + "extensions": ["Sdtrig"], + "params": [], + "raw": { + "extension": { + "name": "Sdtrig" + } + }, + "summary": "ext:Sdtrig" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mcontext", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "mcontext", + "field": "HCONTEXT", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('AVAILABLE' suffix)", + "source_file": "spec/std/isa/param/MCONTEXT_AVAILABLE.yaml" + }, + { + "name": "MCOUNTENABLE_EN", + "long_name": "TODO", + "description": "Indicates which counters can be delegated via `mcounteren`.\n\nAn unimplemented counter cannot be specified, i.e., if\nHPM_COUNTER_EN[3] is false, it would be illegal to set\nMCOUNTENABLE_EN[3] to true.\n\nMCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.\nMCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented.", + "defined_by": { + "extensions": ["U"], + "params": [], + "raw": { + "extension": { + "name": "U" + } + }, + "summary": "ext:U" + }, + "value_type": { + "type": "bitmask", + "details": { + "length": 32 + } + }, + "has_requirements": true, + "requirements_summary": "for (U32 i=3; i < 32; i++) {\n MCOUNTENABLE_EN[i] -> !implemented?(ExtensionName::Smhpm) || HPM_COUNTER_EN[i];\n}\n", + "csr_references": [ + { + "csr": "mcounteren", + "field": "CY", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "CY", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "IR", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "IR", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM3", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM3", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM4", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM4", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM5", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM5", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM6", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM6", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM7", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM7", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM8", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM8", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM9", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM9", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM10", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM10", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM11", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM11", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM12", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM12", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM13", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM13", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM14", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM14", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM15", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM15", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM16", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM16", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM17", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM17", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM18", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM18", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM19", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM19", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM20", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM20", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM21", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM21", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM22", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM22", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM23", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM23", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM24", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM24", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM25", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM25", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM26", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM26", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM27", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM27", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM28", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM28", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM29", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM29", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM30", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM30", + "idl_key": "reset_value()" + }, + { + "csr": "mcounteren", + "field": "HPM31", + "idl_key": "type()" + }, + { + "csr": "mcounteren", + "field": "HPM31", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of mcounteren.CY", + "source_file": "spec/std/isa/param/MCOUNTENABLE_EN.yaml" + }, + { + "name": "MIMPID_IMPLEMENTED", + "long_name": "Whether or not the `mimpid` CSR is implemented.", + "description": "* false: `mimpid` is not implemented, and must be read-only-0\n* true: `mimpid` is implemented, and the value is determined by `IMP_ID_VALUE`", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('IMPLEMENTED' suffix)", + "source_file": "spec/std/isa/param/MIMPID_IMPLEMENTED.yaml" + }, + { + "name": "MISALIGNED_AMO", + "long_name": "TODO", + "description": "whether or not the implementation supports misaligned atomics in main memory", + "defined_by": { + "extensions": ["Zaamo"], + "params": [], + "raw": { + "extension": { + "name": "Zaamo" + } + }, + "summary": "ext:Zaamo" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Misaligned access behavior parameter", + "source_file": "spec/std/isa/param/MISALIGNED_AMO.yaml" + }, + { + "name": "MISALIGNED_LDST", + "long_name": "Support for misaligned loads and stores to main memory.", + "description": "Does the implementation perform non-atomic misaligned loads and stores to main memory\n(does *not* affect misaligned support to device memory)?\nIf not, the implementation always throws a misaligned exception.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Misaligned access behavior parameter", + "source_file": "spec/std/isa/param/MISALIGNED_LDST.yaml" + }, + { + "name": "MISALIGNED_LDST_EXCEPTION_PRIORITY", + "long_name": "The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault\nor access-fault exceptions.", + "description": "The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault\nor access-fault exceptions.\n\nMay be one of:\n\n[separator=\"!\"]\n!===\n! low ! Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.\n! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.\n!===\n\nMISALIGNED_LDST_EXCEPTION_PRIORITY cannot be \"high\" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE\nis non-zero, since the atomicity of an access cannot be determined in that case until after\naddress translation.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["low", "high"] + } + }, + "has_requirements": true, + "requirements_summary": "MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be \"high\" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Misaligned access behavior parameter", + "source_file": "spec/std/isa/param/MISALIGNED_LDST_EXCEPTION_PRIORITY.yaml" + }, + { + "name": "MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE", + "long_name": "The maximum granule size, in bytes, that the hart can atomically perform a\nmisaligned load/store/AMO without raising a Misaligned exception", + "description": "When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart\ncannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can\natomically load/store/AMO a misaligned access that is fully contained in a\nMISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.\n\n[NOTE]\nEven if the hart is capable of performing a misaligned load/store/AMO atomically,\na misaligned exception may still occur if the access does not have the appropriate\nMisaligned Atomicity Granule PMA set.", + "defined_by": { + "extensions": ["Sm"], + "params": [ + { + "name": "MISALIGNED_LDST", + "condition": { + "equal": true + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Sm" + } + }, + { + "param": { + "name": "MISALIGNED_LDST", + "equal": true, + "reason": "Granule size is only relevant when misaligned load/stores might execute without an exception." + } + } + ] + }, + "summary": "ext:Sm AND param:MISALIGNED_LDST(equal=True)" + }, + "value_type": { + "type": "enum", + "details": { + "values": [0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096] + } + }, + "has_requirements": true, + "requirements_summary": "MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be \"high\" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Misaligned access behavior parameter", + "source_file": "spec/std/isa/param/MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE.yaml" + }, + { + "name": "MISALIGNED_SPLIT_STRATEGY", + "long_name": "The *order* the implementation appears\nto process a non-atomic misaligned load/store, which determines how/which\nexceptions will be reported.", + "description": "Options:\n\n * sequential_bytes: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address\n * custom: Something else. Will result in a call to unpredictable() in the execution", + "defined_by": { + "extensions": ["Sm"], + "params": [ + { + "name": "MISALIGNED_LDST", + "condition": { + "equal": true + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Sm" + } + }, + { + "param": { + "name": "MISALIGNED_LDST", + "equal": true, + "reason": "Granule size is only relevant when misaligned load/stores might execute without an exception." + } + } + ] + }, + "summary": "ext:Sm AND param:MISALIGNED_LDST(equal=True)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["sequential_bytes", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Misaligned access behavior parameter", + "source_file": "spec/std/isa/param/MISALIGNED_SPLIT_STRATEGY.yaml" + }, + { + "name": "MISA_CSR_IMPLEMENTED", + "long_name": "Whether or not the `misa` CSR is implemented", + "description": "Options:\n\n true::\n The `misa` CSR returns a non-zero value.\n\n false::\n The `misa` CSR is read-only-0.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "FS", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mstatus", + "field": "FS", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "VS", + "idl_key": "type()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('IMPLEMENTED' suffix)", + "source_file": "spec/std/isa/param/MISA_CSR_IMPLEMENTED.yaml" + }, + { + "name": "MSTATEEN_AIA_TYPE", + "long_name": "TODO", + "description": "Behavior of the mstateen0.AIA bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["Smstateen", "Ssaia"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Ssaia" + }, + { + "name": "Smstateen", + "version": "~> 1.0" + } + ] + } + }, + "summary": "ext:Ssaia AND ext:Smstateen(~> 1.0)" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'mstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/MSTATEEN_AIA_TYPE.yaml" + }, + { + "name": "MSTATEEN_CONTEXT_TYPE", + "long_name": "TODO", + "description": "Behavior of the mstateen0.CONTEXT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["Sdtrig", "Smstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Sdtrig" + }, + { + "name": "Smstateen" + } + ] + } + }, + "summary": "ext:Sdtrig AND ext:Smstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'mstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml" + }, + { + "name": "MSTATEEN_CSRIND_TYPE", + "long_name": "TODO", + "description": "Behavior of the mstateen0.CSRIND bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["Smstateen", "Sscsrind"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Sscsrind" + }, + { + "name": "Smstateen" + } + ] + } + }, + "summary": "ext:Sscsrind AND ext:Smstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'mstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/MSTATEEN_CSRIND_TYPE.yaml" + }, + { + "name": "MSTATEEN_ENVCFG_TYPE", + "long_name": "TODO", + "description": "Behavior of the mstateen0.ENVCFG bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["S", "Smstateen"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "S" + }, + { + "name": "Smstateen" + } + ] + } + }, + "summary": "ext:S AND ext:Smstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'mstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/MSTATEEN_ENVCFG_TYPE.yaml" + }, + { + "name": "MSTATEEN_IMSIC_TYPE", + "long_name": "TODO", + "description": "Behavior of the mstateen0.IMSIC bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["Smstateen", "Ssaia"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Ssaia" + }, + { + "name": "Smstateen", + "version": "~> 1.0" + } + ] + } + }, + "summary": "ext:Ssaia AND ext:Smstateen(~> 1.0)" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'mstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/MSTATEEN_IMSIC_TYPE.yaml" + }, + { + "name": "MSTATEEN_JVT_TYPE", + "long_name": "TODO", + "description": "Behavior of the mstateen0.JVT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["Smstateen", "Zcmt"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Zcmt" + }, + { + "name": "Smstateen", + "version": "~> 1.0" + } + ] + } + }, + "summary": "ext:Zcmt AND ext:Smstateen(~> 1.0)" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'mstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/MSTATEEN_JVT_TYPE.yaml" + }, + { + "name": "MSTATUS_FS_LEGAL_VALUES", + "long_name": "TODO", + "description": "The set of values that mstatus.FS supports.", + "defined_by": { + "extensions": ["F", "S"], + "params": [], + "raw": { + "extension": { + "anyOf": [ + { + "name": "F" + }, + { + "name": "S" + } + ] + } + }, + "summary": "(ext:F OR ext:S)" + }, + "value_type": { + "type": "set", + "details": { + "universe": [0, 1, 2, 3], + "min_items": 1, + "max_items": 4 + } + }, + "has_requirements": true, + "requirements_summary": "If there is a hardware update to mstatus.FS, then the Dirty state must be supported", + "csr_references": [ + { + "csr": "mstatus", + "field": "FS", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mstatus", + "field": "FS", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "FS", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of mstatus.FS", + "source_file": "spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml" + }, + { + "name": "MSTATUS_TVM_IMPLEMENTED", + "long_name": "TODO", + "description": "Whether or not mstatus.TVM is implemented.\n\nWhen not implemented mstatus.TVM will be read-only-zero.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "TVM", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mstatus", + "field": "TVM", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('IMPLEMENTED' suffix)", + "source_file": "spec/std/isa/param/MSTATUS_TVM_IMPLEMENTED.yaml" + }, + { + "name": "MSTATUS_VS_LEGAL_VALUES", + "long_name": "TODO", + "description": "The set of values that mstatus.VS will accept from a software write.", + "defined_by": { + "extensions": ["S", "V"], + "params": [], + "raw": { + "extension": { + "anyOf": [ + { + "name": "V" + }, + { + "name": "S" + } + ] + } + }, + "summary": "(ext:V OR ext:S)" + }, + "value_type": { + "type": "set", + "details": { + "universe": [0, 1, 2, 3], + "min_items": 1, + "max_items": 4 + } + }, + "has_requirements": true, + "requirements_summary": "If V is supported, both Off (0) and Dirty (3) must be supported\n\nIf there is a hardware update to mstatus.VS, then the Dirty state must be supported\n", + "csr_references": [ + { + "csr": "mstatus", + "field": "VS", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mstatus", + "field": "VS", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "VS", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of mstatus.VS", + "source_file": "spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml" + }, + { + "name": "MTVAL_WIDTH", + "long_name": "Width of the `mtval` CSR", + "description": "The number of implemented bits in the `mtval` CSR.\nThis is the CSR that may be written when a trap is taken into M-mode with exception-specific information to\nassist software in handling the trap (e.g., address associated with exception).\n\nMust be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `VA_SIZE`)", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 32 + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 64 + } + } + } + ] + } + }, + "has_requirements": true, + "requirements_summary": "`mtval` must be able to hold physical and/or virtual addresses\n", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Trap value reporting parameter", + "source_file": "spec/std/isa/param/MTVAL_WIDTH.yaml" + }, + { + "name": "MTVEC_ACCESS", + "long_name": "Acess type of the `mtvec` CSR (read-only or read-write).", + "description": "Options:\n\n ro::\n `mtvec` is read-only.\n\n rw::\n `mtvec` is read-write, but may not accept all values.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["ro", "rw"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mtvec", + "field": "BASE", + "idl_key": "type()" + }, + { + "csr": "mtvec", + "field": "MODE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of mtvec.BASE", + "source_file": "spec/std/isa/param/MTVEC_ACCESS.yaml" + }, + { + "name": "MTVEC_BASE_ALIGNMENT_DIRECT", + "long_name": "Minumum alignment of `mtvec.BASE` when `mtvec.MODE` is 0 (direct)", + "description": "Minimum alignment of the base pointer. Because `mtvec` excludes the two least-significant bits of\nthe base, the minimum alignment cannot be less than 4.", + "defined_by": { + "extensions": ["Sm"], + "params": [ + { + "name": "MTVEC_MODES", + "condition": { + "includes": 0 + } + }, + { + "name": "MTVEC_ACCESS", + "condition": { + "equal": "rw" + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Sm" + } + }, + { + "param": { + "allOf": [ + { + "name": "MTVEC_MODES", + "includes": 0, + "reason": "Only relevant when direct mode is supported" + }, + { + "name": "MTVEC_ACCESS", + "equal": "rw", + "reason": "Base address is hard-coded when MTVEC_ACCESS is read-only" + } + ] + } + } + ] + }, + "summary": "ext:Sm AND {'param': {'allOf': [{'name': 'MTVEC_MODES', 'includes': 0, 'reason': 'Only rele" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "enum", + "details": { + "values": [ + 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, + 16384, 32768, 65536, 131072, 262144, 524288, 1048576, + 2097152, 4194304, 8388608, 16777216, 33554432, 67108864, + 134217728, 268435456, 536870912, 1073741824, 2147483648 + ] + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "enum", + "details": { + "values": [ + 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, + 16384, 32768, 65536, 131072, 262144, 524288, 1048576, + 2097152, 4194304, 8388608, 16777216, 33554432, 67108864, + 134217728, 268435456, 536870912, 1073741824, 2147483648, + 4294967296, 8589934592, 17179869184, 34359738368, + 68719476736, 137438953472, 274877906944, 549755813888, + 1099511627776, 2199023255552, 4398046511104, 8796093022208, + 17592186044416, 35184372088832, 70368744177664, + 140737488355328, 281474976710656, 562949953421312, + 1125899906842624, 2251799813685248, 4503599627370496, + 9007199254740992, 18014398509481984, 36028797018963968, + 72057594037927936, 144115188075855872, 288230376151711744, + 576460752303423488, 1152921504606846976, + 2305843009213693952, 4611686018427387904, + 9223372036854775808 + ] + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_WARL", + "classification_confidence": "low", + "classification_reasoning": "Name pattern suggests CSR 'mtvec' association, but no IDL cross-reference found", + "source_file": "spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml" + }, + { + "name": "MTVEC_BASE_ALIGNMENT_VECTORED", + "long_name": "Minumum alignment of `mtvec.BASE` when `mtvec.MODE` is 1 (vectored)", + "description": "Because `mtvec` excludes the two least-significant bits of\nthe base, the minimum alignment cannot be less than 4.", + "defined_by": { + "extensions": ["Sm"], + "params": [ + { + "name": "MTVEC_MODES", + "condition": { + "includes": 1 + } + }, + { + "name": "MTVEC_ACCESS", + "condition": { + "equal": "rw" + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "Sm" + } + }, + { + "param": { + "allOf": [ + { + "name": "MTVEC_MODES", + "includes": 1, + "reason": "Only relevant when vectored mode is supported" + }, + { + "name": "MTVEC_ACCESS", + "equal": "rw", + "reason": "Base address is hard-coded when MTVEC_ACCESS is read-only" + } + ] + } + } + ] + }, + "summary": "ext:Sm AND {'param': {'allOf': [{'name': 'MTVEC_MODES', 'includes': 1, 'reason': 'Only rele" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "enum", + "details": { + "values": [ + 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, + 16384, 32768, 65536, 131072, 262144, 524288, 1048576, + 2097152, 4194304, 8388608, 16777216, 33554432, 67108864, + 134217728, 268435456, 536870912, 1073741824, 2147483648 + ] + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "enum", + "details": { + "values": [ + 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, + 16384, 32768, 65536, 131072, 262144, 524288, 1048576, + 2097152, 4194304, 8388608, 16777216, 33554432, 67108864, + 134217728, 268435456, 536870912, 1073741824, 2147483648, + 4294967296, 8589934592, 17179869184, 34359738368, + 68719476736, 137438953472, 274877906944, 549755813888, + 1099511627776, 2199023255552, 4398046511104, 8796093022208, + 17592186044416, 35184372088832, 70368744177664, + 140737488355328, 281474976710656, 562949953421312, + 1125899906842624, 2251799813685248, 4503599627370496, + 9007199254740992, 18014398509481984, 36028797018963968, + 72057594037927936, 144115188075855872, 288230376151711744, + 576460752303423488, 1152921504606846976, + 2305843009213693952, 4611686018427387904, + 9223372036854775808 + ] + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_CSR_WARL", + "classification_confidence": "low", + "classification_reasoning": "Name pattern suggests CSR 'mtvec' association, but no IDL cross-reference found", + "source_file": "spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml" + }, + { + "name": "MTVEC_ILLEGAL_WRITE_BEHAVIOR", + "long_name": "What happens when `mtvec` is written with an illegal value", + "description": "Options:\n\n retain::\n When either `mtvec.MODE` or `mtvec.BASE` is illegal, `mtvec` will retain its current value\n\n custom::\n When either `mtvec.MODE` or `mtvec.BASE` is illegal, `mtvec` will obtain an unpredictable value\n\nOther values may be added over time once other common behaviors are identified.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["retain", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mtvec", + "field": "BASE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mtvec", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of mtvec.BASE", + "source_file": "spec/std/isa/param/MTVEC_ILLEGAL_WRITE_BEHAVIOR.yaml" + }, + { + "name": "MTVEC_MODES", + "long_name": "Modes supported by `mtvec.MODE`", + "description": "Options:\n\n 0::\n Direct; All traps set `pc` to `mtvec.BASE`\n 1::\n Vectored; Asynchronous interrupts set `pc` to `mtvec.BASE` + 4 x cause.\n\nIf only one mode is given, `mtvec.MODE` is assumed to be read-only with that value.\nOtherwise, `mtvec.MODE` is read-write.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "set", + "details": { + "universe": [0, 1], + "min_items": 1, + "max_items": 2 + } + }, + "has_requirements": true, + "requirements_summary": "If `mtvec` is read-only, the mode cannot be changed.", + "csr_references": [ + { + "csr": "mtvec", + "field": "BASE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mtvec", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mtvec", + "field": "MODE", + "idl_key": "type()" + }, + { + "csr": "mtvec", + "field": "MODE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of mtvec.BASE", + "source_file": "spec/std/isa/param/MTVEC_MODES.yaml" + }, + { + "name": "MUTABLE_MISA_A", + "long_name": "TODO", + "description": "When the `A` extensions is supported, indicates whether or not\nthe extension can be disabled in the `misa.A` bit.", + "defined_by": { + "extensions": ["A"], + "params": [], + "raw": { + "extension": { + "name": "A" + } + }, + "summary": "ext:A" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "A", + "idl_key": "type()" + }, + { + "csr": "misa", + "field": "G", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.A", + "source_file": "spec/std/isa/param/MUTABLE_MISA_A.yaml" + }, + { + "name": "MUTABLE_MISA_B", + "long_name": "TODO", + "description": "Indicates whether or not the `B` extension can be disabled with the `misa.B` bit.", + "defined_by": { + "extensions": ["B"], + "params": [], + "raw": { + "extension": { + "name": "B" + } + }, + "summary": "ext:B" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "B", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.B", + "source_file": "spec/std/isa/param/MUTABLE_MISA_B.yaml" + }, + { + "name": "MUTABLE_MISA_C", + "long_name": "TODO", + "description": "Indicates whether or not the `C` extension can be disabled with the `misa.C` bit.", + "defined_by": { + "extensions": ["C"], + "params": [], + "raw": { + "extension": { + "name": "C" + } + }, + "summary": "ext:C" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "C", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.C", + "source_file": "spec/std/isa/param/MUTABLE_MISA_C.yaml" + }, + { + "name": "MUTABLE_MISA_D", + "long_name": "TODO", + "description": "Indicates whether or not the `D` extension can be disabled with the `misa.D` bit.", + "defined_by": { + "extensions": ["D"], + "params": [], + "raw": { + "extension": { + "name": "D" + } + }, + "summary": "ext:D" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "D", + "idl_key": "type()" + }, + { + "csr": "misa", + "field": "G", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.D", + "source_file": "spec/std/isa/param/MUTABLE_MISA_D.yaml" + }, + { + "name": "MUTABLE_MISA_F", + "long_name": "TODO", + "description": "Indicates whether or not the `F` extension can be disabled with the `misa.F` bit.", + "defined_by": { + "extensions": ["F"], + "params": [], + "raw": { + "extension": { + "name": "F" + } + }, + "summary": "ext:F" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "F", + "idl_key": "type()" + }, + { + "csr": "misa", + "field": "G", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.F", + "source_file": "spec/std/isa/param/MUTABLE_MISA_F.yaml" + }, + { + "name": "MUTABLE_MISA_H", + "long_name": "TODO", + "description": "Indicates whether or not the `H` extension can be disabled with the `misa.H` bit.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "If S mode can be disabled, then H mode must also be disabled since you can't be in H mode\nwithout S mode (and thus MUTABLE_MISA_H is not an option -- it's always true)\n", + "csr_references": [ + { + "csr": "misa", + "field": "H", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.H", + "source_file": "spec/std/isa/param/MUTABLE_MISA_H.yaml" + }, + { + "name": "MUTABLE_MISA_M", + "long_name": "TODO", + "description": "Indicates whether or not the `M` extension can be disabled with the `misa.M` bit.", + "defined_by": { + "extensions": ["M"], + "params": [], + "raw": { + "extension": { + "name": "M" + } + }, + "summary": "ext:M" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "G", + "idl_key": "type()" + }, + { + "csr": "misa", + "field": "M", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.G", + "source_file": "spec/std/isa/param/MUTABLE_MISA_M.yaml" + }, + { + "name": "MUTABLE_MISA_Q", + "long_name": "TODO", + "description": "Indicates whether or not the `Q` extension can be disabled with the `misa.Q` bit.", + "defined_by": { + "extensions": ["Q"], + "params": [], + "raw": { + "extension": { + "name": "Q" + } + }, + "summary": "ext:Q" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "Q", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.Q", + "source_file": "spec/std/isa/param/MUTABLE_MISA_Q.yaml" + }, + { + "name": "MUTABLE_MISA_S", + "long_name": "TODO", + "description": "Indicates whether or not the `S` extension can be disabled with the `misa.S` bit.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "If U-mode can be disabled, then S must also be disabled since S cannot exist without U (and thus there is no option for MUTABLE_MISA_S).", + "csr_references": [ + { + "csr": "misa", + "field": "S", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.S", + "source_file": "spec/std/isa/param/MUTABLE_MISA_S.yaml" + }, + { + "name": "MUTABLE_MISA_U", + "long_name": "TODO", + "description": "Indicates whether or not the `U` extension can be disabled with the `misa.U` bit.", + "defined_by": { + "extensions": ["U"], + "params": [], + "raw": { + "extension": { + "name": "U" + } + }, + "summary": "ext:U" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "U", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.U", + "source_file": "spec/std/isa/param/MUTABLE_MISA_U.yaml" + }, + { + "name": "MUTABLE_MISA_V", + "long_name": "TODO", + "description": "Indicates whether or not the `V` extension can be disabled with the `misa.V` bit.", + "defined_by": { + "extensions": ["V"], + "params": [], + "raw": { + "extension": { + "name": "V" + } + }, + "summary": "ext:V" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "misa", + "field": "V", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of misa.V", + "source_file": "spec/std/isa/param/MUTABLE_MISA_V.yaml" + }, + { + "name": "MXLEN", + "long_name": "XLEN in machine mode", + "description": "XLEN in machine mode, specified in bits", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [32, 64] + } + }, + "has_requirements": true, + "requirements_summary": "# if M-mode is rv32, then every mode must be rv32\nMXLEN == 32 -> xlen() == 32;\n\n# can't get in to rv64 anywhere unless MXLEN is 64\nxlen() == 64 -> MXLEN == 64;\n\n# if it's just M-mode, then xlen is alw", + "csr_references": [ + { + "csr": "satp", + "field": "ASID", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "mconfigptr", + "field": "ADDRESS", + "idl_key": "legal?(csr_value)" + }, + { + "csr": "misa", + "field": "MXL", + "idl_key": "reset_value()" + }, + { + "csr": "hcontext", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr32", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr24", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr49", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr4", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr28", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr53", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr12", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr8", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr45", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr44", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr9", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr13", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr52", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr29", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr5", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr48", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr25", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr33", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr38", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr55", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr14", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr43", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr34", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr63", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr22", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr59", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr18", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr2", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr3", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr19", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr58", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr23", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr62", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr35", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr42", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr15", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr54", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr39", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr41", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr16", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr57", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr0", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr20", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr61", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr36", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr37", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr60", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr21", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr1", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr56", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr17", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr40", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr6", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr26", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr30", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr47", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr10", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr51", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr50", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr11", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr46", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr31", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr27", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr7", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "vsatp", + "field": "ASID", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'MXLEN'", + "source_file": "spec/std/isa/param/MXLEN.yaml" + }, + { + "name": "M_MODE_ENDIANNESS", + "long_name": "Endianness of data in M-mode", + "description": "Options:\n\n[separator=\"!\"]\n!===\nh! little ! M-mode data is always little endian\nh! big ! M-mode data is always big endian\nh! dynamic ! M-mode data can be either little or big endian,\n depending on the CSR field `mstatus.MBE`\n!===", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["little", "big", "dynamic"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "MBE", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "MBE", + "idl_key": "reset_value()" + }, + { + "csr": "mstatush", + "field": "MBE", + "idl_key": "type()" + }, + { + "csr": "mstatush", + "field": "MBE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of mstatus.MBE", + "source_file": "spec/std/isa/param/M_MODE_ENDIANNESS.yaml" + }, + { + "name": "NUM_EXTERNAL_GUEST_INTERRUPTS", + "long_name": "TODO", + "description": "Number of supported virtualized guest interrupts\n\nCorresponds to the `GEILEN` parameter in the RVI specs", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 31 + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 63 + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "hstatus", + "field": "VGEIN", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hstatus", + "field": "VGEIN", + "idl_key": "type()" + }, + { + "csr": "hstatus", + "field": "VGEIN", + "idl_key": "legal?(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'NUM_EXTERNAL_GUEST_INTERRUPTS'", + "source_file": "spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml" + }, + { + "name": "NUM_PMP_ENTRIES", + "long_name": "TODO", + "description": "Number of implemented PMP entries. Can be any value between 0-64, inclusive.\n\nThe architecture mandates that the number of implemented PMP registers\nmust appear to be 0, 16, or 64.\n\nTherefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:\n\n[separator=\"!\"]\n!===\n! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15>\n! 0 ! N ! N\n! 1-16 ! Y ! N\n! 17-64 ! Y ! Y\n!===\n\n** N = Not implemented; access will cause `IllegalInstruction`\n if TRAP_ON_UNIMPLEMENTED_CSR is true\n** Y = Implemented; access will not cause an exception (from M-mode), but register\n may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register\n\n[NOTE]\n`pmpcfgN` for an odd N never exists when XLEN == 64\n\nWhen NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers,\nand associated pmpNcfg, will be read-only zero (but will never cause an exception).", + "defined_by": { + "extensions": ["Smpmp"], + "params": [], + "raw": { + "extension": { + "name": "Smpmp" + } + }, + "summary": "ext:Smpmp" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 64 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "pmpaddr32", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr32", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp56cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp57cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp58cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp59cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp60cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp61cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp62cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg14", + "field": "pmp63cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr24", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr24", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp16cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp17cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp18cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp19cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp20cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp21cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp22cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg4", + "field": "pmp23cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr49", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr49", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr4", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr4", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr28", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr28", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr53", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr53", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp32cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp33cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp34cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp35cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp36cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp37cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp38cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg8", + "field": "pmp39cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr12", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr12", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr8", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr8", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr45", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr45", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr44", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr44", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr9", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr9", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg9", + "field": "pmp36cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg9", + "field": "pmp37cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg9", + "field": "pmp38cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg9", + "field": "pmp39cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr13", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr13", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr52", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr52", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr29", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr29", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr5", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr5", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr48", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr48", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg5", + "field": "pmp20cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg5", + "field": "pmp21cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg5", + "field": "pmp22cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg5", + "field": "pmp23cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr25", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr25", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg15", + "field": "pmp60cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg15", + "field": "pmp61cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg15", + "field": "pmp62cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg15", + "field": "pmp63cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr33", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr33", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr38", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr38", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr55", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr55", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr14", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr14", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr43", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr43", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr34", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr34", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr63", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr63", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp48cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp49cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp50cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp51cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp52cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp53cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp54cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg12", + "field": "pmp55cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr22", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr22", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr59", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr59", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp8cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp9cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp10cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp11cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp12cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp13cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp14cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg2", + "field": "pmp15cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr18", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr18", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr2", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr2", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr3", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr3", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg3", + "field": "pmp12cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg3", + "field": "pmp13cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg3", + "field": "pmp14cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg3", + "field": "pmp15cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr19", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr19", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr58", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr58", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr23", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr23", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg13", + "field": "pmp52cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg13", + "field": "pmp53cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg13", + "field": "pmp54cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg13", + "field": "pmp55cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr62", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr62", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr35", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr35", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr42", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr42", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr15", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr15", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr54", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr54", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr39", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr39", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr41", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr41", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr16", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr16", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr57", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr57", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr0", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr0", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp0cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp1cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp2cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp3cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp4cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp5cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp6cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg0", + "field": "pmp7cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr20", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr20", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp40cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp41cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp42cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp43cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp44cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp45cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp46cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg10", + "field": "pmp47cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr61", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr61", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr36", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr36", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr37", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr37", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr60", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr60", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg11", + "field": "pmp44cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg11", + "field": "pmp45cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg11", + "field": "pmp46cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg11", + "field": "pmp47cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr21", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr21", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg1", + "field": "pmp4cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg1", + "field": "pmp5cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg1", + "field": "pmp6cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg1", + "field": "pmp7cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr1", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr1", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr56", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr56", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr17", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr17", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr40", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr40", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr6", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr6", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp24cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp25cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp26cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp27cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp28cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp29cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp30cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg6", + "field": "pmp31cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr26", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr26", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr30", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr30", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr47", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr47", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr10", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr10", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr51", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr51", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr50", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr50", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr11", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr11", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr46", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr46", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr31", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr31", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpaddr27", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr27", + "field": "ADDR", + "idl_key": "type()" + }, + { + "csr": "pmpcfg7", + "field": "pmp28cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg7", + "field": "pmp29cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg7", + "field": "pmp30cfg", + "idl_key": "type()" + }, + { + "csr": "pmpcfg7", + "field": "pmp31cfg", + "idl_key": "type()" + }, + { + "csr": "pmpaddr7", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr7", + "field": "ADDR", + "idl_key": "type()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'NUM_PMP_ENTRIES'", + "source_file": "spec/std/isa/param/NUM_PMP_ENTRIES.yaml" + }, + { + "name": "PHYS_ADDR_WIDTH", + "long_name": "Number of bits in a physical address", + "description": "Implementation-defined size of the physical address space.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 34 + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 64 + } + } + } + ] + } + }, + "has_requirements": true, + "requirements_summary": "without Sv32 translation, there is no way to create an address > 32 bits", + "csr_references": [ + { + "csr": "pmpaddr32", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr32", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr24", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr24", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr49", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr49", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr4", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr4", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr28", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr28", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr53", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr53", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr12", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr12", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr8", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr8", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr45", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr45", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr44", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr44", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr9", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr9", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr13", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr13", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr52", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr52", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr29", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr29", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr5", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr5", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr48", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr48", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr25", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr25", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr33", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr33", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr38", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr38", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr55", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr55", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr14", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr14", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr43", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr43", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr34", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr34", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr63", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr63", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr22", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr22", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr59", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr59", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr18", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr18", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr2", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr2", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr3", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr3", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr19", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr19", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr58", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr58", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr23", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr23", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr62", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr62", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr35", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr35", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr42", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr42", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr15", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr15", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr54", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr54", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr39", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr39", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr41", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr41", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr16", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr16", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr57", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr57", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr0", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr0", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr20", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr20", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr61", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr61", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr36", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr36", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr37", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr37", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr60", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr60", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr21", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr21", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr1", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr1", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr56", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr56", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr17", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr17", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr40", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr40", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr6", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr6", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr26", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr26", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr30", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr30", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr47", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr47", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr10", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr10", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr51", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr51", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr50", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr50", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr11", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr11", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr46", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr46", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr31", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr31", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr27", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr27", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr7", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr7", + "field": "ADDR", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'PHYS_ADDR_WIDTH'", + "source_file": "spec/std/isa/param/PHYS_ADDR_WIDTH.yaml" + }, + { + "name": "PMA_GRANULARITY", + "long_name": "log2 of the smallest supported PMA region", + "description": "Generally, for systems with an MMU, should not be smaller than 12,\nas that would preclude caching PMA results in the TLB along with\nvirtual memory translations", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 2, + "maximum": 66 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'PMA_GRANULARITY'", + "source_file": "spec/std/isa/param/PMA_GRANULARITY.yaml" + }, + { + "name": "PMLEN", + "long_name": "TODO", + "description": "The number of high-order bits of an address that are masked by the\npointer masking facility.", + "defined_by": { + "extensions": ["Smmpm", "Smnpm", "Ssnpm"], + "params": [], + "raw": { + "extension": { + "anyOf": [ + { + "name": "Smmpm" + }, + { + "name": "Smnpm" + }, + { + "name": "Ssnpm" + } + ] + } + }, + "summary": "(ext:Smmpm OR ext:Smnpm OR ext:Ssnpm)" + }, + "value_type": { + "type": "value", + "details": { + "base": "integer" + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'PMLEN'", + "source_file": "spec/std/isa/param/PMLEN.yaml" + }, + { + "name": "PMP_GRANULARITY", + "long_name": "TODO", + "description": "log2 of the smallest supported PMP region.\n\nGenerally, for systems with an MMU, should not be smaller than 12,\nas that would preclude caching PMP results in the TLB along with\nvirtual memory translations\n\nNote that PMP_GRANULARITY is equal to G+2 (not G) as described in\nthe privileged architecture.", + "defined_by": { + "extensions": ["Smpmp"], + "params": [], + "raw": { + "extension": { + "name": "Smpmp" + } + }, + "summary": "ext:Smpmp" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 2, + "maximum": 66 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "pmpaddr32", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg14", + "field": "pmp56cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp57cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp58cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp59cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp60cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp61cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp62cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg14", + "field": "pmp63cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr24", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg4", + "field": "pmp16cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp17cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp18cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp19cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp20cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp21cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp22cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg4", + "field": "pmp23cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr49", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr4", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr28", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr53", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg8", + "field": "pmp32cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp33cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp34cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp35cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp36cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp37cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp38cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg8", + "field": "pmp39cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr12", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr8", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr45", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr44", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr9", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg9", + "field": "pmp36cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg9", + "field": "pmp37cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg9", + "field": "pmp38cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg9", + "field": "pmp39cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr13", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr52", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr29", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr5", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr48", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg5", + "field": "pmp20cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg5", + "field": "pmp21cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg5", + "field": "pmp22cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg5", + "field": "pmp23cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr25", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg15", + "field": "pmp60cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg15", + "field": "pmp61cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg15", + "field": "pmp62cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg15", + "field": "pmp63cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr33", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr38", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr55", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr14", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr43", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr34", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr63", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg12", + "field": "pmp48cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp49cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp50cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp51cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp52cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp53cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp54cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg12", + "field": "pmp55cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr22", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr59", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg2", + "field": "pmp8cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp9cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp10cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp11cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp12cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp13cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp14cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg2", + "field": "pmp15cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr18", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr2", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr3", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg3", + "field": "pmp12cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg3", + "field": "pmp13cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg3", + "field": "pmp14cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg3", + "field": "pmp15cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr19", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr58", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr23", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg13", + "field": "pmp52cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg13", + "field": "pmp53cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg13", + "field": "pmp54cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg13", + "field": "pmp55cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr62", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr35", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr42", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr15", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr54", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr39", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr41", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr16", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr57", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr0", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg0", + "field": "pmp0cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp1cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp2cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp3cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp4cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp5cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp6cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg0", + "field": "pmp7cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr20", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg10", + "field": "pmp40cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp41cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp42cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp43cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp44cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp45cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp46cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg10", + "field": "pmp47cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr61", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr36", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr37", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr60", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg11", + "field": "pmp44cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg11", + "field": "pmp45cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg11", + "field": "pmp46cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg11", + "field": "pmp47cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr21", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg1", + "field": "pmp4cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg1", + "field": "pmp5cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg1", + "field": "pmp6cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg1", + "field": "pmp7cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr1", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr56", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr17", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr40", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr6", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg6", + "field": "pmp24cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp25cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp26cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp27cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp28cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp29cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp30cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg6", + "field": "pmp31cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr26", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr30", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr47", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr10", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr51", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr50", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr11", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr46", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr31", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpaddr27", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "pmpcfg7", + "field": "pmp28cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg7", + "field": "pmp29cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg7", + "field": "pmp30cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpcfg7", + "field": "pmp31cfg", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "pmpaddr7", + "field": "(csr-level)", + "idl_key": "sw_read()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'PMP_GRANULARITY'", + "source_file": "spec/std/isa/param/PMP_GRANULARITY.yaml" + }, + { + "name": "PRECISE_SYNCHRONOUS_EXCEPTIONS", + "long_name": "Whether or not all synchronous exceptions are precise.", + "description": "If false, any exception not otherwise mandated to precise (e.g., PMP violation)\nwill cause execution to enter an unpredictable state.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^PRECISE_)", + "source_file": "spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml" + }, + { + "name": "RCID_WIDTH", + "long_name": "TODO", + "description": "Number of bits used for the Resource Control ID field (RCID).\nDefault is 12.", + "defined_by": { + "extensions": ["Ssqosid"], + "params": [], + "raw": { + "extension": { + "name": "Ssqosid" + } + }, + "summary": "ext:Ssqosid" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 1, + "maximum": 12 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "srmcfg", + "field": "RCID", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of srmcfg.RCID", + "source_file": "spec/std/isa/param/RCID_WIDTH.yaml" + }, + { + "name": "REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "long_name": "TODO", + "description": "When true, `mtval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.\n\nWhen false, `mtval` is written with 0.", + "defined_by": { + "extensions": ["Zicfilp"], + "params": [], + "raw": { + "extension": { + "name": "Zicfilp" + } + }, + "summary": "ext:Zicfilp" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml" + }, + { + "name": "REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "long_name": "TODO", + "description": "When true, `mtval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into M-mode due to a shadow stack pop check instruction.\n\nWhen false, `mtval` is written with 0.", + "defined_by": { + "extensions": ["Zicfiss"], + "params": [], + "raw": { + "extension": { + "name": "Zicfiss" + } + }, + "summary": "ext:Zicfiss" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml" + }, + { + "name": "REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "long_name": "TODO", + "description": "When true, `stval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.\n\nWhen false, `stval` is written with 0.", + "defined_by": { + "extensions": ["Zicfilp"], + "params": [], + "raw": { + "extension": { + "name": "Zicfilp" + } + }, + "summary": "ext:Zicfilp" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml" + }, + { + "name": "REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "long_name": "TODO", + "description": "When true, `stval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into S-mode due to a shadow stack pop check instruction.\n\nWhen false, `stval` is written with 0.", + "defined_by": { + "extensions": ["Zicfiss"], + "params": [], + "raw": { + "extension": { + "name": "Zicfiss" + } + }, + "summary": "ext:Zicfiss" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml" + }, + { + "name": "REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "long_name": "TODO", + "description": "When true, `vstval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.\n\nWhen false, `vstval` is written with 0.", + "defined_by": { + "extensions": ["Zicfilp"], + "params": [], + "raw": { + "extension": { + "name": "Zicfilp" + } + }, + "summary": "ext:Zicfilp" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml" + }, + { + "name": "REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "long_name": "TODO", + "description": "When true, `vstval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into VS-mode due to a shadow stack pop check instruction.\n\nWhen false, `vstval` is written with 0.", + "defined_by": { + "extensions": ["Zicfiss"], + "params": [], + "raw": { + "extension": { + "name": "Zicfiss" + } + }, + "summary": "ext:Zicfiss" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml" + }, + { + "name": "REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION", + "long_name": "Whether or not `mtval` is written with the encoding of an instruction causing an IllegalInstruction exception", + "description": "Options:\n\n * true: `mtval` is written with the encoding of an instruction causing an IllegalInstruction exception\n * false: `mtval` is written with 0 when an instruction causes an IllegalInstruction exception.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION.yaml" + }, + { + "name": "REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION", + "long_name": "TODO", + "description": "When true, `stval` is written with the encoding of an instruction that causes an\n`IllegalInstruction` exception.\n\nWhen false `stval` is written with 0 when an `IllegalInstruction` exception occurs.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION.yaml" + }, + { + "name": "REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION", + "long_name": "TODO", + "description": "When true, `vstval` is written with the encoding of an instruction that causes an\n`IllegalInstruction` exception.\n\nWhen false `vstval` is written with 0 when an `IllegalInstruction` exception occurs.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION.yaml" + }, + { + "name": "REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION", + "long_name": "TODO", + "description": "When true, `vstval` is written with the encoding of an instruction that causes an\n`VirualInstruction` exception.\n\nWhen false `vstval` is written with 0 when an `VirtualInstruction` exception occurs.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION.yaml" + }, + { + "name": "REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `htval` is written with the Guest Physical Address, shifted right by 2, that\ncaused a `GuestPageFault` exception.\n\nWhen false, `htval` is written with 0 when a `GuestPageFault` exception occurs.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs.\n\nIf false, 0 will be written into htval/mtval2 on an instruction guest page fault.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htval", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtval2", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while\nwalking a VS-mode page table.\n\nIf false, 0 will be written into htval/mtval2 on an intermediate guest page fault.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htval", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtval2", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs.\n\nIf false, 0 will be written into htval/mtval2 on a load guest page fault.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htval", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtval2", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs.\n\nIf false, 0 will be written into htval/mtval2 on a store/amo guest page fault.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htval", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtval2", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_BREAKPOINT", + "long_name": "Whether or not `mtval` is written with the virtual PC of an EBREAK instruction.", + "description": "Options:\n\n * true: `mtval` is written with the virtual PC of an EBREAK instruction (same information as `mepc`).\n * false: `mtval` is written with 0 on an EBREAK instruction.\n\nRegardless, `mtval` is always written with a virtual PC when an external breakpoint is generated", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_BREAKPOINT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT", + "long_name": "Whether or not `mtval` is written with the virtual address of a fetch causing an access fault", + "description": "Options:\n\n * true: `mtval` is written with the virtual address of a fetch causing the access fault\n * false: `mtval` is written with 0 when a fetch causes an access fault", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED", + "long_name": "Whether or not `mtval` is written with the virtual address of a misaligned fetch", + "description": "Options:\n\n * true: `mtval` is written with the virtual address of a trapping misaligned fetch\n * false: `mtval` is written with 0 when a misaligned fetch traps", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `mtval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionPageFault`.\n\nWHen false, `mtval` is written with 0 when an instruction fetch causes an\n`InstructionPageFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT", + "long_name": "Whether or not `mtval` is written with the virtual address of a load causing an access fault", + "description": "Options:\n\n * true: `mtval` is written with the virtual address of a load causing the access fault\n * false: `mtval` is written with 0 when a load causes an access fault", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED", + "long_name": "Whether or not `mtval` is written with the virtual address of a misaligned load", + "description": "Options:\n\n * true: `mtval` is written with the virtual address of a trapping misaligned load.\n * false: `mtval` is written with 0 when a misaligned load traps.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `mtval` is written with the virtual address of a load when it causes a\n`LoadPageFault`.\n\nWHen false, `mtval` is written with 0 when a load causes a `LoadPageFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT", + "long_name": "Whether or not `mtval` is written with the virtual address of a store or AMO causing an access fault", + "description": "Options:\n\n * true: `mtval` is written with the virtual address of a store or AMO causing the access fault\n * false: `mtval` is written with 0 when a store or AMO causes an access fault", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED", + "long_name": "Whether or not `mtval` is written with the virtual address of a misaligned store or AMO", + "description": "Options:\n\n * true: `mtval` is written with the virtual address of a trapping misaligned store or AMO.\n * false: `mtval` is written with 0 when a misaligned store or AMO traps.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `mtval` is written with the virtual address of a store when it causes a\n`StoreAmoPageFault`.\n\nWHen false, `mtval` is written with 0 when a store causes a `StoreAmoPageFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_BREAKPOINT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual PC of the EBREAK instruction (same information as `mepc`).\n\nWhen false, `stval` is written with 0 on an EBREAK instruction.\n\nRegardless, `stval` is always written with a virtual PC when an external breakpoint is generated", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_BREAKPOINT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionAccessFault`.\n\nWHen false, `stval` is written with 0 when an instruction fetch causes an\n`InstructionAccessFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual PC when an instruction fetch is misaligned.\n\nWhen false, `stval` is written with 0 when an instruction fetch is misaligned.\n\nNote that when IALIGN=16 (i.e., when the `C` or one of the `Zc*` extensions are implemented),\nit is impossible to generate a misaligned fetch, and so this parameter has no effect.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionPageFault`.\n\nWHen false, `stval` is written with 0 when an instruction fetch causes an\n`InstructionPageFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual address of a load when it causes a\n`LoadAccessFault`.\n\nWHen false, `stval` is written with 0 when a load causes a `LoadAccessFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual address of a load instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `stval` is written with 0 when a load address is misaligned and\nMISALIGNED_LDST is false.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual address of a load when it causes a\n`LoadPageFault`.\n\nWHen false, `stval` is written with 0 when a load causes a `LoadPageFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual address of a store when it causes a\n`StoreAmoAccessFault`.\n\nWHen false, `stval` is written with 0 when a store causes a `StoreAmoAccessFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual address of a store instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `stval` is written with 0 when a store address is misaligned and\nMISALIGNED_LDST is false.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `stval` is written with the virtual address of a store when it causes a\n`StoreAmoPageFault`.\n\nWHen false, `stval` is written with 0 when a store causes a `StoreAmoPageFault`.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_BREAKPOINT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual PC of the EBREAK instruction (same information as `mepc`).\n\nWhen false, `vstval` is written with 0 on an EBREAK instruction.\n\nRegardless, `vstval` is always written with a virtual PC when an external breakpoint is generated.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_BREAKPOINT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionAccessFault`.\n\nWHen false, `vstval` is written with 0 when an instruction fetch causes an\n`InstructionAccessFault`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual PC when an instruction fetch is misaligned.\n\nWhen false, `vstval` is written with 0 when an instruction fetch is misaligned.\n\nNote that when IALIGN=16 (i.e., when the `C` or one of the `Zc*` extensions are implemented),\nit is impossible to generate a misaligned fetch, and so this parameter has no effect.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionPageFault`.\n\nWHen false, `vstval` is written with 0 when an instruction fetch causes an\n`InstructionPageFault`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual address of a load when it causes a\n`LoadAccessFault`.\n\nWHen false, `vstval` is written with 0 when a load causes a `LoadAccessFault`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual address of a load instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `vstval` is written with 0 when a load address is misaligned and\nMISALIGNED_LDST is false.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual address of a load when it causes a\n`LoadPageFault`.\n\nWHen false, `vstval` is written with 0 when a load causes a `LoadPageFault`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual address of a store when it causes a\n`StoreAmoAccessFault`.\n\nWHen false, `vstval` is written with 0 when a store causes a `StoreAmoAccessFault`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual address of a store instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `vstval` is written with 0 when a store address is misaligned and\nMISALIGNED_LDST is false.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED.yaml" + }, + { + "name": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT", + "long_name": "TODO", + "description": "When true, `vstval` is written with the virtual address of a store when it causes a\n`StoreAmoPageFault`.\n\nWHen false, `vstval` is written with 0 when a store causes a `StoreAmoPageFault`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^REPORT_)", + "source_file": "spec/std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT.yaml" + }, + { + "name": "RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX", + "long_name": "TODO", + "description": "The value assigned to VL when AVL < 2*VLMAX.", + "defined_by": { + "extensions": ["V"], + "params": [], + "raw": { + "extension": { + "name": "V" + } + }, + "summary": "ext:V" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["ceil(AVL/2)", "VLMAX", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "low", + "classification_reasoning": "No strong signals; defaulting to direct normative parameter", + "source_file": "spec/std/isa/param/RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX.yaml" + }, + { + "name": "SATP_MODE_BARE", + "long_name": "TODO", + "description": "Whether or not satp.MODE == Bare is supported.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "satp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of satp.MODE", + "source_file": "spec/std/isa/param/SATP_MODE_BARE.yaml" + }, + { + "name": "SCOUNTENABLE_EN", + "long_name": "TODO", + "description": "Indicates which counters can delegated via `scounteren`\n\nAn unimplemented counter cannot be specified, i.e., if\nHPM_COUNTER_EN[3] is false, it would be illegal to set\nSCOUNTENABLE_EN[3] to true.\n\nSCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.\nSCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented.", + "defined_by": { + "extensions": ["S", "Zicntr", "Zihpm"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "S" + }, + { + "anyOf": [ + { + "name": "Zicntr" + }, + { + "name": "Zihpm" + } + ] + } + ] + } + }, + "summary": "ext:S AND (ext:Zicntr OR ext:Zihpm)" + }, + "value_type": { + "type": "bitmask", + "details": { + "length": 32 + } + }, + "has_requirements": true, + "requirements_summary": "Counters 0-2 are defined by Zicntr\n\nCounters 3..31 are defined by Zihpm\n\nWhen mhpmcounter[i] does not exist, it cannot be enabled.\n", + "csr_references": [ + { + "csr": "scounteren", + "field": "CY", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "CY", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "TM", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "TM", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "IR", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "IR", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM3", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM3", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM4", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM4", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM5", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM5", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM6", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM6", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM7", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM7", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM8", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM8", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM9", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM9", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM10", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM10", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM11", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM11", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM12", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM12", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM13", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM13", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM14", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM14", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM15", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM15", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM16", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM16", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM17", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM17", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM18", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM18", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM19", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM19", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM20", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM20", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM21", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM21", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM22", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM22", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM23", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM23", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM24", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM24", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM25", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM25", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM26", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM26", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM27", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM27", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM28", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM28", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM29", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM29", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM30", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM30", + "idl_key": "reset_value()" + }, + { + "csr": "scounteren", + "field": "HPM31", + "idl_key": "type()" + }, + { + "csr": "scounteren", + "field": "HPM31", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of scounteren.CY", + "source_file": "spec/std/isa/param/SCOUNTENABLE_EN.yaml" + }, + { + "name": "SSTATEEN_JVT_TYPE", + "long_name": "TODO", + "description": "Behavior of the sstateen0.JVT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1", + "defined_by": { + "extensions": ["Ssstateen", "Zcmt"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "Zcmt" + }, + { + "name": "Ssstateen" + } + ] + } + }, + "summary": "ext:Zcmt AND ext:Ssstateen" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["rw", "read-only-0", "read-only-1"] + } + }, + "has_requirements": true, + "requirements_summary": "SSTATEEN cannot have more options that MSTATEEN\n\nSSTATEEN cannot have more options that HSTATEEN\n", + "csr_references": [], + "classification": "NORM_CSR_RW", + "classification_confidence": "low", + "classification_reasoning": "CSR field type control parameter for 'sstateen' (determines RO/RW behavior)", + "source_file": "spec/std/isa/param/SSTATEEN_JVT_TYPE.yaml" + }, + { + "name": "STVAL_WIDTH", + "long_name": "TODO", + "description": "The number of implemented bits in `stval`.\n\nMust be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `VA_SIZE`)", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "range", + "details": { + "minimum": null, + "maximum": 18446744073709551615 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Trap value reporting parameter", + "source_file": "spec/std/isa/param/STVAL_WIDTH.yaml" + }, + { + "name": "STVEC_MODE_DIRECT", + "long_name": "TODO", + "description": "Whether or not `stvec.MODE` supports Direct (0).", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "stvec must support at least one mode", + "csr_references": [ + { + "csr": "stvec", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of stvec.MODE", + "source_file": "spec/std/isa/param/STVEC_MODE_DIRECT.yaml" + }, + { + "name": "STVEC_MODE_VECTORED", + "long_name": "TODO", + "description": "Whether or not `stvec.MODE` supports Vectored (1).", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "stvec must support at least one mode", + "csr_references": [ + { + "csr": "stvec", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of stvec.MODE", + "source_file": "spec/std/isa/param/STVEC_MODE_VECTORED.yaml" + }, + { + "name": "SV32X4_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv32x4 translation mode is supported.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "SXLEN", + "condition": { + "includes": 32 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "SXLEN", + "includes": 32 + } + } + ] + }, + "summary": "ext:H AND param:SXLEN(includes=32)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, Sv32x4 must be supported", + "csr_references": [ + { + "csr": "hgatp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "type()" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of hgatp.MODE", + "source_file": "spec/std/isa/param/SV32X4_TRANSLATION.yaml" + }, + { + "name": "SV32_VSMODE_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv32 translation is supported in first-stage (VS-stage)\ntranslation.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "VSXLEN", + "condition": { + "includes": 32 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "VSXLEN", + "includes": 32 + } + } + ] + }, + "summary": "ext:H AND param:VSXLEN(includes=32)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, Sv32 must be supported", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Translation/mode parameter", + "source_file": "spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml" + }, + { + "name": "SV39X4_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv39x4 translation mode is supported.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "SXLEN", + "condition": { + "includes": 64 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "SXLEN", + "includes": 64 + } + } + ] + }, + "summary": "ext:H AND param:SXLEN(includes=64)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "Sv39x4 is only valid if S-mode can get into RV64 mode", + "csr_references": [ + { + "csr": "hgatp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "type()" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of hgatp.MODE", + "source_file": "spec/std/isa/param/SV39X4_TRANSLATION.yaml" + }, + { + "name": "SV39_VSMODE_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv39 translation is supported in first-stage (VS-stage)\ntranslation.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "VSXLEN", + "condition": { + "includes": 64 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "VSXLEN", + "includes": 64 + } + } + ] + }, + "summary": "ext:H AND param:VSXLEN(includes=64)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, SvQQX4 must be supported", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Translation/mode parameter", + "source_file": "spec/std/isa/param/SV39_VSMODE_TRANSLATION.yaml" + }, + { + "name": "SV48X4_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv48x4 translation mode is supported.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "SXLEN", + "condition": { + "includes": 64 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "SXLEN", + "includes": 64 + } + } + ] + }, + "summary": "ext:H AND param:SXLEN(includes=64)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, SvQQx4 must be supported", + "csr_references": [ + { + "csr": "hgatp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "type()" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of hgatp.MODE", + "source_file": "spec/std/isa/param/SV48X4_TRANSLATION.yaml" + }, + { + "name": "SV48_VSMODE_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv48 translation is supported in first-stage (VS-stage)\ntranslation.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "VSXLEN", + "condition": { + "includes": 64 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "VSXLEN", + "includes": 64 + } + } + ] + }, + "summary": "ext:H AND param:VSXLEN(includes=64)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, SvQQX4 must be supported", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Translation/mode parameter", + "source_file": "spec/std/isa/param/SV48_VSMODE_TRANSLATION.yaml" + }, + { + "name": "SV57X4_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv57x4 translation mode is supported.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "SXLEN", + "condition": { + "includes": 64 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "SXLEN", + "includes": 64 + } + } + ] + }, + "summary": "ext:H AND param:SXLEN(includes=64)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, SvQQx4 must be supported", + "csr_references": [ + { + "csr": "hgatp", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "type()" + }, + { + "csr": "hgatp", + "field": "PPN", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of hgatp.MODE", + "source_file": "spec/std/isa/param/SV57X4_TRANSLATION.yaml" + }, + { + "name": "SV57_VSMODE_TRANSLATION", + "long_name": "TODO", + "description": "Whether or not Sv57 translation is supported in first-stage (VS-stage)\ntranslation.", + "defined_by": { + "extensions": ["H"], + "params": [ + { + "name": "VSXLEN", + "condition": { + "includes": 64 + } + } + ], + "raw": { + "allOf": [ + { + "extension": { + "name": "H" + } + }, + { + "param": { + "name": "VSXLEN", + "includes": 64 + } + } + ] + }, + "summary": "ext:H AND param:VSXLEN(includes=64)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "at least one of Bare, SvQQX4 must be supported", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Translation/mode parameter", + "source_file": "spec/std/isa/param/SV57_VSMODE_TRANSLATION.yaml" + }, + { + "name": "SXLEN", + "long_name": "TODO", + "description": "Set of XLENs supported in S-mode. Can be one of:\n\n * 32: SXLEN is always 32\n * 64: SXLEN is always 64\n * [32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "set", + "details": { + "universe": [32, 64], + "min_items": 1, + "max_items": 2 + } + }, + "has_requirements": true, + "requirements_summary": "XLEN in S-mode can never be larger than XLEN in M-mode", + "csr_references": [ + { + "csr": "mstatus", + "field": "SXL", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "SXL", + "idl_key": "reset_value()" + }, + { + "csr": "hstatus", + "field": "VSXL", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'SXLEN'", + "source_file": "spec/std/isa/param/SXLEN.yaml" + }, + { + "name": "S_MODE_ENDIANNESS", + "long_name": "TODO", + "description": "Endianness of data in S-mode. Can be one of:\n\n * little: S-mode data is always little endian\n * big: S-mode data is always big endian\n * dynamic: S-mode data can be either little or big endian,\n depending on the CSR field `mstatus.SBE`", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["little", "big", "dynamic"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "SBE", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "SBE", + "idl_key": "reset_value()" + }, + { + "csr": "mstatush", + "field": "SBE", + "idl_key": "type()" + }, + { + "csr": "mstatush", + "field": "SBE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of mstatus.SBE", + "source_file": "spec/std/isa/param/S_MODE_ENDIANNESS.yaml" + }, + { + "name": "TIME_CSR_IMPLEMENTED", + "long_name": "TODO", + "description": "Whether or not a real hardware `time` CSR exists. Implementations can either provide a real\nCSR or emulate access at M-mode.\n\nPossible values:\n\ntrue::\n `time`/`timeh` exists, and accessing it will not cause an IllegalInstruction trap\n\nfalse::\n `time`/`timeh` does not exist.\n Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state,\n depending on TRAP_ON_UNIMPLEMENTED_CSR.\n Privileged software may emulate the `time` CSR, or may pass the exception to a lower level.", + "defined_by": { + "extensions": ["Zicntr"], + "params": [], + "raw": { + "extension": { + "name": "Zicntr" + } + }, + "summary": "ext:Zicntr" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "timeh", + "field": "(csr-level)", + "idl_key": "sw_read()" + }, + { + "csr": "time", + "field": "(csr-level)", + "idl_key": "sw_read()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Feature/CSR existence parameter ('IMPLEMENTED' suffix)", + "source_file": "spec/std/isa/param/TIME_CSR_IMPLEMENTED.yaml" + }, + { + "name": "TINST_VALUE_ON_BREAKPOINT", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_BREAKPOINT.yaml" + }, + { + "name": "TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Value to write into htval/mtval2 when there is a guest page fault on a final translation.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always pseudoinstruction\": Always write the pseudoinstruction", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "always pseudoinstruction"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Value to write into htval/mtval2 when there is a guest page fault on a final translation.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always pseudoinstruction\": Always write the pseudoinstruction\n * \"always transformed standard instruction\": Always write the transformation of the standard instruction encoding\n * \"custom\": A custom value, which will cause an UNPREDICTABLE event.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always pseudoinstruction", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT", + "long_name": "TODO", + "description": "Value to write into htval/mtval2 when there is a guest page fault on a final translation.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always pseudoinstruction\": Always write the pseudoinstruction\n * \"always transformed standard instruction\": Always write the transformation of the standard instruction encoding\n * \"custom\": A custom value, which will cause an UNPREDICTABLE event.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always pseudoinstruction", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED", + "long_name": "TODO", + "description": "Value written into htinst/mtinst when there is an instruction address misaligned exception.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED.yaml" + }, + { + "name": "TINST_VALUE_ON_LOAD_ACCESS_FAULT", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_LOAD_ACCESS_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml" + }, + { + "name": "TINST_VALUE_ON_LOAD_PAGE_FAULT", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_LOAD_PAGE_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_MCALL", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a MCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_MCALL.yaml" + }, + { + "name": "TINST_VALUE_ON_SCALL", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a SCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_SCALL.yaml" + }, + { + "name": "TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml" + }, + { + "name": "TINST_VALUE_ON_STORE_AMO_PAGE_FAULT", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": [ + "always zero", + "always transformed standard instruction", + "custom" + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_PAGE_FAULT.yaml" + }, + { + "name": "TINST_VALUE_ON_UCALL", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a UCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_UCALL.yaml" + }, + { + "name": "TINST_VALUE_ON_VIRTUAL_INSTRUCTION", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_VIRTUAL_INSTRUCTION.yaml" + }, + { + "name": "TINST_VALUE_ON_VSCALL", + "long_name": "TODO", + "description": "Value written into htinst/mtinst on a VSCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": ["always zero", "custom"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "htinst", + "field": "VALUE", + "idl_key": "type()" + }, + { + "csr": "mtinst", + "field": "VALUE", + "idl_key": "type()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of htinst.VALUE", + "source_file": "spec/std/isa/param/TINST_VALUE_ON_VSCALL.yaml" + }, + { + "name": "TRAP_ON_EBREAK", + "long_name": "Whether or not an EBREAK causes a synchronous exception.", + "description": "The spec states that implementations may handle EBREAKs transparently\nwithout raising a trap, in which case the EEI must provide a builtin.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_EBREAK.yaml" + }, + { + "name": "TRAP_ON_ECALL_FROM_M", + "long_name": "Whether or not an ECALL-from-M-mode causes a synchronous exception.", + "description": "The spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml" + }, + { + "name": "TRAP_ON_ECALL_FROM_S", + "long_name": "TODO", + "description": "Whether or not an ECALL-from-S-mode causes a synchronous exception.\n\nThe spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin.", + "defined_by": { + "extensions": ["S"], + "params": [], + "raw": { + "extension": { + "name": "S" + } + }, + "summary": "ext:S" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml" + }, + { + "name": "TRAP_ON_ECALL_FROM_U", + "long_name": "TODO", + "description": "Whether or not an ECALL-from-U-mode causes a synchronous exception.\n\nThe spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin.", + "defined_by": { + "extensions": ["U"], + "params": [], + "raw": { + "extension": { + "name": "U" + } + }, + "summary": "ext:U" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml" + }, + { + "name": "TRAP_ON_ECALL_FROM_VS", + "long_name": "TODO", + "description": "Whether or not an ECALL-from-VS-mode causes a synchronous exception.\n\nThe spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml" + }, + { + "name": "TRAP_ON_ILLEGAL_WLRL", + "long_name": "Whether or not writing an illegal value to a WLRL CSR field causes a trap.", + "description": "Options:\n\n * true: Writing an illegal value to a WLRL CSR field will cause an IllegalInstruction exception.\n * false: Writing an illegal value to a WLRL CSR field causes unpredictable behavior.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_ILLEGAL_WLRL.yaml" + }, + { + "name": "TRAP_ON_RESERVED_INSTRUCTION", + "long_name": "Whether or not fetching an unimplemented standard instruction and/or an undefined standard\ninstruction from the standard/reserved opcode space causes a trap", + "description": "Options:\n\n * true: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcode space will cause an IllegalInstruction exception.\n * false: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcose space causes unpredictable behavior.\n\nTRAP_ON_RESERVED_INSTRUCTION may be false while TRAP_ON_UNIMPLEMENTED_INSTRUCTION is true\nwhen a custom instruction is implemented in the standard/reserved opcode space.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_RESERVED_INSTRUCTION.yaml" + }, + { + "name": "TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY", + "long_name": "TODO", + "description": "For implementations that make `satp`.MODE read-only zero\n(always Bare, _i.e._, no virtual translation is implemented),\nattempts to execute an SFENCE.VMA instruction might raise an\nillegal-instruction exception.\n\nTRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY indicates whether\nor not that exception occurs.\n\nTRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when\nsome virtual translation mode is supported.", + "defined_by": { + "extensions": ["S", "Sv32", "Sv39", "Sv48", "Sv57"], + "params": [], + "raw": { + "extension": { + "allOf": [ + { + "name": "S" + }, + { + "noneOf": [ + { + "name": "Sv32" + }, + { + "name": "Sv39" + }, + { + "name": "Sv48" + }, + { + "name": "Sv57" + } + ] + } + ] + } + }, + "summary": "ext:S AND NONE(ext:Sv32, ext:Sv39, ext:Sv48, ext:Sv57)" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml" + }, + { + "name": "TRAP_ON_UNIMPLEMENTED_CSR", + "long_name": "Whether or not fetching an unimplemented instruction causes a trap", + "description": "Options:\n\n * true: Accessing an unimplemented CSR (via a `Zicsr` instruction) will cause an IllegalInstruction exception.\n * false: Accessing an unimplemented CSR (via a `Zicsr` instruction) will cause unpredictable behavior.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_UNIMPLEMENTED_CSR.yaml" + }, + { + "name": "TRAP_ON_UNIMPLEMENTED_INSTRUCTION", + "long_name": "Whether or not fetching an unimplemented instruction causes a trap", + "description": "Options:\n\n * true: Fetching an unimplemented instruction will cause an IllegalInstruction exception.\n * false: Fetching an unimplemented instruction causes unpredictable behavior.\n\nAn unimplemented instruction is any instruction encoding that is not defined by the implementation.\nCustom instructions are considered implemented.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Trap/report behavior parameter (matches ^TRAP_ON_)", + "source_file": "spec/std/isa/param/TRAP_ON_UNIMPLEMENTED_INSTRUCTION.yaml" + }, + { + "name": "UXLEN", + "long_name": "TODO", + "description": "Set of XLENs supported in U-mode. When both 32 and 64 are supported, SXLEN can be changed,\nvia mstatus.UXL, between 32 and 64.", + "defined_by": { + "extensions": ["U"], + "params": [], + "raw": { + "extension": { + "name": "U" + } + }, + "summary": "ext:U" + }, + "value_type": { + "type": "set", + "details": { + "universe": [32, 64], + "min_items": 1, + "max_items": 2 + } + }, + "has_requirements": true, + "requirements_summary": "# XLEN in U-mode can never be larger than XLEN in M-mode\nMXLEN == 32 -> !$array_includes?(UXLEN, 64);\n\n# If S-mode supports RV32, then U mode must also support it.\n$array_includes?(SXLEN, 32) -> $arra", + "csr_references": [ + { + "csr": "mstatus", + "field": "UXL", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "UXL", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'UXLEN'", + "source_file": "spec/std/isa/param/UXLEN.yaml" + }, + { + "name": "U_MODE_ENDIANNESS", + "long_name": "TODO", + "description": "Endianness of data in U-mode. Can be one of:\n\n * little: U-mode data is always little endian\n * big: U-mode data is always big endian\n * dynamic: U-mode data can be either little or big endian,\n depending on the CSR field `mstatus.UBE`", + "defined_by": { + "extensions": ["U"], + "params": [], + "raw": { + "extension": { + "name": "U" + } + }, + "summary": "ext:U" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["little", "big", "dynamic"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mstatus", + "field": "UBE", + "idl_key": "type()" + }, + { + "csr": "mstatus", + "field": "UBE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of mstatus.UBE", + "source_file": "spec/std/isa/param/U_MODE_ENDIANNESS.yaml" + }, + { + "name": "VENDOR_ID_BANK", + "long_name": "JEDEC Vendor ID bank, for `mvendorid`.", + "description": "Encodes the number of one-byte continuation codes in the Bank field of `mvendorid`.\n\niN JEDEC’s parlance, the bank number is one greater than the number of continuation codes; hence, the mvendorid Bank field encodes a value that is one less than the JEDEC bank number.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 33554431 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mvendorid", + "field": "Bank", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'VENDOR_ID_BANK'", + "source_file": "spec/std/isa/param/VENDOR_ID_BANK.yaml" + }, + { + "name": "VENDOR_ID_OFFSET", + "long_name": "JEDEC Vendor ID offset, for `mvendorid`.", + "description": "Encodes the final byte of a JEDEC manufactor ID, discarding the parity bit.", + "defined_by": { + "extensions": ["Sm"], + "params": [], + "raw": { + "extension": { + "name": "Sm" + } + }, + "summary": "ext:Sm" + }, + "value_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 127 + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "mvendorid", + "field": "Offset", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'VENDOR_ID_OFFSET'", + "source_file": "spec/std/isa/param/VENDOR_ID_OFFSET.yaml" + }, + { + "name": "VLEN", + "long_name": "TODO", + "description": "The number of bits in a single vector register.", + "defined_by": { + "extensions": ["V"], + "params": [], + "raw": { + "extension": { + "name": "V" + } + }, + "summary": "ext:V" + }, + "value_type": { + "type": "value", + "details": { + "base": "integer" + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "vlenb", + "field": "VALUE", + "idl_key": "reset_value()" + }, + { + "csr": "vstart", + "field": "VALUE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'VLEN'", + "source_file": "spec/std/isa/param/VLEN.yaml" + }, + { + "name": "VMID_WIDTH", + "long_name": "TODO", + "description": "Number of bits supported in `hgatp.VMID` (i.e., the supported width of a virtual machine ID).", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "conditional", + "details": { + "branches": [ + { + "condition": "MXLEN == 32", + "inner_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 7 + } + } + }, + { + "condition": "MXLEN == 64", + "inner_type": { + "type": "range", + "details": { + "minimum": 0, + "maximum": 14 + } + } + } + ] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "hgatp", + "field": "VMID", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hgatp", + "field": "VMID", + "idl_key": "type()" + }, + { + "csr": "hgatp", + "field": "VMID", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'VMID_WIDTH'", + "source_file": "spec/std/isa/param/VMID_WIDTH.yaml" + }, + { + "name": "VSSTAGE_MODE_BARE", + "long_name": "TODO", + "description": "Whether or not writing mode=Bare is supported in the `vsatp` register.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "# if guest is 32 bit, then one of Bare or SV32_VSMODE_TRANSLATION must be supported\n$array_includes?(VSXLEN, 32) && !SV32_VSMODE_TRANSLATION\n -> VSSTAGE_MODE_BARE;\n\n# if guest is 64 bit, then one of ", + "csr_references": [], + "classification": "NORM_DIRECT", + "classification_confidence": "medium", + "classification_reasoning": "Translation/mode parameter", + "source_file": "spec/std/isa/param/VSSTAGE_MODE_BARE.yaml" + }, + { + "name": "VSTVEC_MODE_DIRECT", + "long_name": "TODO", + "description": "Whether or not `vstvec.MODE` supports Direct (0).", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "At least one vstvec mode must be supported", + "csr_references": [ + { + "csr": "vstvec", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of vstvec.MODE", + "source_file": "spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml" + }, + { + "name": "VSTVEC_MODE_VECTORED", + "long_name": "TODO", + "description": "Whether or not `stvec.MODE` supports Vectored (1).", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "binary", + "details": { + "choices": [true, false] + } + }, + "has_requirements": true, + "requirements_summary": "At least one vstvec mode must be supported", + "csr_references": [ + { + "csr": "vstvec", + "field": "MODE", + "idl_key": "sw_write(csr_value)" + } + ], + "classification": "NORM_CSR_WARL", + "classification_confidence": "high", + "classification_reasoning": "Referenced in sw_write() of vstvec.MODE", + "source_file": "spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml" + }, + { + "name": "VSXLEN", + "long_name": "TODO", + "description": "Set of XLENs supported in VS-mode. Can be one of:\n\n * [32]: VSXLEN is always 32\n * [64]: VSXLEN is always 64\n * [32, 64]: VSXLEN can be changed (via `hstatus.VSXL`) between 32 and 64", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "set", + "details": { + "universe": [32, 64], + "min_items": 1, + "max_items": 2 + } + }, + "has_requirements": true, + "requirements_summary": "XLEN in VS-mode can never be larger than XLEN in S-mode\n(and, transitively, cannot be larger than XLEN in M-mode).\n", + "csr_references": [ + { + "csr": "hstatus", + "field": "VSXL", + "idl_key": "sw_write(csr_value)" + }, + { + "csr": "hstatus", + "field": "VSXL", + "idl_key": "type()" + }, + { + "csr": "hstatus", + "field": "VSXL", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'VSXLEN'", + "source_file": "spec/std/isa/param/VSXLEN.yaml" + }, + { + "name": "VS_MODE_ENDIANNESS", + "long_name": "TODO", + "description": "Endianness of data in VS-mode. Can be one of:\n\n * little: VS-mode data is always little endian\n * big: VS-mode data is always big endian\n * dynamic: VS-mode data can be either little or big endian,\n depending on the CSR field `hstatus.VSBE`", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["little", "big", "dynamic"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "hstatus", + "field": "VSBE", + "idl_key": "type()" + }, + { + "csr": "hstatus", + "field": "VSBE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of hstatus.VSBE", + "source_file": "spec/std/isa/param/VS_MODE_ENDIANNESS.yaml" + }, + { + "name": "VUXLEN", + "long_name": "TODO", + "description": "Set of XLENs supported in VU-mode. When both 32 and 64 are supported, VUXLEN can be changed\nvia `vsstatus.UXL`.", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "set", + "details": { + "universe": [32, 64], + "min_items": 1, + "max_items": 2 + } + }, + "has_requirements": true, + "requirements_summary": "XLEN in VU-mode can never be larger than XLEN in VS-mode\n(and, transitively, cannot be larger than XLEN in S-mode or M-mode).\n", + "csr_references": [ + { + "csr": "vsstatus", + "field": "UXL", + "idl_key": "type()" + }, + { + "csr": "vsstatus", + "field": "UXL", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_DIRECT", + "classification_confidence": "high", + "classification_reasoning": "Well-known architectural parameter 'VUXLEN'", + "source_file": "spec/std/isa/param/VUXLEN.yaml" + }, + { + "name": "VU_MODE_ENDIANNESS", + "long_name": "TODO", + "description": "Endianness of data in VU-mode. Can be one of:\n\n * little: VU-mode data is always little endian\n * big: VU-mode data is always big endian\n * dynamic: VU-mode data can be either little or big endian,\n depending on the CSR field `vsstatus.UBE`", + "defined_by": { + "extensions": ["H"], + "params": [], + "raw": { + "extension": { + "name": "H" + } + }, + "summary": "ext:H" + }, + "value_type": { + "type": "enum", + "details": { + "values": ["little", "big", "dynamic"] + } + }, + "has_requirements": false, + "requirements_summary": null, + "csr_references": [ + { + "csr": "vsstatus", + "field": "UBE", + "idl_key": "type()" + }, + { + "csr": "vsstatus", + "field": "UBE", + "idl_key": "reset_value()" + } + ], + "classification": "NORM_CSR_RW", + "classification_confidence": "high", + "classification_reasoning": "Controls type (RO/RW) of vsstatus.UBE", + "source_file": "spec/std/isa/param/VU_MODE_ENDIANNESS.yaml" + } + ] +} diff --git a/param_extraction/data/parameters_catalog.csv b/param_extraction/data/parameters_catalog.csv new file mode 100644 index 0000000000..046ecaba0c --- /dev/null +++ b/param_extraction/data/parameters_catalog.csv @@ -0,0 +1,723 @@ +parameter_name,long_name,classification,classification_confidence,classification_reasoning,value_type,value_details,defined_by_extensions,defined_by_summary,has_requirements,num_csr_references,csr_names,spec_file,spec_line,spec_score,spec_is_normative,spec_in_note,spec_text,description +ARCH_ID_VALUE,Vendor-specific architecture ID in `marchid`,NORM_DIRECT,high,Well-known architectural parameter 'ARCH_ID_VALUE',conditional,2 conditional branches,Sm,ext:Sm AND param:MARCHID_IMPLEMENTED(equal=True),False,1,marchid,machine.adoc,297,8,False,False,==== Machine Architecture ID (`marchid`) Register,"The value of `marchid` +The combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is implemented." +ASID_WIDTH,TODO,NORM_DIRECT,high,Well-known architectural parameter 'ASID_WIDTH',conditional,2 conditional branches,S,ext:S,False,0,,supervisor.adoc,1373,5,True,False,"[#norm:sfence-vma-asid_effect]#Likewise, changes to `satp`.ASID take effect immediately.#","Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32" +CACHE_BLOCK_SIZE,TODO,NORM_DIRECT,high,Well-known architectural parameter 'CACHE_BLOCK_SIZE',range,[1..18446744073709551615],"Zicbom, Zicbop, Zicboz",(ext:Zicbom OR ext:Zicbop OR ext:Zicboz),False,0,,cmo.adoc,973,5,True,False,[#norm:cbo-zero_unaligned]#It is not required that _rs1_ is aligned to the size of a cache block.# On,"The observable size of a cache block, in bytes" +CONFIG_PTR_ADDRESS,Physical address in `mconfigptr`,NORM_DIRECT,high,Well-known architectural parameter 'CONFIG_PTR_ADDRESS',conditional,2 conditional branches,Sm,ext:Sm(>= 1.12.0),True,1,mconfigptr,machine.adoc,2136,6,False,False,==== Machine Configuration Pointer (`mconfigptr`) Register,The value returned from `mconfigptr` +COUNTINHIBIT_EN,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of mcountinhibit.CY,bitmask,32-bit mask,Sm,ext:Sm,False,62,mcountinhibit,machine.adoc,1669,13,True,False,[#norm:mcountinhibit_sz_warl_op1]#The counter-inhibit register `mcountinhibit` is a 32-bit,"Indicates which hardware performance monitor counters can be disabled from `mcountinhibit`. + +An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, +it would be illegal to set COUNTINHIBIT_EN[3] to true. + +COUNTINHIBIT_EN[1] can never be true, since it corresponds to `mcoun" +DBG_HCONTEXT_WIDTH,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of hcontext.HCONTEXT,range,[0..14],Sdtrig,ext:Sdtrig,False,2,"hcontext, mcontext",smstateen.adoc,287,8,False,False,`hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in,Specifies the size of HCONTEXT +DBG_SCONTEXT_WIDTH,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of scontext.DATA,range,[0..32],Sdtrig,ext:Sdtrig,False,1,scontext,hypervisor.adoc,146,6,False,False,"Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`,",Specifies the size of SCONTEXT +DCSR_MPRVEN_TYPE,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of dcsr.MPRVEN,enum,"values: ['read-only-0', 'read-only-1', 'rw']",Sdtrig,ext:Sdtrig,False,2,dcsr,priv-cfi.adoc,87,4,False,False,"transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#","Implementation of dcsr.MPRVEN is optional. +It may be tied to either 0 or 1. + +Behavior of the dcsr.MPRVEN bit: + * 'read-only-0': tied to 0 + * 'read-only-1': tied to 1 + * 'rw': read-write" +DCSR_STEPIE_TYPE,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of dcsr.STEPIE,enum,"values: ['read-only-0', 'read-only-1', 'rw']",Sdtrig,ext:Sdtrig,False,2,dcsr,priv-cfi.adoc,87,4,False,False,"transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#","Implementation of dcsr.STEPIE is optional. +It may be tied to either 0 or 1. + +Behavior of the dcsr.STEPIE bit: + * 'read-only-0': tied to 0 + * 'read-only-1': tied to 1 + * 'rw': read-write" +DCSR_STOPCOUNT_TYPE,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of dcsr.STOPCOUNT,enum,"values: ['read-only-0', 'read-only-1', 'rw']",Sdtrig,ext:Sdtrig,False,2,dcsr,priv-cfi.adoc,87,4,False,False,"transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#","Implementation of dcsr.STOPCOUNT is optional. +It may be tied to either 0 or 1. + +Behavior of the dcsr.STOPCOUNT bit: + * 'read-only-0': tied to 0 + * 'read-only-1': tied to 1 + * 'rw': read-write" +DCSR_STOPTIME_TYPE,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of dcsr.STOPTIME,enum,"values: ['read-only-0', 'read-only-1', 'rw']",Sdtrig,ext:Sdtrig,False,2,dcsr,priv-cfi.adoc,87,4,False,False,"transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#","Implementation of dcsr.STOPTIME is optional. +It may be tied to either 0 or 1. + +Behavior of the dcsr.STOPTIME bit: + * 'read-only-0': tied to 0 + * 'read-only-1': tied to 1 + * 'rw': read-write" +ELEN,TODO,NORM_DIRECT,high,Well-known architectural parameter 'ELEN',value,{'base': 'integer'},V,ext:V,False,0,,v-st-ext.adoc,24,9,True,False,". [#norm:vlen_param]#The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.#",The maximum size in bits of a vector element that any operation can produce or consume. +FOLLOW_VTYPE_RESET_RECOMMENDATION,TODO,NORM_DIRECT,medium,Implementation behavioral choice parameter,binary,"choices: [True, False]",V,ext:V,False,6,"vl, vtype",v-st-ext.adoc,169,14,True,False,"NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits f","It is recommended that at reset, vtype.vill is set, the remaining bits in vtype are zero, and vl is set to zero. +If this parameter is set to true, this recommendation is followed. If it is false, at reset the respective fields +will be UNDEFINED_LEGAL." +FORCE_UPGRADE_CBO_INVAL_TO_FLUSH,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of menvcfg.CBIE,binary,"choices: [True, False]",Zicbom,ext:Zicbom,False,1,menvcfg,supervisor.adoc,913,20,False,False,"implemented, `CBIE` is read-only zero. Execution of `CBO.INVAL` in U-mode is","When true, an implementation prohibits setting `menvcfg.CBIE` == `11` such that all `cbo.inval` +instructions either trap (when `menvcfg.CBIE` == '00') or flush (when `menvcfg.CBIE` == '01'). + +When false, an implementation allows a true INVAL operation for `cbo.inval`, and thus supports +the setting `" +GSTAGE_MODE_BARE,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of hgatp.MODE,binary,"choices: [True, False]",H,ext:H,True,1,hgatp,hypervisor.adoc,1075,11,False,False,"is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,",Whether or not writing mode=Bare is supported in the `hgatp` register. +HCONTEXT_AVAILABLE,TODO,NORM_DIRECT,high,Feature/CSR existence parameter ('AVAILABLE' suffix),binary,"choices: [True, False]",Sdtrig,ext:Sdtrig,True,2,hcontext,smstateen.adoc,287,8,False,False,`hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in,Specifies if HCONTEXT is available +HCOUNTENABLE_EN,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of hcounteren.CY,bitmask,32-bit mask,H,ext:H,False,64,hcounteren,hypervisor.adoc,857,12,False,False,"When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is","Indicates which counters can delegated via `hcounteren` + +An unimplemented counter cannot be specified, i.e., if +HPM_COUNTER_EN[3] is false, it would be illegal to set +HCOUNTENABLE_EN[3] to true. + +HCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented. +HCOUNTENABLE_EN[3:31] must all be" +HPM_COUNTER_EN,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of scountovf.OF3,bitmask,32-bit mask,Smhpm,ext:Smhpm,False,1044,"mhpmcounter10, mhpmcounter10h, mhpmcounter11, mhpmcounter11h, mhpmcounter12, mhpmcounter12h, mhpmcounter13, mhpmcounter13h, mhpmcounter14, mhpmcounter14h, mhpmcounter15, mhpmcounter15h, mhpmcounter16, mhpmcounter16h, mhpmcounter17, mhpmcounter17h, mhpmcounter18, mhpmcounter18h, mhpmcounter19, mhpmcounter19h, mhpmcounter20, mhpmcounter20h, mhpmcounter21, mhpmcounter21h, mhpmcounter22, mhpmcounter22h, mhpmcounter23, mhpmcounter23h, mhpmcounter24, mhpmcounter24h, mhpmcounter25, mhpmcounter25h, mhpmcounter26, mhpmcounter26h, mhpmcounter27, mhpmcounter27h, mhpmcounter28, mhpmcounter28h, mhpmcounter29, mhpmcounter29h, mhpmcounter3, mhpmcounter30, mhpmcounter30h, mhpmcounter31, mhpmcounter31h, mhpmcounter3h, mhpmcounter4, mhpmcounter4h, mhpmcounter5, mhpmcounter5h, mhpmcounter6, mhpmcounter6h, mhpmcounter7, mhpmcounter7h, mhpmcounter8, mhpmcounter8h, mhpmcounter9, mhpmcounter9h, mhpmevent10, mhpmevent10h, mhpmevent11, mhpmevent11h, mhpmevent12, mhpmevent12h, mhpmevent13, mhpmevent13h, mhpmevent14, mhpmevent14h, mhpmevent15, mhpmevent15h, mhpmevent16, mhpmevent16h, mhpmevent17, mhpmevent17h, mhpmevent18, mhpmevent18h, mhpmevent19, mhpmevent19h, mhpmevent20, mhpmevent20h, mhpmevent21, mhpmevent21h, mhpmevent22, mhpmevent22h, mhpmevent23, mhpmevent23h, mhpmevent24, mhpmevent24h, mhpmevent25, mhpmevent25h, mhpmevent26, mhpmevent26h, mhpmevent27, mhpmevent27h, mhpmevent28, mhpmevent28h, mhpmevent29, mhpmevent29h, mhpmevent3, mhpmevent30, mhpmevent30h, mhpmevent31, mhpmevent31h, mhpmevent3h, mhpmevent4, mhpmevent4h, mhpmevent5, mhpmevent5h, mhpmevent6, mhpmevent6h, mhpmevent7, mhpmevent7h, mhpmevent8, mhpmevent8h, mhpmevent9, mhpmevent9h, scountovf",machine.adoc,1615,8,True,False,"[#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is","List of HPM counters that are enabled. +There is one entry for each hpmcounter. + +The first three entries *must* be false (as they correspond to CY, IR, TM in, _e.g._ `mhmpcountinhibit`) +Index 3 in HPM_COUNTER_EN corresponds to hpmcounter3. +Index 31 in HPM_COUNTER_EN corresponds to hpmcounter31." +HPM_EVENTS,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of mhpmevent14.EVENT,set,set of integer,Smhpm,ext:Smhpm,False,29,"mhpmevent10, mhpmevent11, mhpmevent12, mhpmevent13, mhpmevent14, mhpmevent15, mhpmevent16, mhpmevent17, mhpmevent18, mhpmevent19, mhpmevent20, mhpmevent21, mhpmevent22, mhpmevent23, mhpmevent24, mhpmevent25, mhpmevent26, mhpmevent27, mhpmevent28, mhpmevent29, mhpmevent3, mhpmevent30, mhpmevent31, mhpmevent4, mhpmevent5, mhpmevent6, mhpmevent7, mhpmevent8, mhpmevent9",machine.adoc,1581,8,False,False,"`mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which",List of defined event numbers that can be written into hpmeventN +HSTATEEN_AIA_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'hstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","H, Ssaia, Ssstateen",ext:Ssaia AND ext:H AND ext:Ssstateen,True,0,,,,0,,,,"Behavior of the hstateen0.AIA bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +HSTATEEN_CONTEXT_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'hstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","H, Sdtrig, Ssstateen",ext:Sdtrig AND ext:H AND ext:Ssstateen,True,0,,smctr.adoc,652,5,True,False,"[#norm:ccounter_reset]#The CtrCycleCounter is reset on writes to `__x__ctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.#","Behavior of the hstateen0.CONTEXT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +HSTATEEN_CSRIND_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'hstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","H, Sscsrind, Ssstateen",ext:Sscsrind AND ext:H AND ext:Ssstateen,True,0,,smstateen.adoc,191,3,False,False,"{bits: 1, name: 'CSRIND'},","Behavior of the hstateen0.CSRIND bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +HSTATEEN_ENVCFG_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'hstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","H, Ssstateen",ext:H(~> 1.0) AND ext:Ssstateen(~> 1.0),True,0,,priv-cfi.adoc,134,3,False,False,*__x__*`envcfg.SSE` fields. The conditions are specified as follows:,"Behavior of the hstateen0.ENVCFG bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +HSTATEEN_IMSIC_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'hstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","H, Ssaia, Ssstateen",ext:Ssaia AND ext:H AND ext:Ssstateen,True,0,,smstateen.adoc,189,3,False,False,"{bits: 1, name: 'IMSIC'},","Behavior of the hstateen0.IMSIC bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +HSTATEEN_JVT_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'hstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","H, Ssstateen, Zcmt",ext:Zcmt AND ext:H AND ext:Ssstateen,True,0,,zc.adoc,2341,4,True,False,"[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#","Behavior of the hstateen0.JVT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +HW_MSTATUS_FS_DIRTY_UPDATE,TODO,SW_RULE,medium,Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing,enum,"values: ['never', 'precise', 'imprecise']",F,ext:F,False,1,mstatus,v-st-ext.adoc,3313,26,True,False,[#norm:mstatus-FS_off_V_fp_ill]#If the floating-point unit status field `mstatus.FS` is `Off` then any,"Indicates whether or not hardware will write to `mstatus.FS` + +Values are: +[separator=""!""] +!=== +h! never ! Hardware never writes `mstatus.FS` +h! precise ! Hardware writes `mstatus.FS` to the Dirty (3) state precisely when F registers are modified +h! imprecise ! Hardware writes `mstatus.FS` imprecis" +HW_MSTATUS_VS_DIRTY_UPDATE,TODO,SW_RULE,medium,Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing,enum,"values: ['never', 'precise', 'imprecise']",V,ext:V,False,1,mstatus,v-st-ext.adoc,107,27,False,False,"If `mstatus.VS` is Dirty, `mstatus.SD` is 1;","Indicates whether or not hardware will write to `mstatus.VS` + +Values are: +[separator=""!""] +!=== +h! never ! Hardware never writes `mstatus.VS` +h! precise ! Hardware writes `mstatus.VS` to the Dirty (3) state precisely when V registers are modified +h! imprecise ! Hardware writes `mstatus.VS` imprecis" +IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of vsatp.MODE,binary,"choices: [True, False]",H,ext:H,False,3,vsatp,hypervisor.adoc,1416,9,False,False,"ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in","Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are +ignored (as they are with satp), or if they are treated as WARL, leading to undpredictable +behavior." +IMP_ID_VALUE,Vendor-specific implementation ID in `mimpid`,NORM_DIRECT,high,Well-known architectural parameter 'IMP_ID_VALUE',conditional,2 conditional branches,Sm,ext:Sm AND param:MIMPID_IMPLEMENTED(equal=True),False,1,mimpid,machine.adoc,335,5,False,False,==== Machine Implementation ID (`mimpid`) Register,A unique encoding of the version of the processor implementation. +JVT_BASE_MASK,Mask representing the implemented bits of jvt.BASE,NORM_CSR_WARL,high,Referenced in sw_write() of jvt.BASE,range,[64..576460752303423487],Zcmt,ext:Zcmt AND param:JVT_BASE_TYPE(equal=mask),True,1,jvt,c-st-ext.adoc,466,8,True,False,"instructions. [#norm:Zca_offsets_mul2]#As with base RVI instructions, the offsets of all RVC","Mask representing the implemented bits of jvt.BASE. +Includes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0." +JVT_BASE_TYPE,Type of the jvt.BASE CSR field,NORM_CSR_WARL,high,Referenced in sw_write() of jvt.BASE,binary,"choices: ['mask', 'custom']",Zcmt,ext:Zcmt,False,1,jvt,c-st-ext.adoc,466,10,True,False,"instructions. [#norm:Zca_offsets_mul2]#As with base RVI instructions, the offsets of all RVC","Type of the jvt.BASE CSR field. One of: + +* mask: jvt.BASE contains one or more implemented bits, which are indicated by JVT_BASE_MASK. +* custom: Custom behavior. Will cause hart to enter 'unpredictable' state on a write to jvt.BASE." +JVT_READ_ONLY,Whether or not the JVT CSR is read-only,NORM_CSR_WARL,high,Referenced in sw_write() of jvt.MODE,binary,"choices: [True, False]",Zcmt,ext:Zcmt,False,3,jvt,zc.adoc,2341,6,True,False,"[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#","If Zcmt is implemented, JVT is implemented, but can contain a read-only value" +LRSC_FAIL_ON_NON_EXACT_LRSC,TODO,NORM_DIRECT,medium,Load-reserved/store-conditional behavior parameter,binary,"choices: [True, False]",Zalrsc,ext:Zalrsc,False,0,,a-st-ext.adoc,169,3,False,False,The SC must fail if the address is not within the reservation set of the,"Whether or not a Store Conditional fails if its physical address and size do not +exactly match the physical address and size of the last Load Reserved in program order +(independent of whether or not the SC is in the current reservation set)" +LRSC_FAIL_ON_VA_SYNONYM,TODO,NORM_DIRECT,medium,Load-reserved/store-conditional behavior parameter,binary,"choices: [True, False]",Zalrsc,ext:Zalrsc,False,0,,a-st-ext.adoc,76,7,False,False,SC.W instruction invalidates any reservation held by this hart. LR.D and,"Whether or not an `sc.l`/`sc.d` will fail if its VA does not match the VA of the prior +`lr.l`/`lr.d`, even if the physical address of the SC and LR are the same" +LRSC_MISALIGNED_BEHAVIOR,TODO,NORM_DIRECT,medium,Load-reserved/store-conditional behavior parameter,enum,"values: ['always raise misaligned exception', 'always raise access fault', 'custom']",Zalrsc,ext:Zalrsc,False,0,,a-st-ext.adoc,59,12,False,False,are performed with the load-reserved (LR) and store-conditional (SC),"What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false. + + * 'always raise misaligned exception': self-explainitory + * 'always raise access fault': self-explainitory + * 'custom': Custom behavior; misaligned LR/SC may sometimes raise a misaligned exception and sometimes raise a " +LRSC_RESERVATION_STRATEGY,TODO,NORM_DIRECT,medium,Load-reserved/store-conditional behavior parameter,enum,"values: ['reserve naturally-aligned 64-byte region', 'reserve naturally-aligned 128-byte region', 'reserve exactly enough to cover the access', 'custom']",Zalrsc,ext:Zalrsc,False,0,,a-st-ext.adoc,76,19,False,False,SC.W instruction invalidates any reservation held by this hart. LR.D and,"Strategy used to handle reservation sets. + + * ""reserve naturally-aligned 64-byte region"": Always reserve the 64-byte block containing the LR/SC address + * ""reserve naturally-aligned 128-byte region"": Always reserve the 128-byte block containing the LR/SC address + * ""reserve exactly enough to cove" +MARCHID_IMPLEMENTED,Whether or not the `marchid` CSR is implemented.,NORM_DIRECT,high,Feature/CSR existence parameter ('IMPLEMENTED' suffix),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,303,10,False,False,The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.,"* false: `marchid` is not implemented, and must be read-only-0 +* true: `marchid` is implemented, and the value is determined by `ARCH_ID_VALUE`" +MCID_WIDTH,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of srmcfg.MCID,range,[1..12],Ssqosid,ext:Ssqosid,False,1,srmcfg,supervisor.adoc,2586,8,False,False,The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege,"Number of bits used for the Monitoring Counter ID field (MCID). +Default is 12." +MCONTEXT_AVAILABLE,TODO,NORM_DIRECT,high,Feature/CSR existence parameter ('AVAILABLE' suffix),binary,"choices: [True, False]",Sdtrig,ext:Sdtrig,False,2,mcontext,priv-csrs.adoc,1019,6,False,False,`mcontext`,Specifies if MCONTEXT is available +MCOUNTENABLE_EN,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of mcounteren.CY,bitmask,32-bit mask,U,ext:U,True,62,mcounteren,machine.adoc,1656,13,True,False,"[#norm:mcounteren_flds_mandatory_warl]#In harts with U-mode, the `mcounteren` must be","Indicates which counters can be delegated via `mcounteren`. + +An unimplemented counter cannot be specified, i.e., if +HPM_COUNTER_EN[3] is false, it would be illegal to set +MCOUNTENABLE_EN[3] to true. + +MCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented. +MCOUNTENABLE_EN[3:31] must al" +MIMPID_IMPLEMENTED,Whether or not the `mimpid` CSR is implemented.,NORM_DIRECT,high,Feature/CSR existence parameter ('IMPLEMENTED' suffix),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,337,9,True,False,[#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the,"* false: `mimpid` is not implemented, and must be read-only-0 +* true: `mimpid` is implemented, and the value is determined by `IMP_ID_VALUE`" +MISALIGNED_AMO,TODO,NORM_DIRECT,medium,Misaligned access behavior parameter,binary,"choices: [True, False]",Zaamo,ext:Zaamo,False,0,,machine.adoc,1976,5,True,False,[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or,whether or not the implementation supports misaligned atomics in main memory +MISALIGNED_LDST,Support for misaligned loads and stores to main memory.,NORM_DIRECT,medium,Misaligned access behavior parameter,binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,1976,5,True,False,[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or,"Does the implementation perform non-atomic misaligned loads and stores to main memory +(does *not* affect misaligned support to device memory)? +If not, the implementation always throws a misaligned exception." +MISALIGNED_LDST_EXCEPTION_PRIORITY,"The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault +or access-fault exceptions.",NORM_DIRECT,medium,Misaligned access behavior parameter,binary,"choices: ['low', 'high']",Sm,ext:Sm,True,0,,rv32.adoc,139,6,True,False,[#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch,"The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault +or access-fault exceptions. + +May be one of: + +[separator=""!""] +!=== +! low ! Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions. +! high ! Misaligned " +MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE,"The maximum granule size, in bytes, that the hart can atomically perform a +misaligned load/store/AMO without raising a Misaligned exception",NORM_DIRECT,medium,Misaligned access behavior parameter,enum,13 values,Sm,ext:Sm AND param:MISALIGNED_LDST(equal=True),True,0,,a-st-ext.adoc,385,7,False,False,"The misaligned atomicity granule PMA, defined in Volume II of this manual,","When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart +cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can +atomically load/store/AMO a misaligned access that is fully contained in a +MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region. + +[NOTE] +Even if the hart" +MISALIGNED_SPLIT_STRATEGY,"The *order* the implementation appears +to process a non-atomic misaligned load/store, which determines how/which +exceptions will be reported.",NORM_DIRECT,medium,Misaligned access behavior parameter,binary,"choices: ['sequential_bytes', 'custom']",Sm,ext:Sm AND param:MISALIGNED_LDST(equal=True),False,0,,machine.adoc,1976,5,True,False,[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or,"Options: + + * sequential_bytes: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address + * custom: Something else. Will result in a call to unpredictable() in the execution" +MISA_CSR_IMPLEMENTED,Whether or not the `misa` CSR is implemented,NORM_DIRECT,high,Feature/CSR existence parameter ('IMPLEMENTED' suffix),binary,"choices: [True, False]",Sm,ext:Sm,False,3,mstatus,machine.adoc,23,12,True,False,"but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standar","Options: + + true:: + The `misa` CSR returns a non-zero value. + + false:: + The `misa` CSR is read-only-0." +MSTATEEN_AIA_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'mstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","Smstateen, Ssaia",ext:Ssaia AND ext:Smstateen(~> 1.0),False,0,,,,0,,,,"Behavior of the mstateen0.AIA bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +MSTATEEN_CONTEXT_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'mstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","Sdtrig, Smstateen",ext:Sdtrig AND ext:Smstateen,False,0,,smctr.adoc,652,5,True,False,"[#norm:ccounter_reset]#The CtrCycleCounter is reset on writes to `__x__ctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.#","Behavior of the mstateen0.CONTEXT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +MSTATEEN_CSRIND_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'mstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","Smstateen, Sscsrind",ext:Sscsrind AND ext:Smstateen,False,0,,smstateen.adoc,191,3,False,False,"{bits: 1, name: 'CSRIND'},","Behavior of the mstateen0.CSRIND bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +MSTATEEN_ENVCFG_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'mstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","S, Smstateen",ext:S AND ext:Smstateen,False,0,,priv-cfi.adoc,134,3,False,False,*__x__*`envcfg.SSE` fields. The conditions are specified as follows:,"Behavior of the mstateen0.ENVCFG bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +MSTATEEN_IMSIC_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'mstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","Smstateen, Ssaia",ext:Ssaia AND ext:Smstateen(~> 1.0),False,0,,smstateen.adoc,189,3,False,False,"{bits: 1, name: 'IMSIC'},","Behavior of the mstateen0.IMSIC bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +MSTATEEN_JVT_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'mstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","Smstateen, Zcmt",ext:Zcmt AND ext:Smstateen(~> 1.0),False,0,,zc.adoc,2341,4,True,False,"[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#","Behavior of the mstateen0.JVT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +MSTATUS_FS_LEGAL_VALUES,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of mstatus.FS,set,"subset of [0, 1, 2, 3]","F, S",(ext:F OR ext:S),True,3,mstatus,machine.adoc,679,11,True,False,"[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that",The set of values that mstatus.FS supports. +MSTATUS_TVM_IMPLEMENTED,TODO,NORM_DIRECT,high,Feature/CSR existence parameter ('IMPLEMENTED' suffix),binary,"choices: [True, False]",S,ext:S,False,2,mstatus,hypervisor.adoc,999,12,True,False,"addresses. [#norm:hgatp_tvm_illegal]#When `mstatus`.TVM=1, attempts to read or write `hgatp` while","Whether or not mstatus.TVM is implemented. + +When not implemented mstatus.TVM will be read-only-zero." +MSTATUS_VS_LEGAL_VALUES,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of mstatus.VS,set,"subset of [0, 1, 2, 3]","S, V",(ext:V OR ext:S),True,3,mstatus,machine.adoc,679,11,True,False,"[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that",The set of values that mstatus.VS will accept from a software write. +MTVAL_WIDTH,Width of the `mtval` CSR,NORM_DIRECT,medium,Trap value reporting parameter,conditional,2 conditional branches,Sm,ext:Sm,True,0,,hypervisor.adoc,25,6,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","The number of implemented bits in the `mtval` CSR. +This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to +assist software in handling the trap (e.g., address associated with exception). + +Must be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `V" +MTVEC_ACCESS,Acess type of the `mtvec` CSR (read-only or read-write).,NORM_CSR_RW,high,Controls type (RO/RW) of mtvec.BASE,binary,"choices: ['ro', 'rw']",Sm,ext:Sm,False,2,mtvec,machine.adoc,1209,17,True,False,[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds,"Options: + + ro:: + `mtvec` is read-only. + + rw:: + `mtvec` is read-write, but may not accept all values." +MTVEC_BASE_ALIGNMENT_DIRECT,Minumum alignment of `mtvec.BASE` when `mtvec.MODE` is 0 (direct),NORM_CSR_WARL,low,"Name pattern suggests CSR 'mtvec' association, but no IDL cross-reference found",conditional,2 conditional branches,Sm,"ext:Sm AND {'param': {'allOf': [{'name': 'MTVEC_MODES', 'includes': 0, 'reason': 'Only rele",False,0,,machine.adoc,1209,6,True,False,[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds,"Minimum alignment of the base pointer. Because `mtvec` excludes the two least-significant bits of +the base, the minimum alignment cannot be less than 4." +MTVEC_BASE_ALIGNMENT_VECTORED,Minumum alignment of `mtvec.BASE` when `mtvec.MODE` is 1 (vectored),NORM_CSR_WARL,low,"Name pattern suggests CSR 'mtvec' association, but no IDL cross-reference found",conditional,2 conditional branches,Sm,"ext:Sm AND {'param': {'allOf': [{'name': 'MTVEC_MODES', 'includes': 1, 'reason': 'Only rele",False,0,,priv-preface.adoc,540,7,False,False,* Optional vectored interrupt support has been added to the `mtvec` and,"Because `mtvec` excludes the two least-significant bits of +the base, the minimum alignment cannot be less than 4." +MTVEC_ILLEGAL_WRITE_BEHAVIOR,What happens when `mtvec` is written with an illegal value,NORM_CSR_WARL,high,Referenced in sw_write() of mtvec.BASE,binary,"choices: ['retain', 'custom']",Sm,ext:Sm,False,2,mtvec,machine.adoc,1209,18,True,False,[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds,"Options: + + retain:: + When either `mtvec.MODE` or `mtvec.BASE` is illegal, `mtvec` will retain its current value + + custom:: + When either `mtvec.MODE` or `mtvec.BASE` is illegal, `mtvec` will obtain an unpredictable value + +Other values may be added over time once other common behaviors are ide" +MTVEC_MODES,Modes supported by `mtvec.MODE`,NORM_CSR_WARL,high,Referenced in sw_write() of mtvec.BASE,set,"subset of [0, 1]",Sm,ext:Sm,True,4,mtvec,machine.adoc,1255,18,False,False,machine mode cause the `pc` to be set to the address in the BASE field.#,"Options: + + 0:: + Direct; All traps set `pc` to `mtvec.BASE` + 1:: + Vectored; Asynchronous interrupts set `pc` to `mtvec.BASE` + 4 x cause. + +If only one mode is given, `mtvec.MODE` is assumed to be read-only with that value. +Otherwise, `mtvec.MODE` is read-write." +MUTABLE_MISA_A,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.A,binary,"choices: [True, False]",A,ext:A,False,2,misa,machine.adoc,21,16,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,"When the `A` extensions is supported, indicates whether or not +the extension can be disabled in the `misa.A` bit." +MUTABLE_MISA_B,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.B,binary,"choices: [True, False]",B,ext:B,False,1,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `B` extension can be disabled with the `misa.B` bit. +MUTABLE_MISA_C,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.C,binary,"choices: [True, False]",C,ext:C,False,1,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `C` extension can be disabled with the `misa.C` bit. +MUTABLE_MISA_D,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.D,binary,"choices: [True, False]",D,ext:D,False,2,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `D` extension can be disabled with the `misa.D` bit. +MUTABLE_MISA_F,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.F,binary,"choices: [True, False]",F,ext:F,False,2,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `F` extension can be disabled with the `misa.F` bit. +MUTABLE_MISA_H,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.H,binary,"choices: [True, False]",H,ext:H,True,1,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `H` extension can be disabled with the `misa.H` bit. +MUTABLE_MISA_M,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.G,binary,"choices: [True, False]",M,ext:M,False,2,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `M` extension can be disabled with the `misa.M` bit. +MUTABLE_MISA_Q,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.Q,binary,"choices: [True, False]",Q,ext:Q,False,1,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `Q` extension can be disabled with the `misa.Q` bit. +MUTABLE_MISA_S,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.S,binary,"choices: [True, False]",S,ext:S,True,1,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `S` extension can be disabled with the `misa.S` bit. +MUTABLE_MISA_U,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.U,binary,"choices: [True, False]",U,ext:U,False,1,misa,machine.adoc,21,11,True,False,[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.,Indicates whether or not the `U` extension can be disabled with the `misa.U` bit. +MUTABLE_MISA_V,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of misa.V,binary,"choices: [True, False]",V,ext:V,False,1,misa,v-st-ext.adoc,5161,14,True,False,[#norm:misa-V_op]#The `misa.v` bit is set for implementations providing `misa` and,Indicates whether or not the `V` extension can be disabled with the `misa.V` bit. +MXLEN,XLEN in machine mode,NORM_DIRECT,high,Well-known architectural parameter 'MXLEN',binary,"choices: [32, 64]",Sm,ext:Sm,True,69,"hcontext, mconfigptr, misa, pmpaddr0, pmpaddr1, pmpaddr10, pmpaddr11, pmpaddr12, pmpaddr13, pmpaddr14, pmpaddr15, pmpaddr16, pmpaddr17, pmpaddr18, pmpaddr19, pmpaddr2, pmpaddr20, pmpaddr21, pmpaddr22, pmpaddr23, pmpaddr24, pmpaddr25, pmpaddr26, pmpaddr27, pmpaddr28, pmpaddr29, pmpaddr3, pmpaddr30, pmpaddr31, pmpaddr32, pmpaddr33, pmpaddr34, pmpaddr35, pmpaddr36, pmpaddr37, pmpaddr38, pmpaddr39, pmpaddr4, pmpaddr40, pmpaddr41, pmpaddr42, pmpaddr43, pmpaddr44, pmpaddr45, pmpaddr46, pmpaddr47, pmpaddr48, pmpaddr49, pmpaddr5, pmpaddr50, pmpaddr51, pmpaddr52, pmpaddr53, pmpaddr54, pmpaddr55, pmpaddr56, pmpaddr57, pmpaddr58, pmpaddr59, pmpaddr6, pmpaddr60, pmpaddr61, pmpaddr62, pmpaddr63, pmpaddr7, pmpaddr8, pmpaddr9, satp, vsatp",machine.adoc,50,12,True,False,[#norm:misa_sz]#The `misa` CSR is MXLEN bits wide.#,"XLEN in machine mode, specified in bits" +M_MODE_ENDIANNESS,Endianness of data in M-mode,NORM_CSR_RW,high,Controls type (RO/RW) of mstatus.MBE,enum,"values: ['little', 'big', 'dynamic']",Sm,ext:Sm,False,4,"mstatus, mstatush",machine.adoc,679,22,True,False,"[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that","Options: + +[separator=""!""] +!=== +h! little ! M-mode data is always little endian +h! big ! M-mode data is always big endian +h! dynamic ! M-mode data can be either little or big endian, + depending on the CSR field `mstatus.MBE` +!===" +NUM_EXTERNAL_GUEST_INTERRUPTS,TODO,NORM_DIRECT,high,Well-known architectural parameter 'NUM_EXTERNAL_GUEST_INTERRUPTS',conditional,2 conditional branches,H,ext:H,False,3,hstatus,hypervisor.adoc,259,9,False,False,"VS-level external interrupts. GEILEN may be zero, in which case VGEIN","Number of supported virtualized guest interrupts + +Corresponds to the `GEILEN` parameter in the RVI specs" +NUM_PMP_ENTRIES,TODO,NORM_DIRECT,high,Well-known architectural parameter 'NUM_PMP_ENTRIES',range,[0..64],Smpmp,ext:Smpmp,False,224,"pmpaddr0, pmpaddr1, pmpaddr10, pmpaddr11, pmpaddr12, pmpaddr13, pmpaddr14, pmpaddr15, pmpaddr16, pmpaddr17, pmpaddr18, pmpaddr19, pmpaddr2, pmpaddr20, pmpaddr21, pmpaddr22, pmpaddr23, pmpaddr24, pmpaddr25, pmpaddr26, pmpaddr27, pmpaddr28, pmpaddr29, pmpaddr3, pmpaddr30, pmpaddr31, pmpaddr32, pmpaddr33, pmpaddr34, pmpaddr35, pmpaddr36, pmpaddr37, pmpaddr38, pmpaddr39, pmpaddr4, pmpaddr40, pmpaddr41, pmpaddr42, pmpaddr43, pmpaddr44, pmpaddr45, pmpaddr46, pmpaddr47, pmpaddr48, pmpaddr49, pmpaddr5, pmpaddr50, pmpaddr51, pmpaddr52, pmpaddr53, pmpaddr54, pmpaddr55, pmpaddr56, pmpaddr57, pmpaddr58, pmpaddr59, pmpaddr6, pmpaddr60, pmpaddr61, pmpaddr62, pmpaddr63, pmpaddr7, pmpaddr8, pmpaddr9, pmpcfg0, pmpcfg1, pmpcfg10, pmpcfg11, pmpcfg12, pmpcfg13, pmpcfg14, pmpcfg15, pmpcfg2, pmpcfg3, pmpcfg4, pmpcfg5, pmpcfg6, pmpcfg7, pmpcfg8, pmpcfg9",machine.adoc,668,4,True,False,"Note that, [#norm:mstatus_sum_op_mprv_mpp]#while SUM is ordinarily ignored when not","Number of implemented PMP entries. Can be any value between 0-64, inclusive. + +The architecture mandates that the number of implemented PMP registers +must appear to be 0, 16, or 64. + +Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES: + +[separator=""!""] +!=== +! NUM_PMP_ENTRIES " +PHYS_ADDR_WIDTH,Number of bits in a physical address,NORM_DIRECT,high,Well-known architectural parameter 'PHYS_ADDR_WIDTH',conditional,2 conditional branches,Sm,ext:Sm,True,128,"pmpaddr0, pmpaddr1, pmpaddr10, pmpaddr11, pmpaddr12, pmpaddr13, pmpaddr14, pmpaddr15, pmpaddr16, pmpaddr17, pmpaddr18, pmpaddr19, pmpaddr2, pmpaddr20, pmpaddr21, pmpaddr22, pmpaddr23, pmpaddr24, pmpaddr25, pmpaddr26, pmpaddr27, pmpaddr28, pmpaddr29, pmpaddr3, pmpaddr30, pmpaddr31, pmpaddr32, pmpaddr33, pmpaddr34, pmpaddr35, pmpaddr36, pmpaddr37, pmpaddr38, pmpaddr39, pmpaddr4, pmpaddr40, pmpaddr41, pmpaddr42, pmpaddr43, pmpaddr44, pmpaddr45, pmpaddr46, pmpaddr47, pmpaddr48, pmpaddr49, pmpaddr5, pmpaddr50, pmpaddr51, pmpaddr52, pmpaddr53, pmpaddr54, pmpaddr55, pmpaddr56, pmpaddr57, pmpaddr58, pmpaddr59, pmpaddr6, pmpaddr60, pmpaddr61, pmpaddr62, pmpaddr63, pmpaddr7, pmpaddr8, pmpaddr9",hypervisor.adoc,1027,3,False,False,<>.,Implementation-defined size of the physical address space. +PMA_GRANULARITY,log2 of the smallest supported PMA region,NORM_DIRECT,high,Well-known architectural parameter 'PMA_GRANULARITY',range,[2..66],Sm,ext:Sm,False,0,,cmo.adoc,754,3,False,False,"granularity and atomicity, including individual bytes.","Generally, for systems with an MMU, should not be smaller than 12, +as that would preclude caching PMA results in the TLB along with +virtual memory translations" +PMLEN,TODO,NORM_DIRECT,high,Well-known architectural parameter 'PMLEN',value,{'base': 'integer'},"Smmpm, Smnpm, Ssnpm",(ext:Smmpm OR ext:Smnpm OR ext:Ssnpm),False,0,,hypervisor.adoc,807,7,False,False,|00|Pointer masking is disabled (PMLEN = 0),"The number of high-order bits of an address that are masked by the +pointer masking facility." +PMP_GRANULARITY,TODO,NORM_DIRECT,high,Well-known architectural parameter 'PMP_GRANULARITY',range,[2..66],Smpmp,ext:Smpmp,False,160,"pmpaddr0, pmpaddr1, pmpaddr10, pmpaddr11, pmpaddr12, pmpaddr13, pmpaddr14, pmpaddr15, pmpaddr16, pmpaddr17, pmpaddr18, pmpaddr19, pmpaddr2, pmpaddr20, pmpaddr21, pmpaddr22, pmpaddr23, pmpaddr24, pmpaddr25, pmpaddr26, pmpaddr27, pmpaddr28, pmpaddr29, pmpaddr3, pmpaddr30, pmpaddr31, pmpaddr32, pmpaddr33, pmpaddr34, pmpaddr35, pmpaddr36, pmpaddr37, pmpaddr38, pmpaddr39, pmpaddr4, pmpaddr40, pmpaddr41, pmpaddr42, pmpaddr43, pmpaddr44, pmpaddr45, pmpaddr46, pmpaddr47, pmpaddr48, pmpaddr49, pmpaddr5, pmpaddr50, pmpaddr51, pmpaddr52, pmpaddr53, pmpaddr54, pmpaddr55, pmpaddr56, pmpaddr57, pmpaddr58, pmpaddr59, pmpaddr6, pmpaddr60, pmpaddr61, pmpaddr62, pmpaddr63, pmpaddr7, pmpaddr8, pmpaddr9, pmpcfg0, pmpcfg1, pmpcfg10, pmpcfg11, pmpcfg12, pmpcfg13, pmpcfg14, pmpcfg15, pmpcfg2, pmpcfg3, pmpcfg4, pmpcfg5, pmpcfg6, pmpcfg7, pmpcfg8, pmpcfg9",cmo.adoc,754,3,False,False,"granularity and atomicity, including individual bytes.","log2 of the smallest supported PMP region. + +Generally, for systems with an MMU, should not be smaller than 12, +as that would preclude caching PMP results in the TLB along with +virtual memory translations + +Note that PMP_GRANULARITY is equal to G+2 (not G) as described in +the privileged architecture." +PRECISE_SYNCHRONOUS_EXCEPTIONS,Whether or not all synchronous exceptions are precise.,NORM_DIRECT,high,Trap/report behavior parameter (matches ^PRECISE_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,1256,4,True,False,"[#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause","If false, any exception not otherwise mandated to precise (e.g., PMP violation) +will cause execution to enter an unpredictable state." +RCID_WIDTH,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of srmcfg.RCID,range,[1..12],Ssqosid,ext:Ssqosid,False,1,srmcfg,supervisor.adoc,2586,8,False,False,The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege,"Number of bits used for the Resource Control ID field (RCID). +Default is 12." +REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Zicfilp,ext:Zicfilp,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","When true, `mtval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into M-mode due to a landing pad error. + +When false, `mtval` is written with 0." +REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Zicfiss,ext:Zicfiss,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","When true, `mtval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into M-mode due to a shadow stack pop check instruction. + +When false, `mtval` is written with 0." +REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Zicfilp,ext:Zicfilp,False,0,,supervisor.adoc,707,9,True,False,[[norm:stval]],"When true, `stval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into S-mode due to a landing pad error. + +When false, `stval` is written with 0." +REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Zicfiss,ext:Zicfiss,False,0,,supervisor.adoc,707,9,True,False,[[norm:stval]],"When true, `stval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into S-mode due to a shadow stack pop check instruction. + +When false, `stval` is written with 0." +REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Zicfilp,ext:Zicfilp,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error. + +When false, `vstval` is written with 0." +REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Zicfiss,ext:Zicfiss,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into VS-mode due to a shadow stack pop check instruction. + +When false, `vstval` is written with 0." +REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION,Whether or not `mtval` is written with the encoding of an instruction causing an IllegalInstruction exception,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,2082,11,False,False,"nonzero value when an illegal-instruction exception occurs, then `mtval`","Options: + + * true: `mtval` is written with the encoding of an instruction causing an IllegalInstruction exception + * false: `mtval` is written with 0 when an instruction causes an IllegalInstruction exception." +REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,751,11,False,False,"nonzero value when an illegal-instruction exception occurs, then `stval`","When true, `stval` is written with the encoding of an instruction that causes an +`IllegalInstruction` exception. + +When false `stval` is written with 0 when an `IllegalInstruction` exception occurs." +REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the encoding of an instruction that causes an +`IllegalInstruction` exception. + +When false `vstval` is written with 0 when an `IllegalInstruction` exception occurs." +REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,8,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the encoding of an instruction that causes an +`VirualInstruction` exception. + +When false `vstval` is written with 0 when an `VirtualInstruction` exception occurs." +REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,917,9,False,False,"When a guest-page-fault trap is taken into HS-mode, `htval` is written","When true, `htval` is written with the Guest Physical Address, shifted right by 2, that +caused a `GuestPageFault` exception. + +When false, `htval` is written with 0 when a `GuestPageFault` exception occurs." +REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,2,"htval, mtval2",hypervisor.adoc,2832,8,False,False,"`mtval2` or `htval`. If both conditions are met, the value written to","Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs. + +If false, 0 will be written into htval/mtval2 on an instruction guest page fault." +REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,2,"htval, mtval2",hypervisor.adoc,2832,8,False,False,"`mtval2` or `htval`. If both conditions are met, the value written to","Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while +walking a VS-mode page table. + +If false, 0 will be written into htval/mtval2 on an intermediate guest page fault." +REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,2,"htval, mtval2",hypervisor.adoc,2832,8,False,False,"`mtval2` or `htval`. If both conditions are met, the value written to","Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs. + +If false, 0 will be written into htval/mtval2 on a load guest page fault." +REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,2,"htval, mtval2",hypervisor.adoc,2832,8,False,False,"`mtval2` or `htval`. If both conditions are met, the value written to","Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs. + +If false, 0 will be written into htval/mtval2 on a store/amo guest page fault." +REPORT_VA_IN_MTVAL_ON_BREAKPOINT,Whether or not `mtval` is written with the virtual PC of an EBREAK instruction.,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,2049,17,False,False,"On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`","Options: + + * true: `mtval` is written with the virtual PC of an EBREAK instruction (same information as `mepc`). + * false: `mtval` is written with 0 on an EBREAK instruction. + +Regardless, `mtval` is always written with a virtual PC when an external breakpoint is generated" +REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT,Whether or not `mtval` is written with the virtual address of a fetch causing an access fault,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","Options: + + * true: `mtval` is written with the virtual address of a fetch causing the access fault + * false: `mtval` is written with 0 when a fetch causes an access fault" +REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED,Whether or not `mtval` is written with the virtual address of a misaligned fetch,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","Options: + + * true: `mtval` is written with the virtual address of a trapping misaligned fetch + * false: `mtval` is written with 0 when a misaligned fetch traps" +REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","When true, `mtval` is written with the virtual PC of an instructino when fetch causes an +`InstructionPageFault`. + +WHen false, `mtval` is written with 0 when an instruction fetch causes an +`InstructionPageFault`." +REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT,Whether or not `mtval` is written with the virtual address of a load causing an access fault,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","Options: + + * true: `mtval` is written with the virtual address of a load causing the access fault + * false: `mtval` is written with 0 when a load causes an access fault" +REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED,Whether or not `mtval` is written with the virtual address of a misaligned load,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,machine.adoc,2067,11,False,False,If `mtval` is written with a nonzero value when a misaligned load or,"Options: + + * true: `mtval` is written with the virtual address of a trapping misaligned load. + * false: `mtval` is written with 0 when a misaligned load traps." +REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","When true, `mtval` is written with the virtual address of a load when it causes a +`LoadPageFault`. + +WHen false, `mtval` is written with 0 when a load causes a `LoadPageFault`." +REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT,Whether or not `mtval` is written with the virtual address of a store or AMO causing an access fault,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","Options: + + * true: `mtval` is written with the virtual address of a store or AMO causing the access fault + * false: `mtval` is written with 0 when a store or AMO causes an access fault" +REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED,Whether or not `mtval` is written with the virtual address of a misaligned store or AMO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",Sm,ext:Sm,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","Options: + + * true: `mtval` is written with the virtual address of a trapping misaligned store or AMO. + * false: `mtval` is written with 0 when a misaligned store or AMO traps." +REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,25,10,True,False,"registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and","When true, `mtval` is written with the virtual address of a store when it causes a +`StoreAmoPageFault`. + +WHen false, `mtval` is written with 0 when a store causes a `StoreAmoPageFault`." +REPORT_VA_IN_STVAL_ON_BREAKPOINT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,726,17,False,False,"On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`","When true, `stval` is written with the virtual PC of the EBREAK instruction (same information as `mepc`). + +When false, `stval` is written with 0 on an EBREAK instruction. + +Regardless, `stval` is always written with a virtual PC when an external breakpoint is generated" +REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,936,10,False,False,the instruction as indicated by the virtual address in `stval`.,"When true, `stval` is written with the virtual PC of an instructino when fetch causes an +`InstructionAccessFault`. + +WHen false, `stval` is written with 0 when an instruction fetch causes an +`InstructionAccessFault`." +REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,726,13,False,False,"On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`","When true, `stval` is written with the virtual PC when an instruction fetch is misaligned. + +When false, `stval` is written with 0 when an instruction fetch is misaligned. + +Note that when IALIGN=16 (i.e., when the `C` or one of the `Zc*` extensions are implemented), +it is impossible to generate a mis" +REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,936,10,False,False,the instruction as indicated by the virtual address in `stval`.,"When true, `stval` is written with the virtual PC of an instructino when fetch causes an +`InstructionPageFault`. + +WHen false, `stval` is written with 0 when an instruction fetch causes an +`InstructionPageFault`." +REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,707,9,True,False,[[norm:stval]],"When true, `stval` is written with the virtual address of a load when it causes a +`LoadAccessFault`. + +WHen false, `stval` is written with 0 when a load causes a `LoadAccessFault`." +REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,734,11,False,False,If `stval` is written with a nonzero value when a misaligned load or,"When true, `stval` is written with the virtual address of a load instruction when the +address is misaligned and MISALIGNED_LDST is false. + +When false, `stval` is written with 0 when a load address is misaligned and +MISALIGNED_LDST is false." +REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,2046,9,False,False,"modes. On a guest-page fault, CSR `mtval` or `stval` is written with the","When true, `stval` is written with the virtual address of a load when it causes a +`LoadPageFault`. + +WHen false, `stval` is written with 0 when a load causes a `LoadPageFault`." +REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,707,9,True,False,[[norm:stval]],"When true, `stval` is written with the virtual address of a store when it causes a +`StoreAmoAccessFault`. + +WHen false, `stval` is written with 0 when a store causes a `StoreAmoAccessFault`." +REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,supervisor.adoc,734,10,False,False,If `stval` is written with a nonzero value when a misaligned load or,"When true, `stval` is written with the virtual address of a store instruction when the +address is misaligned and MISALIGNED_LDST is false. + +When false, `stval` is written with 0 when a store address is misaligned and +MISALIGNED_LDST is false." +REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",S,ext:S,False,0,,hypervisor.adoc,2046,9,False,False,"modes. On a guest-page fault, CSR `mtval` or `stval` is written with the","When true, `stval` is written with the virtual address of a store when it causes a +`StoreAmoPageFault`. + +WHen false, `stval` is written with 0 when a store causes a `StoreAmoPageFault`." +REPORT_VA_IN_VSTVAL_ON_BREAKPOINT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,10,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the virtual PC of the EBREAK instruction (same information as `mepc`). + +When false, `vstval` is written with 0 on an EBREAK instruction. + +Regardless, `vstval` is always written with a virtual PC when an external breakpoint is generated." +REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,zc.adoc,1183,9,True,False,"[#norm:Zcmp_trap]#If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and","When true, `vstval` is written with the virtual PC of an instructino when fetch causes an +`InstructionAccessFault`. + +WHen false, `vstval` is written with 0 when an instruction fetch causes an +`InstructionAccessFault`." +REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,c-st-ext.adoc,310,8,True,False,[#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value,"When true, `vstval` is written with the virtual PC when an instruction fetch is misaligned. + +When false, `vstval` is written with 0 when an instruction fetch is misaligned. + +Note that when IALIGN=16 (i.e., when the `C` or one of the `Zc*` extensions are implemented), +it is impossible to generate a m" +REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,zc.adoc,1183,8,True,False,"[#norm:Zcmp_trap]#If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and","When true, `vstval` is written with the virtual PC of an instructino when fetch causes an +`InstructionPageFault`. + +WHen false, `vstval` is written with 0 when an instruction fetch causes an +`InstructionPageFault`." +REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1371,8,False,False,"actually access `vstval` instead. When V=0, `vstval` does not directly","When true, `vstval` is written with the virtual address of a load when it causes a +`LoadAccessFault`. + +WHen false, `vstval` is written with 0 when a load causes a `LoadAccessFault`." +REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the virtual address of a load instruction when the +address is misaligned and MISALIGNED_LDST is false. + +When false, `vstval` is written with 0 when a load address is misaligned and +MISALIGNED_LDST is false." +REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the virtual address of a load when it causes a +`LoadPageFault`. + +WHen false, `vstval` is written with 0 when a load causes a `LoadPageFault`." +REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1371,8,False,False,"actually access `vstval` instead. When V=0, `vstval` does not directly","When true, `vstval` is written with the virtual address of a store when it causes a +`StoreAmoAccessFault`. + +WHen false, `vstval` is written with 0 when a store causes a `StoreAmoAccessFault`." +REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the virtual address of a store instruction when the +address is misaligned and MISALIGNED_LDST is false. + +When false, `vstval` is written with 0 when a store address is misaligned and +MISALIGNED_LDST is false." +REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT,TODO,NORM_DIRECT,high,Trap/report behavior parameter (matches ^REPORT_),binary,"choices: [True, False]",H,ext:H,False,0,,hypervisor.adoc,1364,7,False,False,==== Virtual Supervisor Trap Value (`vstval`) Register,"When true, `vstval` is written with the virtual address of a store when it causes a +`StoreAmoPageFault`. + +WHen false, `vstval` is written with 0 when a store causes a `StoreAmoPageFault`." +RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX,TODO,NORM_DIRECT,low,No strong signals; defaulting to direct normative parameter,enum,"values: ['ceil(AVL/2)', 'VLMAX', 'custom']",V,ext:V,False,0,,v-st-ext.adoc,1279,9,True,False,"[#norm:vsetvl_op_rs1_x0_rd_x0]#When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not t",The value assigned to VL when AVL < 2*VLMAX. +SATP_MODE_BARE,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of satp.MODE,binary,"choices: [True, False]",S,ext:S,False,1,satp,machine.adoc,670,11,True,False,[#norm:mstatus_sum_rdonly0]#SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.#,Whether or not satp.MODE == Bare is supported. +SCOUNTENABLE_EN,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of scounteren.CY,bitmask,32-bit mask,"S, Zicntr, Zihpm",ext:S AND (ext:Zicntr OR ext:Zihpm),True,64,scounteren,supervisor.adoc,511,12,False,False,"When the CY, TM, IR, or HPM__n__ bit in the `scounteren` register is","Indicates which counters can delegated via `scounteren` + +An unimplemented counter cannot be specified, i.e., if +HPM_COUNTER_EN[3] is false, it would be illegal to set +SCOUNTENABLE_EN[3] to true. + +SCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented. +SCOUNTENABLE_EN[3:31] must all be" +SSTATEEN_JVT_TYPE,TODO,NORM_CSR_RW,low,CSR field type control parameter for 'sstateen' (determines RO/RW behavior),enum,"values: ['rw', 'read-only-0', 'read-only-1']","Ssstateen, Zcmt",ext:Zcmt AND ext:Ssstateen,True,0,,zc.adoc,2341,4,True,False,"[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#","Behavior of the sstateen0.JVT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1" +STVAL_WIDTH,TODO,NORM_DIRECT,medium,Trap value reporting parameter,range,[None..18446744073709551615],S,ext:S,False,0,,supervisor.adoc,707,6,True,False,[[norm:stval]],"The number of implemented bits in `stval`. + +Must be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `VA_SIZE`)" +STVEC_MODE_DIRECT,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of stvec.MODE,binary,"choices: [True, False]",S,ext:S,True,1,stvec,hypervisor.adoc,1304,8,False,False,"VS-mode’s version of supervisor register `stvec`, formatted as shown in",Whether or not `stvec.MODE` supports Direct (0). +STVEC_MODE_VECTORED,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of stvec.MODE,binary,"choices: [True, False]",S,ext:S,True,1,stvec,machine.adoc,1256,9,True,False,"[#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause",Whether or not `stvec.MODE` supports Vectored (1). +SV32X4_TRANSLATION,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of hgatp.MODE,binary,"choices: [True, False]",H,ext:H AND param:SXLEN(includes=32),True,3,hgatp,hypervisor.adoc,1915,9,False,False,"When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,",Whether or not Sv32x4 translation mode is supported. +SV32_VSMODE_TRANSLATION,TODO,NORM_DIRECT,medium,Translation/mode parameter,binary,"choices: [True, False]",H,ext:H AND param:VSXLEN(includes=32),True,0,,cmo.adoc,365,5,True,False,"otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed","Whether or not Sv32 translation is supported in first-stage (VS-stage) +translation." +SV39X4_TRANSLATION,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of hgatp.MODE,binary,"choices: [True, False]",H,ext:H AND param:SXLEN(includes=64),True,3,hgatp,hypervisor.adoc,1007,9,False,False,".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.",Whether or not Sv39x4 translation mode is supported. +SV39_VSMODE_TRANSLATION,TODO,NORM_DIRECT,medium,Translation/mode parameter,binary,"choices: [True, False]",H,ext:H AND param:VSXLEN(includes=64),True,0,,cmo.adoc,365,5,True,False,"otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed","Whether or not Sv39 translation is supported in first-stage (VS-stage) +translation." +SV48X4_TRANSLATION,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of hgatp.MODE,binary,"choices: [True, False]",H,ext:H AND param:SXLEN(includes=64),True,3,hgatp,hypervisor.adoc,1007,9,False,False,".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.",Whether or not Sv48x4 translation mode is supported. +SV48_VSMODE_TRANSLATION,TODO,NORM_DIRECT,medium,Translation/mode parameter,binary,"choices: [True, False]",H,ext:H AND param:VSXLEN(includes=64),True,0,,cmo.adoc,365,5,True,False,"otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed","Whether or not Sv48 translation is supported in first-stage (VS-stage) +translation." +SV57X4_TRANSLATION,TODO,NORM_CSR_WARL,high,Referenced in sw_write() of hgatp.MODE,binary,"choices: [True, False]",H,ext:H AND param:SXLEN(includes=64),True,3,hgatp,hypervisor.adoc,1007,9,False,False,".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.",Whether or not Sv57x4 translation mode is supported. +SV57_VSMODE_TRANSLATION,TODO,NORM_DIRECT,medium,Translation/mode parameter,binary,"choices: [True, False]",H,ext:H AND param:VSXLEN(includes=64),True,0,,cmo.adoc,365,5,True,False,"otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed","Whether or not Sv57 translation is supported in first-stage (VS-stage) +translation." +SXLEN,TODO,NORM_DIRECT,high,Well-known architectural parameter 'SXLEN',set,"subset of [32, 64]",S,ext:S,True,3,"hstatus, mstatus",machine.adoc,575,11,False,False,"When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.","Set of XLENs supported in S-mode. Can be one of: + + * 32: SXLEN is always 32 + * 64: SXLEN is always 64 + * [32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64" +S_MODE_ENDIANNESS,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of mstatus.SBE,enum,"values: ['little', 'big', 'dynamic']",S,ext:S,False,4,"mstatus, mstatush",machine.adoc,679,22,True,False,"[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that","Endianness of data in S-mode. Can be one of: + + * little: S-mode data is always little endian + * big: S-mode data is always big endian + * dynamic: S-mode data can be either little or big endian, + depending on the CSR field `mstatus.SBE`" +TIME_CSR_IMPLEMENTED,TODO,NORM_DIRECT,high,Feature/CSR existence parameter ('IMPLEMENTED' suffix),binary,"choices: [True, False]",Zicntr,ext:Zicntr,False,2,"time, timeh",machine.adoc,2621,25,False,False,"When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`","Whether or not a real hardware `time` CSR exists. Implementations can either provide a real +CSR or emulate access at M-mode. + +Possible values: + +true:: + `time`/`timeh` exists, and accessing it will not cause an IllegalInstruction trap + +false:: + `time`/`timeh` does not exist. + Accessing the CSR wil" +TINST_VALUE_ON_BREAKPOINT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""custom"": Write a custom value, which results in UNPREDICTABLE" +TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'always pseudoinstruction']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,2567,9,False,False,==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`,"Value to write into htval/mtval2 when there is a guest page fault on a final translation. + +Possible values: + * ""always zero"": Always write the value zero + * ""always pseudoinstruction"": Always write the pseudoinstruction" +TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always pseudoinstruction', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value to write into htval/mtval2 when there is a guest page fault on a final translation. + +Possible values: + * ""always zero"": Always write the value zero + * ""always pseudoinstruction"": Always write the pseudoinstruction + * ""always transformed standard instruction"": Always write the transformation" +TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always pseudoinstruction', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value to write into htval/mtval2 when there is a guest page fault on a final translation. + +Possible values: + * ""always zero"": Always write the value zero + * ""always pseudoinstruction"": Always write the pseudoinstruction + * ""always transformed standard instruction"": Always write the transformation" +TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,2567,9,False,False,==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`,"Value written into htinst/mtinst when there is an instruction address misaligned exception. + +Possible values: + * ""always zero"": Always write the value zero + * ""custom"": Write a custom value, which results in UNPREDICTABLE" +TINST_VALUE_ON_LOAD_ACCESS_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""always transformed standard instruction"": Always write a transformed standard instruction as defined by H + * ""custom"": Write a custom value, which resu" +TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""always transformed standard instruction"": Always write a transformed standard instruction as defined by H + * ""custom"": Write a custom value, whic" +TINST_VALUE_ON_LOAD_PAGE_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""always transformed standard instruction"": Always write a transformed standard instruction as defined by H + * ""custom"": Write a custom value, which res" +TINST_VALUE_ON_MCALL,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a MCall exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""custom"": Write a custom value, which results in UNPREDICTABLE" +TINST_VALUE_ON_SCALL,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a SCall exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""custom"": Write a custom value, which results in UNPREDICTABLE" +TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""always transformed standard instruction"": Always write a transformed standard instruction as defined by H + * ""custom"": Write a custom value, which resu" +TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""always transformed standard instruction"": Always write a transformed standard instruction as defined by H + * ""custom"": Write a custom value, whic" +TINST_VALUE_ON_STORE_AMO_PAGE_FAULT,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,enum,"values: ['always zero', 'always transformed standard instruction', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""always transformed standard instruction"": Always write a transformed standard instruction as defined by H + * ""custom"": Write a custom value, which" +TINST_VALUE_ON_UCALL,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'custom']",H,ext:H,False,2,"htinst, mtinst",hypervisor.adoc,983,8,False,False,`htinst` is a *WARL* register that need only be able to hold the values that,"Value written into htinst/mtinst on a UCall exception from VU/VS-mode. + +Possible values: + * ""always zero"": Always write the value zero + * ""custom"": Write a custom value, which results in UNPREDICTABLE" +TINST_VALUE_ON_VIRTUAL_INSTRUCTION,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of htinst.VALUE,binary,"choices: ['always zero', 'custom']",H,ext:H,False,2,"htinst, mtinst",smctr.adoc,218,10,True,False,"[#norm:sctrdepth_mode]#Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.# See <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.","Set of XLENs supported in VS-mode. Can be one of: + + * [32]: VSXLEN is always 32 + * [64]: VSXLEN is always 64 + * [32, 64]: VSXLEN can be changed (via `hstatus.VSXL`) between 32 and 64" +VS_MODE_ENDIANNESS,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of hstatus.VSBE,enum,"values: ['little', 'big', 'dynamic']",H,ext:H,False,2,hstatus,hypervisor.adoc,339,14,False,False,"accesses made from VS-mode are little-endian, and if VSBE=1, they are","Endianness of data in VS-mode. Can be one of: + + * little: VS-mode data is always little endian + * big: VS-mode data is always big endian + * dynamic: VS-mode data can be either little or big endian, + depending on the CSR field `hstatus.VSBE`" +VUXLEN,TODO,NORM_DIRECT,high,Well-known architectural parameter 'VUXLEN',set,"subset of [32, 64]",H,ext:H,True,2,vsstatus,hypervisor.adoc,1181,6,False,False,"The UXL field controls the effective XLEN for VU-mode, which may differ","Set of XLENs supported in VU-mode. When both 32 and 64 are supported, VUXLEN can be changed +via `vsstatus.UXL`." +VU_MODE_ENDIANNESS,TODO,NORM_CSR_RW,high,Controls type (RO/RW) of vsstatus.UBE,enum,"values: ['little', 'big', 'dynamic']",H,ext:H,False,2,vsstatus,hypervisor.adoc,2359,10,True,False,"* [#norm:H_virtinst_vu_nonhighctr_h0_s0_m1]#in VU-mode, attempts to access a non-high-half counter CSR when the","Endianness of data in VU-mode. Can be one of: + + * little: VU-mode data is always little endian + * big: VU-mode data is always big endian + * dynamic: VU-mode data can be either little or big endian, + depending on the CSR field `vsstatus.UBE`" diff --git a/param_extraction/data/phase1_report.txt b/param_extraction/data/phase1_report.txt new file mode 100644 index 0000000000..672b889799 --- /dev/null +++ b/param_extraction/data/phase1_report.txt @@ -0,0 +1,821 @@ +======================================================================== +PHASE 1 REPORT: UDB Parameter Ground Truth +RISC-V Architectural Parameter Extraction Project +======================================================================== + +1. OVERVIEW +---------------------------------------- + Total real parameters in UDB: 185 + Spec files searched: 74 + Total spec lines: 52602 + Parameters with spec matches: 183 (98%) + Parameters with strong matches: 161 (87%) + +2. CLASSIFICATION BREAKDOWN +---------------------------------------- + NORM_CSR_RW 55 (29%) + NORM_CSR_WARL 26 (14%) + NORM_DIRECT 102 (55%) + SW_RULE 2 ( 1%) + + Classification descriptions: + NORM_DIRECT = Normative, directly configurable (not CSR-controlled) + NORM_CSR_WARL = Normative, legal values of a WARL CSR field + NORM_CSR_RW = Normative, controls whether CSR field is RO/RW + SW_RULE = Software-deterministic (impl-defined but deterministic w/ correct SW) + +3. VALUE TYPE BREAKDOWN +---------------------------------------- + binary 111 (60%) + bitmask 5 ( 2%) + conditional 10 ( 5%) + enum 36 (19%) + range 12 ( 6%) + set 8 ( 4%) + value 3 ( 1%) + + Value type descriptions: + binary = Exactly 2 choices (boolean or 2-value enum) + enum = Finite set of 3+ discrete values + range = Continuous integer range with min/max bounds + set = Subset selection from a fixed universe of values + bitmask = Fixed-length boolean array (one bit per feature) + conditional = Schema varies based on another parameter (e.g., MXLEN) + value = Single unconstrained value + +4. CLASSIFICATION CONFIDENCE +---------------------------------------- + high 150 (81%) + low 16 ( 8%) + medium 19 (10%) + +5. DEFINING EXTENSIONS (Top 15) +---------------------------------------- + H 61 + Sm 38 + S 29 + Sdtrig 10 + V 7 + Ssstateen 7 + Zcmt 6 + Smstateen 6 + U 5 + Ssaia 4 + Zalrsc 4 + F 3 + Zicfilp 3 + Zicfiss 3 + Zicbom 2 + +6. PARAMETER LISTING BY CLASSIFICATION +---------------------------------------- + + --- NORM_DIRECT (102 parameters) --- + ARCH_ID_VALUE + Type: conditional | Exts: ext:Sm AND param:MARCHID_IMPLEMENTED(equal=True) CSRs: marchid + Spec: -> machine.adoc:297 + Conf: high | Well-known architectural parameter 'ARCH_ID_VALUE' + ASID_WIDTH + Type: conditional | Exts: ext:S + Spec: -> supervisor.adoc:1373 [NORM] + Conf: high | Well-known architectural parameter 'ASID_WIDTH' + CACHE_BLOCK_SIZE + Type: range | Exts: (ext:Zicbom OR ext:Zicbop OR ext:Zicboz) + Spec: -> cmo.adoc:973 [NORM] + Conf: high | Well-known architectural parameter 'CACHE_BLOCK_SIZE' + CONFIG_PTR_ADDRESS + Type: conditional | Exts: ext:Sm(>= 1.12.0) CSRs: mconfigptr + Spec: -> machine.adoc:2136 + Conf: high | Well-known architectural parameter 'CONFIG_PTR_ADDRESS' + ELEN + Type: value | Exts: ext:V + Spec: -> v-st-ext.adoc:24 [NORM] + Conf: high | Well-known architectural parameter 'ELEN' + FOLLOW_VTYPE_RESET_RECOMMENDATION + Type: binary([True, False]) | Exts: ext:V CSRs: vl, vtype + Spec: -> v-st-ext.adoc:169 [NORM] + Conf: medium | Implementation behavioral choice parameter + HCONTEXT_AVAILABLE + Type: binary([True, False]) | Exts: ext:Sdtrig CSRs: hcontext + Spec: -> smstateen.adoc:287 + Conf: high | Feature/CSR existence parameter ('AVAILABLE' suffix) + IMP_ID_VALUE + Type: conditional | Exts: ext:Sm AND param:MIMPID_IMPLEMENTED(equal=True) CSRs: mimpid + Spec: -> machine.adoc:335 + Conf: high | Well-known architectural parameter 'IMP_ID_VALUE' + LRSC_FAIL_ON_NON_EXACT_LRSC + Type: binary([True, False]) | Exts: ext:Zalrsc + Spec: -> a-st-ext.adoc:169 + Conf: medium | Load-reserved/store-conditional behavior parameter + LRSC_FAIL_ON_VA_SYNONYM + Type: binary([True, False]) | Exts: ext:Zalrsc + Spec: -> a-st-ext.adoc:76 + Conf: medium | Load-reserved/store-conditional behavior parameter + LRSC_MISALIGNED_BEHAVIOR + Type: enum(3 vals) | Exts: ext:Zalrsc + Spec: -> a-st-ext.adoc:59 + Conf: medium | Load-reserved/store-conditional behavior parameter + LRSC_RESERVATION_STRATEGY + Type: enum(4 vals) | Exts: ext:Zalrsc + Spec: -> a-st-ext.adoc:76 + Conf: medium | Load-reserved/store-conditional behavior parameter + MARCHID_IMPLEMENTED + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:303 + Conf: high | Feature/CSR existence parameter ('IMPLEMENTED' suffix) + MCONTEXT_AVAILABLE + Type: binary([True, False]) | Exts: ext:Sdtrig CSRs: mcontext + Spec: -> priv-csrs.adoc:1019 + Conf: high | Feature/CSR existence parameter ('AVAILABLE' suffix) + MIMPID_IMPLEMENTED + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:337 [NORM] + Conf: high | Feature/CSR existence parameter ('IMPLEMENTED' suffix) + MISALIGNED_AMO + Type: binary([True, False]) | Exts: ext:Zaamo + Spec: -> machine.adoc:1976 [NORM] + Conf: medium | Misaligned access behavior parameter + MISALIGNED_LDST + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:1976 [NORM] + Conf: medium | Misaligned access behavior parameter + MISALIGNED_LDST_EXCEPTION_PRIORITY + Type: binary(['low', 'high']) | Exts: ext:Sm + Spec: -> rv32.adoc:139 [NORM] + Conf: medium | Misaligned access behavior parameter + MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE + Type: enum(13 vals) | Exts: ext:Sm AND param:MISALIGNED_LDST(equal=True) + Spec: -> a-st-ext.adoc:385 + Conf: medium | Misaligned access behavior parameter + MISALIGNED_SPLIT_STRATEGY + Type: binary(['sequential_bytes', 'custom']) | Exts: ext:Sm AND param:MISALIGNED_LDST(equal=True) + Spec: -> machine.adoc:1976 [NORM] + Conf: medium | Misaligned access behavior parameter + MISA_CSR_IMPLEMENTED + Type: binary([True, False]) | Exts: ext:Sm CSRs: mstatus + Spec: -> machine.adoc:23 [NORM] + Conf: high | Feature/CSR existence parameter ('IMPLEMENTED' suffix) + MSTATUS_TVM_IMPLEMENTED + Type: binary([True, False]) | Exts: ext:S CSRs: mstatus + Spec: -> hypervisor.adoc:999 [NORM] + Conf: high | Feature/CSR existence parameter ('IMPLEMENTED' suffix) + MTVAL_WIDTH + Type: conditional | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: medium | Trap value reporting parameter + MXLEN + Type: binary([32, 64]) | Exts: ext:Sm CSRs: hcontext, mconfigptr, misa + Spec: -> machine.adoc:50 [NORM] + Conf: high | Well-known architectural parameter 'MXLEN' + NUM_EXTERNAL_GUEST_INTERRUPTS + Type: conditional | Exts: ext:H CSRs: hstatus + Spec: -> hypervisor.adoc:259 + Conf: high | Well-known architectural parameter 'NUM_EXTERNAL_GUEST_INTERRUPTS' + NUM_PMP_ENTRIES + Type: range | Exts: ext:Smpmp CSRs: pmpaddr0, pmpaddr1, pmpaddr10 + Spec: -> machine.adoc:668 [NORM] + Conf: high | Well-known architectural parameter 'NUM_PMP_ENTRIES' + PHYS_ADDR_WIDTH + Type: conditional | Exts: ext:Sm CSRs: pmpaddr0, pmpaddr1, pmpaddr10 + Spec: -> hypervisor.adoc:1027 + Conf: high | Well-known architectural parameter 'PHYS_ADDR_WIDTH' + PMA_GRANULARITY + Type: range | Exts: ext:Sm + Spec: -> cmo.adoc:754 + Conf: high | Well-known architectural parameter 'PMA_GRANULARITY' + PMLEN + Type: value | Exts: (ext:Smmpm OR ext:Smnpm OR ext:Ssnpm) + Spec: -> hypervisor.adoc:807 + Conf: high | Well-known architectural parameter 'PMLEN' + PMP_GRANULARITY + Type: range | Exts: ext:Smpmp CSRs: pmpaddr0, pmpaddr1, pmpaddr10 + Spec: -> cmo.adoc:754 + Conf: high | Well-known architectural parameter 'PMP_GRANULARITY' + PRECISE_SYNCHRONOUS_EXCEPTIONS + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:1256 [NORM] + Conf: high | Trap/report behavior parameter (matches ^PRECISE_) + REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK + Type: binary([True, False]) | Exts: ext:Zicfilp + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK + Type: binary([True, False]) | Exts: ext:Zicfiss + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK + Type: binary([True, False]) | Exts: ext:Zicfilp + Spec: -> supervisor.adoc:707 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK + Type: binary([True, False]) | Exts: ext:Zicfiss + Spec: -> supervisor.adoc:707 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK + Type: binary([True, False]) | Exts: ext:Zicfilp + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK + Type: binary([True, False]) | Exts: ext:Zicfiss + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:2082 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:751 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:917 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H CSRs: htval, mtval2 + Spec: -> hypervisor.adoc:2832 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H CSRs: htval, mtval2 + Spec: -> hypervisor.adoc:2832 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H CSRs: htval, mtval2 + Spec: -> hypervisor.adoc:2832 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H CSRs: htval, mtval2 + Spec: -> hypervisor.adoc:2832 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_BREAKPOINT + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:2049 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> machine.adoc:2067 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_BREAKPOINT + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:726 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:936 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:726 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:936 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:707 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:734 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:2046 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:707 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED + Type: binary([True, False]) | Exts: ext:S + Spec: -> supervisor.adoc:734 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:S + Spec: -> hypervisor.adoc:2046 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_BREAKPOINT + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> zc.adoc:1183 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED + Type: binary([True, False]) | Exts: ext:H + Spec: -> c-st-ext.adoc:310 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> zc.adoc:1183 [NORM] + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1371 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1371 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT + Type: binary([True, False]) | Exts: ext:H + Spec: -> hypervisor.adoc:1364 + Conf: high | Trap/report behavior parameter (matches ^REPORT_) + RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX + Type: enum(3 vals) | Exts: ext:V + Spec: -> v-st-ext.adoc:1279 [NORM] + Conf: low | No strong signals; defaulting to direct normative parameter + STVAL_WIDTH + Type: range | Exts: ext:S + Spec: -> supervisor.adoc:707 [NORM] + Conf: medium | Trap value reporting parameter + SV32_VSMODE_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:VSXLEN(includes=32) + Spec: -> cmo.adoc:365 [NORM] + Conf: medium | Translation/mode parameter + SV39_VSMODE_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:VSXLEN(includes=64) + Spec: -> cmo.adoc:365 [NORM] + Conf: medium | Translation/mode parameter + SV48_VSMODE_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:VSXLEN(includes=64) + Spec: -> cmo.adoc:365 [NORM] + Conf: medium | Translation/mode parameter + SV57_VSMODE_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:VSXLEN(includes=64) + Spec: -> cmo.adoc:365 [NORM] + Conf: medium | Translation/mode parameter + SXLEN + Type: set | Exts: ext:S CSRs: hstatus, mstatus + Spec: -> machine.adoc:575 + Conf: high | Well-known architectural parameter 'SXLEN' + TIME_CSR_IMPLEMENTED + Type: binary([True, False]) | Exts: ext:Zicntr CSRs: time, timeh + Spec: -> machine.adoc:2621 + Conf: high | Feature/CSR existence parameter ('IMPLEMENTED' suffix) + TRAP_ON_EBREAK + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> rv32.adoc:684 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_ECALL_FROM_M + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> rv32.adoc:684 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_ECALL_FROM_S + Type: binary([True, False]) | Exts: ext:S + Spec: -> rv32.adoc:925 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_ECALL_FROM_U + Type: binary([True, False]) | Exts: ext:U + Spec: -> rv32.adoc:925 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_ECALL_FROM_VS + Type: binary([True, False]) | Exts: ext:H + Spec: -> machine.adoc:932 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_ILLEGAL_WLRL + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> hypervisor.adoc:25 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_RESERVED_INSTRUCTION + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> c-st-ext.adoc:756 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY + Type: binary([True, False]) | Exts: ext:S AND NONE(ext:Sv32, ext:Sv39, ext:Sv48, ext:Sv57) + Spec: -> hypervisor.adoc:250 + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_UNIMPLEMENTED_CSR + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> v-st-ext.adoc:5140 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + TRAP_ON_UNIMPLEMENTED_INSTRUCTION + Type: binary([True, False]) | Exts: ext:Sm + Spec: -> c-st-ext.adoc:310 [NORM] + Conf: high | Trap/report behavior parameter (matches ^TRAP_ON_) + UXLEN + Type: set | Exts: ext:U CSRs: mstatus + Spec: -> machine.adoc:575 + Conf: high | Well-known architectural parameter 'UXLEN' + VENDOR_ID_BANK + Type: range | Exts: ext:Sm CSRs: mvendorid + Spec: -> machine.adoc:263 [NORM] + Conf: high | Well-known architectural parameter 'VENDOR_ID_BANK' + VENDOR_ID_OFFSET + Type: range | Exts: ext:Sm CSRs: mvendorid + Spec: -> machine.adoc:263 [NORM] + Conf: high | Well-known architectural parameter 'VENDOR_ID_OFFSET' + VLEN + Type: value | Exts: ext:V CSRs: vlenb, vstart + Spec: -> v-st-ext.adoc:511 + Conf: high | Well-known architectural parameter 'VLEN' + VMID_WIDTH + Type: conditional | Exts: ext:H CSRs: hgatp + Spec: -> hypervisor.adoc:1089 + Conf: high | Well-known architectural parameter 'VMID_WIDTH' + VSSTAGE_MODE_BARE + Type: binary([True, False]) | Exts: ext:H + Spec: -> priv-cfi.adoc:216 [NORM] + Conf: medium | Translation/mode parameter + VSXLEN + Type: set | Exts: ext:H CSRs: hstatus + Spec: -> hypervisor.adoc:1184 + Conf: high | Well-known architectural parameter 'VSXLEN' + VUXLEN + Type: set | Exts: ext:H CSRs: vsstatus + Spec: -> hypervisor.adoc:1181 + Conf: high | Well-known architectural parameter 'VUXLEN' + + --- NORM_CSR_WARL (26 parameters) --- + DBG_HCONTEXT_WIDTH + Type: range | Exts: ext:Sdtrig CSRs: hcontext, mcontext + Spec: -> smstateen.adoc:287 + Conf: high | Referenced in sw_write() of hcontext.HCONTEXT + DBG_SCONTEXT_WIDTH + Type: range | Exts: ext:Sdtrig CSRs: scontext + Spec: -> hypervisor.adoc:146 + Conf: high | Referenced in sw_write() of scontext.DATA + FORCE_UPGRADE_CBO_INVAL_TO_FLUSH + Type: binary([True, False]) | Exts: ext:Zicbom CSRs: menvcfg + Spec: -> supervisor.adoc:913 + Conf: high | Referenced in sw_write() of menvcfg.CBIE + GSTAGE_MODE_BARE + Type: binary([True, False]) | Exts: ext:H CSRs: hgatp + Spec: -> hypervisor.adoc:1075 + Conf: high | Referenced in sw_write() of hgatp.MODE + HPM_EVENTS + Type: set | Exts: ext:Smhpm CSRs: mhpmevent10, mhpmevent11, mhpmevent12 + Spec: -> machine.adoc:1581 + Conf: high | Referenced in sw_write() of mhpmevent14.EVENT + IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO + Type: binary([True, False]) | Exts: ext:H CSRs: vsatp + Spec: -> hypervisor.adoc:1416 + Conf: high | Referenced in sw_write() of vsatp.MODE + JVT_BASE_MASK + Type: range | Exts: ext:Zcmt AND param:JVT_BASE_TYPE(equal=mask) CSRs: jvt + Spec: -> c-st-ext.adoc:466 [NORM] + Conf: high | Referenced in sw_write() of jvt.BASE + JVT_BASE_TYPE + Type: binary(['mask', 'custom']) | Exts: ext:Zcmt CSRs: jvt + Spec: -> c-st-ext.adoc:466 [NORM] + Conf: high | Referenced in sw_write() of jvt.BASE + JVT_READ_ONLY + Type: binary([True, False]) | Exts: ext:Zcmt CSRs: jvt + Spec: -> zc.adoc:2341 [NORM] + Conf: high | Referenced in sw_write() of jvt.MODE + MCID_WIDTH + Type: range | Exts: ext:Ssqosid CSRs: srmcfg + Spec: -> supervisor.adoc:2586 + Conf: high | Referenced in sw_write() of srmcfg.MCID + MSTATUS_FS_LEGAL_VALUES + Type: set | Exts: (ext:F OR ext:S) CSRs: mstatus + Spec: -> machine.adoc:679 [NORM] + Conf: high | Referenced in sw_write() of mstatus.FS + MSTATUS_VS_LEGAL_VALUES + Type: set | Exts: (ext:V OR ext:S) CSRs: mstatus + Spec: -> machine.adoc:679 [NORM] + Conf: high | Referenced in sw_write() of mstatus.VS + MTVEC_BASE_ALIGNMENT_DIRECT + Type: conditional | Exts: ext:Sm AND {'param': {'allOf': [{'name': 'MTVEC_MODES', 'includes': 0, 'reason': 'Only rele + Spec: -> machine.adoc:1209 [NORM] + Conf: low | Name pattern suggests CSR 'mtvec' association, but no IDL cross-reference found + MTVEC_BASE_ALIGNMENT_VECTORED + Type: conditional | Exts: ext:Sm AND {'param': {'allOf': [{'name': 'MTVEC_MODES', 'includes': 1, 'reason': 'Only rele + Spec: -> priv-preface.adoc:540 + Conf: low | Name pattern suggests CSR 'mtvec' association, but no IDL cross-reference found + MTVEC_ILLEGAL_WRITE_BEHAVIOR + Type: binary(['retain', 'custom']) | Exts: ext:Sm CSRs: mtvec + Spec: -> machine.adoc:1209 [NORM] + Conf: high | Referenced in sw_write() of mtvec.BASE + MTVEC_MODES + Type: set | Exts: ext:Sm CSRs: mtvec + Spec: -> machine.adoc:1255 + Conf: high | Referenced in sw_write() of mtvec.BASE + RCID_WIDTH + Type: range | Exts: ext:Ssqosid CSRs: srmcfg + Spec: -> supervisor.adoc:2586 + Conf: high | Referenced in sw_write() of srmcfg.RCID + SATP_MODE_BARE + Type: binary([True, False]) | Exts: ext:S CSRs: satp + Spec: -> machine.adoc:670 [NORM] + Conf: high | Referenced in sw_write() of satp.MODE + STVEC_MODE_DIRECT + Type: binary([True, False]) | Exts: ext:S CSRs: stvec + Spec: -> hypervisor.adoc:1304 + Conf: high | Referenced in sw_write() of stvec.MODE + STVEC_MODE_VECTORED + Type: binary([True, False]) | Exts: ext:S CSRs: stvec + Spec: -> machine.adoc:1256 [NORM] + Conf: high | Referenced in sw_write() of stvec.MODE + SV32X4_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:SXLEN(includes=32) CSRs: hgatp + Spec: -> hypervisor.adoc:1915 + Conf: high | Referenced in sw_write() of hgatp.MODE + SV39X4_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:SXLEN(includes=64) CSRs: hgatp + Spec: -> hypervisor.adoc:1007 + Conf: high | Referenced in sw_write() of hgatp.MODE + SV48X4_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:SXLEN(includes=64) CSRs: hgatp + Spec: -> hypervisor.adoc:1007 + Conf: high | Referenced in sw_write() of hgatp.MODE + SV57X4_TRANSLATION + Type: binary([True, False]) | Exts: ext:H AND param:SXLEN(includes=64) CSRs: hgatp + Spec: -> hypervisor.adoc:1007 + Conf: high | Referenced in sw_write() of hgatp.MODE + VSTVEC_MODE_DIRECT + Type: binary([True, False]) | Exts: ext:H CSRs: vstvec + Spec: -> machine.adoc:423 [NORM] + Conf: high | Referenced in sw_write() of vstvec.MODE + VSTVEC_MODE_VECTORED + Type: binary([True, False]) | Exts: ext:H CSRs: vstvec + Spec: -> machine.adoc:1256 [NORM] + Conf: high | Referenced in sw_write() of vstvec.MODE + + --- NORM_CSR_RW (55 parameters) --- + COUNTINHIBIT_EN + Type: bitmask | Exts: ext:Sm CSRs: mcountinhibit + Spec: -> machine.adoc:1669 [NORM] + Conf: high | Controls type (RO/RW) of mcountinhibit.CY + DCSR_MPRVEN_TYPE + Type: enum(3 vals) | Exts: ext:Sdtrig CSRs: dcsr + Spec: -> priv-cfi.adoc:87 + Conf: high | Controls type (RO/RW) of dcsr.MPRVEN + DCSR_STEPIE_TYPE + Type: enum(3 vals) | Exts: ext:Sdtrig CSRs: dcsr + Spec: -> priv-cfi.adoc:87 + Conf: high | Controls type (RO/RW) of dcsr.STEPIE + DCSR_STOPCOUNT_TYPE + Type: enum(3 vals) | Exts: ext:Sdtrig CSRs: dcsr + Spec: -> priv-cfi.adoc:87 + Conf: high | Controls type (RO/RW) of dcsr.STOPCOUNT + DCSR_STOPTIME_TYPE + Type: enum(3 vals) | Exts: ext:Sdtrig CSRs: dcsr + Spec: -> priv-cfi.adoc:87 + Conf: high | Controls type (RO/RW) of dcsr.STOPTIME + HCOUNTENABLE_EN + Type: bitmask | Exts: ext:H CSRs: hcounteren + Spec: -> hypervisor.adoc:857 + Conf: high | Controls type (RO/RW) of hcounteren.CY + HPM_COUNTER_EN + Type: bitmask | Exts: ext:Smhpm CSRs: mhpmcounter10, mhpmcounter10h, mhpmcounter11 + Spec: -> machine.adoc:1615 [NORM] + Conf: high | Controls type (RO/RW) of scountovf.OF3 + HSTATEEN_AIA_TYPE + Type: enum(3 vals) | Exts: ext:Ssaia AND ext:H AND ext:Ssstateen + Conf: low | CSR field type control parameter for 'hstateen' (determines RO/RW behavior) + HSTATEEN_CONTEXT_TYPE + Type: enum(3 vals) | Exts: ext:Sdtrig AND ext:H AND ext:Ssstateen + Spec: -> smctr.adoc:652 [NORM] + Conf: low | CSR field type control parameter for 'hstateen' (determines RO/RW behavior) + HSTATEEN_CSRIND_TYPE + Type: enum(3 vals) | Exts: ext:Sscsrind AND ext:H AND ext:Ssstateen + Spec: -> smstateen.adoc:191 + Conf: low | CSR field type control parameter for 'hstateen' (determines RO/RW behavior) + HSTATEEN_ENVCFG_TYPE + Type: enum(3 vals) | Exts: ext:H(~> 1.0) AND ext:Ssstateen(~> 1.0) + Spec: -> priv-cfi.adoc:134 + Conf: low | CSR field type control parameter for 'hstateen' (determines RO/RW behavior) + HSTATEEN_IMSIC_TYPE + Type: enum(3 vals) | Exts: ext:Ssaia AND ext:H AND ext:Ssstateen + Spec: -> smstateen.adoc:189 + Conf: low | CSR field type control parameter for 'hstateen' (determines RO/RW behavior) + HSTATEEN_JVT_TYPE + Type: enum(3 vals) | Exts: ext:Zcmt AND ext:H AND ext:Ssstateen + Spec: -> zc.adoc:2341 [NORM] + Conf: low | CSR field type control parameter for 'hstateen' (determines RO/RW behavior) + MCOUNTENABLE_EN + Type: bitmask | Exts: ext:U CSRs: mcounteren + Spec: -> machine.adoc:1656 [NORM] + Conf: high | Controls type (RO/RW) of mcounteren.CY + MSTATEEN_AIA_TYPE + Type: enum(3 vals) | Exts: ext:Ssaia AND ext:Smstateen(~> 1.0) + Conf: low | CSR field type control parameter for 'mstateen' (determines RO/RW behavior) + MSTATEEN_CONTEXT_TYPE + Type: enum(3 vals) | Exts: ext:Sdtrig AND ext:Smstateen + Spec: -> smctr.adoc:652 [NORM] + Conf: low | CSR field type control parameter for 'mstateen' (determines RO/RW behavior) + MSTATEEN_CSRIND_TYPE + Type: enum(3 vals) | Exts: ext:Sscsrind AND ext:Smstateen + Spec: -> smstateen.adoc:191 + Conf: low | CSR field type control parameter for 'mstateen' (determines RO/RW behavior) + MSTATEEN_ENVCFG_TYPE + Type: enum(3 vals) | Exts: ext:S AND ext:Smstateen + Spec: -> priv-cfi.adoc:134 + Conf: low | CSR field type control parameter for 'mstateen' (determines RO/RW behavior) + MSTATEEN_IMSIC_TYPE + Type: enum(3 vals) | Exts: ext:Ssaia AND ext:Smstateen(~> 1.0) + Spec: -> smstateen.adoc:189 + Conf: low | CSR field type control parameter for 'mstateen' (determines RO/RW behavior) + MSTATEEN_JVT_TYPE + Type: enum(3 vals) | Exts: ext:Zcmt AND ext:Smstateen(~> 1.0) + Spec: -> zc.adoc:2341 [NORM] + Conf: low | CSR field type control parameter for 'mstateen' (determines RO/RW behavior) + MTVEC_ACCESS + Type: binary(['ro', 'rw']) | Exts: ext:Sm CSRs: mtvec + Spec: -> machine.adoc:1209 [NORM] + Conf: high | Controls type (RO/RW) of mtvec.BASE + MUTABLE_MISA_A + Type: binary([True, False]) | Exts: ext:A CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.A + MUTABLE_MISA_B + Type: binary([True, False]) | Exts: ext:B CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.B + MUTABLE_MISA_C + Type: binary([True, False]) | Exts: ext:C CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.C + MUTABLE_MISA_D + Type: binary([True, False]) | Exts: ext:D CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.D + MUTABLE_MISA_F + Type: binary([True, False]) | Exts: ext:F CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.F + MUTABLE_MISA_H + Type: binary([True, False]) | Exts: ext:H CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.H + MUTABLE_MISA_M + Type: binary([True, False]) | Exts: ext:M CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.G + MUTABLE_MISA_Q + Type: binary([True, False]) | Exts: ext:Q CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.Q + MUTABLE_MISA_S + Type: binary([True, False]) | Exts: ext:S CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.S + MUTABLE_MISA_U + Type: binary([True, False]) | Exts: ext:U CSRs: misa + Spec: -> machine.adoc:21 [NORM] + Conf: high | Controls type (RO/RW) of misa.U + MUTABLE_MISA_V + Type: binary([True, False]) | Exts: ext:V CSRs: misa + Spec: -> v-st-ext.adoc:5161 [NORM] + Conf: high | Controls type (RO/RW) of misa.V + M_MODE_ENDIANNESS + Type: enum(3 vals) | Exts: ext:Sm CSRs: mstatus, mstatush + Spec: -> machine.adoc:679 [NORM] + Conf: high | Controls type (RO/RW) of mstatus.MBE + SCOUNTENABLE_EN + Type: bitmask | Exts: ext:S AND (ext:Zicntr OR ext:Zihpm) CSRs: scounteren + Spec: -> supervisor.adoc:511 + Conf: high | Controls type (RO/RW) of scounteren.CY + SSTATEEN_JVT_TYPE + Type: enum(3 vals) | Exts: ext:Zcmt AND ext:Ssstateen + Spec: -> zc.adoc:2341 [NORM] + Conf: low | CSR field type control parameter for 'sstateen' (determines RO/RW behavior) + S_MODE_ENDIANNESS + Type: enum(3 vals) | Exts: ext:S CSRs: mstatus, mstatush + Spec: -> machine.adoc:679 [NORM] + Conf: high | Controls type (RO/RW) of mstatus.SBE + TINST_VALUE_ON_BREAKPOINT + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT + Type: binary(['always zero', 'always pseudoinstruction']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:2567 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT + Type: enum(4 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT + Type: enum(4 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:2567 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_LOAD_ACCESS_FAULT + Type: enum(3 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED + Type: enum(3 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_LOAD_PAGE_FAULT + Type: enum(3 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_MCALL + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_SCALL + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT + Type: enum(3 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED + Type: enum(3 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_STORE_AMO_PAGE_FAULT + Type: enum(3 vals) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_UCALL + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_VIRTUAL_INSTRUCTION + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> smctr.adoc:218 [NORM] + Conf: high | Controls type (RO/RW) of htinst.VALUE + TINST_VALUE_ON_VSCALL + Type: binary(['always zero', 'custom']) | Exts: ext:H CSRs: htinst, mtinst + Spec: -> hypervisor.adoc:983 + Conf: high | Controls type (RO/RW) of htinst.VALUE + U_MODE_ENDIANNESS + Type: enum(3 vals) | Exts: ext:U CSRs: mstatus + Spec: -> machine.adoc:679 [NORM] + Conf: high | Controls type (RO/RW) of mstatus.UBE + VS_MODE_ENDIANNESS + Type: enum(3 vals) | Exts: ext:H CSRs: hstatus + Spec: -> hypervisor.adoc:339 + Conf: high | Controls type (RO/RW) of hstatus.VSBE + VU_MODE_ENDIANNESS + Type: enum(3 vals) | Exts: ext:H CSRs: vsstatus + Spec: -> hypervisor.adoc:2359 [NORM] + Conf: high | Controls type (RO/RW) of vsstatus.UBE + + --- SW_RULE (2 parameters) --- + HW_MSTATUS_FS_DIRTY_UPDATE + Type: enum(3 vals) | Exts: ext:F CSRs: mstatus + Spec: -> v-st-ext.adoc:3313 [NORM] + Conf: medium | Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing + HW_MSTATUS_VS_DIRTY_UPDATE + Type: enum(3 vals) | Exts: ext:V CSRs: mstatus + Spec: -> v-st-ext.adoc:107 + Conf: medium | Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing + +======================================================================== +END OF REPORT +======================================================================== diff --git a/param_extraction/data/spec_mappings.json b/param_extraction/data/spec_mappings.json new file mode 100644 index 0000000000..acd6d66347 --- /dev/null +++ b/param_extraction/data/spec_mappings.json @@ -0,0 +1,13093 @@ +{ + "metadata": { + "total_parameters": 185, + "params_with_matches": 183, + "params_with_strong_matches": 161, + "spec_files_searched": 74, + "total_spec_lines": 52602 + }, + "mappings": [ + { + "parameter_name": "ARCH_ID_VALUE", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 7, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Description keyword 'marchid'", + "CSR field name 'Architecture'", + "CSR name 'marchid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 297, + "line_text": "==== Machine Architecture ID (`marchid`) Register", + "context": " 295| ====\n 296| \n>>> 297| ==== Machine Architecture ID (`marchid`) Register\n 298| \n 299| [#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'marchid'", + "CSR name 'marchid' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 299, + "line_text": "[#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base", + "context": " 297| ==== Machine Architecture ID (`marchid`) Register\n 298| \n>>> 299| [#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base\n 300| microarchitecture of the hart.#\n 301| [#norm:marchid_always_rd]#This register must be readable in any" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'marchid'", + "CSR field name 'Architecture'", + "CSR name 'marchid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 305, + "line_text": ".Machine Architecture ID (`marchid`) register", + "context": " 303| The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.\n 304| \n>>> 305| .Machine Architecture ID (`marchid`) register\n 306| include::images/bytefield/marchid.edn[]\n 307| " + }, + { + "score": 6, + "reasons": [ + "Description keyword 'marchid'", + "CSR name 'marchid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 303, + "line_text": "The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.", + "context": " 301| [#norm:marchid_always_rd]#This register must be readable in any\n 302| implementation, but a value of 0 can be returned to indicate the field is not implemented.#\n>>> 303| The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.\n 304| \n 305| .Machine Architecture ID (`marchid`) register" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'marchid'", + "CSR name 'marchid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 650, + "line_text": "`marchid` +", + "context": " 648| MRO\n 649| |`mvendorid` +\n>>> 650| `marchid` +\n 651| `mimpid` +\n 652| `mhartid` +" + } + ] + }, + { + "parameter_name": "ASID_WIDTH", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": ["Description keyword 'ASID'", "Name segment 'ASID'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 1373, + "line_text": "[#norm:sfence-vma-asid_effect]#Likewise, changes to `satp`.ASID take effect immediately.#", + "context": " 1371| `satp`.MODE from Bare to other modes and vice versa also takes effect\n 1372| immediately, without the need to execute an SFENCE.VMA instruction.#\n>>> 1373| [#norm:sfence-vma-asid_effect]#Likewise, changes to `satp`.ASID take effect immediately.#\n 1374| \n 1375| [NOTE]" + }, + { + "score": 3, + "reasons": ["Description keyword 'ASID'", "Name segment 'ASID'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1559, + "line_text": "at the time HFENCE.VVMA executed. If operand __rs1__≠`x0`, it specifies a single guest virtual address, and if operand __rs2__≠`x0`, it specifies a single guest address-space identifier (ASID).", + "context": " 1557| [[norm:hfence-vvma_limits]]\n 1558| Implicit reads need not be ordered when `hgatp`.VMID is different than\n>>> 1559| at the time HFENCE.VVMA executed. If operand __rs1__≠`x0`, it specifies a single guest virtual address, and if operand __rs2__≠`x0`, it specifies a single guest address-space identifier (ASID).\n 1560| \n 1561| [NOTE]" + }, + { + "score": 3, + "reasons": ["Description keyword 'ASID'", "Name segment 'ASID'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2075, + "line_text": "HS-level virtual address, and the ASID argument is an HS-level ASID. The", + "context": " 2073| The behavior of the SFENCE.VMA instruction is affected by the current\n 2074| virtualization mode V. When V=0, the virtual-address argument is an\n>>> 2075| HS-level virtual address, and the ASID argument is an HS-level ASID. The\n 2076| instruction orders stores only to HS-level address-translation\n 2077| structures with subsequent HS-level address translations." + }, + { + "score": 3, + "reasons": ["Description keyword 'ASID'", "Name segment 'ASID'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2081, + "line_text": "address within the current virtual machine, and the ASID argument is a", + "context": " 2079| [[norm:sfence-vma_v1]]\n 2080| When V=1, the virtual-address argument to SFENCE.VMA is a guest virtual\n>>> 2081| address within the current virtual machine, and the ASID argument is a\n 2082| VS-level ASID within the current virtual machine. The current virtual\n 2083| machine is identified by the VMID field of CSR `hgatp`, and the" + }, + { + "score": 3, + "reasons": ["Description keyword 'ASID'", "Name segment 'ASID'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2082, + "line_text": "VS-level ASID within the current virtual machine. The current virtual", + "context": " 2080| When V=1, the virtual-address argument to SFENCE.VMA is a guest virtual\n 2081| address within the current virtual machine, and the ASID argument is a\n>>> 2082| VS-level ASID within the current virtual machine. The current virtual\n 2083| machine is identified by the VMID field of CSR `hgatp`, and the\n 2084| effective ASID can be considered to be the combination of this VMID with" + } + ] + }, + { + "parameter_name": "CACHE_BLOCK_SIZE", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'BLOCK'", + "Name segment 'SIZE'", + "Name segment 'CACHE'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 973, + "line_text": "[#norm:cbo-zero_unaligned]#It is not required that _rs1_ is aligned to the size of a cache block.# On", + "context": " 971| [#norm:cbo-zero_op]#A *cbo.zero* instruction performs stores of zeros to the full set of bytes\n 972| corresponding to the cache block that contains the address specified in _rs1_.#\n>>> 973| [#norm:cbo-zero_unaligned]#It is not required that _rs1_ is aligned to the size of a cache block.# On\n 974| faults, the faulting virtual address is considered to be the value in rs1,\n 975| rather than the base address of the cache block. An implementation may or" + }, + { + "score": 4, + "reasons": ["Name segment 'BLOCK'", "Name segment 'CACHE'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 327, + "line_text": "* [#norm:PMA_same]#The PMAs shall be the same for _all_ physical addresses in the cache block,", + "context": " 325| bits, read permission shall also be granted#\n 326| \n>>> 327| * [#norm:PMA_same]#The PMAs shall be the same for _all_ physical addresses in the cache block,\n 328| and if write permission is granted by the supported access type PMAs, read\n 329| permission shall also be granted#" + }, + { + "score": 4, + "reasons": ["Name segment 'BLOCK'", "Name segment 'CACHE'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 356, + "line_text": "[#norm:cbm_access]#A cache-block management instruction is permitted to access the specified cache", + "context": " 354| whether accesses by cache-block zero instructions are supported.\n 355| \n>>> 356| [#norm:cbm_access]#A cache-block management instruction is permitted to access the specified cache\n 357| block whenever a load instruction or store instruction is permitted to access\n 358| the corresponding physical addresses.# If neither a load instruction nor store" + }, + { + "score": 4, + "reasons": ["Name segment 'BLOCK'", "Name segment 'CACHE'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 361, + "line_text": "management instruction is permitted to access the cache block is UNSPECIFIED. [#norm:cbm_unperm_fault]#If", + "context": " 359| instruction is permitted to access the physical addresses, but an instruction\n 360| fetch is permitted to access the physical addresses, whether a cache-block\n>>> 361| management instruction is permitted to access the cache block is UNSPECIFIED. [#norm:cbm_unperm_fault]#If\n 362| access to the cache block is not permitted, a cache-block management instruction\n 363| raises a store page-fault or store guest-page-fault exception if address" + }, + { + "score": 4, + "reasons": ["Name segment 'BLOCK'", "Name segment 'CACHE'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 377, + "line_text": "[#norm:cbz_access]#A cache-block zero instruction is permitted to access the specified cache block", + "context": " 375| ====\n 376| \n>>> 377| [#norm:cbz_access]#A cache-block zero instruction is permitted to access the specified cache block\n 378| whenever a store instruction is permitted to access the corresponding physical\n 379| addresses and when the PMAs indicate that cache-block zero instructions are a" + } + ] + }, + { + "parameter_name": "CONFIG_PTR_ADDRESS", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": [ + "CSR name 'mconfigptr' in backticks", + "Description keyword 'mconfigptr'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2136, + "line_text": "==== Machine Configuration Pointer (`mconfigptr`) Register", + "context": " 2134| _N_ is the smaller of MXLEN and ILEN.\n 2135| \n>>> 2136| ==== Machine Configuration Pointer (`mconfigptr`) Register\n 2137| \n 2138| The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mconfigptr' in backticks", + "Description keyword 'mconfigptr'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2138, + "line_text": "The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in", + "context": " 2136| ==== Machine Configuration Pointer (`mconfigptr`) Register\n 2137| \n>>> 2138| The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in\n 2139| <>, that holds the physical\n 2140| address of a configuration data structure. Software can traverse this" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mconfigptr' in backticks", + "Description keyword 'mconfigptr'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2145, + "line_text": ".Machine Configuration Pointer (`mconfigptr`) register.", + "context": " 2143| \n 2144| [[mconfigptrreg]]\n>>> 2145| .Machine Configuration Pointer (`mconfigptr`) register.\n 2146| include::images/bytefield/mconfigptrreg.edn[]\n 2147| " + }, + { + "score": 6, + "reasons": [ + "CSR name 'mconfigptr' in backticks", + "Description keyword 'mconfigptr'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2151, + "line_text": "8{times}__n__, then `mconfigptr`[log~2n~-1:0]", + "context": " 2149| The pointer alignment in bits must be no smaller than MXLEN:\n 2150| i.e., if MXLEN is\n>>> 2151| 8{times}__n__, then `mconfigptr`[log~2n~-1:0]\n 2152| must be zero.\n 2153| " + }, + { + "score": 6, + "reasons": [ + "CSR name 'mconfigptr' in backticks", + "Description keyword 'mconfigptr'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2154, + "line_text": "The `mconfigptr` register must be implemented, but it may be zero to indicate the", + "context": " 2152| must be zero.\n 2153| \n>>> 2154| The `mconfigptr` register must be implemented, but it may be zero to indicate the\n 2155| configuration data structure does not exist or that an alternative\n 2156| mechanism must be used to locate it." + } + ] + }, + { + "parameter_name": "COUNTINHIBIT_EN", + "classification": "NORM_CSR_RW", + "value_type": "bitmask", + "num_candidates": 10, + "best_score": 13, + "candidates": [ + { + "score": 13, + "reasons": [ + "CSR name 'mcountinhibit' in backticks", + "Description keyword 'mcountinhibit'", + "WARL + CSR 'mcountinhibit'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1669, + "line_text": "[#norm:mcountinhibit_sz_warl_op1]#The counter-inhibit register `mcountinhibit` is a 32-bit", + "context": " 1667| include::images/bytefield/counterinh.edn[]\n 1668| \n>>> 1669| [#norm:mcountinhibit_sz_warl_op1]#The counter-inhibit register `mcountinhibit` is a 32-bit\n 1670| *WARL* register that controls which of the hardware performance-monitoring counters increment.#\n 1671| [#norm:mcountinhibit_only_inc]#The settings in this register only control whether the" + }, + { + "score": 12, + "reasons": [ + "CSR name 'mcountinhibit' in backticks", + "CSR field name 'IR'", + "CSR field name 'CY'", + "Description keyword 'mcountinhibit'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1675, + "line_text": "[#norm:mcountinhibit_op2]#When the CY, IR, or HPM__n__ bit in the `mcountinhibit` register is clear,", + "context": " 1673| of this register.#\n 1674| \n>>> 1675| [#norm:mcountinhibit_op2]#When the CY, IR, or HPM__n__ bit in the `mcountinhibit` register is clear,\n 1676| the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.\n 1677| When the CY, IR, or HPM__n__ bit is set, the corresponding counter does" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'TM'", + "CSR field name 'IR'", + "CSR field name 'CY'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1615, + "line_text": "[#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is", + "context": " 1613| counters, which continue to increment even when not accessible.#\n 1614| \n>>> 1615| [#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is\n 1616| clear, attempts to read the `cycle`, `time`, `instret`, or\n 1617| `hpmcountern` register while executing in S-mode or U-mode will cause an" + }, + { + "score": 8, + "reasons": [ + "CSR name 'mcountinhibit' in backticks", + "Description keyword 'mcountinhibit'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1684, + "line_text": "[#norm:mcountinhibit_not_impl]#If the `mcountinhibit` register is not implemented, the implementation", + "context": " 1682| and so writes to `mcountinhibit.CY` will be visible to those harts.#\n 1683| \n>>> 1684| [#norm:mcountinhibit_not_impl]#If the `mcountinhibit` register is not implemented, the implementation\n 1685| behaves as though the register were set to zero.#\n 1686| " + }, + { + "score": 6, + "reasons": [ + "Description keyword 'TM'", + "CSR field name 'IR'", + "CSR field name 'CY'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 857, + "line_text": "When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is", + "context": " 855| \n 856| [[norm:hcounteren_op]]\n>>> 857| When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is\n 858| clear, attempts to read the `cycle`, `time`, `instret`, or\n 859| `hpmcounter` _n_ register while V=1 will cause a virtual-instruction" + } + ] + }, + { + "parameter_name": "DBG_HCONTEXT_WIDTH", + "classification": "NORM_CSR_WARL", + "value_type": "range", + "num_candidates": 2, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Description keyword 'HCONTEXT'", + "CSR field name 'HCONTEXT'", + "Name segment 'HCONTEXT'", + "CSR name 'hcontext' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 287, + "line_text": "`hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in", + "context": " 285| \n 286| The CONTEXT bit in `mstateen0` controls access to the `scontext` and\n>>> 287| `hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in\n 288| `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig\n 289| extension." + }, + { + "score": 3, + "reasons": ["CSR name 'mcontext' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 1019, + "line_text": "`mcontext`", + "context": " 1017| `tdata2` +\n 1018| `tdata3` +\n>>> 1019| `mcontext`\n 1020| \n 1021| |Debug/Trace trigger register select. +" + } + ] + }, + { + "parameter_name": "DBG_SCONTEXT_WIDTH", + "classification": "NORM_CSR_WARL", + "value_type": "range", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": [ + "Description keyword 'SCONTEXT'", + "Name segment 'SCONTEXT'", + "CSR name 'scontext' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 146, + "line_text": "Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`,", + "context": " 144| \n 145| [[norm:H_scsrs_nomatch]]\n>>> 146| Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`,\n 147| possibly others) have no matching VS CSR. These supervisor CSRs continue\n 148| to have their usual function and accessibility even when V=1, except" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'SCONTEXT'", + "Name segment 'SCONTEXT'", + "CSR name 'scontext' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 286, + "line_text": "The CONTEXT bit in `mstateen0` controls access to the `scontext` and", + "context": " 284| bits of `hstateen0`.\n 285| \n>>> 286| The CONTEXT bit in `mstateen0` controls access to the `scontext` and\n 287| `hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in\n 288| `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'SCONTEXT'", + "Name segment 'SCONTEXT'", + "CSR name 'scontext' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 288, + "line_text": "`hstateen0` controls access to the `scontext` CSR provided by the Sdtrig", + "context": " 286| The CONTEXT bit in `mstateen0` controls access to the `scontext` and\n 287| `hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in\n>>> 288| `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig\n 289| extension.\n 290| " + }, + { + "score": 4, + "reasons": ["CSR field name 'DATA'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 698, + "line_text": "[#norm:mstatus_sbe_implicit]#For _implicit_ accesses to supervisor-level memory management data", + "context": " 696| little-endian (UBE=0) or big-endian (UBE=1).\n 697| \n>>> 698| [#norm:mstatus_sbe_implicit]#For _implicit_ accesses to supervisor-level memory management data\n 699| structures, such as page tables, endianness is always controlled by SBE.#\n 700| [#norm:mstatus_sbe_change_fence]#Since changing SBE alters the implementation’s interpretation of these" + }, + { + "score": 4, + "reasons": ["CSR field name 'DATA'"], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 294, + "line_text": "[#norm:ctrsource_op]#The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.# [#norm:ctrsource_ctrtartget_ctrdata_Vbit]#The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.#", + "context": " 292| ==== Control Transfer Record Source Register (`ctrsource`)\n 293| \n>>> 294| [#norm:ctrsource_op]#The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.# [#norm:ctrsource_ctrtartget_ctrdata_Vbit]#The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.#\n 295| \n 296| [#norm:Ssctr_ctrsource_sz_acc_op]#`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.#" + } + ] + }, + { + "parameter_name": "DCSR_MPRVEN_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 4, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 87, + "line_text": "transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#", + "context": " 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n>>> 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| \n 89| [[norm:zicflip_pelp_trap]]" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 101, + "line_text": "Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`", + "context": " 99| \n 100| [[norm:zicflip_pelp_debug_mode]]\n>>> 101| Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`\n 102| at the privilege level the hart was previously in, and the `ELP` is set to\n 103| `NO_LP_EXPECTED`. When a hart resumes from Debug Mode, if the new privilege mode" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 1037, + "line_text": "|`dcsr` +", + "context": " 1035| DRW +\n 1036| DRW +\n>>> 1037| |`dcsr` +\n 1038| `dpc` +\n 1039| `dscratch0` +" + }, + { + "score": 3, + "reasons": ["Name segment 'DCSR'"], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 86, + "line_text": "`vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on", + "context": " 84| `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.# [#norm:vsstatus-spelp_op2]#To store\n 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n>>> 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| " + } + ] + }, + { + "parameter_name": "DCSR_STEPIE_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 4, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 87, + "line_text": "transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#", + "context": " 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n>>> 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| \n 89| [[norm:zicflip_pelp_trap]]" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 101, + "line_text": "Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`", + "context": " 99| \n 100| [[norm:zicflip_pelp_debug_mode]]\n>>> 101| Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`\n 102| at the privilege level the hart was previously in, and the `ELP` is set to\n 103| `NO_LP_EXPECTED`. When a hart resumes from Debug Mode, if the new privilege mode" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 1037, + "line_text": "|`dcsr` +", + "context": " 1035| DRW +\n 1036| DRW +\n>>> 1037| |`dcsr` +\n 1038| `dpc` +\n 1039| `dscratch0` +" + }, + { + "score": 3, + "reasons": ["Name segment 'DCSR'"], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 86, + "line_text": "`vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on", + "context": " 84| `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.# [#norm:vsstatus-spelp_op2]#To store\n 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n>>> 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| " + } + ] + }, + { + "parameter_name": "DCSR_STOPCOUNT_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 4, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 87, + "line_text": "transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#", + "context": " 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n>>> 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| \n 89| [[norm:zicflip_pelp_trap]]" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 101, + "line_text": "Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`", + "context": " 99| \n 100| [[norm:zicflip_pelp_debug_mode]]\n>>> 101| Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`\n 102| at the privilege level the hart was previously in, and the `ELP` is set to\n 103| `NO_LP_EXPECTED`. When a hart resumes from Debug Mode, if the new privilege mode" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 1037, + "line_text": "|`dcsr` +", + "context": " 1035| DRW +\n 1036| DRW +\n>>> 1037| |`dcsr` +\n 1038| `dpc` +\n 1039| `dscratch0` +" + }, + { + "score": 3, + "reasons": ["Name segment 'DCSR'"], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 86, + "line_text": "`vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on", + "context": " 84| `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.# [#norm:vsstatus-spelp_op2]#To store\n 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n>>> 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| " + } + ] + }, + { + "parameter_name": "DCSR_STOPTIME_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 4, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 87, + "line_text": "transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#", + "context": " 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n>>> 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| \n 89| [[norm:zicflip_pelp_trap]]" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 101, + "line_text": "Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`", + "context": " 99| \n 100| [[norm:zicflip_pelp_debug_mode]]\n>>> 101| Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`\n 102| at the privilege level the hart was previously in, and the `ELP` is set to\n 103| `NO_LP_EXPECTED`. When a hart resumes from Debug Mode, if the new privilege mode" + }, + { + "score": 4, + "reasons": ["Name segment 'DCSR'", "CSR name 'dcsr' in backticks"], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 1037, + "line_text": "|`dcsr` +", + "context": " 1035| DRW +\n 1036| DRW +\n>>> 1037| |`dcsr` +\n 1038| `dpc` +\n 1039| `dscratch0` +" + }, + { + "score": 3, + "reasons": ["Name segment 'DCSR'"], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 86, + "line_text": "`vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on", + "context": " 84| `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.# [#norm:vsstatus-spelp_op2]#To store\n 85| the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the\n>>> 86| `vsstatus` (VS-modes version of `sstatus`).# [#norm:dcsr-pelp_op]#To store the previous `ELP` state on\n 87| transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.#\n 88| " + } + ] + }, + { + "parameter_name": "ELEN", + "classification": "NORM_DIRECT", + "value_type": "value", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": ["Exact parameter name 'ELEN'", "Name segment 'ELEN'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 24, + "line_text": ". [#norm:vlen_param]#The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.#", + "context": " 22| . [#norm:elen_param]#The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which\n 23| must be a power of 2.#\n>>> 24| . [#norm:vlen_param]#The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.#\n 25| \n 26| Standard vector extensions (<>) and" + }, + { + "score": 9, + "reasons": ["Exact parameter name 'ELEN'", "Name segment 'ELEN'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 169, + "line_text": "NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage", + "context": " 167| \n 168| \n>>> 169| NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage\n 170| bit to hold `vill`.#\n 171| " + }, + { + "score": 8, + "reasons": ["Parameter name in emphasis '_ELEN_'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 22, + "line_text": ". [#norm:elen_param]#The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which", + "context": " 20| Each hart supporting a vector extension defines two parameters:\n 21| \n>>> 22| . [#norm:elen_param]#The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which\n 23| must be a power of 2.#\n 24| . [#norm:vlen_param]#The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.#" + }, + { + "score": 7, + "reasons": ["Exact parameter name 'ELEN'", "Name segment 'ELEN'"], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 29, + "line_text": "NOTE: Future extensions may allow ELEN {gt} VLEN by holding one", + "context": " 27| architecture profiles may set further constraints on _ELEN_ and _VLEN_.\n 28| \n>>> 29| NOTE: Future extensions may allow ELEN {gt} VLEN by holding one\n 30| element using bits from multiple vector registers, but this\n 31| extension does not include this option." + }, + { + "score": 7, + "reasons": ["Exact parameter name 'ELEN'", "Name segment 'ELEN'"], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 50, + "line_text": "VLEN or ELEN parameters.", + "context": " 48| NOTE: In general, thread contexts with active vector state cannot be\n 49| migrated during execution between harts that have any difference in\n>>> 50| VLEN or ELEN parameters.\n 51| \n 52| === Vector Extension Programmer's Model" + } + ] + }, + { + "parameter_name": "FOLLOW_VTYPE_RESET_RECOMMENDATION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 14, + "candidates": [ + { + "score": 14, + "reasons": [ + "Name segment 'VTYPE'", + "CSR field name 'VALUE'", + "CSR name 'vtype' in backticks", + "CSR field name 'VLMUL'", + "CSR field name 'VSEW'", + "CSR field name 'VILL'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 169, + "line_text": "NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage", + "context": " 167| \n 168| \n>>> 169| NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage\n 170| bit to hold `vill`.#\n 171| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'VTYPE'", + "CSR name 'vtype' in backticks", + "CSR field name 'VTA'", + "CSR field name 'VMA'", + "CSR field name 'VILL'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 162, + "line_text": "The `vtype` register has five fields, `vill`, `vma`, `vta`,", + "context": " 160| \n 161| [[norm:vtype-fields_sz]]\n>>> 162| The `vtype` register has five fields, `vill`, `vma`, `vta`,\n 163| `vsew[2:0]`, and `vlmul[2:0]`. Bits `vtype[XLEN-2:8]` should be\n 164| written with zero, and non-zero values in this field are reserved." + }, + { + "score": 9, + "reasons": [ + "Name segment 'VTYPE'", + "CSR name 'vl' in backticks", + "CSR name 'vtype' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1178, + "line_text": "values in `vl` and `vtype` to match application needs. [#norm:vset_op]#The", + "context": " 1176| \n 1177| A set of instructions is provided to allow rapid configuration of the\n>>> 1178| values in `vl` and `vtype` to match application needs. [#norm:vset_op]#The\n 1179| `vset{i}vl{i}` instructions set the `vtype` and `vl` CSRs based on\n 1180| their arguments, and write the new value of `vl` into `rd`.#" + }, + { + "score": 9, + "reasons": [ + "CSR field name 'VILL'", + "CSR name 'vl' in backticks", + "CSR field name 'VALUE'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1279, + "line_text": "[#norm:vsetvl_op_rs1_x0_rd_x0]#When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register. This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.# [#norm:vtype_vset_rsv]#Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if `vill` was 1 beforehand.# [#norm:reserved_vill_set_param]#Implementations may set `vill` in either case.#", + "context": " 1277| also to the `x` register specified by `rd`.\n 1278| \n>>> 1279| [#norm:vsetvl_op_rs1_x0_rd_x0]#When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register. This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.# [#norm:vtype_vset_rsv]#Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if `vill` was 1 beforehand.# [#norm:reserved_vill_set_param]#Implementations may set `vill` in either case.#\n 1280| \n 1281| NOTE: This last form of the instructions allows the `vtype` register to" + }, + { + "score": 9, + "reasons": [ + "Name segment 'VTYPE'", + "CSR name 'vl' in backticks", + "CSR field name 'VALUE'", + "CSR name 'vtype' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1284, + "line_text": "legal value for current `vtype` setting. The current `vl` value can", + "context": " 1282| be changed while maintaining the current `vl`, provided VLMAX is not\n 1283| reduced. This design was chosen to ensure `vl` would always hold a\n>>> 1284| legal value for current `vtype` setting. The current `vl` value can\n 1285| be read from the `vl` CSR. The `vl` value could be reduced by these\n 1286| instructions if the new SEW/LMUL ratio causes VLMAX to shrink, and so" + } + ] + }, + { + "parameter_name": "FORCE_UPGRADE_CBO_INVAL_TO_FLUSH", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 20, + "candidates": [ + { + "score": 20, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'CBIE'", + "CSR field name 'CBIE'", + "Name segment 'INVAL'", + "Description keyword 'cbo.inval'", + "Description keyword 'INVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 913, + "line_text": "implemented, `CBIE` is read-only zero. Execution of `CBO.INVAL` in U-mode is", + "context": " 911| WARL field to `senvcfg` to control execution of the `CBO.INVAL` instruction in\n 912| U-mode. The encoding `10b` is reserved. When the Zicbom extension is not\n>>> 913| implemented, `CBIE` is read-only zero. Execution of `CBO.INVAL` in U-mode is\n 914| enabled only if execution of the instruction is enabled for use in S-mode and\n 915| `CBIE` is set to `01b` or `11b`; otherwise, an illegal-instruction exception is" + }, + { + "score": 19, + "reasons": [ + "Description keyword 'CBIE'", + "CSR field name 'CBIE'", + "Name segment 'INVAL'", + "Description keyword 'cbo.inval'", + "Description keyword 'INVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2293, + "line_text": "instruction (`CBO.INVAL`) in modes less privileged than M. When `CBIE` is set to", + "context": " 2291| [#norm:menvcfg-cbie]#The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable)\n 2292| WARL field to `menvcfg` to control execution of the cache block invalidate\n>>> 2293| instruction (`CBO.INVAL`) in modes less privileged than M. When `CBIE` is set to\n 2294| `00b`, the instruction raises an illegal-instruction exception in modes less\n 2295| privileged than M. When the Zicbom extension is not implemented, `CBIE` is" + }, + { + "score": 12, + "reasons": ["Description keyword 'CBIE'", "CSR field name 'CBIE'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 772, + "line_text": "[[norm:henvcfg-cbie]]", + "context": " 770| not implemented, `CBCFE` is read-only zero.\n 771| \n>>> 772| [[norm:henvcfg-cbie]]\n 773| The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable)\n 774| WARL field to `henvcfg`. The `CBIE` field controls execution of the cache block" + }, + { + "score": 12, + "reasons": [ + "Name segment 'INVAL'", + "Name segment 'FLUSH'", + "Description keyword 'cbo.inval'", + "Description keyword 'INVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 785, + "line_text": "[#norm:cbo-inval_h-mode_op0]#If `CBO.INVAL` is enabled in HS-mode to perform a flush operation, then when the", + "context": " 783| otherwise, it raises a virtual-instruction exception.\n 784| \n>>> 785| [#norm:cbo-inval_h-mode_op0]#If `CBO.INVAL` is enabled in HS-mode to perform a flush operation, then when the\n 786| instruction is enabled in VS- or VU-mode it performs a flush operation, even if\n 787| `CBIE` is set to `11b`. Otherwise, when the instruction is enabled for" + }, + { + "score": 12, + "reasons": ["Description keyword 'CBIE'", "CSR field name 'CBIE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 2291, + "line_text": "[#norm:menvcfg-cbie]#The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable)", + "context": " 2289| than M. When the Zicbom extension is not implemented, `CBCFE` is read-only zero.\n 2290| \n>>> 2291| [#norm:menvcfg-cbie]#The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable)\n 2292| WARL field to `menvcfg` to control execution of the cache block invalidate\n 2293| instruction (`CBO.INVAL`) in modes less privileged than M. When `CBIE` is set to" + } + ] + }, + { + "parameter_name": "GSTAGE_MODE_BARE", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Description keyword 'hgatp'", + "WARL + CSR 'hgatp'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1075, + "line_text": "is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,", + "context": " 1073| [[norm:hgatp-mode_warl]]\n 1074| A write to `hgatp` with an unsupported MODE value is not ignored as it\n>>> 1075| is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,\n 1076| when so indicated.\n 1077| " + }, + { + "score": 9, + "reasons": [ + "Description keyword 'hgatp'", + "CSR field name 'MODE'", + "Name segment 'BARE'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1007, + "line_text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.", + "context": " 1005| \n 1006| [[rv64hgatp]]\n>>> 1007| .Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.\n 1008| include::images/bytefield/rv64hgatp.edn[]\n 1009| " + }, + { + "score": 8, + "reasons": [ + "Description keyword 'hgatp'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 989, + "line_text": "[#norm:hgatp_sz_acc_op]#The `hgatp` register is an HSXLEN-bit read/write register, formatted as", + "context": " 987| ==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register\n 988| \n>>> 989| [#norm:hgatp_sz_acc_op]#The `hgatp` register is an HSXLEN-bit read/write register, formatted as\n 990| shown in <> for HSXLEN=32 and\n 991| <> for HSXLEN=64, which controls" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'hgatp'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 999, + "line_text": "addresses. [#norm:hgatp_tvm_illegal]#When `mstatus`.TVM=1, attempts to read or write `hgatp` while", + "context": " 997| address-translation fences on a per-virtual-machine basis; and the MODE\n 998| field, which selects the address-translation scheme for guest physical\n>>> 999| addresses. [#norm:hgatp_tvm_illegal]#When `mstatus`.TVM=1, attempts to read or write `hgatp` while\n 1000| executing in HS-mode will raise an illegal-instruction exception.#\n 1001| " + }, + { + "score": 8, + "reasons": [ + "Description keyword 'hgatp'", + "CSR field name 'MODE'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1033, + "line_text": ".Encoding of `hgatp` MODE field.", + "context": " 1031| \n 1032| [[hgatp-mode]]\n>>> 1033| .Encoding of `hgatp` MODE field.\n 1034| [%autowidth,float=\"center\",align=\"center\",cols=\"^,^,<\",options=\"header\"]\n 1035| |===" + } + ] + }, + { + "parameter_name": "HCONTEXT_AVAILABLE", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Description keyword 'HCONTEXT'", + "CSR field name 'HCONTEXT'", + "Name segment 'HCONTEXT'", + "CSR name 'hcontext' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 287, + "line_text": "`hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in", + "context": " 285| \n 286| The CONTEXT bit in `mstateen0` controls access to the `scontext` and\n>>> 287| `hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in\n 288| `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig\n 289| extension." + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 231, + "line_text": "[#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the", + "context": " 229| \n 230| [#norm:misa_e_acc]#The \"E\" bit is read-only.#\n>>> 231| [#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the\n 232| \"E\" bit always reads as the complement of the \"I\" bit.#\n 233| If an execution environment supports both RV32E and RV32I, software can select" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + } + ] + }, + { + "parameter_name": "HCOUNTENABLE_EN", + "classification": "NORM_CSR_RW", + "value_type": "bitmask", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "CSR field name 'IR'", + "CSR name 'hcounteren' in backticks", + "CSR field name 'TM'", + "Description keyword 'hcounteren'", + "CSR field name 'CY'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 857, + "line_text": "When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is", + "context": " 855| \n 856| [[norm:hcounteren_op]]\n>>> 857| When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is\n 858| clear, attempts to read the `cycle`, `time`, `instret`, or\n 859| `hpmcounter` _n_ register while V=1 will cause a virtual-instruction" + }, + { + "score": 8, + "reasons": [ + "CSR name 'hcounteren' in backticks", + "CSR field name 'TM'", + "Description keyword 'hcounteren'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 867, + "line_text": "In addition, when the TM bit in the `hcounteren` register is clear, attempts to", + "context": " 865| \n 866| [[norm:hcounteren_acc]]\n>>> 867| In addition, when the TM bit in the `hcounteren` register is clear, attempts to\n 868| access the `vstimecmp` register (via `stimecmp`) while executing in VS-mode will\n 869| cause a virtual-instruction exception if the same bit in `mcounteren` is set." + }, + { + "score": 8, + "reasons": [ + "CSR field name 'IR'", + "CSR field name 'TM'", + "CSR field name 'CY'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1615, + "line_text": "[#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is", + "context": " 1613| counters, which continue to increment even when not accessible.#\n 1614| \n>>> 1615| [#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is\n 1616| clear, attempts to read the `cycle`, `time`, `instret`, or\n 1617| `hpmcountern` register while executing in S-mode or U-mode will cause an" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'Zihpm'", + "Description keyword 'Zicntr'" + ], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 2, + "line_text": "== \"Zicntr\" and \"Zihpm\" Extensions for Counters, Version 2.0", + "context": " 1| [[counters]]\n>>> 2| == \"Zicntr\" and \"Zihpm\" Extensions for Counters, Version 2.0\n 3| \n 4| [[norm:zihpm_op_sz_mode_acc]]" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'Zihpm'", + "Description keyword 'Zicntr'" + ], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 9, + "line_text": "divided between the \"Zicntr\" and \"Zihpm\" extensions.", + "context": " 7| read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits\n 8| are accessed via CSR registers `0xC80`–`0xC9F`). These counters are\n>>> 9| divided between the \"Zicntr\" and \"Zihpm\" extensions.\n 10| \n 11| === \"Zicntr\" Extension for Base Counters and Timers" + } + ] + }, + { + "parameter_name": "HPM_COUNTER_EN", + "classification": "NORM_CSR_RW", + "value_type": "bitmask", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Description keyword 'TM'", + "Description keyword 'CY'", + "Description keyword 'IR'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1615, + "line_text": "[#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is", + "context": " 1613| counters, which continue to increment even when not accessible.#\n 1614| \n>>> 1615| [#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is\n 1616| clear, attempts to read the `cycle`, `time`, `instret`, or\n 1617| `hpmcountern` register while executing in S-mode or U-mode will cause an" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'TM'", + "Description keyword 'CY'", + "Description keyword 'IR'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 857, + "line_text": "When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is", + "context": " 855| \n 856| [[norm:hcounteren_op]]\n>>> 857| When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is\n 858| clear, attempts to read the `cycle`, `time`, `instret`, or\n 859| `hpmcounter` _n_ register while V=1 will cause a virtual-instruction" + }, + { + "score": 6, + "reasons": ["Description keyword 'CY'", "Description keyword 'IR'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1675, + "line_text": "[#norm:mcountinhibit_op2]#When the CY, IR, or HPM__n__ bit in the `mcountinhibit` register is clear,", + "context": " 1673| of this register.#\n 1674| \n>>> 1675| [#norm:mcountinhibit_op2]#When the CY, IR, or HPM__n__ bit in the `mcountinhibit` register is clear,\n 1676| the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.\n 1677| When the CY, IR, or HPM__n__ bit is set, the corresponding counter does" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'TM'", + "Description keyword 'CY'", + "Description keyword 'IR'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 511, + "line_text": "When the CY, TM, IR, or HPM__n__ bit in the `scounteren` register is", + "context": " 509| \n 510| [[norm:scounteren_op]]\n>>> 511| When the CY, TM, IR, or HPM__n__ bit in the `scounteren` register is\n 512| clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern`\n 513| register while executing in U-mode will cause an illegal-instruction" + }, + { + "score": 5, + "reasons": [ + "Name segment 'COUNTER'", + "Description keyword 'CY'", + "Description keyword 'IR'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1677, + "line_text": "When the CY, IR, or HPM__n__ bit is set, the corresponding counter does", + "context": " 1675| [#norm:mcountinhibit_op2]#When the CY, IR, or HPM__n__ bit in the `mcountinhibit` register is clear,\n 1676| the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.\n>>> 1677| When the CY, IR, or HPM__n__ bit is set, the corresponding counter does\n 1678| not increment.#\n 1679| " + } + ] + }, + { + "parameter_name": "HPM_EVENTS", + "classification": "NORM_CSR_WARL", + "value_type": "set", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR name 'mhpmevent3' in backticks", + "WARL + CSR 'mhpmevent3'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1581, + "line_text": "`mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which", + "context": " 1579| counters, `mhpmcounter3`-`mhpmcounter31`.#\n 1580| [#norm:mhpmevent_sz_warl_op]#The event selector CSRs,\n>>> 1581| `mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which\n 1582| event causes the corresponding counter to increment.#\n 1583| [#norm:mhpmevent_enc]#The meaning of these events is defined by the platform," + }, + { + "score": 4, + "reasons": ["CSR field name 'EVENT'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 526, + "line_text": "[#norm:trap_unexp_hndl_lead-in]#In the event of a _unexpected trap_, the handling is as follows:#", + "context": " 524| `mnstatus.NMIE` set to 0 is an _unexpected trap_.#\n 525| \n>>> 526| [#norm:trap_unexp_hndl_lead-in]#In the event of a _unexpected trap_, the handling is as follows:#\n 527| \n 528| * [#norm:trap_unexp_hndl_rnmi]#When the Smrnmi extension is implemented and `mnstatus.NMIE` is 1, the hart" + }, + { + "score": 4, + "reasons": ["CSR field name 'EVENT'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1578, + "line_text": "[#norm:mhpmcounter_num]#The hardware performance monitor includes 29 additional 64-bit event", + "context": " 1576| to indicate which harts share an `mcycle` CSR.\n 1577| \n>>> 1578| [#norm:mhpmcounter_num]#The hardware performance monitor includes 29 additional 64-bit event\n 1579| counters, `mhpmcounter3`-`mhpmcounter31`.#\n 1580| [#norm:mhpmevent_sz_warl_op]#The event selector CSRs," + }, + { + "score": 4, + "reasons": ["CSR field name 'EVENT'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1580, + "line_text": "[#norm:mhpmevent_sz_warl_op]#The event selector CSRs,", + "context": " 1578| [#norm:mhpmcounter_num]#The hardware performance monitor includes 29 additional 64-bit event\n 1579| counters, `mhpmcounter3`-`mhpmcounter31`.#\n>>> 1580| [#norm:mhpmevent_sz_warl_op]#The event selector CSRs,\n 1581| `mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which\n 1582| event causes the corresponding counter to increment.#" + }, + { + "score": 4, + "reasons": ["CSR field name 'EVENT'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1586, + "line_text": "[#norm:mhpmcounter_mhpmevent_rdonly0]#a legal implementation is to make both the counter and its corresponding event selector be read-only 0.#", + "context": " 1584| but event 0 is defined to mean \"no event.\"#\n 1585| [#norm:mhpmcounter_mandatory]#All counters should be implemented#, but\n>>> 1586| [#norm:mhpmcounter_mhpmevent_rdonly0]#a legal implementation is to make both the counter and its corresponding event selector be read-only 0.#\n 1587| \n 1588| .Hardware performance monitor counters." + } + ] + }, + { + "parameter_name": "HSTATEEN_AIA_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 0, + "best_score": 0, + "candidates": [] + }, + { + "parameter_name": "HSTATEEN_CONTEXT_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 652, + "line_text": "[#norm:ccounter_reset]#The CtrCycleCounter is reset on writes to `__x__ctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.#", + "context": " 650| ----\n 651| \n>>> 652| [#norm:ccounter_reset]#The CtrCycleCounter is reset on writes to `__x__ctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.#\n 653| \n 654| [#norm:ccounter_impl]#An implementation that supports cycle counting must implement CCV and all" + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "bfloat16.adoc", + "line_number": 82, + "line_text": "in context, and advise on how they best to fit the functionality.", + "context": " 80| Furthermore, we expect architects to be able to examine our instructions\n 81| for implementation issues, understand how the instructions will be used\n>>> 82| in context, and advise on how they best to fit the functionality.\n 83| \n 84| Digital design engineers & micro-architects::" + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "calling-convention.adoc", + "line_number": 24, + "line_text": "NOTE: This scheme allows system calls that cause context switches to avoid", + "context": " 22| (`v0`-`v31`, `vl`, `vtype`) and `vstart` to become unspecified.\n 23| \n>>> 24| NOTE: This scheme allows system calls that cause context switches to avoid\n 25| saving and later restoring the vector registers.\n 26| " + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1218, + "line_text": "Read-only fields SD and XS summarize the extension context status as it", + "context": " 1216| \n 1217| [[norm:vsstatus-sd_xs_op]]\n>>> 1218| Read-only fields SD and XS summarize the extension context status as it\n 1219| is visible to VS-mode only. For example, the value of the HS-level\n 1220| `sstatus`.FS does not affect `vsstatus`.SD." + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 828, + "line_text": "===== Extension Context Status in `mstatus` Register", + "context": " 826| ====\n 827| \n>>> 828| ===== Extension Context Status in `mstatus` Register\n 829| \n 830| Supporting substantial extensions is one of the primary goals of RISC-V," + } + ] + }, + { + "parameter_name": "HSTATEEN_CSRIND_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 6, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 191, + "line_text": "{bits: 1, name: 'CSRIND'},", + "context": " 189| {bits: 1, name: 'IMSIC'},\n 190| {bits: 1, name: 'AIA'},\n>>> 191| {bits: 1, name: 'CSRIND'},\n 192| {bits: 1, name: 'WPRI'},\n 193| {bits: 1, name: 'ENVCFG'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 211, + "line_text": "{bits: 1, name: 'CSRIND'},", + "context": " 209| {bits: 1, name: 'IMSIC'},\n 210| {bits: 1, name: 'AIA'},\n>>> 211| {bits: 1, name: 'CSRIND'},\n 212| {bits: 1, name: 'WPRI'},\n 213| {bits: 1, name: 'ENVCFG'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 263, + "line_text": "The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`,", + "context": " 261| `senvcfg` CSRs.\n 262| \n>>> 263| The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`,\n 264| `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.\n 265| The CSRIND bit in `hstateen0` controls access to the `siselect` and the" + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 265, + "line_text": "The CSRIND bit in `hstateen0` controls access to the `siselect` and the", + "context": " 263| The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`,\n 264| `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.\n>>> 265| The CSRIND bit in `hstateen0` controls access to the `siselect` and the\n 266| `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind\n 267| extensions." + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 281, + "line_text": "Ssaia extension and not controlled by either the CSRIND or the IMSIC", + "context": " 279| \n 280| The AIA bit in `mstateen0` controls access to all state introduced by the\n>>> 281| Ssaia extension and not controlled by either the CSRIND or the IMSIC\n 282| bits. The AIA bit in `hstateen0` controls access to all state introduced by the\n 283| Ssaia extension and not controlled by either the CSRIND or the IMSIC" + } + ] + }, + { + "parameter_name": "HSTATEEN_ENVCFG_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 6, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 134, + "line_text": "*__x__*`envcfg.SSE` fields. The conditions are specified as follows:", + "context": " 132| Attempts to access the `ssp` CSR may result in either an illegal-instruction\n 133| exception or a virtual-instruction exception, contingent upon the state of the\n>>> 134| *__x__*`envcfg.SSE` fields. The conditions are specified as follows:\n 135| \n 136| * [#norm:zicfiss_m_menvcfg-sse]#If the privilege mode is less than M and `menvcfg.SSE` is 0, an" + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "riscv-unprivileged.adoc", + "line_number": 47, + "line_text": ":csrname: envcfg", + "context": " 45| :stem: latexmath\n 46| :footnote:\n>>> 47| :csrname: envcfg\n 48| :imagesdir: images\n 49| " + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 193, + "line_text": "{bits: 1, name: 'ENVCFG'},", + "context": " 191| {bits: 1, name: 'CSRIND'},\n 192| {bits: 1, name: 'WPRI'},\n>>> 193| {bits: 1, name: 'ENVCFG'},\n 194| {bits: 1, name: 'SE0'},\n 195| ], config: {bits: 64, lanes: 4, hspace:1024}}" + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 213, + "line_text": "{bits: 1, name: 'ENVCFG'},", + "context": " 211| {bits: 1, name: 'CSRIND'},\n 212| {bits: 1, name: 'WPRI'},\n>>> 213| {bits: 1, name: 'ENVCFG'},\n 214| {bits: 1, name: 'SE0'},\n 215| ], config: {bits: 64, lanes: 4, hspace:1024}}" + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 259, + "line_text": "The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`,", + "context": " 257| `sstateen0` CSR.\n 258| \n>>> 259| The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`,\n 260| and the `senvcfg` CSRs. The ENVCFG bit in `hstateen0` controls access to the\n 261| `senvcfg` CSRs." + } + ] + }, + { + "parameter_name": "HSTATEEN_IMSIC_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 7, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 189, + "line_text": "{bits: 1, name: 'IMSIC'},", + "context": " 187| {bits: 1, name: 'P1P13'},\n 188| {bits: 1, name: 'CONTEXT'},\n>>> 189| {bits: 1, name: 'IMSIC'},\n 190| {bits: 1, name: 'AIA'},\n 191| {bits: 1, name: 'CSRIND'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 209, + "line_text": "{bits: 1, name: 'IMSIC'},", + "context": " 207| {bits: 2, name: 'WPRI'},\n 208| {bits: 1, name: 'CONTEXT'},\n>>> 209| {bits: 1, name: 'IMSIC'},\n 210| {bits: 1, name: 'AIA'},\n 211| {bits: 1, name: 'CSRIND'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 269, + "line_text": "The IMSIC bit in `mstateen0` controls access to the IMSIC state, including", + "context": " 267| extensions.\n 268| \n>>> 269| The IMSIC bit in `mstateen0` controls access to the IMSIC state, including\n 270| CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in\n 271| `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`" + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 270, + "line_text": "CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in", + "context": " 268| \n 269| The IMSIC bit in `mstateen0` controls access to the IMSIC state, including\n>>> 270| CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in\n 271| `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`\n 272| (really `vstopei`), provided by the Ssaia extension." + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 271, + "line_text": "`hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`", + "context": " 269| The IMSIC bit in `mstateen0` controls access to the IMSIC state, including\n 270| CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in\n>>> 271| `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`\n 272| (really `vstopei`), provided by the Ssaia extension.\n 273| " + } + ] + }, + { + "parameter_name": "HSTATEEN_JVT_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 1, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Description keyword 'JVT'"], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2341, + "line_text": "[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#", + "context": " 2339| ==== jvt\n 2340| \n>>> 2341| [#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#\n 2342| \n 2343| If the same function is called with and without linking then it must have two entries in the table." + } + ] + }, + { + "parameter_name": "HW_MSTATUS_FS_DIRTY_UPDATE", + "classification": "SW_RULE", + "value_type": "enum", + "num_candidates": 10, + "best_score": 26, + "candidates": [ + { + "score": 26, + "reasons": [ + "Description keyword 'FS'", + "Name segment 'MSTATUS'", + "Description keyword 'mstatus.FS'", + "Description keyword 'mstatus'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 3313, + "line_text": "[#norm:mstatus-FS_off_V_fp_ill]#If the floating-point unit status field `mstatus.FS` is `Off` then any", + "context": " 3311| half-precision floating-point support.\n 3312| \n>>> 3313| [#norm:mstatus-FS_off_V_fp_ill]#If the floating-point unit status field `mstatus.FS` is `Off` then any\n 3314| attempt to execute a vector floating-point instruction will raise an\n 3315| illegal-instruction exception.# [#norm:mstatus-FS_dirty_V_fp]#Any vector floating-point instruction" + }, + { + "score": 25, + "reasons": [ + "Name segment 'DIRTY'", + "Description keyword 'mstatus'", + "Description keyword 'mstatus.FS'", + "Description keyword 'FS'", + "Name segment 'MSTATUS'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 3317, + "line_text": "CSRs or `f` registers) must set `mstatus.FS` to `Dirty`.#", + "context": " 3315| illegal-instruction exception.# [#norm:mstatus-FS_dirty_V_fp]#Any vector floating-point instruction\n 3316| that modifies any floating-point extension state (i.e., floating-point\n>>> 3317| CSRs or `f` registers) must set `mstatus.FS` to `Dirty`.#\n 3318| \n 3319| [#norm:vsstatus_mstatus-FS_off_hypervisor_V_fp_ill]#If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is" + }, + { + "score": 25, + "reasons": [ + "Name segment 'DIRTY'", + "Description keyword 'mstatus'", + "Description keyword 'mstatus.FS'", + "Description keyword 'FS'", + "Name segment 'MSTATUS'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 3325, + "line_text": "CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`.#", + "context": " 3323| illegal-instruction exception.# [#norm:vsstatus_mstatus-FS_dirty_hypervisor_V_fp]#Any vector floating-point instruction\n 3324| that modifies any floating-point extension state (i.e., floating-point\n>>> 3325| CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`.#\n 3326| \n 3327| The vector floating-point instructions have the same behavior as the" + }, + { + "score": 24, + "reasons": [ + "Description keyword 'FS'", + "Name segment 'MSTATUS'", + "Description keyword 'mstatus.FS'", + "Description keyword 'mstatus'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 3321, + "line_text": "`vsstatus.FS` or `mstatus.FS` is `Off` then any", + "context": " 3319| [#norm:vsstatus_mstatus-FS_off_hypervisor_V_fp_ill]#If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is\n 3320| additionally in effect for vector floating-point instructions. If\n>>> 3321| `vsstatus.FS` or `mstatus.FS` is `Off` then any\n 3322| attempt to execute a vector floating-point instruction will raise an\n 3323| illegal-instruction exception.# [#norm:vsstatus_mstatus-FS_dirty_hypervisor_V_fp]#Any vector floating-point instruction" + }, + { + "score": 15, + "reasons": [ + "Description keyword 'FS'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks", + "Description keyword 'mstatus'" + ], + "is_normative": false, + "in_note": false, + "file": "zfinx.adoc", + "line_number": 151, + "line_text": "`mstatus` field FS is hardwired to 0 if the Zfinx extension is", + "context": " 149| [[norm:Zfinx_mstatus-FS_zero]]\n 150| In the standard privileged architecture defined in Volume II, the\n>>> 151| `mstatus` field FS is hardwired to 0 if the Zfinx extension is\n 152| implemented, and FS no longer affects the trapping behavior of\n 153| floating-point instructions or `fcsr` accesses." + } + ] + }, + { + "parameter_name": "HW_MSTATUS_VS_DIRTY_UPDATE", + "classification": "SW_RULE", + "value_type": "enum", + "num_candidates": 10, + "best_score": 27, + "candidates": [ + { + "score": 27, + "reasons": [ + "Name segment 'DIRTY'", + "Description keyword 'mstatus'", + "Description keyword 'mstatus.VS'", + "CSR field name 'SD'", + "Name segment 'MSTATUS'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 107, + "line_text": "If `mstatus.VS` is Dirty, `mstatus.SD` is 1;", + "context": " 105| \n 106| [[norm:mstatus-sd_op]]\n>>> 107| If `mstatus.VS` is Dirty, `mstatus.SD` is 1;\n 108| otherwise, `mstatus.SD` is set in accordance with existing specifications.\n 109| " + }, + { + "score": 27, + "reasons": [ + "Name segment 'DIRTY'", + "Description keyword 'mstatus'", + "Description keyword 'mstatus.VS'", + "CSR field name 'SD'", + "Name segment 'MSTATUS'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 141, + "line_text": "If `mstatus.VS` is Dirty, `mstatus.SD` is 1;", + "context": " 139| \n 140| [[norm:mstatus-sd_op_vs]]\n>>> 141| If `mstatus.VS` is Dirty, `mstatus.SD` is 1;\n 142| otherwise, `mstatus.SD` is set in accordance with existing specifications.\n 143| " + }, + { + "score": 26, + "reasons": [ + "Description keyword 'mstatus'", + "Name segment 'MSTATUS'", + "Description keyword 'mstatus.VS'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 130, + "line_text": "[#norm:vsstatus-vs_mstatus-vs_op_active]#When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing", + "context": " 128| illegal-instruction exception when either field is set to Off.\n 129| \n>>> 130| [#norm:vsstatus-vs_mstatus-vs_op_active]#When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing\n 131| any instruction that changes vector state, including the vector CSRs, will\n 132| change both `mstatus.VS` and `vsstatus.VS` to Dirty.#" + }, + { + "score": 26, + "reasons": [ + "Description keyword 'mstatus'", + "Name segment 'MSTATUS'", + "Description keyword 'mstatus.VS'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 133, + "line_text": "[#norm:hw_mstatus_vs_dirty_update_param]#Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or", + "context": " 131| any instruction that changes vector state, including the vector CSRs, will\n 132| change both `mstatus.VS` and `vsstatus.VS` to Dirty.#\n>>> 133| [#norm:hw_mstatus_vs_dirty_update_param]#Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or\n 134| Clean to Dirty at any time, even when there is no change in vector state.#\n 135| " + }, + { + "score": 25, + "reasons": [ + "Name segment 'DIRTY'", + "Description keyword 'mstatus'", + "Description keyword 'mstatus.VS'", + "Name segment 'MSTATUS'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 99, + "line_text": "change `mstatus.VS` to Dirty.", + "context": " 97| When `mstatus.VS` is set to Initial or Clean, executing any\n 98| instruction that changes vector state, including the vector CSRs, will\n>>> 99| change `mstatus.VS` to Dirty.\n 100| Implementations may also change `mstatus.VS` from Initial or Clean to Dirty\n 101| at any time, even when there is no change in vector state." + } + ] + }, + { + "parameter_name": "IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "WARL + CSR 'vsatp'", + "Name segment 'VSATP'", + "CSR name 'vsatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1416, + "line_text": "ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in", + "context": " 1414| \n 1415| [#norm:vsatp_mode_unsupported_v0]#When V=0, a write to `vsatp` with an unsupported MODE value is either\n>>> 1416| ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in\n 1417| the normal way.# [#norm:vsatp_mode_unsupported_v1]#However, when V=1, a write to `satp` with an unsupported\n 1418| MODE value _is_ ignored and no write to `vsatp` is effected.#" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'VSATP'", + "CSR name 'vsatp' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1415, + "line_text": "[#norm:vsatp_mode_unsupported_v0]#When V=0, a write to `vsatp` with an unsupported MODE value is either", + "context": " 1413| ====\n 1414| \n>>> 1415| [#norm:vsatp_mode_unsupported_v0]#When V=0, a write to `vsatp` with an unsupported MODE value is either\n 1416| ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in\n 1417| the normal way.# [#norm:vsatp_mode_unsupported_v1]#However, when V=1, a write to `satp` with an unsupported" + }, + { + "score": 6, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'VSATP'", + "CSR name 'vsatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1418, + "line_text": "MODE value _is_ ignored and no write to `vsatp` is effected.#", + "context": " 1416| ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in\n 1417| the normal way.# [#norm:vsatp_mode_unsupported_v1]#However, when V=1, a write to `satp` with an unsupported\n>>> 1418| MODE value _is_ ignored and no write to `vsatp` is effected.#\n 1419| \n 1420| [[norm:vsatp_v0]]" + }, + { + "score": 6, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'VSATP'", + "CSR name 'vsatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2800, + "line_text": "`hgatp`.MODE and `vsatp`.MODE fields are reset to 0. If the Smrnmi", + "context": " 2798| the platform mandates a different reset value for some PMP registers’ A\n 2799| and L fields. If the hypervisor extension is implemented, the\n>>> 2800| `hgatp`.MODE and `vsatp`.MODE fields are reset to 0. If the Smrnmi\n 2801| extension is implemented, the `mnstatus`.NMIE field is reset to 0. No\n 2802| *WARL* field contains an illegal value. If the Zicfilp extension is" + }, + { + "score": 6, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'VSATP'", + "CSR name 'vsatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2340, + "line_text": "Second, if `vsatp`.MODE is not equal to zero, non-zero VS-stage PTE PBMT", + "context": " 2338| override the attributes in the PMA to produce an intermediate set of\n 2339| attributes. Otherwise, the PMAs serve as the intermediate attributes.\n>>> 2340| Second, if `vsatp`.MODE is not equal to zero, non-zero VS-stage PTE PBMT\n 2341| bits override the intermediate attributes to produce the final set of\n 2342| attributes used by accesses to the page in question. Otherwise, the" + } + ] + }, + { + "parameter_name": "IMP_ID_VALUE", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "CSR field name 'Implementation'", + "CSR name 'mimpid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 335, + "line_text": "==== Machine Implementation ID (`mimpid`) Register", + "context": " 333| ====\n 334| \n>>> 335| ==== Machine Implementation ID (`mimpid`) Register\n 336| \n 337| [#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the" + }, + { + "score": 5, + "reasons": ["CSR name 'mimpid' in backticks"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 337, + "line_text": "[#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the", + "context": " 335| ==== Machine Implementation ID (`mimpid`) Register\n 336| \n>>> 337| [#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the\n 338| processor implementation.#\n 339| [#norm:mimpid_always_rd]#This register must be readable in any" + }, + { + "score": 5, + "reasons": [ + "CSR field name 'Implementation'", + "CSR name 'mimpid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 343, + "line_text": ".Machine Implementation ID (`mimpid`) register", + "context": " 341| The Implementation value should reflect the design of the RISC-V processor itself and not any surrounding system.\n 342| \n>>> 343| .Machine Implementation ID (`mimpid`) register\n 344| include::images/bytefield/mimpid.edn[]\n 345| " + }, + { + "score": 4, + "reasons": ["CSR field name 'Implementation'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 245, + "line_text": "implementation-specific, bounded time limit.# [#norm:vtw_virtinstr_param]#An implementation may have", + "context": " 243| an attempt in VS-mode to execute WFI raises a virtual-instruction\n 244| exception if the WFI does not complete within an\n>>> 245| implementation-specific, bounded time limit.# [#norm:vtw_virtinstr_param]#An implementation may have\n 246| WFI always raise a virtual-instruction exception in VS-mode when VTW=1\n 247| (and `mstatus`.TW=0), even if there are pending globally-disabled" + }, + { + "score": 4, + "reasons": ["CSR field name 'Implementation'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 22, + "line_text": "[#norm:misa_always_rd]#This register must be readable in any implementation#,", + "context": " 20| \n 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n>>> 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism.\n 24| " + } + ] + }, + { + "parameter_name": "JVT_BASE_MASK", + "classification": "NORM_CSR_WARL", + "value_type": "range", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 466, + "line_text": "instructions. [#norm:Zca_offsets_mul2]#As with base RVI instructions, the offsets of all RVC", + "context": " 464| \n 465| RVC provides unconditional jump instructions and conditional branch\n>>> 466| instructions. [#norm:Zca_offsets_mul2]#As with base RVI instructions, the offsets of all RVC\n 467| control transfer instructions are in multiples of 2 bytes.#\n 468| " + }, + { + "score": 8, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 858, + "line_text": "effective address is the base address specified in _rs1_.# [#norm:cbo-clean_offset]#The offset operand may", + "context": " 856| \n 857| [#norm:cbo-clean_op]#A *cbo.clean* instruction performs a clean operation on the cache block whose\n>>> 858| effective address is the base address specified in _rs1_.# [#norm:cbo-clean_offset]#The offset operand may\n 859| be omitted; otherwise, any expression that computes the offset shall evaluate to\n 860| zero.# The instruction operates on the set of coherent caches accessed by the" + }, + { + "score": 8, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 29, + "line_text": "[#norm:misa_mxl_op_isa]#The MXL (Machine XLEN) field encodes the native base integer ISA width as", + "context": " 27| include::images/bytefield/misareg.edn[]\n 28| \n>>> 29| [#norm:misa_mxl_op_isa]#The MXL (Machine XLEN) field encodes the native base integer ISA width as\n 30| shown in <>.#\n 31| [#norm:misa_mxl_acc]#The MXL field is read-only.#" + }, + { + "score": 8, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 69, + "line_text": "[#norm:misa_i_op]#The \"I\" bit will be set for the RV32I and RV64I base ISAs#,", + "context": " 67| extension \"A\" , bit 1 encodes presence of extension \"B\", through to\n 68| bit 25 which encodes \"Z\").#\n>>> 69| [#norm:misa_i_op]#The \"I\" bit will be set for the RV32I and RV64I base ISAs#,\n 70| and [#norm:misa_e_op]#the \"E\" bit will be set for RV32E and RV64E.#\n 71| [#norm:misa_extensions_warl_op]#The Extensions field is a *WARL* field that can contain writable bits where the" + }, + { + "score": 8, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 299, + "line_text": "[#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base", + "context": " 297| ==== Machine Architecture ID (`marchid`) Register\n 298| \n>>> 299| [#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base\n 300| microarchitecture of the hart.#\n 301| [#norm:marchid_always_rd]#This register must be readable in any" + } + ] + }, + { + "parameter_name": "JVT_BASE_TYPE", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 466, + "line_text": "instructions. [#norm:Zca_offsets_mul2]#As with base RVI instructions, the offsets of all RVC", + "context": " 464| \n 465| RVC provides unconditional jump instructions and conditional branch\n>>> 466| instructions. [#norm:Zca_offsets_mul2]#As with base RVI instructions, the offsets of all RVC\n 467| control transfer instructions are in multiples of 2 bytes.#\n 468| " + }, + { + "score": 10, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 858, + "line_text": "effective address is the base address specified in _rs1_.# [#norm:cbo-clean_offset]#The offset operand may", + "context": " 856| \n 857| [#norm:cbo-clean_op]#A *cbo.clean* instruction performs a clean operation on the cache block whose\n>>> 858| effective address is the base address specified in _rs1_.# [#norm:cbo-clean_offset]#The offset operand may\n 859| be omitted; otherwise, any expression that computes the offset shall evaluate to\n 860| zero.# The instruction operates on the set of coherent caches accessed by the" + }, + { + "score": 10, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 29, + "line_text": "[#norm:misa_mxl_op_isa]#The MXL (Machine XLEN) field encodes the native base integer ISA width as", + "context": " 27| include::images/bytefield/misareg.edn[]\n 28| \n>>> 29| [#norm:misa_mxl_op_isa]#The MXL (Machine XLEN) field encodes the native base integer ISA width as\n 30| shown in <>.#\n 31| [#norm:misa_mxl_acc]#The MXL field is read-only.#" + }, + { + "score": 10, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 69, + "line_text": "[#norm:misa_i_op]#The \"I\" bit will be set for the RV32I and RV64I base ISAs#,", + "context": " 67| extension \"A\" , bit 1 encodes presence of extension \"B\", through to\n 68| bit 25 which encodes \"Z\").#\n>>> 69| [#norm:misa_i_op]#The \"I\" bit will be set for the RV32I and RV64I base ISAs#,\n 70| and [#norm:misa_e_op]#the \"E\" bit will be set for RV32E and RV64E.#\n 71| [#norm:misa_extensions_warl_op]#The Extensions field is a *WARL* field that can contain writable bits where the" + }, + { + "score": 10, + "reasons": ["CSR field name 'BASE'", "Description keyword 'BASE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 299, + "line_text": "[#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base", + "context": " 297| ==== Machine Architecture ID (`marchid`) Register\n 298| \n>>> 299| [#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base\n 300| microarchitecture of the hart.#\n 301| [#norm:marchid_always_rd]#This register must be readable in any" + } + ] + }, + { + "parameter_name": "JVT_READ_ONLY", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": ["CSR field name 'BASE'", "Description keyword 'JVT'"], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2341, + "line_text": "[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#", + "context": " 2339| ==== jvt\n 2340| \n>>> 2341| [#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#\n 2342| \n 2343| If the same function is called with and without linking then it must have two entries in the table." + }, + { + "score": 6, + "reasons": ["CSR field name 'BASE'", "CSR field name 'MODE'"], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2399, + "line_text": "[#norm:jvt_reg]#The _jvt_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).#", + "context": " 2397| Description::\n 2398| \n>>> 2399| [#norm:jvt_reg]#The _jvt_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).#\n 2400| \n 2401| [#norm:jvt_op]#If <> is implemented then _jvt_ must also be implemented, but can contain a read-only value. If _jvt_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary." + }, + { + "score": 5, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 5, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + }, + { + "score": 5, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 577, + "line_text": "[#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "context": " 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n>>> 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.\n 578| Otherwise, it is a *WARL* field that encodes the current value of SXLEN.#\n 579| In particular, [#norm:mstatus_sxl_rdonly_mxlen64]#an implementation may make SXL be a read-only field whose" + } + ] + }, + { + "parameter_name": "LRSC_FAIL_ON_NON_EXACT_LRSC", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Name segment 'FAIL'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 169, + "line_text": "The SC must fail if the address is not within the reservation set of the", + "context": " 167| ====\n 168| \n>>> 169| The SC must fail if the address is not within the reservation set of the\n 170| most recent LR in program order. The SC must fail if a store to the\n 171| reservation set from another hart can be observed to occur between the" + }, + { + "score": 3, + "reasons": ["Name segment 'FAIL'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 170, + "line_text": "most recent LR in program order. The SC must fail if a store to the", + "context": " 168| \n 169| The SC must fail if the address is not within the reservation set of the\n>>> 170| most recent LR in program order. The SC must fail if a store to the\n 171| reservation set from another hart can be observed to occur between the\n 172| LR and SC. The SC must fail if a write from some other device to the" + }, + { + "score": 3, + "reasons": ["Name segment 'FAIL'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 172, + "line_text": "LR and SC. The SC must fail if a write from some other device to the", + "context": " 170| most recent LR in program order. The SC must fail if a store to the\n 171| reservation set from another hart can be observed to occur between the\n>>> 172| LR and SC. The SC must fail if a write from some other device to the\n 173| bytes accessed by the LR can be observed to occur between the LR and SC.\n 174| (If such a device writes the reservation set but does not write the" + }, + { + "score": 3, + "reasons": ["Name segment 'FAIL'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 175, + "line_text": "bytes accessed by the LR, the SC may or may not fail.) An SC must fail", + "context": " 173| bytes accessed by the LR can be observed to occur between the LR and SC.\n 174| (If such a device writes the reservation set but does not write the\n>>> 175| bytes accessed by the LR, the SC may or may not fail.) An SC must fail\n 176| if there is another SC (to any address) between the LR and the SC in\n 177| program order. The precise statement of the atomicity requirements for" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + } + ] + }, + { + "parameter_name": "LRSC_FAIL_ON_VA_SYNONYM", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": [ + "Description keyword 'LR'", + "Description keyword 'SC'", + "Description keyword 'lr.d'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 76, + "line_text": "SC.W instruction invalidates any reservation held by this hart. LR.D and", + "context": " 74| treated like a store.\n 75| Regardless of success or failure, executing an\n>>> 76| SC.W instruction invalidates any reservation held by this hart. LR.D and\n 77| SC.D act analogously on doublewords and are only available on RV64. For\n 78| RV64, LR.W and SC.W sign-extend the value placed in _rd_." + }, + { + "score": 5, + "reasons": ["Description keyword 'sc.d'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 77, + "line_text": "SC.D act analogously on doublewords and are only available on RV64. For", + "context": " 75| Regardless of success or failure, executing an\n 76| SC.W instruction invalidates any reservation held by this hart. LR.D and\n>>> 77| SC.D act analogously on doublewords and are only available on RV64. For\n 78| RV64, LR.W and SC.W sign-extend the value placed in _rd_.\n 79| " + }, + { + "score": 5, + "reasons": [ + "Description keyword 'LR'", + "Name segment 'FAIL'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 170, + "line_text": "most recent LR in program order. The SC must fail if a store to the", + "context": " 168| \n 169| The SC must fail if the address is not within the reservation set of the\n>>> 170| most recent LR in program order. The SC must fail if a store to the\n 171| reservation set from another hart can be observed to occur between the\n 172| LR and SC. The SC must fail if a write from some other device to the" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'LR'", + "Name segment 'FAIL'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 172, + "line_text": "LR and SC. The SC must fail if a write from some other device to the", + "context": " 170| most recent LR in program order. The SC must fail if a store to the\n 171| reservation set from another hart can be observed to occur between the\n>>> 172| LR and SC. The SC must fail if a write from some other device to the\n 173| bytes accessed by the LR can be observed to occur between the LR and SC.\n 174| (If such a device writes the reservation set but does not write the" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'LR'", + "Name segment 'FAIL'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 175, + "line_text": "bytes accessed by the LR, the SC may or may not fail.) An SC must fail", + "context": " 173| bytes accessed by the LR can be observed to occur between the LR and SC.\n 174| (If such a device writes the reservation set but does not write the\n>>> 175| bytes accessed by the LR, the SC may or may not fail.) An SC must fail\n 176| if there is another SC (to any address) between the LR and the SC in\n 177| program order. The precise statement of the atomicity requirements for" + } + ] + }, + { + "parameter_name": "LRSC_MISALIGNED_BEHAVIOR", + "classification": "NORM_DIRECT", + "value_type": "enum", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": ["Description keyword 'LR'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 59, + "line_text": "are performed with the load-reserved (LR) and store-conditional (SC)", + "context": " 57| \n 58| Complex atomic memory operations on a single memory word or doubleword\n>>> 59| are performed with the load-reserved (LR) and store-conditional (SC)\n 60| instructions. LR.W loads a word from the address in _rs1_, places the\n 61| sign-extended value in _rd_, and registers a _reservation set_—a set of" + }, + { + "score": 12, + "reasons": ["Description keyword 'LR'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 76, + "line_text": "SC.W instruction invalidates any reservation held by this hart. LR.D and", + "context": " 74| treated like a store.\n 75| Regardless of success or failure, executing an\n>>> 76| SC.W instruction invalidates any reservation held by this hart. LR.D and\n 77| SC.D act analogously on doublewords and are only available on RV64. For\n 78| RV64, LR.W and SC.W sign-extend the value placed in _rd_." + }, + { + "score": 12, + "reasons": ["Description keyword 'LR'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 78, + "line_text": "RV64, LR.W and SC.W sign-extend the value placed in _rd_.", + "context": " 76| SC.W instruction invalidates any reservation held by this hart. LR.D and\n 77| SC.D act analogously on doublewords and are only available on RV64. For\n>>> 78| RV64, LR.W and SC.W sign-extend the value placed in _rd_.\n 79| \n 80| [NOTE]" + }, + { + "score": 12, + "reasons": ["Description keyword 'LR'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 126, + "line_text": "For LR and SC, the Zalrsc extension requires that the address held in _rs1_", + "context": " 124| ====\n 125| \n>>> 126| For LR and SC, the Zalrsc extension requires that the address held in _rs1_\n 127| be naturally aligned to the size of the operand (i.e., eight-byte\n 128| aligned for _doublewords_ and four-byte aligned for _words_). If the" + }, + { + "score": 12, + "reasons": ["Description keyword 'LR'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 146, + "line_text": "recent LR in program order. An SC may succeed only if no store from", + "context": " 144| each LR, provided the reservation set includes all bytes of the\n 145| addressed data word or doubleword. An SC can only pair with the most\n>>> 146| recent LR in program order. An SC may succeed only if no store from\n 147| another hart to the reservation set can be observed to have occurred\n 148| between the LR and the SC, and if there is no other SC between the LR" + } + ] + }, + { + "parameter_name": "LRSC_RESERVATION_STRATEGY", + "classification": "NORM_DIRECT", + "value_type": "enum", + "num_candidates": 10, + "best_score": 19, + "candidates": [ + { + "score": 19, + "reasons": [ + "Description keyword 'LR'", + "Description keyword 'reservation'", + "Name segment 'RESERVATION'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 76, + "line_text": "SC.W instruction invalidates any reservation held by this hart. LR.D and", + "context": " 74| treated like a store.\n 75| Regardless of success or failure, executing an\n>>> 76| SC.W instruction invalidates any reservation held by this hart. LR.D and\n 77| SC.D act analogously on doublewords and are only available on RV64. For\n 78| RV64, LR.W and SC.W sign-extend the value placed in _rd_." + }, + { + "score": 19, + "reasons": [ + "Description keyword 'LR'", + "Description keyword 'reservation'", + "Name segment 'RESERVATION'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 316, + "line_text": "the reservation set of the LR instruction in _H_'s constrained LR/SC", + "context": " 314| of the LR instruction in _H_'s constrained LR/SC loops.\n 315| * Some other hart executes an unconditional store or AMO instruction to\n>>> 316| the reservation set of the LR instruction in _H_'s constrained LR/SC\n 317| loop, or some other device in the system writes to that reservation set.\n 318| * _H_ executes a branch or jump that exits the constrained LR/SC loop." + }, + { + "score": 19, + "reasons": [ + "Description keyword 'LR'", + "Description keyword 'reservation'", + "Name segment 'RESERVATION'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 418, + "line_text": "* Constrained the LR/SC reservation set size and shape when using", + "context": " 416| specification implied that PPO rules other than fences and\n 417| acquire/release annotations did not apply.\n>>> 418| * Constrained the LR/SC reservation set size and shape when using\n 419| page-based virtual memory.\n 420| * PMP changes require an SFENCE.VMA on any hart that implements" + }, + { + "score": 19, + "reasons": [ + "Description keyword 'LR'", + "Description keyword 'reservation'", + "Name segment 'RESERVATION'", + "Description keyword 'SC'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 1714, + "line_text": "standard extension, the LR/SC reservation set must lie completely within", + "context": " 1712| \n 1713| For implementations with both page-based virtual memory and the \"A\"\n>>> 1714| standard extension, the LR/SC reservation set must lie completely within\n 1715| a single base physical page (i.e., a naturally aligned 4 KiB physical-memory\n 1716| region)." + }, + { + "score": 16, + "reasons": ["Description keyword 'LR'", "Description keyword 'SC'"], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 59, + "line_text": "are performed with the load-reserved (LR) and store-conditional (SC)", + "context": " 57| \n 58| Complex atomic memory operations on a single memory word or doubleword\n>>> 59| are performed with the load-reserved (LR) and store-conditional (SC)\n 60| instructions. LR.W loads a word from the address in _rs1_, places the\n 61| sign-extended value in _rd_, and registers a _reservation set_—a set of" + } + ] + }, + { + "parameter_name": "MARCHID_IMPLEMENTED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Description keyword 'implemented'", + "Name segment 'MARCHID'", + "Name segment 'IMPLEMENTED'", + "Description keyword 'marchid'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 303, + "line_text": "The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.", + "context": " 301| [#norm:marchid_always_rd]#This register must be readable in any\n 302| implementation, but a value of 0 can be returned to indicate the field is not implemented.#\n>>> 303| The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.\n 304| \n 305| .Machine Architecture ID (`marchid`) register" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MARCHID'", + "Description keyword 'marchid'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 299, + "line_text": "[#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base", + "context": " 297| ==== Machine Architecture ID (`marchid`) Register\n 298| \n>>> 299| [#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base\n 300| microarchitecture of the hart.#\n 301| [#norm:marchid_always_rd]#This register must be readable in any" + }, + { + "score": 7, + "reasons": [ + "Name segment 'MARCHID'", + "Description keyword 'marchid'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 297, + "line_text": "==== Machine Architecture ID (`marchid`) Register", + "context": " 295| ====\n 296| \n>>> 297| ==== Machine Architecture ID (`marchid`) Register\n 298| \n 299| [#norm:marchid_sz_acc_op]#The `marchid` CSR is an MXLEN-bit read-only register encoding the base" + }, + { + "score": 7, + "reasons": [ + "Name segment 'MARCHID'", + "Description keyword 'marchid'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 305, + "line_text": ".Machine Architecture ID (`marchid`) register", + "context": " 303| The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.\n 304| \n>>> 305| .Machine Architecture ID (`marchid`) register\n 306| include::images/bytefield/marchid.edn[]\n 307| " + }, + { + "score": 7, + "reasons": [ + "Name segment 'MARCHID'", + "Description keyword 'marchid'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 306, + "line_text": "include::images/bytefield/marchid.edn[]", + "context": " 304| \n 305| .Machine Architecture ID (`marchid`) register\n>>> 306| include::images/bytefield/marchid.edn[]\n 307| \n 308| Open-source project architecture IDs are allocated globally by RISC-V" + } + ] + }, + { + "parameter_name": "MCID_WIDTH", + "classification": "NORM_CSR_WARL", + "value_type": "range", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'MCID'", + "CSR name 'srmcfg' in backticks", + "Description keyword 'MCID'", + "Name segment 'MCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2586, + "line_text": "The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege", + "context": " 2584| ....\n 2585| \n>>> 2586| The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege\n 2587| modes of software execution on that hart by default, but this behavior may be\n 2588| overridden by future extensions." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'ID'", + "CSR field name 'MCID'", + "Description keyword 'MCID'", + "Name segment 'MCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2531, + "line_text": "Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). These identifiers", + "context": " 2529| To facilitate this, the QoS Identifiers extension (Ssqosid) introduces the\n 2530| `srmcfg` register, which configures a hart with two identifiers: a Resource\n>>> 2531| Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). These identifiers\n 2532| accompany each request issued by the hart to shared resource controllers.\n 2533| " + }, + { + "score": 7, + "reasons": [ + "Description keyword 'ID'", + "CSR field name 'MCID'", + "Description keyword 'MCID'", + "Name segment 'MCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2551, + "line_text": "Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). Both `RCID`", + "context": " 2549| \n 2550| The `srmcfg` register is an SXLEN-bit read/write register used to configure a\n>>> 2551| Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). Both `RCID`\n 2552| and `MCID` are WARL fields. The register is formatted as shown in <>\n 2553| when SXLEN=64 and <> when SXLEN=32." + }, + { + "score": 5, + "reasons": [ + "CSR field name 'MCID'", + "Description keyword 'MCID'", + "Name segment 'MCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2535, + "line_text": "originating supervisor domain, can accompany `RCID` and `MCID`. Resource", + "context": " 2533| \n 2534| Additional metadata, like the nature of the memory access and the ID of the\n>>> 2535| originating supervisor domain, can accompany `RCID` and `MCID`. Resource\n 2536| controllers may use this metadata for differentiated service such as a different\n 2537| capacity allocation for code storage vs. data storage. Resource controllers can" + }, + { + "score": 5, + "reasons": [ + "CSR field name 'MCID'", + "Description keyword 'MCID'", + "Name segment 'MCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2544, + "line_text": "resource allocations, while the `MCID` is used for tracking resource usage.", + "context": " 2542| QoS Register Interface (CBQRI) specification, which provides methods for setting\n 2543| resource usage limits and monitoring resource consumption. The `RCID` controls\n>>> 2544| resource allocations, while the `MCID` is used for tracking resource usage.\n 2545| \n 2546| NOTE: The Ssqosid extension does not require that S-mode mode be implemented." + } + ] + }, + { + "parameter_name": "MCONTEXT_AVAILABLE", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": [ + "Description keyword 'MCONTEXT'", + "Name segment 'MCONTEXT'", + "CSR name 'mcontext' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 1019, + "line_text": "`mcontext`", + "context": " 1017| `tdata2` +\n 1018| `tdata3` +\n>>> 1019| `mcontext`\n 1020| \n 1021| |Debug/Trace trigger register select. +" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 231, + "line_text": "[#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the", + "context": " 229| \n 230| [#norm:misa_e_acc]#The \"E\" bit is read-only.#\n>>> 231| [#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the\n 232| \"E\" bit always reads as the complement of the \"I\" bit.#\n 233| If an execution environment supports both RV32E and RV32I, software can select" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + } + ] + }, + { + "parameter_name": "MCOUNTENABLE_EN", + "classification": "NORM_CSR_RW", + "value_type": "bitmask", + "num_candidates": 10, + "best_score": 13, + "candidates": [ + { + "score": 13, + "reasons": [ + "Description keyword 'mcounteren'", + "CSR name 'mcounteren' in backticks", + "WARL + CSR 'mcounteren'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1656, + "line_text": "[#norm:mcounteren_flds_mandatory_warl]#In harts with U-mode, the `mcounteren` must be", + "context": " 1654| ====\n 1655| \n>>> 1656| [#norm:mcounteren_flds_mandatory_warl]#In harts with U-mode, the `mcounteren` must be\n 1657| implemented, but all fields are *WARL*# and\n 1658| [#norm:mcounteren_flds_rdonly0]#may be read-only zero, indicating reads to the" + }, + { + "score": 12, + "reasons": [ + "Description keyword 'mcounteren'", + "CSR field name 'IR'", + "CSR name 'mcounteren' in backticks", + "CSR field name 'CY'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1615, + "line_text": "[#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is", + "context": " 1613| counters, which continue to increment even when not accessible.#\n 1614| \n>>> 1615| [#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is\n 1616| clear, attempts to read the `cycle`, `time`, `instret`, or\n 1617| `hpmcountern` register while executing in S-mode or U-mode will cause an" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mcounteren'", + "CSR name 'mcounteren' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1603, + "line_text": "[#norm:mcounteren_sz]#The counter-enable `mcounteren` register is a 32-bit register# that", + "context": " 1601| ==== Machine Counter-Enable (`mcounteren`) Register\n 1602| \n>>> 1603| [#norm:mcounteren_sz]#The counter-enable `mcounteren` register is a 32-bit register# that\n 1604| [#norm:mcounteren_op]#controls the availability of the hardware performance-monitoring\n 1605| counters to the next-lower privileged mode.#" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mcounteren'", + "CSR name 'mcounteren' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1633, + "line_text": "In addition, [#norm:mcounteren_tm_clr]#when the TM bit in the `mcounteren` register is clear, attempts to", + "context": " 1631| ====\n 1632| \n>>> 1633| In addition, [#norm:mcounteren_tm_clr]#when the TM bit in the `mcounteren` register is clear, attempts to\n 1634| access the `stimecmp` or `vstimecmp` register while executing in a mode less\n 1635| privileged than M will cause an illegal-instruction exception.#" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mcounteren'", + "CSR name 'mcounteren' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1661, + "line_text": "[#norm:mcounteren_presence]#In harts without U-mode, the `mcounteren` register should not exist.#", + "context": " 1659| corresponding counter will cause an illegal-instruction exception when\n 1660| executing in a less-privileged mode.#\n>>> 1661| [#norm:mcounteren_presence]#In harts without U-mode, the `mcounteren` register should not exist.#\n 1662| \n 1663| ==== Machine Counter-Inhibit (`mcountinhibit`) Register" + } + ] + }, + { + "parameter_name": "MIMPID_IMPLEMENTED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": ["Description keyword 'mimpid'", "Name segment 'MIMPID'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 337, + "line_text": "[#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the", + "context": " 335| ==== Machine Implementation ID (`mimpid`) Register\n 336| \n>>> 337| [#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the\n 338| processor implementation.#\n 339| [#norm:mimpid_always_rd]#This register must be readable in any" + }, + { + "score": 7, + "reasons": ["Description keyword 'mimpid'", "Name segment 'MIMPID'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 335, + "line_text": "==== Machine Implementation ID (`mimpid`) Register", + "context": " 333| ====\n 334| \n>>> 335| ==== Machine Implementation ID (`mimpid`) Register\n 336| \n 337| [#norm:mimpid_op]#The `mimpid` CSR provides a unique encoding of the version of the" + }, + { + "score": 7, + "reasons": ["Description keyword 'mimpid'", "Name segment 'MIMPID'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 343, + "line_text": ".Machine Implementation ID (`mimpid`) register", + "context": " 341| The Implementation value should reflect the design of the RISC-V processor itself and not any surrounding system.\n 342| \n>>> 343| .Machine Implementation ID (`mimpid`) register\n 344| include::images/bytefield/mimpid.edn[]\n 345| " + }, + { + "score": 7, + "reasons": ["Description keyword 'mimpid'", "Name segment 'MIMPID'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 344, + "line_text": "include::images/bytefield/mimpid.edn[]", + "context": " 342| \n 343| .Machine Implementation ID (`mimpid`) register\n>>> 344| include::images/bytefield/mimpid.edn[]\n 345| \n 346| [NOTE]" + }, + { + "score": 7, + "reasons": ["Description keyword 'mimpid'", "Name segment 'MIMPID'"], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 651, + "line_text": "`mimpid` +", + "context": " 649| |`mvendorid` +\n 650| `marchid` +\n>>> 651| `mimpid` +\n 652| `mhartid` +\n 653| `mconfigptr`" + } + ] + }, + { + "parameter_name": "MISALIGNED_AMO", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1976, + "line_text": "[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or", + "context": " 1974| raised.\n 1975| \n>>> 1976| [#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or\n 1977| lower priority than load/store/AMO page-fault and access-fault exceptions.#\n 1978| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 139, + "line_text": "[#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch", + "context": " 137| (R/I/S/U), as shown in <>. All are a fixed 32 bits in length.\n 138| The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.\n>>> 139| [#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch\n 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 142, + "line_text": "[#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated", + "context": " 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#\n>>> 142| [#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated\n 143| for a conditional branch that is not taken.#\n 144| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 739, + "line_text": "[#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or", + "context": " 737| supported, and so the software running inside the execution environment\n 738| will never experience a contained or fatal address-misaligned trap. In this case, the\n>>> 739| [#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or\n 740| [#norm:MISALIGNED_LDST_INVISIBLE_TRAP]#via an invisible trap into the execution environment implementation#, or possibly a\n 741| [#norm:MISALIGNED_LDST_HW_OR_INVISIBLE_TRAP_FUNC_OF_ADDR]#combination of hardware and invisible trap depending on address.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + } + ] + }, + { + "parameter_name": "MISALIGNED_LDST", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1976, + "line_text": "[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or", + "context": " 1974| raised.\n 1975| \n>>> 1976| [#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or\n 1977| lower priority than load/store/AMO page-fault and access-fault exceptions.#\n 1978| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 139, + "line_text": "[#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch", + "context": " 137| (R/I/S/U), as shown in <>. All are a fixed 32 bits in length.\n 138| The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.\n>>> 139| [#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch\n 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 142, + "line_text": "[#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated", + "context": " 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#\n>>> 142| [#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated\n 143| for a conditional branch that is not taken.#\n 144| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 739, + "line_text": "[#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or", + "context": " 737| supported, and so the software running inside the execution environment\n 738| will never experience a contained or fatal address-misaligned trap. In this case, the\n>>> 739| [#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or\n 740| [#norm:MISALIGNED_LDST_INVISIBLE_TRAP]#via an invisible trap into the execution environment implementation#, or possibly a\n 741| [#norm:MISALIGNED_LDST_HW_OR_INVISIBLE_TRAP_FUNC_OF_ADDR]#combination of hardware and invisible trap depending on address.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + } + ] + }, + { + "parameter_name": "MISALIGNED_LDST_EXCEPTION_PRIORITY", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'EXCEPTION'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 139, + "line_text": "[#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch", + "context": " 137| (R/I/S/U), as shown in <>. All are a fixed 32 bits in length.\n 138| The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.\n>>> 139| [#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch\n 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#" + }, + { + "score": 6, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'EXCEPTION'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 142, + "line_text": "[#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated", + "context": " 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#\n>>> 142| [#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated\n 143| for a conditional branch that is not taken.#\n 144| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1976, + "line_text": "[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or", + "context": " 1974| raised.\n 1975| \n>>> 1976| [#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or\n 1977| lower priority than load/store/AMO page-fault and access-fault exceptions.#\n 1978| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 739, + "line_text": "[#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or", + "context": " 737| supported, and so the software running inside the execution environment\n 738| will never experience a contained or fatal address-misaligned trap. In this case, the\n>>> 739| [#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or\n 740| [#norm:MISALIGNED_LDST_INVISIBLE_TRAP]#via an invisible trap into the execution environment implementation#, or possibly a\n 741| [#norm:MISALIGNED_LDST_HW_OR_INVISIBLE_TRAP_FUNC_OF_ADDR]#combination of hardware and invisible trap depending on address.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + } + ] + }, + { + "parameter_name": "MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE", + "classification": "NORM_DIRECT", + "value_type": "enum", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": [ + "Name segment 'ATOMICITY'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'GRANULE'", + "Description keyword 'PMA'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 385, + "line_text": "The misaligned atomicity granule PMA, defined in Volume II of this manual,", + "context": " 383| not be emulated.\n 384| \n>>> 385| The misaligned atomicity granule PMA, defined in Volume II of this manual,\n 386| optionally relaxes this alignment requirement.\n 387| If present, the misaligned atomicity granule PMA specifies the size" + }, + { + "score": 7, + "reasons": [ + "Name segment 'ATOMICITY'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'GRANULE'", + "Description keyword 'PMA'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 387, + "line_text": "If present, the misaligned atomicity granule PMA specifies the size", + "context": " 385| The misaligned atomicity granule PMA, defined in Volume II of this manual,\n 386| optionally relaxes this alignment requirement.\n>>> 387| If present, the misaligned atomicity granule PMA specifies the size\n 388| of a misaligned atomicity granule, a power-of-two number of bytes.\n 389| The misaligned atomicity granule PMA applies only to AMOs, loads and stores" + }, + { + "score": 7, + "reasons": [ + "Name segment 'ATOMICITY'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'GRANULE'", + "Description keyword 'PMA'" + ], + "is_normative": false, + "in_note": false, + "file": "a-st-ext.adoc", + "line_number": 389, + "line_text": "The misaligned atomicity granule PMA applies only to AMOs, loads and stores", + "context": " 387| If present, the misaligned atomicity granule PMA specifies the size\n 388| of a misaligned atomicity granule, a power-of-two number of bytes.\n>>> 389| The misaligned atomicity granule PMA applies only to AMOs, loads and stores\n 390| defined in the base ISAs, and loads and stores of no more than XLEN bits\n 391| defined in the F, D, and Q extensions, and compressed encodings thereof." + }, + { + "score": 7, + "reasons": [ + "Name segment 'ATOMICITY'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'GRANULE'", + "Description keyword 'PMA'" + ], + "is_normative": false, + "in_note": false, + "file": "colophon.adoc", + "line_number": 157, + "line_text": "* The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA.", + "context": " 155| \n 156| * The inclusion of all ratified extensions through February 2025.\n>>> 157| * The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA.\n 158| * The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions.\n 159| * The removal of unratified content, including the sketch of the RV128I base ISA." + }, + { + "score": 7, + "reasons": [ + "Name segment 'ATOMICITY'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'GRANULE'", + "Description keyword 'PMA'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 3084, + "line_text": "==== Misaligned Atomicity Granule PMA", + "context": " 3082| ====\n 3083| \n>>> 3084| ==== Misaligned Atomicity Granule PMA\n 3085| \n 3086| The misaligned atomicity granule PMA provides constrained support for" + } + ] + }, + { + "parameter_name": "MISALIGNED_SPLIT_STRATEGY", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1976, + "line_text": "[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or", + "context": " 1974| raised.\n 1975| \n>>> 1976| [#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or\n 1977| lower priority than load/store/AMO page-fault and access-fault exceptions.#\n 1978| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 139, + "line_text": "[#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch", + "context": " 137| (R/I/S/U), as shown in <>. All are a fixed 32 bits in length.\n 138| The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.\n>>> 139| [#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch\n 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 142, + "line_text": "[#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated", + "context": " 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#\n>>> 142| [#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated\n 143| for a conditional branch that is not taken.#\n 144| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 739, + "line_text": "[#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or", + "context": " 737| supported, and so the software running inside the execution environment\n 738| will never experience a contained or fatal address-misaligned trap. In this case, the\n>>> 739| [#norm:MISALIGNED_LDST_FULLY_HW_SUPPORTED]#misaligned loads and stores can be handled in hardware#, or\n 740| [#norm:MISALIGNED_LDST_INVISIBLE_TRAP]#via an invisible trap into the execution environment implementation#, or possibly a\n 741| [#norm:MISALIGNED_LDST_HW_OR_INVISIBLE_TRAP_FUNC_OF_ADDR]#combination of hardware and invisible trap depending on address.#" + }, + { + "score": 5, + "reasons": [ + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + } + ] + }, + { + "parameter_name": "MISA_CSR_IMPLEMENTED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "Description keyword 'implemented'", + "Name segment 'MISA'", + "Name segment 'IMPLEMENTED'", + "Description keyword 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 23, + "line_text": "but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism.", + "context": " 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n>>> 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism.\n 24| \n 25| [[norm:misa_enc_img]]" + }, + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'MISA'", + "Description keyword 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 231, + "line_text": "[#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the", + "context": " 229| \n 230| [#norm:misa_e_acc]#The \"E\" bit is read-only.#\n>>> 231| [#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the\n 232| \"E\" bit always reads as the complement of the \"I\" bit.#\n 233| If an execution environment supports both RV32E and RV32I, software can select" + }, + { + "score": 10, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'mstatus' in backticks", + "Description keyword 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2791, + "line_text": "supported, the `mstatus`/`mstatush` field MBE is reset to 0. The `misa`", + "context": " 2789| Upon reset, a hart’s privilege mode is set to M. The `mstatus` fields\n 2790| MIE and MPRV are reset to 0. If little-endian memory accesses are\n>>> 2791| supported, the `mstatus`/`mstatush` field MBE is reset to 0. The `misa`\n 2792| register is reset to enable the maximal set of supported extensions,\n 2793| as described in <>. For" + }, + { + "score": 9, + "reasons": ["Name segment 'MISA'", "Description keyword 'misa'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 30, + "line_text": "[#norm:misa-h_op]#The hypervisor extension is enabled by setting bit 7 in the `misa` CSR#,", + "context": " 28| or a minimum of Sv39 for RV64#.\n 29| \n>>> 30| [#norm:misa-h_op]#The hypervisor extension is enabled by setting bit 7 in the `misa` CSR#,\n 31| which corresponds to the letter H. RISC-V harts that implement the\n 32| hypervisor extension are encouraged not to hardwire `misa`[7], so that" + }, + { + "score": 9, + "reasons": ["Name segment 'MISA'", "Description keyword 'misa'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + } + ] + }, + { + "parameter_name": "MSTATEEN_AIA_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 0, + "best_score": 0, + "candidates": [] + }, + { + "parameter_name": "MSTATEEN_CONTEXT_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 652, + "line_text": "[#norm:ccounter_reset]#The CtrCycleCounter is reset on writes to `__x__ctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.#", + "context": " 650| ----\n 651| \n>>> 652| [#norm:ccounter_reset]#The CtrCycleCounter is reset on writes to `__x__ctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.#\n 653| \n 654| [#norm:ccounter_impl]#An implementation that supports cycle counting must implement CCV and all" + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "bfloat16.adoc", + "line_number": 82, + "line_text": "in context, and advise on how they best to fit the functionality.", + "context": " 80| Furthermore, we expect architects to be able to examine our instructions\n 81| for implementation issues, understand how the instructions will be used\n>>> 82| in context, and advise on how they best to fit the functionality.\n 83| \n 84| Digital design engineers & micro-architects::" + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "calling-convention.adoc", + "line_number": 24, + "line_text": "NOTE: This scheme allows system calls that cause context switches to avoid", + "context": " 22| (`v0`-`v31`, `vl`, `vtype`) and `vstart` to become unspecified.\n 23| \n>>> 24| NOTE: This scheme allows system calls that cause context switches to avoid\n 25| saving and later restoring the vector registers.\n 26| " + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1218, + "line_text": "Read-only fields SD and XS summarize the extension context status as it", + "context": " 1216| \n 1217| [[norm:vsstatus-sd_xs_op]]\n>>> 1218| Read-only fields SD and XS summarize the extension context status as it\n 1219| is visible to VS-mode only. For example, the value of the HS-level\n 1220| `sstatus`.FS does not affect `vsstatus`.SD." + }, + { + "score": 3, + "reasons": [ + "Name segment 'CONTEXT'", + "Description keyword 'CONTEXT'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 828, + "line_text": "===== Extension Context Status in `mstatus` Register", + "context": " 826| ====\n 827| \n>>> 828| ===== Extension Context Status in `mstatus` Register\n 829| \n 830| Supporting substantial extensions is one of the primary goals of RISC-V," + } + ] + }, + { + "parameter_name": "MSTATEEN_CSRIND_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 6, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 191, + "line_text": "{bits: 1, name: 'CSRIND'},", + "context": " 189| {bits: 1, name: 'IMSIC'},\n 190| {bits: 1, name: 'AIA'},\n>>> 191| {bits: 1, name: 'CSRIND'},\n 192| {bits: 1, name: 'WPRI'},\n 193| {bits: 1, name: 'ENVCFG'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 211, + "line_text": "{bits: 1, name: 'CSRIND'},", + "context": " 209| {bits: 1, name: 'IMSIC'},\n 210| {bits: 1, name: 'AIA'},\n>>> 211| {bits: 1, name: 'CSRIND'},\n 212| {bits: 1, name: 'WPRI'},\n 213| {bits: 1, name: 'ENVCFG'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 263, + "line_text": "The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`,", + "context": " 261| `senvcfg` CSRs.\n 262| \n>>> 263| The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`,\n 264| `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.\n 265| The CSRIND bit in `hstateen0` controls access to the `siselect` and the" + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 265, + "line_text": "The CSRIND bit in `hstateen0` controls access to the `siselect` and the", + "context": " 263| The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`,\n 264| `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.\n>>> 265| The CSRIND bit in `hstateen0` controls access to the `siselect` and the\n 266| `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind\n 267| extensions." + }, + { + "score": 3, + "reasons": ["Description keyword 'CSRIND'", "Name segment 'CSRIND'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 281, + "line_text": "Ssaia extension and not controlled by either the CSRIND or the IMSIC", + "context": " 279| \n 280| The AIA bit in `mstateen0` controls access to all state introduced by the\n>>> 281| Ssaia extension and not controlled by either the CSRIND or the IMSIC\n 282| bits. The AIA bit in `hstateen0` controls access to all state introduced by the\n 283| Ssaia extension and not controlled by either the CSRIND or the IMSIC" + } + ] + }, + { + "parameter_name": "MSTATEEN_ENVCFG_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 6, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 134, + "line_text": "*__x__*`envcfg.SSE` fields. The conditions are specified as follows:", + "context": " 132| Attempts to access the `ssp` CSR may result in either an illegal-instruction\n 133| exception or a virtual-instruction exception, contingent upon the state of the\n>>> 134| *__x__*`envcfg.SSE` fields. The conditions are specified as follows:\n 135| \n 136| * [#norm:zicfiss_m_menvcfg-sse]#If the privilege mode is less than M and `menvcfg.SSE` is 0, an" + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "riscv-unprivileged.adoc", + "line_number": 47, + "line_text": ":csrname: envcfg", + "context": " 45| :stem: latexmath\n 46| :footnote:\n>>> 47| :csrname: envcfg\n 48| :imagesdir: images\n 49| " + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 193, + "line_text": "{bits: 1, name: 'ENVCFG'},", + "context": " 191| {bits: 1, name: 'CSRIND'},\n 192| {bits: 1, name: 'WPRI'},\n>>> 193| {bits: 1, name: 'ENVCFG'},\n 194| {bits: 1, name: 'SE0'},\n 195| ], config: {bits: 64, lanes: 4, hspace:1024}}" + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 213, + "line_text": "{bits: 1, name: 'ENVCFG'},", + "context": " 211| {bits: 1, name: 'CSRIND'},\n 212| {bits: 1, name: 'WPRI'},\n>>> 213| {bits: 1, name: 'ENVCFG'},\n 214| {bits: 1, name: 'SE0'},\n 215| ], config: {bits: 64, lanes: 4, hspace:1024}}" + }, + { + "score": 3, + "reasons": ["Name segment 'ENVCFG'", "Description keyword 'ENVCFG'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 259, + "line_text": "The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`,", + "context": " 257| `sstateen0` CSR.\n 258| \n>>> 259| The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`,\n 260| and the `senvcfg` CSRs. The ENVCFG bit in `hstateen0` controls access to the\n 261| `senvcfg` CSRs." + } + ] + }, + { + "parameter_name": "MSTATEEN_IMSIC_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 7, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 189, + "line_text": "{bits: 1, name: 'IMSIC'},", + "context": " 187| {bits: 1, name: 'P1P13'},\n 188| {bits: 1, name: 'CONTEXT'},\n>>> 189| {bits: 1, name: 'IMSIC'},\n 190| {bits: 1, name: 'AIA'},\n 191| {bits: 1, name: 'CSRIND'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 209, + "line_text": "{bits: 1, name: 'IMSIC'},", + "context": " 207| {bits: 2, name: 'WPRI'},\n 208| {bits: 1, name: 'CONTEXT'},\n>>> 209| {bits: 1, name: 'IMSIC'},\n 210| {bits: 1, name: 'AIA'},\n 211| {bits: 1, name: 'CSRIND'}," + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 269, + "line_text": "The IMSIC bit in `mstateen0` controls access to the IMSIC state, including", + "context": " 267| extensions.\n 268| \n>>> 269| The IMSIC bit in `mstateen0` controls access to the IMSIC state, including\n 270| CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in\n 271| `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`" + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 270, + "line_text": "CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in", + "context": " 268| \n 269| The IMSIC bit in `mstateen0` controls access to the IMSIC state, including\n>>> 270| CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in\n 271| `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`\n 272| (really `vstopei`), provided by the Ssaia extension." + }, + { + "score": 3, + "reasons": ["Description keyword 'IMSIC'", "Name segment 'IMSIC'"], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 271, + "line_text": "`hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`", + "context": " 269| The IMSIC bit in `mstateen0` controls access to the IMSIC state, including\n 270| CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in\n>>> 271| `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei`\n 272| (really `vstopei`), provided by the Ssaia extension.\n 273| " + } + ] + }, + { + "parameter_name": "MSTATEEN_JVT_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 1, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Description keyword 'JVT'"], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2341, + "line_text": "[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#", + "context": " 2339| ==== jvt\n 2340| \n>>> 2341| [#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#\n 2342| \n 2343| If the same function is called with and without linking then it must have two entries in the table." + } + ] + }, + { + "parameter_name": "MSTATUS_FS_LEGAL_VALUES", + "classification": "NORM_CSR_WARL", + "value_type": "set", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "WARL + CSR 'mstatus'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 679, + "line_text": "[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that", + "context": " 677| ===== Endianness Control in `mstatus` and `mstatush` Registers\n 678| \n>>> 679| [#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that\n 680| control the endianness of memory accesses other than instruction fetches.\n 681| [#norm:endianness_inst_fetch_little]#Instruction fetches are always little-endian.#" + }, + { + "score": 9, + "reasons": [ + "WARL + CSR 'mstatus'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 501, + "line_text": "* Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.", + "context": " 499| the possibility of a future global-ASID extension.\n 500| * SFENCE.VMA semantics have been clarified.\n>>> 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*." + }, + { + "score": 8, + "reasons": [ + "Description keyword 'FS'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks", + "CSR field name 'FS'" + ], + "is_normative": false, + "in_note": false, + "file": "zfinx.adoc", + "line_number": 151, + "line_text": "`mstatus` field FS is hardwired to 0 if the Zfinx extension is", + "context": " 149| [[norm:Zfinx_mstatus-FS_zero]]\n 150| In the standard privileged architecture defined in Volume II, the\n>>> 151| `mstatus` field FS is hardwired to 0 if the Zfinx extension is\n 152| implemented, and FS no longer affects the trapping behavior of\n 153| floating-point instructions or `fcsr` accesses." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'FS'", + "Name segment 'MSTATUS'", + "CSR field name 'FS'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 3313, + "line_text": "[#norm:mstatus-FS_off_V_fp_ill]#If the floating-point unit status field `mstatus.FS` is `Off` then any", + "context": " 3311| half-precision floating-point support.\n 3312| \n>>> 3313| [#norm:mstatus-FS_off_V_fp_ill]#If the floating-point unit status field `mstatus.FS` is `Off` then any\n 3314| attempt to execute a vector floating-point instruction will raise an\n 3315| illegal-instruction exception.# [#norm:mstatus-FS_dirty_V_fp]#Any vector floating-point instruction" + }, + { + "score": 6, + "reasons": [ + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 242, + "line_text": "[#norm:hstatus-vtw_op]#When VTW=1 (and assuming `mstatus`.TW=0),", + "context": " 240| [#norm:hstatus-vtsr_op]#When VTSR=1, an attempt in VS-mode to execute SRET raises a\n 241| virtual-instruction exception.#\n>>> 242| [#norm:hstatus-vtw_op]#When VTW=1 (and assuming `mstatus`.TW=0),\n 243| an attempt in VS-mode to execute WFI raises a virtual-instruction\n 244| exception if the WFI does not complete within an" + } + ] + }, + { + "parameter_name": "MSTATUS_TVM_IMPLEMENTED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "CSR field name 'TVM'", + "Description keyword 'TVM'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 999, + "line_text": "addresses. [#norm:hgatp_tvm_illegal]#When `mstatus`.TVM=1, attempts to read or write `hgatp` while", + "context": " 997| address-translation fences on a per-virtual-machine basis; and the MODE\n 998| field, which selects the address-translation scheme for guest physical\n>>> 999| addresses. [#norm:hgatp_tvm_illegal]#When `mstatus`.TVM=1, attempts to read or write `hgatp` while\n 1000| executing in HS-mode will raise an illegal-instruction exception.#\n 1001| " + }, + { + "score": 10, + "reasons": [ + "CSR field name 'TVM'", + "Description keyword 'TVM'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 237, + "line_text": "`mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode,", + "context": " 235| \n 236| The `hstatus` fields VTSR, VTW, and VTVM are defined analogously to the\n>>> 237| `mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode,\n 238| and cause virtual-instruction exceptions instead of illegal-instruction\n 239| exceptions." + }, + { + "score": 10, + "reasons": [ + "CSR field name 'TVM'", + "Description keyword 'TVM'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1585, + "line_text": "Neither `mstatus`.TVM nor `hstatus`.VTVM causes HFENCE.VVMA to trap.", + "context": " 1583| \n 1584| [[norm:hfence-vvma_tvm]]\n>>> 1585| Neither `mstatus`.TVM nor `hstatus`.VTVM causes HFENCE.VVMA to trap.\n 1586| \n 1587| [[norm:hfence-gvma_op]]" + }, + { + "score": 10, + "reasons": [ + "CSR field name 'TVM'", + "Description keyword 'TVM'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1588, + "line_text": "HFENCE.GVMA is valid only in HS-mode when `mstatus`.TVM=0, or in M-mode", + "context": " 1586| \n 1587| [[norm:hfence-gvma_op]]\n>>> 1588| HFENCE.GVMA is valid only in HS-mode when `mstatus`.TVM=0, or in M-mode\n 1589| (irrespective of `mstatus`.TVM). Executing an HFENCE.GVMA instruction\n 1590| guarantees that any previous stores already visible to the current hart" + }, + { + "score": 10, + "reasons": [ + "CSR field name 'TVM'", + "Description keyword 'TVM'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1589, + "line_text": "(irrespective of `mstatus`.TVM). Executing an HFENCE.GVMA instruction", + "context": " 1587| [[norm:hfence-gvma_op]]\n 1588| HFENCE.GVMA is valid only in HS-mode when `mstatus`.TVM=0, or in M-mode\n>>> 1589| (irrespective of `mstatus`.TVM). Executing an HFENCE.GVMA instruction\n 1590| guarantees that any previous stores already visible to the current hart\n 1591| are ordered before all implicit reads by that hart done for G-stage" + } + ] + }, + { + "parameter_name": "MSTATUS_VS_LEGAL_VALUES", + "classification": "NORM_CSR_WARL", + "value_type": "set", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "WARL + CSR 'mstatus'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 679, + "line_text": "[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that", + "context": " 677| ===== Endianness Control in `mstatus` and `mstatush` Registers\n 678| \n>>> 679| [#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that\n 680| control the endianness of memory accesses other than instruction fetches.\n 681| [#norm:endianness_inst_fetch_little]#Instruction fetches are always little-endian.#" + }, + { + "score": 9, + "reasons": [ + "WARL + CSR 'mstatus'", + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 501, + "line_text": "* Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.", + "context": " 499| the possibility of a future global-ASID extension.\n 500| * SFENCE.VMA semantics have been clarified.\n>>> 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*." + }, + { + "score": 8, + "reasons": [ + "Name segment 'MSTATUS'", + "CSR name 'mstatus' in backticks", + "CSR field name 'VS'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 237, + "line_text": "`mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode,", + "context": " 235| \n 236| The `hstatus` fields VTSR, VTW, and VTVM are defined analogously to the\n>>> 237| `mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode,\n 238| and cause virtual-instruction exceptions instead of illegal-instruction\n 239| exceptions." + }, + { + "score": 7, + "reasons": [ + "Name segment 'MSTATUS'", + "CSR field name 'VS'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 130, + "line_text": "[#norm:vsstatus-vs_mstatus-vs_op_active]#When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing", + "context": " 128| illegal-instruction exception when either field is set to Off.\n 129| \n>>> 130| [#norm:vsstatus-vs_mstatus-vs_op_active]#When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing\n 131| any instruction that changes vector state, including the vector CSRs, will\n 132| change both `mstatus.VS` and `vsstatus.VS` to Dirty.#" + }, + { + "score": 7, + "reasons": [ + "Name segment 'MSTATUS'", + "CSR field name 'VS'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 133, + "line_text": "[#norm:hw_mstatus_vs_dirty_update_param]#Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or", + "context": " 131| any instruction that changes vector state, including the vector CSRs, will\n 132| change both `mstatus.VS` and `vsstatus.VS` to Dirty.#\n>>> 133| [#norm:hw_mstatus_vs_dirty_update_param]#Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or\n 134| Clean to Dirty at any time, even when there is no change in vector state.#\n 135| " + } + ] + }, + { + "parameter_name": "MTVAL_WIDTH", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 6, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 4, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1691, + "line_text": "guest virtual address to `mtval`, GVA is set to 1. For any other trap", + "context": " 1689| whenever a trap is taken into M-mode. For any trap (breakpoint, address\n 1690| misaligned, access fault, page fault, or guest-page fault) that writes a\n>>> 1691| guest virtual address to `mtval`, GVA is set to 1. For any other trap\n 1692| into M-mode, GVA is set to 0.\n 1693| " + }, + { + "score": 4, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1814, + "line_text": "information, alongside `mtval`, to assist software in handling the trap.", + "context": " 1812| shown in <>. When a trap is taken into\n 1813| M-mode, `mtval2` is written with additional exception-specific\n>>> 1814| information, alongside `mtval`, to assist software in handling the trap.\n 1815| \n 1816| [[mtval2reg]]" + }, + { + "score": 4, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1837, + "line_text": "portion of the access as indicated by the virtual address in `mtval`.", + "context": " 1835| Otherwise, for misaligned loads and stores that cause guest-page faults,\n 1836| a nonzero guest physical address in `mtval2` corresponds to the faulting\n>>> 1837| portion of the access as indicated by the virtual address in `mtval`.\n 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of" + } + ] + }, + { + "parameter_name": "MTVEC_ACCESS", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 17, + "candidates": [ + { + "score": 17, + "reasons": [ + "Description keyword 'mtvec'", + "CSR name 'mtvec' in backticks", + "WARL + CSR 'mtvec'", + "Name segment 'MTVEC'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1209, + "line_text": "[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds", + "context": " 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n>>> 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds\n 1210| trap vector configuration, consisting of a vector base address (BASE)\n 1211| and a vector mode (MODE).#" + }, + { + "score": 12, + "reasons": [ + "CSR field name 'BASE'", + "Description keyword 'mtvec'", + "CSR name 'mtvec' in backticks", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1207, + "line_text": "==== Machine Trap-Vector Base-Address (`mtvec`) Register", + "context": " 1205| * 1 - `LP_EXPECTED` - a landing pad instruction is expected.\n 1206| \n>>> 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds" + }, + { + "score": 12, + "reasons": [ + "Description keyword 'mtvec'", + "CSR name 'mtvec' in backticks", + "Name segment 'MTVEC'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1217, + "line_text": "[#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but", + "context": " 1215| include::images/bytefield/mtvec.edn[]\n 1216| \n>>> 1217| [#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but\n 1218| [#norm:mtvec_rdonly]#can contain a read-only value.#\n 1219| If `mtvec` is writable, the set of values the register" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'mtvec'", + "CSR name 'mtvec' in backticks", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1219, + "line_text": "If `mtvec` is writable, the set of values the register", + "context": " 1217| [#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but\n 1218| [#norm:mtvec_rdonly]#can contain a read-only value.#\n>>> 1219| If `mtvec` is writable, the set of values the register\n 1220| may hold can vary by implementation.\n 1221| [#norm:mtvec_base_align_4B]#The value in the BASE field must" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'mtvec'", + "CSR name 'mtvec' in backticks", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-csrs.adoc", + "line_number": 685, + "line_text": "`mtvec` +", + "context": " 683| `mideleg` +\n 684| `mie` +\n>>> 685| `mtvec` +\n 686| `mcounteren` +\n 687| `mstatush` +" + } + ] + }, + { + "parameter_name": "MTVEC_BASE_ALIGNMENT_DIRECT", + "classification": "NORM_CSR_WARL", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1209, + "line_text": "[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds", + "context": " 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n>>> 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds\n 1210| trap vector configuration, consisting of a vector base address (BASE)\n 1211| and a vector mode (MODE).#" + }, + { + "score": 6, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1217, + "line_text": "[#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but", + "context": " 1215| include::images/bytefield/mtvec.edn[]\n 1216| \n>>> 1217| [#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but\n 1218| [#norm:mtvec_rdonly]#can contain a read-only value.#\n 1219| If `mtvec` is writable, the set of values the register" + }, + { + "score": 4, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1207, + "line_text": "==== Machine Trap-Vector Base-Address (`mtvec`) Register", + "context": " 1205| * 1 - `LP_EXPECTED` - a landing pad instruction is expected.\n 1206| \n>>> 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds" + }, + { + "score": 4, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1214, + "line_text": ".Encoding of mtvec MODE field.", + "context": " 1212| \n 1213| [[norm:mtvec_enc]]\n>>> 1214| .Encoding of mtvec MODE field.\n 1215| include::images/bytefield/mtvec.edn[]\n 1216| " + }, + { + "score": 4, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1215, + "line_text": "include::images/bytefield/mtvec.edn[]", + "context": " 1213| [[norm:mtvec_enc]]\n 1214| .Encoding of mtvec MODE field.\n>>> 1215| include::images/bytefield/mtvec.edn[]\n 1216| \n 1217| [#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but" + } + ] + }, + { + "parameter_name": "MTVEC_BASE_ALIGNMENT_VECTORED", + "classification": "NORM_CSR_WARL", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": [ + "Name segment 'VECTORED'", + "Description keyword 'mtvec'", + "Description keyword 'vectored'", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 540, + "line_text": "* Optional vectored interrupt support has been added to the `mtvec` and", + "context": " 538| * Clarified expected use of XS to summarize additional extension state\n 539| status fields in `mstatus`.\n>>> 540| * Optional vectored interrupt support has been added to the `mtvec` and\n 541| `stvec` CSRs.\n 542| * The SEIP and UEIP bits in the `mip` CSR have been redefined to support" + }, + { + "score": 6, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1209, + "line_text": "[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds", + "context": " 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n>>> 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds\n 1210| trap vector configuration, consisting of a vector base address (BASE)\n 1211| and a vector mode (MODE).#" + }, + { + "score": 6, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1217, + "line_text": "[#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but", + "context": " 1215| include::images/bytefield/mtvec.edn[]\n 1216| \n>>> 1217| [#norm:mtvec_mandatory]#The `mtvec` register must always be implemented#, but\n 1218| [#norm:mtvec_rdonly]#can contain a read-only value.#\n 1219| If `mtvec` is writable, the set of values the register" + }, + { + "score": 5, + "reasons": [ + "Name segment 'VECTORED'", + "Description keyword 'vectored'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1256, + "line_text": "[#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause", + "context": " 1254| [#norm:mtvec_mode_direct_op]#When MODE=Direct, all traps into\n 1255| machine mode cause the `pc` to be set to the address in the BASE field.#\n>>> 1256| [#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause\n 1257| the `pc` to be set to the address in the BASE field, whereas interrupts\n 1258| cause the `pc` to be set to the address in the BASE field plus four" + }, + { + "score": 4, + "reasons": ["Description keyword 'mtvec'", "Name segment 'MTVEC'"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1207, + "line_text": "==== Machine Trap-Vector Base-Address (`mtvec`) Register", + "context": " 1205| * 1 - `LP_EXPECTED` - a landing pad instruction is expected.\n 1206| \n>>> 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds" + } + ] + }, + { + "parameter_name": "MTVEC_ILLEGAL_WRITE_BEHAVIOR", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 18, + "candidates": [ + { + "score": 18, + "reasons": [ + "Name segment 'WRITE'", + "WARL + CSR 'mtvec'", + "CSR name 'mtvec' in backticks", + "Description keyword 'mtvec'", + "Name segment 'MTVEC'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1209, + "line_text": "[#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds", + "context": " 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n>>> 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds\n 1210| trap vector configuration, consisting of a vector base address (BASE)\n 1211| and a vector mode (MODE).#" + }, + { + "score": 16, + "reasons": [ + "CSR field name 'BASE'", + "Description keyword 'BASE'", + "CSR name 'mtvec' in backticks", + "Description keyword 'mtvec'", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1207, + "line_text": "==== Machine Trap-Vector Base-Address (`mtvec`) Register", + "context": " 1205| * 1 - `LP_EXPECTED` - a landing pad instruction is expected.\n 1206| \n>>> 1207| ==== Machine Trap-Vector Base-Address (`mtvec`) Register\n 1208| \n 1209| [#norm:mtvec_sz_warl_acc]#The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds" + }, + { + "score": 15, + "reasons": [ + "Name segment 'WRITE'", + "CSR field name 'BASE'", + "CSR field name 'MODE'", + "Description keyword 'BASE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2399, + "line_text": "[#norm:jvt_reg]#The _jvt_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).#", + "context": " 2397| Description::\n 2398| \n>>> 2399| [#norm:jvt_reg]#The _jvt_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).#\n 2400| \n 2401| [#norm:jvt_op]#If <> is implemented then _jvt_ must also be implemented, but can contain a read-only value. If _jvt_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary." + }, + { + "score": 13, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'mtvec'", + "Description keyword 'MODE'", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1214, + "line_text": ".Encoding of mtvec MODE field.", + "context": " 1212| \n 1213| [[norm:mtvec_enc]]\n>>> 1214| .Encoding of mtvec MODE field.\n 1215| include::images/bytefield/mtvec.edn[]\n 1216| " + }, + { + "score": 13, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'mtvec'", + "Description keyword 'MODE'", + "Name segment 'MTVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1238, + "line_text": ".Encoding of mtvec MODE field.", + "context": " 1236| \n 1237| [[norm:mtvec_mode_enc]]\n>>> 1238| .Encoding of mtvec MODE field.\n 1239| [%autowidth,float=\"center\",align=\"center\",cols=\">,^,<\",options=\"header\"]\n 1240| |===" + } + ] + }, + { + "parameter_name": "MTVEC_MODES", + "classification": "NORM_CSR_WARL", + "value_type": "set", + "num_candidates": 10, + "best_score": 18, + "candidates": [ + { + "score": 18, + "reasons": [ + "CSR field name 'BASE'", + "CSR field name 'MODE'", + "Description keyword 'pc'", + "Description keyword 'BASE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1255, + "line_text": "machine mode cause the `pc` to be set to the address in the BASE field.#", + "context": " 1253| The encoding of the MODE field is shown in <>.\n 1254| [#norm:mtvec_mode_direct_op]#When MODE=Direct, all traps into\n>>> 1255| machine mode cause the `pc` to be set to the address in the BASE field.#\n 1256| [#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause\n 1257| the `pc` to be set to the address in the BASE field, whereas interrupts" + }, + { + "score": 18, + "reasons": [ + "CSR field name 'BASE'", + "CSR field name 'MODE'", + "Description keyword 'pc'", + "Description keyword 'BASE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1260, + "line_text": "For example, a machine-mode timer interrupt (see <>) causes the `pc` to be set to BASE+`0x1c`.", + "context": " 1258| cause the `pc` to be set to the address in the BASE field plus four\n 1259| times the interrupt cause number.#\n>>> 1260| For example, a machine-mode timer interrupt (see <>) causes the `pc` to be set to BASE+`0x1c`.\n 1261| \n 1262| An implementation may have different alignment constraints for different" + }, + { + "score": 18, + "reasons": [ + "CSR field name 'BASE'", + "CSR field name 'MODE'", + "Description keyword 'pc'", + "Description keyword 'BASE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 356, + "line_text": "supervisor mode cause the `pc` to be set to the address in the BASE", + "context": " 354| The encoding of the MODE field is shown in\n 355| <>. When MODE=Direct, all traps into\n>>> 356| supervisor mode cause the `pc` to be set to the address in the BASE\n 357| field. When MODE=Vectored, all synchronous exceptions into supervisor\n 358| mode cause the `pc` to be set to the address in the BASE field, whereas" + }, + { + "score": 18, + "reasons": [ + "CSR field name 'BASE'", + "CSR field name 'MODE'", + "Description keyword 'pc'", + "Description keyword 'BASE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 358, + "line_text": "mode cause the `pc` to be set to the address in the BASE field, whereas", + "context": " 356| supervisor mode cause the `pc` to be set to the address in the BASE\n 357| field. When MODE=Vectored, all synchronous exceptions into supervisor\n>>> 358| mode cause the `pc` to be set to the address in the BASE field, whereas\n 359| interrupts cause the `pc` to be set to the address in the BASE field\n 360| plus four times the interrupt cause number. For example, a" + }, + { + "score": 18, + "reasons": [ + "CSR field name 'BASE'", + "CSR field name 'MODE'", + "Description keyword 'pc'", + "Description keyword 'BASE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 362, + "line_text": "causes the `pc` to be set to BASE+`0x14`. Setting MODE=Vectored may", + "context": " 360| plus four times the interrupt cause number. For example, a\n 361| supervisor-mode timer interrupt (see <>)\n>>> 362| causes the `pc` to be set to BASE+`0x14`. Setting MODE=Vectored may\n 363| impose a stricter alignment constraint on BASE.\n 364| " + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_A", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 16, + "candidates": [ + { + "score": 16, + "reasons": [ + "WARL + CSR 'misa'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'A'", + "CSR field name 'A'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 14, + "reasons": [ + "WARL + CSR 'misa'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'A'", + "CSR field name 'A'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 11, + "reasons": [ + "CSR field name 'A'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'A'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 23, + "line_text": "but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism.", + "context": " 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n>>> 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism.\n 24| \n 25| [[norm:misa_enc_img]]" + }, + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'G'", + "CSR field name 'A'", + "Description keyword 'A'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 250, + "line_text": "|WRPTR |[#norm:sctrstatus-wrptr]#WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see <>), though there are exceptions when `__x__ctrctl`.RASEMU=1, see <>. For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value.#", + "context": " 248| |===\n 249| |Field |Description\n>>> 250| |WRPTR |[#norm:sctrstatus-wrptr]#WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see <>), though there are exceptions when `__x__ctrctl`.RASEMU=1, see <>. For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value.#\n 251| |FROZEN |[#norm:sctrstatus-frozen_op]#Inhibit transfer recording.# See <>.\n 252| |===" + }, + { + "score": 9, + "reasons": [ + "CSR field name 'A'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'A'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1184, + "line_text": "encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.", + "context": " 1182| from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does\n 1183| not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is\n>>> 1184| encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.\n 1185| \n 1186| [[norm:vsstatus-uxl_change]]" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_B", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'B'", + "CSR field name 'B'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 341, + "line_text": "* Defined the `misa`.B field to reflect that the B extension has been", + "context": " 339| made to the Machine and Supervisor ISAs since version 1.12:\n 340| \n>>> 341| * Defined the `misa`.B field to reflect that the B extension has been\n 342| implemented.\n 343| * Defined the `misa`.V field to reflect that the V extension has been" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 7, + "reasons": ["Description keyword 'B'", "CSR field name 'B'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 199, + "line_text": "[#norm:misa_b_op]#When the \"B\" bit is 1, the implementation supports the instructions provided by the", + "context": " 197| [#norm:misa_x_op]#The \"X\" bit will be set if there are any non-standard extensions.#\n 198| \n>>> 199| [#norm:misa_b_op]#When the \"B\" bit is 1, the implementation supports the instructions provided by the\n 200| Zba, Zbb, and Zbs extensions.# When the \"B\" bit is 0, it indicates that the\n 201| implementation might not support one or more of the Zba, Zbb, or Zbs extensions." + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_C", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 11, + "reasons": [ + "CSR field name 'C'", + "Description keyword 'C'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 246, + "line_text": "[#norm:misa_inc_ialign]#Writing `misa` may increase IALIGN, e.g., by disabling the \"C\"", + "context": " 244| collectively as a single *WARL* field. An attempt to write an unsupported combination causes those bits to be set to some supported combination.\n 245| \n>>> 246| [#norm:misa_inc_ialign]#Writing `misa` may increase IALIGN, e.g., by disabling the \"C\"\n 247| extension. If an instruction that would write `misa` increases IALIGN,\n 248| and the subsequent instruction's address is not IALIGN-bit aligned, the" + }, + { + "score": 11, + "reasons": [ + "CSR field name 'C'", + "Description keyword 'C'", + "Name segment 'MISA'", + "Description keyword 'misa.C'" + ], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 84, + "line_text": "[#norm:misa-c_set_line]#MISA.C is set if the following extensions are selected:#", + "context": " 82| === MISA.C\n 83| \n>>> 84| [#norm:misa-c_set_line]#MISA.C is set if the following extensions are selected:#\n 85| \n 86| [[norm:misa-c_set_list]]" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_D", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "Description keyword 'D'", + "CSR name 'misa' in backticks", + "CSR field name 'D'" + ], + "is_normative": false, + "in_note": false, + "file": "zfinx.adoc", + "line_number": 156, + "line_text": "The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension", + "context": " 154| \n 155| [[norm:Zfinx_misa-F_D_Q_zero]]\n>>> 156| The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension\n 157| is implemented.\n 158| [NOTE]" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'G'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 246, + "line_text": "[#norm:misa_inc_ialign]#Writing `misa` may increase IALIGN, e.g., by disabling the \"C\"", + "context": " 244| collectively as a single *WARL* field. An attempt to write an unsupported combination causes those bits to be set to some supported combination.\n 245| \n>>> 246| [#norm:misa_inc_ialign]#Writing `misa` may increase IALIGN, e.g., by disabling the \"C\"\n 247| extension. If an instruction that would write `misa` increases IALIGN,\n 248| and the subsequent instruction's address is not IALIGN-bit aligned, the" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_F", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 9, + "reasons": [ + "Description keyword 'misa.F'", + "CSR field name 'F'", + "Name segment 'MISA'", + "Description keyword 'F'" + ], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 245, + "line_text": "the Zfinx and related extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit", + "context": " 243| The FCSR bit controls access to `fcsr` for the case when floating-point\n 244| instructions operate on `x` registers instead of `f` registers as specified by\n>>> 245| the Zfinx and related extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit\n 246| of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and\n 247| `sstateen0` too). For convenience, when the `stateen` CSRs are implemented and" + }, + { + "score": 9, + "reasons": [ + "Description keyword 'misa.F'", + "CSR field name 'F'", + "Name segment 'MISA'", + "Description keyword 'F'" + ], + "is_normative": false, + "in_note": false, + "file": "smstateen.adoc", + "line_number": 248, + "line_text": "`misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all", + "context": " 246| of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and\n 247| `sstateen0` too). For convenience, when the `stateen` CSRs are implemented and\n>>> 248| `misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all\n 249| floating-point instructions cause an illegal-instruction exception (or virtual-instruction\n 250| exception, if relevant), as though they all access `fcsr`, regardless of" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_H", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'H'", + "CSR field name 'H'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 413, + "line_text": "[#norm:hstateen_ctr]#If the H extension is implemented and `mstateen0`.CTR=1, the `hstateen0`.CTR bit controls access to supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0`.CTR is read-only 0 when `mstateen0`.CTR=0.#", + "context": " 411| [#norm:mstateen_ctr0_qualified_transfer]#When `mstateen0`.CTR=0, qualified control transfers executed in privilege modes less privileged than M-mode will continue to implicitly update entry registers and `sctrstatus`.#\n 412| \n>>> 413| [#norm:hstateen_ctr]#If the H extension is implemented and `mstateen0`.CTR=1, the `hstateen0`.CTR bit controls access to supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0`.CTR is read-only 0 when `mstateen0`.CTR=0.#\n 414| \n 415| [#norm:hstateen_vs]#When `mstateen0`.CTR=1 and `hstateen0`.CTR=1, VS-mode accesses to supervisor CTR state behave as described in <> and <> above, while SCTRCLR behaves as described in <>. When `mstateen0`.CTR=1 and `hstateen0`.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of SCTRCLR raise a virtual-instruction exception.#" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'MISA'", + "CSR name 'misa' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 231, + "line_text": "[#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the", + "context": " 229| \n 230| [#norm:misa_e_acc]#The \"E\" bit is read-only.#\n>>> 231| [#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the\n 232| \"E\" bit always reads as the complement of the \"I\" bit.#\n 233| If an execution environment supports both RV32E and RV32I, software can select" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_M", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'G'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 246, + "line_text": "[#norm:misa_inc_ialign]#Writing `misa` may increase IALIGN, e.g., by disabling the \"C\"", + "context": " 244| collectively as a single *WARL* field. An attempt to write an unsupported combination causes those bits to be set to some supported combination.\n 245| \n>>> 246| [#norm:misa_inc_ialign]#Writing `misa` may increase IALIGN, e.g., by disabling the \"C\"\n 247| extension. If an instruction that would write `misa` increases IALIGN,\n 248| and the subsequent instruction's address is not IALIGN-bit aligned, the" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'M'", + "CSR field name 'M'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 802, + "line_text": "[#norm:mstatus_tw_acc]#TW is read-only 0 when there are no modes less privileged than M.#", + "context": " 800| TW=1, even if there are pending globally-disabled interrupts when the\n 801| instruction is executed.#\n>>> 802| [#norm:mstatus_tw_acc]#TW is read-only 0 when there are no modes less privileged than M.#\n 803| \n 804| [NOTE]" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_Q", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 9, + "reasons": [ + "Description keyword 'Q'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "CSR field name 'Q'" + ], + "is_normative": false, + "in_note": false, + "file": "zfinx.adoc", + "line_number": 156, + "line_text": "The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension", + "context": " 154| \n 155| [[norm:Zfinx_misa-F_D_Q_zero]]\n>>> 156| The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension\n 157| is implemented.\n 158| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'MISA'", + "CSR name 'misa' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 231, + "line_text": "[#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the", + "context": " 229| \n 230| [#norm:misa_e_acc]#The \"E\" bit is read-only.#\n>>> 231| [#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the\n 232| \"E\" bit always reads as the complement of the \"I\" bit.#\n 233| If an execution environment supports both RV32E and RV32I, software can select" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_S", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'S'", + "Description keyword 'S'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 577, + "line_text": "[#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "context": " 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n>>> 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.\n 578| Otherwise, it is a *WARL* field that encodes the current value of SXLEN.#\n 579| In particular, [#norm:mstatus_sxl_rdonly_mxlen64]#an implementation may make SXL be a read-only field whose" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'S'", + "Description keyword 'S'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 648, + "line_text": "[#norm:mstatus_mxr_rdonly0_no_smode]#MXR is read-only 0 if S-mode is not supported.#", + "context": " 646| When MXR=1, loads from pages marked either readable or executable (R=1 or\n 647| X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.#\n>>> 648| [#norm:mstatus_mxr_rdonly0_no_smode]#MXR is read-only 0 if S-mode is not supported.#\n 649| \n 650| [NOTE]" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_U", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 503, + "line_text": "* Made the unused `misa` fields *WARL*, rather than *WIRI*.", + "context": " 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n>>> 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*.\n 504| * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*.\n 505| * Required all harts in a system to employ the same PTE-update scheme as" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'U'", + "CSR field name 'U'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 582, + "line_text": "[#norm:mstatus_uxl_acc_mxlen64]#When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.", + "context": " 580| value always ensures that SXLEN=MXLEN.#\n 581| \n>>> 582| [#norm:mstatus_uxl_acc_mxlen64]#When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.\n 583| Otherwise, it is a *WARL* field that encodes the current value of UXLEN.#\n 584| In particular, [#norm:mstatus_uxl_rdonly_mxlen64]#an implementation may make UXL be a read-only field whose" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'U'", + "CSR field name 'U'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 639, + "line_text": "[#norm:mstatus_mprv_rdonly0_no_umode]#MPRV is read-only 0 if U-mode is not supported.#", + "context": " 637| [#norm:mstatus_mprv_inst_xlat_op]#Instruction address-translation and protection are unaffected by the\n 638| setting of MPRV.#\n>>> 639| [#norm:mstatus_mprv_rdonly0_no_umode]#MPRV is read-only 0 if U-mode is not supported.#\n 640| \n 641| [#norm:mstatus_mprv_clr_mret_sret_less_priv]#An MRET or SRET instruction that changes the privilege mode to a mode" + } + ] + }, + { + "parameter_name": "MUTABLE_MISA_V", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 14, + "candidates": [ + { + "score": 14, + "reasons": [ + "CSR field name 'V'", + "Description keyword 'misa.V'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'V'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 5161, + "line_text": "[#norm:misa-V_op]#The `misa.v` bit is set for implementations providing `misa` and", + "context": " 5159| processor profiles.\n 5160| \n>>> 5161| [#norm:misa-V_op]#The `misa.v` bit is set for implementations providing `misa` and\n 5162| supporting V.#\n 5163| " + }, + { + "score": 11, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 21, + "line_text": "[#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.", + "context": " 19| ==== Machine ISA (`misa`) Register\n 20| \n>>> 21| [#norm:misa_acc]#The `misa` CSR is a *WARL* read-write register# reporting the ISA supported by the hart.\n 22| [#norm:misa_always_rd]#This register must be readable in any implementation#,\n 23| but [#norm:misa_csr_implemented]#a value of zero can be returned to indicate the `misa` register has not been implemented#, requiring that CPU capabilities be determined through a separate non-standard mechanism." + }, + { + "score": 11, + "reasons": [ + "Description keyword 'misa.V'", + "CSR field name 'V'", + "Name segment 'MISA'", + "Description keyword 'V'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 110, + "line_text": "[#norm:mutable_misa_v_param]#Implementations may have a writable `misa.V` field.# [#norm:mstatus_vs_exists_param]#Analogous to the", + "context": " 108| otherwise, `mstatus.SD` is set in accordance with existing specifications.\n 109| \n>>> 110| [#norm:mutable_misa_v_param]#Implementations may have a writable `misa.V` field.# [#norm:mstatus_vs_exists_param]#Analogous to the\n 111| way in which the floating-point unit is handled, the `mstatus.VS`\n 112| field may exist even if `misa.V` is clear.#" + }, + { + "score": 9, + "reasons": [ + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "WARL + CSR 'misa'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 226, + "line_text": "VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,", + "context": " 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n>>> 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always" + }, + { + "score": 9, + "reasons": [ + "CSR field name 'V'", + "Name segment 'MISA'", + "CSR name 'misa' in backticks", + "Description keyword 'V'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 343, + "line_text": "* Defined the `misa`.V field to reflect that the V extension has been", + "context": " 341| * Defined the `misa`.B field to reflect that the B extension has been\n 342| implemented.\n>>> 343| * Defined the `misa`.V field to reflect that the V extension has been\n 344| implemented.\n 345| * Defined the RV32-only `medelegh` and `hedelegh` CSRs." + } + ] + }, + { + "parameter_name": "MXLEN", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "Exact parameter name 'MXLEN'", + "Name segment 'MXLEN'", + "CSR name 'misa' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 50, + "line_text": "[#norm:misa_sz]#The `misa` CSR is MXLEN bits wide.#", + "context": " 48| |===\n 49| \n>>> 50| [#norm:misa_sz]#The `misa` CSR is MXLEN bits wide.#\n 51| \n 52| [NOTE]" + }, + { + "score": 12, + "reasons": [ + "Exact parameter name 'MXLEN'", + "Name segment 'MXLEN'", + "CSR name 'misa' in backticks", + "CSR field name 'MXL'" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 335, + "line_text": "* Redefined `misa`.MXL to be read-only, making MXLEN a constant.", + "context": " 333| anticipated to cause software portability problems in practice:\n 334| \n>>> 335| * Redefined `misa`.MXL to be read-only, making MXLEN a constant.\n 336| * Added the constraint that SXLEN{ge}UXLEN.\n 337| " + }, + { + "score": 11, + "reasons": [ + "Exact parameter name 'MXLEN'", + "Name segment 'MXLEN'", + "CSR field name 'ADDRESS'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 296, + "line_text": "[#norm:Ssctr_ctrsource_sz_acc_op]#`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.#", + "context": " 294| [#norm:ctrsource_op]#The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.# [#norm:ctrsource_ctrtartget_ctrdata_Vbit]#The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.#\n 295| \n>>> 296| [#norm:Ssctr_ctrsource_sz_acc_op]#`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.#\n 297| \n 298| .Control Transfer Record Source Register Format for MXLEN=64" + }, + { + "score": 11, + "reasons": [ + "Exact parameter name 'MXLEN'", + "Name segment 'MXLEN'", + "CSR field name 'ADDRESS'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 324, + "line_text": "[#norm:ctrtarget_sz_acc]#`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended.#", + "context": " 322| is read-only 0 when not implemented.#\n 323| \n>>> 324| [#norm:ctrtarget_sz_acc]#`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended.#\n 325| \n 326| .Control Transfer Record Target Register Format for MXLEN=64" + }, + { + "score": 10, + "reasons": [ + "Exact parameter name 'MXLEN'", + "Name segment 'MXLEN'", + "CSR name 'mconfigptr' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2138, + "line_text": "The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in", + "context": " 2136| ==== Machine Configuration Pointer (`mconfigptr`) Register\n 2137| \n>>> 2138| The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in\n 2139| <>, that holds the physical\n 2140| address of a configuration data structure. Software can traverse this" + } + ] + }, + { + "parameter_name": "M_MODE_ENDIANNESS", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 22, + "candidates": [ + { + "score": 22, + "reasons": [ + "WARL + CSR 'mstatush'", + "CSR field name 'MBE'", + "CSR name 'mstatus' in backticks", + "CSR name 'mstatush' in backticks", + "Description keyword 'MBE'", + "WARL + CSR 'mstatus'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 679, + "line_text": "[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that", + "context": " 677| ===== Endianness Control in `mstatus` and `mstatush` Registers\n 678| \n>>> 679| [#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that\n 680| control the endianness of memory accesses other than instruction fetches.\n 681| [#norm:endianness_inst_fetch_little]#Instruction fetches are always little-endian.#" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'MBE'", + "CSR name 'mstatus' in backticks", + "CSR field name 'MBE'", + "CSR name 'mstatush' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2791, + "line_text": "supported, the `mstatus`/`mstatush` field MBE is reset to 0. The `misa`", + "context": " 2789| Upon reset, a hart’s privilege mode is set to M. The `mstatus` fields\n 2790| MIE and MPRV are reset to 0. If little-endian memory accesses are\n>>> 2791| supported, the `mstatus`/`mstatush` field MBE is reset to 0. The `misa`\n 2792| register is reset to enable the maximal set of supported extensions,\n 2793| as described in <>. For" + }, + { + "score": 9, + "reasons": [ + "Description keyword 'MBE'", + "CSR name 'mstatus' in backticks", + "CSR field name 'MBE'", + "Description keyword 'endian'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 685, + "line_text": "M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or", + "context": " 683| [[norm:mstatus_mbe_op]]\n 684| MBE controls whether non-instruction-fetch memory accesses made from\n>>> 685| M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or\n 686| big-endian (MBE=1).\n 687| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mstatus' in backticks", + "CSR name 'mstatush' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 393, + "line_text": "[#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#", + "context": " 391| \n 392| [#norm:mstatush_sz_acc]#For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>.#\n>>> 393| [#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#\n 394| \n 395| [[mstatushreg]]" + }, + { + "score": 8, + "reasons": [ + "WARL + CSR 'mstatus'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 501, + "line_text": "* Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.", + "context": " 499| the possibility of a future global-ASID extension.\n 500| * SFENCE.VMA semantics have been clarified.\n>>> 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*." + } + ] + }, + { + "parameter_name": "NUM_EXTERNAL_GUEST_INTERRUPTS", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'INTERRUPTS'", + "CSR field name 'VGEIN'", + "Description keyword 'GEILEN'", + "Name segment 'EXTERNAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 259, + "line_text": "VS-level external interrupts. GEILEN may be zero, in which case VGEIN", + "context": " 257| maximum guest external interrupt number (known as GEILEN), inclusive.\n 258| When VGEIN=0, no guest external interrupt source is selected for\n>>> 259| VS-level external interrupts. GEILEN may be zero, in which case VGEIN\n 260| may be read-only zero. Guest external interrupts are explained in\n 261| <>, and the use of VGEIN is covered" + }, + { + "score": 7, + "reasons": [ + "Name segment 'GUEST'", + "Description keyword 'GEILEN'", + "Name segment 'EXTERNAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 257, + "line_text": "maximum guest external interrupt number (known as GEILEN), inclusive.", + "context": " 255| guest external interrupt source for VS-level external interrupts. VGEIN\n 256| is a *WLRL* field that must be able to hold values between zero and the\n>>> 257| maximum guest external interrupt number (known as GEILEN), inclusive.\n 258| When VGEIN=0, no guest external interrupt source is selected for\n 259| VS-level external interrupts. GEILEN may be zero, in which case VGEIN" + }, + { + "score": 5, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'INTERRUPTS'", + "CSR field name 'VGEIN'", + "Name segment 'EXTERNAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 255, + "line_text": "guest external interrupt source for VS-level external interrupts. VGEIN", + "context": " 253| [[norm:hstatus-vgein_op]]\n 254| The VGEIN (Virtual Guest External Interrupt Number) field selects a\n>>> 255| guest external interrupt source for VS-level external interrupts. VGEIN\n 256| is a *WLRL* field that must be able to hold values between zero and the\n 257| maximum guest external interrupt number (known as GEILEN), inclusive." + }, + { + "score": 5, + "reasons": [ + "CSR field name 'VGEIN'", + "CSR name 'hstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 571, + "line_text": "* the bit of `hgeip` selected by `hstatus`.VGEIN; and", + "context": " 569| \n 570| * bit VSEIP of `hvip`;\n>>> 571| * the bit of `hgeip` selected by `hstatus`.VGEIN; and\n 572| * any other platform-specific external interrupt signal directed to\n 573| VS-level." + }, + { + "score": 5, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'INTERRUPTS'", + "Name segment 'EXTERNAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 604, + "line_text": "guest external interrupts at this hart.# [#norm:hgeip_hgeie_fields]#Guest external interrupt number", + "context": " 602| read/write register, formatted as shown in\n 603| <>, that contains enable bits for the\n>>> 604| guest external interrupts at this hart.# [#norm:hgeip_hgeie_fields]#Guest external interrupt number\n 605| _i_ corresponds with bit _i_ in both `hgeip` and `hgeie`.#\n 606| " + } + ] + }, + { + "parameter_name": "NUM_PMP_ENTRIES", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Description keyword 'NOTE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 668, + "line_text": "Note that, [#norm:mstatus_sum_op_mprv_mpp]#while SUM is ordinarily ignored when not", + "context": " 666| (U=1 in <>) will fault. When SUM=1, these accesses are permitted.#\n 667| [#norm:mstatus_sum_op_no-vm]#SUM has no effect when page-based virtual memory is not in effect.#\n>>> 668| Note that, [#norm:mstatus_sum_op_mprv_mpp]#while SUM is ordinarily ignored when not\n 669| executing in S-mode, it _is_ in effect when MPRV=1 and MPP=S.#\n 670| [#norm:mstatus_sum_rdonly0]#SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.#" + }, + { + "score": 4, + "reasons": ["Description keyword 'NOTE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1780, + "line_text": "[#norm:mcause_exccode_ld_ldrsv]#Note that load and load-reserved instructions generate load exceptions#, whereas", + "context": " 1778| include::images/bytefield/mcausereg.edn[]\n 1779| \n>>> 1780| [#norm:mcause_exccode_ld_ldrsv]#Note that load and load-reserved instructions generate load exceptions#, whereas\n 1781| [#norm:mcause_exccode_st_sc_amo]#store, store-conditional, and AMO instructions generate\n 1782| store/AMO exceptions.#" + }, + { + "score": 4, + "reasons": ["Description keyword 'NOTE'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 169, + "line_text": "NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage", + "context": " 167| \n 168| \n>>> 169| NOTE: [#norm:vill_implicit_encoding_param]#A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage\n 170| bit to hold `vill`.#\n 171| " + }, + { + "score": 4, + "reasons": ["Description keyword 'NOTE'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 206, + "line_text": "NOTE: [#norm:vtype-vsew_rsv]#While it is anticipated the larger `vsew[2:0]` encodings", + "context": " 204| |===\n 205| \n>>> 206| NOTE: [#norm:vtype-vsew_rsv]#While it is anticipated the larger `vsew[2:0]` encodings\n 207| (`100`-`111`) will be used to encode larger SEW, the encodings are\n 208| formally _reserved_ at this point.#" + }, + { + "score": 4, + "reasons": ["Description keyword 'NOTE'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 2309, + "line_text": "NOTE: [#norm:V_Zinx_fp_scalar]#When adding a vector extension to the Zfinx/Zdinx/Zhinx", + "context": " 2307| by naming the immediate `uimm` in the assembly syntax.\n 2308| \n>>> 2309| NOTE: [#norm:V_Zinx_fp_scalar]#When adding a vector extension to the Zfinx/Zdinx/Zhinx\n 2310| extensions, floating-point scalar arguments are taken from the `x` registers.\n 2311| NaN-boxing is not supported in these extensions, and so operands narrower" + } + ] + }, + { + "parameter_name": "PHYS_ADDR_WIDTH", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Name segment 'ADDR'", "CSR field name 'ADDR'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1027, + "line_text": "<>.", + "context": " 1025| Sv39, Sv48, and Sv57 paged virtual-memory schemes. All of these paged\n 1026| virtual-memory schemes are described in\n>>> 1027| <>.\n 1028| \n 1029| The remaining MODE settings when HSXLEN=64 are reserved for future use" + }, + { + "score": 3, + "reasons": ["Name segment 'ADDR'", "CSR field name 'ADDR'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1079, + "line_text": "As explained in <>, for the", + "context": " 1077| \n 1078| [[norm:hgatp-ppn_op]]\n>>> 1079| As explained in <>, for the\n 1080| paged virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the\n 1081| root page table is 16 KiB and must be aligned to a 16-KiB boundary. In" + }, + { + "score": 3, + "reasons": ["Name segment 'ADDR'", "CSR field name 'ADDR'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1901, + "line_text": "[[guest-addr-translation]]", + "context": " 1899| addresses and is in effect regardless of virtualization mode.\n 1900| \n>>> 1901| [[guest-addr-translation]]\n 1902| ==== Guest Physical Address Translation\n 1903| " + }, + { + "score": 3, + "reasons": ["Name segment 'ADDR'", "CSR field name 'ADDR'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2784, + "line_text": ".Transformed atomic instruction (load-reserved, store-conditional, or AMO instruction). All fields are the same as the trapping instruction except bits 19:15, Addr. Offset.", + "context": " 2782| \n 2783| [[transformedatomicinst]]\n>>> 2784| .Transformed atomic instruction (load-reserved, store-conditional, or AMO instruction). All fields are the same as the trapping instruction except bits 19:15, Addr. Offset.\n 2785| include::images/wavedrom/transformedatomicinst.edn[]\n 2786| " + }, + { + "score": 3, + "reasons": ["Name segment 'ADDR'", "CSR field name 'ADDR'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2790, + "line_text": ".Transformed virtual-machine load/store instruction (HLV, HLVX, HSV). All fields are the same as the trapping instruction except bits 19:15, Addr. Offset", + "context": " 2788| \n 2789| [[transformedvmaccessinst]]\n>>> 2790| .Transformed virtual-machine load/store instruction (HLV, HLVX, HSV). All fields are the same as the trapping instruction except bits 19:15, Addr. Offset\n 2791| include::images/wavedrom/transformedvmaccessinst.edn[]\n 2792| " + } + ] + }, + { + "parameter_name": "PMA_GRANULARITY", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 754, + "line_text": "granularity and atomicity, including individual bytes.", + "context": " 752| Cache-block zero instructions store zeros to the set of bytes corresponding to a\n 753| cache block. An implementation may update the bytes in any order and with any\n>>> 754| granularity and atomicity, including individual bytes.\n 755| \n 756| [NOTE]" + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2901, + "line_text": "registers can be provided to specify these attributes at a granularity", + "context": " 2899| region, and can be hardwired into the PMA checker. Where the attributes\n 2900| are run-time configurable, platform-specific memory-mapped control\n>>> 2901| registers can be provided to specify these attributes at a granularity\n 2902| appropriate to each region on the platform (e.g., for an on-chip SRAM\n 2903| that can be flexibly divided between cacheable and uncacheable uses)." + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 3308, + "line_text": "The granularity of PMP access control settings are platform-specific,", + "context": " 3306| checks described in <>.\n 3307| \n>>> 3308| The granularity of PMP access control settings are platform-specific,\n 3309| but the standard PMP encoding supports regions as small as four bytes.\n 3310| Certain regions’ privileges can be hardwired—for example, some regions" + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 3428, + "line_text": "(TOR). These modes support four-byte granularity.", + "context": " 3426| regions (NAPOT), including the special case of naturally aligned\n 3427| four-byte regions (NA4); and the top boundary of an arbitrary range\n>>> 3428| (TOR). These modes support four-byte granularity.\n 3429| \n 3430| [[pmpcfg-a]]" + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "mm-eplan.adoc", + "line_number": 423, + "line_text": "cache line granularity (and which therefore will see the four snippets", + "context": " 421| the same hart as the paired load-reserved and store-conditional\n 422| instructions. This way, a memory system that tracks memory accesses at\n>>> 423| cache line granularity (and which therefore will see the four snippets\n 424| of <> as identical) will not\n 425| be forced to fail a store-conditional instruction that happens to" + } + ] + }, + { + "parameter_name": "PMLEN", + "classification": "NORM_DIRECT", + "value_type": "value", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'PMLEN'", "Exact parameter name 'PMLEN'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 807, + "line_text": "|00|Pointer masking is disabled (PMLEN = 0)", + "context": " 805| |===\n 806| |Value|Description\n>>> 807| |00|Pointer masking is disabled (PMLEN = 0)\n 808| |01|Reserved\n 809| |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64)" + }, + { + "score": 7, + "reasons": ["Name segment 'PMLEN'", "Exact parameter name 'PMLEN'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 809, + "line_text": "|10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64)", + "context": " 807| |00|Pointer masking is disabled (PMLEN = 0)\n 808| |01|Reserved\n>>> 809| |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64)\n 810| |11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64)\n 811| |===" + }, + { + "score": 7, + "reasons": ["Name segment 'PMLEN'", "Exact parameter name 'PMLEN'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 810, + "line_text": "|11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64)", + "context": " 808| |01|Reserved\n 809| |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64)\n>>> 810| |11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64)\n 811| |===\n 812| " + }, + { + "score": 7, + "reasons": ["Name segment 'PMLEN'", "Exact parameter name 'PMLEN'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2149, + "line_text": "To support implementations where (XLEN-PMLEN) can be less than the GPA width", + "context": " 2147| ====\n 2148| \n>>> 2149| To support implementations where (XLEN-PMLEN) can be less than the GPA width\n 2150| supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with\n 2151| _rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)" + }, + { + "score": 7, + "reasons": ["Name segment 'PMLEN'", "Exact parameter name 'PMLEN'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2151, + "line_text": "_rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)", + "context": " 2149| To support implementations where (XLEN-PMLEN) can be less than the GPA width\n 2150| supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with\n>>> 2151| _rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)\n 2152| is less than GPA width supported by the `hgatp` translation mode of that guest.\n 2153| Specifically, these cases are:" + } + ] + }, + { + "parameter_name": "PMP_GRANULARITY", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 754, + "line_text": "granularity and atomicity, including individual bytes.", + "context": " 752| Cache-block zero instructions store zeros to the set of bytes corresponding to a\n 753| cache block. An implementation may update the bytes in any order and with any\n>>> 754| granularity and atomicity, including individual bytes.\n 755| \n 756| [NOTE]" + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2901, + "line_text": "registers can be provided to specify these attributes at a granularity", + "context": " 2899| region, and can be hardwired into the PMA checker. Where the attributes\n 2900| are run-time configurable, platform-specific memory-mapped control\n>>> 2901| registers can be provided to specify these attributes at a granularity\n 2902| appropriate to each region on the platform (e.g., for an on-chip SRAM\n 2903| that can be flexibly divided between cacheable and uncacheable uses)." + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 3308, + "line_text": "The granularity of PMP access control settings are platform-specific,", + "context": " 3306| checks described in <>.\n 3307| \n>>> 3308| The granularity of PMP access control settings are platform-specific,\n 3309| but the standard PMP encoding supports regions as small as four bytes.\n 3310| Certain regions’ privileges can be hardwired—for example, some regions" + }, + { + "score": 3, + "reasons": ["CSR name 'pmpcfg14' in backticks"], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 3349, + "line_text": "even-numbered CSRs, `pmpcfg0`, `pmpcfg2`, …, `pmpcfg14`, hold the", + "context": " 3347| the configurations `pmp0cfg`–`pmp63cfg` for the 64 PMP entries, as shown\n 3348| in <>. For RV64, eight\n>>> 3349| even-numbered CSRs, `pmpcfg0`, `pmpcfg2`, …, `pmpcfg14`, hold the\n 3350| configurations for the 64 PMP entries, as shown in\n 3351| <>. For RV64, the odd-numbered" + }, + { + "score": 3, + "reasons": [ + "Name segment 'GRANULARITY'", + "Description keyword 'granularity'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 3428, + "line_text": "(TOR). These modes support four-byte granularity.", + "context": " 3426| regions (NAPOT), including the special case of naturally aligned\n 3427| four-byte regions (NA4); and the top boundary of an arbitrary range\n>>> 3428| (TOR). These modes support four-byte granularity.\n 3429| \n 3430| [[pmpcfg-a]]" + } + ] + }, + { + "parameter_name": "PRECISE_SYNCHRONOUS_EXCEPTIONS", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": [ + "Name segment 'EXCEPTIONS'", + "Name segment 'SYNCHRONOUS'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1256, + "line_text": "[#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause", + "context": " 1254| [#norm:mtvec_mode_direct_op]#When MODE=Direct, all traps into\n 1255| machine mode cause the `pc` to be set to the address in the BASE field.#\n>>> 1256| [#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause\n 1257| the `pc` to be set to the address in the BASE field, whereas interrupts\n 1258| cause the `pc` to be set to the address in the BASE field plus four" + }, + { + "score": 4, + "reasons": [ + "Name segment 'EXCEPTIONS'", + "Name segment 'SYNCHRONOUS'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1801, + "line_text": "[#norm:mcause_exccode_pri1]#If an instruction may raise multiple synchronous exceptions, the", + "context": " 1799| ====\n 1800| \n>>> 1801| [#norm:mcause_exccode_pri1]#If an instruction may raise multiple synchronous exceptions, the\n 1802| decreasing priority order of <> indicates which\n 1803| exception is taken and reported in `mcause`.#" + }, + { + "score": 4, + "reasons": [ + "Name segment 'EXCEPTIONS'", + "Name segment 'SYNCHRONOUS'" + ], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 65, + "line_text": "* [#norm:zicflip_forward_trap_async_exception]#Synchronous exceptions with priority higher than that of a software-check", + "context": " 63| \n 64| * [#norm:zicflip_forward_trap_async_interrupt]#Asynchronous interrupts.#\n>>> 65| * [#norm:zicflip_forward_trap_async_exception]#Synchronous exceptions with priority higher than that of a software-check\n 66| exception with `__x__tval` set to \"landing pad fault (code=2)\" (See\n 67| <> of Privileged Specification).#" + }, + { + "score": 4, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'EXCEPTIONS'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 250, + "line_text": "|WRPTR |[#norm:sctrstatus-wrptr]#WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see <>), though there are exceptions when `__x__ctrctl`.RASEMU=1, see <>. For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value.#", + "context": " 248| |===\n 249| |Field |Description\n>>> 250| |WRPTR |[#norm:sctrstatus-wrptr]#WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see <>), though there are exceptions when `__x__ctrctl`.RASEMU=1, see <>. For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value.#\n 251| |FROZEN |[#norm:sctrstatus-frozen_op]#Inhibit transfer recording.# See <>.\n 252| |===" + }, + { + "score": 3, + "reasons": ["Name segment 'EXCEPTIONS'"], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 391, + "line_text": "exceptions and shall not access any caches or memory.# [#norm:cbp_unperm_translate]#During address", + "context": " 389| permitted to access the corresponding physical addresses.# [#norm:cbp_unperm_noexcep]#If access to the cache\n 390| block is not permitted, a cache-block prefetch instruction does not raise any\n>>> 391| exceptions and shall not access any caches or memory.# [#norm:cbp_unperm_translate]#During address\n 392| translation, the instruction does _not_ check the accessed and dirty bits and\n 393| neither raises an exception nor sets the bits.#" + } + ] + }, + { + "parameter_name": "RCID_WIDTH", + "classification": "NORM_CSR_WARL", + "value_type": "range", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Description keyword 'RCID'", + "CSR name 'srmcfg' in backticks", + "Name segment 'RCID'", + "CSR field name 'RCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2586, + "line_text": "The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege", + "context": " 2584| ....\n 2585| \n>>> 2586| The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege\n 2587| modes of software execution on that hart by default, but this behavior may be\n 2588| overridden by future extensions." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'RCID'", + "Name segment 'RCID'", + "Description keyword 'ID'", + "CSR field name 'RCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2531, + "line_text": "Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). These identifiers", + "context": " 2529| To facilitate this, the QoS Identifiers extension (Ssqosid) introduces the\n 2530| `srmcfg` register, which configures a hart with two identifiers: a Resource\n>>> 2531| Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). These identifiers\n 2532| accompany each request issued by the hart to shared resource controllers.\n 2533| " + }, + { + "score": 7, + "reasons": [ + "Description keyword 'RCID'", + "Name segment 'RCID'", + "Description keyword 'ID'", + "CSR field name 'RCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2551, + "line_text": "Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). Both `RCID`", + "context": " 2549| \n 2550| The `srmcfg` register is an SXLEN-bit read/write register used to configure a\n>>> 2551| Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). Both `RCID`\n 2552| and `MCID` are WARL fields. The register is formatted as shown in <>\n 2553| when SXLEN=64 and <> when SXLEN=32." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'RCID'", + "Name segment 'RCID'", + "CSR field name 'RCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2535, + "line_text": "originating supervisor domain, can accompany `RCID` and `MCID`. Resource", + "context": " 2533| \n 2534| Additional metadata, like the nature of the memory access and the ID of the\n>>> 2535| originating supervisor domain, can accompany `RCID` and `MCID`. Resource\n 2536| controllers may use this metadata for differentiated service such as a different\n 2537| capacity allocation for code storage vs. data storage. Resource controllers can" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'RCID'", + "Name segment 'RCID'", + "CSR field name 'RCID'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 2543, + "line_text": "resource usage limits and monitoring resource consumption. The `RCID` controls", + "context": " 2541| These identifiers are crucial for the RISC-V Capacity and Bandwidth Controller\n 2542| QoS Register Interface (CBQRI) specification, which provides methods for setting\n>>> 2543| resource usage limits and monitoring resource consumption. The `RCID` controls\n 2544| resource allocations, while the `MCID` is used for tracking resource usage.\n 2545| " + } + ] + }, + { + "parameter_name": "REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 9, + "reasons": [ + "Name segment 'SOFTWARE'", + "Name segment 'CHECK'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2117, + "line_text": "On a trap caused by a software-check exception, the `mtval` register holds", + "context": " 2115| ====\n 2116| \n>>> 2117| On a trap caused by a software-check exception, the `mtval` register holds\n 2118| the cause for the exception. The following encodings are defined:\n 2119| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'SOFTWARE'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1814, + "line_text": "information, alongside `mtval`, to assist software in handling the trap.", + "context": " 1812| shown in <>. When a trap is taken into\n 1813| M-mode, `mtval2` is written with additional exception-specific\n>>> 1814| information, alongside `mtval`, to assist software in handling the trap.\n 1815| \n 1816| [[mtval2reg]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'SOFTWARE'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2034, + "line_text": "information to assist software in handling the trap. Otherwise, `mtval`", + "context": " 2032| shown in <>. When a trap is taken into\n 2033| M-mode, `mtval` is either set to zero or written with exception-specific\n>>> 2034| information to assist software in handling the trap. Otherwise, `mtval`\n 2035| is never written by the implementation, though it may be explicitly\n 2036| written by software. The hardware platform will specify which exceptions" + } + ] + }, + { + "parameter_name": "REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 9, + "reasons": [ + "Name segment 'SOFTWARE'", + "Name segment 'CHECK'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2117, + "line_text": "On a trap caused by a software-check exception, the `mtval` register holds", + "context": " 2115| ====\n 2116| \n>>> 2117| On a trap caused by a software-check exception, the `mtval` register holds\n 2118| the cause for the exception. The following encodings are defined:\n 2119| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'SOFTWARE'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1814, + "line_text": "information, alongside `mtval`, to assist software in handling the trap.", + "context": " 1812| shown in <>. When a trap is taken into\n 1813| M-mode, `mtval2` is written with additional exception-specific\n>>> 1814| information, alongside `mtval`, to assist software in handling the trap.\n 1815| \n 1816| [[mtval2reg]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'SOFTWARE'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2034, + "line_text": "information to assist software in handling the trap. Otherwise, `mtval`", + "context": " 2032| shown in <>. When a trap is taken into\n 2033| M-mode, `mtval` is either set to zero or written with exception-specific\n>>> 2034| information to assist software in handling the trap. Otherwise, `mtval`\n 2035| is never written by the implementation, though it may be explicitly\n 2036| written by software. The hardware platform will specify which exceptions" + } + ] + }, + { + "parameter_name": "REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 9, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'SOFTWARE'", + "Description keyword 'stval'", + "Name segment 'CHECK'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 763, + "line_text": "On a trap caused by a software-check exception, the `stval` register holds the", + "context": " 761| \n 762| [[norm:stval_exception_info]]\n>>> 763| On a trap caused by a software-check exception, the `stval` register holds the\n 764| cause for the exception. The following encodings are defined:\n 765| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'SOFTWARE'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 910, + "line_text": "information, alongside `stval`, to assist software in handling the trap.", + "context": " 908| shown in <>. When a trap is taken into\n 909| HS-mode, `htval` is written with additional exception-specific\n>>> 910| information, alongside `stval`, to assist software in handling the trap.\n 911| \n 912| [[htvalreg]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'SOFTWARE'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 711, + "line_text": "software in handling the trap. Otherwise, `stval` is never written by", + "context": " 709| shown in <>. When a trap is taken into\n 710| S-mode, `stval` is written with exception-specific information to assist\n>>> 711| software in handling the trap. Otherwise, `stval` is never written by\n 712| the implementation, though it may be explicitly written by software. The\n 713| hardware platform will specify which exceptions must set `stval`" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + } + ] + }, + { + "parameter_name": "REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 9, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'SOFTWARE'", + "Description keyword 'stval'", + "Name segment 'CHECK'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 763, + "line_text": "On a trap caused by a software-check exception, the `stval` register holds the", + "context": " 761| \n 762| [[norm:stval_exception_info]]\n>>> 763| On a trap caused by a software-check exception, the `stval` register holds the\n 764| cause for the exception. The following encodings are defined:\n 765| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'SOFTWARE'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 910, + "line_text": "information, alongside `stval`, to assist software in handling the trap.", + "context": " 908| shown in <>. When a trap is taken into\n 909| HS-mode, `htval` is written with additional exception-specific\n>>> 910| information, alongside `stval`, to assist software in handling the trap.\n 911| \n 912| [[htvalreg]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'SOFTWARE'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 711, + "line_text": "software in handling the trap. Otherwise, `stval` is never written by", + "context": " 709| shown in <>. When a trap is taken into\n 710| S-mode, `stval` is written with exception-specific information to assist\n>>> 711| software in handling the trap. Otherwise, `stval` is never written by\n 712| the implementation, though it may be explicitly written by software. The\n 713| hardware platform will specify which exceptions must set `stval`" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + } + ] + }, + { + "parameter_name": "REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'ILLEGAL'", + "Description keyword 'instruction'", + "Name segment 'MTVAL'", + "Name segment 'INSTRUCTION'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2082, + "line_text": "nonzero value when an illegal-instruction exception occurs, then `mtval`", + "context": " 2080| instruction bits on an illegal-instruction exception (`mepc` points to\n 2081| the faulting instruction in memory). If `mtval` is written with a\n>>> 2082| nonzero value when an illegal-instruction exception occurs, then `mtval`\n 2083| will contain the shortest of:\n 2084| " + }, + { + "score": 11, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'ILLEGAL'", + "Description keyword 'instruction'", + "Name segment 'MTVAL'", + "Name segment 'INSTRUCTION'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2091, + "line_text": "The value loaded into `mtval` on an illegal-instruction exception is", + "context": " 2089| * the first MXLEN bits of the faulting instruction\n 2090| \n>>> 2091| The value loaded into `mtval` on an illegal-instruction exception is\n 2092| right-justified and all unused upper bits are cleared to zero.\n 2093| " + }, + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1840, + "line_text": "the instruction as indicated by the virtual address in `mtval`.", + "context": " 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of\n>>> 1840| the instruction as indicated by the virtual address in `mtval`.\n 1841| \n 1842| [[norm:mtval2_val]]" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + } + ] + }, + { + "parameter_name": "REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'ILLEGAL'", + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 751, + "line_text": "nonzero value when an illegal-instruction exception occurs, then `stval`", + "context": " 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a\n>>> 751| nonzero value when an illegal-instruction exception occurs, then `stval`\n 752| will contain the shortest of:\n 753| " + }, + { + "score": 11, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'ILLEGAL'", + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 759, + "line_text": "The value loaded into `stval` on an illegal-instruction exception is", + "context": " 757| \n 758| [[norm:stval_op_illegal_instr_format]]\n>>> 759| The value loaded into `stval` on an illegal-instruction exception is\n 760| right-justified and all unused upper bits are cleared to zero.\n 761| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 936, + "line_text": "the instruction as indicated by the virtual address in `stval`.", + "context": " 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of\n>>> 936| the instruction as indicated by the virtual address in `stval`.\n 937| \n 938| [NOTE]" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1305, + "line_text": "address of the instruction that took the trap; the `stval` register is", + "context": " 1303| [#norm:trap_del_S-mode_op]#the `scause` register is written\n 1304| with the trap cause; the `sepc` register is written with the virtual\n>>> 1305| address of the instruction that took the trap; the `stval` register is\n 1306| written with an exception-specific datum; the SPP field of `mstatus` is\n 1307| written with the active privilege mode at the time of the trap; the SPIE" + } + ] + }, + { + "parameter_name": "REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Name segment 'VSTVAL'", + "Name segment 'VIRTUAL'", + "Description keyword 'vstval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'VSTVAL'", + "Name segment 'VIRTUAL'", + "Description keyword 'vstval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1379, + "line_text": ".Virtual supervisor trap value register (`vstval`).", + "context": " 1377| \n 1378| [[vstvalreg]]\n>>> 1379| .Virtual supervisor trap value register (`vstval`).\n 1380| include::images/bytefield/vstvalreg.edn[]\n 1381| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + } + ] + }, + { + "parameter_name": "REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'HTVAL'", + "Name segment 'PAGE'", + "Description keyword 'htval'", + "Name segment 'GUEST'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 917, + "line_text": "When a guest-page-fault trap is taken into HS-mode, `htval` is written", + "context": " 915| \n 916| [[norm:htval_trapval_param]]\n>>> 917| When a guest-page-fault trap is taken into HS-mode, `htval` is written\n 918| with either zero or the guest physical address that faulted, shifted\n 919| right by 2 bits. For other traps, `htval` is set to zero, but a future" + }, + { + "score": 8, + "reasons": [ + "Name segment 'HTVAL'", + "Description keyword 'htval'", + "Name segment 'GUEST'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 932, + "line_text": "a nonzero guest physical address in `htval` corresponds to the faulting", + "context": " 930| \n 931| Otherwise, for misaligned loads and stores that cause guest-page faults,\n>>> 932| a nonzero guest physical address in `htval` corresponds to the faulting\n 933| portion of the access as indicated by the virtual address in `stval`.\n 934| For instruction guest-page faults on systems with variable-length" + }, + { + "score": 8, + "reasons": [ + "Name segment 'HTVAL'", + "Description keyword 'htval'", + "Name segment 'GUEST'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2047, + "line_text": "faulting guest virtual address as usual, and `mtval2` or `htval` is", + "context": " 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n>>> 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written" + }, + { + "score": 7, + "reasons": ["Name segment 'HTVAL'", "Description keyword 'htval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 120, + "line_text": "`htimedeltah`, `htval`, `htinst`, and `hgatp`.#", + "context": " 118| VS-mode guest: `hstatus`, `hedeleg`, `hideleg`, `hvip`, `hip`, `hie`,\n 119| `hgeip`, `hgeie`, `henvcfg`, `henvcfgh`, `hcounteren`, `htimedelta`,\n>>> 120| `htimedeltah`, `htval`, `htinst`, and `hgatp`.#\n 121| \n 122| Furthermore, several _virtual supervisor_ CSRs (VS CSRs) are replicas of" + }, + { + "score": 7, + "reasons": ["Name segment 'HTVAL'", "Description keyword 'htval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 904, + "line_text": "==== Hypervisor Trap Value (`htval`) Register", + "context": " 902| must be implemented.\n 903| \n>>> 904| ==== Hypervisor Trap Value (`htval`) Register\n 905| \n 906| [[norm:htval_sz_acc_op]]" + } + ] + }, + { + "parameter_name": "REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'VALUE'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2832, + "line_text": "`mtval2` or `htval`. If both conditions are met, the value written to", + "context": " 2830| implicit memory access for VS-stage address translation, and (b) a\n 2831| nonzero value (the faulting guest physical address) is written to\n>>> 2832| `mtval2` or `htval`. If both conditions are met, the value written to\n 2833| `mtinst` or `htinst` must be taken from\n 2834| <>; zero is not allowed." + }, + { + "score": 7, + "reasons": [ + "Name segment 'INSTRUCTION'", + "CSR field name 'VALUE'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 310, + "line_text": "[#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value", + "context": " 308| valid only when _rd_≠`x0`; the code points with _rd_=`x0` are reserved.#\n 309| \n>>> 310| [#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value\n 311| from memory into register _rd_. It computes its effective address by\n 312| adding the zero-extended offset, scaled by 8, to the stack pointer," + }, + { + "score": 7, + "reasons": [ + "Name segment 'INSTRUCTION'", + "CSR field name 'VALUE'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 340, + "line_text": "[#norm:c-sdsp_op]#C.SDSP is an RV64C-only instruction that stores a 64-bit value in", + "context": " 338| the stack pointer, `x2`. It expands to `sw rs2, offset(x2)`.#\n 339| \n>>> 340| [#norm:c-sdsp_op]#C.SDSP is an RV64C-only instruction that stores a 64-bit value in\n 341| register _rs2_ to memory. It computes an effective address by adding the\n 342| _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It" + }, + { + "score": 7, + "reasons": [ + "Name segment 'INSTRUCTION'", + "CSR field name 'VALUE'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 411, + "line_text": "[#norm:c-ld_op]#C.LD is an RV64C-only instruction that loads a 64-bit value from", + "context": " 409| `_rs1′_`. It expands to `lw rd′, offset(rs1′)`.#\n 410| \n>>> 411| [#norm:c-ld_op]#C.LD is an RV64C-only instruction that loads a 64-bit value from\n 412| memory into register `_rd′_`. It computes an effective\n 413| address by adding the _zero_-extended offset, scaled by 8, to the base" + }, + { + "score": 7, + "reasons": [ + "Name segment 'INSTRUCTION'", + "CSR field name 'VALUE'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 443, + "line_text": "[#norm:c-sd_op]#C.SD is an RV64C-only instruction that stores a 64-bit value in", + "context": " 441| expands to `sw rs2′, offset(rs1′)`.#\n 442| \n>>> 443| [#norm:c-sd_op]#C.SD is an RV64C-only instruction that stores a 64-bit value in\n 444| register `_rs2′_` to memory. It computes an effective\n 445| address by adding the _zero_-extended offset, scaled by 8, to the base" + } + ] + }, + { + "parameter_name": "REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'VALUE'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2832, + "line_text": "`mtval2` or `htval`. If both conditions are met, the value written to", + "context": " 2830| implicit memory access for VS-stage address translation, and (b) a\n 2831| nonzero value (the faulting guest physical address) is written to\n>>> 2832| `mtval2` or `htval`. If both conditions are met, the value written to\n 2833| `mtinst` or `htinst` must be taken from\n 2834| <>; zero is not allowed." + }, + { + "score": 7, + "reasons": [ + "Name segment 'GUEST'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2047, + "line_text": "faulting guest virtual address as usual, and `mtval2` or `htval` is", + "context": " 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n>>> 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written" + }, + { + "score": 6, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 917, + "line_text": "When a guest-page-fault trap is taken into HS-mode, `htval` is written", + "context": " 915| \n 916| [[norm:htval_trapval_param]]\n>>> 917| When a guest-page-fault trap is taken into HS-mode, `htval` is written\n 918| with either zero or the guest physical address that faulted, shifted\n 919| right by 2 bits. For other traps, `htval` is set to zero, but a future" + }, + { + "score": 6, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "CSR name 'mtval2' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1822, + "line_text": "When a guest-page-fault trap is taken into M-mode, `mtval2` is written", + "context": " 1820| \n 1821| [[norm:mtval2_trapval_param]]\n>>> 1822| When a guest-page-fault trap is taken into M-mode, `mtval2` is written\n 1823| with either zero or the guest physical address that faulted, shifted\n 1824| right by 2 bits. For other traps, `mtval2` is set to zero, but a future" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2066, + "line_text": "to `mtval2`/`htval` shall correspond to the exact virtual address", + "context": " 2064| When a guest-page fault is not due to an implicit memory access for\n 2065| VS-stage address translation, a nonzero guest physical address written\n>>> 2066| to `mtval2`/`htval` shall correspond to the exact virtual address\n 2067| written to `mtval`/`stval`.\n 2068| " + } + ] + }, + { + "parameter_name": "REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'VALUE'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2832, + "line_text": "`mtval2` or `htval`. If both conditions are met, the value written to", + "context": " 2830| implicit memory access for VS-stage address translation, and (b) a\n 2831| nonzero value (the faulting guest physical address) is written to\n>>> 2832| `mtval2` or `htval`. If both conditions are met, the value written to\n 2833| `mtinst` or `htinst` must be taken from\n 2834| <>; zero is not allowed." + }, + { + "score": 7, + "reasons": [ + "Name segment 'GUEST'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2047, + "line_text": "faulting guest virtual address as usual, and `mtval2` or `htval` is", + "context": " 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n>>> 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written" + }, + { + "score": 6, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 917, + "line_text": "When a guest-page-fault trap is taken into HS-mode, `htval` is written", + "context": " 915| \n 916| [[norm:htval_trapval_param]]\n>>> 917| When a guest-page-fault trap is taken into HS-mode, `htval` is written\n 918| with either zero or the guest physical address that faulted, shifted\n 919| right by 2 bits. For other traps, `htval` is set to zero, but a future" + }, + { + "score": 6, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "CSR name 'mtval2' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1822, + "line_text": "When a guest-page-fault trap is taken into M-mode, `mtval2` is written", + "context": " 1820| \n 1821| [[norm:mtval2_trapval_param]]\n>>> 1822| When a guest-page-fault trap is taken into M-mode, `mtval2` is written\n 1823| with either zero or the guest physical address that faulted, shifted\n 1824| right by 2 bits. For other traps, `mtval2` is set to zero, but a future" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2066, + "line_text": "to `mtval2`/`htval` shall correspond to the exact virtual address", + "context": " 2064| When a guest-page fault is not due to an implicit memory access for\n 2065| VS-stage address translation, a nonzero guest physical address written\n>>> 2066| to `mtval2`/`htval` shall correspond to the exact virtual address\n 2067| written to `mtval`/`stval`.\n 2068| " + } + ] + }, + { + "parameter_name": "REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'VALUE'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2832, + "line_text": "`mtval2` or `htval`. If both conditions are met, the value written to", + "context": " 2830| implicit memory access for VS-stage address translation, and (b) a\n 2831| nonzero value (the faulting guest physical address) is written to\n>>> 2832| `mtval2` or `htval`. If both conditions are met, the value written to\n 2833| `mtinst` or `htinst` must be taken from\n 2834| <>; zero is not allowed." + }, + { + "score": 7, + "reasons": [ + "Name segment 'GUEST'", + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2047, + "line_text": "faulting guest virtual address as usual, and `mtval2` or `htval` is", + "context": " 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n>>> 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written" + }, + { + "score": 6, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 917, + "line_text": "When a guest-page-fault trap is taken into HS-mode, `htval` is written", + "context": " 915| \n 916| [[norm:htval_trapval_param]]\n>>> 917| When a guest-page-fault trap is taken into HS-mode, `htval` is written\n 918| with either zero or the guest physical address that faulted, shifted\n 919| right by 2 bits. For other traps, `htval` is set to zero, but a future" + }, + { + "score": 6, + "reasons": [ + "Name segment 'GUEST'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "CSR name 'mtval2' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1822, + "line_text": "When a guest-page-fault trap is taken into M-mode, `mtval2` is written", + "context": " 1820| \n 1821| [[norm:mtval2_trapval_param]]\n>>> 1822| When a guest-page-fault trap is taken into M-mode, `mtval2` is written\n 1823| with either zero or the guest physical address that faulted, shifted\n 1824| right by 2 bits. For other traps, `mtval2` is set to zero, but a future" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtval2' in backticks", + "CSR name 'htval' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2066, + "line_text": "to `mtval2`/`htval` shall correspond to the exact virtual address", + "context": " 2064| When a guest-page fault is not due to an implicit memory access for\n 2065| VS-stage address translation, a nonzero guest physical address written\n>>> 2066| to `mtval2`/`htval` shall correspond to the exact virtual address\n 2067| written to `mtval`/`stval`.\n 2068| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_BREAKPOINT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 17, + "candidates": [ + { + "score": 17, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'MTVAL'", + "Name segment 'BREAKPOINT'", + "Description keyword 'EBREAK'", + "Description keyword 'breakpoint'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2049, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`", + "context": " 2047| faulting virtual address.\n 2048| \n>>> 2049| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`\n 2050| is written with either zero or the virtual address of the instruction.\n 2051| " + }, + { + "score": 15, + "reasons": [ + "Description keyword 'mepc'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 13, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 13, + "reasons": [ + "Description keyword 'breakpoint'", + "Description keyword 'mtval'", + "Name segment 'BREAKPOINT'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2043, + "line_text": "If `mtval` is written with a nonzero value when a breakpoint,", + "context": " 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n>>> 2043| If `mtval` is written with a nonzero value when a breakpoint,\n 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an" + }, + { + "score": 11, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1840, + "line_text": "the instruction as indicated by the virtual address in `mtval`.", + "context": " 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of\n>>> 1840| the instruction as indicated by the virtual address in `mtval`.\n 1841| \n 1842| [[norm:mtval2_val]]" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2049, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`", + "context": " 2047| faulting virtual address.\n 2048| \n>>> 2049| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`\n 2050| is written with either zero or the virtual address of the instruction.\n 2051| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1840, + "line_text": "the instruction as indicated by the virtual address in `mtval`.", + "context": " 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of\n>>> 1840| the instruction as indicated by the virtual address in `mtval`.\n 1841| \n 1842| [[norm:mtval2_val]]" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2049, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`", + "context": " 2047| faulting virtual address.\n 2048| \n>>> 2049| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`\n 2050| is written with either zero or the virtual address of the instruction.\n 2051| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1840, + "line_text": "the instruction as indicated by the virtual address in `mtval`.", + "context": " 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of\n>>> 1840| the instruction as indicated by the virtual address in `mtval`.\n 1841| \n 1842| [[norm:mtval2_val]]" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + }, + { + "score": 10, + "reasons": [ + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2049, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`", + "context": " 2047| faulting virtual address.\n 2048| \n>>> 2049| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval`\n 2050| is written with either zero or the virtual address of the instruction.\n 2051| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'ACCESS'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1837, + "line_text": "portion of the access as indicated by the virtual address in `mtval`.", + "context": " 1835| Otherwise, for misaligned loads and stores that cause guest-page faults,\n 1836| a nonzero guest physical address in `mtval2` corresponds to the faulting\n>>> 1837| portion of the access as indicated by the virtual address in `mtval`.\n 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'FAULT'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'MTVAL'", + "Name segment 'LOAD'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2067, + "line_text": "If `mtval` is written with a nonzero value when a misaligned load or", + "context": " 2065| \n 2066| \n>>> 2067| If `mtval` is written with a nonzero value when a misaligned load or\n 2068| store causes an access-fault, page-fault, or hardware-error exception,\n 2069| then `mtval` will" + }, + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'LOAD'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": [ + "Name segment 'PAGE'", + "Description keyword 'mtval'", + "Name segment 'FAULT'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'LOAD'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'ACCESS'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1837, + "line_text": "portion of the access as indicated by the virtual address in `mtval`.", + "context": " 1835| Otherwise, for misaligned loads and stores that cause guest-page faults,\n 1836| a nonzero guest physical address in `mtval2` corresponds to the faulting\n>>> 1837| portion of the access as indicated by the virtual address in `mtval`.\n 1838| For instruction guest-page faults on systems with variable-length\n 1839| instructions, a nonzero `mtval2` corresponds to the faulting portion of" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'FAULT'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 10, + "reasons": [ + "Description keyword 'mtval'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2067, + "line_text": "If `mtval` is written with a nonzero value when a misaligned load or", + "context": " 2065| \n 2066| \n>>> 2067| If `mtval` is written with a nonzero value when a misaligned load or\n 2068| store causes an access-fault, page-fault, or hardware-error exception,\n 2069| then `mtval` will" + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + }, + { + "score": 8, + "reasons": [ + "Name segment 'STORE'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 9, + "reasons": [ + "Name segment 'PAGE'", + "Description keyword 'mtval'", + "Name segment 'FAULT'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 9, + "reasons": ["Description keyword 'mtval'", "Name segment 'MTVAL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1310, + "line_text": "[#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of", + "context": " 1308| field of `mstatus` is written with the value of the SIE field at the\n 1309| time of the trap; and the SIE field of `mstatus` is cleared.#\n>>> 1310| [#norm:trap_del_S-mode_no_M-mode]#The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of\n 1311| `mstatus` are not written.#\n 1312| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2041, + "line_text": "to a nonzero value, then `mtval` is read-only zero.", + "context": " 2039| that caused the exception.\n 2040| If the hardware platform specifies that no exceptions set `mtval`\n>>> 2041| to a nonzero value, then `mtval` is read-only zero.\n 2042| \n 2043| If `mtval` is written with a nonzero value when a breakpoint," + }, + { + "score": 8, + "reasons": [ + "Name segment 'STORE'", + "Description keyword 'mtval'", + "Name segment 'MTVAL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2046, + "line_text": "instruction fetch, load, or store, then `mtval` will contain the", + "context": " 2044| address-misaligned, access-fault, page-fault, or hardware-error exception\n 2045| occurs on an\n>>> 2046| instruction fetch, load, or store, then `mtval` will contain the\n 2047| faulting virtual address.\n 2048| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_BREAKPOINT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 17, + "candidates": [ + { + "score": 17, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'BREAKPOINT'", + "Description keyword 'EBREAK'", + "Description keyword 'breakpoint'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 726, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`", + "context": " 724| \n 725| [[norm:stval_op_breakpoint]]\n>>> 726| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`\n 727| is written with either zero or the virtual address of the instruction.\n 728| " + }, + { + "score": 13, + "reasons": [ + "Description keyword 'breakpoint'", + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'BREAKPOINT'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 719, + "line_text": "If `stval` is written with a nonzero value when a breakpoint,", + "context": " 717| \n 718| [[norm:stval_op_faulting_addr]]\n>>> 719| If `stval` is written with a nonzero value when a breakpoint,\n 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an" + }, + { + "score": 12, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 11, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + }, + { + "score": 10, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 325, + "line_text": "guest virtual address to `stval`, GVA is set to 1. For any other trap", + "context": " 323| whenever a trap is taken into HS-mode. For any trap (breakpoint, address\n 324| misaligned, access fault, page fault, or guest-page fault) that writes a\n>>> 325| guest virtual address to `stval`, GVA is set to 1. For any other trap\n 326| into HS-mode, GVA is set to 0.\n 327| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 936, + "line_text": "the instruction as indicated by the virtual address in `stval`.", + "context": " 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of\n>>> 936| the instruction as indicated by the virtual address in `stval`.\n 937| \n 938| [NOTE]" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1305, + "line_text": "address of the instruction that took the trap; the `stval` register is", + "context": " 1303| [#norm:trap_del_S-mode_op]#the `scause` register is written\n 1304| with the trap cause; the `sepc` register is written with the virtual\n>>> 1305| address of the instruction that took the trap; the `stval` register is\n 1306| written with an exception-specific datum; the SPP field of `mstatus` is\n 1307| written with the active privilege mode at the time of the trap; the SPIE" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 726, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`", + "context": " 724| \n 725| [[norm:stval_op_breakpoint]]\n>>> 726| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`\n 727| is written with either zero or the virtual address of the instruction.\n 728| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 13, + "candidates": [ + { + "score": 13, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'instruction'", + "Description keyword 'C'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 726, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`", + "context": " 724| \n 725| [[norm:stval_op_breakpoint]]\n>>> 726| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`\n 727| is written with either zero or the virtual address of the instruction.\n 728| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 936, + "line_text": "the instruction as indicated by the virtual address in `stval`.", + "context": " 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of\n>>> 936| the instruction as indicated by the virtual address in `stval`.\n 937| \n 938| [NOTE]" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1305, + "line_text": "address of the instruction that took the trap; the `stval` register is", + "context": " 1303| [#norm:trap_del_S-mode_op]#the `scause` register is written\n 1304| with the trap cause; the `sepc` register is written with the virtual\n>>> 1305| address of the instruction that took the trap; the `stval` register is\n 1306| written with an exception-specific datum; the SPP field of `mstatus` is\n 1307| written with the active privilege mode at the time of the trap; the SPIE" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 936, + "line_text": "the instruction as indicated by the virtual address in `stval`.", + "context": " 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of\n>>> 936| the instruction as indicated by the virtual address in `stval`.\n 937| \n 938| [NOTE]" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2405, + "line_text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as", + "context": " 2403| \n 2404| [[norm:H_virtinst_xtval]]\n>>> 2405| On a virtual-instruction trap, `mtval` or `stval` is written the same as\n 2406| for an illegal-instruction trap.\n 2407| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 1305, + "line_text": "address of the instruction that took the trap; the `stval` register is", + "context": " 1303| [#norm:trap_del_S-mode_op]#the `scause` register is written\n 1304| with the trap cause; the `sepc` register is written with the virtual\n>>> 1305| address of the instruction that took the trap; the `stval` register is\n 1306| written with an exception-specific datum; the SPP field of `mstatus` is\n 1307| written with the active privilege mode at the time of the trap; the SPIE" + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'INSTRUCTION'", + "Description keyword 'stval'", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 726, + "line_text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`", + "context": " 724| \n 725| [[norm:stval_op_breakpoint]]\n>>> 726| On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval`\n 727| is written with either zero or the virtual address of the instruction.\n 728| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'ACCESS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 933, + "line_text": "portion of the access as indicated by the virtual address in `stval`.", + "context": " 931| Otherwise, for misaligned loads and stores that cause guest-page faults,\n 932| a nonzero guest physical address in `htval` corresponds to the faulting\n>>> 933| portion of the access as indicated by the virtual address in `stval`.\n 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'FAULT'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'LOAD'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'LOAD'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 734, + "line_text": "If `stval` is written with a nonzero value when a misaligned load or", + "context": " 732| \n 733| [[norm:stval_op_load_store_fault]]\n>>> 734| If `stval` is written with a nonzero value when a misaligned load or\n 735| store causes an access-fault, page-fault, or hardware-error exception,\n 736| then `stval` will" + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'LOAD'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 734, + "line_text": "If `stval` is written with a nonzero value when a misaligned load or", + "context": " 732| \n 733| [[norm:stval_op_load_store_fault]]\n>>> 734| If `stval` is written with a nonzero value when a misaligned load or\n 735| store causes an access-fault, page-fault, or hardware-error exception,\n 736| then `stval` will" + }, + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'LOAD'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + }, + { + "score": 7, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 325, + "line_text": "guest virtual address to `stval`, GVA is set to 1. For any other trap", + "context": " 323| whenever a trap is taken into HS-mode. For any trap (breakpoint, address\n 324| misaligned, access fault, page fault, or guest-page fault) that writes a\n>>> 325| guest virtual address to `stval`, GVA is set to 1. For any other trap\n 326| into HS-mode, GVA is set to 0.\n 327| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'LOAD'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'LOAD'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 734, + "line_text": "If `stval` is written with a nonzero value when a misaligned load or", + "context": " 732| \n 733| [[norm:stval_op_load_store_fault]]\n>>> 734| If `stval` is written with a nonzero value when a misaligned load or\n 735| store causes an access-fault, page-fault, or hardware-error exception,\n 736| then `stval` will" + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'ACCESS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 933, + "line_text": "portion of the access as indicated by the virtual address in `stval`.", + "context": " 931| Otherwise, for misaligned loads and stores that cause guest-page faults,\n 932| a nonzero guest physical address in `htval` corresponds to the faulting\n>>> 933| portion of the access as indicated by the virtual address in `stval`.\n 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'FAULT'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'STORE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 734, + "line_text": "If `stval` is written with a nonzero value when a misaligned load or", + "context": " 732| \n 733| [[norm:stval_op_load_store_fault]]\n>>> 734| If `stval` is written with a nonzero value when a misaligned load or\n 735| store causes an access-fault, page-fault, or hardware-error exception,\n 736| then `stval` will" + }, + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'STORE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + }, + { + "score": 7, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 325, + "line_text": "guest virtual address to `stval`, GVA is set to 1. For any other trap", + "context": " 323| whenever a trap is taken into HS-mode. For any trap (breakpoint, address\n 324| misaligned, access fault, page fault, or guest-page fault) that writes a\n>>> 325| guest virtual address to `stval`, GVA is set to 1. For any other trap\n 326| into HS-mode, GVA is set to 0.\n 327| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'STVAL'", + "Name segment 'PAGE'", + "Name segment 'FAULT'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2046, + "line_text": "modes. On a guest-page fault, CSR `mtval` or `stval` is written with the", + "context": " 2044| Guest-page-fault traps may be delegated from M-mode to HS-mode under the\n 2045| control of CSR `medeleg`, but cannot be delegated to other privilege\n>>> 2046| modes. On a guest-page fault, CSR `mtval` or `stval` is written with the\n 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address," + }, + { + "score": 9, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 8, + "reasons": [ + "Name segment 'STVAL'", + "Description keyword 'stval'", + "Name segment 'STORE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 722, + "line_text": "instruction fetch, load, or store, then `stval` will contain the", + "context": " 720| address-misaligned, access-fault, page-fault, or hardware-error exception\n 721| occurs on an\n>>> 722| instruction fetch, load, or store, then `stval` will contain the\n 723| faulting virtual address.\n 724| " + }, + { + "score": 8, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'STVAL'", + "Description keyword 'stval'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 748, + "line_text": "The `stval` register can optionally also be used to return the faulting", + "context": " 746| \n 747| [[norm:stval_op_illegal_instr]]\n>>> 748| The `stval` register can optionally also be used to return the faulting\n 749| instruction bits on an illegal-instruction exception (`sepc` points to\n 750| the faulting instruction in memory). If `stval` is written with a" + }, + { + "score": 7, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 325, + "line_text": "guest virtual address to `stval`, GVA is set to 1. For any other trap", + "context": " 323| whenever a trap is taken into HS-mode. For any trap (breakpoint, address\n 324| misaligned, access fault, page fault, or guest-page fault) that writes a\n>>> 325| guest virtual address to `stval`, GVA is set to 1. For any other trap\n 326| into HS-mode, GVA is set to 0.\n 327| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_BREAKPOINT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 10, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 10, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 10, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 10, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Description keyword 'PC'", + "Name segment 'ACCESS'", + "Name segment 'FAULT'", + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'" + ], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 1183, + "line_text": "[#norm:Zcmp_trap]#If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and _xCAUSE_ updated with the type of trap.#", + "context": " 1181| The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.\n 1182| \n>>> 1183| [#norm:Zcmp_trap]#If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and _xCAUSE_ updated with the type of trap.#\n 1184| \n 1185| [[norm:interrupts_allowed_in_pushpop_param]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'VSTVAL'", + "Description keyword 'vstval'", + "Name segment 'ACCESS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 8, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'FAULT'", + "Description keyword 'PC'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2359, + "line_text": "[#norm:Zcmt_trap]#If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.#", + "context": " 2357| if the tables have not been updated in memory since the last _fence.i_.\n 2358| \n>>> 2359| [#norm:Zcmt_trap]#If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.#\n 2360| \n 2361| <<<" + }, + { + "score": 7, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'FAULT'", + "Description keyword 'instruction'", + "Name segment 'ACCESS'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 383, + "line_text": "access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction", + "context": " 381| cache-block zero instruction raises a store page-fault or store guest-page-fault\n 382| exception if address translation does not permit write access or raises a store\n>>> 383| access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction\n 384| also checks the accessed and dirty bits and may either raise an exception or set\n 385| the bits as required.#" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Description keyword 'C'", + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 310, + "line_text": "[#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value", + "context": " 308| valid only when _rd_≠`x0`; the code points with _rd_=`x0` are reserved.#\n 309| \n>>> 310| [#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value\n 311| from memory into register _rd_. It computes its effective address by\n 312| adding the zero-extended offset, scaled by 8, to the stack pointer," + }, + { + "score": 8, + "reasons": [ + "Description keyword 'C'", + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 318, + "line_text": "[#norm:c-flwsp_op]#C.FLWSP is an RV32FC-only instruction that loads a single-precision", + "context": " 316| _rd_=`x0` are reserved.#\n 317| \n>>> 318| [#norm:c-flwsp_op]#C.FLWSP is an RV32FC-only instruction that loads a single-precision\n 319| floating-point value from memory into floating-point register _rd_. It\n 320| computes its effective address by adding the _zero_-extended offset," + }, + { + "score": 8, + "reasons": [ + "Description keyword 'C'", + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 324, + "line_text": "[#norm:c-fldsp_op]#C.FLDSP is an RV32DC/RV64DC-only instruction that loads a", + "context": " 322| `flw rd, offset(x2)`.#\n 323| \n>>> 324| [#norm:c-fldsp_op]#C.FLDSP is an RV32DC/RV64DC-only instruction that loads a\n 325| double-precision floating-point value from memory into floating-point\n 326| register _rd_. It computes its effective address by adding the" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'C'", + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 340, + "line_text": "[#norm:c-sdsp_op]#C.SDSP is an RV64C-only instruction that stores a 64-bit value in", + "context": " 338| the stack pointer, `x2`. It expands to `sw rs2, offset(x2)`.#\n 339| \n>>> 340| [#norm:c-sdsp_op]#C.SDSP is an RV64C-only instruction that stores a 64-bit value in\n 341| register _rs2_ to memory. It computes an effective address by adding the\n 342| _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It" + }, + { + "score": 8, + "reasons": [ + "Description keyword 'C'", + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 345, + "line_text": "[#norm:c-fswsp_op]#C.FSWSP is an RV32FC-only instruction that stores a single-precision", + "context": " 343| expands to `sd rs2, offset(x2)`.#\n 344| \n>>> 345| [#norm:c-fswsp_op]#C.FSWSP is an RV32FC-only instruction that stores a single-precision\n 346| floating-point value in floating-point register _rs2_ to memory. It\n 347| computes an effective address by adding the _zero_-extended offset," + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'FAULT'", + "Description keyword 'PC'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 1183, + "line_text": "[#norm:Zcmp_trap]#If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and _xCAUSE_ updated with the type of trap.#", + "context": " 1181| The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.\n 1182| \n>>> 1183| [#norm:Zcmp_trap]#If a trap occurs during the sequence then _xEPC_ is updated with the PC of the instruction, _xTVAL_ (if not read-only-zero) updated with the bad address if it was an access fault and _xCAUSE_ updated with the type of trap.#\n 1184| \n 1185| [[norm:interrupts_allowed_in_pushpop_param]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'FAULT'", + "Description keyword 'PC'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2359, + "line_text": "[#norm:Zcmt_trap]#If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.#", + "context": " 2357| if the tables have not been updated in memory since the last _fence.i_.\n 2358| \n>>> 2359| [#norm:Zcmt_trap]#If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.#\n 2360| \n 2361| <<<" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Name segment 'VSTVAL'", + "Description keyword 'vstval'", + "Name segment 'ACCESS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "Name segment 'VSTVAL'", + "Description keyword 'vstval'", + "Name segment 'ACCESS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1364, + "line_text": "==== Virtual Supervisor Trap Value (`vstval`) Register", + "context": " 1362| include::images/bytefield/vscausereg.edn[]\n 1363| \n>>> 1364| ==== Virtual Supervisor Trap Value (`vstval`) Register\n 1365| \n 1366| [[norm:vstval_sz_acc_op]]" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1367, + "line_text": "The `vstval` register is a VSXLEN-bit read/write register that is", + "context": " 1365| \n 1366| [[norm:vstval_sz_acc_op]]\n>>> 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n 1369| <>. When V=1, `vstval` substitutes for" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1369, + "line_text": "<>. When V=1, `vstval` substitutes for", + "context": " 1367| The `vstval` register is a VSXLEN-bit read/write register that is\n 1368| VS-mode’s version of supervisor register `stval`, formatted as shown in\n>>> 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n 1371| actually access `vstval` instead. When V=0, `vstval` does not directly" + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1371, + "line_text": "actually access `vstval` instead. When V=0, `vstval` does not directly", + "context": " 1369| <>. When V=1, `vstval` substitutes for\n 1370| the usual `stval`, so instructions that normally read or modify `stval`\n>>> 1371| actually access `vstval` instead. When V=0, `vstval` does not directly\n 1372| affect the behavior of the machine.\n 1373| " + }, + { + "score": 7, + "reasons": ["Name segment 'VSTVAL'", "Description keyword 'vstval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1375, + "line_text": "`vstval` is a *WARL* register that must be able to hold the same set of values", + "context": " 1373| \n 1374| [[norm:vstval_warl]]\n>>> 1375| `vstval` is a *WARL* register that must be able to hold the same set of values\n 1376| that `stval` can hold.\n 1377| " + } + ] + }, + { + "parameter_name": "RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX", + "classification": "NORM_DIRECT", + "value_type": "enum", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'VLMAX'", + "Description keyword 'VLMAX'", + "Description keyword 'AVL'", + "Description keyword 'VL'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1279, + "line_text": "[#norm:vsetvl_op_rs1_x0_rd_x0]#When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register. This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.# [#norm:vtype_vset_rsv]#Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if `vill` was 1 beforehand.# [#norm:reserved_vill_set_param]#Implementations may set `vill` in either case.#", + "context": " 1277| also to the `x` register specified by `rd`.\n 1278| \n>>> 1279| [#norm:vsetvl_op_rs1_x0_rd_x0]#When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register. This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.# [#norm:vtype_vset_rsv]#Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if `vill` was 1 beforehand.# [#norm:reserved_vill_set_param]#Implementations may set `vill` in either case.#\n 1280| \n 1281| NOTE: This last form of the instructions allows the `vtype` register to" + }, + { + "score": 7, + "reasons": [ + "Name segment 'VLMAX'", + "Description keyword 'VLMAX'", + "Description keyword 'AVL'", + "Description keyword 'VL'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1276, + "line_text": "is used as the AVL, and the resulting VLMAX is written to `vl` and", + "context": " 1274| [[norm:vsetvl_op_rs1_x0_rd_nx0]]\n 1275| When _rs1_=`x0` but _rd_≠`x0`, the maximum unsigned integer value (`~0`)\n>>> 1276| is used as the AVL, and the resulting VLMAX is written to `vl` and\n 1277| also to the `x` register specified by `rd`.\n 1278| " + }, + { + "score": 7, + "reasons": [ + "Name segment 'VLMAX'", + "Description keyword 'VLMAX'", + "Description keyword 'AVL'", + "Description keyword 'VL'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1310, + "line_text": ". `vl = AVL` if `AVL {le} VLMAX`", + "context": " 1308| \n 1309| [[norm:vl_val_list]]\n>>> 1310| . `vl = AVL` if `AVL {le} VLMAX`\n 1311| . `ceil(AVL / 2) {le} vl {le} VLMAX` if `AVL < (2 * VLMAX)`\n 1312| . `vl = VLMAX` if `AVL {ge} (2 * VLMAX)`" + }, + { + "score": 7, + "reasons": [ + "Name segment 'VLMAX'", + "Description keyword 'VLMAX'", + "Description keyword 'AVL'", + "Description keyword 'VL'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1311, + "line_text": ". `ceil(AVL / 2) {le} vl {le} VLMAX` if `AVL < (2 * VLMAX)`", + "context": " 1309| [[norm:vl_val_list]]\n 1310| . `vl = AVL` if `AVL {le} VLMAX`\n>>> 1311| . `ceil(AVL / 2) {le} vl {le} VLMAX` if `AVL < (2 * VLMAX)`\n 1312| . `vl = VLMAX` if `AVL {ge} (2 * VLMAX)`\n 1313| . Deterministic on any given implementation for same input AVL and VLMAX values" + }, + { + "score": 7, + "reasons": [ + "Name segment 'VLMAX'", + "Description keyword 'VLMAX'", + "Description keyword 'AVL'", + "Description keyword 'VL'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1312, + "line_text": ". `vl = VLMAX` if `AVL {ge} (2 * VLMAX)`", + "context": " 1310| . `vl = AVL` if `AVL {le} VLMAX`\n 1311| . `ceil(AVL / 2) {le} vl {le} VLMAX` if `AVL < (2 * VLMAX)`\n>>> 1312| . `vl = VLMAX` if `AVL {ge} (2 * VLMAX)`\n 1313| . Deterministic on any given implementation for same input AVL and VLMAX values\n 1314| . These specific properties follow from the prior rules:" + } + ] + }, + { + "parameter_name": "SATP_MODE_BARE", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR name 'satp' in backticks", + "Name segment 'SATP'", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 670, + "line_text": "[#norm:mstatus_sum_rdonly0]#SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.#", + "context": " 668| Note that, [#norm:mstatus_sum_op_mprv_mpp]#while SUM is ordinarily ignored when not\n 669| executing in S-mode, it _is_ in effect when MPRV=1 and MPP=S.#\n>>> 670| [#norm:mstatus_sum_rdonly0]#SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.#\n 671| \n 672| [[norm:mstatus_mxr_sum_op_acc_fault]]" + }, + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR name 'satp' in backticks", + "Name segment 'SATP'", + "CSR field name 'MODE'", + "Name segment 'BARE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 840, + "line_text": "If `satp`.MODE is read-only zero (always Bare), the implementation may", + "context": " 838| \n 839| [[norm:senvcfg-fiom_acc]]\n>>> 840| If `satp`.MODE is read-only zero (always Bare), the implementation may\n 841| make FIOM read-only zero.\n 842| " + }, + { + "score": 10, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR name 'satp' in backticks", + "Name segment 'SATP'", + "CSR field name 'MODE'", + "Name segment 'BARE'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 1426, + "line_text": "For implementations that make `satp`.MODE read-only zero (always Bare),", + "context": " 1424| \n 1425| [[norm:satp-mode_roz_sfence_illegal_param]]\n>>> 1426| For implementations that make `satp`.MODE read-only zero (always Bare),\n 1427| attempts to execute an SFENCE.VMA instruction might raise an\n 1428| illegal-instruction exception." + }, + { + "score": 9, + "reasons": [ + "Name segment 'SATP'", + "CSR name 'satp' in backticks", + "WARL + CSR 'satp'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1075, + "line_text": "is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,", + "context": " 1073| [[norm:hgatp-mode_warl]]\n 1074| A write to `hgatp` with an unsupported MODE value is not ignored as it\n>>> 1075| is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,\n 1076| when so indicated.\n 1077| " + }, + { + "score": 9, + "reasons": [ + "Name segment 'SATP'", + "CSR name 'satp' in backticks", + "WARL + CSR 'satp'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1416, + "line_text": "ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in", + "context": " 1414| \n 1415| [#norm:vsatp_mode_unsupported_v0]#When V=0, a write to `vsatp` with an unsupported MODE value is either\n>>> 1416| ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in\n 1417| the normal way.# [#norm:vsatp_mode_unsupported_v1]#However, when V=1, a write to `satp` with an unsupported\n 1418| MODE value _is_ ignored and no write to `vsatp` is effected.#" + } + ] + }, + { + "parameter_name": "SCOUNTENABLE_EN", + "classification": "NORM_CSR_RW", + "value_type": "bitmask", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "Description keyword 'scounteren'", + "CSR field name 'IR'", + "CSR name 'scounteren' in backticks", + "CSR field name 'TM'", + "CSR field name 'CY'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 511, + "line_text": "When the CY, TM, IR, or HPM__n__ bit in the `scounteren` register is", + "context": " 509| \n 510| [[norm:scounteren_op]]\n>>> 511| When the CY, TM, IR, or HPM__n__ bit in the `scounteren` register is\n 512| clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern`\n 513| register while executing in U-mode will cause an illegal-instruction" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'IR'", + "CSR field name 'TM'", + "CSR field name 'CY'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1615, + "line_text": "[#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is", + "context": " 1613| counters, which continue to increment even when not accessible.#\n 1614| \n>>> 1615| [#norm:mcounteren_clr_ill_inst_exc]#When the CY, TM, IR, or HPM__n__ bit in the `mcounteren` register is\n 1616| clear, attempts to read the `cycle`, `time`, `instret`, or\n 1617| `hpmcountern` register while executing in S-mode or U-mode will cause an" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'Zihpm'", + "Description keyword 'Zicntr'" + ], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 2, + "line_text": "== \"Zicntr\" and \"Zihpm\" Extensions for Counters, Version 2.0", + "context": " 1| [[counters]]\n>>> 2| == \"Zicntr\" and \"Zihpm\" Extensions for Counters, Version 2.0\n 3| \n 4| [[norm:zihpm_op_sz_mode_acc]]" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'Zihpm'", + "Description keyword 'Zicntr'" + ], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 9, + "line_text": "divided between the \"Zicntr\" and \"Zihpm\" extensions.", + "context": " 7| read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits\n 8| are accessed via CSR registers `0xC80`–`0xC9F`). These counters are\n>>> 9| divided between the \"Zicntr\" and \"Zihpm\" extensions.\n 10| \n 11| === \"Zicntr\" Extension for Base Counters and Timers" + }, + { + "score": 6, + "reasons": [ + "Description keyword 'scounteren'", + "CSR name 'scounteren' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 146, + "line_text": "Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`,", + "context": " 144| \n 145| [[norm:H_scsrs_nomatch]]\n>>> 146| Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`,\n 147| possibly others) have no matching VS CSR. These supervisor CSRs continue\n 148| to have their usual function and accessibility even when V=1, except" + } + ] + }, + { + "parameter_name": "SSTATEEN_JVT_TYPE", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 1, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Description keyword 'JVT'"], + "is_normative": true, + "in_note": false, + "file": "zc.adoc", + "line_number": 2341, + "line_text": "[#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#", + "context": " 2339| ==== jvt\n 2340| \n>>> 2341| [#norm:Zcmt_entry_sz]#The base of the table is in the jvt CSR (see <>), each table entry is XLEN bits.#\n 2342| \n 2343| If the same function is called with and without linking then it must have two entries in the table." + } + ] + }, + { + "parameter_name": "STVAL_WIDTH", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 707, + "line_text": "[[norm:stval]]", + "context": " 705| ==== Supervisor Trap Value (`stval`) Register\n 706| \n>>> 707| [[norm:stval]]\n 708| The `stval` CSR is an SXLEN-bit read-write register formatted as\n 709| shown in <>. When a trap is taken into" + }, + { + "score": 4, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 325, + "line_text": "guest virtual address to `stval`, GVA is set to 1. For any other trap", + "context": " 323| whenever a trap is taken into HS-mode. For any trap (breakpoint, address\n 324| misaligned, access fault, page fault, or guest-page fault) that writes a\n>>> 325| guest virtual address to `stval`, GVA is set to 1. For any other trap\n 326| into HS-mode, GVA is set to 0.\n 327| " + }, + { + "score": 4, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 910, + "line_text": "information, alongside `stval`, to assist software in handling the trap.", + "context": " 908| shown in <>. When a trap is taken into\n 909| HS-mode, `htval` is written with additional exception-specific\n>>> 910| information, alongside `stval`, to assist software in handling the trap.\n 911| \n 912| [[htvalreg]]" + }, + { + "score": 4, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 933, + "line_text": "portion of the access as indicated by the virtual address in `stval`.", + "context": " 931| Otherwise, for misaligned loads and stores that cause guest-page faults,\n 932| a nonzero guest physical address in `htval` corresponds to the faulting\n>>> 933| portion of the access as indicated by the virtual address in `stval`.\n 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of" + }, + { + "score": 4, + "reasons": ["Name segment 'STVAL'", "Description keyword 'stval'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 936, + "line_text": "the instruction as indicated by the virtual address in `stval`.", + "context": " 934| For instruction guest-page faults on systems with variable-length\n 935| instructions, a nonzero `htval` corresponds to the faulting portion of\n>>> 936| the instruction as indicated by the virtual address in `stval`.\n 937| \n 938| [NOTE]" + } + ] + }, + { + "parameter_name": "STVEC_MODE_DIRECT", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "CSR name 'stvec' in backticks", + "Description keyword 'MODE'", + "Name segment 'STVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1304, + "line_text": "VS-mode’s version of supervisor register `stvec`, formatted as shown in", + "context": " 1302| [[norm:vstvec_sz_acc_op]]\n 1303| The `vstvec` register is a VSXLEN-bit read/write register that is\n>>> 1304| VS-mode’s version of supervisor register `stvec`, formatted as shown in\n 1305| <>. When V=1, `vstvec` substitutes for\n 1306| the usual `stvec`, so instructions that normally read or modify `stvec`" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "CSR name 'stvec' in backticks", + "Description keyword 'MODE'", + "Name segment 'STVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 340, + "line_text": ".Encoding of `stvec` MODE field.", + "context": " 338| \n 339| [[stvec-mode]]\n>>> 340| .Encoding of `stvec` MODE field.\n 341| [%autowidth,float=\"center\",align=\"center\",cols=\">,^,<\",options=\"header\",]\n 342| |===" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 577, + "line_text": "[#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "context": " 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n>>> 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.\n 578| Otherwise, it is a *WARL* field that encodes the current value of SXLEN.#\n 579| In particular, [#norm:mstatus_sxl_rdonly_mxlen64]#an implementation may make SXL be a read-only field whose" + } + ] + }, + { + "parameter_name": "STVEC_MODE_VECTORED", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'VECTORED'", + "Description keyword 'MODE'", + "Description keyword 'vectored'", + "CSR field name 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1256, + "line_text": "[#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause", + "context": " 1254| [#norm:mtvec_mode_direct_op]#When MODE=Direct, all traps into\n 1255| machine mode cause the `pc` to be set to the address in the BASE field.#\n>>> 1256| [#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause\n 1257| the `pc` to be set to the address in the BASE field, whereas interrupts\n 1258| cause the `pc` to be set to the address in the BASE field plus four" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "CSR name 'stvec' in backticks", + "Description keyword 'MODE'", + "Name segment 'STVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1304, + "line_text": "VS-mode’s version of supervisor register `stvec`, formatted as shown in", + "context": " 1302| [[norm:vstvec_sz_acc_op]]\n 1303| The `vstvec` register is a VSXLEN-bit read/write register that is\n>>> 1304| VS-mode’s version of supervisor register `stvec`, formatted as shown in\n 1305| <>. When V=1, `vstvec` substitutes for\n 1306| the usual `stvec`, so instructions that normally read or modify `stvec`" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "CSR name 'stvec' in backticks", + "Description keyword 'MODE'", + "Name segment 'STVEC'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 340, + "line_text": ".Encoding of `stvec` MODE field.", + "context": " 338| \n 339| [[stvec-mode]]\n>>> 340| .Encoding of `stvec` MODE field.\n 341| [%autowidth,float=\"center\",align=\"center\",cols=\">,^,<\",options=\"header\",]\n 342| |===" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + } + ] + }, + { + "parameter_name": "SV32X4_TRANSLATION", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'SV32X4'", + "Name segment 'TRANSLATION'", + "Description keyword 'translation'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1915, + "line_text": "When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,", + "context": " 1913| \n 1914| [[norm:hgatp-mode_x4]]\n>>> 1915| When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,\n 1916| Sv48x4, or Sv57x4, G-stage address translation is a variation on the\n 1917| usual page-based virtual address translation scheme of Sv32, Sv39, Sv48," + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1007, + "line_text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.", + "context": " 1005| \n 1006| [[rv64hgatp]]\n>>> 1007| .Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.\n 1008| include::images/bytefield/rv64hgatp.edn[]\n 1009| " + }, + { + "score": 8, + "reasons": ["WARL + CSR 'hgatp'", "CSR name 'hgatp' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1075, + "line_text": "is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,", + "context": " 1073| [[norm:hgatp-mode_warl]]\n 1074| A write to `hgatp` with an unsupported MODE value is not ignored as it\n>>> 1075| is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,\n 1076| when so indicated.\n 1077| " + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2152, + "line_text": "is less than GPA width supported by the `hgatp` translation mode of that guest.", + "context": " 2150| supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with\n 2151| _rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)\n>>> 2152| is less than GPA width supported by the `hgatp` translation mode of that guest.\n 2153| Specifically, these cases are:\n 2154| " + }, + { + "score": 6, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 987, + "line_text": "==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "context": " 985| \n 986| [[hgatp]]\n>>> 987| ==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register\n 988| \n 989| [#norm:hgatp_sz_acc_op]#The `hgatp` register is an HSXLEN-bit read/write register, formatted as" + } + ] + }, + { + "parameter_name": "SV32_VSMODE_TRANSLATION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 365, + "line_text": "otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed", + "context": " 363| raises a store page-fault or store guest-page-fault exception if address\n 364| translation does not permit any access or raises a store access-fault exception\n>>> 365| otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed\n 366| bit and may either raise an exception or set the bit as required.#\n 367| " + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 383, + "line_text": "access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction", + "context": " 381| cache-block zero instruction raises a store page-fault or store guest-page-fault\n 382| exception if address translation does not permit write access or raises a store\n>>> 383| access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction\n 384| also checks the accessed and dirty bits and may either raise an exception or set\n 385| the bits as required.#" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 730, + "line_text": "in VS-stage address translation. When PBMTE=1, Svpbmt is available for", + "context": " 728| [[norm:henvcfg-pbmte_op]]\n 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n>>> 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 731, + "line_text": "VS-stage address translation. When PBMTE=0, the implementation behaves", + "context": " 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n>>> 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 732, + "line_text": "as though Svpbmt were not implemented for VS-stage address translation.", + "context": " 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n>>> 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero.\n 734| " + } + ] + }, + { + "parameter_name": "SV39X4_TRANSLATION", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'TRANSLATION'", + "Description keyword 'translation'", + "Name segment 'SV39X4'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1007, + "line_text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.", + "context": " 1005| \n 1006| [[rv64hgatp]]\n>>> 1007| .Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.\n 1008| include::images/bytefield/rv64hgatp.edn[]\n 1009| " + }, + { + "score": 9, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'TRANSLATION'", + "Description keyword 'translation'", + "Name segment 'SV39X4'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1915, + "line_text": "When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,", + "context": " 1913| \n 1914| [[norm:hgatp-mode_x4]]\n>>> 1915| When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,\n 1916| Sv48x4, or Sv57x4, G-stage address translation is a variation on the\n 1917| usual page-based virtual address translation scheme of Sv32, Sv39, Sv48," + }, + { + "score": 8, + "reasons": ["WARL + CSR 'hgatp'", "CSR name 'hgatp' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1075, + "line_text": "is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,", + "context": " 1073| [[norm:hgatp-mode_warl]]\n 1074| A write to `hgatp` with an unsupported MODE value is not ignored as it\n>>> 1075| is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,\n 1076| when so indicated.\n 1077| " + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2152, + "line_text": "is less than GPA width supported by the `hgatp` translation mode of that guest.", + "context": " 2150| supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with\n 2151| _rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)\n>>> 2152| is less than GPA width supported by the `hgatp` translation mode of that guest.\n 2153| Specifically, these cases are:\n 2154| " + }, + { + "score": 6, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 987, + "line_text": "==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "context": " 985| \n 986| [[hgatp]]\n>>> 987| ==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register\n 988| \n 989| [#norm:hgatp_sz_acc_op]#The `hgatp` register is an HSXLEN-bit read/write register, formatted as" + } + ] + }, + { + "parameter_name": "SV39_VSMODE_TRANSLATION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 365, + "line_text": "otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed", + "context": " 363| raises a store page-fault or store guest-page-fault exception if address\n 364| translation does not permit any access or raises a store access-fault exception\n>>> 365| otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed\n 366| bit and may either raise an exception or set the bit as required.#\n 367| " + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 383, + "line_text": "access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction", + "context": " 381| cache-block zero instruction raises a store page-fault or store guest-page-fault\n 382| exception if address translation does not permit write access or raises a store\n>>> 383| access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction\n 384| also checks the accessed and dirty bits and may either raise an exception or set\n 385| the bits as required.#" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 730, + "line_text": "in VS-stage address translation. When PBMTE=1, Svpbmt is available for", + "context": " 728| [[norm:henvcfg-pbmte_op]]\n 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n>>> 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 731, + "line_text": "VS-stage address translation. When PBMTE=0, the implementation behaves", + "context": " 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n>>> 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 732, + "line_text": "as though Svpbmt were not implemented for VS-stage address translation.", + "context": " 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n>>> 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero.\n 734| " + } + ] + }, + { + "parameter_name": "SV48X4_TRANSLATION", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'TRANSLATION'", + "Description keyword 'translation'", + "CSR name 'hgatp' in backticks", + "Name segment 'SV48X4'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1007, + "line_text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.", + "context": " 1005| \n 1006| [[rv64hgatp]]\n>>> 1007| .Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.\n 1008| include::images/bytefield/rv64hgatp.edn[]\n 1009| " + }, + { + "score": 8, + "reasons": ["WARL + CSR 'hgatp'", "CSR name 'hgatp' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1075, + "line_text": "is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,", + "context": " 1073| [[norm:hgatp-mode_warl]]\n 1074| A write to `hgatp` with an unsupported MODE value is not ignored as it\n>>> 1075| is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,\n 1076| when so indicated.\n 1077| " + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1915, + "line_text": "When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,", + "context": " 1913| \n 1914| [[norm:hgatp-mode_x4]]\n>>> 1915| When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,\n 1916| Sv48x4, or Sv57x4, G-stage address translation is a variation on the\n 1917| usual page-based virtual address translation scheme of Sv32, Sv39, Sv48," + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2152, + "line_text": "is less than GPA width supported by the `hgatp` translation mode of that guest.", + "context": " 2150| supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with\n 2151| _rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)\n>>> 2152| is less than GPA width supported by the `hgatp` translation mode of that guest.\n 2153| Specifically, these cases are:\n 2154| " + }, + { + "score": 6, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 987, + "line_text": "==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "context": " 985| \n 986| [[hgatp]]\n>>> 987| ==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register\n 988| \n 989| [#norm:hgatp_sz_acc_op]#The `hgatp` register is an HSXLEN-bit read/write register, formatted as" + } + ] + }, + { + "parameter_name": "SV48_VSMODE_TRANSLATION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 365, + "line_text": "otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed", + "context": " 363| raises a store page-fault or store guest-page-fault exception if address\n 364| translation does not permit any access or raises a store access-fault exception\n>>> 365| otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed\n 366| bit and may either raise an exception or set the bit as required.#\n 367| " + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 383, + "line_text": "access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction", + "context": " 381| cache-block zero instruction raises a store page-fault or store guest-page-fault\n 382| exception if address translation does not permit write access or raises a store\n>>> 383| access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction\n 384| also checks the accessed and dirty bits and may either raise an exception or set\n 385| the bits as required.#" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 730, + "line_text": "in VS-stage address translation. When PBMTE=1, Svpbmt is available for", + "context": " 728| [[norm:henvcfg-pbmte_op]]\n 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n>>> 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 731, + "line_text": "VS-stage address translation. When PBMTE=0, the implementation behaves", + "context": " 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n>>> 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 732, + "line_text": "as though Svpbmt were not implemented for VS-stage address translation.", + "context": " 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n>>> 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero.\n 734| " + } + ] + }, + { + "parameter_name": "SV57X4_TRANSLATION", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "CSR field name 'MODE'", + "Name segment 'TRANSLATION'", + "Description keyword 'translation'", + "CSR name 'hgatp' in backticks", + "Name segment 'SV57X4'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1007, + "line_text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.", + "context": " 1005| \n 1006| [[rv64hgatp]]\n>>> 1007| .Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.\n 1008| include::images/bytefield/rv64hgatp.edn[]\n 1009| " + }, + { + "score": 8, + "reasons": ["WARL + CSR 'hgatp'", "CSR name 'hgatp' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1075, + "line_text": "is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,", + "context": " 1073| [[norm:hgatp-mode_warl]]\n 1074| A write to `hgatp` with an unsupported MODE value is not ignored as it\n>>> 1075| is for `satp`. Instead, the fields of `hgatp` are *WARL* in the normal way,\n 1076| when so indicated.\n 1077| " + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1915, + "line_text": "When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,", + "context": " 1913| \n 1914| [[norm:hgatp-mode_x4]]\n>>> 1915| When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4,\n 1916| Sv48x4, or Sv57x4, G-stage address translation is a variation on the\n 1917| usual page-based virtual address translation scheme of Sv32, Sv39, Sv48," + }, + { + "score": 8, + "reasons": [ + "CSR field name 'MODE'", + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2152, + "line_text": "is less than GPA width supported by the `hgatp` translation mode of that guest.", + "context": " 2150| supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with\n 2151| _rs1_=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN)\n>>> 2152| is less than GPA width supported by the `hgatp` translation mode of that guest.\n 2153| Specifically, these cases are:\n 2154| " + }, + { + "score": 6, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "CSR name 'hgatp' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 987, + "line_text": "==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "context": " 985| \n 986| [[hgatp]]\n>>> 987| ==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register\n 988| \n 989| [#norm:hgatp_sz_acc_op]#The `hgatp` register is an HSXLEN-bit read/write register, formatted as" + } + ] + }, + { + "parameter_name": "SV57_VSMODE_TRANSLATION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 365, + "line_text": "otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed", + "context": " 363| raises a store page-fault or store guest-page-fault exception if address\n 364| translation does not permit any access or raises a store access-fault exception\n>>> 365| otherwise.# [#norm:cbm_unperm_translate]#During address translation, the instruction also checks the accessed\n 366| bit and may either raise an exception or set the bit as required.#\n 367| " + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'" + ], + "is_normative": true, + "in_note": false, + "file": "cmo.adoc", + "line_number": 383, + "line_text": "access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction", + "context": " 381| cache-block zero instruction raises a store page-fault or store guest-page-fault\n 382| exception if address translation does not permit write access or raises a store\n>>> 383| access-fault exception otherwise.# [#norm:cbz_unperm_translate]#During address translation, the instruction\n 384| also checks the accessed and dirty bits and may either raise an exception or set\n 385| the bits as required.#" + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 730, + "line_text": "in VS-stage address translation. When PBMTE=1, Svpbmt is available for", + "context": " 728| [[norm:henvcfg-pbmte_op]]\n 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n>>> 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 731, + "line_text": "VS-stage address translation. When PBMTE=0, the implementation behaves", + "context": " 729| The PBMTE bit controls whether the Svpbmt extension is available for use\n 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n>>> 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero." + }, + { + "score": 5, + "reasons": [ + "Description keyword 'translation'", + "Name segment 'TRANSLATION'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 732, + "line_text": "as though Svpbmt were not implemented for VS-stage address translation.", + "context": " 730| in VS-stage address translation. When PBMTE=1, Svpbmt is available for\n 731| VS-stage address translation. When PBMTE=0, the implementation behaves\n>>> 732| as though Svpbmt were not implemented for VS-stage address translation.\n 733| If Svpbmt is not implemented, PBMTE is read-only zero.\n 734| " + } + ] + }, + { + "parameter_name": "SXLEN", + "classification": "NORM_DIRECT", + "value_type": "set", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "Description keyword 'SXL'", + "Name segment 'SXLEN'", + "Exact parameter name 'SXLEN'", + "CSR field name 'SXL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 575, + "line_text": "When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.", + "context": " 573| \n 574| [[norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32]]\n>>> 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero." + }, + { + "score": 9, + "reasons": [ + "CSR name 'mstatus' in backticks", + "Description keyword 'SXL'", + "CSR field name 'SXL'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 393, + "line_text": "[#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#", + "context": " 391| \n 392| [#norm:mstatush_sz_acc]#For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>.#\n>>> 393| [#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#\n 394| \n 395| [[mstatushreg]]" + }, + { + "score": 8, + "reasons": ["Parameter name in emphasis '_SXLEN_'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 572, + "line_text": "[#norm:sxlen_uxlen]#The effective XLEN in S-mode and U-mode are termed _SXLEN_ and _UXLEN_, respectively.#", + "context": " 570| value of XLEN for S-mode and U-mode, respectively.#\n 571| [#norm:mstatus_sxl_uxl_enc]#The encoding of these fields is the same as the MXL field of `misa`, shown in <>.#\n>>> 572| [#norm:sxlen_uxlen]#The effective XLEN in S-mode and U-mode are termed _SXLEN_ and _UXLEN_, respectively.#\n 573| \n 574| [[norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32]]" + }, + { + "score": 7, + "reasons": ["Name segment 'SXLEN'", "Exact parameter name 'SXLEN'"], + "is_normative": false, + "in_note": false, + "file": "indirect-csr.adoc", + "line_number": 201, + "line_text": "current XLEN rather than SXLEN. Hence, for example, if MXLEN = 64 and", + "context": " 199| \n 200| Note that the widths of `siselect` and `sireg*` are always the\n>>> 201| current XLEN rather than SXLEN. Hence, for example, if MXLEN = 64 and\n 202| SXLEN = 32, then these registers are 64 bits when the current privilege\n 203| mode is M (running RV64 code) but 32 bits when the privilege mode is S" + }, + { + "score": 7, + "reasons": ["Name segment 'SXLEN'", "Exact parameter name 'SXLEN'"], + "is_normative": false, + "in_note": false, + "file": "indirect-csr.adoc", + "line_number": 202, + "line_text": "SXLEN = 32, then these registers are 64 bits when the current privilege", + "context": " 200| Note that the widths of `siselect` and `sireg*` are always the\n 201| current XLEN rather than SXLEN. Hence, for example, if MXLEN = 64 and\n>>> 202| SXLEN = 32, then these registers are 64 bits when the current privilege\n 203| mode is M (running RV64 code) but 32 bits when the privilege mode is S\n 204| (RV32 code)." + } + ] + }, + { + "parameter_name": "S_MODE_ENDIANNESS", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 22, + "candidates": [ + { + "score": 22, + "reasons": [ + "WARL + CSR 'mstatush'", + "CSR field name 'SBE'", + "CSR name 'mstatus' in backticks", + "Description keyword 'SBE'", + "CSR name 'mstatush' in backticks", + "WARL + CSR 'mstatus'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 679, + "line_text": "[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that", + "context": " 677| ===== Endianness Control in `mstatus` and `mstatush` Registers\n 678| \n>>> 679| [#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that\n 680| control the endianness of memory accesses other than instruction fetches.\n 681| [#norm:endianness_inst_fetch_little]#Instruction fetches are always little-endian.#" + }, + { + "score": 8, + "reasons": [ + "CSR name 'mstatus' in backticks", + "CSR name 'mstatush' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 393, + "line_text": "[#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#", + "context": " 391| \n 392| [#norm:mstatush_sz_acc]#For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>.#\n>>> 393| [#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#\n 394| \n 395| [[mstatushreg]]" + }, + { + "score": 8, + "reasons": [ + "WARL + CSR 'mstatus'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 501, + "line_text": "* Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.", + "context": " 499| the possibility of a future global-ASID extension.\n 500| * SFENCE.VMA semantics have been clarified.\n>>> 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*." + }, + { + "score": 7, + "reasons": [ + "CSR name 'mstatus' in backticks", + "Name segment 'ENDIANNESS'", + "CSR name 'mstatush' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 677, + "line_text": "===== Endianness Control in `mstatus` and `mstatush` Registers", + "context": " 675| whether access-fault exceptions are raised due to PMAs or PMP.\n 676| \n>>> 677| ===== Endianness Control in `mstatus` and `mstatush` Registers\n 678| \n 679| [#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mstatus' in backticks", + "CSR name 'mstatush' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1658, + "line_text": "==== Machine Status (`mstatus` and `mstatush`) Registers", + "context": " 1656| `mtinst`.\n 1657| \n>>> 1658| ==== Machine Status (`mstatus` and `mstatush`) Registers\n 1659| \n 1660| The hypervisor extension adds two fields, MPV and GVA, to the" + } + ] + }, + { + "parameter_name": "TIME_CSR_IMPLEMENTED", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 25, + "candidates": [ + { + "score": 25, + "reasons": [ + "Name segment 'TIME'", + "CSR name 'time' in backticks", + "Description keyword 'time'", + "CSR name 'timeh' in backticks", + "Description keyword 'timeh'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 2621, + "line_text": "When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`", + "context": " 2619| memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of\n 2620| `mtime`.\n>>> 2621| When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`\n 2622| eventually, but not necessarily immediately.\n 2623| " + }, + { + "score": 19, + "reasons": [ + "Description keyword 'implemented'", + "Name segment 'TIME'", + "Description keyword 'time'", + "CSR name 'time' in backticks", + "Name segment 'IMPLEMENTED'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 901, + "line_text": "If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32)", + "context": " 899| \n 900| [[norm:time_htimedelta_req]]\n>>> 901| If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32)\n 902| must be implemented.\n 903| " + }, + { + "score": 18, + "reasons": [ + "Description keyword 'time'", + "Name segment 'TIME'", + "CSR name 'time' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1642, + "line_text": "[#norm:time_op_rdonly]#The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.#", + "context": " 1640| \n 1641| [#norm:cycle_instret_hpmcounter_op_rdonly]#The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of `mcycle`, `minstret`, and `mhpmcounter n`, respectively.#\n>>> 1642| [#norm:time_op_rdonly]#The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.#\n 1643| Analogously, [#norm:cycleh_instreth_hpmcounternh_op_rdonly]#when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs\n 1644| are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`, respectively.#" + }, + { + "score": 16, + "reasons": [ + "Description keyword 'time'", + "Name segment 'TIME'", + "CSR name 'time' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 36, + "line_text": "`time`, and `instret` counters.", + "context": " 34| the full 64-bit CSRs directly. In particular, the RDCYCLE, RDTIME, and\n 35| RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`,\n>>> 36| `time`, and `instret` counters.\n 37| \n 38| [NOTE]" + }, + { + "score": 16, + "reasons": [ + "Description keyword 'time'", + "Name segment 'TIME'", + "CSR name 'time' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 581, + "line_text": "`vstimecmp` with a value that is less than or equal to the sum of `time` and", + "context": " 579| timer interrupt signal resulting from `vstimecmp`. The `hip`.VSTIP bit, in\n 580| response to timer interrupts generated by `vstimecmp`, is set by writing\n>>> 581| `vstimecmp` with a value that is less than or equal to the sum of `time` and\n 582| `htimedelta`, truncated to 64 bits; it is cleared by writing `vstimecmp` with a\n 583| greater value. The `hip`.VSTIP bit remains defined while V=0 as well as V=1." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_BREAKPOINT", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'breakpoint'", + "Name segment 'BREAKPOINT'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 168, + "line_text": "|BPFRZ |[#norm:vsctrctl-bpfrz_op]#Set `sctrstatus`.FROZEN on a breakpoint exception that traps to VS-mode.# See <>.", + "context": " 166| |U |[#norm:vsctrctl-u_op]#Enable transfer recording in VU-mode.#\n 167| |STE |[#norm:vsctrctl-ste_op]#Enables recording of traps to VS-mode when S=0.# See <>.\n>>> 168| |BPFRZ |[#norm:vsctrctl-bpfrz_op]#Set `sctrstatus`.FROZEN on a breakpoint exception that traps to VS-mode.# See <>.\n 169| |LCOFIFRZ |[#norm:vsctrctl-lcofifrz_op]#Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to VS-mode.# See <>.\n 170| 2+|Other field definitions match those of `sctrctl`. The optional fields implemented in `vsctrctl` should match those implemented in `sctrctl`." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'breakpoint'", + "Name segment 'BREAKPOINT'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 752, + "line_text": "[#norm:freeze_vs]#If the H extension is implemented, freeze behavior for LCOFIs and breakpoint exceptions that trap to VS-mode is determined by the LCOFIFRZ and BPFRZ values, respectively, in `vsctrctl`. This includes virtual LCOFIs pended by a hypervisor.#", + "context": " 750| ====\n 751| \n>>> 752| [#norm:freeze_vs]#If the H extension is implemented, freeze behavior for LCOFIs and breakpoint exceptions that trap to VS-mode is determined by the LCOFIFRZ and BPFRZ values, respectively, in `vsctrctl`. This includes virtual LCOFIs pended by a hypervisor.#\n 753| \n 754| [NOTE]" + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "CSR name 'mtinst' in backticks", + "Name segment 'INSTRUCTION'", + "CSR name 'htinst' in backticks", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2567, + "line_text": "==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "context": " 2565| \n 2566| [[tinst-vals]]\n>>> 2567| ==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`\n 2568| \n 2569| [[norm:H_trap_xtinst]]" + }, + { + "score": 9, + "reasons": [ + "CSR name 'mtinst' in backticks", + "Name segment 'INSTRUCTION'", + "CSR name 'htinst' in backticks", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2669, + "line_text": ".Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.", + "context": " 2667| \n 2668| [[tinst-values]]\n>>> 2669| .Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.\n 2670| [float=\"center\",align=\"center\",cols=\"2,^,^,^,^\",options=\"header\"]\n 2671| |===" + }, + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "CSR name 'mtinst' in backticks", + "Name segment 'INSTRUCTION'", + "CSR name 'htinst' in backticks", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2567, + "line_text": "==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "context": " 2565| \n 2566| [[tinst-vals]]\n>>> 2567| ==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`\n 2568| \n 2569| [[norm:H_trap_xtinst]]" + }, + { + "score": 9, + "reasons": [ + "CSR name 'mtinst' in backticks", + "Name segment 'INSTRUCTION'", + "CSR name 'htinst' in backticks", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2669, + "line_text": ".Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.", + "context": " 2667| \n 2668| [[tinst-values]]\n>>> 2669| .Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.\n 2670| [float=\"center\",align=\"center\",cols=\"2,^,^,^,^\",options=\"header\"]\n 2671| |===" + }, + { + "score": 9, + "reasons": [ + "Description keyword 'misaligned'", + "Name segment 'MISALIGNED'", + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Name segment 'ADDRESS'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 139, + "line_text": "[#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch", + "context": " 137| (R/I/S/U), as shown in <>. All are a fixed 32 bits in length.\n 138| The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.\n>>> 139| [#norm:taken_cti_misaligned_exc]#An instruction-address-misaligned exception is generated on a taken branch\n 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#" + }, + { + "score": 9, + "reasons": [ + "Description keyword 'misaligned'", + "Name segment 'MISALIGNED'", + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Name segment 'ADDRESS'" + ], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 142, + "line_text": "[#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated", + "context": " 140| or unconditional jump if the target address is not `IALIGN-bit` aligned.\n 141| This exception is reported on the branch or jump instruction, not on the target instruction.#\n>>> 142| [#norm:cond_br_no_ia_misaligned_exc_not_taken]#No instruction-address-misaligned exception is generated\n 143| for a conditional branch that is not taken.#\n 144| " + }, + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_LOAD_ACCESS_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'VU'", + "Description keyword 'VS'", + "Name segment 'ACCESS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2370, + "line_text": "* [#norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0]#in VS-mode or VU-mode, attempts to access an implemented non-high-half", + "context": " 2368| (HLV, HLVX, HSV, or HFENCE);#\n 2369| \n>>> 2370| * [#norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0]#in VS-mode or VU-mode, attempts to access an implemented non-high-half\n 2371| hypervisor CSR or VS CSR when the same access (read/write) would be\n 2372| allowed in HS-mode, assuming `mstatus`.TVM=0;#" + }, + { + "score": 7, + "reasons": [ + "Description keyword 'VU'", + "Description keyword 'VS'", + "Name segment 'ACCESS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2374, + "line_text": "* [#norm:H_virtinst_vu_vs32_high_allowedhs_tvm0]#in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented", + "context": " 2372| allowed in HS-mode, assuming `mstatus`.TVM=0;#\n 2373| \n>>> 2374| * [#norm:H_virtinst_vu_vs32_high_allowedhs_tvm0]#in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented\n 2375| high-half hypervisor CSR or high-half VS CSR when the same access\n 2376| (read/write) to the CSR\"s low-half partner would be allowed in HS-mode," + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 7, + "reasons": [ + "Name segment 'LOAD'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'ADDRESS'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1976, + "line_text": "[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or", + "context": " 1974| raised.\n 1975| \n>>> 1976| [#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or\n 1977| lower priority than load/store/AMO page-fault and access-fault exceptions.#\n 1978| " + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_LOAD_PAGE_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_MCALL", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_SCALL", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'VU'", + "Description keyword 'VS'", + "Name segment 'ACCESS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2370, + "line_text": "* [#norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0]#in VS-mode or VU-mode, attempts to access an implemented non-high-half", + "context": " 2368| (HLV, HLVX, HSV, or HFENCE);#\n 2369| \n>>> 2370| * [#norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0]#in VS-mode or VU-mode, attempts to access an implemented non-high-half\n 2371| hypervisor CSR or VS CSR when the same access (read/write) would be\n 2372| allowed in HS-mode, assuming `mstatus`.TVM=0;#" + }, + { + "score": 7, + "reasons": [ + "Description keyword 'VU'", + "Description keyword 'VS'", + "Name segment 'ACCESS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2374, + "line_text": "* [#norm:H_virtinst_vu_vs32_high_allowedhs_tvm0]#in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented", + "context": " 2372| allowed in HS-mode, assuming `mstatus`.TVM=0;#\n 2373| \n>>> 2374| * [#norm:H_virtinst_vu_vs32_high_allowedhs_tvm0]#in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented\n 2375| high-half hypervisor CSR or high-half VS CSR when the same access\n 2376| (read/write) to the CSR\"s low-half partner would be allowed in HS-mode," + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 7, + "reasons": [ + "Name segment 'STORE'", + "Name segment 'MISALIGNED'", + "Description keyword 'misaligned'", + "Name segment 'ADDRESS'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1976, + "line_text": "[#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or", + "context": " 1974| raised.\n 1975| \n>>> 1976| [#norm:mcause_exccode_pri2]#Load/store/AMO address-misaligned exceptions may have either higher or\n 1977| lower priority than load/store/AMO page-fault and access-fault exceptions.#\n 1978| " + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_STORE_AMO_PAGE_FAULT", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_UCALL", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_VIRTUAL_INSTRUCTION", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": [ + "Name segment 'VIRTUAL'", + "Description keyword 'VU'", + "Description keyword 'instruction'", + "Name segment 'INSTRUCTION'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 218, + "line_text": "[#norm:sctrdepth_mode]#Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.# See <>.", + "context": " 216| |===\n 217| \n>>> 218| [#norm:sctrdepth_mode]#Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.# See <>.\n 219| \n 220| [NOTE]" + }, + { + "score": 9, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'VU'", + "Description keyword 'instruction'", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2367, + "line_text": "* [#norm:H_virtinst_vu_vs_hinst]#in VS-mode or VU-mode, attempts to execute a hypervisor instruction", + "context": " 2365| and the same bit in `mcounteren` is 1;#\n 2366| \n>>> 2367| * [#norm:H_virtinst_vu_vs_hinst]#in VS-mode or VU-mode, attempts to execute a hypervisor instruction\n 2368| (HLV, HLVX, HSV, or HFENCE);#\n 2369| " + }, + { + "score": 9, + "reasons": [ + "CSR name 'mtinst' in backticks", + "Name segment 'INSTRUCTION'", + "CSR name 'htinst' in backticks", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2567, + "line_text": "==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "context": " 2565| \n 2566| [[tinst-vals]]\n>>> 2567| ==== Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`\n 2568| \n 2569| [[norm:H_trap_xtinst]]" + }, + { + "score": 9, + "reasons": [ + "CSR name 'mtinst' in backticks", + "Name segment 'INSTRUCTION'", + "CSR name 'htinst' in backticks", + "Description keyword 'instruction'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2669, + "line_text": ".Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.", + "context": " 2667| \n 2668| [[tinst-values]]\n>>> 2669| .Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.\n 2670| [float=\"center\",align=\"center\",cols=\"2,^,^,^,^\",options=\"header\"]\n 2671| |===" + }, + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + } + ] + }, + { + "parameter_name": "TINST_VALUE_ON_VSCALL", + "classification": "NORM_CSR_RW", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["WARL + CSR 'htinst'", "CSR name 'htinst' in backticks"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 983, + "line_text": "`htinst` is a *WARL* register that need only be able to hold the values that", + "context": " 981| \n 982| [[norm:htinst_val]]\n>>> 983| `htinst` is a *WARL* register that need only be able to hold the values that\n 984| the implementation may automatically write to it on a trap.\n 985| " + }, + { + "score": 8, + "reasons": ["CSR name 'mtinst' in backticks", "WARL + CSR 'mtinst'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1866, + "line_text": "`mtinst` is a *WARL* register that need only be able to hold the values that", + "context": " 1864| \n 1865| [[norm:mtinst_val]]\n>>> 1866| `mtinst` is a *WARL* register that need only be able to hold the values that\n 1867| the implementation may automatically write to it on a trap.\n 1868| " + }, + { + "score": 8, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR field name 'VALUE'", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2581, + "line_text": "value written to `mtinst` or `htinst` may always be zero, indicating", + "context": " 2579| \n 2580| Except when a pseudoinstruction value is required (described later), the\n>>> 2581| value written to `mtinst` or `htinst` may always be zero, indicating\n 2582| that the hardware is providing no information in the register for this\n 2583| particular trap." + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "cmo.adoc", + "line_number": 483, + "line_text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the", + "context": " 481| \n 482| [[norm:h_trans_cache]]\n>>> 483| For the purposes of writing the `mtinst` or `htinst` register on a trap, the\n 484| following standard transformation is defined for cache-block management\n 485| instructions and cache-block zero instructions:" + }, + { + "score": 6, + "reasons": [ + "CSR name 'mtinst' in backticks", + "CSR name 'htinst' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2049, + "line_text": "shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written", + "context": " 2047| faulting guest virtual address as usual, and `mtval2` or `htval` is\n 2048| written either with zero or with the faulting guest physical address,\n>>> 2049| shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written\n 2050| with information about the faulting instruction or other reason for the\n 2051| access, as explained in <>." + } + ] + }, + { + "parameter_name": "TRAP_ON_EBREAK", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 684, + "line_text": "[#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#", + "context": " 682| even though the load value is discarded.#\n 683| \n>>> 684| [#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#\n 685| [#norm:ldst_endian_byte_invariant]#In RISC-V, endianness is byte-address invariant.#\n 686| " + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 730, + "line_text": "Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are", + "context": " 728| 8-bit values from the low bits of register _rs2_ to memory.#\n 729| \n>>> 730| Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are\n 731| naturally aligned shall not raise an address-misaligned exception.#\n 732| [#norm:MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR]#Loads and stores whose effective address is not naturally aligned to the" + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + }, + { + "score": 3, + "reasons": ["Name segment 'EBREAK'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 788, + "line_text": "[#norm:c-ebreak_op]#Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`,", + "context": " 786| ((((compressed. C.BREAKPOINTINSTR))))\n 787| \n>>> 788| [#norm:c-ebreak_op]#Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`,\n 789| to cause control to be transferred back to the debugging environment.\n 790| `C.EBREAK` shares the opcode with the `C.ADD` instruction, but with _rd_ and" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + } + ] + }, + { + "parameter_name": "TRAP_ON_ECALL_FROM_M", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 4, + "candidates": [ + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 684, + "line_text": "[#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#", + "context": " 682| even though the load value is discarded.#\n 683| \n>>> 684| [#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#\n 685| [#norm:ldst_endian_byte_invariant]#In RISC-V, endianness is byte-address invariant.#\n 686| " + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 730, + "line_text": "Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are", + "context": " 728| 8-bit values from the low bits of register _rs2_ to memory.#\n 729| \n>>> 730| Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are\n 731| naturally aligned shall not raise an address-misaligned exception.#\n 732| [#norm:MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR]#Loads and stores whose effective address is not naturally aligned to the" + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + }, + { + "score": 3, + "reasons": ["Name segment 'FROM'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 304, + "line_text": "[#norm:c-lwsp_op]#C.LWSP loads a 32-bit value from memory into register _rd_. It computes", + "context": " 302| These instructions use the CI format.\n 303| \n>>> 304| [#norm:c-lwsp_op]#C.LWSP loads a 32-bit value from memory into register _rd_. It computes\n 305| an effective address by adding the _zero_-extended offset, scaled by 4,\n 306| to the stack pointer, `x2`. It expands to `lw rd, offset(x2)`.#" + }, + { + "score": 3, + "reasons": ["Name segment 'FROM'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 406, + "line_text": "[#norm:c-lw_op]#C.LW loads a 32-bit value from memory into register", + "context": " 404| These instructions use the CL format.\n 405| \n>>> 406| [#norm:c-lw_op]#C.LW loads a 32-bit value from memory into register\n 407| `_rd′_`. It computes an effective address by adding the\n 408| _zero_-extended offset, scaled by 4, to the base address in register" + } + ] + }, + { + "parameter_name": "TRAP_ON_ECALL_FROM_S", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": ["Name segment 'ECALL'", "Description keyword 'ECALL'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 925, + "line_text": "[#norm:ecall_op]#The `ECALL` instruction is used to make a service request to the execution environment.#", + "context": " 923| execution environment.\n 924| \n>>> 925| [#norm:ecall_op]#The `ECALL` instruction is used to make a service request to the execution environment.#\n 926| The `EEI` will define how parameters for the service request\n 927| are passed, but usually these will be in defined locations in the" + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 684, + "line_text": "[#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#", + "context": " 682| even though the load value is discarded.#\n 683| \n>>> 684| [#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#\n 685| [#norm:ldst_endian_byte_invariant]#In RISC-V, endianness is byte-address invariant.#\n 686| " + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 730, + "line_text": "Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are", + "context": " 728| 8-bit values from the low bits of register _rs2_ to memory.#\n 729| \n>>> 730| Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are\n 731| naturally aligned shall not raise an address-misaligned exception.#\n 732| [#norm:MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR]#Loads and stores whose effective address is not naturally aligned to the" + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + }, + { + "score": 3, + "reasons": ["Name segment 'FROM'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 304, + "line_text": "[#norm:c-lwsp_op]#C.LWSP loads a 32-bit value from memory into register _rd_. It computes", + "context": " 302| These instructions use the CI format.\n 303| \n>>> 304| [#norm:c-lwsp_op]#C.LWSP loads a 32-bit value from memory into register _rd_. It computes\n 305| an effective address by adding the _zero_-extended offset, scaled by 4,\n 306| to the stack pointer, `x2`. It expands to `lw rd, offset(x2)`.#" + } + ] + }, + { + "parameter_name": "TRAP_ON_ECALL_FROM_U", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": ["Name segment 'ECALL'", "Description keyword 'ECALL'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 925, + "line_text": "[#norm:ecall_op]#The `ECALL` instruction is used to make a service request to the execution environment.#", + "context": " 923| execution environment.\n 924| \n>>> 925| [#norm:ecall_op]#The `ECALL` instruction is used to make a service request to the execution environment.#\n 926| The `EEI` will define how parameters for the service request\n 927| are passed, but usually these will be in defined locations in the" + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 684, + "line_text": "[#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#", + "context": " 682| even though the load value is discarded.#\n 683| \n>>> 684| [#norm:ENDIANNESS_LITTLE_OR_BIG]#The EEI will define whether the memory system is little-endian or big-endian.#\n 685| [#norm:ldst_endian_byte_invariant]#In RISC-V, endianness is byte-address invariant.#\n 686| " + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 730, + "line_text": "Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are", + "context": " 728| 8-bit values from the low bits of register _rs2_ to memory.#\n 729| \n>>> 730| Regardless of EEI, [#norm:ldst_no_exc_aligned]#loads and stores whose effective addresses are\n 731| naturally aligned shall not raise an address-misaligned exception.#\n 732| [#norm:MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR]#Loads and stores whose effective address is not naturally aligned to the" + }, + { + "score": 4, + "reasons": ["Description keyword 'EEI'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 753, + "line_text": "[#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and", + "context": " 751| access should not be emulated, e.g., if accesses to the memory region\n 752| have side effects.#\n>>> 753| [#norm:MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP]#When an EEI does not guarantee misaligned loads and\n 754| stores are handled invisibly, the EEI must define if exceptions caused\n 755| by address misalignment result in a contained trap (allowing software" + }, + { + "score": 3, + "reasons": ["Name segment 'FROM'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 304, + "line_text": "[#norm:c-lwsp_op]#C.LWSP loads a 32-bit value from memory into register _rd_. It computes", + "context": " 302| These instructions use the CI format.\n 303| \n>>> 304| [#norm:c-lwsp_op]#C.LWSP loads a 32-bit value from memory into register _rd_. It computes\n 305| an effective address by adding the _zero_-extended offset, scaled by 4,\n 306| to the stack pointer, `x2`. It expands to `lw rd, offset(x2)`.#" + } + ] + }, + { + "parameter_name": "TRAP_ON_ECALL_FROM_VS", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 932, + "line_text": "[#norm:mstatus_sd_rdonly0]#If FS, XS, and VS are all read-only zero, then SD is also always zero.#", + "context": " 930| or XS fields signal the presence of some dirty state that will require\n 931| saving extended user context to memory.#\n>>> 932| [#norm:mstatus_sd_rdonly0]#If FS, XS, and VS are all read-only zero, then SD is also always zero.#\n 933| \n 934| [#norm:mstatus_fs_vs_xs_off_op]#When an extension's status is set to Off, any instruction that attempts" + }, + { + "score": 5, + "reasons": ["Name segment 'ECALL'", "Description keyword 'ECALL'"], + "is_normative": true, + "in_note": false, + "file": "rv32.adoc", + "line_number": 925, + "line_text": "[#norm:ecall_op]#The `ECALL` instruction is used to make a service request to the execution environment.#", + "context": " 923| execution environment.\n 924| \n>>> 925| [#norm:ecall_op]#The `ECALL` instruction is used to make a service request to the execution environment.#\n 926| The `EEI` will define how parameters for the service request\n 927| are passed, but usually these will be in defined locations in the" + }, + { + "score": 5, + "reasons": ["Name segment 'FROM'", "Description keyword 'VS'"], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 218, + "line_text": "[#norm:sctrdepth_mode]#Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.# See <>.", + "context": " 216| |===\n 217| \n>>> 218| [#norm:sctrdepth_mode]#Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.# See <>.\n 219| \n 220| [NOTE]" + }, + { + "score": 5, + "reasons": ["Name segment 'FROM'", "Description keyword 'VS'"], + "is_normative": true, + "in_note": false, + "file": "smctr.adoc", + "line_number": 507, + "line_text": "[#norm:exttrap_def]#External traps are traps from a privilege mode enabled for CTR recording to a privilege mode that is not enabled for CTR recording. By default external traps are not recorded, but privileged software running in the target mode of the trap can opt-in to allowing CTR to record external traps into that mode. The `__x__ctrctl`.__x__TE bits allow M-mode, S-mode, and VS-mode to opt-in separately.#", + "context": " 505| ===== External Traps\n 506| \n>>> 507| [#norm:exttrap_def]#External traps are traps from a privilege mode enabled for CTR recording to a privilege mode that is not enabled for CTR recording. By default external traps are not recorded, but privileged software running in the target mode of the trap can opt-in to allowing CTR to record external traps into that mode. The `__x__ctrctl`.__x__TE bits allow M-mode, S-mode, and VS-mode to opt-in separately.#\n 508| \n 509| [#norm:exttrap_requirements]#External trap recording depends not only on the target mode, but on any intervening modes, which are modes that are more privileged than the source mode but less privileged than the target mode. Not only must the external trap enable bit for the target mode be set, but the external trap enable bit(s) for any intervening modes must also be set.# See the table below for details." + }, + { + "score": 5, + "reasons": ["Name segment 'FROM'", "Description keyword 'VS'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 133, + "line_text": "[#norm:hw_mstatus_vs_dirty_update_param]#Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or", + "context": " 131| any instruction that changes vector state, including the vector CSRs, will\n 132| change both `mstatus.VS` and `vsstatus.VS` to Dirty.#\n>>> 133| [#norm:hw_mstatus_vs_dirty_update_param]#Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or\n 134| Clean to Dirty at any time, even when there is no change in vector state.#\n 135| " + } + ] + }, + { + "parameter_name": "TRAP_ON_ILLEGAL_WLRL", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 3, + "candidates": [ + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 231, + "line_text": "[#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the", + "context": " 229| \n 230| [#norm:misa_e_acc]#The \"E\" bit is read-only.#\n>>> 231| [#norm:misa_e_not_i]#Unless `misa` is all read-only zero, the\n 232| \"E\" bit always reads as the complement of the \"I\" bit.#\n 233| If an execution environment supports both RV32E and RV32I, software can select" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 577, + "line_text": "[#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "context": " 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n>>> 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.\n 578| Otherwise, it is a *WARL* field that encodes the current value of SXLEN.#\n 579| In particular, [#norm:mstatus_sxl_rdonly_mxlen64]#an implementation may make SXL be a read-only field whose" + } + ] + }, + { + "parameter_name": "TRAP_ON_RESERVED_INSTRUCTION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'RESERVED'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 756, + "line_text": "[#norm:Zca_illegal]#A 16-bit instruction with all bits zero is permanently reserved as an", + "context": " 754| ((((compressed. C.DIINST))))\n 755| \n>>> 756| [#norm:Zca_illegal]#A 16-bit instruction with all bits zero is permanently reserved as an\n 757| illegal instruction.#\n 758| " + }, + { + "score": 6, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'RESERVED'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 1553, + "line_text": "EMUL<1/8), the instruction encoding is reserved.# [#norm:vector_ls_emul_offgroup_rsv]#The vector register", + "context": " 1551| instruction. The corresponding EMUL is calculated as EMUL =\n 1552| (EEW/SEW)*LMUL.# [#norm:vector_ls_emul_rsv]#If the EMUL would be out of range (EMUL>8 or\n>>> 1553| EMUL<1/8), the instruction encoding is reserved.# [#norm:vector_ls_emul_offgroup_rsv]#The vector register\n 1554| groups must have legal register specifiers for the selected EMUL,\n 1555| otherwise the instruction encoding is reserved.#" + }, + { + "score": 6, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'RESERVED'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 2089, + "line_text": "otherwise the instruction encoding is reserved. [#norm:vector_ls_seg_wholereg_op]#NFIELDS", + "context": " 2087| The encoded number of registers must be a power of 2 and the vector\n 2088| register numbers must be aligned as with a vector register group,\n>>> 2089| otherwise the instruction encoding is reserved. [#norm:vector_ls_seg_wholereg_op]#NFIELDS\n 2090| indicates the number of vector registers to transfer, numbered\n 2091| successively after the base.# [#norm:vector_ls_seg_wholereg_nf_rsv]#Only NFIELDS values of 1, 2, 4, 8 are" + }, + { + "score": 6, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Name segment 'RESERVED'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 2631, + "line_text": "[#norm:vadc_vsbc_vd_v0_rsv]#For `vadc` and `vsbc`, the instruction encoding is reserved if the", + "context": " 2629| truncation, is negative.#\n 2630| \n>>> 2631| [#norm:vadc_vsbc_vd_v0_rsv]#For `vadc` and `vsbc`, the instruction encoding is reserved if the\n 2632| destination vector register is `v0`.#\n 2633| " + }, + { + "score": 5, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 310, + "line_text": "[#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value", + "context": " 308| valid only when _rd_≠`x0`; the code points with _rd_=`x0` are reserved.#\n 309| \n>>> 310| [#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value\n 311| from memory into register _rd_. It computes its effective address by\n 312| adding the zero-extended offset, scaled by 8, to the stack pointer," + } + ] + }, + { + "parameter_name": "TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'SATP'", + "Name segment 'SFENCE'", + "Description keyword 'SFENCE.VMA'", + "Description keyword 'satp'", + "Description keyword 'MODE'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 250, + "line_text": "VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR `satp`", + "context": " 248| interrupts when the instruction is executed.#\n 249| [#norm:hstatus-vtvm_op]#When VTVM=1, an attempt in\n>>> 250| VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR `satp`\n 251| raises a virtual-instruction exception.#\n 252| " + }, + { + "score": 9, + "reasons": [ + "Optional/read-only pattern for boolean param", + "Name segment 'SATP'", + "Description keyword 'satp'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 670, + "line_text": "[#norm:mstatus_sum_rdonly0]#SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.#", + "context": " 668| Note that, [#norm:mstatus_sum_op_mprv_mpp]#while SUM is ordinarily ignored when not\n 669| executing in S-mode, it _is_ in effect when MPRV=1 and MPP=S.#\n>>> 670| [#norm:mstatus_sum_rdonly0]#SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.#\n 671| \n 672| [[norm:mstatus_mxr_sum_op_acc_fault]]" + }, + { + "score": 8, + "reasons": [ + "Name segment 'SATP'", + "Description keyword 'satp'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 216, + "line_text": "[#norm:satp-mode_bare]#If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective", + "context": " 214| `henvcfg.SSE=0`, this encoding remains reserved at `VS` and `VU` levels.#\n 215| \n>>> 216| [#norm:satp-mode_bare]#If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective\n 217| privilege mode is less than M, shadow stack instructions raise a store/AMO access-fault exception.#\n 218| [#norm:ssmp_ssamoswap]#When the effective privilege mode is M, memory access" + }, + { + "score": 8, + "reasons": [ + "Name segment 'SATP'", + "Description keyword 'satp'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 1008, + "line_text": "[[norm:satp-mode]]", + "context": " 1006| ====\n 1007| \n>>> 1008| [[norm:satp-mode]]\n 1009| <> shows the encodings of the MODE field when\n 1010| SXLEN=32 and SXLEN=64. When MODE=Bare, supervisor virtual addresses are" + }, + { + "score": 7, + "reasons": [ + "Name segment 'SFENCE'", + "Description keyword 'SFENCE.VMA'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2397, + "line_text": "* [#norm:H_virtinst_vs_sfence_sinval_satp_vtvm1]#in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA", + "context": " 2395| * [#norm:H_virtinst_vs_sret_vtsr1]#in VS-mode, attempts to execute SRET when `hstatus`.VTSR=1#; and\n 2396| \n>>> 2397| * [#norm:H_virtinst_vs_sfence_sinval_satp_vtvm1]#in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA\n 2398| instruction or to access `satp`, when `hstatus`.VTVM=1.#\n 2399| " + } + ] + }, + { + "parameter_name": "TRAP_ON_UNIMPLEMENTED_CSR", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": ["Description keyword 'Zicsr'"], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 5140, + "line_text": "[#norm:Zve32x_dependent_Zicsr]#The Zve32x extension depends on the Zicsr extension.#", + "context": " 5138| with EEW=64 floating-point operands.#\n 5139| \n>>> 5140| [#norm:Zve32x_dependent_Zicsr]#The Zve32x extension depends on the Zicsr extension.#\n 5141| [#norm:Zve32f_Zve64f_dependent_F]#The Zve32f and Zve64f extensions depend upon the F extension,\n 5142| and implement all" + }, + { + "score": 6, + "reasons": ["Description keyword 'Zicsr'"], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 16, + "line_text": "The Zicntr extension depends on the Zicsr extension.", + "context": " 14| counters (CYCLE, TIME, and INSTRET), which have dedicated functions\n 15| (cycle count, real-time clock, and instructions retired, respectively).\n>>> 16| The Zicntr extension depends on the Zicsr extension.\n 17| \n 18| [NOTE]" + }, + { + "score": 6, + "reasons": ["Description keyword 'Zicsr'"], + "is_normative": false, + "in_note": false, + "file": "counters.adoc", + "line_number": 197, + "line_text": "depends on the Zicsr extension.", + "context": " 195| XLEN=32, the upper 32 bits of these performance counters are accessible\n 196| via additional CSRs `hpmcounter3h- hpmcounter31h`.# The Zihpm extension\n>>> 197| depends on the Zicsr extension.\n 198| [NOTE]\n 199| ====" + }, + { + "score": 6, + "reasons": ["Description keyword 'Zicsr'"], + "is_normative": false, + "in_note": false, + "file": "f-st-ext.adoc", + "line_number": 10, + "line_text": "with the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the \"Zicsr\" extension for control and status register access.", + "context": " 8| single-precision floating-point, which is named \"F\" and adds\n 9| single-precision floating-point computational instructions compliant\n>>> 10| with the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the \"Zicsr\" extension for control and status register access.\n 11| \n 12| === F Register State" + }, + { + "score": 6, + "reasons": ["Description keyword 'Zicsr'"], + "is_normative": false, + "in_note": false, + "file": "naming.adoc", + "line_number": 44, + "line_text": "\"D\" depends on \"F\" and \"F\" depends on \"Zicsr\". These dependencies", + "context": " 42| \n 43| Some ISA extensions depend on the presence of other extensions, e.g.,\n>>> 44| \"D\" depends on \"F\" and \"F\" depends on \"Zicsr\". These dependencies\n 45| may be implicit in the ISA name: for example, RV32IF is equivalent to\n 46| RV32IFZicsr, and RV32ID is equivalent to RV32IFD and RV32IFDZicsr." + } + ] + }, + { + "parameter_name": "TRAP_ON_UNIMPLEMENTED_INSTRUCTION", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 5, + "candidates": [ + { + "score": 5, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 310, + "line_text": "[#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value", + "context": " 308| valid only when _rd_≠`x0`; the code points with _rd_=`x0` are reserved.#\n 309| \n>>> 310| [#norm:c-ldsp_op]#C.LDSP is an RV64C-only instruction that loads a 64-bit value\n 311| from memory into register _rd_. It computes its effective address by\n 312| adding the zero-extended offset, scaled by 8, to the stack pointer," + }, + { + "score": 5, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 318, + "line_text": "[#norm:c-flwsp_op]#C.FLWSP is an RV32FC-only instruction that loads a single-precision", + "context": " 316| _rd_=`x0` are reserved.#\n 317| \n>>> 318| [#norm:c-flwsp_op]#C.FLWSP is an RV32FC-only instruction that loads a single-precision\n 319| floating-point value from memory into floating-point register _rd_. It\n 320| computes its effective address by adding the _zero_-extended offset," + }, + { + "score": 5, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 324, + "line_text": "[#norm:c-fldsp_op]#C.FLDSP is an RV32DC/RV64DC-only instruction that loads a", + "context": " 322| `flw rd, offset(x2)`.#\n 323| \n>>> 324| [#norm:c-fldsp_op]#C.FLDSP is an RV32DC/RV64DC-only instruction that loads a\n 325| double-precision floating-point value from memory into floating-point\n 326| register _rd_. It computes its effective address by adding the" + }, + { + "score": 5, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 340, + "line_text": "[#norm:c-sdsp_op]#C.SDSP is an RV64C-only instruction that stores a 64-bit value in", + "context": " 338| the stack pointer, `x2`. It expands to `sw rs2, offset(x2)`.#\n 339| \n>>> 340| [#norm:c-sdsp_op]#C.SDSP is an RV64C-only instruction that stores a 64-bit value in\n 341| register _rs2_ to memory. It computes an effective address by adding the\n 342| _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It" + }, + { + "score": 5, + "reasons": [ + "Name segment 'INSTRUCTION'", + "Description keyword 'instruction'" + ], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 345, + "line_text": "[#norm:c-fswsp_op]#C.FSWSP is an RV32FC-only instruction that stores a single-precision", + "context": " 343| expands to `sd rs2, offset(x2)`.#\n 344| \n>>> 345| [#norm:c-fswsp_op]#C.FSWSP is an RV32FC-only instruction that stores a single-precision\n 346| floating-point value in floating-point register _rs2_ to memory. It\n 347| computes an effective address by adding the _zero_-extended offset," + } + ] + }, + { + "parameter_name": "UXLEN", + "classification": "NORM_DIRECT", + "value_type": "set", + "num_candidates": 10, + "best_score": 11, + "candidates": [ + { + "score": 11, + "reasons": [ + "CSR field name 'UXL'", + "Name segment 'UXLEN'", + "Exact parameter name 'UXLEN'", + "Description keyword 'UXL'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 575, + "line_text": "When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.", + "context": " 573| \n 574| [[norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32]]\n>>> 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero." + }, + { + "score": 11, + "reasons": [ + "CSR field name 'UXL'", + "Name segment 'UXLEN'", + "Exact parameter name 'UXLEN'", + "Description keyword 'UXL'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 143, + "line_text": "When SXLEN=32, the UXL field does not exist, and UXLEN=32. When", + "context": " 141| \n 142| [[norm:sstatus-uxl_sz]]\n>>> 143| When SXLEN=32, the UXL field does not exist, and UXLEN=32. When\n 144| SXLEN=64, it is a *WARL* field that encodes the current value of UXLEN. In\n 145| particular, an implementation may make UXL be a read-only field whose" + }, + { + "score": 10, + "reasons": [ + "CSR field name 'UXL'", + "Description keyword 'UXL'", + "Parameter name in emphasis '_UXLEN_'" + ], + "is_normative": false, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 137, + "line_text": "The UXL field controls the value of XLEN for U-mode, termed _UXLEN_,", + "context": " 135| \n 136| [[norm:sstatus-uxl]]\n>>> 137| The UXL field controls the value of XLEN for U-mode, termed _UXLEN_,\n 138| which may differ from the value of XLEN for S-mode, termed _SXLEN_. The\n 139| encoding of UXL is the same as that of the MXL field of `misa`, shown in" + }, + { + "score": 9, + "reasons": [ + "CSR name 'mstatus' in backticks", + "CSR field name 'UXL'", + "Description keyword 'UXL'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 393, + "line_text": "[#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#", + "context": " 391| \n 392| [#norm:mstatush_sz_acc]#For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>.#\n>>> 393| [#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#\n 394| \n 395| [[mstatushreg]]" + }, + { + "score": 8, + "reasons": ["Parameter name in emphasis '_UXLEN_'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 572, + "line_text": "[#norm:sxlen_uxlen]#The effective XLEN in S-mode and U-mode are termed _SXLEN_ and _UXLEN_, respectively.#", + "context": " 570| value of XLEN for S-mode and U-mode, respectively.#\n 571| [#norm:mstatus_sxl_uxl_enc]#The encoding of these fields is the same as the MXL field of `misa`, shown in <>.#\n>>> 572| [#norm:sxlen_uxlen]#The effective XLEN in S-mode and U-mode are termed _SXLEN_ and _UXLEN_, respectively.#\n 573| \n 574| [[norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32]]" + } + ] + }, + { + "parameter_name": "U_MODE_ENDIANNESS", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 14, + "candidates": [ + { + "score": 14, + "reasons": [ + "CSR field name 'UBE'", + "WARL + CSR 'mstatus'", + "CSR name 'mstatus' in backticks", + "Description keyword 'UBE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 679, + "line_text": "[#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that", + "context": " 677| ===== Endianness Control in `mstatus` and `mstatush` Registers\n 678| \n>>> 679| [#norm:mstatus_mstatush_xbe_warl]#The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields# that\n 680| control the endianness of memory accesses other than instruction fetches.\n 681| [#norm:endianness_inst_fetch_little]#Instruction fetches are always little-endian.#" + }, + { + "score": 8, + "reasons": [ + "WARL + CSR 'mstatus'", + "CSR name 'mstatus' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 501, + "line_text": "* Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.", + "context": " 499| the possibility of a future global-ASID extension.\n 500| * SFENCE.VMA semantics have been clarified.\n>>> 501| * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*.\n 502| * Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*.\n 503| * Made the unused `misa` fields *WARL*, rather than *WIRI*." + }, + { + "score": 6, + "reasons": [ + "CSR field name 'UBE'", + "Description keyword 'endian'", + "Description keyword 'UBE'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 696, + "line_text": "little-endian (UBE=0) or big-endian (UBE=1).", + "context": " 694| If U-mode is not supported, UBE is read-only 0. Otherwise, UBE controls\n 695| whether explicit load and store memory accesses made from U-mode are\n>>> 696| little-endian (UBE=0) or big-endian (UBE=1).\n 697| \n 698| [#norm:mstatus_sbe_implicit]#For _implicit_ accesses to supervisor-level memory management data" + }, + { + "score": 6, + "reasons": ["CSR field name 'UBE'", "Description keyword 'UBE'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 718, + "line_text": "[#norm:mstatus_ube_rocopy]#If U-mode is supported, an implementation may make UBE be a", + "context": " 716| [#norm:mstatus_sbe_rocopy]#If S-mode is supported, an implementation may make SBE be a read-only\n 717| copy of MBE.#\n>>> 718| [#norm:mstatus_ube_rocopy]#If U-mode is supported, an implementation may make UBE be a\n 719| read-only copy of either MBE or SBE.#\n 720| " + }, + { + "score": 6, + "reasons": ["CSR field name 'UBE'", "Description keyword 'UBE'"], + "is_normative": true, + "in_note": false, + "file": "supervisor.adoc", + "line_number": 224, + "line_text": "[[norm:sstatus-ube]]", + "context": " 222| ===== Endianness Control in `sstatus` Register\n 223| \n>>> 224| [[norm:sstatus-ube]]\n 225| The UBE bit is a *WARL* field that controls the endianness of explicit memory\n 226| accesses made from U-mode, which may differ from the endianness of" + } + ] + }, + { + "parameter_name": "VENDOR_ID_BANK", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "Description keyword 'mvendorid'", + "Description keyword 'JEDEC'", + "CSR name 'mvendorid' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 263, + "line_text": "[#norm:mvendorid_sz_acc_op]#The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC", + "context": " 261| ==== Machine Vendor ID (`mvendorid`) Register\n 262| \n>>> 263| [#norm:mvendorid_sz_acc_op]#The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC\n 264| manufacturer ID of the provider of the core.#\n 265| [#norm:mvendorid_always_rd]#This register must be readable in any implementation, but a value of 0 can be returned to" + }, + { + "score": 10, + "reasons": [ + "Description keyword 'mvendorid'", + "Description keyword 'JEDEC'", + "CSR name 'mvendorid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "priv-preface.adoc", + "line_number": 531, + "line_text": "* The `mvendorid` register now contains the JEDEC code of the core", + "context": " 529| * The explicit convention on shadow CSR addresses has been removed to\n 530| reclaim CSR space. Shadow CSRs can still be added as needed.\n>>> 531| * The `mvendorid` register now contains the JEDEC code of the core\n 532| provider as opposed to a code supplied by the Foundation. This avoids\n 533| redundancy and offloads work from the Foundation." + }, + { + "score": 7, + "reasons": [ + "Description keyword 'mvendorid'", + "Name segment 'VENDOR'", + "CSR name 'mvendorid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 261, + "line_text": "==== Machine Vendor ID (`mvendorid`) Register", + "context": " 259| reserved, not necessarily illegal.\n 260| \n>>> 261| ==== Machine Vendor ID (`mvendorid`) Register\n 262| \n 263| [#norm:mvendorid_sz_acc_op]#The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC" + }, + { + "score": 7, + "reasons": [ + "Description keyword 'mvendorid'", + "Name segment 'VENDOR'", + "CSR name 'mvendorid' in backticks" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 271, + "line_text": ".Vendor ID register (`mvendorid`)", + "context": " 269| //image::png/mvendorid.png[align=\"center\"]\n 270| \n>>> 271| .Vendor ID register (`mvendorid`)\n 272| include::images/bytefield/mvendorid.edn[]\n 273| " + }, + { + "score": 6, + "reasons": ["Description keyword 'JEDEC'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 274, + "line_text": "[#norm:mvendorid_enc]#JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte", + "context": " 272| include::images/bytefield/mvendorid.edn[]\n 273| \n>>> 274| [#norm:mvendorid_enc]#JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte\n 275| continuation codes `0x7f`, terminated by a one-byte ID not equal to\n 276| `0x7f`, with an odd parity bit in the most-significant bit of each byte." + } + ] + }, + { + "parameter_name": "VENDOR_ID_OFFSET", + "classification": "NORM_DIRECT", + "value_type": "range", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": [ + "Description keyword 'JEDEC'", + "CSR name 'mvendorid' in backticks" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 263, + "line_text": "[#norm:mvendorid_sz_acc_op]#The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC", + "context": " 261| ==== Machine Vendor ID (`mvendorid`) Register\n 262| \n>>> 263| [#norm:mvendorid_sz_acc_op]#The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC\n 264| manufacturer ID of the provider of the core.#\n 265| [#norm:mvendorid_always_rd]#This register must be readable in any implementation, but a value of 0 can be returned to" + }, + { + "score": 6, + "reasons": [ + "Name segment 'VENDOR'", + "CSR name 'mvendorid' in backticks", + "Description keyword 'ID'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 261, + "line_text": "==== Machine Vendor ID (`mvendorid`) Register", + "context": " 259| reserved, not necessarily illegal.\n 260| \n>>> 261| ==== Machine Vendor ID (`mvendorid`) Register\n 262| \n 263| [#norm:mvendorid_sz_acc_op]#The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC" + }, + { + "score": 6, + "reasons": [ + "Name segment 'VENDOR'", + "CSR name 'mvendorid' in backticks", + "Description keyword 'ID'" + ], + "is_normative": false, + "in_note": false, + "file": "machine.adoc", + "line_number": 271, + "line_text": ".Vendor ID register (`mvendorid`)", + "context": " 269| //image::png/mvendorid.png[align=\"center\"]\n 270| \n>>> 271| .Vendor ID register (`mvendorid`)\n 272| include::images/bytefield/mvendorid.edn[]\n 273| " + }, + { + "score": 5, + "reasons": ["CSR field name 'Offset'", "Name segment 'OFFSET'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 476, + "line_text": "[#norm:c-j_op]#C.J performs an unconditional control transfer. The offset is", + "context": " 474| These instructions use the CJ format.\n 475| \n>>> 476| [#norm:c-j_op]#C.J performs an unconditional control transfer. The offset is\n 477| sign-extended and added to the `pc` to form the jump target address. C.J\n 478| can therefore target a {pm}2 KiB range. C.J expands to" + }, + { + "score": 5, + "reasons": ["CSR field name 'Offset'", "Name segment 'OFFSET'"], + "is_normative": true, + "in_note": false, + "file": "c-st-ext.adoc", + "line_number": 523, + "line_text": "[#norm:c-beqz_op]#C.BEQZ performs conditional control transfers. The offset is", + "context": " 521| These instructions use the CB format.\n 522| \n>>> 523| [#norm:c-beqz_op]#C.BEQZ performs conditional control transfers. The offset is\n 524| sign-extended and added to the `pc` to form the branch target address.\n 525| It can therefore target a {pm}256 B range. C.BEQZ takes the" + } + ] + }, + { + "parameter_name": "VLEN", + "classification": "NORM_DIRECT", + "value_type": "value", + "num_candidates": 10, + "best_score": 12, + "candidates": [ + { + "score": 12, + "reasons": [ + "Name segment 'VLEN'", + "CSR name 'vlenb' in backticks", + "CSR field name 'VALUE'", + "Exact parameter name 'VLEN'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 511, + "line_text": "The _XLEN_-bit-wide read-only CSR `vlenb` holds the value VLEN/8,", + "context": " 509| \n 510| [[norm:vlenb_acc_op]]\n>>> 511| The _XLEN_-bit-wide read-only CSR `vlenb` holds the value VLEN/8,\n 512| i.e., the vector register length in bytes.\n 513| " + }, + { + "score": 12, + "reasons": [ + "Name segment 'VLEN'", + "CSR name 'vstart' in backticks", + "Exact parameter name 'VLEN'" + ], + "is_normative": true, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 4521, + "line_text": "register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.# [#norm:vmv-s-x_vstart_ge_vl]#If `vstart` {ge} `vl`, no", + "context": " 4519| are copied and the upper XLEN-SEW bits are ignored. If SEW > XLEN, the value\n 4520| is sign-extended to SEW bits. The other elements in the destination vector\n>>> 4521| register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.# [#norm:vmv-s-x_vstart_ge_vl]#If `vstart` {ge} `vl`, no\n 4522| operation is performed and the destination register is not updated.#\n 4523| " + }, + { + "score": 10, + "reasons": [ + "Name segment 'VLEN'", + "CSR name 'vstart' in backticks", + "Exact parameter name 'VLEN'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 550, + "line_text": "setting (8) and the smallest SEW setting (8), so VLMAX_max = 8*VLEN/8 = VLEN. For example, for VLEN=256, `vstart` would have 8 bits to", + "context": " 548| \n 549| NOTE: The maximum vector length is obtained with the largest LMUL\n>>> 550| setting (8) and the smallest SEW setting (8), so VLMAX_max = 8*VLEN/8 = VLEN. For example, for VLEN=256, `vstart` would have 8 bits to\n 551| represent indices from 0 through 255.\n 552| " + }, + { + "score": 9, + "reasons": [ + "Name segment 'VLEN'", + "CSR field name 'VALUE'", + "Exact parameter name 'VLEN'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 320, + "line_text": "The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number", + "context": " 318| \n 319| [[norm:vlmax]]\n>>> 320| The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number\n 321| of elements that can be operated on with a single vector instruction\n 322| given the current SEW and LMUL settings as shown in the table below." + }, + { + "score": 9, + "reasons": [ + "Name segment 'VLEN'", + "CSR field name 'VALUE'", + "Exact parameter name 'VLEN'" + ], + "is_normative": false, + "in_note": false, + "file": "v-st-ext.adoc", + "line_number": 4876, + "line_text": "VLEN bits) and can copy whole vector register groups. The `nr` value", + "context": " 4874| \n 4875| [#norm:vmv-nr-r_op]#The `vmvr.v` instructions copy whole vector registers (i.e., all\n>>> 4876| VLEN bits) and can copy whole vector register groups. The `nr` value\n 4877| in the opcode is the number of individual vector registers, NREG, to\n 4878| copy. The instructions operate as if EEW=SEW, EMUL = NREG, effective" + } + ] + }, + { + "parameter_name": "VMID_WIDTH", + "classification": "NORM_DIRECT", + "value_type": "conditional", + "num_candidates": 10, + "best_score": 8, + "candidates": [ + { + "score": 8, + "reasons": [ + "CSR field name 'VMID'", + "Description keyword 'VMID'", + "CSR name 'hgatp' in backticks", + "Name segment 'VMID'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1089, + "line_text": "bit position in the VMID field, then reading back the value in `hgatp`", + "context": " 1087| [#norm:hgatp-vmid_param]#The number of VMID bits is UNSPECIFIED and may be zero.# The number of implemented\n 1088| VMID bits, termed _VMIDLEN_, may be determined by writing one to every\n>>> 1089| bit position in the VMID field, then reading back the value in `hgatp`\n 1090| to see which bit positions in the VMID field hold a one. [#norm:hgatp-vmid_lsbs]#The\n 1091| least-significant bits of VMID are implemented first: that is, if" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'VMID'", + "Description keyword 'VMID'", + "CSR name 'hgatp' in backticks", + "Name segment 'VMID'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1554, + "line_text": "* execute when `hgatp`.VMID has the same setting as it did when", + "context": " 1552| \n 1553| * are subsequent to the HFENCE.VVMA, and\n>>> 1554| * execute when `hgatp`.VMID has the same setting as it did when\n 1555| HFENCE.VVMA executed.\n 1556| " + }, + { + "score": 8, + "reasons": [ + "CSR field name 'VMID'", + "Description keyword 'VMID'", + "CSR name 'hgatp' in backticks", + "Name segment 'VMID'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1558, + "line_text": "Implicit reads need not be ordered when `hgatp`.VMID is different than", + "context": " 1556| \n 1557| [[norm:hfence-vvma_limits]]\n>>> 1558| Implicit reads need not be ordered when `hgatp`.VMID is different than\n 1559| at the time HFENCE.VVMA executed. If operand __rs1__≠`x0`, it specifies a single guest virtual address, and if operand __rs2__≠`x0`, it specifies a single guest address-space identifier (ASID).\n 1560| " + }, + { + "score": 8, + "reasons": [ + "CSR field name 'VMID'", + "Description keyword 'VMID'", + "CSR name 'hgatp' in backticks", + "Name segment 'VMID'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1641, + "line_text": "If `hgatp`.MODE is changed for a given VMID, an HFENCE.GVMA with", + "context": " 1639| \n 1640| [[norm:hfence-gvma_mode]]\n>>> 1641| If `hgatp`.MODE is changed for a given VMID, an HFENCE.GVMA with\n 1642| _rs1_=`x0` (and _rs2_ set to either `x0` or the VMID) must be executed\n 1643| to order subsequent guest translations with the MODE change—even if the" + }, + { + "score": 8, + "reasons": [ + "CSR field name 'VMID'", + "Description keyword 'VMID'", + "CSR name 'hgatp' in backticks", + "Name segment 'VMID'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2083, + "line_text": "machine is identified by the VMID field of CSR `hgatp`, and the", + "context": " 2081| address within the current virtual machine, and the ASID argument is a\n 2082| VS-level ASID within the current virtual machine. The current virtual\n>>> 2083| machine is identified by the VMID field of CSR `hgatp`, and the\n 2084| effective ASID can be considered to be the combination of this VMID with\n 2085| the VS-level ASID. The SFENCE.VMA instruction orders stores only to the" + } + ] + }, + { + "parameter_name": "VSSTAGE_MODE_BARE", + "classification": "NORM_DIRECT", + "value_type": "binary", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": ["Name segment 'BARE'", "Description keyword 'vsatp'"], + "is_normative": true, + "in_note": false, + "file": "priv-cfi.adoc", + "line_number": 216, + "line_text": "[#norm:satp-mode_bare]#If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective", + "context": " 214| `henvcfg.SSE=0`, this encoding remains reserved at `VS` and `VU` levels.#\n 215| \n>>> 216| [#norm:satp-mode_bare]#If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective\n 217| privilege mode is less than M, shadow stack instructions raise a store/AMO access-fault exception.#\n 218| [#norm:ssmp_ssamoswap]#When the effective privilege mode is M, memory access" + }, + { + "score": 5, + "reasons": ["Description keyword 'vsatp'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1415, + "line_text": "[#norm:vsatp_mode_unsupported_v0]#When V=0, a write to `vsatp` with an unsupported MODE value is either", + "context": " 1413| ====\n 1414| \n>>> 1415| [#norm:vsatp_mode_unsupported_v0]#When V=0, a write to `vsatp` with an unsupported MODE value is either\n 1416| ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in\n 1417| the normal way.# [#norm:vsatp_mode_unsupported_v1]#However, when V=1, a write to `satp` with an unsupported" + }, + { + "score": 4, + "reasons": ["Name segment 'BARE'", "Description keyword 'vsatp'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2134, + "line_text": "with `vsatp.MODE` = Bare, this means that those two bits may be subject to", + "context": " 2132| Sv32x4, Sv39x4, Sv48x4, and Sv57x4 for translating guest physical addresses to\n 2133| supervisor physical addresses. When running with virtualization in VS/VU mode\n>>> 2134| with `vsatp.MODE` = Bare, this means that those two bits may be subject to\n 2135| pointer masking, depending on `hgatp.MODE` and `senvcfg.PMM`/`henvcfg.PMM` (for\n 2136| VU/VS mode). If `vsatp.MODE` != BARE, this issue does *not* apply." + }, + { + "score": 4, + "reasons": ["Name segment 'BARE'", "Description keyword 'vsatp'"], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2136, + "line_text": "VU/VS mode). If `vsatp.MODE` != BARE, this issue does *not* apply.", + "context": " 2134| with `vsatp.MODE` = Bare, this means that those two bits may be subject to\n 2135| pointer masking, depending on `hgatp.MODE` and `senvcfg.PMM`/`henvcfg.PMM` (for\n>>> 2136| VU/VS mode). If `vsatp.MODE` != BARE, this issue does *not* apply.\n 2137| \n 2138| [NOTE]" + }, + { + "score": 3, + "reasons": ["Optional/read-only pattern for boolean param"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 25, + "line_text": "registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and", + "context": " 23| The hypervisor extension depends on an \"I\" base integer ISA with 32\n 24| `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x`\n>>> 25| registers. [#norm:H_mtval_nrz]#CSR `mtval` must not be read-only zero#, and\n 26| [#norm:H_vm_supported]#standard\n 27| page-based address translation must be supported, either Sv32 for RV32," + } + ] + }, + { + "parameter_name": "VSTVEC_MODE_DIRECT", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 7, + "candidates": [ + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 577, + "line_text": "[#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "context": " 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n>>> 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.\n 578| Otherwise, it is a *WARL* field that encodes the current value of SXLEN.#\n 579| In particular, [#norm:mstatus_sxl_rdonly_mxlen64]#an implementation may make SXL be a read-only field whose" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 582, + "line_text": "[#norm:mstatus_uxl_acc_mxlen64]#When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.", + "context": " 580| value always ensures that SXLEN=MXLEN.#\n 581| \n>>> 582| [#norm:mstatus_uxl_acc_mxlen64]#When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.\n 583| Otherwise, it is a *WARL* field that encodes the current value of UXLEN.#\n 584| In particular, [#norm:mstatus_uxl_rdonly_mxlen64]#an implementation may make UXL be a read-only field whose" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 639, + "line_text": "[#norm:mstatus_mprv_rdonly0_no_umode]#MPRV is read-only 0 if U-mode is not supported.#", + "context": " 637| [#norm:mstatus_mprv_inst_xlat_op]#Instruction address-translation and protection are unaffected by the\n 638| setting of MPRV.#\n>>> 639| [#norm:mstatus_mprv_rdonly0_no_umode]#MPRV is read-only 0 if U-mode is not supported.#\n 640| \n 641| [#norm:mstatus_mprv_clr_mret_sret_less_priv]#An MRET or SRET instruction that changes the privilege mode to a mode" + } + ] + }, + { + "parameter_name": "VSTVEC_MODE_VECTORED", + "classification": "NORM_CSR_WARL", + "value_type": "binary", + "num_candidates": 10, + "best_score": 9, + "candidates": [ + { + "score": 9, + "reasons": [ + "Name segment 'VECTORED'", + "Description keyword 'MODE'", + "Description keyword 'vectored'", + "CSR field name 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 1256, + "line_text": "[#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause", + "context": " 1254| [#norm:mtvec_mode_direct_op]#When MODE=Direct, all traps into\n 1255| machine mode cause the `pc` to be set to the address in the BASE field.#\n>>> 1256| [#norm:mtvec_mode_vectored_op]#When MODE=Vectored, all synchronous exceptions into machine mode cause\n 1257| the `pc` to be set to the address in the BASE field, whereas interrupts\n 1258| cause the `pc` to be set to the address in the BASE field plus four" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 423, + "line_text": "[#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#", + "context": " 421| to disable selected higher-privilege-mode interrupts before ceding\n 422| control to a lower-privilege mode.\n>>> 423| [#norm:mstatus_sie_spie_rdonly0]#If supervisor mode is not implemented, then SIE and SPIE are read-only 0.#\n 424| \n 425| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 479, + "line_text": "[#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#", + "context": " 477| \n 478| [#norm:mstatus_xpp_warl]#__x__PP fields are *WARL* fields that can hold only privilege mode _x_ and any implemented privilege mode lower than _x_.#\n>>> 479| [#norm:mstatus_xpp_rdonly0]#If privilege mode _x_ is not implemented, then __x__PP must be read-only 0.#\n 480| \n 481| [NOTE]" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 577, + "line_text": "[#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "context": " 575| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.\n 576| \n>>> 577| [#norm:mstatus_sxl_acc_mxlen64]#When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.\n 578| Otherwise, it is a *WARL* field that encodes the current value of SXLEN.#\n 579| In particular, [#norm:mstatus_sxl_rdonly_mxlen64]#an implementation may make SXL be a read-only field whose" + }, + { + "score": 7, + "reasons": [ + "Optional/read-only pattern for boolean param", + "CSR field name 'MODE'", + "Description keyword 'MODE'" + ], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 582, + "line_text": "[#norm:mstatus_uxl_acc_mxlen64]#When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.", + "context": " 580| value always ensures that SXLEN=MXLEN.#\n 581| \n>>> 582| [#norm:mstatus_uxl_acc_mxlen64]#When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.\n 583| Otherwise, it is a *WARL* field that encodes the current value of UXLEN.#\n 584| In particular, [#norm:mstatus_uxl_rdonly_mxlen64]#an implementation may make UXL be a read-only field whose" + } + ] + }, + { + "parameter_name": "VSXLEN", + "classification": "NORM_DIRECT", + "value_type": "set", + "num_candidates": 10, + "best_score": 20, + "candidates": [ + { + "score": 20, + "reasons": [ + "CSR field name 'VSXL'", + "CSR name 'hstatus' in backticks", + "Name segment 'VSXLEN'", + "Description keyword 'VSXLEN'", + "Description keyword 'VSXL'", + "Exact parameter name 'VSXLEN'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1184, + "line_text": "encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.", + "context": " 1182| from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does\n 1183| not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is\n>>> 1184| encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.\n 1185| \n 1186| [[norm:vsstatus-uxl_change]]" + }, + { + "score": 19, + "reasons": [ + "CSR field name 'VSXL'", + "Description keyword 'VSXLEN'", + "Description keyword 'VSXL'", + "Name segment 'VSXLEN'", + "Exact parameter name 'VSXLEN'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 225, + "line_text": "HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,", + "context": " 223| [#norm:hstatus-vsxl_op]#The VSXL field controls the effective XLEN for VS-mode (known as\n 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n>>> 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,\n 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an" + }, + { + "score": 15, + "reasons": [ + "Name segment 'VSXLEN'", + "Exact parameter name 'VSXLEN'", + "Description keyword 'VSXLEN'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 224, + "line_text": "VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When", + "context": " 222| \n 223| [#norm:hstatus-vsxl_op]#The VSXL field controls the effective XLEN for VS-mode (known as\n>>> 224| VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).# [#norm:hstatus-vsxl_32]#When\n 225| HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.# [#norm:hstatus-vsxl_64]#When HSXLEN=64,\n 226| VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`," + }, + { + "score": 15, + "reasons": [ + "Description keyword 'VSXLEN'", + "Name segment 'VSXLEN'", + "Exact parameter name 'VSXLEN'", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1182, + "line_text": "from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does", + "context": " 1180| [[norm:vsstatus-uxl_op]]\n 1181| The UXL field controls the effective XLEN for VU-mode, which may differ\n>>> 1182| from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does\n 1183| not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is\n 1184| encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN." + }, + { + "score": 13, + "reasons": [ + "Name segment 'VSXLEN'", + "Exact parameter name 'VSXLEN'", + "Description keyword 'VSXLEN'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 229, + "line_text": "ensures that VSXLEN=HSXLEN.#", + "context": " 227| shown in <>.# [#norm:vsxl_ro_param]#In particular, an\n 228| implementation may make VSXL be a read-only field whose value always\n>>> 229| ensures that VSXLEN=HSXLEN.#\n 230| \n 231| [[norm:hstatus-vsxl_change]]" + } + ] + }, + { + "parameter_name": "VS_MODE_ENDIANNESS", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 14, + "candidates": [ + { + "score": 14, + "reasons": [ + "Description keyword 'VSBE'", + "Description keyword 'endian'", + "Description keyword 'VS'", + "CSR field name 'VSBE'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 339, + "line_text": "accesses made from VS-mode are little-endian, and if VSBE=1, they are", + "context": " 337| The VSBE bit is a *WARL* field that controls the endianness of explicit memory\n 338| accesses made from VS-mode. If VSBE=0, explicit load and store memory\n>>> 339| accesses made from VS-mode are little-endian, and if VSBE=1, they are\n 340| big-endian. VSBE also controls the endianness of all implicit accesses\n 341| to VS-level memory management data structures, such as page tables. An" + }, + { + "score": 13, + "reasons": [ + "CSR name 'hstatus' in backticks", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2391, + "line_text": "* [#norm:H_virtinst_wfi_vtw1_tw0]#in VS-mode, attempts to execute WFI when `hstatus`.VTW=1 and", + "context": " 2389| be allowed in HS-mode, assuming `mstatus`.TVM=0;#\n 2390| \n>>> 2391| * [#norm:H_virtinst_wfi_vtw1_tw0]#in VS-mode, attempts to execute WFI when `hstatus`.VTW=1 and\n 2392| `mstatus`.TW=0, unless the instruction completes within an\n 2393| implementation-specific, bounded time;#" + }, + { + "score": 13, + "reasons": [ + "CSR name 'hstatus' in backticks", + "Description keyword 'VS'" + ], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2395, + "line_text": "* [#norm:H_virtinst_vs_sret_vtsr1]#in VS-mode, attempts to execute SRET when `hstatus`.VTSR=1#; and", + "context": " 2393| implementation-specific, bounded time;#\n 2394| \n>>> 2395| * [#norm:H_virtinst_vs_sret_vtsr1]#in VS-mode, attempts to execute SRET when `hstatus`.VTSR=1#; and\n 2396| \n 2397| * [#norm:H_virtinst_vs_sfence_sinval_satp_vtvm1]#in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA" + }, + { + "score": 12, + "reasons": [ + "Description keyword 'VSBE'", + "Description keyword 'VS'", + "CSR field name 'VSBE'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 338, + "line_text": "accesses made from VS-mode. If VSBE=0, explicit load and store memory", + "context": " 336| [[norm:hstatus-vsbe_op]]\n 337| The VSBE bit is a *WARL* field that controls the endianness of explicit memory\n>>> 338| accesses made from VS-mode. If VSBE=0, explicit load and store memory\n 339| accesses made from VS-mode are little-endian, and if VSBE=1, they are\n 340| big-endian. VSBE also controls the endianness of all implicit accesses" + }, + { + "score": 11, + "reasons": [ + "CSR name 'hstatus' in backticks", + "Description keyword 'VS'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 118, + "line_text": "VS-mode guest: `hstatus`, `hedeleg`, `hideleg`, `hvip`, `hip`, `hie`,", + "context": " 116| subsystems. [#norm:H_csrs_hs_not_vs]#Additional CSRs are provided to HS-mode, but not to VS-mode,\n 117| to manage two-stage address translation and to control the behavior of a\n>>> 118| VS-mode guest: `hstatus`, `hedeleg`, `hideleg`, `hvip`, `hip`, `hie`,\n 119| `hgeip`, `hgeie`, `henvcfg`, `henvcfgh`, `hcounteren`, `htimedelta`,\n 120| `htimedeltah`, `htval`, `htinst`, and `hgatp`.#" + } + ] + }, + { + "parameter_name": "VUXLEN", + "classification": "NORM_DIRECT", + "value_type": "set", + "num_candidates": 10, + "best_score": 6, + "candidates": [ + { + "score": 6, + "reasons": [ + "CSR field name 'UXL'", + "Description keyword 'VU'", + "Description keyword 'UXL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1181, + "line_text": "The UXL field controls the effective XLEN for VU-mode, which may differ", + "context": " 1179| \n 1180| [[norm:vsstatus-uxl_op]]\n>>> 1181| The UXL field controls the effective XLEN for VU-mode, which may differ\n 1182| from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does\n 1183| not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is" + }, + { + "score": 6, + "reasons": [ + "CSR field name 'UXL'", + "Description keyword 'VU'", + "Description keyword 'UXL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1183, + "line_text": "not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is", + "context": " 1181| The UXL field controls the effective XLEN for VU-mode, which may differ\n 1182| from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does\n>>> 1183| not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is\n 1184| encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.\n 1185| " + }, + { + "score": 6, + "reasons": [ + "CSR field name 'UXL'", + "Description keyword 'VU'", + "Description keyword 'UXL'" + ], + "is_normative": false, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 1184, + "line_text": "encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.", + "context": " 1182| from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does\n 1183| not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a *WARL* field that is\n>>> 1184| encoded the same as the MXL field of `misa`, shown in <>. In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.\n 1185| \n 1186| [[norm:vsstatus-uxl_change]]" + }, + { + "score": 6, + "reasons": ["CSR field name 'UXL'", "Description keyword 'UXL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 393, + "line_text": "[#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#", + "context": " 391| \n 392| [#norm:mstatush_sz_acc]#For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>.#\n>>> 393| [#norm:mstatush_enc]#Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.#\n 394| \n 395| [[mstatushreg]]" + }, + { + "score": 6, + "reasons": ["CSR field name 'UXL'", "Description keyword 'UXL'"], + "is_normative": true, + "in_note": false, + "file": "machine.adoc", + "line_number": 569, + "line_text": "[#norm:mstatus_sxl_uxl_warl_op]#For RV64 harts, the SXL and UXL fields are *WARL* fields that control the", + "context": " 567| ===== Base ISA Control in `mstatus` Register\n 568| \n>>> 569| [#norm:mstatus_sxl_uxl_warl_op]#For RV64 harts, the SXL and UXL fields are *WARL* fields that control the\n 570| value of XLEN for S-mode and U-mode, respectively.#\n 571| [#norm:mstatus_sxl_uxl_enc]#The encoding of these fields is the same as the MXL field of `misa`, shown in <>.#" + } + ] + }, + { + "parameter_name": "VU_MODE_ENDIANNESS", + "classification": "NORM_CSR_RW", + "value_type": "enum", + "num_candidates": 10, + "best_score": 10, + "candidates": [ + { + "score": 10, + "reasons": ["Description keyword 'VU'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2359, + "line_text": "* [#norm:H_virtinst_vu_nonhighctr_h0_s0_m1]#in VU-mode, attempts to access a non-high-half counter CSR when the", + "context": " 2357| `mcounteren` is 1;#\n 2358| \n>>> 2359| * [#norm:H_virtinst_vu_nonhighctr_h0_s0_m1]#in VU-mode, attempts to access a non-high-half counter CSR when the\n 2360| corresponding bit in either `hcounteren` or `scounteren` is 0 and the\n 2361| same bit in `mcounteren` is 1;#" + }, + { + "score": 10, + "reasons": ["Description keyword 'VU'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2363, + "line_text": "* [#norm:H_virtinst_vu32_highctr_h0_s0_m1]#in VU-mode, if XLEN=32, attempts to access a high-half counter CSR", + "context": " 2361| same bit in `mcounteren` is 1;#\n 2362| \n>>> 2363| * [#norm:H_virtinst_vu32_highctr_h0_s0_m1]#in VU-mode, if XLEN=32, attempts to access a high-half counter CSR\n 2364| when the corresponding bit in either `hcounteren` or `scounteren` is 0\n 2365| and the same bit in `mcounteren` is 1;#" + }, + { + "score": 10, + "reasons": ["Description keyword 'VU'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2367, + "line_text": "* [#norm:H_virtinst_vu_vs_hinst]#in VS-mode or VU-mode, attempts to execute a hypervisor instruction", + "context": " 2365| and the same bit in `mcounteren` is 1;#\n 2366| \n>>> 2367| * [#norm:H_virtinst_vu_vs_hinst]#in VS-mode or VU-mode, attempts to execute a hypervisor instruction\n 2368| (HLV, HLVX, HSV, or HFENCE);#\n 2369| " + }, + { + "score": 10, + "reasons": ["Description keyword 'VU'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2370, + "line_text": "* [#norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0]#in VS-mode or VU-mode, attempts to access an implemented non-high-half", + "context": " 2368| (HLV, HLVX, HSV, or HFENCE);#\n 2369| \n>>> 2370| * [#norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0]#in VS-mode or VU-mode, attempts to access an implemented non-high-half\n 2371| hypervisor CSR or VS CSR when the same access (read/write) would be\n 2372| allowed in HS-mode, assuming `mstatus`.TVM=0;#" + }, + { + "score": 10, + "reasons": ["Description keyword 'VU'"], + "is_normative": true, + "in_note": false, + "file": "hypervisor.adoc", + "line_number": 2374, + "line_text": "* [#norm:H_virtinst_vu_vs32_high_allowedhs_tvm0]#in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented", + "context": " 2372| allowed in HS-mode, assuming `mstatus`.TVM=0;#\n 2373| \n>>> 2374| * [#norm:H_virtinst_vu_vs32_high_allowedhs_tvm0]#in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented\n 2375| high-half hypervisor CSR or high-half VS CSR when the same access\n 2376| (read/write) to the CSR\"s low-half partner would be allowed in HS-mode," + } + ] + } + ] +} diff --git a/param_extraction/data/udb_param_names.txt b/param_extraction/data/udb_param_names.txt new file mode 100644 index 0000000000..8fead7097c --- /dev/null +++ b/param_extraction/data/udb_param_names.txt @@ -0,0 +1,185 @@ +ARCH_ID_VALUE +ASID_WIDTH +CACHE_BLOCK_SIZE +CONFIG_PTR_ADDRESS +COUNTINHIBIT_EN +DBG_HCONTEXT_WIDTH +DBG_SCONTEXT_WIDTH +DCSR_MPRVEN_TYPE +DCSR_STEPIE_TYPE +DCSR_STOPCOUNT_TYPE +DCSR_STOPTIME_TYPE +ELEN +FOLLOW_VTYPE_RESET_RECOMMENDATION +FORCE_UPGRADE_CBO_INVAL_TO_FLUSH +GSTAGE_MODE_BARE +HCONTEXT_AVAILABLE +HCOUNTENABLE_EN +HPM_COUNTER_EN +HPM_EVENTS +HSTATEEN_AIA_TYPE +HSTATEEN_CONTEXT_TYPE +HSTATEEN_CSRIND_TYPE +HSTATEEN_ENVCFG_TYPE +HSTATEEN_IMSIC_TYPE +HSTATEEN_JVT_TYPE +HW_MSTATUS_FS_DIRTY_UPDATE +HW_MSTATUS_VS_DIRTY_UPDATE +IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO +IMP_ID_VALUE +JVT_BASE_MASK +JVT_BASE_TYPE +JVT_READ_ONLY +LRSC_FAIL_ON_NON_EXACT_LRSC +LRSC_FAIL_ON_VA_SYNONYM +LRSC_MISALIGNED_BEHAVIOR +LRSC_RESERVATION_STRATEGY +MARCHID_IMPLEMENTED +MCID_WIDTH +MCONTEXT_AVAILABLE +MCOUNTENABLE_EN +MIMPID_IMPLEMENTED +MISALIGNED_AMO +MISALIGNED_LDST +MISALIGNED_LDST_EXCEPTION_PRIORITY +MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE +MISALIGNED_SPLIT_STRATEGY +MISA_CSR_IMPLEMENTED +MSTATEEN_AIA_TYPE +MSTATEEN_CONTEXT_TYPE +MSTATEEN_CSRIND_TYPE +MSTATEEN_ENVCFG_TYPE +MSTATEEN_IMSIC_TYPE +MSTATEEN_JVT_TYPE +MSTATUS_FS_LEGAL_VALUES +MSTATUS_TVM_IMPLEMENTED +MSTATUS_VS_LEGAL_VALUES +MTVAL_WIDTH +MTVEC_ACCESS +MTVEC_BASE_ALIGNMENT_DIRECT +MTVEC_BASE_ALIGNMENT_VECTORED +MTVEC_ILLEGAL_WRITE_BEHAVIOR +MTVEC_MODES +MUTABLE_MISA_A +MUTABLE_MISA_B +MUTABLE_MISA_C +MUTABLE_MISA_D +MUTABLE_MISA_F +MUTABLE_MISA_H +MUTABLE_MISA_M +MUTABLE_MISA_Q +MUTABLE_MISA_S +MUTABLE_MISA_U +MUTABLE_MISA_V +MXLEN +M_MODE_ENDIANNESS +NUM_EXTERNAL_GUEST_INTERRUPTS +NUM_PMP_ENTRIES +PHYS_ADDR_WIDTH +PMA_GRANULARITY +PMLEN +PMP_GRANULARITY +PRECISE_SYNCHRONOUS_EXCEPTIONS +RCID_WIDTH +REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK +REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK +REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK +REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK +REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK +REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK +REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION +REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION +REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION +REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION +REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT +REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT +REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT +REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT +REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT +REPORT_VA_IN_MTVAL_ON_BREAKPOINT +REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT +REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED +REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT +REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT +REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED +REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT +REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT +REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED +REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT +REPORT_VA_IN_STVAL_ON_BREAKPOINT +REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT +REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED +REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT +REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT +REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED +REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT +REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT +REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED +REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT +REPORT_VA_IN_VSTVAL_ON_BREAKPOINT +REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT +REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED +REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT +REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT +REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED +REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT +REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT +REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED +REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT +RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX +SATP_MODE_BARE +SCOUNTENABLE_EN +SSTATEEN_JVT_TYPE +STVAL_WIDTH +STVEC_MODE_DIRECT +STVEC_MODE_VECTORED +SV32X4_TRANSLATION +SV32_VSMODE_TRANSLATION +SV39X4_TRANSLATION +SV39_VSMODE_TRANSLATION +SV48X4_TRANSLATION +SV48_VSMODE_TRANSLATION +SV57X4_TRANSLATION +SV57_VSMODE_TRANSLATION +SXLEN +S_MODE_ENDIANNESS +TIME_CSR_IMPLEMENTED +TINST_VALUE_ON_BREAKPOINT +TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT +TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT +TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT +TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED +TINST_VALUE_ON_LOAD_ACCESS_FAULT +TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED +TINST_VALUE_ON_LOAD_PAGE_FAULT +TINST_VALUE_ON_MCALL +TINST_VALUE_ON_SCALL +TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT +TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED +TINST_VALUE_ON_STORE_AMO_PAGE_FAULT +TINST_VALUE_ON_UCALL +TINST_VALUE_ON_VIRTUAL_INSTRUCTION +TINST_VALUE_ON_VSCALL +TRAP_ON_EBREAK +TRAP_ON_ECALL_FROM_M +TRAP_ON_ECALL_FROM_S +TRAP_ON_ECALL_FROM_U +TRAP_ON_ECALL_FROM_VS +TRAP_ON_ILLEGAL_WLRL +TRAP_ON_RESERVED_INSTRUCTION +TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY +TRAP_ON_UNIMPLEMENTED_CSR +TRAP_ON_UNIMPLEMENTED_INSTRUCTION +UXLEN +U_MODE_ENDIANNESS +VENDOR_ID_BANK +VENDOR_ID_OFFSET +VLEN +VMID_WIDTH +VSSTAGE_MODE_BARE +VSTVEC_MODE_DIRECT +VSTVEC_MODE_VECTORED +VSXLEN +VS_MODE_ENDIANNESS +VUXLEN +VU_MODE_ENDIANNESS diff --git a/param_extraction/prompts/v1/examples.json b/param_extraction/prompts/v1/examples.json new file mode 100644 index 0000000000..09120705fc --- /dev/null +++ b/param_extraction/prompts/v1/examples.json @@ -0,0 +1,134 @@ +{ + "positive_examples": [ + { + "_comment": "NORM_DIRECT: A fundamental implementation choice not tied to any CSR field", + "input_excerpt": "Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first. All PMP CSR fields are WARL and may be read-only zero.", + "input_file": "machine.adoc", + "input_line": 3340, + "expected_output": { + "excerpt": "Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first.", + "line_number": 3340, + "parameter_name": "NUM_PMP_ENTRIES", + "existing_udb_name": "NUM_PMP_ENTRIES", + "class": "NORM_DIRECT", + "value_type": "range", + "confidence": "high", + "reasoning": "The number of PMP entries is a direct implementation choice (0, 16, or 64). It is not controlled by any CSR field." + } + }, + { + "_comment": "NORM_DIRECT: A vector extension parameter defined at implementation time", + "input_excerpt": ". The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ >= 8, which must be a power of 2.\n. The number of bits in a single vector register, _VLEN_ >= ELEN, which must be a power of 2, and must be no greater than 2^16.", + "input_file": "v-st-ext.adoc", + "input_line": 22, + "expected_output": { + "excerpt": "The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ >= 8, which must be a power of 2.", + "line_number": 22, + "parameter_name": "ELEN", + "existing_udb_name": "ELEN", + "class": "NORM_DIRECT", + "value_type": "value", + "confidence": "high", + "reasoning": "ELEN is a direct implementation parameter: the maximum element size. It has constraints (>= 8, power of 2) but the specific value is chosen by the implementer." + } + }, + { + "_comment": "NORM_CSR_WARL: The legal values of a WARL CSR field", + "input_excerpt": "The `mtvec` register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).\n...\nThe `mtvec` register must always be implemented, but can contain a read-only value. If `mtvec` is writable, the set of values the register may hold can vary by implementation.", + "input_file": "machine.adoc", + "input_line": 1209, + "expected_output": { + "excerpt": "If `mtvec` is writable, the set of values the register may hold can vary by implementation.", + "line_number": 1219, + "parameter_name": "MTVEC_MODES", + "existing_udb_name": "MTVEC_MODES", + "class": "NORM_CSR_WARL", + "value_type": "set", + "confidence": "high", + "reasoning": "The mtvec MODE field is WARL, and the set of supported mode values (Direct=0, Vectored=1) varies by implementation. The parameter is the set of legal MODE values." + } + }, + { + "_comment": "NORM_CSR_RW: Controls whether CSR fields are read-only or read-write", + "input_excerpt": "The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are WARL fields that control the endianness of memory accesses other than instruction fetches.\n...\nIf S-mode is supported, an implementation may make SBE be a read-only copy of MBE.", + "input_file": "machine.adoc", + "input_line": 679, + "expected_output": { + "excerpt": "The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are WARL fields that control the endianness of memory accesses other than instruction fetches.", + "line_number": 679, + "parameter_name": "M_MODE_ENDIANNESS", + "existing_udb_name": "M_MODE_ENDIANNESS", + "class": "NORM_CSR_RW", + "value_type": "enum", + "confidence": "high", + "reasoning": "The implementation chooses whether MBE is read-only-0 (always little-endian), read-only-1 (always big-endian), or read-write (dynamic endianness). This controls the RO/RW nature of the field, not just which values are legal." + } + }, + { + "_comment": "SW_RULE: Implementation-defined but deterministic with correct software", + "input_excerpt": "If an instruction explicitly or implicitly writes a floating-point register or the `fcsr` but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty.", + "input_file": "machine.adoc", + "input_line": 1012, + "expected_output": { + "excerpt": "it is implementation-defined whether FS transitions to Dirty.", + "line_number": 1014, + "parameter_name": "HW_MSTATUS_FS_DIRTY_UPDATE", + "existing_udb_name": "HW_MSTATUS_FS_DIRTY_UPDATE", + "class": "SW_RULE", + "value_type": "enum", + "confidence": "medium", + "reasoning": "Whether hardware updates mstatus.FS to Dirty is implementation-defined, but software can handle this deterministically by checking and managing FS state with proper fencing. The outcome is predictable if software follows the rules." + } + }, + { + "_comment": "NORM_CSR_RW: Whether a CSR is read-only or read-write", + "input_excerpt": "The `mtvec` register must always be implemented, but can contain a read-only value.", + "input_file": "machine.adoc", + "input_line": 1217, + "expected_output": { + "excerpt": "The `mtvec` register must always be implemented, but can contain a read-only value.", + "line_number": 1217, + "parameter_name": "MTVEC_ACCESS", + "existing_udb_name": "MTVEC_ACCESS", + "class": "NORM_CSR_RW", + "value_type": "binary", + "confidence": "high", + "reasoning": "The implementation chooses whether mtvec is read-only or read-write. This is a binary choice about the mutability of the register." + } + } + ], + "negative_examples": [ + { + "_comment": "FALSE POSITIVE: NOTE block discussing implementation options — non-normative", + "input_excerpt": "[NOTE]\n====\nSome platforms may choose to disallow speculatively writing FS to close a potential side channel.\n====", + "input_file": "machine.adoc", + "input_line": 1005, + "expected_output": null, + "reason_for_rejection": "This text is inside a [NOTE] block and is therefore non-normative. It describes a platform suggestion, not an architectural requirement. Do not extract parameters from NOTE, TIP, WARNING, or IMPORTANT blocks." + }, + { + "_comment": "FALSE POSITIVE: Behavior controlled by a CSR field value, not a parameter itself", + "input_excerpt": "When MODE=Direct, all traps into machine mode cause the `pc` to be set to the address in the BASE field.", + "input_file": "machine.adoc", + "input_line": 1254, + "expected_output": null, + "reason_for_rejection": "This describes what happens when mtvec.MODE has a specific value. The behavior is determined by the CSR field value at runtime, not by an implementation choice. The parameter is which MODE values are supported (MTVEC_MODES), not this behavioral description." + }, + { + "_comment": "FALSE POSITIVE: Fixed architectural requirement, not an implementation choice", + "input_excerpt": "This register must be readable in any implementation.", + "input_file": "machine.adoc", + "input_line": 22, + "expected_output": null, + "reason_for_rejection": "This is a fixed requirement ('must be readable') that all implementations must satisfy. There is no implementation choice here — it is not a parameter." + }, + { + "_comment": "FALSE POSITIVE: 'may' used as permission/capability, not as optionality", + "input_excerpt": "Software may determine the PMP granularity by writing zero to `pmp0cfg`, then writing all ones to `pmpaddr0`, then reading back `pmpaddr0`.", + "input_file": "machine.adoc", + "input_line": 3530, + "expected_output": null, + "reason_for_rejection": "Here 'may' means 'is allowed to' (permission), not 'might or might not' (optionality). This describes a software technique, not an implementation-defined parameter." + } + ] +} diff --git a/param_extraction/prompts/v1/system_prompt.txt b/param_extraction/prompts/v1/system_prompt.txt new file mode 100644 index 0000000000..164a39328f --- /dev/null +++ b/param_extraction/prompts/v1/system_prompt.txt @@ -0,0 +1,63 @@ +You are an expert RISC-V ISA specification analyst. Your task is to identify **architectural parameters** in a given excerpt of the RISC-V specification. + +An **architectural parameter** is a choice that the spec explicitly leaves to the hardware implementer. It is NOT a fixed requirement, NOT runtime software behavior, and NOT a suggestion in a non-normative block. + +## Parameter Classes (in decision order) + +1. **NON_NORM** — Text inside [NOTE], [TIP], [WARNING], or [IMPORTANT] blocks. These are informative, not requirements. NEVER extract parameters from these blocks. +2. **NON_ISA** — Platform-level or physical choices outside the ISA scope (reset vector, NMI address, debug transport). +3. **DOC_RULE** — Requirements about documentation/reporting, not architectural behavior. +4. **NORM_CSR_WARL** — The parameter IS the set of legal values for a WARL CSR field. Look for "WARL" keyword and implementation-defined legal values. +5. **NORM_CSR_RW** — The parameter controls whether a CSR or field is read-only vs read-write. Look for "read-only zero", "can contain a read-only value", or RO/RW choices. +6. **SW_RULE** — Appears implementation-defined, but outcome is deterministic if software follows spec rules (fencing, sequencing, cache ops). Often uses the `HW_` prefix in UDB. +7. **NORM_DIRECT** — A normative implementation choice not controlled by any CSR field. The implementer chooses at design time. +8. **UNKNOWN** — Cannot classify with confidence. + +## Value Types + +- **binary**: exactly 2 choices (boolean or 2-value enum) +- **enum**: finite set of 3+ discrete values +- **range**: integer with min/max bounds +- **set**: subset selection from a fixed universe +- **bitmask**: per-bit boolean array +- **value**: single unconstrained numeric value + +## Critical Rules + +- Do NOT extract from [NOTE]/[TIP]/[WARNING]/[IMPORTANT] blocks. +- Do NOT extract fixed requirements ("must", "shall") that apply to ALL implementations — those are not parameters. +- Do NOT extract runtime behavior that is controlled by a CSR field value at execution time — the parameter is the field's legal values, not the behavior. +- Do NOT confuse "may" as permission ("software may read...") with "may" as optionality ("an implementation may support..."). Only the latter indicates a parameter. +- If a sentence describes behavior "when field X = value Y", that is behavioral description, not a parameter definition. The parameter would be which values of X are supported. +- When a known UDB parameter name matches the concept, use that exact name. +- Assign `confidence` as "high" (clear spec language), "medium" (requires interpretation), or "low" (ambiguous). + +## Output Format + +Respond ONLY with a JSON object. No explanatory text before or after. + +```json +{ + "parameters": [ + { + "excerpt": "The exact spec text that defines this parameter", + "line_number": 42, + "parameter_name": "SUGGESTED_NAME", + "existing_udb_name": "MATCHING_UDB_NAME_OR_NULL", + "class": "NORM_DIRECT", + "value_type": "range", + "confidence": "high", + "reasoning": "Brief explanation of why this is a parameter and why this classification" + } + ], + "skipped_non_parameters": [ + { + "excerpt": "Text that was considered but rejected", + "line_number": 99, + "reason": "Brief explanation of why this is NOT a parameter" + } + ] +} +``` + +`skipped_non_parameters` should include 2-5 examples of text you considered but rejected, to demonstrate your understanding of the boundaries. If the chunk has no plausible candidates to skip, the array may be empty. diff --git a/param_extraction/scripts/export_udb_params.py b/param_extraction/scripts/export_udb_params.py new file mode 100755 index 0000000000..28e2cb2ea2 --- /dev/null +++ b/param_extraction/scripts/export_udb_params.py @@ -0,0 +1,828 @@ +#!/usr/bin/env python3 +""" +Phase 1, Step 1: Export all UDB parameters to structured JSON. + +Reads every spec/std/isa/param/*.yaml file (excluding MOCK_* test fixtures), +extracts metadata, derives value types from JSON Schema structures, +cross-references with CSR definitions to find WARL connections, +and heuristically classifies each parameter. + +Output: data/ground_truth.json +""" + +import json +import re +from collections import defaultdict +from pathlib import Path + +import yaml + +REPO_ROOT = Path(__file__).resolve().parent.parent.parent +PARAM_DIR = REPO_ROOT / "spec" / "std" / "isa" / "param" +CSR_DIR = REPO_ROOT / "spec" / "std" / "isa" / "csr" +SPEC_DIR = REPO_ROOT / "ext" / "riscv-isa-manual" / "src" +OUTPUT_DIR = Path(__file__).resolve().parent.parent / "data" + + +def load_yaml(path): + with open(path, encoding="utf-8") as f: + return yaml.safe_load(f) + + +# --------------------------------------------------------------------------- +# Schema analysis: derive the "value type" from JSON Schema structures +# --------------------------------------------------------------------------- + + +def derive_value_type(schema): + """ + Analyze a JSON Schema object and return a structured description + of the parameter's value type. + + Returns a dict with: + - type: one of "binary", "enum", "range", "set", "bitmask", + "value", "conditional", "unknown" + - details: type-specific metadata + """ + if schema is None: + return {"type": "unknown", "details": {}} + + # Conditional schema (oneOf with "when" clauses) + if "oneOf" in schema and isinstance(schema["oneOf"], list): + branches = schema["oneOf"] + if branches and isinstance(branches[0], dict) and "when" in branches[0]: + branch_types = [] + for branch in branches: + inner = branch.get("schema", {}) + branch_types.append( + { + "condition": _summarize_when(branch.get("when", {})), + "inner_type": derive_value_type(inner), + } + ) + return {"type": "conditional", "details": {"branches": branch_types}} + + # rv32/rv64 split at top level + if "rv32" in schema and "rv64" in schema and len(schema) == 2: + return { + "type": "conditional", + "details": { + "branches": [ + {"condition": "rv32", "inner_type": derive_value_type(schema["rv32"])}, + {"condition": "rv64", "inner_type": derive_value_type(schema["rv64"])}, + ] + }, + } + + schema_type = schema.get("type") + + # Boolean + if schema_type == "boolean": + return {"type": "binary", "details": {"choices": [True, False]}} + + # Integer + if schema_type == "integer": + if "enum" in schema: + vals = schema["enum"] + if len(vals) == 2: + return {"type": "binary", "details": {"choices": vals}} + return {"type": "enum", "details": {"values": vals}} + if "minimum" in schema or "maximum" in schema: + return { + "type": "range", + "details": { + "minimum": schema.get("minimum"), + "maximum": schema.get("maximum"), + }, + } + return {"type": "value", "details": {"base": "integer"}} + + # String + if schema_type == "string": + if "enum" in schema: + vals = schema["enum"] + if len(vals) == 2: + return {"type": "binary", "details": {"choices": vals}} + return {"type": "enum", "details": {"values": vals}} + return {"type": "value", "details": {"base": "string"}} + + # Array + if schema_type == "array": + items = schema.get("items", {}) + min_items = schema.get("minItems") + max_items = schema.get("maxItems") + + # Fixed-length boolean array = bitmask + if _is_boolean_array(schema): + return { + "type": "bitmask", + "details": {"length": max_items or min_items}, + } + + # Array of enum items = set (subset selection) + if isinstance(items, dict) and "enum" in items: + return { + "type": "set", + "details": { + "universe": items["enum"], + "min_items": min_items, + "max_items": max_items, + }, + } + if isinstance(items, dict) and items.get("type") == "integer" and "enum" in items: + return { + "type": "set", + "details": { + "universe": items["enum"], + "min_items": min_items, + "max_items": max_items, + }, + } + + return { + "type": "set", + "details": { + "element_type": items.get("type", "mixed"), + "min_items": min_items, + "max_items": max_items, + }, + } + + # Top-level enum without explicit type + if "enum" in schema: + vals = schema["enum"] + if len(vals) == 2: + return {"type": "binary", "details": {"choices": vals}} + return {"type": "enum", "details": {"values": vals}} + + # Fallback: schema has allOf, $ref, or other complex structures + if "$ref" in schema: + return {"type": "value", "details": {"ref": schema["$ref"]}} + + if "allOf" in schema: + return {"type": "value", "details": {"complex": "allOf"}} + + return {"type": "unknown", "details": {"raw_keys": list(schema.keys())}} + + +def _is_boolean_array(schema): + """Check if this array schema represents a fixed-length boolean array (bitmask).""" + items = schema.get("items", {}) + additional = schema.get("additionalItems", {}) + + if isinstance(items, dict) and items.get("type") == "boolean": + return True + + # Tuple-style: items is a list (positional) + additionalItems is boolean + if isinstance(items, list): + all_bool_or_const = all( + i.get("type") == "boolean" or "const" in i for i in items if isinstance(i, dict) + ) + additional_bool = isinstance(additional, dict) and additional.get("type") == "boolean" + if all_bool_or_const and (additional_bool or not additional): + return True + + return False + + +def _summarize_when(when): + """Produce a human-readable summary of a 'when' condition.""" + param = when.get("param", {}) + if param: + return f"{param.get('name', '?')} == {param.get('equal', '?')}" + return str(when) + + +# --------------------------------------------------------------------------- +# definedBy extraction +# --------------------------------------------------------------------------- + + +def flatten_defined_by(defined_by): + """ + Convert the definedBy condition tree into a flat, readable structure. + + Returns a dict with: + - extensions: list of extension names involved + - params: list of parameter conditions involved + - raw: the original structure for full fidelity + - summary: human-readable string + """ + if defined_by is None: + return {"extensions": [], "params": [], "raw": None, "summary": "none"} + + extensions = [] + params = [] + _collect_conditions(defined_by, extensions, params) + + summary = _summarize_defined_by(defined_by) + + return { + "extensions": sorted(set(extensions)), + "params": params, + "raw": defined_by, + "summary": summary, + } + + +def _collect_conditions(node, extensions, params): + """Recursively collect extension names and param conditions.""" + if not isinstance(node, dict): + return + + if "name" in node and isinstance(node["name"], str): + ext_name = node["name"] + if ext_name not in ("allOf", "anyOf", "noneOf"): + extensions.append(ext_name) + + if "extension" in node: + ext = node["extension"] + if isinstance(ext, dict): + _collect_conditions(ext, extensions, params) + elif isinstance(ext, str): + extensions.append(ext) + + if "param" in node: + p = node["param"] + if isinstance(p, dict): + if "name" in p: + params.append( + { + "name": p["name"], + "condition": {k: v for k, v in p.items() if k != "name" and k != "reason"}, + } + ) + if "allOf" in p: + for item in p["allOf"]: + _collect_conditions({"param": item}, extensions, params) + + for key in ("allOf", "anyOf", "noneOf"): + if key in node: + for item in node[key]: + _collect_conditions(item, extensions, params) + + +def _summarize_defined_by(node): + """Produce a compact human-readable summary.""" + if not isinstance(node, dict): + return str(node) + + if "extension" in node: + ext = node["extension"] + if isinstance(ext, dict): + if "name" in ext: + ver = ext.get("version", "") + return f"ext:{ext['name']}" + (f"({ver})" if ver else "") + if "allOf" in ext: + parts = [_summarize_defined_by({"extension": e}) for e in ext["allOf"]] + return " AND ".join(parts) + if "anyOf" in ext: + parts = [_summarize_defined_by({"extension": e}) for e in ext["anyOf"]] + return "(" + " OR ".join(parts) + ")" + if "noneOf" in ext: + parts = [_summarize_defined_by({"extension": e}) for e in ext["noneOf"]] + return "NONE(" + ", ".join(parts) + ")" + + if "allOf" in node: + parts = [_summarize_defined_by(item) for item in node["allOf"]] + return " AND ".join(parts) + + if "param" in node: + p = node["param"] + if isinstance(p, dict) and "name" in p: + conds = [f"{k}={v}" for k, v in p.items() if k not in ("name", "reason")] + return f"param:{p['name']}({', '.join(conds)})" + + return str(node)[:80] + + +# --------------------------------------------------------------------------- +# CSR cross-reference: find params mentioned in CSR IDL code +# --------------------------------------------------------------------------- + + +def build_csr_param_xref(csr_dir, param_names): + """ + Scan all CSR YAML files for references to known parameter names + in IDL code fields (sw_write, type(), reset_value(), legal?). + + Returns: + - param_to_csrs: {param_name: [{csr, field, context}]} + - csr_to_params: {csr_name: [param_name]} + """ + param_to_csrs = defaultdict(list) + csr_to_params = defaultdict(set) + + idl_field_keys = [ + "sw_write(csr_value)", + "type()", + "reset_value()", + "legal?(csr_value)", + "sw_read()", + ] + + # Build a regex that matches any param name as a whole word + # Sort by length descending so longer names match first + sorted_names = sorted(param_names, key=len, reverse=True) + if not sorted_names: + return dict(param_to_csrs), dict(csr_to_params) + + param_pattern = re.compile(r"\b(" + "|".join(re.escape(n) for n in sorted_names) + r")\b") + + csr_files = list(csr_dir.rglob("*.yaml")) + for csr_path in csr_files: + try: + data = load_yaml(csr_path) + except Exception: + continue + + if not isinstance(data, dict) or data.get("kind") != "csr": + continue + + csr_name = data.get("name", csr_path.stem) + fields = data.get("fields", {}) + + # Check CSR-level IDL + for key in idl_field_keys: + idl_code = data.get(key) + if isinstance(idl_code, str): + for match in param_pattern.finditer(idl_code): + pname = match.group(1) + param_to_csrs[pname].append( + { + "csr": csr_name, + "field": "(csr-level)", + "idl_key": key, + } + ) + csr_to_params[csr_name].add(pname) + + # Check field-level IDL + if isinstance(fields, dict): + for field_name, field_data in fields.items(): + if not isinstance(field_data, dict): + continue + for key in idl_field_keys: + idl_code = field_data.get(key) + if isinstance(idl_code, str): + for match in param_pattern.finditer(idl_code): + pname = match.group(1) + param_to_csrs[pname].append( + { + "csr": csr_name, + "field": field_name, + "idl_key": key, + } + ) + csr_to_params[csr_name].add(pname) + + # Also check type() which returns CsrFieldType + type_func = field_data.get("type()") + if isinstance(type_func, str): + for match in param_pattern.finditer(type_func): + pname = match.group(1) + param_to_csrs[pname].append( + { + "csr": csr_name, + "field": field_name, + "idl_key": "type()", + } + ) + csr_to_params[csr_name].add(pname) + + # Deduplicate + for pname in param_to_csrs: + seen = set() + deduped = [] + for ref in param_to_csrs[pname]: + key = (ref["csr"], ref["field"], ref["idl_key"]) + if key not in seen: + seen.add(key) + deduped.append(ref) + param_to_csrs[pname] = deduped + + return dict(param_to_csrs), {k: sorted(v) for k, v in csr_to_params.items()} + + +# --------------------------------------------------------------------------- +# Classification logic +# --------------------------------------------------------------------------- + +# Patterns in parameter names that indicate CSR-related parameters +CSR_NAME_PATTERNS = [ + (r"^MTVEC_", "mtvec"), + (r"^STVEC_", "stvec"), + (r"^VSTVEC_", "vstvec"), + (r"^MSTATUS_", "mstatus"), + (r"^MISA_", "misa"), + (r"^MUTABLE_MISA_", "misa"), + (r"^SATP_", "satp"), + (r"^DCSR_", "dcsr"), + (r"^JVT_", "jvt"), + (r"^MSTATEEN_", "mstateen"), + (r"^HSTATEEN_", "hstateen"), + (r"^SSTATEEN_", "sstateen"), + (r"^HPM_", "hpmcounter/hpmevent"), + (r"^COUNTINHIBIT_", "mcountinhibit"), + (r"^MCOUNTENABLE_", "mcounteren"), + (r"^SCOUNTENABLE_", "scounteren"), + (r"^HCOUNTENABLE_", "hcounteren"), +] + +# Parameters that are clearly about trap/reporting behavior (not CSR fields) +TRAP_REPORT_PATTERNS = [ + r"^TRAP_ON_", + r"^REPORT_", + r"^PRECISE_", +] + +# Parameters known to be direct architectural choices +DIRECT_ARCH_NAMES = { + "MXLEN", + "SXLEN", + "UXLEN", + "VSXLEN", + "VUXLEN", + "PHYS_ADDR_WIDTH", + "NUM_PMP_ENTRIES", + "PMP_GRANULARITY", + "VLEN", + "ELEN", + "CACHE_BLOCK_SIZE", + "PMA_GRANULARITY", + "ASID_WIDTH", + "VMID_WIDTH", + "PMLEN", + "ARCH_ID_VALUE", + "IMP_ID_VALUE", + "VENDOR_ID_BANK", + "VENDOR_ID_OFFSET", + "CONFIG_PTR_ADDRESS", + "NUM_EXTERNAL_GUEST_INTERRUPTS", + "MARCHID_IMPLEMENTED", + "MIMPID_IMPLEMENTED", +} + + +def classify_parameter(param_data, csr_refs, value_type_info): + """ + Heuristically assign a classification to a parameter. + + Classification hierarchy: + NORM_DIRECT - Normative, directly configurable (not CSR-controlled) + NORM_CSR_WARL - Normative, parameter is legal values of a WARL CSR field + NORM_CSR_RW - Normative, whether a CSR/field is RO vs RW + SW_RULE - Software-deterministic (impl-defined but determinate with correct SW) + NON_ISA - Platform-level, not ISA architectural + NON_NORM - Non-normative / informational + UNKNOWN - Cannot confidently classify + """ + name = param_data.get("name", "") + desc = param_data.get("description", "").lower() + has_csr_refs = len(csr_refs) > 0 + has_sw_write_ref = any(r["idl_key"] == "sw_write(csr_value)" for r in csr_refs) + has_type_ref = any(r["idl_key"] == "type()" for r in csr_refs) + + classification = "UNKNOWN" + confidence = "low" + reasoning = "" + + # --- Check for HW_ prefix first (hardware update behavior, SW-deterministic) --- + # Must come before CSR checks because HW_ params are referenced in CSR type() + # but are conceptually SW rules, not CSR-controlled parameters + if name.startswith("HW_"): + classification = "SW_RULE" + confidence = "medium" + reasoning = ( + "Hardware update behavior (HW_ prefix) — software-deterministic with correct fencing" + ) + return classification, confidence, reasoning + + # --- Check for existence/availability parameters --- + # Params with _IMPLEMENTED or _AVAILABLE suffix control whether a CSR/feature + # exists at all. They may be referenced in CSR IDL (because the CSR behavior + # depends on whether it exists), but the parameter itself is a direct + # architectural choice, not a WARL/RW control. + if name.endswith("_IMPLEMENTED") or name.endswith("_AVAILABLE"): + classification = "NORM_DIRECT" + confidence = "high" + reasoning = f"Feature/CSR existence parameter ('{name.split('_')[-1]}' suffix)" + return classification, confidence, reasoning + + # --- Check for direct architectural parameters --- + if name in DIRECT_ARCH_NAMES: + classification = "NORM_DIRECT" + confidence = "high" + reasoning = f"Well-known architectural parameter '{name}'" + return classification, confidence, reasoning + + # --- Check for trap/report behavior (normative, not CSR-controlled) --- + for pattern in TRAP_REPORT_PATTERNS: + if re.match(pattern, name): + classification = "NORM_DIRECT" + confidence = "high" + reasoning = f"Trap/report behavior parameter (matches {pattern})" + return classification, confidence, reasoning + + # --- Check for CSR WARL field parameters --- + # If the parameter is referenced in sw_write() of a CSR field, + # it controls the legal write values — classic WARL parameter + if has_sw_write_ref: + csr_fields = [ + (r["csr"], r["field"]) for r in csr_refs if r["idl_key"] == "sw_write(csr_value)" + ] + classification = "NORM_CSR_WARL" + confidence = "high" + reasoning = f"Referenced in sw_write() of {csr_fields[0][0]}.{csr_fields[0][1]}" + return classification, confidence, reasoning + + # If referenced in type() of a CSR field, it controls read-write behavior + if has_type_ref: + csr_fields = [(r["csr"], r["field"]) for r in csr_refs if r["idl_key"] == "type()"] + classification = "NORM_CSR_RW" + confidence = "high" + reasoning = f"Controls type (RO/RW) of {csr_fields[0][0]}.{csr_fields[0][1]}" + return classification, confidence, reasoning + + # --- Check name patterns that suggest CSR association --- + for pattern, csr in CSR_NAME_PATTERNS: + if re.match(pattern, name): + # _TYPE suffix with rw/read-only values = controls field RO/RW behavior + if name.endswith("_TYPE"): + classification = "NORM_CSR_RW" + confidence = "medium" if has_csr_refs else "low" + reasoning = ( + f"CSR field type control parameter for '{csr}' (determines RO/RW behavior)" + ) + return classification, confidence, reasoning + + if has_csr_refs: + classification = "NORM_CSR_WARL" + confidence = "medium" + reasoning = ( + f"Name pattern suggests CSR '{csr}' association, confirmed by IDL references" + ) + else: + classification = "NORM_CSR_WARL" + confidence = "low" + reasoning = f"Name pattern suggests CSR '{csr}' association, but no IDL cross-reference found" + return classification, confidence, reasoning + + # --- Check for SW-rule parameters --- + sw_rule_keywords = [ + "implementation-defined whether", + "implementation may choose", + "implementation defined", + "imprecise", + "unpredictable", + ] + for kw in sw_rule_keywords: + if kw in desc: + if "dirty" in desc or "fence" in desc or "cache" in desc: + classification = "SW_RULE" + confidence = "medium" + reasoning = f"Description contains '{kw}' with dirty/fence/cache context" + return classification, confidence, reasoning + + # --- Check for endianness parameters --- + if "ENDIANNESS" in name: + if has_csr_refs: + classification = "NORM_CSR_WARL" + confidence = "high" + reasoning = "Endianness parameter controlled via mstatus/mstatush WARL bits" + else: + classification = "NORM_DIRECT" + confidence = "medium" + reasoning = "Endianness parameter" + return classification, confidence, reasoning + + # --- Check for translation mode parameters --- + if "TRANSLATION" in name or "MODE" in name: + if has_csr_refs: + classification = "NORM_CSR_WARL" + confidence = "medium" + reasoning = "Translation/mode parameter with CSR references" + else: + classification = "NORM_DIRECT" + confidence = "medium" + reasoning = "Translation/mode parameter" + return classification, confidence, reasoning + + # --- Check for TINST/TVAL parameters --- + if name.startswith("TINST_") or "TVAL" in name: + classification = "NORM_DIRECT" + confidence = "medium" + reasoning = "Trap value reporting parameter" + return classification, confidence, reasoning + + # --- Check for FOLLOW/FORCE/IGNORE parameters (behavioral choices) --- + if name.startswith("FOLLOW_") or name.startswith("FORCE_") or name.startswith("IGNORE_"): + classification = "NORM_DIRECT" + confidence = "medium" + reasoning = "Implementation behavioral choice parameter" + return classification, confidence, reasoning + + # --- Check for LRSC parameters --- + if "LRSC" in name: + classification = "NORM_DIRECT" + confidence = "medium" + reasoning = "Load-reserved/store-conditional behavior parameter" + return classification, confidence, reasoning + + # --- Check for MISALIGNED parameters --- + if "MISALIGNED" in name: + classification = "NORM_DIRECT" + confidence = "medium" + reasoning = "Misaligned access behavior parameter" + return classification, confidence, reasoning + + # --- Check for HW_ prefix (hardware update behavior) --- + if name.startswith("HW_"): + classification = "SW_RULE" + confidence = "medium" + reasoning = "Hardware update behavior — may be software-deterministic" + return classification, confidence, reasoning + + # --- Fallback: if it has CSR refs, lean toward CSR-related --- + if has_csr_refs: + # Distinguish: sw_write/type refs → CSR-controlled; sw_read/reset refs → incidental + has_write_or_type = any( + r["idl_key"] in ("sw_write(csr_value)", "type()", "legal?(csr_value)") for r in csr_refs + ) + if has_write_or_type: + classification = "NORM_CSR_WARL" + confidence = "low" + reasoning = "Has CSR write/type IDL references but no strong name/description signal" + else: + classification = "NORM_DIRECT" + confidence = "low" + reasoning = ( + "Has CSR read/reset IDL references only (incidental, not controlling WARL behavior)" + ) + return classification, confidence, reasoning + + # --- Default --- + classification = "NORM_DIRECT" + confidence = "low" + reasoning = "No strong signals; defaulting to direct normative parameter" + return classification, confidence, reasoning + + +# --------------------------------------------------------------------------- +# Main export logic +# --------------------------------------------------------------------------- + + +def export_single_param(yaml_path, param_csr_refs): + """Read one param YAML and produce a structured dict.""" + data = load_yaml(yaml_path) + if not isinstance(data, dict): + return None + + name = data.get("name", yaml_path.stem) + schema = data.get("schema", {}) + defined_by = data.get("definedBy") + requirements = data.get("requirements") + description = data.get("description", "") + long_name = data.get("long_name", "") + + value_type_info = derive_value_type(schema) + defined_by_info = flatten_defined_by(defined_by) + csr_refs = param_csr_refs.get(name, []) + + classification, confidence, reasoning = classify_parameter(data, csr_refs, value_type_info) + + has_requirements = requirements is not None + req_summary = None + if has_requirements: + if isinstance(requirements, dict): + req_summary = requirements.get("reason", requirements.get("idl()", "")[:200]) + elif isinstance(requirements, str): + req_summary = requirements[:200] + + result = { + "name": name, + "long_name": long_name.strip() if isinstance(long_name, str) else str(long_name), + "description": description.strip() if isinstance(description, str) else str(description), + "defined_by": defined_by_info, + "value_type": value_type_info, + "has_requirements": has_requirements, + "requirements_summary": req_summary, + "csr_references": csr_refs, + "classification": classification, + "classification_confidence": confidence, + "classification_reasoning": reasoning, + "source_file": str(yaml_path.relative_to(REPO_ROOT)), + } + + return result + + +def main(): + OUTPUT_DIR.mkdir(parents=True, exist_ok=True) + + # Step 1: Collect all non-MOCK parameter names + param_files = sorted(PARAM_DIR.glob("*.yaml")) + real_params = [f for f in param_files if not f.stem.startswith("MOCK_")] + print( + f"Found {len(real_params)} real parameter files (excluded {len(param_files) - len(real_params)} MOCK files)" + ) + + param_names = [f.stem for f in real_params] + + # Step 2: Build CSR cross-reference + print("Building CSR cross-reference...") + param_to_csrs, _csr_to_params = build_csr_param_xref(CSR_DIR, param_names) + params_with_csr_refs = sum(1 for v in param_to_csrs.values() if v) + print(f" {params_with_csr_refs} parameters referenced in CSR IDL code") + + # Step 3: Export each parameter + print("Exporting parameters...") + results = [] + for pf in real_params: + entry = export_single_param(pf, param_to_csrs) + if entry: + results.append(entry) + + # Step 4: Compute statistics + stats = compute_statistics(results) + + output = { + "metadata": { + "total_parameters": len(results), + "source": str(PARAM_DIR.relative_to(REPO_ROOT)), + "csr_source": str(CSR_DIR.relative_to(REPO_ROOT)), + }, + "statistics": stats, + "parameters": results, + } + + out_path = OUTPUT_DIR / "ground_truth.json" + with open(out_path, "w", encoding="utf-8") as f: + json.dump(output, f, indent=2, ensure_ascii=False, default=str) + + print(f"\nWritten {len(results)} parameters to {out_path}") + print_summary(stats) + + +def compute_statistics(results): + """Compute summary statistics over the exported parameters.""" + class_counts = defaultdict(int) + type_counts = defaultdict(int) + confidence_counts = defaultdict(int) + ext_counts = defaultdict(int) + + params_with_csr_refs = 0 + params_with_requirements = 0 + + for r in results: + class_counts[r["classification"]] += 1 + type_counts[r["value_type"]["type"]] += 1 + confidence_counts[r["classification_confidence"]] += 1 + + if r["csr_references"]: + params_with_csr_refs += 1 + if r["has_requirements"]: + params_with_requirements += 1 + + for ext in r["defined_by"]["extensions"]: + ext_counts[ext] += 1 + + return { + "by_classification": dict(sorted(class_counts.items())), + "by_value_type": dict(sorted(type_counts.items())), + "by_confidence": dict(sorted(confidence_counts.items())), + "params_with_csr_references": params_with_csr_refs, + "params_with_requirements": params_with_requirements, + "top_defining_extensions": dict(sorted(ext_counts.items(), key=lambda x: -x[1])[:15]), + } + + +def print_summary(stats): + """Print a human-readable summary to stdout.""" + print("\n" + "=" * 60) + print("PARAMETER EXPORT SUMMARY") + print("=" * 60) + + print("\nBy Classification:") + for cls, count in sorted(stats["by_classification"].items()): + print(f" {cls:20s} {count:4d}") + + print("\nBy Value Type:") + for vt, count in sorted(stats["by_value_type"].items()): + print(f" {vt:20s} {count:4d}") + + print("\nBy Confidence:") + for conf, count in sorted(stats["by_confidence"].items()): + print(f" {conf:20s} {count:4d}") + + print(f"\nWith CSR references: {stats['params_with_csr_references']}") + print(f"With requirements IDL: {stats['params_with_requirements']}") + + print("\nTop Defining Extensions:") + for ext, count in list(stats["top_defining_extensions"].items())[:10]: + print(f" {ext:20s} {count:4d}") + + +if __name__ == "__main__": + main() diff --git a/param_extraction/scripts/generate_report.py b/param_extraction/scripts/generate_report.py new file mode 100755 index 0000000000..d31de6f60f --- /dev/null +++ b/param_extraction/scripts/generate_report.py @@ -0,0 +1,247 @@ +#!/usr/bin/env python3 +""" +Phase 1, Final: Generate a comprehensive human-readable report and CSV +from the ground truth and spec mapping data. + +Produces: + - data/phase1_report.txt (human-readable summary) + - data/parameters_catalog.csv (spreadsheet-ready catalog) + - data/udb_param_names.txt (flat list for LLM prompt inclusion) + +Reads: + - data/ground_truth.json + - data/spec_mappings.json +""" + +import csv +import json +from collections import defaultdict +from pathlib import Path + +DATA_DIR = Path(__file__).resolve().parent.parent / "data" + + +def main(): + # Load data + with open(DATA_DIR / "ground_truth.json", encoding="utf-8") as f: + gt = json.load(f) + with open(DATA_DIR / "spec_mappings.json", encoding="utf-8") as f: + sm = json.load(f) + + params = gt["parameters"] + mappings = {m["parameter_name"]: m for m in sm["mappings"]} + + # Generate flat name list (for LLM prompts) + names = sorted(p["name"] for p in params) + names_path = DATA_DIR / "udb_param_names.txt" + with open(names_path, "w") as f: + for name in names: + f.write(name + "\n") + print(f"Written {len(names)} parameter names to {names_path}") + + # Generate CSV catalog + csv_path = DATA_DIR / "parameters_catalog.csv" + generate_csv(params, mappings, csv_path) + print(f"Written CSV catalog to {csv_path}") + + # Generate human-readable report + report_path = DATA_DIR / "phase1_report.txt" + generate_report(params, mappings, gt["statistics"], sm["metadata"], report_path) + print(f"Written report to {report_path}") + + +def generate_csv(params, mappings, out_path): + """Generate a CSV file suitable for review or import into a spreadsheet.""" + rows = [] + for p in params: + m = mappings.get(p["name"], {}) + candidates = m.get("candidates", []) + best = candidates[0] if candidates else {} + + rows.append( + { + "parameter_name": p["name"], + "long_name": p["long_name"], + "classification": p["classification"], + "classification_confidence": p["classification_confidence"], + "classification_reasoning": p["classification_reasoning"], + "value_type": p["value_type"]["type"], + "value_details": _format_value_details(p["value_type"]), + "defined_by_extensions": ", ".join(p["defined_by"]["extensions"]), + "defined_by_summary": p["defined_by"]["summary"], + "has_requirements": p["has_requirements"], + "num_csr_references": len(p["csr_references"]), + "csr_names": ", ".join(sorted(set(r["csr"] for r in p["csr_references"]))), + "spec_file": best.get("file", ""), + "spec_line": best.get("line_number", ""), + "spec_score": best.get("score", 0), + "spec_is_normative": best.get("is_normative", ""), + "spec_in_note": best.get("in_note", ""), + "spec_text": best.get("line_text", "")[:200], + "description": p["description"][:300], + } + ) + + with open(out_path, "w", newline="", encoding="utf-8") as f: + writer = csv.DictWriter(f, fieldnames=list(rows[0].keys())) + writer.writeheader() + writer.writerows(rows) + + +def _format_value_details(value_type): + """Format value type details into a compact string.""" + vt = value_type["type"] + details = value_type.get("details", {}) + + if vt == "binary": + choices = details.get("choices", []) + return f"choices: {choices}" + elif vt == "enum": + vals = details.get("values", []) + if len(vals) <= 5: + return f"values: {vals}" + return f"{len(vals)} values" + elif vt == "range": + return f"[{details.get('minimum', '?')}..{details.get('maximum', '?')}]" + elif vt == "set": + universe = details.get("universe", []) + if universe: + return f"subset of {universe}" + return f"set of {details.get('element_type', '?')}" + elif vt == "bitmask": + return f"{details.get('length', '?')}-bit mask" + elif vt == "conditional": + branches = details.get("branches", []) + return f"{len(branches)} conditional branches" + return str(details)[:80] + + +def generate_report(params, mappings, stats, mapping_meta, out_path): + """Generate a comprehensive human-readable report.""" + lines = [] + w = lines.append + + w("=" * 72) + w("PHASE 1 REPORT: UDB Parameter Ground Truth") + w("RISC-V Architectural Parameter Extraction Project") + w("=" * 72) + w("") + + # --- Overview --- + w("1. OVERVIEW") + w("-" * 40) + w(f" Total real parameters in UDB: {len(params)}") + w(f" Spec files searched: {mapping_meta['spec_files_searched']}") + w(f" Total spec lines: {mapping_meta['total_spec_lines']}") + w( + f" Parameters with spec matches: {mapping_meta['params_with_matches']} ({mapping_meta['params_with_matches'] * 100 // len(params)}%)" + ) + w( + f" Parameters with strong matches: {mapping_meta['params_with_strong_matches']} ({mapping_meta['params_with_strong_matches'] * 100 // len(params)}%)" + ) + w("") + + # --- Classification breakdown --- + w("2. CLASSIFICATION BREAKDOWN") + w("-" * 40) + for cls, count in sorted(stats["by_classification"].items()): + pct = count * 100 // len(params) + w(f" {cls:20s} {count:4d} ({pct:2d}%)") + w("") + w(" Classification descriptions:") + w(" NORM_DIRECT = Normative, directly configurable (not CSR-controlled)") + w(" NORM_CSR_WARL = Normative, legal values of a WARL CSR field") + w(" NORM_CSR_RW = Normative, controls whether CSR field is RO/RW") + w(" SW_RULE = Software-deterministic (impl-defined but deterministic w/ correct SW)") + w("") + + # --- Value type breakdown --- + w("3. VALUE TYPE BREAKDOWN") + w("-" * 40) + for vt, count in sorted(stats["by_value_type"].items()): + pct = count * 100 // len(params) + w(f" {vt:20s} {count:4d} ({pct:2d}%)") + w("") + w(" Value type descriptions:") + w(" binary = Exactly 2 choices (boolean or 2-value enum)") + w(" enum = Finite set of 3+ discrete values") + w(" range = Continuous integer range with min/max bounds") + w(" set = Subset selection from a fixed universe of values") + w(" bitmask = Fixed-length boolean array (one bit per feature)") + w(" conditional = Schema varies based on another parameter (e.g., MXLEN)") + w(" value = Single unconstrained value") + w("") + + # --- Confidence breakdown --- + w("4. CLASSIFICATION CONFIDENCE") + w("-" * 40) + for conf, count in sorted(stats["by_confidence"].items()): + pct = count * 100 // len(params) + w(f" {conf:20s} {count:4d} ({pct:2d}%)") + w("") + + # --- Extension breakdown --- + w("5. DEFINING EXTENSIONS (Top 15)") + w("-" * 40) + for ext, count in list(stats["top_defining_extensions"].items())[:15]: + w(f" {ext:20s} {count:4d}") + w("") + + # --- Detailed parameter listing by classification --- + w("6. PARAMETER LISTING BY CLASSIFICATION") + w("-" * 40) + + by_class = defaultdict(list) + for p in params: + by_class[p["classification"]].append(p) + + for cls in ["NORM_DIRECT", "NORM_CSR_WARL", "NORM_CSR_RW", "SW_RULE", "UNKNOWN"]: + class_params = by_class.get(cls, []) + if not class_params: + continue + + w(f"\n --- {cls} ({len(class_params)} parameters) ---") + for p in sorted(class_params, key=lambda x: x["name"]): + m = mappings.get(p["name"], {}) + candidates = m.get("candidates", []) + best = candidates[0] if candidates else {} + + vt = p["value_type"] + vt_str = vt["type"] + if vt["type"] == "binary": + choices = vt.get("details", {}).get("choices", []) + vt_str = f"binary({choices})" + elif vt["type"] == "enum": + vals = vt.get("details", {}).get("values", []) + vt_str = f"enum({len(vals)} vals)" + + spec_loc = "" + if best: + spec_loc = f" -> {best.get('file', '?')}:{best.get('line_number', '?')}" + if best.get("is_normative"): + spec_loc += " [NORM]" + + csr_str = "" + if p["csr_references"]: + csrs = sorted(set(r["csr"] for r in p["csr_references"]))[:3] + csr_str = f" CSRs: {', '.join(csrs)}" + + w(f" {p['name']}") + w(f" Type: {vt_str} | Exts: {p['defined_by']['summary']}{csr_str}") + if spec_loc: + w(f" Spec:{spec_loc}") + w( + f" Conf: {p['classification_confidence']} | {p['classification_reasoning'][:90]}" + ) + + w("") + w("=" * 72) + w("END OF REPORT") + w("=" * 72) + + with open(out_path, "w", encoding="utf-8") as f: + f.write("\n".join(lines)) + + +if __name__ == "__main__": + main() diff --git a/param_extraction/scripts/map_params_to_spec.py b/param_extraction/scripts/map_params_to_spec.py new file mode 100755 index 0000000000..552953e6c1 --- /dev/null +++ b/param_extraction/scripts/map_params_to_spec.py @@ -0,0 +1,476 @@ +#!/usr/bin/env python3 +""" +Phase 1, Step 2: Map UDB parameters to their source locations in the RISC-V spec. + +For each parameter, searches the spec .adoc files for sentences that describe +the implementation choice that parameter represents. Uses multiple search +strategies: keyword matching from descriptions, CSR name references, +known WARL/implementation-defined language patterns, and exact name matches. + +Reads: data/ground_truth.json +Output: data/spec_mappings.json +""" + +import json +import re +from collections import defaultdict +from pathlib import Path + +REPO_ROOT = Path(__file__).resolve().parent.parent.parent +SPEC_DIR = REPO_ROOT / "ext" / "riscv-isa-manual" / "src" +DATA_DIR = Path(__file__).resolve().parent.parent / "data" + + +# --------------------------------------------------------------------------- +# Spec file loading and indexing +# --------------------------------------------------------------------------- + + +def load_spec_files(): + """Load all .adoc files from the spec directory, returning {filename: [lines]}.""" + spec_files = {} + for adoc in sorted(SPEC_DIR.glob("*.adoc")): + with open(adoc, encoding="utf-8") as f: + spec_files[adoc.name] = f.readlines() + return spec_files + + +def is_note_block(lines, line_idx): + """ + Check if a given line is inside a NOTE/TIP/WARNING block (non-normative). + AsciiDoc NOTE blocks are delimited by '===='. + Also checks for explicit [NOTE]/[TIP]/[WARNING] markers. + """ + note_markers = {"[NOTE]", "[TIP]", "[WARNING]", "[IMPORTANT]", "[CAUTION]"} + + # Look backwards from this line for the nearest block marker + depth = 0 + for i in range(line_idx - 1, max(line_idx - 30, -1), -1): + if i < 0: + break + stripped = lines[i].strip() + if stripped == "====": + depth += 1 + if depth == 1: + # Check if the line before this ==== is a note marker + for j in range(i - 1, max(i - 3, -1), -1): + if j >= 0 and lines[j].strip() in note_markers: + return True + return False + return False + + +# --------------------------------------------------------------------------- +# Search strategy: build search terms from parameter metadata +# --------------------------------------------------------------------------- + + +def build_search_terms(param): + """ + Build a list of (pattern, weight, reason) tuples to search for this parameter. + Higher weight = more likely to be a relevant match. + """ + name = param["name"] + desc = param.get("description", "") + csr_refs = param.get("csr_references", []) + value_type = param.get("value_type", {}) + + terms = [] + + # Strategy 0: The parameter name itself (may appear verbatim in spec) + # Match as a whole word, case-sensitive for ALL_CAPS names + if name == name.upper() and len(name) >= 3: + terms.append( + ( + re.compile(rf"\b{re.escape(name)}\b"), + 6, + f"Exact parameter name '{name}'", + ) + ) + # Also search for the name in italic/emphasis form: _NAME_ + terms.append( + ( + re.compile(rf"_{re.escape(name)}_"), + 6, + f"Parameter name in emphasis '_{name}_'", + ) + ) + + # Strategy 0b: Search for key segments of multi-word param names + name_segments = name.split("_") + # For short distinctive segments (>=4 chars, not common words), search directly + common_words = { + "MODE", + "TYPE", + "VALUE", + "WIDTH", + "LEGAL", + "VALUES", + "READ", + "ONLY", + "WHEN", + "ZERO", + "BASE", + "TRAP", + "REPORT", + } + for seg in name_segments: + if len(seg) >= 4 and seg not in common_words: + terms.append( + ( + re.compile(rf"\b{re.escape(seg)}\b", re.IGNORECASE), + 1, + f"Name segment '{seg}'", + ) + ) + + # Strategy 1: CSR name + field name (for CSR-related params) + # Cap to avoid score inflation for params with hundreds of CSR refs + csr_names_seen = set() + fields_seen = set() + MAX_CSR_TERMS = 10 + csr_term_count = 0 + for ref in csr_refs: + if csr_term_count >= MAX_CSR_TERMS: + break + csr = ref["csr"] + field = ref["field"] + if csr not in csr_names_seen: + terms.append( + ( + re.compile(rf"`{re.escape(csr)}`", re.IGNORECASE), + 3, + f"CSR name '{csr}' in backticks", + ) + ) + csr_names_seen.add(csr) + csr_term_count += 1 + if field != "(csr-level)" and field not in fields_seen: + terms.append( + ( + re.compile(rf"\b{re.escape(field)}\b", re.IGNORECASE), + 2, + f"CSR field name '{field}'", + ) + ) + fields_seen.add(field) + csr_term_count += 1 + + # Strategy 2: Extract key nouns/phrases from parameter description (cap to avoid noise) + desc_keywords = _extract_description_keywords(name, desc) + for kw, weight in desc_keywords[:12]: + terms.append( + ( + re.compile(rf"\b{re.escape(kw)}\b", re.IGNORECASE), + weight, + f"Description keyword '{kw}'", + ) + ) + + # Strategy 3: Look for WARL near CSR names (for WARL params) + if param.get("classification") in ("NORM_CSR_WARL", "NORM_CSR_RW"): + for csr in csr_names_seen: + terms.append( + ( + re.compile( + rf"WARL.*`{re.escape(csr)}`|`{re.escape(csr)}`.*WARL", re.IGNORECASE + ), + 5, + f"WARL + CSR '{csr}'", + ) + ) + + # Strategy 4: Specific value mentions for enum/binary params + if value_type.get("type") == "binary": + choices = value_type.get("details", {}).get("choices", []) + if choices == [True, False]: + # For boolean params, look for "may" / "optionally" / "read-only" patterns + terms.append( + ( + re.compile( + r"\b(may\s+optionally|optionally|read-only\s+zero|read-only\s+0)\b", + re.IGNORECASE, + ), + 1, + "Optional/read-only pattern for boolean param", + ) + ) + + return terms + + +def _extract_description_keywords(name, description): + """ + Extract meaningful search keywords from the parameter's description. + Returns list of (keyword, weight) tuples. + """ + keywords = [] + + # Extract CSR names from description (things in backticks) + backtick_refs = re.findall(r"`([a-zA-Z][a-zA-Z0-9_.]*)`", description) + for ref in backtick_refs: + keywords.append((ref, 3)) + + # Look for capitalized CSR field references like MODE, BASE, etc. + field_refs = re.findall(r"\b([A-Z]{2,}(?:\.[A-Z]+)?)\b", description) + for ref in field_refs: + if ref not in ( + "WARL", + "WLRL", + "CSR", + "ISA", + "RISC", + "TODO", + "XLEN", + "MXLEN", + "AND", + "NOT", + "THE", + "FOR", + "WHEN", + "SXLEN", + "UXLEN", + "ALL", + "PMP", + "HPM", + "AMO", + "NMI", + ): + keywords.append((ref, 2)) + + # Extract meaningful phrases based on parameter name segments + name_parts = name.split("_") + # Find multi-word concepts in the name + name_to_phrase = { + "ENDIANNESS": "endian", + "MISALIGNED": "misaligned", + "ALIGNMENT": "align", + "TRANSLATION": "translation", + "RESERVATION": "reservation", + "GRANULARITY": "granularity", + "BREAKPOINT": "breakpoint", + "INSTRUCTION": "instruction", + "VECTORED": "vectored", + "IMPLEMENTED": "implemented", + } + for part in name_parts: + phrase = name_to_phrase.get(part) + if phrase: + keywords.append((phrase, 2)) + + return keywords + + +# --------------------------------------------------------------------------- +# Core matching engine +# --------------------------------------------------------------------------- + + +def find_spec_locations(param, spec_files): + """ + Search all spec files for text related to this parameter. + + Returns a list of candidate matches, sorted by relevance score. + Each match: {file, line_number, line_text, score, reasons, is_normative, in_note} + """ + search_terms = build_search_terms(param) + if not search_terms: + return [] + + candidates = defaultdict( + lambda: { + "score": 0, + "reasons": [], + "is_normative": False, + "in_note": False, + } + ) + + for filename, lines in spec_files.items(): + for line_idx, line in enumerate(lines): + line_stripped = line.strip() + if not line_stripped or line_stripped.startswith("//"): + continue + + # Skip table-heavy lines (pipes indicate table cells, not prose) + if line_stripped.count("|") >= 3: + continue + + line_key = (filename, line_idx + 1) + + # Track which strategy categories matched to prevent score inflation + segment_score = 0 + max_segment_score = 3 # cap contribution from name-segment matches + normative_bonus_applied = False + + for pattern, weight, reason in search_terms: + if pattern.search(line): + entry = candidates[line_key] + entry["file"] = filename + entry["line_number"] = line_idx + 1 + entry["line_text"] = line_stripped + + if "Name segment" in reason: + segment_score += weight + entry["score"] += min(weight, max_segment_score - (segment_score - weight)) + if segment_score - weight < max_segment_score: + entry["reasons"].append(reason) + else: + entry["score"] += weight + entry["reasons"].append(reason) + + if not normative_bonus_applied and ("[#norm:" in line or "[[norm:" in line): + entry["is_normative"] = True + entry["score"] += 2 + normative_bonus_applied = True + + if is_note_block(lines, line_idx): + entry["in_note"] = True + entry["score"] -= 3 + + # Convert to list, filter low-score noise, sort by score descending + results = [] + MAX_SCORE = 50 + for _key, entry in candidates.items(): + if entry["score"] >= 3: + entry["score"] = min(entry["score"], MAX_SCORE) + entry["reasons"] = list(set(entry["reasons"])) + results.append(entry) + + results.sort(key=lambda x: (-x["score"], x["file"], x["line_number"])) + return results[:10] + + +# --------------------------------------------------------------------------- +# Context extraction: get surrounding lines for each match +# --------------------------------------------------------------------------- + + +def extract_context(spec_files, filename, line_number, context_lines=2): + """Get the matched line plus surrounding context lines.""" + lines = spec_files.get(filename, []) + if not lines: + return "" + + start = max(0, line_number - 1 - context_lines) + end = min(len(lines), line_number + context_lines) + + context_parts = [] + for i in range(start, end): + prefix = ">>>" if i == line_number - 1 else " " + context_parts.append(f"{prefix} {i + 1:5d}| {lines[i].rstrip()}") + + return "\n".join(context_parts) + + +# --------------------------------------------------------------------------- +# Main mapping logic +# --------------------------------------------------------------------------- + + +def main(): + # Load ground truth + gt_path = DATA_DIR / "ground_truth.json" + if not gt_path.exists(): + print(f"ERROR: {gt_path} not found. Run export_udb_params.py first.") + return + + with open(gt_path, encoding="utf-8") as f: + ground_truth = json.load(f) + + params = ground_truth["parameters"] + print(f"Loaded {len(params)} parameters from ground truth") + + # Load spec files + print(f"Loading spec files from {SPEC_DIR}...") + spec_files = load_spec_files() + total_lines = sum(len(lines) for lines in spec_files.values()) + print(f" {len(spec_files)} files, {total_lines} total lines") + + # Map each parameter + print("Mapping parameters to spec text...") + mappings = [] + params_with_matches = 0 + params_with_strong_matches = 0 + + for i, param in enumerate(params): + candidates = find_spec_locations(param, spec_files) + + has_match = len(candidates) > 0 + best_score = candidates[0]["score"] if candidates else 0 + has_strong = best_score >= 5 + + if has_match: + params_with_matches += 1 + if has_strong: + params_with_strong_matches += 1 + + # Add context to top candidates + for cand in candidates[:5]: + cand["context"] = extract_context(spec_files, cand["file"], cand["line_number"]) + + entry = { + "parameter_name": param["name"], + "classification": param["classification"], + "value_type": param["value_type"]["type"], + "num_candidates": len(candidates), + "best_score": best_score, + "candidates": candidates[:5], + } + mappings.append(entry) + + if (i + 1) % 20 == 0: + print(f" Processed {i + 1}/{len(params)} parameters...") + + # Output + output = { + "metadata": { + "total_parameters": len(params), + "params_with_matches": params_with_matches, + "params_with_strong_matches": params_with_strong_matches, + "spec_files_searched": len(spec_files), + "total_spec_lines": total_lines, + }, + "mappings": mappings, + } + + out_path = DATA_DIR / "spec_mappings.json" + with open(out_path, "w", encoding="utf-8") as f: + json.dump(output, f, indent=2, ensure_ascii=False) + + print(f"\nWritten mappings to {out_path}") + print(f"\n{'=' * 60}") + print("SPEC MAPPING SUMMARY") + print(f"{'=' * 60}") + print(f"Total parameters: {len(params)}") + print( + f"With any match (score>=3): {params_with_matches} ({params_with_matches * 100 // len(params)}%)" + ) + print( + f"With strong match (>=5): {params_with_strong_matches} ({params_with_strong_matches * 100 // len(params)}%)" + ) + print(f"No matches found: {len(params) - params_with_matches}") + + # Show a few examples of strong matches + print("\n--- Sample strong matches ---") + shown = 0 + for m in mappings: + if m["best_score"] >= 7 and shown < 5: + cand = m["candidates"][0] + print(f"\n {m['parameter_name']} (score={cand['score']}, {m['classification']})") + print(f" File: {cand['file']}:{cand['line_number']}") + print(f" Text: {cand['line_text'][:120]}") + shown += 1 + + # Show parameters with no matches + no_match = [m["parameter_name"] for m in mappings if m["num_candidates"] == 0] + if no_match: + print(f"\n--- Parameters with NO spec matches ({len(no_match)}) ---") + for nm in no_match[:20]: + print(f" {nm}") + if len(no_match) > 20: + print(f" ... and {len(no_match) - 20} more") + + +if __name__ == "__main__": + main() diff --git a/param_extraction/scripts/run_prompt.py b/param_extraction/scripts/run_prompt.py new file mode 100755 index 0000000000..26e9594deb --- /dev/null +++ b/param_extraction/scripts/run_prompt.py @@ -0,0 +1,456 @@ +#!/usr/bin/env python3 +""" +Prompt assembler for RISC-V architectural parameter extraction. + +Combines system prompt + few-shot examples + UDB parameter names + spec chunk +into a complete prompt suitable for LLM analysis. + +Three operational modes: + assemble — build and print a complete prompt for a given spec chunk + chunk — split a spec file into overlapping chunks suitable for LLM context + estimate — report token estimates for each prompt layer +""" + +from __future__ import annotations + +import argparse +import json +import sys +from pathlib import Path +from typing import TypedDict + +SCRIPT_DIR = Path(__file__).resolve().parent +PROJECT_DIR = SCRIPT_DIR.parent +PROMPT_DIR = PROJECT_DIR / "prompts" / "v1" +DATA_DIR = PROJECT_DIR / "data" + +CHARS_PER_TOKEN = 3.8 + +CONTEXT_LIMITS: dict[str, int] = { + "gpt-4o": 128_000, + "gpt-4-turbo": 128_000, + "claude-3-5-sonnet": 200_000, + "claude-3-opus": 200_000, + "gemini-1.5-pro": 1_000_000, + "llama-3-70b": 8_192, + "default": 128_000, +} + +RESERVED_OUTPUT_TOKENS = 4_096 +SYSTEM_OVERHEAD_TOKENS = 200 + + +class ChunkMeta(TypedDict): + file: str + start_line: int + end_line: int + total_lines: int + chunk_index: int + total_chunks: int + + +def estimate_tokens(text: str) -> int: + """Rough token estimate using chars/token ratio.""" + return max(1, int(len(text) / CHARS_PER_TOKEN)) + + +def load_system_prompt() -> str: + path = PROMPT_DIR / "system_prompt.txt" + if not path.exists(): + raise FileNotFoundError(f"System prompt not found: {path}") + return path.read_text(encoding="utf-8").strip() + + +def load_examples() -> dict: + path = PROMPT_DIR / "examples.json" + if not path.exists(): + raise FileNotFoundError(f"Examples not found: {path}") + with open(path, encoding="utf-8") as f: + return json.load(f) + + +def load_udb_param_names() -> list[str]: + path = DATA_DIR / "udb_param_names.txt" + if not path.exists(): + raise FileNotFoundError(f"UDB param names not found: {path}") + names = [line.strip() for line in path.read_text(encoding="utf-8").splitlines() if line.strip()] + return sorted(set(names)) + + +def format_examples_section(examples: dict) -> str: + """Format few-shot examples into a clear prompt section.""" + lines = ["## Few-Shot Examples", ""] + lines.append("### Positive Examples (extract these)") + lines.append("") + + for i, ex in enumerate(examples.get("positive_examples", []), 1): + lines.append(f"**Example {i}** — `{ex['input_file']}`, line {ex['input_line']}") + lines.append("") + lines.append("Input text:") + lines.append(f"> {ex['input_excerpt']}") + lines.append("") + lines.append("Expected output:") + lines.append("```json") + lines.append(json.dumps(ex["expected_output"], indent=2)) + lines.append("```") + lines.append("") + + lines.append("### Negative Examples (do NOT extract these)") + lines.append("") + + for i, ex in enumerate(examples.get("negative_examples", []), 1): + lines.append(f"**Non-parameter {i}** — `{ex['input_file']}`, line {ex['input_line']}") + lines.append("") + lines.append("Input text:") + lines.append(f"> {ex['input_excerpt']}") + lines.append("") + lines.append(f"Why not a parameter: {ex['reason_for_rejection']}") + lines.append("") + + return "\n".join(lines) + + +def format_param_names_section(names: list[str]) -> str: + """Format UDB parameter names as a reference list.""" + lines = [ + "## Known UDB Parameter Names", + "", + "When a parameter you find matches one of these known names, use the exact name.", + "For new parameters not in this list, suggest a descriptive UPPER_SNAKE_CASE name.", + "", + ] + lines.append(", ".join(names)) + return "\n".join(lines) + + +def format_chunk_section(chunk_text: str, meta: ChunkMeta) -> str: + """Format the spec chunk with metadata for the LLM.""" + lines = [ + "## Specification Text to Analyze", + "", + f"File: `{meta['file']}`", + f"Lines: {meta['start_line']}-{meta['end_line']} " + f"(chunk {meta['chunk_index']}/{meta['total_chunks']})", + "", + "Analyze the following specification text and extract all architectural parameters.", + "Include line numbers relative to the original file (starting from " + f"line {meta['start_line']}).", + "", + "```", + chunk_text, + "```", + ] + return "\n".join(lines) + + +def assemble_prompt( + chunk_text: str, + meta: ChunkMeta, + model: str = "default", + include_examples: bool = True, + include_param_names: bool = True, +) -> dict[str, str]: + """ + Assemble the complete prompt from all layers. + + Returns a dict with 'system' and 'user' keys suitable for chat API calls. + """ + system_prompt = load_system_prompt() + + user_parts: list[str] = [] + + if include_examples: + examples = load_examples() + user_parts.append(format_examples_section(examples)) + + if include_param_names: + names = load_udb_param_names() + user_parts.append(format_param_names_section(names)) + + user_parts.append(format_chunk_section(chunk_text, meta)) + + user_message = "\n\n---\n\n".join(user_parts) + + total_tokens = ( + estimate_tokens(system_prompt) + + estimate_tokens(user_message) + + SYSTEM_OVERHEAD_TOKENS + + RESERVED_OUTPUT_TOKENS + ) + + limit = CONTEXT_LIMITS.get(model, CONTEXT_LIMITS["default"]) + if total_tokens > limit: + raise ValueError( + f"Assembled prompt ({total_tokens:,} est. tokens) exceeds " + f"{model} context limit ({limit:,} tokens). " + f"Reduce chunk size or disable examples/param names." + ) + + return { + "system": system_prompt, + "user": user_message, + "estimated_tokens": total_tokens, + "model": model, + } + + +# --- Chunking logic --- + + +def detect_section_boundaries(lines: list[str]) -> list[int]: + """ + Find AsciiDoc section headers (lines starting with == or more). + Returns a list of 0-based line indices that are section starts. + """ + boundaries = [] + for i, line in enumerate(lines): + stripped = line.strip() + if ( + stripped.startswith("== ") + or stripped.startswith("=== ") + or stripped.startswith("==== ") + or stripped.startswith("===== ") + ): + boundaries.append(i) + return boundaries + + +def chunk_spec_file( + filepath: Path, + max_chunk_tokens: int = 40_000, + overlap_lines: int = 20, +) -> list[tuple[str, ChunkMeta]]: + """ + Split a spec file into chunks that respect section boundaries. + + Strategy: + 1. Find all section headers in the file. + 2. Greedily accumulate sections until the chunk would exceed max_chunk_tokens. + 3. Emit the chunk and start a new one with `overlap_lines` of overlap. + """ + text = filepath.read_text(encoding="utf-8") + lines = text.splitlines(keepends=True) + total_lines = len(lines) + + if total_lines == 0: + return [] + + boundaries = detect_section_boundaries(lines) + + if not boundaries: + boundaries = [0] + if boundaries[0] != 0: + boundaries.insert(0, 0) + + chunks: list[tuple[str, ChunkMeta]] = [] + current_start = 0 + chunk_index = 0 + + while current_start < total_lines: + candidate_sections = [b for b in boundaries if b >= current_start] + if not candidate_sections: + candidate_sections = [current_start] + + chunk_end = current_start + for i, _sec_start in enumerate(candidate_sections): + next_boundary = ( + candidate_sections[i + 1] if i + 1 < len(candidate_sections) else total_lines + ) + candidate_text = "".join(lines[current_start:next_boundary]) + if estimate_tokens(candidate_text) > max_chunk_tokens and chunk_end > current_start: + break + chunk_end = next_boundary + + if chunk_end <= current_start: + chunk_end = min( + current_start + int(max_chunk_tokens * CHARS_PER_TOKEN / 80), total_lines + ) + + chunk_text = "".join(lines[current_start:chunk_end]) + chunk_index += 1 + meta: ChunkMeta = { + "file": filepath.name, + "start_line": current_start + 1, + "end_line": chunk_end, + "total_lines": total_lines, + "chunk_index": chunk_index, + "total_chunks": 0, + } + chunks.append((chunk_text, meta)) + + if chunk_end >= total_lines: + break + + current_start = max(current_start + 1, chunk_end - overlap_lines) + + for _, meta in chunks: + meta["total_chunks"] = len(chunks) + + return chunks + + +# --- CLI --- + + +def cmd_assemble(args: argparse.Namespace) -> None: + """Assemble and print a complete prompt for a spec chunk.""" + filepath = Path(args.file) + if not filepath.exists(): + print(f"Error: file not found: {filepath}", file=sys.stderr) + sys.exit(1) + + text = filepath.read_text(encoding="utf-8") + lines = text.splitlines(keepends=True) + total_lines = len(lines) + + start = max(1, args.start_line) if args.start_line else 1 + end = min(args.end_line, total_lines) if args.end_line else total_lines + + chunk_text = "".join(lines[start - 1 : end]) + meta: ChunkMeta = { + "file": filepath.name, + "start_line": start, + "end_line": end, + "total_lines": total_lines, + "chunk_index": 1, + "total_chunks": 1, + } + + prompt = assemble_prompt( + chunk_text, + meta, + model=args.model, + include_examples=not args.no_examples, + include_param_names=not args.no_param_names, + ) + + if args.output_json: + json.dump(prompt, sys.stdout, indent=2) + print() + else: + print("=" * 70) + print("SYSTEM PROMPT") + print("=" * 70) + print(prompt["system"]) + print() + print("=" * 70) + print("USER MESSAGE") + print("=" * 70) + print(prompt["user"]) + print() + print("=" * 70) + print(f"Estimated tokens: {prompt['estimated_tokens']:,}") + print(f"Model: {prompt['model']}") + print("=" * 70) + + +def cmd_chunk(args: argparse.Namespace) -> None: + """Split a spec file into chunks and show their boundaries.""" + filepath = Path(args.file) + if not filepath.exists(): + print(f"Error: file not found: {filepath}", file=sys.stderr) + sys.exit(1) + + chunks = chunk_spec_file( + filepath, + max_chunk_tokens=args.max_tokens, + overlap_lines=args.overlap, + ) + + if args.output_json: + output = [] + for chunk_text, meta in chunks: + output.append( + { + "meta": meta, + "text": chunk_text if args.include_text else None, + "estimated_tokens": estimate_tokens(chunk_text), + } + ) + json.dump(output, sys.stdout, indent=2) + print() + else: + print(f"File: {filepath.name}") + print(f"Total lines: {chunks[0][1]['total_lines'] if chunks else 0}") + print(f"Chunks: {len(chunks)}") + print() + for chunk_text, meta in chunks: + tokens = estimate_tokens(chunk_text) + print( + f" Chunk {meta['chunk_index']}/{meta['total_chunks']}: " + f"lines {meta['start_line']}-{meta['end_line']} " + f"({meta['end_line'] - meta['start_line'] + 1} lines, " + f"~{tokens:,} tokens)" + ) + + +def cmd_estimate(args: argparse.Namespace) -> None: + """Report token estimates for each prompt layer.""" + system_prompt = load_system_prompt() + examples = load_examples() + param_names = load_udb_param_names() + + system_tokens = estimate_tokens(system_prompt) + examples_text = format_examples_section(examples) + examples_tokens = estimate_tokens(examples_text) + names_text = format_param_names_section(param_names) + names_tokens = estimate_tokens(names_text) + + fixed_total = system_tokens + examples_tokens + names_tokens + SYSTEM_OVERHEAD_TOKENS + + print("Prompt Layer Token Estimates") + print("=" * 50) + print(f" System prompt: {system_tokens:>6,} tokens") + print(f" Few-shot examples: {examples_tokens:>6,} tokens") + print(f" UDB param names: {names_tokens:>6,} tokens") + print(f" System overhead: {SYSTEM_OVERHEAD_TOKENS:>6,} tokens") + print(f" Reserved for output: {RESERVED_OUTPUT_TOKENS:>6,} tokens") + print(f" {'─' * 36}") + print(f" Fixed overhead: {fixed_total:>6,} tokens") + print() + + print("Available for spec chunk per model:") + for model, limit in sorted(CONTEXT_LIMITS.items()): + available = limit - fixed_total - RESERVED_OUTPUT_TOKENS + print( + f" {model:<25s} {available:>8,} tokens (~{int(available * CHARS_PER_TOKEN):,} chars)" + ) + + +def main() -> None: + parser = argparse.ArgumentParser( + description="Prompt assembler for RISC-V parameter extraction", + formatter_class=argparse.RawDescriptionHelpFormatter, + ) + subparsers = parser.add_subparsers(dest="command", required=True) + + # --- assemble --- + p_asm = subparsers.add_parser("assemble", help="Build a complete prompt for a spec chunk") + p_asm.add_argument("file", help="Path to the .adoc spec file") + p_asm.add_argument("--start-line", type=int, default=None, help="Start line (1-based)") + p_asm.add_argument("--end-line", type=int, default=None, help="End line (1-based)") + p_asm.add_argument("--model", default="default", help="Target model for context limit check") + p_asm.add_argument("--no-examples", action="store_true", help="Omit few-shot examples") + p_asm.add_argument("--no-param-names", action="store_true", help="Omit UDB param name list") + p_asm.add_argument("--output-json", action="store_true", help="Output as JSON") + p_asm.set_defaults(func=cmd_assemble) + + # --- chunk --- + p_chunk = subparsers.add_parser("chunk", help="Split a spec file into chunks") + p_chunk.add_argument("file", help="Path to the .adoc spec file") + p_chunk.add_argument("--max-tokens", type=int, default=40_000, help="Max tokens per chunk") + p_chunk.add_argument("--overlap", type=int, default=20, help="Overlap lines between chunks") + p_chunk.add_argument("--output-json", action="store_true", help="Output as JSON") + p_chunk.add_argument("--include-text", action="store_true", help="Include chunk text in JSON") + p_chunk.set_defaults(func=cmd_chunk) + + # --- estimate --- + p_est = subparsers.add_parser("estimate", help="Report token estimates for prompt layers") + p_est.set_defaults(func=cmd_estimate) + + args = parser.parse_args() + args.func(args) + + +if __name__ == "__main__": + main() diff --git a/param_extraction/scripts/validate_prompt.py b/param_extraction/scripts/validate_prompt.py new file mode 100755 index 0000000000..b6cf6c7607 --- /dev/null +++ b/param_extraction/scripts/validate_prompt.py @@ -0,0 +1,391 @@ +#!/usr/bin/env python3 +""" +Validation script for Phase 2 deliverables. + +Checks: +1. taxonomy.md completeness and consistency +2. examples.json structure, coverage, and spec text accuracy +3. system_prompt.txt output schema and taxonomy coverage +4. run_prompt.py assembly correctness and token budgets +5. Chunk boundary integrity +""" + +from __future__ import annotations + +import json +import sys +from pathlib import Path + +SCRIPT_DIR = Path(__file__).resolve().parent +PROJECT_DIR = SCRIPT_DIR.parent +PROMPT_DIR = PROJECT_DIR / "prompts" / "v1" +DATA_DIR = PROJECT_DIR / "data" +SPEC_DIR = PROJECT_DIR.parent / "ext" / "riscv-isa-manual" / "src" + +EXPECTED_CLASSES = { + "NORM_DIRECT", + "NORM_CSR_WARL", + "NORM_CSR_RW", + "SW_RULE", + "NON_ISA", + "NON_NORM", + "DOC_RULE", + "UNKNOWN", +} + +EXPECTED_VALUE_TYPES = {"binary", "enum", "range", "set", "bitmask", "value"} + +REQUIRED_OUTPUT_FIELDS = { + "excerpt", + "line_number", + "parameter_name", + "existing_udb_name", + "class", + "value_type", + "confidence", + "reasoning", +} + +errors: list[str] = [] +warnings: list[str] = [] +checks_passed = 0 + + +def check(condition: bool, message: str, *, warn_only: bool = False) -> None: + global checks_passed + if condition: + checks_passed += 1 + elif warn_only: + warnings.append(f" WARNING: {message}") + else: + errors.append(f" FAIL: {message}") + + +def validate_taxonomy() -> None: + print("\n1. Validating taxonomy.md") + print("-" * 40) + + path = PROMPT_DIR.parent.parent / "taxonomy.md" + check(path.exists(), "taxonomy.md exists") + if not path.exists(): + return + + text = path.read_text(encoding="utf-8") + + for cls in EXPECTED_CLASSES: + check( + f"`{cls}`" in text or f"### `{cls}`" in text, + f"taxonomy.md defines class {cls}", + ) + + for vt in EXPECTED_VALUE_TYPES: + check(f"`{vt}`" in text, f"taxonomy.md defines value type {vt}") + + check("Decision Tree" in text, "taxonomy.md has a decision tree section") + check("Disambiguation" in text, "taxonomy.md has disambiguation guidance") + + lines = text.splitlines() + check(len(lines) >= 50, f"taxonomy.md has sufficient content ({len(lines)} lines)") + + +def validate_examples() -> None: + print("\n2. Validating examples.json") + print("-" * 40) + + path = PROMPT_DIR / "examples.json" + check(path.exists(), "examples.json exists") + if not path.exists(): + return + + with open(path, encoding="utf-8") as f: + data = json.load(f) + + pos = data.get("positive_examples", []) + neg = data.get("negative_examples", []) + + check(len(pos) >= 5, f"At least 5 positive examples (got {len(pos)})") + check(len(neg) >= 3, f"At least 3 negative examples (got {len(neg)})") + + classes_covered = set() + for ex in pos: + check("input_excerpt" in ex, "Positive example has input_excerpt") + check("input_file" in ex, "Positive example has input_file") + check("expected_output" in ex, "Positive example has expected_output") + + out = ex.get("expected_output", {}) + for field in REQUIRED_OUTPUT_FIELDS: + check( + field in out, + f"Positive example {out.get('parameter_name', '?')} has field '{field}'", + ) + + cls = out.get("class") + if cls: + classes_covered.add(cls) + check( + cls in EXPECTED_CLASSES, + f"Example class '{cls}' is a valid class", + ) + + vt = out.get("value_type") + if vt: + check( + vt in EXPECTED_VALUE_TYPES, + f"Example value_type '{vt}' is valid", + ) + + normative_classes = {"NORM_DIRECT", "NORM_CSR_WARL", "NORM_CSR_RW", "SW_RULE"} + for cls in normative_classes: + check( + cls in classes_covered, + f"Positive examples cover class {cls}", + ) + + for ex in neg: + check("input_excerpt" in ex, "Negative example has input_excerpt") + check("reason_for_rejection" in ex, "Negative example has reason_for_rejection") + check( + ex.get("expected_output") is None, + "Negative example has null expected_output", + ) + + udb_names = set() + names_path = DATA_DIR / "udb_param_names.txt" + if names_path.exists(): + udb_names = {line.strip() for line in names_path.read_text().splitlines() if line.strip()} + + for ex in pos: + out = ex.get("expected_output", {}) + udb_name = out.get("existing_udb_name") + if udb_name and udb_names: + check( + udb_name in udb_names, + f"Example UDB name '{udb_name}' exists in udb_param_names.txt", + ) + + for ex in pos: + spec_file = ex.get("input_file", "") + spec_path = SPEC_DIR / spec_file + if spec_path.exists(): + spec_text = spec_path.read_text(encoding="utf-8") + excerpt = ex["input_excerpt"] + first_sentence = excerpt.split("\n")[0][:80] + check( + first_sentence in spec_text or first_sentence.replace(">=", "{ge}") in spec_text, + f"Excerpt for {ex.get('expected_output', {}).get('parameter_name', '?')} found in {spec_file}", + warn_only=True, + ) + + +def validate_system_prompt() -> None: + print("\n3. Validating system_prompt.txt") + print("-" * 40) + + path = PROMPT_DIR / "system_prompt.txt" + check(path.exists(), "system_prompt.txt exists") + if not path.exists(): + return + + text = path.read_text(encoding="utf-8") + + for cls in EXPECTED_CLASSES: + check( + cls in text or f"**{cls}**" in text, + f"System prompt mentions class {cls}", + ) + + for vt in EXPECTED_VALUE_TYPES: + check( + f"**{vt}**" in text or f"- **{vt}**" in text, f"System prompt mentions value type {vt}" + ) + + check('"parameters"' in text, "System prompt defines output schema with 'parameters' key") + check('"excerpt"' in text, "System prompt output schema has 'excerpt' field") + check('"reasoning"' in text, "System prompt output schema has 'reasoning' field") + check('"line_number"' in text, "System prompt output schema has 'line_number' field") + + check("JSON" in text, "System prompt mentions JSON output format") + + check("NOTE" in text, "System prompt warns about NOTE blocks") + check('"may"' in text or "'may'" in text, "System prompt discusses 'may' disambiguation") + + from run_prompt import estimate_tokens + + tokens = estimate_tokens(text) + check(tokens <= 1200, f"System prompt is ≤1200 tokens ({tokens} estimated)", warn_only=True) + + +def validate_assembler() -> None: + print("\n4. Validating run_prompt.py assembly") + print("-" * 40) + + from run_prompt import ( + assemble_prompt, + load_examples, + load_system_prompt, + load_udb_param_names, + ) + + system = load_system_prompt() + check(len(system) > 100, "System prompt loads successfully") + + examples = load_examples() + check(len(examples.get("positive_examples", [])) >= 5, "Examples load successfully") + + names = load_udb_param_names() + check(len(names) >= 100, f"UDB param names load successfully ({len(names)} names)") + + test_file = SPEC_DIR / "machine.adoc" + if not test_file.exists(): + print(" SKIP: machine.adoc not available for assembly test") + return + + text = test_file.read_text(encoding="utf-8") + lines = text.splitlines(keepends=True) + chunk_text = "".join(lines[3334:3400]) + meta = { + "file": "machine.adoc", + "start_line": 3335, + "end_line": 3400, + "total_lines": len(lines), + "chunk_index": 1, + "total_chunks": 1, + } + + prompt = assemble_prompt(chunk_text, meta, model="gpt-4o") + check("system" in prompt, "Assembled prompt has 'system' key") + check("user" in prompt, "Assembled prompt has 'user' key") + check("estimated_tokens" in prompt, "Assembled prompt has 'estimated_tokens'") + + total = prompt["estimated_tokens"] + check(total < 128_000, f"Assembled prompt fits in gpt-4o context ({total:,} tokens)") + + check( + "NUM_PMP_ENTRIES" in prompt["user"], + "UDB param names appear in user message", + ) + check( + "Few-Shot Examples" in prompt["user"], + "Few-shot examples appear in user message", + ) + check( + "Specification Text" in prompt["user"], + "Spec chunk header appears in user message", + ) + + try: + assemble_prompt(chunk_text, meta, model="llama-3-70b") + errors.append(" FAIL: Should have raised ValueError for llama-3-70b context overflow") + except ValueError: + check(True, "Context overflow correctly raises ValueError for small models") + + prompt_no_extras = assemble_prompt( + chunk_text, + meta, + model="default", + include_examples=False, + include_param_names=False, + ) + check( + "Few-Shot Examples" not in prompt_no_extras["user"], + "Examples correctly omitted when disabled", + ) + check( + prompt_no_extras["estimated_tokens"] < prompt["estimated_tokens"], + "Token count is lower without examples/names", + ) + + +def validate_chunking() -> None: + print("\n5. Validating chunking logic") + print("-" * 40) + + from run_prompt import chunk_spec_file + + test_file = SPEC_DIR / "machine.adoc" + if not test_file.exists(): + print(" SKIP: machine.adoc not available for chunking test") + return + + chunks = chunk_spec_file(test_file, max_chunk_tokens=40_000) + check(len(chunks) >= 1, f"Chunking produces at least 1 chunk ({len(chunks)} chunks)") + + all_text = test_file.read_text(encoding="utf-8") + total_lines = len(all_text.splitlines()) + + check( + chunks[0][1]["start_line"] == 1, + "First chunk starts at line 1", + ) + check( + chunks[-1][1]["end_line"] == total_lines, + f"Last chunk ends at last line ({chunks[-1][1]['end_line']} == {total_lines})", + ) + + for _chunk_text, meta in chunks: + check( + meta["total_chunks"] == len(chunks), + f"Chunk {meta['chunk_index']} total_chunks is correct", + ) + + if len(chunks) > 1: + for i in range(1, len(chunks)): + prev_end = chunks[i - 1][1]["end_line"] + curr_start = chunks[i][1]["start_line"] + check( + curr_start <= prev_end, + f"Chunks {i} and {i + 1} overlap (prev_end={prev_end}, curr_start={curr_start})", + ) + + small_chunks = chunk_spec_file(test_file, max_chunk_tokens=5_000) + check( + len(small_chunks) > len(chunks), + f"Smaller max_tokens produces more chunks ({len(small_chunks)} > {len(chunks)})", + ) + + for _, meta in small_chunks: + from run_prompt import estimate_tokens + + chunk_text = _ + tokens = estimate_tokens(chunk_text) + check( + tokens < 8_000, + f"Chunk {meta['chunk_index']} with 5K limit is under 8K tokens ({tokens:,})", + warn_only=True, + ) + + +def main() -> None: + global checks_passed + + print("=" * 60) + print("Phase 2 Deliverable Validation") + print("=" * 60) + + validate_taxonomy() + validate_examples() + validate_system_prompt() + validate_assembler() + validate_chunking() + + print() + print("=" * 60) + print(f"Results: {checks_passed} passed, {len(errors)} failed, {len(warnings)} warnings") + print("=" * 60) + + if warnings: + print("\nWarnings:") + for w in warnings: + print(w) + + if errors: + print("\nErrors:") + for e in errors: + print(e) + sys.exit(1) + else: + print("\nAll checks passed!") + + +if __name__ == "__main__": + main() diff --git a/param_extraction/taxonomy.md b/param_extraction/taxonomy.md new file mode 100644 index 0000000000..96a5849291 --- /dev/null +++ b/param_extraction/taxonomy.md @@ -0,0 +1,199 @@ +# Architectural Parameter Classification Taxonomy + +This document defines the classification system used to categorize architectural +parameters extracted from the RISC-V privileged and unprivileged specifications. + +Every parameter gets exactly one **class** and one **value type**. + +--- + +## Parameter Classes + +### `NORM_DIRECT` — Normative, Directly Configurable + +An implementation-defined choice that the spec explicitly leaves to the +implementer. Not controlled by or derived from any CSR field. + +**How to identify**: The spec says an implementer "may", "can", or "optionally" +choose a value, or describes a quantity whose value is not fixed by the spec. +The choice is made at design time and does not change at runtime via CSR writes. + +**Typical spec wording**: +- "Implementations may implement zero, 16, or 64 PMP entries" +- "The number of bits in a single vector register, _VLEN_ ≥ ELEN" +- "MXLEN is a constant" + +**Examples**: `MXLEN`, `NUM_PMP_ENTRIES`, `PHYS_ADDR_WIDTH`, `VLEN`, `ELEN`, +`CACHE_BLOCK_SIZE`, `TRAP_ON_UNIMPLEMENTED_INSTRUCTION` + +**Disambiguation**: +- If the choice is controlled by a CSR field's legal values → `NORM_CSR_WARL` +- If the choice is about whether a CSR field is read-only vs read-write → `NORM_CSR_RW` +- If the behavior becomes determinate when software follows spec rules → `SW_RULE` + +--- + +### `NORM_CSR_WARL` — Normative, CSR WARL Legal Values + +The parameter defines the set of legal values that a WARL (Write Any, Read +Legal) CSR field will accept. When software writes an illegal value, the field +retains its previous value or takes an implementation-defined legal value. + +**How to identify**: The spec describes a CSR field as "WARL" and the legal +values are implementation-defined. The parameter IS the set of legal values. + +**Typical spec wording**: +- "The `mtvec` register is an MXLEN-bit WARL read/write register" +- "The MODE field is WARL" +- "A write to `hgatp` with an unsupported MODE value..." + +**Examples**: `MTVEC_MODES`, `SATP_MODE_BARE`, `MSTATUS_FS_LEGAL_VALUES`, +`GSTAGE_MODE_BARE`, `SV39X4_TRANSLATION` + +**Disambiguation**: +- If the field is described as WARL but the parameter controls whether the + field is read-only vs read-write (not which values are legal) → `NORM_CSR_RW` +- If the WARL behavior is described in a NOTE block → still `NORM_CSR_WARL` + (WARL field definitions are normative even when discussed in notes) + +--- + +### `NORM_CSR_RW` — Normative, CSR Read-Write Behavior + +The parameter controls whether a CSR or CSR field is read-only, read-write, +or has a specific fixed value. This is about the mutability of the field, not +the set of legal values. + +**How to identify**: The spec says a field "may be read-only zero", "can be +read-only", or that the field's type (RO/RW) depends on implementation choices. + +**Typical spec wording**: +- "The `mtvec` register ... can contain a read-only value" +- "Bits of `misa` that correspond to implemented extensions are writable..." +- "MBE, SBE, and UBE bits in `mstatus` are WARL fields" (where the parameter + controls whether they are read-only-0, read-only-1, or read-write) + +**Examples**: `MTVEC_ACCESS`, `MUTABLE_MISA_C`, `M_MODE_ENDIANNESS`, +`HSTATEEN_CONTEXT_TYPE`, `SCOUNTENABLE_EN` + +**Disambiguation**: +- If the parameter controls which values are legal in a writable field → `NORM_CSR_WARL` +- If the parameter controls whether a CSR/feature exists at all → `NORM_DIRECT` + (e.g., `TIME_CSR_IMPLEMENTED`, `MISA_CSR_IMPLEMENTED`) + +--- + +### `SW_RULE` — Software-Deterministic + +Behavior that appears implementation-defined but whose outcome is fully +determined if software follows the spec's prescribed rules (e.g., fencing, +cache operations, proper sequencing). + +**How to identify**: The spec describes hardware behavior that varies by +implementation, but also prescribes software rules that make the outcome +predictable. Often involves hardware state updates that software can control +through proper synchronization. + +**Typical spec wording**: +- "It is implementation-defined whether FS transitions to Dirty" + (but software can prevent this by managing FS correctly) +- "dirtiness might not be tracked at all" + (but software can use fencing to ensure correctness) + +**Examples**: `HW_MSTATUS_FS_DIRTY_UPDATE`, `HW_MSTATUS_VS_DIRTY_UPDATE` + +**Disambiguation**: +- If the behavior is truly a fixed design choice with no software workaround → `NORM_DIRECT` +- The key question: "Can software guarantee a specific outcome regardless of + the implementation choice?" If yes → `SW_RULE`. If no → `NORM_DIRECT`. + +--- + +### `NON_ISA` — Non-ISA / Platform + +A choice that is outside the ISA scope — platform-level, electrical, or +physical rather than architectural. These are not governed by the ISA +specification. + +**How to identify**: The choice involves physical characteristics, platform +integration, or debug infrastructure rather than instruction execution behavior. + +**Typical spec wording**: +- "The reset vector is platform-specified" +- "NMI vector address is implementation-specific" + +**Examples**: Reset vector address, NMI vector, physical memory attributes, +debug transport mechanism + +--- + +### `NON_NORM` — Non-Normative + +Text that appears in a NOTE, TIP, WARNING, or other informative block. These +blocks describe rationale, design intent, or implementation suggestions but +do not constitute requirements. + +**How to identify**: The text is enclosed in AsciiDoc `[NOTE]`/`====` blocks, +or is explicitly labeled as informative. + +**Critical rule**: Even if a NOTE block discusses implementation choices using +words like "may" or "optionally", the content is non-normative and should NOT +be extracted as a parameter. Only normative prose outside of such blocks +defines actual parameters. + +**Example of a false positive (do NOT extract)**: +> [NOTE] +> Some platforms may choose to disallow speculatively writing FS to close a +> potential side channel. + +This is a suggestion, not a requirement — no parameter. + +--- + +### `DOC_RULE` — Documentation Rule + +A requirement about how something should be documented, reported, or +described, rather than about architectural behavior. + +**How to identify**: The spec requires reporting or documenting a value, but +the value itself is not an architectural choice that affects execution. + +**Examples**: Requirements about what must appear in documentation, how +extensions should be described + +--- + +### `UNKNOWN` — Needs Further Analysis + +Cannot be confidently classified into any of the above categories. Use this +sparingly — it flags items for human review. + +--- + +## Value Types + +Value types are orthogonal to classes. Every parameter has exactly one. + +| Type | Definition | Example | +|---|---|---| +| `binary` | Exactly 2 choices (boolean, or 2-value enum) | `TRAP_ON_UNIMPLEMENTED_INSTRUCTION` (true/false) | +| `enum` | Finite set of 3+ discrete values | `LRSC_RESERVATION_STRATEGY` (4 choices) | +| `range` | Integer range with min/max bounds | `NUM_PMP_ENTRIES` (0-64) | +| `set` | Subset selection from a fixed universe | `MTVEC_MODES` (subset of {0, 1}) | +| `bitmask` | Fixed-length boolean array (one bit per feature) | `SCOUNTENABLE_EN` (32 booleans) | +| `value` | Single unconstrained value (no enumerated choices or bounds) | `VLEN` (any power of 2 ≥ ELEN) | + +--- + +## Decision Tree + +When classifying a parameter, follow this order: + +1. **Is the text in a NOTE/TIP/WARNING block?** → `NON_NORM` +2. **Is the choice about platform/physical/debug, not ISA?** → `NON_ISA` +3. **Is it about documenting/reporting, not behavior?** → `DOC_RULE` +4. **Does the text describe a WARL CSR field's legal values?** → `NORM_CSR_WARL` +5. **Does the text describe whether a CSR field is RO/RW/fixed?** → `NORM_CSR_RW` +6. **Does the behavior become deterministic with proper software?** → `SW_RULE` +7. **Is it a normative implementation choice?** → `NORM_DIRECT` +8. **None of the above?** → `UNKNOWN` diff --git a/tests/data/golden/Xqci@0.13.0.adoc b/tests/data/golden/Xqci@0.13.0.adoc index e6905a1dec..887239a25c 100644 --- a/tests/data/golden/Xqci@0.13.0.adoc +++ b/tests/data/golden/Xqci@0.13.0.adoc @@ -1,6 +1,6 @@ [[header]] :description: Qualcomm uC extensions (Xqci) -:revdate: 2026-03-22 +:revdate: 2026-03-26 :revnumber: 0.13.0 :revmark: This document is in the http://riscv.org/spec-state[Frozen state]. + \ + \